1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 1986-2017 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
29 #include "arch-utils.h"
34 #include "parser-defs.h"
37 #include "sim-regno.h"
38 #include "gdb/sim-ppc.h"
39 #include "reggroups.h"
40 #include "dwarf2-frame.h"
41 #include "target-descriptions.h"
42 #include "user-regs.h"
43 #include "record-full.h"
46 #include "coff/internal.h" /* for libcoff.h */
47 #include "libcoff.h" /* for xcoff_data */
48 #include "coff/xcoff.h"
53 #include "elf/ppc64.h"
55 #include "solib-svr4.h"
57 #include "ppc-ravenscar-thread.h"
61 #include "trad-frame.h"
62 #include "frame-unwind.h"
63 #include "frame-base.h"
69 #include "features/rs6000/powerpc-32.c"
70 #include "features/rs6000/powerpc-altivec32.c"
71 #include "features/rs6000/powerpc-vsx32.c"
72 #include "features/rs6000/powerpc-403.c"
73 #include "features/rs6000/powerpc-403gc.c"
74 #include "features/rs6000/powerpc-405.c"
75 #include "features/rs6000/powerpc-505.c"
76 #include "features/rs6000/powerpc-601.c"
77 #include "features/rs6000/powerpc-602.c"
78 #include "features/rs6000/powerpc-603.c"
79 #include "features/rs6000/powerpc-604.c"
80 #include "features/rs6000/powerpc-64.c"
81 #include "features/rs6000/powerpc-altivec64.c"
82 #include "features/rs6000/powerpc-vsx64.c"
83 #include "features/rs6000/powerpc-7400.c"
84 #include "features/rs6000/powerpc-750.c"
85 #include "features/rs6000/powerpc-860.c"
86 #include "features/rs6000/powerpc-e500.c"
87 #include "features/rs6000/rs6000.c"
89 /* Determine if regnum is an SPE pseudo-register. */
90 #define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \
91 && (regnum) >= (tdep)->ppc_ev0_regnum \
92 && (regnum) < (tdep)->ppc_ev0_regnum + 32)
94 /* Determine if regnum is a decimal float pseudo-register. */
95 #define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \
96 && (regnum) >= (tdep)->ppc_dl0_regnum \
97 && (regnum) < (tdep)->ppc_dl0_regnum + 16)
99 /* Determine if regnum is a POWER7 VSX register. */
100 #define IS_VSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_vsr0_regnum >= 0 \
101 && (regnum) >= (tdep)->ppc_vsr0_regnum \
102 && (regnum) < (tdep)->ppc_vsr0_regnum + ppc_num_vsrs)
104 /* Determine if regnum is a POWER7 Extended FP register. */
105 #define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \
106 && (regnum) >= (tdep)->ppc_efpr0_regnum \
107 && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_efprs)
109 /* Holds the current set of options to be passed to the disassembler. */
110 static char *powerpc_disassembler_options
;
112 /* The list of available "set powerpc ..." and "show powerpc ..."
114 static struct cmd_list_element
*setpowerpccmdlist
= NULL
;
115 static struct cmd_list_element
*showpowerpccmdlist
= NULL
;
117 static enum auto_boolean powerpc_soft_float_global
= AUTO_BOOLEAN_AUTO
;
119 /* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */
120 static const char *const powerpc_vector_strings
[] =
129 /* A variable that can be configured by the user. */
130 static enum powerpc_vector_abi powerpc_vector_abi_global
= POWERPC_VEC_AUTO
;
131 static const char *powerpc_vector_abi_string
= "auto";
133 /* To be used by skip_prologue. */
135 struct rs6000_framedata
137 int offset
; /* total size of frame --- the distance
138 by which we decrement sp to allocate
140 int saved_gpr
; /* smallest # of saved gpr */
141 unsigned int gpr_mask
; /* Each bit is an individual saved GPR. */
142 int saved_fpr
; /* smallest # of saved fpr */
143 int saved_vr
; /* smallest # of saved vr */
144 int saved_ev
; /* smallest # of saved ev */
145 int alloca_reg
; /* alloca register number (frame ptr) */
146 char frameless
; /* true if frameless functions. */
147 char nosavedpc
; /* true if pc not saved. */
148 char used_bl
; /* true if link register clobbered */
149 int gpr_offset
; /* offset of saved gprs from prev sp */
150 int fpr_offset
; /* offset of saved fprs from prev sp */
151 int vr_offset
; /* offset of saved vrs from prev sp */
152 int ev_offset
; /* offset of saved evs from prev sp */
153 int lr_offset
; /* offset of saved lr */
154 int lr_register
; /* register of saved lr, if trustworthy */
155 int cr_offset
; /* offset of saved cr */
156 int vrsave_offset
; /* offset of saved vrsave register */
160 /* Is REGNO a VSX register? Return 1 if so, 0 otherwise. */
162 vsx_register_p (struct gdbarch
*gdbarch
, int regno
)
164 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
165 if (tdep
->ppc_vsr0_regnum
< 0)
168 return (regno
>= tdep
->ppc_vsr0_upper_regnum
&& regno
169 <= tdep
->ppc_vsr0_upper_regnum
+ 31);
172 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
174 altivec_register_p (struct gdbarch
*gdbarch
, int regno
)
176 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
177 if (tdep
->ppc_vr0_regnum
< 0 || tdep
->ppc_vrsave_regnum
< 0)
180 return (regno
>= tdep
->ppc_vr0_regnum
&& regno
<= tdep
->ppc_vrsave_regnum
);
184 /* Return true if REGNO is an SPE register, false otherwise. */
186 spe_register_p (struct gdbarch
*gdbarch
, int regno
)
188 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
190 /* Is it a reference to EV0 -- EV31, and do we have those? */
191 if (IS_SPE_PSEUDOREG (tdep
, regno
))
194 /* Is it a reference to one of the raw upper GPR halves? */
195 if (tdep
->ppc_ev0_upper_regnum
>= 0
196 && tdep
->ppc_ev0_upper_regnum
<= regno
197 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
200 /* Is it a reference to the 64-bit accumulator, and do we have that? */
201 if (tdep
->ppc_acc_regnum
>= 0
202 && tdep
->ppc_acc_regnum
== regno
)
205 /* Is it a reference to the SPE floating-point status and control register,
206 and do we have that? */
207 if (tdep
->ppc_spefscr_regnum
>= 0
208 && tdep
->ppc_spefscr_regnum
== regno
)
215 /* Return non-zero if the architecture described by GDBARCH has
216 floating-point registers (f0 --- f31 and fpscr). */
218 ppc_floating_point_unit_p (struct gdbarch
*gdbarch
)
220 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
222 return (tdep
->ppc_fp0_regnum
>= 0
223 && tdep
->ppc_fpscr_regnum
>= 0);
226 /* Return non-zero if the architecture described by GDBARCH has
227 VSX registers (vsr0 --- vsr63). */
229 ppc_vsx_support_p (struct gdbarch
*gdbarch
)
231 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
233 return tdep
->ppc_vsr0_regnum
>= 0;
236 /* Return non-zero if the architecture described by GDBARCH has
237 Altivec registers (vr0 --- vr31, vrsave and vscr). */
239 ppc_altivec_support_p (struct gdbarch
*gdbarch
)
241 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
243 return (tdep
->ppc_vr0_regnum
>= 0
244 && tdep
->ppc_vrsave_regnum
>= 0);
247 /* Check that TABLE[GDB_REGNO] is not already initialized, and then
250 This is a helper function for init_sim_regno_table, constructing
251 the table mapping GDB register numbers to sim register numbers; we
252 initialize every element in that table to -1 before we start
255 set_sim_regno (int *table
, int gdb_regno
, int sim_regno
)
257 /* Make sure we don't try to assign any given GDB register a sim
258 register number more than once. */
259 gdb_assert (table
[gdb_regno
] == -1);
260 table
[gdb_regno
] = sim_regno
;
264 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
265 numbers to simulator register numbers, based on the values placed
266 in the ARCH->tdep->ppc_foo_regnum members. */
268 init_sim_regno_table (struct gdbarch
*arch
)
270 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
271 int total_regs
= gdbarch_num_regs (arch
);
272 int *sim_regno
= GDBARCH_OBSTACK_CALLOC (arch
, total_regs
, int);
274 static const char *const segment_regs
[] = {
275 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
276 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
279 /* Presume that all registers not explicitly mentioned below are
280 unavailable from the sim. */
281 for (i
= 0; i
< total_regs
; i
++)
284 /* General-purpose registers. */
285 for (i
= 0; i
< ppc_num_gprs
; i
++)
286 set_sim_regno (sim_regno
, tdep
->ppc_gp0_regnum
+ i
, sim_ppc_r0_regnum
+ i
);
288 /* Floating-point registers. */
289 if (tdep
->ppc_fp0_regnum
>= 0)
290 for (i
= 0; i
< ppc_num_fprs
; i
++)
291 set_sim_regno (sim_regno
,
292 tdep
->ppc_fp0_regnum
+ i
,
293 sim_ppc_f0_regnum
+ i
);
294 if (tdep
->ppc_fpscr_regnum
>= 0)
295 set_sim_regno (sim_regno
, tdep
->ppc_fpscr_regnum
, sim_ppc_fpscr_regnum
);
297 set_sim_regno (sim_regno
, gdbarch_pc_regnum (arch
), sim_ppc_pc_regnum
);
298 set_sim_regno (sim_regno
, tdep
->ppc_ps_regnum
, sim_ppc_ps_regnum
);
299 set_sim_regno (sim_regno
, tdep
->ppc_cr_regnum
, sim_ppc_cr_regnum
);
301 /* Segment registers. */
302 for (i
= 0; i
< ppc_num_srs
; i
++)
306 gdb_regno
= user_reg_map_name_to_regnum (arch
, segment_regs
[i
], -1);
308 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_sr0_regnum
+ i
);
311 /* Altivec registers. */
312 if (tdep
->ppc_vr0_regnum
>= 0)
314 for (i
= 0; i
< ppc_num_vrs
; i
++)
315 set_sim_regno (sim_regno
,
316 tdep
->ppc_vr0_regnum
+ i
,
317 sim_ppc_vr0_regnum
+ i
);
319 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
320 we can treat this more like the other cases. */
321 set_sim_regno (sim_regno
,
322 tdep
->ppc_vr0_regnum
+ ppc_num_vrs
,
323 sim_ppc_vscr_regnum
);
325 /* vsave is a special-purpose register, so the code below handles it. */
327 /* SPE APU (E500) registers. */
328 if (tdep
->ppc_ev0_upper_regnum
>= 0)
329 for (i
= 0; i
< ppc_num_gprs
; i
++)
330 set_sim_regno (sim_regno
,
331 tdep
->ppc_ev0_upper_regnum
+ i
,
332 sim_ppc_rh0_regnum
+ i
);
333 if (tdep
->ppc_acc_regnum
>= 0)
334 set_sim_regno (sim_regno
, tdep
->ppc_acc_regnum
, sim_ppc_acc_regnum
);
335 /* spefscr is a special-purpose register, so the code below handles it. */
338 /* Now handle all special-purpose registers. Verify that they
339 haven't mistakenly been assigned numbers by any of the above
341 for (i
= 0; i
< sim_ppc_num_sprs
; i
++)
343 const char *spr_name
= sim_spr_register_name (i
);
346 if (spr_name
!= NULL
)
347 gdb_regno
= user_reg_map_name_to_regnum (arch
, spr_name
, -1);
350 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_spr0_regnum
+ i
);
354 /* Drop the initialized array into place. */
355 tdep
->sim_regno
= sim_regno
;
359 /* Given a GDB register number REG, return the corresponding SIM
362 rs6000_register_sim_regno (struct gdbarch
*gdbarch
, int reg
)
364 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
367 if (tdep
->sim_regno
== NULL
)
368 init_sim_regno_table (gdbarch
);
371 && reg
<= gdbarch_num_regs (gdbarch
)
372 + gdbarch_num_pseudo_regs (gdbarch
));
373 sim_regno
= tdep
->sim_regno
[reg
];
378 return LEGACY_SIM_REGNO_IGNORE
;
383 /* Register set support functions. */
385 /* REGS + OFFSET contains register REGNUM in a field REGSIZE wide.
386 Write the register to REGCACHE. */
389 ppc_supply_reg (struct regcache
*regcache
, int regnum
,
390 const gdb_byte
*regs
, size_t offset
, int regsize
)
392 if (regnum
!= -1 && offset
!= -1)
396 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
397 int gdb_regsize
= register_size (gdbarch
, regnum
);
398 if (gdb_regsize
< regsize
399 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
400 offset
+= regsize
- gdb_regsize
;
402 regcache_raw_supply (regcache
, regnum
, regs
+ offset
);
406 /* Read register REGNUM from REGCACHE and store to REGS + OFFSET
407 in a field REGSIZE wide. Zero pad as necessary. */
410 ppc_collect_reg (const struct regcache
*regcache
, int regnum
,
411 gdb_byte
*regs
, size_t offset
, int regsize
)
413 if (regnum
!= -1 && offset
!= -1)
417 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
418 int gdb_regsize
= register_size (gdbarch
, regnum
);
419 if (gdb_regsize
< regsize
)
421 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
423 memset (regs
+ offset
, 0, regsize
- gdb_regsize
);
424 offset
+= regsize
- gdb_regsize
;
427 memset (regs
+ offset
+ regsize
- gdb_regsize
, 0,
428 regsize
- gdb_regsize
);
431 regcache_raw_collect (regcache
, regnum
, regs
+ offset
);
436 ppc_greg_offset (struct gdbarch
*gdbarch
,
437 struct gdbarch_tdep
*tdep
,
438 const struct ppc_reg_offsets
*offsets
,
442 *regsize
= offsets
->gpr_size
;
443 if (regnum
>= tdep
->ppc_gp0_regnum
444 && regnum
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
)
445 return (offsets
->r0_offset
446 + (regnum
- tdep
->ppc_gp0_regnum
) * offsets
->gpr_size
);
448 if (regnum
== gdbarch_pc_regnum (gdbarch
))
449 return offsets
->pc_offset
;
451 if (regnum
== tdep
->ppc_ps_regnum
)
452 return offsets
->ps_offset
;
454 if (regnum
== tdep
->ppc_lr_regnum
)
455 return offsets
->lr_offset
;
457 if (regnum
== tdep
->ppc_ctr_regnum
)
458 return offsets
->ctr_offset
;
460 *regsize
= offsets
->xr_size
;
461 if (regnum
== tdep
->ppc_cr_regnum
)
462 return offsets
->cr_offset
;
464 if (regnum
== tdep
->ppc_xer_regnum
)
465 return offsets
->xer_offset
;
467 if (regnum
== tdep
->ppc_mq_regnum
)
468 return offsets
->mq_offset
;
474 ppc_fpreg_offset (struct gdbarch_tdep
*tdep
,
475 const struct ppc_reg_offsets
*offsets
,
478 if (regnum
>= tdep
->ppc_fp0_regnum
479 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
)
480 return offsets
->f0_offset
+ (regnum
- tdep
->ppc_fp0_regnum
) * 8;
482 if (regnum
== tdep
->ppc_fpscr_regnum
)
483 return offsets
->fpscr_offset
;
489 ppc_vrreg_offset (struct gdbarch_tdep
*tdep
,
490 const struct ppc_reg_offsets
*offsets
,
493 if (regnum
>= tdep
->ppc_vr0_regnum
494 && regnum
< tdep
->ppc_vr0_regnum
+ ppc_num_vrs
)
495 return offsets
->vr0_offset
+ (regnum
- tdep
->ppc_vr0_regnum
) * 16;
497 if (regnum
== tdep
->ppc_vrsave_regnum
- 1)
498 return offsets
->vscr_offset
;
500 if (regnum
== tdep
->ppc_vrsave_regnum
)
501 return offsets
->vrsave_offset
;
506 /* Supply register REGNUM in the general-purpose register set REGSET
507 from the buffer specified by GREGS and LEN to register cache
508 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
511 ppc_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
512 int regnum
, const void *gregs
, size_t len
)
514 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
515 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
516 const struct ppc_reg_offsets
*offsets
517 = (const struct ppc_reg_offsets
*) regset
->regmap
;
524 int gpr_size
= offsets
->gpr_size
;
526 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
527 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
528 i
++, offset
+= gpr_size
)
529 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) gregs
, offset
,
532 ppc_supply_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
533 (const gdb_byte
*) gregs
, offsets
->pc_offset
, gpr_size
);
534 ppc_supply_reg (regcache
, tdep
->ppc_ps_regnum
,
535 (const gdb_byte
*) gregs
, offsets
->ps_offset
, gpr_size
);
536 ppc_supply_reg (regcache
, tdep
->ppc_lr_regnum
,
537 (const gdb_byte
*) gregs
, offsets
->lr_offset
, gpr_size
);
538 ppc_supply_reg (regcache
, tdep
->ppc_ctr_regnum
,
539 (const gdb_byte
*) gregs
, offsets
->ctr_offset
, gpr_size
);
540 ppc_supply_reg (regcache
, tdep
->ppc_cr_regnum
,
541 (const gdb_byte
*) gregs
, offsets
->cr_offset
,
543 ppc_supply_reg (regcache
, tdep
->ppc_xer_regnum
,
544 (const gdb_byte
*) gregs
, offsets
->xer_offset
,
546 ppc_supply_reg (regcache
, tdep
->ppc_mq_regnum
,
547 (const gdb_byte
*) gregs
, offsets
->mq_offset
,
552 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
553 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) gregs
, offset
, regsize
);
556 /* Supply register REGNUM in the floating-point register set REGSET
557 from the buffer specified by FPREGS and LEN to register cache
558 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
561 ppc_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
562 int regnum
, const void *fpregs
, size_t len
)
564 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
565 struct gdbarch_tdep
*tdep
;
566 const struct ppc_reg_offsets
*offsets
;
569 if (!ppc_floating_point_unit_p (gdbarch
))
572 tdep
= gdbarch_tdep (gdbarch
);
573 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
578 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
579 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
581 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) fpregs
, offset
, 8);
583 ppc_supply_reg (regcache
, tdep
->ppc_fpscr_regnum
,
584 (const gdb_byte
*) fpregs
, offsets
->fpscr_offset
,
585 offsets
->fpscr_size
);
589 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
590 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) fpregs
, offset
,
591 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
594 /* Supply register REGNUM in the VSX register set REGSET
595 from the buffer specified by VSXREGS and LEN to register cache
596 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
599 ppc_supply_vsxregset (const struct regset
*regset
, struct regcache
*regcache
,
600 int regnum
, const void *vsxregs
, size_t len
)
602 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
603 struct gdbarch_tdep
*tdep
;
605 if (!ppc_vsx_support_p (gdbarch
))
608 tdep
= gdbarch_tdep (gdbarch
);
614 for (i
= tdep
->ppc_vsr0_upper_regnum
;
615 i
< tdep
->ppc_vsr0_upper_regnum
+ 32;
617 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) vsxregs
, 0, 8);
622 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) vsxregs
, 0, 8);
625 /* Supply register REGNUM in the Altivec register set REGSET
626 from the buffer specified by VRREGS and LEN to register cache
627 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
630 ppc_supply_vrregset (const struct regset
*regset
, struct regcache
*regcache
,
631 int regnum
, const void *vrregs
, size_t len
)
633 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
634 struct gdbarch_tdep
*tdep
;
635 const struct ppc_reg_offsets
*offsets
;
638 if (!ppc_altivec_support_p (gdbarch
))
641 tdep
= gdbarch_tdep (gdbarch
);
642 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
647 for (i
= tdep
->ppc_vr0_regnum
, offset
= offsets
->vr0_offset
;
648 i
< tdep
->ppc_vr0_regnum
+ ppc_num_vrs
;
650 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) vrregs
, offset
, 16);
652 ppc_supply_reg (regcache
, (tdep
->ppc_vrsave_regnum
- 1),
653 (const gdb_byte
*) vrregs
, offsets
->vscr_offset
, 4);
655 ppc_supply_reg (regcache
, tdep
->ppc_vrsave_regnum
,
656 (const gdb_byte
*) vrregs
, offsets
->vrsave_offset
, 4);
660 offset
= ppc_vrreg_offset (tdep
, offsets
, regnum
);
661 if (regnum
!= tdep
->ppc_vrsave_regnum
662 && regnum
!= tdep
->ppc_vrsave_regnum
- 1)
663 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) vrregs
, offset
, 16);
665 ppc_supply_reg (regcache
, regnum
,
666 (const gdb_byte
*) vrregs
, offset
, 4);
669 /* Collect register REGNUM in the general-purpose register set
670 REGSET from register cache REGCACHE into the buffer specified by
671 GREGS and LEN. If REGNUM is -1, do this for all registers in
675 ppc_collect_gregset (const struct regset
*regset
,
676 const struct regcache
*regcache
,
677 int regnum
, void *gregs
, size_t len
)
679 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
680 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
681 const struct ppc_reg_offsets
*offsets
682 = (const struct ppc_reg_offsets
*) regset
->regmap
;
689 int gpr_size
= offsets
->gpr_size
;
691 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
692 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
693 i
++, offset
+= gpr_size
)
694 ppc_collect_reg (regcache
, i
, (gdb_byte
*) gregs
, offset
, gpr_size
);
696 ppc_collect_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
697 (gdb_byte
*) gregs
, offsets
->pc_offset
, gpr_size
);
698 ppc_collect_reg (regcache
, tdep
->ppc_ps_regnum
,
699 (gdb_byte
*) gregs
, offsets
->ps_offset
, gpr_size
);
700 ppc_collect_reg (regcache
, tdep
->ppc_lr_regnum
,
701 (gdb_byte
*) gregs
, offsets
->lr_offset
, gpr_size
);
702 ppc_collect_reg (regcache
, tdep
->ppc_ctr_regnum
,
703 (gdb_byte
*) gregs
, offsets
->ctr_offset
, gpr_size
);
704 ppc_collect_reg (regcache
, tdep
->ppc_cr_regnum
,
705 (gdb_byte
*) gregs
, offsets
->cr_offset
,
707 ppc_collect_reg (regcache
, tdep
->ppc_xer_regnum
,
708 (gdb_byte
*) gregs
, offsets
->xer_offset
,
710 ppc_collect_reg (regcache
, tdep
->ppc_mq_regnum
,
711 (gdb_byte
*) gregs
, offsets
->mq_offset
,
716 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
717 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) gregs
, offset
, regsize
);
720 /* Collect register REGNUM in the floating-point register set
721 REGSET from register cache REGCACHE into the buffer specified by
722 FPREGS and LEN. If REGNUM is -1, do this for all registers in
726 ppc_collect_fpregset (const struct regset
*regset
,
727 const struct regcache
*regcache
,
728 int regnum
, void *fpregs
, size_t len
)
730 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
731 struct gdbarch_tdep
*tdep
;
732 const struct ppc_reg_offsets
*offsets
;
735 if (!ppc_floating_point_unit_p (gdbarch
))
738 tdep
= gdbarch_tdep (gdbarch
);
739 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
744 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
745 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
747 ppc_collect_reg (regcache
, i
, (gdb_byte
*) fpregs
, offset
, 8);
749 ppc_collect_reg (regcache
, tdep
->ppc_fpscr_regnum
,
750 (gdb_byte
*) fpregs
, offsets
->fpscr_offset
,
751 offsets
->fpscr_size
);
755 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
756 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) fpregs
, offset
,
757 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
760 /* Collect register REGNUM in the VSX register set
761 REGSET from register cache REGCACHE into the buffer specified by
762 VSXREGS and LEN. If REGNUM is -1, do this for all registers in
766 ppc_collect_vsxregset (const struct regset
*regset
,
767 const struct regcache
*regcache
,
768 int regnum
, void *vsxregs
, size_t len
)
770 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
771 struct gdbarch_tdep
*tdep
;
773 if (!ppc_vsx_support_p (gdbarch
))
776 tdep
= gdbarch_tdep (gdbarch
);
782 for (i
= tdep
->ppc_vsr0_upper_regnum
;
783 i
< tdep
->ppc_vsr0_upper_regnum
+ 32;
785 ppc_collect_reg (regcache
, i
, (gdb_byte
*) vsxregs
, 0, 8);
790 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) vsxregs
, 0, 8);
794 /* Collect register REGNUM in the Altivec register set
795 REGSET from register cache REGCACHE into the buffer specified by
796 VRREGS and LEN. If REGNUM is -1, do this for all registers in
800 ppc_collect_vrregset (const struct regset
*regset
,
801 const struct regcache
*regcache
,
802 int regnum
, void *vrregs
, size_t len
)
804 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
805 struct gdbarch_tdep
*tdep
;
806 const struct ppc_reg_offsets
*offsets
;
809 if (!ppc_altivec_support_p (gdbarch
))
812 tdep
= gdbarch_tdep (gdbarch
);
813 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
818 for (i
= tdep
->ppc_vr0_regnum
, offset
= offsets
->vr0_offset
;
819 i
< tdep
->ppc_vr0_regnum
+ ppc_num_vrs
;
821 ppc_collect_reg (regcache
, i
, (gdb_byte
*) vrregs
, offset
, 16);
823 ppc_collect_reg (regcache
, (tdep
->ppc_vrsave_regnum
- 1),
824 (gdb_byte
*) vrregs
, offsets
->vscr_offset
, 4);
826 ppc_collect_reg (regcache
, tdep
->ppc_vrsave_regnum
,
827 (gdb_byte
*) vrregs
, offsets
->vrsave_offset
, 4);
831 offset
= ppc_vrreg_offset (tdep
, offsets
, regnum
);
832 if (regnum
!= tdep
->ppc_vrsave_regnum
833 && regnum
!= tdep
->ppc_vrsave_regnum
- 1)
834 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) vrregs
, offset
, 16);
836 ppc_collect_reg (regcache
, regnum
,
837 (gdb_byte
*) vrregs
, offset
, 4);
842 insn_changes_sp_or_jumps (unsigned long insn
)
844 int opcode
= (insn
>> 26) & 0x03f;
845 int sd
= (insn
>> 21) & 0x01f;
846 int a
= (insn
>> 16) & 0x01f;
847 int subcode
= (insn
>> 1) & 0x3ff;
849 /* Changes the stack pointer. */
851 /* NOTE: There are many ways to change the value of a given register.
852 The ways below are those used when the register is R1, the SP,
853 in a funtion's epilogue. */
855 if (opcode
== 31 && subcode
== 444 && a
== 1)
856 return 1; /* mr R1,Rn */
857 if (opcode
== 14 && sd
== 1)
858 return 1; /* addi R1,Rn,simm */
859 if (opcode
== 58 && sd
== 1)
860 return 1; /* ld R1,ds(Rn) */
862 /* Transfers control. */
868 if (opcode
== 19 && subcode
== 16)
870 if (opcode
== 19 && subcode
== 528)
871 return 1; /* bcctr */
876 /* Return true if we are in the function's epilogue, i.e. after the
877 instruction that destroyed the function's stack frame.
879 1) scan forward from the point of execution:
880 a) If you find an instruction that modifies the stack pointer
881 or transfers control (except a return), execution is not in
883 b) Stop scanning if you find a return instruction or reach the
884 end of the function or reach the hard limit for the size of
886 2) scan backward from the point of execution:
887 a) If you find an instruction that modifies the stack pointer,
888 execution *is* in an epilogue, return.
889 b) Stop scanning if you reach an instruction that transfers
890 control or the beginning of the function or reach the hard
891 limit for the size of an epilogue. */
894 rs6000_in_function_epilogue_frame_p (struct frame_info
*curfrm
,
895 struct gdbarch
*gdbarch
, CORE_ADDR pc
)
897 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
898 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
899 bfd_byte insn_buf
[PPC_INSN_SIZE
];
900 CORE_ADDR scan_pc
, func_start
, func_end
, epilogue_start
, epilogue_end
;
903 /* Find the search limits based on function boundaries and hard limit. */
905 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
908 epilogue_start
= pc
- PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
909 if (epilogue_start
< func_start
) epilogue_start
= func_start
;
911 epilogue_end
= pc
+ PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
912 if (epilogue_end
> func_end
) epilogue_end
= func_end
;
914 /* Scan forward until next 'blr'. */
916 for (scan_pc
= pc
; scan_pc
< epilogue_end
; scan_pc
+= PPC_INSN_SIZE
)
918 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
920 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
921 if (insn
== 0x4e800020)
923 /* Assume a bctr is a tail call unless it points strictly within
925 if (insn
== 0x4e800420)
927 CORE_ADDR ctr
= get_frame_register_unsigned (curfrm
,
928 tdep
->ppc_ctr_regnum
);
929 if (ctr
> func_start
&& ctr
< func_end
)
934 if (insn_changes_sp_or_jumps (insn
))
938 /* Scan backward until adjustment to stack pointer (R1). */
940 for (scan_pc
= pc
- PPC_INSN_SIZE
;
941 scan_pc
>= epilogue_start
;
942 scan_pc
-= PPC_INSN_SIZE
)
944 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
946 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
947 if (insn_changes_sp_or_jumps (insn
))
954 /* Implement the stack_frame_destroyed_p gdbarch method. */
957 rs6000_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
959 return rs6000_in_function_epilogue_frame_p (get_current_frame (),
963 /* Get the ith function argument for the current function. */
965 rs6000_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
968 return get_frame_register_unsigned (frame
, 3 + argi
);
971 /* Sequence of bytes for breakpoint instruction. */
973 constexpr gdb_byte big_breakpoint
[] = { 0x7d, 0x82, 0x10, 0x08 };
974 constexpr gdb_byte little_breakpoint
[] = { 0x08, 0x10, 0x82, 0x7d };
976 typedef BP_MANIPULATION_ENDIAN (little_breakpoint
, big_breakpoint
)
979 /* Instruction masks for displaced stepping. */
980 #define BRANCH_MASK 0xfc000000
981 #define BP_MASK 0xFC0007FE
982 #define B_INSN 0x48000000
983 #define BC_INSN 0x40000000
984 #define BXL_INSN 0x4c000000
985 #define BP_INSN 0x7C000008
987 /* Instruction masks used during single-stepping of atomic
989 #define LOAD_AND_RESERVE_MASK 0xfc0007fe
990 #define LWARX_INSTRUCTION 0x7c000028
991 #define LDARX_INSTRUCTION 0x7c0000A8
992 #define LBARX_INSTRUCTION 0x7c000068
993 #define LHARX_INSTRUCTION 0x7c0000e8
994 #define LQARX_INSTRUCTION 0x7c000228
995 #define STORE_CONDITIONAL_MASK 0xfc0007ff
996 #define STWCX_INSTRUCTION 0x7c00012d
997 #define STDCX_INSTRUCTION 0x7c0001ad
998 #define STBCX_INSTRUCTION 0x7c00056d
999 #define STHCX_INSTRUCTION 0x7c0005ad
1000 #define STQCX_INSTRUCTION 0x7c00016d
1002 /* Check if insn is one of the Load And Reserve instructions used for atomic
1004 #define IS_LOAD_AND_RESERVE_INSN(insn) ((insn & LOAD_AND_RESERVE_MASK) == LWARX_INSTRUCTION \
1005 || (insn & LOAD_AND_RESERVE_MASK) == LDARX_INSTRUCTION \
1006 || (insn & LOAD_AND_RESERVE_MASK) == LBARX_INSTRUCTION \
1007 || (insn & LOAD_AND_RESERVE_MASK) == LHARX_INSTRUCTION \
1008 || (insn & LOAD_AND_RESERVE_MASK) == LQARX_INSTRUCTION)
1009 /* Check if insn is one of the Store Conditional instructions used for atomic
1011 #define IS_STORE_CONDITIONAL_INSN(insn) ((insn & STORE_CONDITIONAL_MASK) == STWCX_INSTRUCTION \
1012 || (insn & STORE_CONDITIONAL_MASK) == STDCX_INSTRUCTION \
1013 || (insn & STORE_CONDITIONAL_MASK) == STBCX_INSTRUCTION \
1014 || (insn & STORE_CONDITIONAL_MASK) == STHCX_INSTRUCTION \
1015 || (insn & STORE_CONDITIONAL_MASK) == STQCX_INSTRUCTION)
1017 /* We can't displaced step atomic sequences. Otherwise this is just
1018 like simple_displaced_step_copy_insn. */
1020 static struct displaced_step_closure
*
1021 ppc_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
1022 CORE_ADDR from
, CORE_ADDR to
,
1023 struct regcache
*regs
)
1025 size_t len
= gdbarch_max_insn_length (gdbarch
);
1026 gdb_byte
*buf
= (gdb_byte
*) xmalloc (len
);
1027 struct cleanup
*old_chain
= make_cleanup (xfree
, buf
);
1028 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1031 read_memory (from
, buf
, len
);
1033 insn
= extract_signed_integer (buf
, PPC_INSN_SIZE
, byte_order
);
1035 /* Assume all atomic sequences start with a Load and Reserve instruction. */
1036 if (IS_LOAD_AND_RESERVE_INSN (insn
))
1038 if (debug_displaced
)
1040 fprintf_unfiltered (gdb_stdlog
,
1041 "displaced: can't displaced step "
1042 "atomic sequence at %s\n",
1043 paddress (gdbarch
, from
));
1045 do_cleanups (old_chain
);
1049 write_memory (to
, buf
, len
);
1051 if (debug_displaced
)
1053 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
1054 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
1055 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
1058 discard_cleanups (old_chain
);
1059 return (struct displaced_step_closure
*) buf
;
1062 /* Fix up the state of registers and memory after having single-stepped
1063 a displaced instruction. */
1065 ppc_displaced_step_fixup (struct gdbarch
*gdbarch
,
1066 struct displaced_step_closure
*closure
,
1067 CORE_ADDR from
, CORE_ADDR to
,
1068 struct regcache
*regs
)
1070 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1071 /* Our closure is a copy of the instruction. */
1072 ULONGEST insn
= extract_unsigned_integer ((gdb_byte
*) closure
,
1073 PPC_INSN_SIZE
, byte_order
);
1074 ULONGEST opcode
= 0;
1075 /* Offset for non PC-relative instructions. */
1076 LONGEST offset
= PPC_INSN_SIZE
;
1078 opcode
= insn
& BRANCH_MASK
;
1080 if (debug_displaced
)
1081 fprintf_unfiltered (gdb_stdlog
,
1082 "displaced: (ppc) fixup (%s, %s)\n",
1083 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
1086 /* Handle PC-relative branch instructions. */
1087 if (opcode
== B_INSN
|| opcode
== BC_INSN
|| opcode
== BXL_INSN
)
1089 ULONGEST current_pc
;
1091 /* Read the current PC value after the instruction has been executed
1092 in a displaced location. Calculate the offset to be applied to the
1093 original PC value before the displaced stepping. */
1094 regcache_cooked_read_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1096 offset
= current_pc
- to
;
1098 if (opcode
!= BXL_INSN
)
1100 /* Check for AA bit indicating whether this is an absolute
1101 addressing or PC-relative (1: absolute, 0: relative). */
1104 /* PC-relative addressing is being used in the branch. */
1105 if (debug_displaced
)
1108 "displaced: (ppc) branch instruction: %s\n"
1109 "displaced: (ppc) adjusted PC from %s to %s\n",
1110 paddress (gdbarch
, insn
), paddress (gdbarch
, current_pc
),
1111 paddress (gdbarch
, from
+ offset
));
1113 regcache_cooked_write_unsigned (regs
,
1114 gdbarch_pc_regnum (gdbarch
),
1120 /* If we're here, it means we have a branch to LR or CTR. If the
1121 branch was taken, the offset is probably greater than 4 (the next
1122 instruction), so it's safe to assume that an offset of 4 means we
1123 did not take the branch. */
1124 if (offset
== PPC_INSN_SIZE
)
1125 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1126 from
+ PPC_INSN_SIZE
);
1129 /* Check for LK bit indicating whether we should set the link
1130 register to point to the next instruction
1131 (1: Set, 0: Don't set). */
1134 /* Link register needs to be set to the next instruction's PC. */
1135 regcache_cooked_write_unsigned (regs
,
1136 gdbarch_tdep (gdbarch
)->ppc_lr_regnum
,
1137 from
+ PPC_INSN_SIZE
);
1138 if (debug_displaced
)
1139 fprintf_unfiltered (gdb_stdlog
,
1140 "displaced: (ppc) adjusted LR to %s\n",
1141 paddress (gdbarch
, from
+ PPC_INSN_SIZE
));
1145 /* Check for breakpoints in the inferior. If we've found one, place the PC
1146 right at the breakpoint instruction. */
1147 else if ((insn
& BP_MASK
) == BP_INSN
)
1148 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
), from
);
1150 /* Handle any other instructions that do not fit in the categories above. */
1151 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1155 /* Always use hardware single-stepping to execute the
1156 displaced instruction. */
1158 ppc_displaced_step_hw_singlestep (struct gdbarch
*gdbarch
,
1159 struct displaced_step_closure
*closure
)
1164 /* Checks for an atomic sequence of instructions beginning with a
1165 Load And Reserve instruction and ending with a Store Conditional
1166 instruction. If such a sequence is found, attempt to step through it.
1167 A breakpoint is placed at the end of the sequence. */
1169 ppc_deal_with_atomic_sequence (struct regcache
*regcache
)
1171 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1172 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1173 CORE_ADDR pc
= regcache_read_pc (regcache
);
1174 CORE_ADDR breaks
[2] = {-1, -1};
1176 CORE_ADDR closing_insn
; /* Instruction that closes the atomic sequence. */
1177 int insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1180 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
1181 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
1182 int bc_insn_count
= 0; /* Conditional branch instruction count. */
1183 VEC (CORE_ADDR
) *next_pcs
= NULL
;
1185 /* Assume all atomic sequences start with a Load And Reserve instruction. */
1186 if (!IS_LOAD_AND_RESERVE_INSN (insn
))
1189 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
1191 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
1193 loc
+= PPC_INSN_SIZE
;
1194 insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1196 /* Assume that there is at most one conditional branch in the atomic
1197 sequence. If a conditional branch is found, put a breakpoint in
1198 its destination address. */
1199 if ((insn
& BRANCH_MASK
) == BC_INSN
)
1201 int immediate
= ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
1202 int absolute
= insn
& 2;
1204 if (bc_insn_count
>= 1)
1205 return 0; /* More than one conditional branch found, fallback
1206 to the standard single-step code. */
1209 breaks
[1] = immediate
;
1211 breaks
[1] = loc
+ immediate
;
1217 if (IS_STORE_CONDITIONAL_INSN (insn
))
1221 /* Assume that the atomic sequence ends with a Store Conditional
1223 if (!IS_STORE_CONDITIONAL_INSN (insn
))
1227 loc
+= PPC_INSN_SIZE
;
1228 insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1230 /* Insert a breakpoint right after the end of the atomic sequence. */
1233 /* Check for duplicated breakpoints. Check also for a breakpoint
1234 placed (branch instruction's destination) anywhere in sequence. */
1236 && (breaks
[1] == breaks
[0]
1237 || (breaks
[1] >= pc
&& breaks
[1] <= closing_insn
)))
1238 last_breakpoint
= 0;
1240 for (index
= 0; index
<= last_breakpoint
; index
++)
1241 VEC_safe_push (CORE_ADDR
, next_pcs
, breaks
[index
]);
1247 #define SIGNED_SHORT(x) \
1248 ((sizeof (short) == 2) \
1249 ? ((int)(short)(x)) \
1250 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
1252 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
1254 /* Limit the number of skipped non-prologue instructions, as the examining
1255 of the prologue is expensive. */
1256 static int max_skip_non_prologue_insns
= 10;
1258 /* Return nonzero if the given instruction OP can be part of the prologue
1259 of a function and saves a parameter on the stack. FRAMEP should be
1260 set if one of the previous instructions in the function has set the
1264 store_param_on_stack_p (unsigned long op
, int framep
, int *r0_contains_arg
)
1266 /* Move parameters from argument registers to temporary register. */
1267 if ((op
& 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
1269 /* Rx must be scratch register r0. */
1270 const int rx_regno
= (op
>> 16) & 31;
1271 /* Ry: Only r3 - r10 are used for parameter passing. */
1272 const int ry_regno
= GET_SRC_REG (op
);
1274 if (rx_regno
== 0 && ry_regno
>= 3 && ry_regno
<= 10)
1276 *r0_contains_arg
= 1;
1283 /* Save a General Purpose Register on stack. */
1285 if ((op
& 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
1286 (op
& 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
1288 /* Rx: Only r3 - r10 are used for parameter passing. */
1289 const int rx_regno
= GET_SRC_REG (op
);
1291 return (rx_regno
>= 3 && rx_regno
<= 10);
1294 /* Save a General Purpose Register on stack via the Frame Pointer. */
1297 ((op
& 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
1298 (op
& 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
1299 (op
& 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
1301 /* Rx: Usually, only r3 - r10 are used for parameter passing.
1302 However, the compiler sometimes uses r0 to hold an argument. */
1303 const int rx_regno
= GET_SRC_REG (op
);
1305 return ((rx_regno
>= 3 && rx_regno
<= 10)
1306 || (rx_regno
== 0 && *r0_contains_arg
));
1309 if ((op
& 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
1311 /* Only f2 - f8 are used for parameter passing. */
1312 const int src_regno
= GET_SRC_REG (op
);
1314 return (src_regno
>= 2 && src_regno
<= 8);
1317 if (framep
&& ((op
& 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
1319 /* Only f2 - f8 are used for parameter passing. */
1320 const int src_regno
= GET_SRC_REG (op
);
1322 return (src_regno
>= 2 && src_regno
<= 8);
1325 /* Not an insn that saves a parameter on stack. */
1329 /* Assuming that INSN is a "bl" instruction located at PC, return
1330 nonzero if the destination of the branch is a "blrl" instruction.
1332 This sequence is sometimes found in certain function prologues.
1333 It allows the function to load the LR register with a value that
1334 they can use to access PIC data using PC-relative offsets. */
1337 bl_to_blrl_insn_p (CORE_ADDR pc
, int insn
, enum bfd_endian byte_order
)
1344 absolute
= (int) ((insn
>> 1) & 1);
1345 immediate
= ((insn
& ~3) << 6) >> 6;
1349 dest
= pc
+ immediate
;
1351 dest_insn
= read_memory_integer (dest
, 4, byte_order
);
1352 if ((dest_insn
& 0xfc00ffff) == 0x4c000021) /* blrl */
1358 /* Masks for decoding a branch-and-link (bl) instruction.
1360 BL_MASK and BL_INSTRUCTION are used in combination with each other.
1361 The former is anded with the opcode in question; if the result of
1362 this masking operation is equal to BL_INSTRUCTION, then the opcode in
1363 question is a ``bl'' instruction.
1365 BL_DISPLACMENT_MASK is anded with the opcode in order to extract
1366 the branch displacement. */
1368 #define BL_MASK 0xfc000001
1369 #define BL_INSTRUCTION 0x48000001
1370 #define BL_DISPLACEMENT_MASK 0x03fffffc
1372 static unsigned long
1373 rs6000_fetch_instruction (struct gdbarch
*gdbarch
, const CORE_ADDR pc
)
1375 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1379 /* Fetch the instruction and convert it to an integer. */
1380 if (target_read_memory (pc
, buf
, 4))
1382 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1387 /* GCC generates several well-known sequences of instructions at the begining
1388 of each function prologue when compiling with -fstack-check. If one of
1389 such sequences starts at START_PC, then return the address of the
1390 instruction immediately past this sequence. Otherwise, return START_PC. */
1393 rs6000_skip_stack_check (struct gdbarch
*gdbarch
, const CORE_ADDR start_pc
)
1395 CORE_ADDR pc
= start_pc
;
1396 unsigned long op
= rs6000_fetch_instruction (gdbarch
, pc
);
1398 /* First possible sequence: A small number of probes.
1399 stw 0, -<some immediate>(1)
1400 [repeat this instruction any (small) number of times]. */
1402 if ((op
& 0xffff0000) == 0x90010000)
1404 while ((op
& 0xffff0000) == 0x90010000)
1407 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1412 /* Second sequence: A probing loop.
1413 addi 12,1,-<some immediate>
1414 lis 0,-<some immediate>
1415 [possibly ori 0,0,<some immediate>]
1419 addi 12,12,-<some immediate>
1422 [possibly one last probe: stw 0,<some immediate>(12)]. */
1426 /* addi 12,1,-<some immediate> */
1427 if ((op
& 0xffff0000) != 0x39810000)
1430 /* lis 0,-<some immediate> */
1432 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1433 if ((op
& 0xffff0000) != 0x3c000000)
1437 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1438 /* [possibly ori 0,0,<some immediate>] */
1439 if ((op
& 0xffff0000) == 0x60000000)
1442 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1445 if (op
!= 0x7c0c0214)
1450 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1451 if (op
!= 0x7c0c0000)
1456 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1457 if ((op
& 0xff9f0001) != 0x41820000)
1460 /* addi 12,12,-<some immediate> */
1462 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1463 if ((op
& 0xffff0000) != 0x398c0000)
1468 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1469 if (op
!= 0x900c0000)
1474 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1475 if ((op
& 0xfc000001) != 0x48000000)
1478 /* [possibly one last probe: stw 0,<some immediate>(12)]. */
1480 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1481 if ((op
& 0xffff0000) == 0x900c0000)
1484 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1487 /* We found a valid stack-check sequence, return the new PC. */
1491 /* Third sequence: No probe; instead, a comparizon between the stack size
1492 limit (saved in a run-time global variable) and the current stack
1495 addi 0,1,-<some immediate>
1496 lis 12,__gnat_stack_limit@ha
1497 lwz 12,__gnat_stack_limit@l(12)
1500 or, with a small variant in the case of a bigger stack frame:
1501 addis 0,1,<some immediate>
1502 addic 0,0,-<some immediate>
1503 lis 12,__gnat_stack_limit@ha
1504 lwz 12,__gnat_stack_limit@l(12)
1509 /* addi 0,1,-<some immediate> */
1510 if ((op
& 0xffff0000) != 0x38010000)
1512 /* small stack frame variant not recognized; try the
1513 big stack frame variant: */
1515 /* addis 0,1,<some immediate> */
1516 if ((op
& 0xffff0000) != 0x3c010000)
1519 /* addic 0,0,-<some immediate> */
1521 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1522 if ((op
& 0xffff0000) != 0x30000000)
1526 /* lis 12,<some immediate> */
1528 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1529 if ((op
& 0xffff0000) != 0x3d800000)
1532 /* lwz 12,<some immediate>(12) */
1534 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1535 if ((op
& 0xffff0000) != 0x818c0000)
1540 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1541 if ((op
& 0xfffffffe) != 0x7c406008)
1544 /* We found a valid stack-check sequence, return the new PC. */
1548 /* No stack check code in our prologue, return the start_pc. */
1552 /* return pc value after skipping a function prologue and also return
1553 information about a function frame.
1555 in struct rs6000_framedata fdata:
1556 - frameless is TRUE, if function does not have a frame.
1557 - nosavedpc is TRUE, if function does not save %pc value in its frame.
1558 - offset is the initial size of this stack frame --- the amount by
1559 which we decrement the sp to allocate the frame.
1560 - saved_gpr is the number of the first saved gpr.
1561 - saved_fpr is the number of the first saved fpr.
1562 - saved_vr is the number of the first saved vr.
1563 - saved_ev is the number of the first saved ev.
1564 - alloca_reg is the number of the register used for alloca() handling.
1566 - gpr_offset is the offset of the first saved gpr from the previous frame.
1567 - fpr_offset is the offset of the first saved fpr from the previous frame.
1568 - vr_offset is the offset of the first saved vr from the previous frame.
1569 - ev_offset is the offset of the first saved ev from the previous frame.
1570 - lr_offset is the offset of the saved lr
1571 - cr_offset is the offset of the saved cr
1572 - vrsave_offset is the offset of the saved vrsave register. */
1575 skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
, CORE_ADDR lim_pc
,
1576 struct rs6000_framedata
*fdata
)
1578 CORE_ADDR orig_pc
= pc
;
1579 CORE_ADDR last_prologue_pc
= pc
;
1580 CORE_ADDR li_found_pc
= 0;
1584 long vr_saved_offset
= 0;
1590 int vrsave_reg
= -1;
1593 int minimal_toc_loaded
= 0;
1594 int prev_insn_was_prologue_insn
= 1;
1595 int num_skip_non_prologue_insns
= 0;
1596 int r0_contains_arg
= 0;
1597 const struct bfd_arch_info
*arch_info
= gdbarch_bfd_arch_info (gdbarch
);
1598 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1599 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1601 memset (fdata
, 0, sizeof (struct rs6000_framedata
));
1602 fdata
->saved_gpr
= -1;
1603 fdata
->saved_fpr
= -1;
1604 fdata
->saved_vr
= -1;
1605 fdata
->saved_ev
= -1;
1606 fdata
->alloca_reg
= -1;
1607 fdata
->frameless
= 1;
1608 fdata
->nosavedpc
= 1;
1609 fdata
->lr_register
= -1;
1611 pc
= rs6000_skip_stack_check (gdbarch
, pc
);
1617 /* Sometimes it isn't clear if an instruction is a prologue
1618 instruction or not. When we encounter one of these ambiguous
1619 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
1620 Otherwise, we'll assume that it really is a prologue instruction. */
1621 if (prev_insn_was_prologue_insn
)
1622 last_prologue_pc
= pc
;
1624 /* Stop scanning if we've hit the limit. */
1628 prev_insn_was_prologue_insn
= 1;
1630 /* Fetch the instruction and convert it to an integer. */
1631 if (target_read_memory (pc
, buf
, 4))
1633 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1635 if ((op
& 0xfc1fffff) == 0x7c0802a6)
1637 /* Since shared library / PIC code, which needs to get its
1638 address at runtime, can appear to save more than one link
1652 remember just the first one, but skip over additional
1655 lr_reg
= (op
& 0x03e00000) >> 21;
1657 r0_contains_arg
= 0;
1660 else if ((op
& 0xfc1fffff) == 0x7c000026)
1662 cr_reg
= (op
& 0x03e00000);
1664 r0_contains_arg
= 0;
1668 else if ((op
& 0xfc1f0000) == 0xd8010000)
1669 { /* stfd Rx,NUM(r1) */
1670 reg
= GET_SRC_REG (op
);
1671 if (fdata
->saved_fpr
== -1 || fdata
->saved_fpr
> reg
)
1673 fdata
->saved_fpr
= reg
;
1674 fdata
->fpr_offset
= SIGNED_SHORT (op
) + offset
;
1679 else if (((op
& 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
1680 (((op
& 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1681 (op
& 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1682 (op
& 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
1685 reg
= GET_SRC_REG (op
);
1686 if ((op
& 0xfc1f0000) == 0xbc010000)
1687 fdata
->gpr_mask
|= ~((1U << reg
) - 1);
1689 fdata
->gpr_mask
|= 1U << reg
;
1690 if (fdata
->saved_gpr
== -1 || fdata
->saved_gpr
> reg
)
1692 fdata
->saved_gpr
= reg
;
1693 if ((op
& 0xfc1f0003) == 0xf8010000)
1695 fdata
->gpr_offset
= SIGNED_SHORT (op
) + offset
;
1700 else if ((op
& 0xffff0000) == 0x3c4c0000
1701 || (op
& 0xffff0000) == 0x3c400000
1702 || (op
& 0xffff0000) == 0x38420000)
1704 /* . 0: addis 2,12,.TOC.-0b@ha
1705 . addi 2,2,.TOC.-0b@l
1709 used by ELFv2 global entry points to set up r2. */
1712 else if (op
== 0x60000000)
1715 /* Allow nops in the prologue, but do not consider them to
1716 be part of the prologue unless followed by other prologue
1718 prev_insn_was_prologue_insn
= 0;
1722 else if ((op
& 0xffff0000) == 0x3c000000)
1723 { /* addis 0,0,NUM, used for >= 32k frames */
1724 fdata
->offset
= (op
& 0x0000ffff) << 16;
1725 fdata
->frameless
= 0;
1726 r0_contains_arg
= 0;
1730 else if ((op
& 0xffff0000) == 0x60000000)
1731 { /* ori 0,0,NUM, 2nd half of >= 32k frames */
1732 fdata
->offset
|= (op
& 0x0000ffff);
1733 fdata
->frameless
= 0;
1734 r0_contains_arg
= 0;
1738 else if (lr_reg
>= 0 &&
1739 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1740 (((op
& 0xffff0000) == (lr_reg
| 0xf8010000)) ||
1741 /* stw Rx, NUM(r1) */
1742 ((op
& 0xffff0000) == (lr_reg
| 0x90010000)) ||
1743 /* stwu Rx, NUM(r1) */
1744 ((op
& 0xffff0000) == (lr_reg
| 0x94010000))))
1745 { /* where Rx == lr */
1746 fdata
->lr_offset
= offset
;
1747 fdata
->nosavedpc
= 0;
1748 /* Invalidate lr_reg, but don't set it to -1.
1749 That would mean that it had never been set. */
1751 if ((op
& 0xfc000003) == 0xf8000000 || /* std */
1752 (op
& 0xfc000000) == 0x90000000) /* stw */
1754 /* Does not update r1, so add displacement to lr_offset. */
1755 fdata
->lr_offset
+= SIGNED_SHORT (op
);
1760 else if (cr_reg
>= 0 &&
1761 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1762 (((op
& 0xffff0000) == (cr_reg
| 0xf8010000)) ||
1763 /* stw Rx, NUM(r1) */
1764 ((op
& 0xffff0000) == (cr_reg
| 0x90010000)) ||
1765 /* stwu Rx, NUM(r1) */
1766 ((op
& 0xffff0000) == (cr_reg
| 0x94010000))))
1767 { /* where Rx == cr */
1768 fdata
->cr_offset
= offset
;
1769 /* Invalidate cr_reg, but don't set it to -1.
1770 That would mean that it had never been set. */
1772 if ((op
& 0xfc000003) == 0xf8000000 ||
1773 (op
& 0xfc000000) == 0x90000000)
1775 /* Does not update r1, so add displacement to cr_offset. */
1776 fdata
->cr_offset
+= SIGNED_SHORT (op
);
1781 else if ((op
& 0xfe80ffff) == 0x42800005 && lr_reg
!= -1)
1783 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1784 prediction bits. If the LR has already been saved, we can
1788 else if (op
== 0x48000005)
1795 else if (op
== 0x48000004)
1800 else if ((op
& 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1801 in V.4 -mminimal-toc */
1802 (op
& 0xffff0000) == 0x3bde0000)
1803 { /* addi 30,30,foo@l */
1807 else if ((op
& 0xfc000001) == 0x48000001)
1811 fdata
->frameless
= 0;
1813 /* If the return address has already been saved, we can skip
1814 calls to blrl (for PIC). */
1815 if (lr_reg
!= -1 && bl_to_blrl_insn_p (pc
, op
, byte_order
))
1821 /* Don't skip over the subroutine call if it is not within
1822 the first three instructions of the prologue and either
1823 we have no line table information or the line info tells
1824 us that the subroutine call is not part of the line
1825 associated with the prologue. */
1826 if ((pc
- orig_pc
) > 8)
1828 struct symtab_and_line prologue_sal
= find_pc_line (orig_pc
, 0);
1829 struct symtab_and_line this_sal
= find_pc_line (pc
, 0);
1831 if ((prologue_sal
.line
== 0)
1832 || (prologue_sal
.line
!= this_sal
.line
))
1836 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
1838 /* At this point, make sure this is not a trampoline
1839 function (a function that simply calls another functions,
1840 and nothing else). If the next is not a nop, this branch
1841 was part of the function prologue. */
1843 if (op
== 0x4def7b82 || op
== 0) /* crorc 15, 15, 15 */
1844 break; /* Don't skip over
1850 /* update stack pointer */
1851 else if ((op
& 0xfc1f0000) == 0x94010000)
1852 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
1853 fdata
->frameless
= 0;
1854 fdata
->offset
= SIGNED_SHORT (op
);
1855 offset
= fdata
->offset
;
1858 else if ((op
& 0xfc1f016a) == 0x7c01016e)
1859 { /* stwux rX,r1,rY */
1860 /* No way to figure out what r1 is going to be. */
1861 fdata
->frameless
= 0;
1862 offset
= fdata
->offset
;
1865 else if ((op
& 0xfc1f0003) == 0xf8010001)
1866 { /* stdu rX,NUM(r1) */
1867 fdata
->frameless
= 0;
1868 fdata
->offset
= SIGNED_SHORT (op
& ~3UL);
1869 offset
= fdata
->offset
;
1872 else if ((op
& 0xfc1f016a) == 0x7c01016a)
1873 { /* stdux rX,r1,rY */
1874 /* No way to figure out what r1 is going to be. */
1875 fdata
->frameless
= 0;
1876 offset
= fdata
->offset
;
1879 else if ((op
& 0xffff0000) == 0x38210000)
1880 { /* addi r1,r1,SIMM */
1881 fdata
->frameless
= 0;
1882 fdata
->offset
+= SIGNED_SHORT (op
);
1883 offset
= fdata
->offset
;
1886 /* Load up minimal toc pointer. Do not treat an epilogue restore
1887 of r31 as a minimal TOC load. */
1888 else if (((op
>> 22) == 0x20f || /* l r31,... or l r30,... */
1889 (op
>> 22) == 0x3af) /* ld r31,... or ld r30,... */
1891 && !minimal_toc_loaded
)
1893 minimal_toc_loaded
= 1;
1896 /* move parameters from argument registers to local variable
1899 else if ((op
& 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1900 (((op
>> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1901 (((op
>> 21) & 31) <= 10) &&
1902 ((long) ((op
>> 16) & 31)
1903 >= fdata
->saved_gpr
)) /* Rx: local var reg */
1907 /* store parameters in stack */
1909 /* Move parameters from argument registers to temporary register. */
1910 else if (store_param_on_stack_p (op
, framep
, &r0_contains_arg
))
1914 /* Set up frame pointer */
1916 else if (op
== 0x603d0000) /* oril r29, r1, 0x0 */
1918 fdata
->frameless
= 0;
1920 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 29);
1923 /* Another way to set up the frame pointer. */
1925 else if (op
== 0x603f0000 /* oril r31, r1, 0x0 */
1926 || op
== 0x7c3f0b78)
1928 fdata
->frameless
= 0;
1930 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 31);
1933 /* Another way to set up the frame pointer. */
1935 else if ((op
& 0xfc1fffff) == 0x38010000)
1936 { /* addi rX, r1, 0x0 */
1937 fdata
->frameless
= 0;
1939 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
1940 + ((op
& ~0x38010000) >> 21));
1943 /* AltiVec related instructions. */
1944 /* Store the vrsave register (spr 256) in another register for
1945 later manipulation, or load a register into the vrsave
1946 register. 2 instructions are used: mfvrsave and
1947 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1948 and mtspr SPR256, Rn. */
1949 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1950 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1951 else if ((op
& 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1953 vrsave_reg
= GET_SRC_REG (op
);
1956 else if ((op
& 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1960 /* Store the register where vrsave was saved to onto the stack:
1961 rS is the register where vrsave was stored in a previous
1963 /* 100100 sssss 00001 dddddddd dddddddd */
1964 else if ((op
& 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1966 if (vrsave_reg
== GET_SRC_REG (op
))
1968 fdata
->vrsave_offset
= SIGNED_SHORT (op
) + offset
;
1973 /* Compute the new value of vrsave, by modifying the register
1974 where vrsave was saved to. */
1975 else if (((op
& 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1976 || ((op
& 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1980 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1981 in a pair of insns to save the vector registers on the
1983 /* 001110 00000 00000 iiii iiii iiii iiii */
1984 /* 001110 01110 00000 iiii iiii iiii iiii */
1985 else if ((op
& 0xffff0000) == 0x38000000 /* li r0, SIMM */
1986 || (op
& 0xffff0000) == 0x39c00000) /* li r14, SIMM */
1988 if ((op
& 0xffff0000) == 0x38000000)
1989 r0_contains_arg
= 0;
1991 vr_saved_offset
= SIGNED_SHORT (op
);
1993 /* This insn by itself is not part of the prologue, unless
1994 if part of the pair of insns mentioned above. So do not
1995 record this insn as part of the prologue yet. */
1996 prev_insn_was_prologue_insn
= 0;
1998 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1999 /* 011111 sssss 11111 00000 00111001110 */
2000 else if ((op
& 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
2002 if (pc
== (li_found_pc
+ 4))
2004 vr_reg
= GET_SRC_REG (op
);
2005 /* If this is the first vector reg to be saved, or if
2006 it has a lower number than others previously seen,
2007 reupdate the frame info. */
2008 if (fdata
->saved_vr
== -1 || fdata
->saved_vr
> vr_reg
)
2010 fdata
->saved_vr
= vr_reg
;
2011 fdata
->vr_offset
= vr_saved_offset
+ offset
;
2013 vr_saved_offset
= -1;
2018 /* End AltiVec related instructions. */
2020 /* Start BookE related instructions. */
2021 /* Store gen register S at (r31+uimm).
2022 Any register less than r13 is volatile, so we don't care. */
2023 /* 000100 sssss 11111 iiiii 01100100001 */
2024 else if (arch_info
->mach
== bfd_mach_ppc_e500
2025 && (op
& 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
2027 if ((op
& 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
2030 ev_reg
= GET_SRC_REG (op
);
2031 imm
= (op
>> 11) & 0x1f;
2032 ev_offset
= imm
* 8;
2033 /* If this is the first vector reg to be saved, or if
2034 it has a lower number than others previously seen,
2035 reupdate the frame info. */
2036 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2038 fdata
->saved_ev
= ev_reg
;
2039 fdata
->ev_offset
= ev_offset
+ offset
;
2044 /* Store gen register rS at (r1+rB). */
2045 /* 000100 sssss 00001 bbbbb 01100100000 */
2046 else if (arch_info
->mach
== bfd_mach_ppc_e500
2047 && (op
& 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
2049 if (pc
== (li_found_pc
+ 4))
2051 ev_reg
= GET_SRC_REG (op
);
2052 /* If this is the first vector reg to be saved, or if
2053 it has a lower number than others previously seen,
2054 reupdate the frame info. */
2055 /* We know the contents of rB from the previous instruction. */
2056 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2058 fdata
->saved_ev
= ev_reg
;
2059 fdata
->ev_offset
= vr_saved_offset
+ offset
;
2061 vr_saved_offset
= -1;
2067 /* Store gen register r31 at (rA+uimm). */
2068 /* 000100 11111 aaaaa iiiii 01100100001 */
2069 else if (arch_info
->mach
== bfd_mach_ppc_e500
2070 && (op
& 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
2072 /* Wwe know that the source register is 31 already, but
2073 it can't hurt to compute it. */
2074 ev_reg
= GET_SRC_REG (op
);
2075 ev_offset
= ((op
>> 11) & 0x1f) * 8;
2076 /* If this is the first vector reg to be saved, or if
2077 it has a lower number than others previously seen,
2078 reupdate the frame info. */
2079 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2081 fdata
->saved_ev
= ev_reg
;
2082 fdata
->ev_offset
= ev_offset
+ offset
;
2087 /* Store gen register S at (r31+r0).
2088 Store param on stack when offset from SP bigger than 4 bytes. */
2089 /* 000100 sssss 11111 00000 01100100000 */
2090 else if (arch_info
->mach
== bfd_mach_ppc_e500
2091 && (op
& 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
2093 if (pc
== (li_found_pc
+ 4))
2095 if ((op
& 0x03e00000) >= 0x01a00000)
2097 ev_reg
= GET_SRC_REG (op
);
2098 /* If this is the first vector reg to be saved, or if
2099 it has a lower number than others previously seen,
2100 reupdate the frame info. */
2101 /* We know the contents of r0 from the previous
2103 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2105 fdata
->saved_ev
= ev_reg
;
2106 fdata
->ev_offset
= vr_saved_offset
+ offset
;
2110 vr_saved_offset
= -1;
2115 /* End BookE related instructions. */
2119 unsigned int all_mask
= ~((1U << fdata
->saved_gpr
) - 1);
2121 /* Not a recognized prologue instruction.
2122 Handle optimizer code motions into the prologue by continuing
2123 the search if we have no valid frame yet or if the return
2124 address is not yet saved in the frame. Also skip instructions
2125 if some of the GPRs expected to be saved are not yet saved. */
2126 if (fdata
->frameless
== 0 && fdata
->nosavedpc
== 0
2127 && (fdata
->gpr_mask
& all_mask
) == all_mask
)
2130 if (op
== 0x4e800020 /* blr */
2131 || op
== 0x4e800420) /* bctr */
2132 /* Do not scan past epilogue in frameless functions or
2135 if ((op
& 0xf4000000) == 0x40000000) /* bxx */
2136 /* Never skip branches. */
2139 if (num_skip_non_prologue_insns
++ > max_skip_non_prologue_insns
)
2140 /* Do not scan too many insns, scanning insns is expensive with
2144 /* Continue scanning. */
2145 prev_insn_was_prologue_insn
= 0;
2151 /* I have problems with skipping over __main() that I need to address
2152 * sometime. Previously, I used to use misc_function_vector which
2153 * didn't work as well as I wanted to be. -MGO */
2155 /* If the first thing after skipping a prolog is a branch to a function,
2156 this might be a call to an initializer in main(), introduced by gcc2.
2157 We'd like to skip over it as well. Fortunately, xlc does some extra
2158 work before calling a function right after a prologue, thus we can
2159 single out such gcc2 behaviour. */
2162 if ((op
& 0xfc000001) == 0x48000001)
2163 { /* bl foo, an initializer function? */
2164 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
2166 if (op
== 0x4def7b82)
2167 { /* cror 0xf, 0xf, 0xf (nop) */
2169 /* Check and see if we are in main. If so, skip over this
2170 initializer function as well. */
2172 tmp
= find_pc_misc_function (pc
);
2174 && strcmp (misc_function_vector
[tmp
].name
, main_name ()) == 0)
2180 if (pc
== lim_pc
&& lr_reg
>= 0)
2181 fdata
->lr_register
= lr_reg
;
2183 fdata
->offset
= -fdata
->offset
;
2184 return last_prologue_pc
;
2188 rs6000_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2190 struct rs6000_framedata frame
;
2191 CORE_ADDR limit_pc
, func_addr
, func_end_addr
= 0;
2193 /* See if we can determine the end of the prologue via the symbol table.
2194 If so, then return either PC, or the PC after the prologue, whichever
2196 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end_addr
))
2198 CORE_ADDR post_prologue_pc
2199 = skip_prologue_using_sal (gdbarch
, func_addr
);
2200 if (post_prologue_pc
!= 0)
2201 return std::max (pc
, post_prologue_pc
);
2204 /* Can't determine prologue from the symbol table, need to examine
2207 /* Find an upper limit on the function prologue using the debug
2208 information. If the debug information could not be used to provide
2209 that bound, then use an arbitrary large number as the upper bound. */
2210 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
2212 limit_pc
= pc
+ 100; /* Magic. */
2214 /* Do not allow limit_pc to be past the function end, if we know
2215 where that end is... */
2216 if (func_end_addr
&& limit_pc
> func_end_addr
)
2217 limit_pc
= func_end_addr
;
2219 pc
= skip_prologue (gdbarch
, pc
, limit_pc
, &frame
);
2223 /* When compiling for EABI, some versions of GCC emit a call to __eabi
2224 in the prologue of main().
2226 The function below examines the code pointed at by PC and checks to
2227 see if it corresponds to a call to __eabi. If so, it returns the
2228 address of the instruction following that call. Otherwise, it simply
2232 rs6000_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2234 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2238 if (target_read_memory (pc
, buf
, 4))
2240 op
= extract_unsigned_integer (buf
, 4, byte_order
);
2242 if ((op
& BL_MASK
) == BL_INSTRUCTION
)
2244 CORE_ADDR displ
= op
& BL_DISPLACEMENT_MASK
;
2245 CORE_ADDR call_dest
= pc
+ 4 + displ
;
2246 struct bound_minimal_symbol s
= lookup_minimal_symbol_by_pc (call_dest
);
2248 /* We check for ___eabi (three leading underscores) in addition
2249 to __eabi in case the GCC option "-fleading-underscore" was
2250 used to compile the program. */
2251 if (s
.minsym
!= NULL
2252 && MSYMBOL_LINKAGE_NAME (s
.minsym
) != NULL
2253 && (strcmp (MSYMBOL_LINKAGE_NAME (s
.minsym
), "__eabi") == 0
2254 || strcmp (MSYMBOL_LINKAGE_NAME (s
.minsym
), "___eabi") == 0))
2260 /* All the ABI's require 16 byte alignment. */
2262 rs6000_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2264 return (addr
& -16);
2267 /* Return whether handle_inferior_event() should proceed through code
2268 starting at PC in function NAME when stepping.
2270 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
2271 handle memory references that are too distant to fit in instructions
2272 generated by the compiler. For example, if 'foo' in the following
2277 is greater than 32767, the linker might replace the lwz with a branch to
2278 somewhere in @FIX1 that does the load in 2 instructions and then branches
2279 back to where execution should continue.
2281 GDB should silently step over @FIX code, just like AIX dbx does.
2282 Unfortunately, the linker uses the "b" instruction for the
2283 branches, meaning that the link register doesn't get set.
2284 Therefore, GDB's usual step_over_function () mechanism won't work.
2286 Instead, use the gdbarch_skip_trampoline_code and
2287 gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past
2291 rs6000_in_solib_return_trampoline (struct gdbarch
*gdbarch
,
2292 CORE_ADDR pc
, const char *name
)
2294 return name
&& startswith (name
, "@FIX");
2297 /* Skip code that the user doesn't want to see when stepping:
2299 1. Indirect function calls use a piece of trampoline code to do context
2300 switching, i.e. to set the new TOC table. Skip such code if we are on
2301 its first instruction (as when we have single-stepped to here).
2303 2. Skip shared library trampoline code (which is different from
2304 indirect function call trampolines).
2306 3. Skip bigtoc fixup code.
2308 Result is desired PC to step until, or NULL if we are not in
2309 code that should be skipped. */
2312 rs6000_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
2314 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2315 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2316 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2317 unsigned int ii
, op
;
2319 CORE_ADDR solib_target_pc
;
2320 struct bound_minimal_symbol msymbol
;
2322 static unsigned trampoline_code
[] =
2324 0x800b0000, /* l r0,0x0(r11) */
2325 0x90410014, /* st r2,0x14(r1) */
2326 0x7c0903a6, /* mtctr r0 */
2327 0x804b0004, /* l r2,0x4(r11) */
2328 0x816b0008, /* l r11,0x8(r11) */
2329 0x4e800420, /* bctr */
2330 0x4e800020, /* br */
2334 /* Check for bigtoc fixup code. */
2335 msymbol
= lookup_minimal_symbol_by_pc (pc
);
2337 && rs6000_in_solib_return_trampoline (gdbarch
, pc
,
2338 MSYMBOL_LINKAGE_NAME (msymbol
.minsym
)))
2340 /* Double-check that the third instruction from PC is relative "b". */
2341 op
= read_memory_integer (pc
+ 8, 4, byte_order
);
2342 if ((op
& 0xfc000003) == 0x48000000)
2344 /* Extract bits 6-29 as a signed 24-bit relative word address and
2345 add it to the containing PC. */
2346 rel
= ((int)(op
<< 6) >> 6);
2347 return pc
+ 8 + rel
;
2351 /* If pc is in a shared library trampoline, return its target. */
2352 solib_target_pc
= find_solib_trampoline_target (frame
, pc
);
2353 if (solib_target_pc
)
2354 return solib_target_pc
;
2356 for (ii
= 0; trampoline_code
[ii
]; ++ii
)
2358 op
= read_memory_integer (pc
+ (ii
* 4), 4, byte_order
);
2359 if (op
!= trampoline_code
[ii
])
2362 ii
= get_frame_register_unsigned (frame
, 11); /* r11 holds destination
2364 pc
= read_memory_unsigned_integer (ii
, tdep
->wordsize
, byte_order
);
2368 /* ISA-specific vector types. */
2370 static struct type
*
2371 rs6000_builtin_type_vec64 (struct gdbarch
*gdbarch
)
2373 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2375 if (!tdep
->ppc_builtin_type_vec64
)
2377 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2379 /* The type we're building is this: */
2381 union __gdb_builtin_type_vec64
2385 int32_t v2_int32
[2];
2386 int16_t v4_int16
[4];
2393 t
= arch_composite_type (gdbarch
,
2394 "__ppc_builtin_type_vec64", TYPE_CODE_UNION
);
2395 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2396 append_composite_type_field (t
, "v2_float",
2397 init_vector_type (bt
->builtin_float
, 2));
2398 append_composite_type_field (t
, "v2_int32",
2399 init_vector_type (bt
->builtin_int32
, 2));
2400 append_composite_type_field (t
, "v4_int16",
2401 init_vector_type (bt
->builtin_int16
, 4));
2402 append_composite_type_field (t
, "v8_int8",
2403 init_vector_type (bt
->builtin_int8
, 8));
2405 TYPE_VECTOR (t
) = 1;
2406 TYPE_NAME (t
) = "ppc_builtin_type_vec64";
2407 tdep
->ppc_builtin_type_vec64
= t
;
2410 return tdep
->ppc_builtin_type_vec64
;
2413 /* Vector 128 type. */
2415 static struct type
*
2416 rs6000_builtin_type_vec128 (struct gdbarch
*gdbarch
)
2418 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2420 if (!tdep
->ppc_builtin_type_vec128
)
2422 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2424 /* The type we're building is this
2426 type = union __ppc_builtin_type_vec128 {
2428 double v2_double[2];
2430 int32_t v4_int32[4];
2431 int16_t v8_int16[8];
2432 int8_t v16_int8[16];
2438 t
= arch_composite_type (gdbarch
,
2439 "__ppc_builtin_type_vec128", TYPE_CODE_UNION
);
2440 append_composite_type_field (t
, "uint128", bt
->builtin_uint128
);
2441 append_composite_type_field (t
, "v2_double",
2442 init_vector_type (bt
->builtin_double
, 2));
2443 append_composite_type_field (t
, "v4_float",
2444 init_vector_type (bt
->builtin_float
, 4));
2445 append_composite_type_field (t
, "v4_int32",
2446 init_vector_type (bt
->builtin_int32
, 4));
2447 append_composite_type_field (t
, "v8_int16",
2448 init_vector_type (bt
->builtin_int16
, 8));
2449 append_composite_type_field (t
, "v16_int8",
2450 init_vector_type (bt
->builtin_int8
, 16));
2452 TYPE_VECTOR (t
) = 1;
2453 TYPE_NAME (t
) = "ppc_builtin_type_vec128";
2454 tdep
->ppc_builtin_type_vec128
= t
;
2457 return tdep
->ppc_builtin_type_vec128
;
2460 /* Return the name of register number REGNO, or the empty string if it
2461 is an anonymous register. */
2464 rs6000_register_name (struct gdbarch
*gdbarch
, int regno
)
2466 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2468 /* The upper half "registers" have names in the XML description,
2469 but we present only the low GPRs and the full 64-bit registers
2471 if (tdep
->ppc_ev0_upper_regnum
>= 0
2472 && tdep
->ppc_ev0_upper_regnum
<= regno
2473 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
2476 /* Hide the upper halves of the vs0~vs31 registers. */
2477 if (tdep
->ppc_vsr0_regnum
>= 0
2478 && tdep
->ppc_vsr0_upper_regnum
<= regno
2479 && regno
< tdep
->ppc_vsr0_upper_regnum
+ ppc_num_gprs
)
2482 /* Check if the SPE pseudo registers are available. */
2483 if (IS_SPE_PSEUDOREG (tdep
, regno
))
2485 static const char *const spe_regnames
[] = {
2486 "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7",
2487 "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15",
2488 "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23",
2489 "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31",
2491 return spe_regnames
[regno
- tdep
->ppc_ev0_regnum
];
2494 /* Check if the decimal128 pseudo-registers are available. */
2495 if (IS_DFP_PSEUDOREG (tdep
, regno
))
2497 static const char *const dfp128_regnames
[] = {
2498 "dl0", "dl1", "dl2", "dl3",
2499 "dl4", "dl5", "dl6", "dl7",
2500 "dl8", "dl9", "dl10", "dl11",
2501 "dl12", "dl13", "dl14", "dl15"
2503 return dfp128_regnames
[regno
- tdep
->ppc_dl0_regnum
];
2506 /* Check if this is a VSX pseudo-register. */
2507 if (IS_VSX_PSEUDOREG (tdep
, regno
))
2509 static const char *const vsx_regnames
[] = {
2510 "vs0", "vs1", "vs2", "vs3", "vs4", "vs5", "vs6", "vs7",
2511 "vs8", "vs9", "vs10", "vs11", "vs12", "vs13", "vs14",
2512 "vs15", "vs16", "vs17", "vs18", "vs19", "vs20", "vs21",
2513 "vs22", "vs23", "vs24", "vs25", "vs26", "vs27", "vs28",
2514 "vs29", "vs30", "vs31", "vs32", "vs33", "vs34", "vs35",
2515 "vs36", "vs37", "vs38", "vs39", "vs40", "vs41", "vs42",
2516 "vs43", "vs44", "vs45", "vs46", "vs47", "vs48", "vs49",
2517 "vs50", "vs51", "vs52", "vs53", "vs54", "vs55", "vs56",
2518 "vs57", "vs58", "vs59", "vs60", "vs61", "vs62", "vs63"
2520 return vsx_regnames
[regno
- tdep
->ppc_vsr0_regnum
];
2523 /* Check if the this is a Extended FP pseudo-register. */
2524 if (IS_EFP_PSEUDOREG (tdep
, regno
))
2526 static const char *const efpr_regnames
[] = {
2527 "f32", "f33", "f34", "f35", "f36", "f37", "f38",
2528 "f39", "f40", "f41", "f42", "f43", "f44", "f45",
2529 "f46", "f47", "f48", "f49", "f50", "f51",
2530 "f52", "f53", "f54", "f55", "f56", "f57",
2531 "f58", "f59", "f60", "f61", "f62", "f63"
2533 return efpr_regnames
[regno
- tdep
->ppc_efpr0_regnum
];
2536 return tdesc_register_name (gdbarch
, regno
);
2539 /* Return the GDB type object for the "standard" data type of data in
2542 static struct type
*
2543 rs6000_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2545 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2547 /* These are the only pseudo-registers we support. */
2548 gdb_assert (IS_SPE_PSEUDOREG (tdep
, regnum
)
2549 || IS_DFP_PSEUDOREG (tdep
, regnum
)
2550 || IS_VSX_PSEUDOREG (tdep
, regnum
)
2551 || IS_EFP_PSEUDOREG (tdep
, regnum
));
2553 /* These are the e500 pseudo-registers. */
2554 if (IS_SPE_PSEUDOREG (tdep
, regnum
))
2555 return rs6000_builtin_type_vec64 (gdbarch
);
2556 else if (IS_DFP_PSEUDOREG (tdep
, regnum
))
2557 /* PPC decimal128 pseudo-registers. */
2558 return builtin_type (gdbarch
)->builtin_declong
;
2559 else if (IS_VSX_PSEUDOREG (tdep
, regnum
))
2560 /* POWER7 VSX pseudo-registers. */
2561 return rs6000_builtin_type_vec128 (gdbarch
);
2563 /* POWER7 Extended FP pseudo-registers. */
2564 return builtin_type (gdbarch
)->builtin_double
;
2567 /* Is REGNUM a member of REGGROUP? */
2569 rs6000_pseudo_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2570 struct reggroup
*group
)
2572 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2574 /* These are the only pseudo-registers we support. */
2575 gdb_assert (IS_SPE_PSEUDOREG (tdep
, regnum
)
2576 || IS_DFP_PSEUDOREG (tdep
, regnum
)
2577 || IS_VSX_PSEUDOREG (tdep
, regnum
)
2578 || IS_EFP_PSEUDOREG (tdep
, regnum
));
2580 /* These are the e500 pseudo-registers or the POWER7 VSX registers. */
2581 if (IS_SPE_PSEUDOREG (tdep
, regnum
) || IS_VSX_PSEUDOREG (tdep
, regnum
))
2582 return group
== all_reggroup
|| group
== vector_reggroup
;
2584 /* PPC decimal128 or Extended FP pseudo-registers. */
2585 return group
== all_reggroup
|| group
== float_reggroup
;
2588 /* The register format for RS/6000 floating point registers is always
2589 double, we need a conversion if the memory format is float. */
2592 rs6000_convert_register_p (struct gdbarch
*gdbarch
, int regnum
,
2595 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2597 return (tdep
->ppc_fp0_regnum
>= 0
2598 && regnum
>= tdep
->ppc_fp0_regnum
2599 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
2600 && TYPE_CODE (type
) == TYPE_CODE_FLT
2601 && TYPE_LENGTH (type
)
2602 != TYPE_LENGTH (builtin_type (gdbarch
)->builtin_double
));
2606 rs6000_register_to_value (struct frame_info
*frame
,
2610 int *optimizedp
, int *unavailablep
)
2612 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2613 gdb_byte from
[MAX_REGISTER_SIZE
];
2615 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
2617 if (!get_frame_register_bytes (frame
, regnum
, 0,
2618 register_size (gdbarch
, regnum
),
2619 from
, optimizedp
, unavailablep
))
2622 convert_typed_floating (from
, builtin_type (gdbarch
)->builtin_double
,
2624 *optimizedp
= *unavailablep
= 0;
2629 rs6000_value_to_register (struct frame_info
*frame
,
2632 const gdb_byte
*from
)
2634 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2635 gdb_byte to
[MAX_REGISTER_SIZE
];
2637 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
2639 convert_typed_floating (from
, type
,
2640 to
, builtin_type (gdbarch
)->builtin_double
);
2641 put_frame_register (frame
, regnum
, to
);
2644 /* The type of a function that moves the value of REG between CACHE
2645 or BUF --- in either direction. */
2646 typedef enum register_status (*move_ev_register_func
) (struct regcache
*,
2649 /* Move SPE vector register values between a 64-bit buffer and the two
2650 32-bit raw register halves in a regcache. This function handles
2651 both splitting a 64-bit value into two 32-bit halves, and joining
2652 two halves into a whole 64-bit value, depending on the function
2653 passed as the MOVE argument.
2655 EV_REG must be the number of an SPE evN vector register --- a
2656 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2659 Call MOVE once for each 32-bit half of that register, passing
2660 REGCACHE, the number of the raw register corresponding to that
2661 half, and the address of the appropriate half of BUFFER.
2663 For example, passing 'regcache_raw_read' as the MOVE function will
2664 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2665 'regcache_raw_supply' will supply the contents of BUFFER to the
2666 appropriate pair of raw registers in REGCACHE.
2668 You may need to cast away some 'const' qualifiers when passing
2669 MOVE, since this function can't tell at compile-time which of
2670 REGCACHE or BUFFER is acting as the source of the data. If C had
2671 co-variant type qualifiers, ... */
2673 static enum register_status
2674 e500_move_ev_register (move_ev_register_func move
,
2675 struct regcache
*regcache
, int ev_reg
, void *buffer
)
2677 struct gdbarch
*arch
= get_regcache_arch (regcache
);
2678 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
2680 gdb_byte
*byte_buffer
= (gdb_byte
*) buffer
;
2681 enum register_status status
;
2683 gdb_assert (IS_SPE_PSEUDOREG (tdep
, ev_reg
));
2685 reg_index
= ev_reg
- tdep
->ppc_ev0_regnum
;
2687 if (gdbarch_byte_order (arch
) == BFD_ENDIAN_BIG
)
2689 status
= move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2691 if (status
== REG_VALID
)
2692 status
= move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
,
2697 status
= move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
, byte_buffer
);
2698 if (status
== REG_VALID
)
2699 status
= move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2706 static enum register_status
2707 do_regcache_raw_read (struct regcache
*regcache
, int regnum
, void *buffer
)
2709 return regcache_raw_read (regcache
, regnum
, (gdb_byte
*) buffer
);
2712 static enum register_status
2713 do_regcache_raw_write (struct regcache
*regcache
, int regnum
, void *buffer
)
2715 regcache_raw_write (regcache
, regnum
, (const gdb_byte
*) buffer
);
2720 static enum register_status
2721 e500_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2722 int reg_nr
, gdb_byte
*buffer
)
2724 return e500_move_ev_register (do_regcache_raw_read
, regcache
, reg_nr
, buffer
);
2728 e500_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2729 int reg_nr
, const gdb_byte
*buffer
)
2731 e500_move_ev_register (do_regcache_raw_write
, regcache
,
2732 reg_nr
, (void *) buffer
);
2735 /* Read method for DFP pseudo-registers. */
2736 static enum register_status
2737 dfp_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2738 int reg_nr
, gdb_byte
*buffer
)
2740 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2741 int reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2742 enum register_status status
;
2744 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2746 /* Read two FP registers to form a whole dl register. */
2747 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2748 2 * reg_index
, buffer
);
2749 if (status
== REG_VALID
)
2750 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2751 2 * reg_index
+ 1, buffer
+ 8);
2755 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2756 2 * reg_index
+ 1, buffer
);
2757 if (status
== REG_VALID
)
2758 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2759 2 * reg_index
, buffer
+ 8);
2765 /* Write method for DFP pseudo-registers. */
2767 dfp_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2768 int reg_nr
, const gdb_byte
*buffer
)
2770 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2771 int reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2773 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2775 /* Write each half of the dl register into a separate
2777 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2778 2 * reg_index
, buffer
);
2779 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2780 2 * reg_index
+ 1, buffer
+ 8);
2784 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2785 2 * reg_index
+ 1, buffer
);
2786 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2787 2 * reg_index
, buffer
+ 8);
2791 /* Read method for POWER7 VSX pseudo-registers. */
2792 static enum register_status
2793 vsx_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2794 int reg_nr
, gdb_byte
*buffer
)
2796 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2797 int reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2798 enum register_status status
;
2800 /* Read the portion that overlaps the VMX registers. */
2802 status
= regcache_raw_read (regcache
, tdep
->ppc_vr0_regnum
+
2803 reg_index
- 32, buffer
);
2805 /* Read the portion that overlaps the FPR registers. */
2806 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2808 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2810 if (status
== REG_VALID
)
2811 status
= regcache_raw_read (regcache
, tdep
->ppc_vsr0_upper_regnum
+
2812 reg_index
, buffer
+ 8);
2816 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2817 reg_index
, buffer
+ 8);
2818 if (status
== REG_VALID
)
2819 status
= regcache_raw_read (regcache
, tdep
->ppc_vsr0_upper_regnum
+
2826 /* Write method for POWER7 VSX pseudo-registers. */
2828 vsx_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2829 int reg_nr
, const gdb_byte
*buffer
)
2831 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2832 int reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2834 /* Write the portion that overlaps the VMX registers. */
2836 regcache_raw_write (regcache
, tdep
->ppc_vr0_regnum
+
2837 reg_index
- 32, buffer
);
2839 /* Write the portion that overlaps the FPR registers. */
2840 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2842 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2844 regcache_raw_write (regcache
, tdep
->ppc_vsr0_upper_regnum
+
2845 reg_index
, buffer
+ 8);
2849 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2850 reg_index
, buffer
+ 8);
2851 regcache_raw_write (regcache
, tdep
->ppc_vsr0_upper_regnum
+
2856 /* Read method for POWER7 Extended FP pseudo-registers. */
2857 static enum register_status
2858 efpr_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2859 int reg_nr
, gdb_byte
*buffer
)
2861 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2862 int reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
2863 int offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 0 : 8;
2865 /* Read the portion that overlaps the VMX register. */
2866 return regcache_raw_read_part (regcache
, tdep
->ppc_vr0_regnum
+ reg_index
,
2867 offset
, register_size (gdbarch
, reg_nr
),
2871 /* Write method for POWER7 Extended FP pseudo-registers. */
2873 efpr_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2874 int reg_nr
, const gdb_byte
*buffer
)
2876 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2877 int reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
2878 int offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 0 : 8;
2880 /* Write the portion that overlaps the VMX register. */
2881 regcache_raw_write_part (regcache
, tdep
->ppc_vr0_regnum
+ reg_index
,
2882 offset
, register_size (gdbarch
, reg_nr
),
2886 static enum register_status
2887 rs6000_pseudo_register_read (struct gdbarch
*gdbarch
,
2888 struct regcache
*regcache
,
2889 int reg_nr
, gdb_byte
*buffer
)
2891 struct gdbarch
*regcache_arch
= get_regcache_arch (regcache
);
2892 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2894 gdb_assert (regcache_arch
== gdbarch
);
2896 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2897 return e500_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2898 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2899 return dfp_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2900 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2901 return vsx_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2902 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
2903 return efpr_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2905 internal_error (__FILE__
, __LINE__
,
2906 _("rs6000_pseudo_register_read: "
2907 "called on unexpected register '%s' (%d)"),
2908 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2912 rs6000_pseudo_register_write (struct gdbarch
*gdbarch
,
2913 struct regcache
*regcache
,
2914 int reg_nr
, const gdb_byte
*buffer
)
2916 struct gdbarch
*regcache_arch
= get_regcache_arch (regcache
);
2917 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2919 gdb_assert (regcache_arch
== gdbarch
);
2921 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2922 e500_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2923 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2924 dfp_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2925 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2926 vsx_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2927 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
2928 efpr_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2930 internal_error (__FILE__
, __LINE__
,
2931 _("rs6000_pseudo_register_write: "
2932 "called on unexpected register '%s' (%d)"),
2933 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2937 rs6000_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
2938 struct agent_expr
*ax
, int reg_nr
)
2940 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2941 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2943 int reg_index
= reg_nr
- tdep
->ppc_ev0_regnum
;
2944 ax_reg_mask (ax
, tdep
->ppc_gp0_regnum
+ reg_index
);
2945 ax_reg_mask (ax
, tdep
->ppc_ev0_upper_regnum
+ reg_index
);
2947 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2949 int reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2950 ax_reg_mask (ax
, tdep
->ppc_fp0_regnum
+ 2 * reg_index
);
2951 ax_reg_mask (ax
, tdep
->ppc_fp0_regnum
+ 2 * reg_index
+ 1);
2953 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2955 int reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2958 ax_reg_mask (ax
, tdep
->ppc_vr0_regnum
+ reg_index
- 32);
2962 ax_reg_mask (ax
, tdep
->ppc_fp0_regnum
+ reg_index
);
2963 ax_reg_mask (ax
, tdep
->ppc_vsr0_upper_regnum
+ reg_index
);
2966 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
2968 int reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
2969 ax_reg_mask (ax
, tdep
->ppc_vr0_regnum
+ reg_index
);
2972 internal_error (__FILE__
, __LINE__
,
2973 _("rs6000_pseudo_register_collect: "
2974 "called on unexpected register '%s' (%d)"),
2975 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2981 rs6000_gen_return_address (struct gdbarch
*gdbarch
,
2982 struct agent_expr
*ax
, struct axs_value
*value
,
2985 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2986 value
->type
= register_type (gdbarch
, tdep
->ppc_lr_regnum
);
2987 value
->kind
= axs_lvalue_register
;
2988 value
->u
.reg
= tdep
->ppc_lr_regnum
;
2992 /* Convert a DBX STABS register number to a GDB register number. */
2994 rs6000_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
2996 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2998 if (0 <= num
&& num
<= 31)
2999 return tdep
->ppc_gp0_regnum
+ num
;
3000 else if (32 <= num
&& num
<= 63)
3001 /* FIXME: jimb/2004-05-05: What should we do when the debug info
3002 specifies registers the architecture doesn't have? Our
3003 callers don't check the value we return. */
3004 return tdep
->ppc_fp0_regnum
+ (num
- 32);
3005 else if (77 <= num
&& num
<= 108)
3006 return tdep
->ppc_vr0_regnum
+ (num
- 77);
3007 else if (1200 <= num
&& num
< 1200 + 32)
3008 return tdep
->ppc_ev0_upper_regnum
+ (num
- 1200);
3013 return tdep
->ppc_mq_regnum
;
3015 return tdep
->ppc_lr_regnum
;
3017 return tdep
->ppc_ctr_regnum
;
3019 return tdep
->ppc_xer_regnum
;
3021 return tdep
->ppc_vrsave_regnum
;
3023 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
3025 return tdep
->ppc_acc_regnum
;
3027 return tdep
->ppc_spefscr_regnum
;
3034 /* Convert a Dwarf 2 register number to a GDB register number. */
3036 rs6000_dwarf2_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
3038 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3040 if (0 <= num
&& num
<= 31)
3041 return tdep
->ppc_gp0_regnum
+ num
;
3042 else if (32 <= num
&& num
<= 63)
3043 /* FIXME: jimb/2004-05-05: What should we do when the debug info
3044 specifies registers the architecture doesn't have? Our
3045 callers don't check the value we return. */
3046 return tdep
->ppc_fp0_regnum
+ (num
- 32);
3047 else if (1124 <= num
&& num
< 1124 + 32)
3048 return tdep
->ppc_vr0_regnum
+ (num
- 1124);
3049 else if (1200 <= num
&& num
< 1200 + 32)
3050 return tdep
->ppc_ev0_upper_regnum
+ (num
- 1200);
3055 return tdep
->ppc_cr_regnum
;
3057 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
3059 return tdep
->ppc_acc_regnum
;
3061 return tdep
->ppc_mq_regnum
;
3063 return tdep
->ppc_xer_regnum
;
3065 return tdep
->ppc_lr_regnum
;
3067 return tdep
->ppc_ctr_regnum
;
3069 return tdep
->ppc_vrsave_regnum
;
3071 return tdep
->ppc_spefscr_regnum
;
3077 /* Translate a .eh_frame register to DWARF register, or adjust a
3078 .debug_frame register. */
3081 rs6000_adjust_frame_regnum (struct gdbarch
*gdbarch
, int num
, int eh_frame_p
)
3083 /* GCC releases before 3.4 use GCC internal register numbering in
3084 .debug_frame (and .debug_info, et cetera). The numbering is
3085 different from the standard SysV numbering for everything except
3086 for GPRs and FPRs. We can not detect this problem in most cases
3087 - to get accurate debug info for variables living in lr, ctr, v0,
3088 et cetera, use a newer version of GCC. But we must detect
3089 one important case - lr is in column 65 in .debug_frame output,
3092 GCC 3.4, and the "hammer" branch, have a related problem. They
3093 record lr register saves in .debug_frame as 108, but still record
3094 the return column as 65. We fix that up too.
3096 We can do this because 65 is assigned to fpsr, and GCC never
3097 generates debug info referring to it. To add support for
3098 handwritten debug info that restores fpsr, we would need to add a
3099 producer version check to this. */
3108 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
3109 internal register numbering; translate that to the standard DWARF2
3110 register numbering. */
3111 if (0 <= num
&& num
<= 63) /* r0-r31,fp0-fp31 */
3113 else if (68 <= num
&& num
<= 75) /* cr0-cr8 */
3114 return num
- 68 + 86;
3115 else if (77 <= num
&& num
<= 108) /* vr0-vr31 */
3116 return num
- 77 + 1124;
3128 case 109: /* vrsave */
3130 case 110: /* vscr */
3132 case 111: /* spe_acc */
3134 case 112: /* spefscr */
3142 /* Handling the various POWER/PowerPC variants. */
3144 /* Information about a particular processor variant. */
3148 /* Name of this variant. */
3151 /* English description of the variant. */
3154 /* bfd_arch_info.arch corresponding to variant. */
3155 enum bfd_architecture arch
;
3157 /* bfd_arch_info.mach corresponding to variant. */
3160 /* Target description for this variant. */
3161 struct target_desc
**tdesc
;
3164 static struct variant variants
[] =
3166 {"powerpc", "PowerPC user-level", bfd_arch_powerpc
,
3167 bfd_mach_ppc
, &tdesc_powerpc_altivec32
},
3168 {"power", "POWER user-level", bfd_arch_rs6000
,
3169 bfd_mach_rs6k
, &tdesc_rs6000
},
3170 {"403", "IBM PowerPC 403", bfd_arch_powerpc
,
3171 bfd_mach_ppc_403
, &tdesc_powerpc_403
},
3172 {"405", "IBM PowerPC 405", bfd_arch_powerpc
,
3173 bfd_mach_ppc_405
, &tdesc_powerpc_405
},
3174 {"601", "Motorola PowerPC 601", bfd_arch_powerpc
,
3175 bfd_mach_ppc_601
, &tdesc_powerpc_601
},
3176 {"602", "Motorola PowerPC 602", bfd_arch_powerpc
,
3177 bfd_mach_ppc_602
, &tdesc_powerpc_602
},
3178 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc
,
3179 bfd_mach_ppc_603
, &tdesc_powerpc_603
},
3180 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc
,
3181 604, &tdesc_powerpc_604
},
3182 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc
,
3183 bfd_mach_ppc_403gc
, &tdesc_powerpc_403gc
},
3184 {"505", "Motorola PowerPC 505", bfd_arch_powerpc
,
3185 bfd_mach_ppc_505
, &tdesc_powerpc_505
},
3186 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc
,
3187 bfd_mach_ppc_860
, &tdesc_powerpc_860
},
3188 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc
,
3189 bfd_mach_ppc_750
, &tdesc_powerpc_750
},
3190 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc
,
3191 bfd_mach_ppc_7400
, &tdesc_powerpc_7400
},
3192 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc
,
3193 bfd_mach_ppc_e500
, &tdesc_powerpc_e500
},
3196 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc
,
3197 bfd_mach_ppc64
, &tdesc_powerpc_altivec64
},
3198 {"620", "Motorola PowerPC 620", bfd_arch_powerpc
,
3199 bfd_mach_ppc_620
, &tdesc_powerpc_64
},
3200 {"630", "Motorola PowerPC 630", bfd_arch_powerpc
,
3201 bfd_mach_ppc_630
, &tdesc_powerpc_64
},
3202 {"a35", "PowerPC A35", bfd_arch_powerpc
,
3203 bfd_mach_ppc_a35
, &tdesc_powerpc_64
},
3204 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc
,
3205 bfd_mach_ppc_rs64ii
, &tdesc_powerpc_64
},
3206 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc
,
3207 bfd_mach_ppc_rs64iii
, &tdesc_powerpc_64
},
3209 /* FIXME: I haven't checked the register sets of the following. */
3210 {"rs1", "IBM POWER RS1", bfd_arch_rs6000
,
3211 bfd_mach_rs6k_rs1
, &tdesc_rs6000
},
3212 {"rsc", "IBM POWER RSC", bfd_arch_rs6000
,
3213 bfd_mach_rs6k_rsc
, &tdesc_rs6000
},
3214 {"rs2", "IBM POWER RS2", bfd_arch_rs6000
,
3215 bfd_mach_rs6k_rs2
, &tdesc_rs6000
},
3217 {0, 0, (enum bfd_architecture
) 0, 0, 0}
3220 /* Return the variant corresponding to architecture ARCH and machine number
3221 MACH. If no such variant exists, return null. */
3223 static const struct variant
*
3224 find_variant_by_arch (enum bfd_architecture arch
, unsigned long mach
)
3226 const struct variant
*v
;
3228 for (v
= variants
; v
->name
; v
++)
3229 if (arch
== v
->arch
&& mach
== v
->mach
)
3236 gdb_print_insn_powerpc (bfd_vma memaddr
, disassemble_info
*info
)
3238 if (info
->endian
== BFD_ENDIAN_BIG
)
3239 return print_insn_big_powerpc (memaddr
, info
);
3241 return print_insn_little_powerpc (memaddr
, info
);
3245 rs6000_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
3247 return frame_unwind_register_unsigned (next_frame
,
3248 gdbarch_pc_regnum (gdbarch
));
3251 static struct frame_id
3252 rs6000_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3254 return frame_id_build (get_frame_register_unsigned
3255 (this_frame
, gdbarch_sp_regnum (gdbarch
)),
3256 get_frame_pc (this_frame
));
3259 struct rs6000_frame_cache
3262 CORE_ADDR initial_sp
;
3263 struct trad_frame_saved_reg
*saved_regs
;
3265 /* Set BASE_P to true if this frame cache is properly initialized.
3266 Otherwise set to false because some registers or memory cannot
3269 /* Cache PC for building unavailable frame. */
3273 static struct rs6000_frame_cache
*
3274 rs6000_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3276 struct rs6000_frame_cache
*cache
;
3277 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3278 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3279 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3280 struct rs6000_framedata fdata
;
3281 int wordsize
= tdep
->wordsize
;
3282 CORE_ADDR func
= 0, pc
= 0;
3284 if ((*this_cache
) != NULL
)
3285 return (struct rs6000_frame_cache
*) (*this_cache
);
3286 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
3287 (*this_cache
) = cache
;
3289 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3293 func
= get_frame_func (this_frame
);
3295 pc
= get_frame_pc (this_frame
);
3296 skip_prologue (gdbarch
, func
, pc
, &fdata
);
3298 /* Figure out the parent's stack pointer. */
3300 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
3301 address of the current frame. Things might be easier if the
3302 ->frame pointed to the outer-most address of the frame. In
3303 the mean time, the address of the prev frame is used as the
3304 base address of this frame. */
3305 cache
->base
= get_frame_register_unsigned
3306 (this_frame
, gdbarch_sp_regnum (gdbarch
));
3308 CATCH (ex
, RETURN_MASK_ERROR
)
3310 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
3311 throw_exception (ex
);
3312 return (struct rs6000_frame_cache
*) (*this_cache
);
3316 /* If the function appears to be frameless, check a couple of likely
3317 indicators that we have simply failed to find the frame setup.
3318 Two common cases of this are missing symbols (i.e.
3319 get_frame_func returns the wrong address or 0), and assembly
3320 stubs which have a fast exit path but set up a frame on the slow
3323 If the LR appears to return to this function, then presume that
3324 we have an ABI compliant frame that we failed to find. */
3325 if (fdata
.frameless
&& fdata
.lr_offset
== 0)
3330 saved_lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
3331 if (func
== 0 && saved_lr
== pc
)
3335 CORE_ADDR saved_func
= get_pc_function_start (saved_lr
);
3336 if (func
== saved_func
)
3342 fdata
.frameless
= 0;
3343 fdata
.lr_offset
= tdep
->lr_frame_offset
;
3347 if (!fdata
.frameless
)
3349 /* Frameless really means stackless. */
3352 if (safe_read_memory_unsigned_integer (cache
->base
, wordsize
,
3353 byte_order
, &backchain
))
3354 cache
->base
= (CORE_ADDR
) backchain
;
3357 trad_frame_set_value (cache
->saved_regs
,
3358 gdbarch_sp_regnum (gdbarch
), cache
->base
);
3360 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
3361 All fpr's from saved_fpr to fp31 are saved. */
3363 if (fdata
.saved_fpr
>= 0)
3366 CORE_ADDR fpr_addr
= cache
->base
+ fdata
.fpr_offset
;
3368 /* If skip_prologue says floating-point registers were saved,
3369 but the current architecture has no floating-point registers,
3370 then that's strange. But we have no indices to even record
3371 the addresses under, so we just ignore it. */
3372 if (ppc_floating_point_unit_p (gdbarch
))
3373 for (i
= fdata
.saved_fpr
; i
< ppc_num_fprs
; i
++)
3375 cache
->saved_regs
[tdep
->ppc_fp0_regnum
+ i
].addr
= fpr_addr
;
3380 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
3381 All gpr's from saved_gpr to gpr31 are saved (except during the
3384 if (fdata
.saved_gpr
>= 0)
3387 CORE_ADDR gpr_addr
= cache
->base
+ fdata
.gpr_offset
;
3388 for (i
= fdata
.saved_gpr
; i
< ppc_num_gprs
; i
++)
3390 if (fdata
.gpr_mask
& (1U << i
))
3391 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= gpr_addr
;
3392 gpr_addr
+= wordsize
;
3396 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
3397 All vr's from saved_vr to vr31 are saved. */
3398 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
3400 if (fdata
.saved_vr
>= 0)
3403 CORE_ADDR vr_addr
= cache
->base
+ fdata
.vr_offset
;
3404 for (i
= fdata
.saved_vr
; i
< 32; i
++)
3406 cache
->saved_regs
[tdep
->ppc_vr0_regnum
+ i
].addr
= vr_addr
;
3407 vr_addr
+= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
3412 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
3413 All vr's from saved_ev to ev31 are saved. ????? */
3414 if (tdep
->ppc_ev0_regnum
!= -1)
3416 if (fdata
.saved_ev
>= 0)
3419 CORE_ADDR ev_addr
= cache
->base
+ fdata
.ev_offset
;
3420 CORE_ADDR off
= (byte_order
== BFD_ENDIAN_BIG
? 4 : 0);
3422 for (i
= fdata
.saved_ev
; i
< ppc_num_gprs
; i
++)
3424 cache
->saved_regs
[tdep
->ppc_ev0_regnum
+ i
].addr
= ev_addr
;
3425 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= ev_addr
+ off
;
3426 ev_addr
+= register_size (gdbarch
, tdep
->ppc_ev0_regnum
);
3431 /* If != 0, fdata.cr_offset is the offset from the frame that
3433 if (fdata
.cr_offset
!= 0)
3434 cache
->saved_regs
[tdep
->ppc_cr_regnum
].addr
3435 = cache
->base
+ fdata
.cr_offset
;
3437 /* If != 0, fdata.lr_offset is the offset from the frame that
3439 if (fdata
.lr_offset
!= 0)
3440 cache
->saved_regs
[tdep
->ppc_lr_regnum
].addr
3441 = cache
->base
+ fdata
.lr_offset
;
3442 else if (fdata
.lr_register
!= -1)
3443 cache
->saved_regs
[tdep
->ppc_lr_regnum
].realreg
= fdata
.lr_register
;
3444 /* The PC is found in the link register. */
3445 cache
->saved_regs
[gdbarch_pc_regnum (gdbarch
)] =
3446 cache
->saved_regs
[tdep
->ppc_lr_regnum
];
3448 /* If != 0, fdata.vrsave_offset is the offset from the frame that
3449 holds the VRSAVE. */
3450 if (fdata
.vrsave_offset
!= 0)
3451 cache
->saved_regs
[tdep
->ppc_vrsave_regnum
].addr
3452 = cache
->base
+ fdata
.vrsave_offset
;
3454 if (fdata
.alloca_reg
< 0)
3455 /* If no alloca register used, then fi->frame is the value of the
3456 %sp for this frame, and it is good enough. */
3458 = get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
3461 = get_frame_register_unsigned (this_frame
, fdata
.alloca_reg
);
3468 rs6000_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3469 struct frame_id
*this_id
)
3471 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3476 (*this_id
) = frame_id_build_unavailable_stack (info
->pc
);
3480 /* This marks the outermost frame. */
3481 if (info
->base
== 0)
3484 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3487 static struct value
*
3488 rs6000_frame_prev_register (struct frame_info
*this_frame
,
3489 void **this_cache
, int regnum
)
3491 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3493 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3496 static const struct frame_unwind rs6000_frame_unwind
=
3499 default_frame_unwind_stop_reason
,
3500 rs6000_frame_this_id
,
3501 rs6000_frame_prev_register
,
3503 default_frame_sniffer
3506 /* Allocate and initialize a frame cache for an epilogue frame.
3507 SP is restored and prev-PC is stored in LR. */
3509 static struct rs6000_frame_cache
*
3510 rs6000_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3512 struct rs6000_frame_cache
*cache
;
3513 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3514 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3517 return (struct rs6000_frame_cache
*) *this_cache
;
3519 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
3520 (*this_cache
) = cache
;
3521 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3525 /* At this point the stack looks as if we just entered the
3526 function, and the return address is stored in LR. */
3529 sp
= get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
3530 lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
3533 cache
->initial_sp
= sp
;
3535 trad_frame_set_value (cache
->saved_regs
,
3536 gdbarch_pc_regnum (gdbarch
), lr
);
3538 CATCH (ex
, RETURN_MASK_ERROR
)
3540 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
3541 throw_exception (ex
);
3548 /* Implementation of frame_unwind.this_id, as defined in frame_unwind.h.
3549 Return the frame ID of an epilogue frame. */
3552 rs6000_epilogue_frame_this_id (struct frame_info
*this_frame
,
3553 void **this_cache
, struct frame_id
*this_id
)
3556 struct rs6000_frame_cache
*info
=
3557 rs6000_epilogue_frame_cache (this_frame
, this_cache
);
3559 pc
= get_frame_func (this_frame
);
3560 if (info
->base
== 0)
3561 (*this_id
) = frame_id_build_unavailable_stack (pc
);
3563 (*this_id
) = frame_id_build (info
->base
, pc
);
3566 /* Implementation of frame_unwind.prev_register, as defined in frame_unwind.h.
3567 Return the register value of REGNUM in previous frame. */
3569 static struct value
*
3570 rs6000_epilogue_frame_prev_register (struct frame_info
*this_frame
,
3571 void **this_cache
, int regnum
)
3573 struct rs6000_frame_cache
*info
=
3574 rs6000_epilogue_frame_cache (this_frame
, this_cache
);
3575 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3578 /* Implementation of frame_unwind.sniffer, as defined in frame_unwind.h.
3579 Check whether this an epilogue frame. */
3582 rs6000_epilogue_frame_sniffer (const struct frame_unwind
*self
,
3583 struct frame_info
*this_frame
,
3584 void **this_prologue_cache
)
3586 if (frame_relative_level (this_frame
) == 0)
3587 return rs6000_in_function_epilogue_frame_p (this_frame
,
3588 get_frame_arch (this_frame
),
3589 get_frame_pc (this_frame
));
3594 /* Frame unwinder for epilogue frame. This is required for reverse step-over
3595 a function without debug information. */
3597 static const struct frame_unwind rs6000_epilogue_frame_unwind
=
3600 default_frame_unwind_stop_reason
,
3601 rs6000_epilogue_frame_this_id
, rs6000_epilogue_frame_prev_register
,
3603 rs6000_epilogue_frame_sniffer
3608 rs6000_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
3610 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3612 return info
->initial_sp
;
3615 static const struct frame_base rs6000_frame_base
= {
3616 &rs6000_frame_unwind
,
3617 rs6000_frame_base_address
,
3618 rs6000_frame_base_address
,
3619 rs6000_frame_base_address
3622 static const struct frame_base
*
3623 rs6000_frame_base_sniffer (struct frame_info
*this_frame
)
3625 return &rs6000_frame_base
;
3628 /* DWARF-2 frame support. Used to handle the detection of
3629 clobbered registers during function calls. */
3632 ppc_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
3633 struct dwarf2_frame_state_reg
*reg
,
3634 struct frame_info
*this_frame
)
3636 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3638 /* PPC32 and PPC64 ABI's are the same regarding volatile and
3639 non-volatile registers. We will use the same code for both. */
3641 /* Call-saved GP registers. */
3642 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 14
3643 && regnum
<= tdep
->ppc_gp0_regnum
+ 31)
3644 || (regnum
== tdep
->ppc_gp0_regnum
+ 1))
3645 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3647 /* Call-clobbered GP registers. */
3648 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 3
3649 && regnum
<= tdep
->ppc_gp0_regnum
+ 12)
3650 || (regnum
== tdep
->ppc_gp0_regnum
))
3651 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3653 /* Deal with FP registers, if supported. */
3654 if (tdep
->ppc_fp0_regnum
>= 0)
3656 /* Call-saved FP registers. */
3657 if ((regnum
>= tdep
->ppc_fp0_regnum
+ 14
3658 && regnum
<= tdep
->ppc_fp0_regnum
+ 31))
3659 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3661 /* Call-clobbered FP registers. */
3662 if ((regnum
>= tdep
->ppc_fp0_regnum
3663 && regnum
<= tdep
->ppc_fp0_regnum
+ 13))
3664 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3667 /* Deal with ALTIVEC registers, if supported. */
3668 if (tdep
->ppc_vr0_regnum
> 0 && tdep
->ppc_vrsave_regnum
> 0)
3670 /* Call-saved Altivec registers. */
3671 if ((regnum
>= tdep
->ppc_vr0_regnum
+ 20
3672 && regnum
<= tdep
->ppc_vr0_regnum
+ 31)
3673 || regnum
== tdep
->ppc_vrsave_regnum
)
3674 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3676 /* Call-clobbered Altivec registers. */
3677 if ((regnum
>= tdep
->ppc_vr0_regnum
3678 && regnum
<= tdep
->ppc_vr0_regnum
+ 19))
3679 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3682 /* Handle PC register and Stack Pointer correctly. */
3683 if (regnum
== gdbarch_pc_regnum (gdbarch
))
3684 reg
->how
= DWARF2_FRAME_REG_RA
;
3685 else if (regnum
== gdbarch_sp_regnum (gdbarch
))
3686 reg
->how
= DWARF2_FRAME_REG_CFA
;
3690 /* Return true if a .gnu_attributes section exists in BFD and it
3691 indicates we are using SPE extensions OR if a .PPC.EMB.apuinfo
3692 section exists in BFD and it indicates that SPE extensions are in
3693 use. Check the .gnu.attributes section first, as the binary might be
3694 compiled for SPE, but not actually using SPE instructions. */
3697 bfd_uses_spe_extensions (bfd
*abfd
)
3700 gdb_byte
*contents
= NULL
;
3710 /* Using Tag_GNU_Power_ABI_Vector here is a bit of a hack, as the user
3711 could be using the SPE vector abi without actually using any spe
3712 bits whatsoever. But it's close enough for now. */
3713 vector_abi
= bfd_elf_get_obj_attr_int (abfd
, OBJ_ATTR_GNU
,
3714 Tag_GNU_Power_ABI_Vector
);
3715 if (vector_abi
== 3)
3719 sect
= bfd_get_section_by_name (abfd
, ".PPC.EMB.apuinfo");
3723 size
= bfd_get_section_size (sect
);
3724 contents
= (gdb_byte
*) xmalloc (size
);
3725 if (!bfd_get_section_contents (abfd
, sect
, contents
, 0, size
))
3731 /* Parse the .PPC.EMB.apuinfo section. The layout is as follows:
3737 char name[name_len rounded up to 4-byte alignment];
3738 char data[data_len];
3741 Technically, there's only supposed to be one such structure in a
3742 given apuinfo section, but the linker is not always vigilant about
3743 merging apuinfo sections from input files. Just go ahead and parse
3744 them all, exiting early when we discover the binary uses SPE
3747 It's not specified in what endianness the information in this
3748 section is stored. Assume that it's the endianness of the BFD. */
3752 unsigned int name_len
;
3753 unsigned int data_len
;
3756 /* If we can't read the first three fields, we're done. */
3760 name_len
= bfd_get_32 (abfd
, ptr
);
3761 name_len
= (name_len
+ 3) & ~3U; /* Round to 4 bytes. */
3762 data_len
= bfd_get_32 (abfd
, ptr
+ 4);
3763 type
= bfd_get_32 (abfd
, ptr
+ 8);
3766 /* The name must be "APUinfo\0". */
3768 && strcmp ((const char *) ptr
, "APUinfo") != 0)
3772 /* The type must be 2. */
3776 /* The data is stored as a series of uint32. The upper half of
3777 each uint32 indicates the particular APU used and the lower
3778 half indicates the revision of that APU. We just care about
3781 /* Not 4-byte quantities. */
3787 unsigned int apuinfo
= bfd_get_32 (abfd
, ptr
);
3788 unsigned int apu
= apuinfo
>> 16;
3792 /* The SPE APU is 0x100; the SPEFP APU is 0x101. Accept
3794 if (apu
== 0x100 || apu
== 0x101)
3809 /* These are macros for parsing instruction fields (I.1.6.28) */
3811 #define PPC_FIELD(value, from, len) \
3812 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
3813 #define PPC_SEXT(v, bs) \
3814 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
3815 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
3816 - ((CORE_ADDR) 1 << ((bs) - 1)))
3817 #define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
3818 #define PPC_EXTOP(insn) PPC_FIELD (insn, 21, 10)
3819 #define PPC_RT(insn) PPC_FIELD (insn, 6, 5)
3820 #define PPC_RS(insn) PPC_FIELD (insn, 6, 5)
3821 #define PPC_RA(insn) PPC_FIELD (insn, 11, 5)
3822 #define PPC_RB(insn) PPC_FIELD (insn, 16, 5)
3823 #define PPC_NB(insn) PPC_FIELD (insn, 16, 5)
3824 #define PPC_VRT(insn) PPC_FIELD (insn, 6, 5)
3825 #define PPC_FRT(insn) PPC_FIELD (insn, 6, 5)
3826 #define PPC_SPR(insn) (PPC_FIELD (insn, 11, 5) \
3827 | (PPC_FIELD (insn, 16, 5) << 5))
3828 #define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
3829 #define PPC_T(insn) PPC_FIELD (insn, 6, 5)
3830 #define PPC_D(insn) PPC_SEXT (PPC_FIELD (insn, 16, 16), 16)
3831 #define PPC_DS(insn) PPC_SEXT (PPC_FIELD (insn, 16, 14), 14)
3832 #define PPC_DQ(insn) PPC_SEXT (PPC_FIELD (insn, 16, 12), 12)
3833 #define PPC_BIT(insn,n) ((insn & (1 << (31 - (n)))) ? 1 : 0)
3834 #define PPC_OE(insn) PPC_BIT (insn, 21)
3835 #define PPC_RC(insn) PPC_BIT (insn, 31)
3836 #define PPC_Rc(insn) PPC_BIT (insn, 21)
3837 #define PPC_LK(insn) PPC_BIT (insn, 31)
3838 #define PPC_TX(insn) PPC_BIT (insn, 31)
3839 #define PPC_LEV(insn) PPC_FIELD (insn, 20, 7)
3841 #define PPC_XT(insn) ((PPC_TX (insn) << 5) | PPC_T (insn))
3842 #define PPC_XER_NB(xer) (xer & 0x7f)
3844 /* Record Vector-Scalar Registers.
3845 For VSR less than 32, it's represented by an FPR and an VSR-upper register.
3846 Otherwise, it's just a VR register. Record them accordingly. */
3849 ppc_record_vsr (struct regcache
*regcache
, struct gdbarch_tdep
*tdep
, int vsr
)
3851 if (vsr
< 0 || vsr
>= 64)
3856 if (tdep
->ppc_vr0_regnum
>= 0)
3857 record_full_arch_list_add_reg (regcache
, tdep
->ppc_vr0_regnum
+ vsr
- 32);
3861 if (tdep
->ppc_fp0_regnum
>= 0)
3862 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fp0_regnum
+ vsr
);
3863 if (tdep
->ppc_vsr0_upper_regnum
>= 0)
3864 record_full_arch_list_add_reg (regcache
,
3865 tdep
->ppc_vsr0_upper_regnum
+ vsr
);
3871 /* Parse and record instructions primary opcode-4 at ADDR.
3872 Return 0 if successful. */
3875 ppc_process_record_op4 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3876 CORE_ADDR addr
, uint32_t insn
)
3878 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3879 int ext
= PPC_FIELD (insn
, 21, 11);
3880 int vra
= PPC_FIELD (insn
, 11, 5);
3884 case 32: /* Vector Multiply-High-Add Signed Halfword Saturate */
3885 case 33: /* Vector Multiply-High-Round-Add Signed Halfword Saturate */
3886 case 39: /* Vector Multiply-Sum Unsigned Halfword Saturate */
3887 case 41: /* Vector Multiply-Sum Signed Halfword Saturate */
3888 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
3890 case 42: /* Vector Select */
3891 case 43: /* Vector Permute */
3892 case 59: /* Vector Permute Right-indexed */
3893 case 44: /* Vector Shift Left Double by Octet Immediate */
3894 case 45: /* Vector Permute and Exclusive-OR */
3895 case 60: /* Vector Add Extended Unsigned Quadword Modulo */
3896 case 61: /* Vector Add Extended & write Carry Unsigned Quadword */
3897 case 62: /* Vector Subtract Extended Unsigned Quadword Modulo */
3898 case 63: /* Vector Subtract Extended & write Carry Unsigned Quadword */
3899 case 34: /* Vector Multiply-Low-Add Unsigned Halfword Modulo */
3900 case 35: /* Vector Multiply-Sum Unsigned Doubleword Modulo */
3901 case 36: /* Vector Multiply-Sum Unsigned Byte Modulo */
3902 case 37: /* Vector Multiply-Sum Mixed Byte Modulo */
3903 case 38: /* Vector Multiply-Sum Unsigned Halfword Modulo */
3904 case 40: /* Vector Multiply-Sum Signed Halfword Modulo */
3905 case 46: /* Vector Multiply-Add Single-Precision */
3906 case 47: /* Vector Negative Multiply-Subtract Single-Precision */
3907 record_full_arch_list_add_reg (regcache
,
3908 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
3911 case 48: /* Multiply-Add High Doubleword */
3912 case 49: /* Multiply-Add High Doubleword Unsigned */
3913 case 51: /* Multiply-Add Low Doubleword */
3914 record_full_arch_list_add_reg (regcache
,
3915 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
3919 switch ((ext
& 0x1ff))
3922 if (vra
!= 0 /* Decimal Convert To Signed Quadword */
3923 && vra
!= 2 /* Decimal Convert From Signed Quadword */
3924 && vra
!= 4 /* Decimal Convert To Zoned */
3925 && vra
!= 5 /* Decimal Convert To National */
3926 && vra
!= 6 /* Decimal Convert From Zoned */
3927 && vra
!= 7 /* Decimal Convert From National */
3928 && vra
!= 31) /* Decimal Set Sign */
3930 /* 5.16 Decimal Integer Arithmetic Instructions */
3931 case 1: /* Decimal Add Modulo */
3932 case 65: /* Decimal Subtract Modulo */
3934 case 193: /* Decimal Shift */
3935 case 129: /* Decimal Unsigned Shift */
3936 case 449: /* Decimal Shift and Round */
3938 case 257: /* Decimal Truncate */
3939 case 321: /* Decimal Unsigned Truncate */
3941 /* Bit-21 should be set. */
3942 if (!PPC_BIT (insn
, 21))
3945 record_full_arch_list_add_reg (regcache
,
3946 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
3947 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
3951 /* Bit-21 is used for RC */
3952 switch (ext
& 0x3ff)
3954 case 6: /* Vector Compare Equal To Unsigned Byte */
3955 case 70: /* Vector Compare Equal To Unsigned Halfword */
3956 case 134: /* Vector Compare Equal To Unsigned Word */
3957 case 199: /* Vector Compare Equal To Unsigned Doubleword */
3958 case 774: /* Vector Compare Greater Than Signed Byte */
3959 case 838: /* Vector Compare Greater Than Signed Halfword */
3960 case 902: /* Vector Compare Greater Than Signed Word */
3961 case 967: /* Vector Compare Greater Than Signed Doubleword */
3962 case 518: /* Vector Compare Greater Than Unsigned Byte */
3963 case 646: /* Vector Compare Greater Than Unsigned Word */
3964 case 582: /* Vector Compare Greater Than Unsigned Halfword */
3965 case 711: /* Vector Compare Greater Than Unsigned Doubleword */
3966 case 966: /* Vector Compare Bounds Single-Precision */
3967 case 198: /* Vector Compare Equal To Single-Precision */
3968 case 454: /* Vector Compare Greater Than or Equal To Single-Precision */
3969 case 710: /* Vector Compare Greater Than Single-Precision */
3970 case 7: /* Vector Compare Not Equal Byte */
3971 case 71: /* Vector Compare Not Equal Halfword */
3972 case 135: /* Vector Compare Not Equal Word */
3973 case 263: /* Vector Compare Not Equal or Zero Byte */
3974 case 327: /* Vector Compare Not Equal or Zero Halfword */
3975 case 391: /* Vector Compare Not Equal or Zero Word */
3977 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
3978 record_full_arch_list_add_reg (regcache
,
3979 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
3987 case 0: /* Vector Count Leading Zero Least-Significant Bits
3989 case 1: /* Vector Count Trailing Zero Least-Significant Bits
3991 record_full_arch_list_add_reg (regcache
,
3992 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
3995 case 6: /* Vector Negate Word */
3996 case 7: /* Vector Negate Doubleword */
3997 case 8: /* Vector Parity Byte Word */
3998 case 9: /* Vector Parity Byte Doubleword */
3999 case 10: /* Vector Parity Byte Quadword */
4000 case 16: /* Vector Extend Sign Byte To Word */
4001 case 17: /* Vector Extend Sign Halfword To Word */
4002 case 24: /* Vector Extend Sign Byte To Doubleword */
4003 case 25: /* Vector Extend Sign Halfword To Doubleword */
4004 case 26: /* Vector Extend Sign Word To Doubleword */
4005 case 28: /* Vector Count Trailing Zeros Byte */
4006 case 29: /* Vector Count Trailing Zeros Halfword */
4007 case 30: /* Vector Count Trailing Zeros Word */
4008 case 31: /* Vector Count Trailing Zeros Doubleword */
4009 record_full_arch_list_add_reg (regcache
,
4010 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4017 case 142: /* Vector Pack Unsigned Halfword Unsigned Saturate */
4018 case 206: /* Vector Pack Unsigned Word Unsigned Saturate */
4019 case 270: /* Vector Pack Signed Halfword Unsigned Saturate */
4020 case 334: /* Vector Pack Signed Word Unsigned Saturate */
4021 case 398: /* Vector Pack Signed Halfword Signed Saturate */
4022 case 462: /* Vector Pack Signed Word Signed Saturate */
4023 case 1230: /* Vector Pack Unsigned Doubleword Unsigned Saturate */
4024 case 1358: /* Vector Pack Signed Doubleword Unsigned Saturate */
4025 case 1486: /* Vector Pack Signed Doubleword Signed Saturate */
4026 case 512: /* Vector Add Unsigned Byte Saturate */
4027 case 576: /* Vector Add Unsigned Halfword Saturate */
4028 case 640: /* Vector Add Unsigned Word Saturate */
4029 case 768: /* Vector Add Signed Byte Saturate */
4030 case 832: /* Vector Add Signed Halfword Saturate */
4031 case 896: /* Vector Add Signed Word Saturate */
4032 case 1536: /* Vector Subtract Unsigned Byte Saturate */
4033 case 1600: /* Vector Subtract Unsigned Halfword Saturate */
4034 case 1664: /* Vector Subtract Unsigned Word Saturate */
4035 case 1792: /* Vector Subtract Signed Byte Saturate */
4036 case 1856: /* Vector Subtract Signed Halfword Saturate */
4037 case 1920: /* Vector Subtract Signed Word Saturate */
4039 case 1544: /* Vector Sum across Quarter Unsigned Byte Saturate */
4040 case 1800: /* Vector Sum across Quarter Signed Byte Saturate */
4041 case 1608: /* Vector Sum across Quarter Signed Halfword Saturate */
4042 case 1672: /* Vector Sum across Half Signed Word Saturate */
4043 case 1928: /* Vector Sum across Signed Word Saturate */
4044 case 970: /* Vector Convert To Signed Fixed-Point Word Saturate */
4045 case 906: /* Vector Convert To Unsigned Fixed-Point Word Saturate */
4046 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
4048 case 12: /* Vector Merge High Byte */
4049 case 14: /* Vector Pack Unsigned Halfword Unsigned Modulo */
4050 case 76: /* Vector Merge High Halfword */
4051 case 78: /* Vector Pack Unsigned Word Unsigned Modulo */
4052 case 140: /* Vector Merge High Word */
4053 case 268: /* Vector Merge Low Byte */
4054 case 332: /* Vector Merge Low Halfword */
4055 case 396: /* Vector Merge Low Word */
4056 case 526: /* Vector Unpack High Signed Byte */
4057 case 590: /* Vector Unpack High Signed Halfword */
4058 case 654: /* Vector Unpack Low Signed Byte */
4059 case 718: /* Vector Unpack Low Signed Halfword */
4060 case 782: /* Vector Pack Pixel */
4061 case 846: /* Vector Unpack High Pixel */
4062 case 974: /* Vector Unpack Low Pixel */
4063 case 1102: /* Vector Pack Unsigned Doubleword Unsigned Modulo */
4064 case 1614: /* Vector Unpack High Signed Word */
4065 case 1676: /* Vector Merge Odd Word */
4066 case 1742: /* Vector Unpack Low Signed Word */
4067 case 1932: /* Vector Merge Even Word */
4068 case 524: /* Vector Splat Byte */
4069 case 588: /* Vector Splat Halfword */
4070 case 652: /* Vector Splat Word */
4071 case 780: /* Vector Splat Immediate Signed Byte */
4072 case 844: /* Vector Splat Immediate Signed Halfword */
4073 case 908: /* Vector Splat Immediate Signed Word */
4074 case 452: /* Vector Shift Left */
4075 case 708: /* Vector Shift Right */
4076 case 1036: /* Vector Shift Left by Octet */
4077 case 1100: /* Vector Shift Right by Octet */
4078 case 0: /* Vector Add Unsigned Byte Modulo */
4079 case 64: /* Vector Add Unsigned Halfword Modulo */
4080 case 128: /* Vector Add Unsigned Word Modulo */
4081 case 192: /* Vector Add Unsigned Doubleword Modulo */
4082 case 256: /* Vector Add Unsigned Quadword Modulo */
4083 case 320: /* Vector Add & write Carry Unsigned Quadword */
4084 case 384: /* Vector Add and Write Carry-Out Unsigned Word */
4085 case 8: /* Vector Multiply Odd Unsigned Byte */
4086 case 72: /* Vector Multiply Odd Unsigned Halfword */
4087 case 136: /* Vector Multiply Odd Unsigned Word */
4088 case 264: /* Vector Multiply Odd Signed Byte */
4089 case 328: /* Vector Multiply Odd Signed Halfword */
4090 case 392: /* Vector Multiply Odd Signed Word */
4091 case 520: /* Vector Multiply Even Unsigned Byte */
4092 case 584: /* Vector Multiply Even Unsigned Halfword */
4093 case 648: /* Vector Multiply Even Unsigned Word */
4094 case 776: /* Vector Multiply Even Signed Byte */
4095 case 840: /* Vector Multiply Even Signed Halfword */
4096 case 904: /* Vector Multiply Even Signed Word */
4097 case 137: /* Vector Multiply Unsigned Word Modulo */
4098 case 1024: /* Vector Subtract Unsigned Byte Modulo */
4099 case 1088: /* Vector Subtract Unsigned Halfword Modulo */
4100 case 1152: /* Vector Subtract Unsigned Word Modulo */
4101 case 1216: /* Vector Subtract Unsigned Doubleword Modulo */
4102 case 1280: /* Vector Subtract Unsigned Quadword Modulo */
4103 case 1344: /* Vector Subtract & write Carry Unsigned Quadword */
4104 case 1408: /* Vector Subtract and Write Carry-Out Unsigned Word */
4105 case 1282: /* Vector Average Signed Byte */
4106 case 1346: /* Vector Average Signed Halfword */
4107 case 1410: /* Vector Average Signed Word */
4108 case 1026: /* Vector Average Unsigned Byte */
4109 case 1090: /* Vector Average Unsigned Halfword */
4110 case 1154: /* Vector Average Unsigned Word */
4111 case 258: /* Vector Maximum Signed Byte */
4112 case 322: /* Vector Maximum Signed Halfword */
4113 case 386: /* Vector Maximum Signed Word */
4114 case 450: /* Vector Maximum Signed Doubleword */
4115 case 2: /* Vector Maximum Unsigned Byte */
4116 case 66: /* Vector Maximum Unsigned Halfword */
4117 case 130: /* Vector Maximum Unsigned Word */
4118 case 194: /* Vector Maximum Unsigned Doubleword */
4119 case 770: /* Vector Minimum Signed Byte */
4120 case 834: /* Vector Minimum Signed Halfword */
4121 case 898: /* Vector Minimum Signed Word */
4122 case 962: /* Vector Minimum Signed Doubleword */
4123 case 514: /* Vector Minimum Unsigned Byte */
4124 case 578: /* Vector Minimum Unsigned Halfword */
4125 case 642: /* Vector Minimum Unsigned Word */
4126 case 706: /* Vector Minimum Unsigned Doubleword */
4127 case 1028: /* Vector Logical AND */
4128 case 1668: /* Vector Logical Equivalent */
4129 case 1092: /* Vector Logical AND with Complement */
4130 case 1412: /* Vector Logical NAND */
4131 case 1348: /* Vector Logical OR with Complement */
4132 case 1156: /* Vector Logical OR */
4133 case 1284: /* Vector Logical NOR */
4134 case 1220: /* Vector Logical XOR */
4135 case 4: /* Vector Rotate Left Byte */
4136 case 132: /* Vector Rotate Left Word VX-form */
4137 case 68: /* Vector Rotate Left Halfword */
4138 case 196: /* Vector Rotate Left Doubleword */
4139 case 260: /* Vector Shift Left Byte */
4140 case 388: /* Vector Shift Left Word */
4141 case 324: /* Vector Shift Left Halfword */
4142 case 1476: /* Vector Shift Left Doubleword */
4143 case 516: /* Vector Shift Right Byte */
4144 case 644: /* Vector Shift Right Word */
4145 case 580: /* Vector Shift Right Halfword */
4146 case 1732: /* Vector Shift Right Doubleword */
4147 case 772: /* Vector Shift Right Algebraic Byte */
4148 case 900: /* Vector Shift Right Algebraic Word */
4149 case 836: /* Vector Shift Right Algebraic Halfword */
4150 case 964: /* Vector Shift Right Algebraic Doubleword */
4151 case 10: /* Vector Add Single-Precision */
4152 case 74: /* Vector Subtract Single-Precision */
4153 case 1034: /* Vector Maximum Single-Precision */
4154 case 1098: /* Vector Minimum Single-Precision */
4155 case 842: /* Vector Convert From Signed Fixed-Point Word */
4156 case 778: /* Vector Convert From Unsigned Fixed-Point Word */
4157 case 714: /* Vector Round to Single-Precision Integer toward -Infinity */
4158 case 522: /* Vector Round to Single-Precision Integer Nearest */
4159 case 650: /* Vector Round to Single-Precision Integer toward +Infinity */
4160 case 586: /* Vector Round to Single-Precision Integer toward Zero */
4161 case 394: /* Vector 2 Raised to the Exponent Estimate Floating-Point */
4162 case 458: /* Vector Log Base 2 Estimate Floating-Point */
4163 case 266: /* Vector Reciprocal Estimate Single-Precision */
4164 case 330: /* Vector Reciprocal Square Root Estimate Single-Precision */
4165 case 1288: /* Vector AES Cipher */
4166 case 1289: /* Vector AES Cipher Last */
4167 case 1352: /* Vector AES Inverse Cipher */
4168 case 1353: /* Vector AES Inverse Cipher Last */
4169 case 1480: /* Vector AES SubBytes */
4170 case 1730: /* Vector SHA-512 Sigma Doubleword */
4171 case 1666: /* Vector SHA-256 Sigma Word */
4172 case 1032: /* Vector Polynomial Multiply-Sum Byte */
4173 case 1160: /* Vector Polynomial Multiply-Sum Word */
4174 case 1096: /* Vector Polynomial Multiply-Sum Halfword */
4175 case 1224: /* Vector Polynomial Multiply-Sum Doubleword */
4176 case 1292: /* Vector Gather Bits by Bytes by Doubleword */
4177 case 1794: /* Vector Count Leading Zeros Byte */
4178 case 1858: /* Vector Count Leading Zeros Halfword */
4179 case 1922: /* Vector Count Leading Zeros Word */
4180 case 1986: /* Vector Count Leading Zeros Doubleword */
4181 case 1795: /* Vector Population Count Byte */
4182 case 1859: /* Vector Population Count Halfword */
4183 case 1923: /* Vector Population Count Word */
4184 case 1987: /* Vector Population Count Doubleword */
4185 case 1356: /* Vector Bit Permute Quadword */
4186 case 1484: /* Vector Bit Permute Doubleword */
4187 case 513: /* Vector Multiply-by-10 Unsigned Quadword */
4188 case 1: /* Vector Multiply-by-10 & write Carry Unsigned
4190 case 577: /* Vector Multiply-by-10 Extended Unsigned Quadword */
4191 case 65: /* Vector Multiply-by-10 Extended & write Carry
4192 Unsigned Quadword */
4193 case 1027: /* Vector Absolute Difference Unsigned Byte */
4194 case 1091: /* Vector Absolute Difference Unsigned Halfword */
4195 case 1155: /* Vector Absolute Difference Unsigned Word */
4196 case 1796: /* Vector Shift Right Variable */
4197 case 1860: /* Vector Shift Left Variable */
4198 case 133: /* Vector Rotate Left Word then Mask Insert */
4199 case 197: /* Vector Rotate Left Doubleword then Mask Insert */
4200 case 389: /* Vector Rotate Left Word then AND with Mask */
4201 case 453: /* Vector Rotate Left Doubleword then AND with Mask */
4202 case 525: /* Vector Extract Unsigned Byte */
4203 case 589: /* Vector Extract Unsigned Halfword */
4204 case 653: /* Vector Extract Unsigned Word */
4205 case 717: /* Vector Extract Doubleword */
4206 case 781: /* Vector Insert Byte */
4207 case 845: /* Vector Insert Halfword */
4208 case 909: /* Vector Insert Word */
4209 case 973: /* Vector Insert Doubleword */
4210 record_full_arch_list_add_reg (regcache
,
4211 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4214 case 1549: /* Vector Extract Unsigned Byte Left-Indexed */
4215 case 1613: /* Vector Extract Unsigned Halfword Left-Indexed */
4216 case 1677: /* Vector Extract Unsigned Word Left-Indexed */
4217 case 1805: /* Vector Extract Unsigned Byte Right-Indexed */
4218 case 1869: /* Vector Extract Unsigned Halfword Right-Indexed */
4219 case 1933: /* Vector Extract Unsigned Word Right-Indexed */
4220 record_full_arch_list_add_reg (regcache
,
4221 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4224 case 1604: /* Move To Vector Status and Control Register */
4225 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
4227 case 1540: /* Move From Vector Status and Control Register */
4228 record_full_arch_list_add_reg (regcache
,
4229 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4231 case 833: /* Decimal Copy Sign */
4232 record_full_arch_list_add_reg (regcache
,
4233 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4234 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4238 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4239 "at %s, 4-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4243 /* Parse and record instructions of primary opcode-19 at ADDR.
4244 Return 0 if successful. */
4247 ppc_process_record_op19 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4248 CORE_ADDR addr
, uint32_t insn
)
4250 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4251 int ext
= PPC_EXTOP (insn
);
4253 switch (ext
& 0x01f)
4255 case 2: /* Add PC Immediate Shifted */
4256 record_full_arch_list_add_reg (regcache
,
4257 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4263 case 0: /* Move Condition Register Field */
4264 case 33: /* Condition Register NOR */
4265 case 129: /* Condition Register AND with Complement */
4266 case 193: /* Condition Register XOR */
4267 case 225: /* Condition Register NAND */
4268 case 257: /* Condition Register AND */
4269 case 289: /* Condition Register Equivalent */
4270 case 417: /* Condition Register OR with Complement */
4271 case 449: /* Condition Register OR */
4272 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4275 case 16: /* Branch Conditional */
4276 case 560: /* Branch Conditional to Branch Target Address Register */
4277 if ((PPC_BO (insn
) & 0x4) == 0)
4278 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
4280 case 528: /* Branch Conditional to Count Register */
4282 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
4285 case 150: /* Instruction Synchronize */
4290 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4291 "at %s, 19-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4295 /* Parse and record instructions of primary opcode-31 at ADDR.
4296 Return 0 if successful. */
4299 ppc_process_record_op31 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4300 CORE_ADDR addr
, uint32_t insn
)
4302 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4303 int ext
= PPC_EXTOP (insn
);
4305 CORE_ADDR at_dcsz
, ea
= 0;
4306 ULONGEST rb
, ra
, xer
;
4309 /* These instructions have OE bit. */
4310 switch (ext
& 0x1ff)
4312 /* These write RT and XER. Update CR if RC is set. */
4313 case 8: /* Subtract from carrying */
4314 case 10: /* Add carrying */
4315 case 136: /* Subtract from extended */
4316 case 138: /* Add extended */
4317 case 200: /* Subtract from zero extended */
4318 case 202: /* Add to zero extended */
4319 case 232: /* Subtract from minus one extended */
4320 case 234: /* Add to minus one extended */
4321 /* CA is always altered, but SO/OV are only altered when OE=1.
4322 In any case, XER is always altered. */
4323 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4325 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4326 record_full_arch_list_add_reg (regcache
,
4327 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4330 /* These write RT. Update CR if RC is set and update XER if OE is set. */
4331 case 40: /* Subtract from */
4332 case 104: /* Negate */
4333 case 233: /* Multiply low doubleword */
4334 case 235: /* Multiply low word */
4336 case 393: /* Divide Doubleword Extended Unsigned */
4337 case 395: /* Divide Word Extended Unsigned */
4338 case 425: /* Divide Doubleword Extended */
4339 case 427: /* Divide Word Extended */
4340 case 457: /* Divide Doubleword Unsigned */
4341 case 459: /* Divide Word Unsigned */
4342 case 489: /* Divide Doubleword */
4343 case 491: /* Divide Word */
4345 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4347 case 9: /* Multiply High Doubleword Unsigned */
4348 case 11: /* Multiply High Word Unsigned */
4349 case 73: /* Multiply High Doubleword */
4350 case 75: /* Multiply High Word */
4352 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4353 record_full_arch_list_add_reg (regcache
,
4354 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4358 if ((ext
& 0x1f) == 15)
4360 /* Integer Select. bit[16:20] is used for BC. */
4361 record_full_arch_list_add_reg (regcache
,
4362 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4366 if ((ext
& 0xff) == 170)
4368 /* Add Extended using alternate carry bits */
4369 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4370 record_full_arch_list_add_reg (regcache
,
4371 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4377 case 78: /* Determine Leftmost Zero Byte */
4379 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4380 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4381 record_full_arch_list_add_reg (regcache
,
4382 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4385 /* These only write RT. */
4386 case 19: /* Move from condition register */
4387 /* Move From One Condition Register Field */
4388 case 74: /* Add and Generate Sixes */
4389 case 74 | 0x200: /* Add and Generate Sixes (bit-21 dont-care) */
4390 case 302: /* Move From Branch History Rolling Buffer */
4391 case 339: /* Move From Special Purpose Register */
4392 case 371: /* Move From Time Base [Phased-Out] */
4393 case 309: /* Load Doubleword Monitored Indexed */
4394 case 128: /* Set Boolean */
4395 case 755: /* Deliver A Random Number */
4396 record_full_arch_list_add_reg (regcache
,
4397 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4400 /* These only write to RA. */
4401 case 51: /* Move From VSR Doubleword */
4402 case 115: /* Move From VSR Word and Zero */
4403 case 122: /* Population count bytes */
4404 case 378: /* Population count words */
4405 case 506: /* Population count doublewords */
4406 case 154: /* Parity Word */
4407 case 186: /* Parity Doubleword */
4408 case 252: /* Bit Permute Doubleword */
4409 case 282: /* Convert Declets To Binary Coded Decimal */
4410 case 314: /* Convert Binary Coded Decimal To Declets */
4411 case 508: /* Compare bytes */
4412 case 307: /* Move From VSR Lower Doubleword */
4413 record_full_arch_list_add_reg (regcache
,
4414 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4417 /* These write CR and optional RA. */
4418 case 792: /* Shift Right Algebraic Word */
4419 case 794: /* Shift Right Algebraic Doubleword */
4420 case 824: /* Shift Right Algebraic Word Immediate */
4421 case 826: /* Shift Right Algebraic Doubleword Immediate (413) */
4422 case 826 | 1: /* Shift Right Algebraic Doubleword Immediate (413) */
4423 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4424 record_full_arch_list_add_reg (regcache
,
4425 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4427 case 0: /* Compare */
4428 case 32: /* Compare logical */
4429 case 144: /* Move To Condition Register Fields */
4430 /* Move To One Condition Register Field */
4431 case 192: /* Compare Ranged Byte */
4432 case 224: /* Compare Equal Byte */
4433 case 576: /* Move XER to CR Extended */
4434 case 902: /* Paste (should always fail due to single-stepping and
4435 the memory location might not be accessible, so
4437 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4440 /* These write to RT. Update RA if 'update indexed.' */
4441 case 53: /* Load Doubleword with Update Indexed */
4442 case 119: /* Load Byte and Zero with Update Indexed */
4443 case 311: /* Load Halfword and Zero with Update Indexed */
4444 case 55: /* Load Word and Zero with Update Indexed */
4445 case 375: /* Load Halfword Algebraic with Update Indexed */
4446 case 373: /* Load Word Algebraic with Update Indexed */
4447 record_full_arch_list_add_reg (regcache
,
4448 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4450 case 21: /* Load Doubleword Indexed */
4451 case 52: /* Load Byte And Reserve Indexed */
4452 case 116: /* Load Halfword And Reserve Indexed */
4453 case 20: /* Load Word And Reserve Indexed */
4454 case 84: /* Load Doubleword And Reserve Indexed */
4455 case 87: /* Load Byte and Zero Indexed */
4456 case 279: /* Load Halfword and Zero Indexed */
4457 case 23: /* Load Word and Zero Indexed */
4458 case 343: /* Load Halfword Algebraic Indexed */
4459 case 341: /* Load Word Algebraic Indexed */
4460 case 790: /* Load Halfword Byte-Reverse Indexed */
4461 case 534: /* Load Word Byte-Reverse Indexed */
4462 case 532: /* Load Doubleword Byte-Reverse Indexed */
4463 case 582: /* Load Word Atomic */
4464 case 614: /* Load Doubleword Atomic */
4465 case 265: /* Modulo Unsigned Doubleword */
4466 case 777: /* Modulo Signed Doubleword */
4467 case 267: /* Modulo Unsigned Word */
4468 case 779: /* Modulo Signed Word */
4469 record_full_arch_list_add_reg (regcache
,
4470 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4473 case 597: /* Load String Word Immediate */
4474 case 533: /* Load String Word Indexed */
4483 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &xer
);
4484 nr
= PPC_XER_NB (xer
);
4489 /* If n=0, the contents of register RT are undefined. */
4493 for (i
= 0; i
< nr
; i
++)
4494 record_full_arch_list_add_reg (regcache
,
4495 tdep
->ppc_gp0_regnum
4496 + ((PPC_RT (insn
) + i
) & 0x1f));
4499 case 276: /* Load Quadword And Reserve Indexed */
4500 tmp
= tdep
->ppc_gp0_regnum
+ (PPC_RT (insn
) & ~1);
4501 record_full_arch_list_add_reg (regcache
, tmp
);
4502 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
4505 /* These write VRT. */
4506 case 6: /* Load Vector for Shift Left Indexed */
4507 case 38: /* Load Vector for Shift Right Indexed */
4508 case 7: /* Load Vector Element Byte Indexed */
4509 case 39: /* Load Vector Element Halfword Indexed */
4510 case 71: /* Load Vector Element Word Indexed */
4511 case 103: /* Load Vector Indexed */
4512 case 359: /* Load Vector Indexed LRU */
4513 record_full_arch_list_add_reg (regcache
,
4514 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4517 /* These write FRT. Update RA if 'update indexed.' */
4518 case 567: /* Load Floating-Point Single with Update Indexed */
4519 case 631: /* Load Floating-Point Double with Update Indexed */
4520 record_full_arch_list_add_reg (regcache
,
4521 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4523 case 535: /* Load Floating-Point Single Indexed */
4524 case 599: /* Load Floating-Point Double Indexed */
4525 case 855: /* Load Floating-Point as Integer Word Algebraic Indexed */
4526 case 887: /* Load Floating-Point as Integer Word and Zero Indexed */
4527 record_full_arch_list_add_reg (regcache
,
4528 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4531 case 791: /* Load Floating-Point Double Pair Indexed */
4532 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
4533 record_full_arch_list_add_reg (regcache
, tmp
);
4534 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
4537 case 179: /* Move To VSR Doubleword */
4538 case 211: /* Move To VSR Word Algebraic */
4539 case 243: /* Move To VSR Word and Zero */
4540 case 588: /* Load VSX Scalar Doubleword Indexed */
4541 case 524: /* Load VSX Scalar Single-Precision Indexed */
4542 case 76: /* Load VSX Scalar as Integer Word Algebraic Indexed */
4543 case 12: /* Load VSX Scalar as Integer Word and Zero Indexed */
4544 case 844: /* Load VSX Vector Doubleword*2 Indexed */
4545 case 332: /* Load VSX Vector Doubleword & Splat Indexed */
4546 case 780: /* Load VSX Vector Word*4 Indexed */
4547 case 268: /* Load VSX Vector Indexed */
4548 case 364: /* Load VSX Vector Word & Splat Indexed */
4549 case 812: /* Load VSX Vector Halfword*8 Indexed */
4550 case 876: /* Load VSX Vector Byte*16 Indexed */
4551 case 269: /* Load VSX Vector with Length */
4552 case 301: /* Load VSX Vector Left-justified with Length */
4553 case 781: /* Load VSX Scalar as Integer Byte & Zero Indexed */
4554 case 813: /* Load VSX Scalar as Integer Halfword & Zero Indexed */
4555 case 403: /* Move To VSR Word & Splat */
4556 case 435: /* Move To VSR Double Doubleword */
4557 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
4560 /* These write RA. Update CR if RC is set. */
4561 case 24: /* Shift Left Word */
4562 case 26: /* Count Leading Zeros Word */
4563 case 27: /* Shift Left Doubleword */
4565 case 58: /* Count Leading Zeros Doubleword */
4566 case 60: /* AND with Complement */
4568 case 284: /* Equivalent */
4570 case 476: /* NAND */
4571 case 412: /* OR with Complement */
4573 case 536: /* Shift Right Word */
4574 case 539: /* Shift Right Doubleword */
4575 case 922: /* Extend Sign Halfword */
4576 case 954: /* Extend Sign Byte */
4577 case 986: /* Extend Sign Word */
4578 case 538: /* Count Trailing Zeros Word */
4579 case 570: /* Count Trailing Zeros Doubleword */
4580 case 890: /* Extend-Sign Word and Shift Left Immediate (445) */
4581 case 890 | 1: /* Extend-Sign Word and Shift Left Immediate (445) */
4583 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4584 record_full_arch_list_add_reg (regcache
,
4585 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4589 case 181: /* Store Doubleword with Update Indexed */
4590 case 183: /* Store Word with Update Indexed */
4591 case 247: /* Store Byte with Update Indexed */
4592 case 439: /* Store Half Word with Update Indexed */
4593 case 695: /* Store Floating-Point Single with Update Indexed */
4594 case 759: /* Store Floating-Point Double with Update Indexed */
4595 record_full_arch_list_add_reg (regcache
,
4596 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4598 case 135: /* Store Vector Element Byte Indexed */
4599 case 167: /* Store Vector Element Halfword Indexed */
4600 case 199: /* Store Vector Element Word Indexed */
4601 case 231: /* Store Vector Indexed */
4602 case 487: /* Store Vector Indexed LRU */
4603 case 716: /* Store VSX Scalar Doubleword Indexed */
4604 case 140: /* Store VSX Scalar as Integer Word Indexed */
4605 case 652: /* Store VSX Scalar Single-Precision Indexed */
4606 case 972: /* Store VSX Vector Doubleword*2 Indexed */
4607 case 908: /* Store VSX Vector Word*4 Indexed */
4608 case 149: /* Store Doubleword Indexed */
4609 case 151: /* Store Word Indexed */
4610 case 215: /* Store Byte Indexed */
4611 case 407: /* Store Half Word Indexed */
4612 case 694: /* Store Byte Conditional Indexed */
4613 case 726: /* Store Halfword Conditional Indexed */
4614 case 150: /* Store Word Conditional Indexed */
4615 case 214: /* Store Doubleword Conditional Indexed */
4616 case 182: /* Store Quadword Conditional Indexed */
4617 case 662: /* Store Word Byte-Reverse Indexed */
4618 case 918: /* Store Halfword Byte-Reverse Indexed */
4619 case 660: /* Store Doubleword Byte-Reverse Indexed */
4620 case 663: /* Store Floating-Point Single Indexed */
4621 case 727: /* Store Floating-Point Double Indexed */
4622 case 919: /* Store Floating-Point Double Pair Indexed */
4623 case 983: /* Store Floating-Point as Integer Word Indexed */
4624 case 396: /* Store VSX Vector Indexed */
4625 case 940: /* Store VSX Vector Halfword*8 Indexed */
4626 case 1004: /* Store VSX Vector Byte*16 Indexed */
4627 case 909: /* Store VSX Scalar as Integer Byte Indexed */
4628 case 941: /* Store VSX Scalar as Integer Halfword Indexed */
4629 if (ext
== 694 || ext
== 726 || ext
== 150 || ext
== 214 || ext
== 182)
4630 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4633 if (PPC_RA (insn
) != 0)
4634 regcache_raw_read_unsigned (regcache
,
4635 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4636 regcache_raw_read_unsigned (regcache
,
4637 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
4642 case 183: /* Store Word with Update Indexed */
4643 case 199: /* Store Vector Element Word Indexed */
4644 case 140: /* Store VSX Scalar as Integer Word Indexed */
4645 case 652: /* Store VSX Scalar Single-Precision Indexed */
4646 case 151: /* Store Word Indexed */
4647 case 150: /* Store Word Conditional Indexed */
4648 case 662: /* Store Word Byte-Reverse Indexed */
4649 case 663: /* Store Floating-Point Single Indexed */
4650 case 695: /* Store Floating-Point Single with Update Indexed */
4651 case 983: /* Store Floating-Point as Integer Word Indexed */
4654 case 247: /* Store Byte with Update Indexed */
4655 case 135: /* Store Vector Element Byte Indexed */
4656 case 215: /* Store Byte Indexed */
4657 case 694: /* Store Byte Conditional Indexed */
4658 case 909: /* Store VSX Scalar as Integer Byte Indexed */
4661 case 439: /* Store Halfword with Update Indexed */
4662 case 167: /* Store Vector Element Halfword Indexed */
4663 case 407: /* Store Halfword Indexed */
4664 case 726: /* Store Halfword Conditional Indexed */
4665 case 918: /* Store Halfword Byte-Reverse Indexed */
4666 case 941: /* Store VSX Scalar as Integer Halfword Indexed */
4669 case 181: /* Store Doubleword with Update Indexed */
4670 case 716: /* Store VSX Scalar Doubleword Indexed */
4671 case 149: /* Store Doubleword Indexed */
4672 case 214: /* Store Doubleword Conditional Indexed */
4673 case 660: /* Store Doubleword Byte-Reverse Indexed */
4674 case 727: /* Store Floating-Point Double Indexed */
4675 case 759: /* Store Floating-Point Double with Update Indexed */
4678 case 972: /* Store VSX Vector Doubleword*2 Indexed */
4679 case 908: /* Store VSX Vector Word*4 Indexed */
4680 case 182: /* Store Quadword Conditional Indexed */
4681 case 231: /* Store Vector Indexed */
4682 case 487: /* Store Vector Indexed LRU */
4683 case 919: /* Store Floating-Point Double Pair Indexed */
4684 case 396: /* Store VSX Vector Indexed */
4685 case 940: /* Store VSX Vector Halfword*8 Indexed */
4686 case 1004: /* Store VSX Vector Byte*16 Indexed */
4693 /* Align address for Store Vector instructions. */
4696 case 167: /* Store Vector Element Halfword Indexed */
4697 addr
= addr
& ~0x1ULL
;
4700 case 199: /* Store Vector Element Word Indexed */
4701 addr
= addr
& ~0x3ULL
;
4704 case 231: /* Store Vector Indexed */
4705 case 487: /* Store Vector Indexed LRU */
4706 addr
= addr
& ~0xfULL
;
4710 record_full_arch_list_add_mem (addr
, size
);
4713 case 397: /* Store VSX Vector with Length */
4714 case 429: /* Store VSX Vector Left-justified with Length */
4716 if (PPC_RA (insn
) != 0)
4717 regcache_raw_read_unsigned (regcache
,
4718 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4720 regcache_raw_read_unsigned (regcache
,
4721 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
4722 /* Store up to 16 bytes. */
4723 nb
= (rb
& 0xff) > 16 ? 16 : (rb
& 0xff);
4725 record_full_arch_list_add_mem (ea
, nb
);
4728 case 710: /* Store Word Atomic */
4729 case 742: /* Store Doubleword Atomic */
4731 if (PPC_RA (insn
) != 0)
4732 regcache_raw_read_unsigned (regcache
,
4733 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4737 case 710: /* Store Word Atomic */
4740 case 742: /* Store Doubleword Atomic */
4746 record_full_arch_list_add_mem (ea
, size
);
4749 case 725: /* Store String Word Immediate */
4751 if (PPC_RA (insn
) != 0)
4752 regcache_raw_read_unsigned (regcache
,
4753 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4760 record_full_arch_list_add_mem (ea
, nb
);
4764 case 661: /* Store String Word Indexed */
4766 if (PPC_RA (insn
) != 0)
4767 regcache_raw_read_unsigned (regcache
,
4768 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4771 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &xer
);
4772 nb
= PPC_XER_NB (xer
);
4776 regcache_raw_read_unsigned (regcache
,
4777 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
),
4780 record_full_arch_list_add_mem (ea
, nb
);
4785 case 467: /* Move To Special Purpose Register */
4786 switch (PPC_SPR (insn
))
4789 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4792 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
4795 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
4797 case 256: /* VRSAVE */
4798 record_full_arch_list_add_reg (regcache
, tdep
->ppc_vrsave_regnum
);
4804 case 147: /* Move To Split Little Endian */
4805 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ps_regnum
);
4808 case 512: /* Move to Condition Register from XER */
4809 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4810 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4813 case 4: /* Trap Word */
4814 case 68: /* Trap Doubleword */
4815 case 430: /* Clear BHRB */
4816 case 598: /* Synchronize */
4817 case 62: /* Wait for Interrupt */
4819 case 22: /* Instruction Cache Block Touch */
4820 case 854: /* Enforce In-order Execution of I/O */
4821 case 246: /* Data Cache Block Touch for Store */
4822 case 54: /* Data Cache Block Store */
4823 case 86: /* Data Cache Block Flush */
4824 case 278: /* Data Cache Block Touch */
4825 case 758: /* Data Cache Block Allocate */
4826 case 982: /* Instruction Cache Block Invalidate */
4827 case 774: /* Copy */
4828 case 838: /* CP_Abort */
4831 case 654: /* Transaction Begin */
4832 case 686: /* Transaction End */
4833 case 750: /* Transaction Suspend or Resume */
4834 case 782: /* Transaction Abort Word Conditional */
4835 case 814: /* Transaction Abort Doubleword Conditional */
4836 case 846: /* Transaction Abort Word Conditional Immediate */
4837 case 878: /* Transaction Abort Doubleword Conditional Immediate */
4838 case 910: /* Transaction Abort */
4839 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ps_regnum
);
4841 case 718: /* Transaction Check */
4842 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4845 case 1014: /* Data Cache Block set to Zero */
4846 if (target_auxv_search (¤t_target
, AT_DCACHEBSIZE
, &at_dcsz
) <= 0
4848 at_dcsz
= 128; /* Assume 128-byte cache line size (POWER8) */
4851 if (PPC_RA (insn
) != 0)
4852 regcache_raw_read_unsigned (regcache
,
4853 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4854 regcache_raw_read_unsigned (regcache
,
4855 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
4856 ea
= (ra
+ rb
) & ~((ULONGEST
) (at_dcsz
- 1));
4857 record_full_arch_list_add_mem (ea
, at_dcsz
);
4862 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4863 "at %s, 31-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4867 /* Parse and record instructions of primary opcode-59 at ADDR.
4868 Return 0 if successful. */
4871 ppc_process_record_op59 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4872 CORE_ADDR addr
, uint32_t insn
)
4874 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4875 int ext
= PPC_EXTOP (insn
);
4879 case 18: /* Floating Divide */
4880 case 20: /* Floating Subtract */
4881 case 21: /* Floating Add */
4882 case 22: /* Floating Square Root */
4883 case 24: /* Floating Reciprocal Estimate */
4884 case 25: /* Floating Multiply */
4885 case 26: /* Floating Reciprocal Square Root Estimate */
4886 case 28: /* Floating Multiply-Subtract */
4887 case 29: /* Floating Multiply-Add */
4888 case 30: /* Floating Negative Multiply-Subtract */
4889 case 31: /* Floating Negative Multiply-Add */
4890 record_full_arch_list_add_reg (regcache
,
4891 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4893 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4894 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4901 case 2: /* DFP Add */
4902 case 3: /* DFP Quantize */
4903 case 34: /* DFP Multiply */
4904 case 35: /* DFP Reround */
4905 case 67: /* DFP Quantize Immediate */
4906 case 99: /* DFP Round To FP Integer With Inexact */
4907 case 227: /* DFP Round To FP Integer Without Inexact */
4908 case 258: /* DFP Convert To DFP Long! */
4909 case 290: /* DFP Convert To Fixed */
4910 case 514: /* DFP Subtract */
4911 case 546: /* DFP Divide */
4912 case 770: /* DFP Round To DFP Short! */
4913 case 802: /* DFP Convert From Fixed */
4914 case 834: /* DFP Encode BCD To DPD */
4916 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4917 record_full_arch_list_add_reg (regcache
,
4918 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4919 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4922 case 130: /* DFP Compare Ordered */
4923 case 162: /* DFP Test Exponent */
4924 case 194: /* DFP Test Data Class */
4925 case 226: /* DFP Test Data Group */
4926 case 642: /* DFP Compare Unordered */
4927 case 674: /* DFP Test Significance */
4928 case 675: /* DFP Test Significance Immediate */
4929 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4930 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4933 case 66: /* DFP Shift Significand Left Immediate */
4934 case 98: /* DFP Shift Significand Right Immediate */
4935 case 322: /* DFP Decode DPD To BCD */
4936 case 354: /* DFP Extract Biased Exponent */
4937 case 866: /* DFP Insert Biased Exponent */
4938 record_full_arch_list_add_reg (regcache
,
4939 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4941 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4944 case 846: /* Floating Convert From Integer Doubleword Single */
4945 case 974: /* Floating Convert From Integer Doubleword Unsigned
4947 record_full_arch_list_add_reg (regcache
,
4948 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4950 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4951 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4956 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4957 "at %s, 59-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4961 /* Parse and record instructions of primary opcode-60 at ADDR.
4962 Return 0 if successful. */
4965 ppc_process_record_op60 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4966 CORE_ADDR addr
, uint32_t insn
)
4968 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4969 int ext
= PPC_EXTOP (insn
);
4973 case 0: /* VSX Scalar Add Single-Precision */
4974 case 32: /* VSX Scalar Add Double-Precision */
4975 case 24: /* VSX Scalar Divide Single-Precision */
4976 case 56: /* VSX Scalar Divide Double-Precision */
4977 case 176: /* VSX Scalar Copy Sign Double-Precision */
4978 case 33: /* VSX Scalar Multiply-Add Double-Precision */
4979 case 41: /* ditto */
4980 case 1: /* VSX Scalar Multiply-Add Single-Precision */
4982 case 160: /* VSX Scalar Maximum Double-Precision */
4983 case 168: /* VSX Scalar Minimum Double-Precision */
4984 case 49: /* VSX Scalar Multiply-Subtract Double-Precision */
4985 case 57: /* ditto */
4986 case 17: /* VSX Scalar Multiply-Subtract Single-Precision */
4987 case 25: /* ditto */
4988 case 48: /* VSX Scalar Multiply Double-Precision */
4989 case 16: /* VSX Scalar Multiply Single-Precision */
4990 case 161: /* VSX Scalar Negative Multiply-Add Double-Precision */
4991 case 169: /* ditto */
4992 case 129: /* VSX Scalar Negative Multiply-Add Single-Precision */
4993 case 137: /* ditto */
4994 case 177: /* VSX Scalar Negative Multiply-Subtract Double-Precision */
4995 case 185: /* ditto */
4996 case 145: /* VSX Scalar Negative Multiply-Subtract Single-Precision */
4997 case 153: /* ditto */
4998 case 40: /* VSX Scalar Subtract Double-Precision */
4999 case 8: /* VSX Scalar Subtract Single-Precision */
5000 case 96: /* VSX Vector Add Double-Precision */
5001 case 64: /* VSX Vector Add Single-Precision */
5002 case 120: /* VSX Vector Divide Double-Precision */
5003 case 88: /* VSX Vector Divide Single-Precision */
5004 case 97: /* VSX Vector Multiply-Add Double-Precision */
5005 case 105: /* ditto */
5006 case 65: /* VSX Vector Multiply-Add Single-Precision */
5007 case 73: /* ditto */
5008 case 224: /* VSX Vector Maximum Double-Precision */
5009 case 192: /* VSX Vector Maximum Single-Precision */
5010 case 232: /* VSX Vector Minimum Double-Precision */
5011 case 200: /* VSX Vector Minimum Single-Precision */
5012 case 113: /* VSX Vector Multiply-Subtract Double-Precision */
5013 case 121: /* ditto */
5014 case 81: /* VSX Vector Multiply-Subtract Single-Precision */
5015 case 89: /* ditto */
5016 case 112: /* VSX Vector Multiply Double-Precision */
5017 case 80: /* VSX Vector Multiply Single-Precision */
5018 case 225: /* VSX Vector Negative Multiply-Add Double-Precision */
5019 case 233: /* ditto */
5020 case 193: /* VSX Vector Negative Multiply-Add Single-Precision */
5021 case 201: /* ditto */
5022 case 241: /* VSX Vector Negative Multiply-Subtract Double-Precision */
5023 case 249: /* ditto */
5024 case 209: /* VSX Vector Negative Multiply-Subtract Single-Precision */
5025 case 217: /* ditto */
5026 case 104: /* VSX Vector Subtract Double-Precision */
5027 case 72: /* VSX Vector Subtract Single-Precision */
5028 case 128: /* VSX Scalar Maximum Type-C Double-Precision */
5029 case 136: /* VSX Scalar Minimum Type-C Double-Precision */
5030 case 144: /* VSX Scalar Maximum Type-J Double-Precision */
5031 case 152: /* VSX Scalar Minimum Type-J Double-Precision */
5032 case 3: /* VSX Scalar Compare Equal Double-Precision */
5033 case 11: /* VSX Scalar Compare Greater Than Double-Precision */
5034 case 19: /* VSX Scalar Compare Greater Than or Equal
5036 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5038 case 240: /* VSX Vector Copy Sign Double-Precision */
5039 case 208: /* VSX Vector Copy Sign Single-Precision */
5040 case 130: /* VSX Logical AND */
5041 case 138: /* VSX Logical AND with Complement */
5042 case 186: /* VSX Logical Equivalence */
5043 case 178: /* VSX Logical NAND */
5044 case 170: /* VSX Logical OR with Complement */
5045 case 162: /* VSX Logical NOR */
5046 case 146: /* VSX Logical OR */
5047 case 154: /* VSX Logical XOR */
5048 case 18: /* VSX Merge High Word */
5049 case 50: /* VSX Merge Low Word */
5050 case 10: /* VSX Permute Doubleword Immediate (DM=0) */
5051 case 10 | 0x20: /* VSX Permute Doubleword Immediate (DM=1) */
5052 case 10 | 0x40: /* VSX Permute Doubleword Immediate (DM=2) */
5053 case 10 | 0x60: /* VSX Permute Doubleword Immediate (DM=3) */
5054 case 2: /* VSX Shift Left Double by Word Immediate (SHW=0) */
5055 case 2 | 0x20: /* VSX Shift Left Double by Word Immediate (SHW=1) */
5056 case 2 | 0x40: /* VSX Shift Left Double by Word Immediate (SHW=2) */
5057 case 2 | 0x60: /* VSX Shift Left Double by Word Immediate (SHW=3) */
5058 case 216: /* VSX Vector Insert Exponent Single-Precision */
5059 case 248: /* VSX Vector Insert Exponent Double-Precision */
5060 case 26: /* VSX Vector Permute */
5061 case 58: /* VSX Vector Permute Right-indexed */
5062 case 213: /* VSX Vector Test Data Class Single-Precision (DC=0) */
5063 case 213 | 0x8: /* VSX Vector Test Data Class Single-Precision (DC=1) */
5064 case 245: /* VSX Vector Test Data Class Double-Precision (DC=0) */
5065 case 245 | 0x8: /* VSX Vector Test Data Class Double-Precision (DC=1) */
5066 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5069 case 61: /* VSX Scalar Test for software Divide Double-Precision */
5070 case 125: /* VSX Vector Test for software Divide Double-Precision */
5071 case 93: /* VSX Vector Test for software Divide Single-Precision */
5072 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5075 case 35: /* VSX Scalar Compare Unordered Double-Precision */
5076 case 43: /* VSX Scalar Compare Ordered Double-Precision */
5077 case 59: /* VSX Scalar Compare Exponents Double-Precision */
5078 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5079 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5083 switch ((ext
>> 2) & 0x7f) /* Mask out Rc-bit. */
5085 case 99: /* VSX Vector Compare Equal To Double-Precision */
5086 case 67: /* VSX Vector Compare Equal To Single-Precision */
5087 case 115: /* VSX Vector Compare Greater Than or
5088 Equal To Double-Precision */
5089 case 83: /* VSX Vector Compare Greater Than or
5090 Equal To Single-Precision */
5091 case 107: /* VSX Vector Compare Greater Than Double-Precision */
5092 case 75: /* VSX Vector Compare Greater Than Single-Precision */
5094 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5095 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5096 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5102 case 265: /* VSX Scalar round Double-Precision to
5103 Single-Precision and Convert to
5104 Single-Precision format */
5105 case 344: /* VSX Scalar truncate Double-Precision to
5106 Integer and Convert to Signed Integer
5107 Doubleword format with Saturate */
5108 case 88: /* VSX Scalar truncate Double-Precision to
5109 Integer and Convert to Signed Integer Word
5110 Format with Saturate */
5111 case 328: /* VSX Scalar truncate Double-Precision integer
5112 and Convert to Unsigned Integer Doubleword
5113 Format with Saturate */
5114 case 72: /* VSX Scalar truncate Double-Precision to
5115 Integer and Convert to Unsigned Integer Word
5116 Format with Saturate */
5117 case 329: /* VSX Scalar Convert Single-Precision to
5118 Double-Precision format */
5119 case 376: /* VSX Scalar Convert Signed Integer
5120 Doubleword to floating-point format and
5121 Round to Double-Precision format */
5122 case 312: /* VSX Scalar Convert Signed Integer
5123 Doubleword to floating-point format and
5124 round to Single-Precision */
5125 case 360: /* VSX Scalar Convert Unsigned Integer
5126 Doubleword to floating-point format and
5127 Round to Double-Precision format */
5128 case 296: /* VSX Scalar Convert Unsigned Integer
5129 Doubleword to floating-point format and
5130 Round to Single-Precision */
5131 case 73: /* VSX Scalar Round to Double-Precision Integer
5132 Using Round to Nearest Away */
5133 case 107: /* VSX Scalar Round to Double-Precision Integer
5134 Exact using Current rounding mode */
5135 case 121: /* VSX Scalar Round to Double-Precision Integer
5136 Using Round toward -Infinity */
5137 case 105: /* VSX Scalar Round to Double-Precision Integer
5138 Using Round toward +Infinity */
5139 case 89: /* VSX Scalar Round to Double-Precision Integer
5140 Using Round toward Zero */
5141 case 90: /* VSX Scalar Reciprocal Estimate Double-Precision */
5142 case 26: /* VSX Scalar Reciprocal Estimate Single-Precision */
5143 case 281: /* VSX Scalar Round to Single-Precision */
5144 case 74: /* VSX Scalar Reciprocal Square Root Estimate
5146 case 10: /* VSX Scalar Reciprocal Square Root Estimate
5148 case 75: /* VSX Scalar Square Root Double-Precision */
5149 case 11: /* VSX Scalar Square Root Single-Precision */
5150 case 393: /* VSX Vector round Double-Precision to
5151 Single-Precision and Convert to
5152 Single-Precision format */
5153 case 472: /* VSX Vector truncate Double-Precision to
5154 Integer and Convert to Signed Integer
5155 Doubleword format with Saturate */
5156 case 216: /* VSX Vector truncate Double-Precision to
5157 Integer and Convert to Signed Integer Word
5158 Format with Saturate */
5159 case 456: /* VSX Vector truncate Double-Precision to
5160 Integer and Convert to Unsigned Integer
5161 Doubleword format with Saturate */
5162 case 200: /* VSX Vector truncate Double-Precision to
5163 Integer and Convert to Unsigned Integer Word
5164 Format with Saturate */
5165 case 457: /* VSX Vector Convert Single-Precision to
5166 Double-Precision format */
5167 case 408: /* VSX Vector truncate Single-Precision to
5168 Integer and Convert to Signed Integer
5169 Doubleword format with Saturate */
5170 case 152: /* VSX Vector truncate Single-Precision to
5171 Integer and Convert to Signed Integer Word
5172 Format with Saturate */
5173 case 392: /* VSX Vector truncate Single-Precision to
5174 Integer and Convert to Unsigned Integer
5175 Doubleword format with Saturate */
5176 case 136: /* VSX Vector truncate Single-Precision to
5177 Integer and Convert to Unsigned Integer Word
5178 Format with Saturate */
5179 case 504: /* VSX Vector Convert and round Signed Integer
5180 Doubleword to Double-Precision format */
5181 case 440: /* VSX Vector Convert and round Signed Integer
5182 Doubleword to Single-Precision format */
5183 case 248: /* VSX Vector Convert Signed Integer Word to
5184 Double-Precision format */
5185 case 184: /* VSX Vector Convert and round Signed Integer
5186 Word to Single-Precision format */
5187 case 488: /* VSX Vector Convert and round Unsigned
5188 Integer Doubleword to Double-Precision format */
5189 case 424: /* VSX Vector Convert and round Unsigned
5190 Integer Doubleword to Single-Precision format */
5191 case 232: /* VSX Vector Convert and round Unsigned
5192 Integer Word to Double-Precision format */
5193 case 168: /* VSX Vector Convert and round Unsigned
5194 Integer Word to Single-Precision format */
5195 case 201: /* VSX Vector Round to Double-Precision
5196 Integer using round to Nearest Away */
5197 case 235: /* VSX Vector Round to Double-Precision
5198 Integer Exact using Current rounding mode */
5199 case 249: /* VSX Vector Round to Double-Precision
5200 Integer using round toward -Infinity */
5201 case 233: /* VSX Vector Round to Double-Precision
5202 Integer using round toward +Infinity */
5203 case 217: /* VSX Vector Round to Double-Precision
5204 Integer using round toward Zero */
5205 case 218: /* VSX Vector Reciprocal Estimate Double-Precision */
5206 case 154: /* VSX Vector Reciprocal Estimate Single-Precision */
5207 case 137: /* VSX Vector Round to Single-Precision Integer
5208 Using Round to Nearest Away */
5209 case 171: /* VSX Vector Round to Single-Precision Integer
5210 Exact Using Current rounding mode */
5211 case 185: /* VSX Vector Round to Single-Precision Integer
5212 Using Round toward -Infinity */
5213 case 169: /* VSX Vector Round to Single-Precision Integer
5214 Using Round toward +Infinity */
5215 case 153: /* VSX Vector Round to Single-Precision Integer
5216 Using round toward Zero */
5217 case 202: /* VSX Vector Reciprocal Square Root Estimate
5219 case 138: /* VSX Vector Reciprocal Square Root Estimate
5221 case 203: /* VSX Vector Square Root Double-Precision */
5222 case 139: /* VSX Vector Square Root Single-Precision */
5223 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5225 case 345: /* VSX Scalar Absolute Value Double-Precision */
5226 case 267: /* VSX Scalar Convert Scalar Single-Precision to
5227 Vector Single-Precision format Non-signalling */
5228 case 331: /* VSX Scalar Convert Single-Precision to
5229 Double-Precision format Non-signalling */
5230 case 361: /* VSX Scalar Negative Absolute Value Double-Precision */
5231 case 377: /* VSX Scalar Negate Double-Precision */
5232 case 473: /* VSX Vector Absolute Value Double-Precision */
5233 case 409: /* VSX Vector Absolute Value Single-Precision */
5234 case 489: /* VSX Vector Negative Absolute Value Double-Precision */
5235 case 425: /* VSX Vector Negative Absolute Value Single-Precision */
5236 case 505: /* VSX Vector Negate Double-Precision */
5237 case 441: /* VSX Vector Negate Single-Precision */
5238 case 164: /* VSX Splat Word */
5239 case 165: /* VSX Vector Extract Unsigned Word */
5240 case 181: /* VSX Vector Insert Word */
5241 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5244 case 298: /* VSX Scalar Test Data Class Single-Precision */
5245 case 362: /* VSX Scalar Test Data Class Double-Precision */
5246 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5248 case 106: /* VSX Scalar Test for software Square Root
5250 case 234: /* VSX Vector Test for software Square Root
5252 case 170: /* VSX Vector Test for software Square Root
5254 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5258 switch (PPC_FIELD (insn
, 11, 5))
5260 case 0: /* VSX Scalar Extract Exponent Double-Precision */
5261 case 1: /* VSX Scalar Extract Significand Double-Precision */
5262 record_full_arch_list_add_reg (regcache
,
5263 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5265 case 16: /* VSX Scalar Convert Half-Precision format to
5266 Double-Precision format */
5267 case 17: /* VSX Scalar round & Convert Double-Precision format
5268 to Half-Precision format */
5269 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5270 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5276 switch (PPC_FIELD (insn
, 11, 5))
5278 case 24: /* VSX Vector Convert Half-Precision format to
5279 Single-Precision format */
5280 case 25: /* VSX Vector round and Convert Single-Precision format
5281 to Half-Precision format */
5282 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5284 case 0: /* VSX Vector Extract Exponent Double-Precision */
5285 case 1: /* VSX Vector Extract Significand Double-Precision */
5286 case 7: /* VSX Vector Byte-Reverse Halfword */
5287 case 8: /* VSX Vector Extract Exponent Single-Precision */
5288 case 9: /* VSX Vector Extract Significand Single-Precision */
5289 case 15: /* VSX Vector Byte-Reverse Word */
5290 case 23: /* VSX Vector Byte-Reverse Doubleword */
5291 case 31: /* VSX Vector Byte-Reverse Quadword */
5292 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5300 case 360: /* VSX Vector Splat Immediate Byte */
5301 if (PPC_FIELD (insn
, 11, 2) == 0)
5303 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5307 case 918: /* VSX Scalar Insert Exponent Double-Precision */
5308 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5312 if (((ext
>> 3) & 0x3) == 3) /* VSX Select */
5314 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5318 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5319 "at %s, 60-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5323 /* Parse and record instructions of primary opcode-61 at ADDR.
5324 Return 0 if successful. */
5327 ppc_process_record_op61 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5328 CORE_ADDR addr
, uint32_t insn
)
5330 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5336 case 0: /* Store Floating-Point Double Pair */
5337 case 2: /* Store VSX Scalar Doubleword */
5338 case 3: /* Store VSX Scalar Single */
5339 if (PPC_RA (insn
) != 0)
5340 regcache_raw_read_unsigned (regcache
,
5341 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5343 ea
+= PPC_DS (insn
) << 2;
5346 case 0: /* Store Floating-Point Double Pair */
5349 case 2: /* Store VSX Scalar Doubleword */
5352 case 3: /* Store VSX Scalar Single */
5358 record_full_arch_list_add_mem (ea
, size
);
5364 case 1: /* Load VSX Vector */
5365 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5367 case 5: /* Store VSX Vector */
5368 if (PPC_RA (insn
) != 0)
5369 regcache_raw_read_unsigned (regcache
,
5370 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5372 ea
+= PPC_DQ (insn
) << 4;
5373 record_full_arch_list_add_mem (ea
, 16);
5377 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5378 "at %s.\n", insn
, paddress (gdbarch
, addr
));
5382 /* Parse and record instructions of primary opcode-63 at ADDR.
5383 Return 0 if successful. */
5386 ppc_process_record_op63 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5387 CORE_ADDR addr
, uint32_t insn
)
5389 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5390 int ext
= PPC_EXTOP (insn
);
5395 case 18: /* Floating Divide */
5396 case 20: /* Floating Subtract */
5397 case 21: /* Floating Add */
5398 case 22: /* Floating Square Root */
5399 case 24: /* Floating Reciprocal Estimate */
5400 case 25: /* Floating Multiply */
5401 case 26: /* Floating Reciprocal Square Root Estimate */
5402 case 28: /* Floating Multiply-Subtract */
5403 case 29: /* Floating Multiply-Add */
5404 case 30: /* Floating Negative Multiply-Subtract */
5405 case 31: /* Floating Negative Multiply-Add */
5406 record_full_arch_list_add_reg (regcache
,
5407 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5409 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5410 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5413 case 23: /* Floating Select */
5414 record_full_arch_list_add_reg (regcache
,
5415 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5417 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5423 case 5: /* VSX Scalar Round to Quad-Precision Integer */
5424 case 37: /* VSX Scalar Round Quad-Precision to Double-Extended
5426 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5427 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5433 case 2: /* DFP Add Quad */
5434 case 3: /* DFP Quantize Quad */
5435 case 34: /* DFP Multiply Quad */
5436 case 35: /* DFP Reround Quad */
5437 case 67: /* DFP Quantize Immediate Quad */
5438 case 99: /* DFP Round To FP Integer With Inexact Quad */
5439 case 227: /* DFP Round To FP Integer Without Inexact Quad */
5440 case 258: /* DFP Convert To DFP Extended Quad */
5441 case 514: /* DFP Subtract Quad */
5442 case 546: /* DFP Divide Quad */
5443 case 770: /* DFP Round To DFP Long Quad */
5444 case 802: /* DFP Convert From Fixed Quad */
5445 case 834: /* DFP Encode BCD To DPD Quad */
5447 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5448 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
5449 record_full_arch_list_add_reg (regcache
, tmp
);
5450 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5451 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5454 case 130: /* DFP Compare Ordered Quad */
5455 case 162: /* DFP Test Exponent Quad */
5456 case 194: /* DFP Test Data Class Quad */
5457 case 226: /* DFP Test Data Group Quad */
5458 case 642: /* DFP Compare Unordered Quad */
5459 case 674: /* DFP Test Significance Quad */
5460 case 675: /* DFP Test Significance Immediate Quad */
5461 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5462 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5465 case 66: /* DFP Shift Significand Left Immediate Quad */
5466 case 98: /* DFP Shift Significand Right Immediate Quad */
5467 case 322: /* DFP Decode DPD To BCD Quad */
5468 case 866: /* DFP Insert Biased Exponent Quad */
5469 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
5470 record_full_arch_list_add_reg (regcache
, tmp
);
5471 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5473 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5476 case 290: /* DFP Convert To Fixed Quad */
5477 record_full_arch_list_add_reg (regcache
,
5478 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5480 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5481 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5484 case 354: /* DFP Extract Biased Exponent Quad */
5485 record_full_arch_list_add_reg (regcache
,
5486 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5488 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5491 case 12: /* Floating Round to Single-Precision */
5492 case 14: /* Floating Convert To Integer Word */
5493 case 15: /* Floating Convert To Integer Word
5494 with round toward Zero */
5495 case 142: /* Floating Convert To Integer Word Unsigned */
5496 case 143: /* Floating Convert To Integer Word Unsigned
5497 with round toward Zero */
5498 case 392: /* Floating Round to Integer Nearest */
5499 case 424: /* Floating Round to Integer Toward Zero */
5500 case 456: /* Floating Round to Integer Plus */
5501 case 488: /* Floating Round to Integer Minus */
5502 case 814: /* Floating Convert To Integer Doubleword */
5503 case 815: /* Floating Convert To Integer Doubleword
5504 with round toward Zero */
5505 case 846: /* Floating Convert From Integer Doubleword */
5506 case 942: /* Floating Convert To Integer Doubleword Unsigned */
5507 case 943: /* Floating Convert To Integer Doubleword Unsigned
5508 with round toward Zero */
5509 case 974: /* Floating Convert From Integer Doubleword Unsigned */
5510 record_full_arch_list_add_reg (regcache
,
5511 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5513 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5514 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5518 switch (PPC_FIELD (insn
, 11, 5))
5520 case 1: /* Move From FPSCR & Clear Enables */
5521 case 20: /* Move From FPSCR Control & set DRN */
5522 case 21: /* Move From FPSCR Control & set DRN Immediate */
5523 case 22: /* Move From FPSCR Control & set RN */
5524 case 23: /* Move From FPSCR Control & set RN Immediate */
5525 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5526 case 0: /* Move From FPSCR */
5527 case 24: /* Move From FPSCR Lightweight */
5528 if (PPC_FIELD (insn
, 11, 5) == 0 && PPC_RC (insn
))
5529 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5530 record_full_arch_list_add_reg (regcache
,
5531 tdep
->ppc_fp0_regnum
5537 case 8: /* Floating Copy Sign */
5538 case 40: /* Floating Negate */
5539 case 72: /* Floating Move Register */
5540 case 136: /* Floating Negative Absolute Value */
5541 case 264: /* Floating Absolute Value */
5542 record_full_arch_list_add_reg (regcache
,
5543 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5545 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5548 case 838: /* Floating Merge Odd Word */
5549 case 966: /* Floating Merge Even Word */
5550 record_full_arch_list_add_reg (regcache
,
5551 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5554 case 38: /* Move To FPSCR Bit 1 */
5555 case 70: /* Move To FPSCR Bit 0 */
5556 case 134: /* Move To FPSCR Field Immediate */
5557 case 711: /* Move To FPSCR Fields */
5559 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5560 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5563 case 0: /* Floating Compare Unordered */
5564 case 32: /* Floating Compare Ordered */
5565 case 64: /* Move to Condition Register from FPSCR */
5566 case 132: /* VSX Scalar Compare Ordered Quad-Precision */
5567 case 164: /* VSX Scalar Compare Exponents Quad-Precision */
5568 case 644: /* VSX Scalar Compare Unordered Quad-Precision */
5569 case 708: /* VSX Scalar Test Data Class Quad-Precision */
5570 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5572 case 128: /* Floating Test for software Divide */
5573 case 160: /* Floating Test for software Square Root */
5574 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5577 case 4: /* VSX Scalar Add Quad-Precision */
5578 case 36: /* VSX Scalar Multiply Quad-Precision */
5579 case 388: /* VSX Scalar Multiply-Add Quad-Precision */
5580 case 420: /* VSX Scalar Multiply-Subtract Quad-Precision */
5581 case 452: /* VSX Scalar Negative Multiply-Add Quad-Precision */
5582 case 484: /* VSX Scalar Negative Multiply-Subtract
5584 case 516: /* VSX Scalar Subtract Quad-Precision */
5585 case 548: /* VSX Scalar Divide Quad-Precision */
5586 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5588 case 100: /* VSX Scalar Copy Sign Quad-Precision */
5589 case 868: /* VSX Scalar Insert Exponent Quad-Precision */
5590 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5594 switch (PPC_FIELD (insn
, 11, 5))
5596 case 27: /* VSX Scalar Square Root Quad-Precision */
5597 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5599 case 0: /* VSX Scalar Absolute Quad-Precision */
5600 case 2: /* VSX Scalar Extract Exponent Quad-Precision */
5601 case 8: /* VSX Scalar Negative Absolute Quad-Precision */
5602 case 16: /* VSX Scalar Negate Quad-Precision */
5603 case 18: /* VSX Scalar Extract Significand Quad-Precision */
5604 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5610 switch (PPC_FIELD (insn
, 11, 5))
5612 case 1: /* VSX Scalar truncate & Convert Quad-Precision format
5613 to Unsigned Word format */
5614 case 2: /* VSX Scalar Convert Unsigned Doubleword format to
5615 Quad-Precision format */
5616 case 9: /* VSX Scalar truncate & Convert Quad-Precision format
5617 to Signed Word format */
5618 case 10: /* VSX Scalar Convert Signed Doubleword format to
5619 Quad-Precision format */
5620 case 17: /* VSX Scalar truncate & Convert Quad-Precision format
5621 to Unsigned Doubleword format */
5622 case 20: /* VSX Scalar round & Convert Quad-Precision format to
5623 Double-Precision format */
5624 case 22: /* VSX Scalar Convert Double-Precision format to
5625 Quad-Precision format */
5626 case 25: /* VSX Scalar truncate & Convert Quad-Precision format
5627 to Signed Doubleword format */
5628 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5629 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5634 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5635 "at %s, 63-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5639 /* Parse the current instruction and record the values of the registers and
5640 memory that will be changed in current instruction to "record_arch_list".
5641 Return -1 if something wrong. */
5644 ppc_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5647 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5648 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5652 insn
= read_memory_unsigned_integer (addr
, 4, byte_order
);
5653 op6
= PPC_OP6 (insn
);
5657 case 2: /* Trap Doubleword Immediate */
5658 case 3: /* Trap Word Immediate */
5663 if (ppc_process_record_op4 (gdbarch
, regcache
, addr
, insn
) != 0)
5667 case 17: /* System call */
5668 if (PPC_LEV (insn
) != 0)
5671 if (tdep
->ppc_syscall_record
!= NULL
)
5673 if (tdep
->ppc_syscall_record (regcache
) != 0)
5678 printf_unfiltered (_("no syscall record support\n"));
5683 case 7: /* Multiply Low Immediate */
5684 record_full_arch_list_add_reg (regcache
,
5685 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5688 case 8: /* Subtract From Immediate Carrying */
5689 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5690 record_full_arch_list_add_reg (regcache
,
5691 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5694 case 10: /* Compare Logical Immediate */
5695 case 11: /* Compare Immediate */
5696 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5699 case 13: /* Add Immediate Carrying and Record */
5700 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5702 case 12: /* Add Immediate Carrying */
5703 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5705 case 14: /* Add Immediate */
5706 case 15: /* Add Immediate Shifted */
5707 record_full_arch_list_add_reg (regcache
,
5708 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5711 case 16: /* Branch Conditional */
5712 if ((PPC_BO (insn
) & 0x4) == 0)
5713 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
5715 case 18: /* Branch */
5717 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
5721 if (ppc_process_record_op19 (gdbarch
, regcache
, addr
, insn
) != 0)
5725 case 20: /* Rotate Left Word Immediate then Mask Insert */
5726 case 21: /* Rotate Left Word Immediate then AND with Mask */
5727 case 23: /* Rotate Left Word then AND with Mask */
5728 case 30: /* Rotate Left Doubleword Immediate then Clear Left */
5729 /* Rotate Left Doubleword Immediate then Clear Right */
5730 /* Rotate Left Doubleword Immediate then Clear */
5731 /* Rotate Left Doubleword then Clear Left */
5732 /* Rotate Left Doubleword then Clear Right */
5733 /* Rotate Left Doubleword Immediate then Mask Insert */
5735 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5736 record_full_arch_list_add_reg (regcache
,
5737 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5740 case 28: /* AND Immediate */
5741 case 29: /* AND Immediate Shifted */
5742 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5744 case 24: /* OR Immediate */
5745 case 25: /* OR Immediate Shifted */
5746 case 26: /* XOR Immediate */
5747 case 27: /* XOR Immediate Shifted */
5748 record_full_arch_list_add_reg (regcache
,
5749 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5753 if (ppc_process_record_op31 (gdbarch
, regcache
, addr
, insn
) != 0)
5757 case 33: /* Load Word and Zero with Update */
5758 case 35: /* Load Byte and Zero with Update */
5759 case 41: /* Load Halfword and Zero with Update */
5760 case 43: /* Load Halfword Algebraic with Update */
5761 record_full_arch_list_add_reg (regcache
,
5762 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5764 case 32: /* Load Word and Zero */
5765 case 34: /* Load Byte and Zero */
5766 case 40: /* Load Halfword and Zero */
5767 case 42: /* Load Halfword Algebraic */
5768 record_full_arch_list_add_reg (regcache
,
5769 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5772 case 46: /* Load Multiple Word */
5773 for (i
= PPC_RT (insn
); i
< 32; i
++)
5774 record_full_arch_list_add_reg (regcache
, tdep
->ppc_gp0_regnum
+ i
);
5777 case 56: /* Load Quadword */
5778 tmp
= tdep
->ppc_gp0_regnum
+ (PPC_RT (insn
) & ~1);
5779 record_full_arch_list_add_reg (regcache
, tmp
);
5780 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5783 case 49: /* Load Floating-Point Single with Update */
5784 case 51: /* Load Floating-Point Double with Update */
5785 record_full_arch_list_add_reg (regcache
,
5786 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5788 case 48: /* Load Floating-Point Single */
5789 case 50: /* Load Floating-Point Double */
5790 record_full_arch_list_add_reg (regcache
,
5791 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5794 case 47: /* Store Multiple Word */
5798 if (PPC_RA (insn
) != 0)
5799 regcache_raw_read_unsigned (regcache
,
5800 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5803 addr
+= PPC_D (insn
);
5804 record_full_arch_list_add_mem (addr
, 4 * (32 - PPC_RS (insn
)));
5808 case 37: /* Store Word with Update */
5809 case 39: /* Store Byte with Update */
5810 case 45: /* Store Halfword with Update */
5811 case 53: /* Store Floating-Point Single with Update */
5812 case 55: /* Store Floating-Point Double with Update */
5813 record_full_arch_list_add_reg (regcache
,
5814 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5816 case 36: /* Store Word */
5817 case 38: /* Store Byte */
5818 case 44: /* Store Halfword */
5819 case 52: /* Store Floating-Point Single */
5820 case 54: /* Store Floating-Point Double */
5825 if (PPC_RA (insn
) != 0)
5826 regcache_raw_read_unsigned (regcache
,
5827 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5829 addr
+= PPC_D (insn
);
5831 if (op6
== 36 || op6
== 37 || op6
== 52 || op6
== 53)
5833 else if (op6
== 54 || op6
== 55)
5835 else if (op6
== 44 || op6
== 45)
5837 else if (op6
== 38 || op6
== 39)
5842 record_full_arch_list_add_mem (addr
, size
);
5849 case 0: /* Load Floating-Point Double Pair */
5850 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_RT (insn
) & ~1);
5851 record_full_arch_list_add_reg (regcache
, tmp
);
5852 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5854 case 2: /* Load VSX Scalar Doubleword */
5855 case 3: /* Load VSX Scalar Single */
5856 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5863 case 58: /* Load Doubleword */
5864 /* Load Doubleword with Update */
5865 /* Load Word Algebraic */
5866 if (PPC_FIELD (insn
, 30, 2) > 2)
5869 record_full_arch_list_add_reg (regcache
,
5870 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5871 if (PPC_BIT (insn
, 31))
5872 record_full_arch_list_add_reg (regcache
,
5873 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5877 if (ppc_process_record_op59 (gdbarch
, regcache
, addr
, insn
) != 0)
5882 if (ppc_process_record_op60 (gdbarch
, regcache
, addr
, insn
) != 0)
5887 if (ppc_process_record_op61 (gdbarch
, regcache
, addr
, insn
) != 0)
5891 case 62: /* Store Doubleword */
5892 /* Store Doubleword with Update */
5893 /* Store Quadword with Update */
5897 int sub2
= PPC_FIELD (insn
, 30, 2);
5902 if (PPC_RA (insn
) != 0)
5903 regcache_raw_read_unsigned (regcache
,
5904 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5907 size
= (sub2
== 2) ? 16 : 8;
5909 addr
+= PPC_DS (insn
) << 2;
5910 record_full_arch_list_add_mem (addr
, size
);
5912 if (op6
== 62 && sub2
== 1)
5913 record_full_arch_list_add_reg (regcache
,
5914 tdep
->ppc_gp0_regnum
+
5921 if (ppc_process_record_op63 (gdbarch
, regcache
, addr
, insn
) != 0)
5927 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5928 "at %s, %d.\n", insn
, paddress (gdbarch
, addr
), op6
);
5932 if (record_full_arch_list_add_reg (regcache
, PPC_PC_REGNUM
))
5934 if (record_full_arch_list_add_end ())
5939 /* Initialize the current architecture based on INFO. If possible, re-use an
5940 architecture from ARCHES, which is a list of architectures already created
5941 during this debugging session.
5943 Called e.g. at program startup, when reading a core file, and when reading
5946 static struct gdbarch
*
5947 rs6000_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5949 struct gdbarch
*gdbarch
;
5950 struct gdbarch_tdep
*tdep
;
5951 int wordsize
, from_xcoff_exec
, from_elf_exec
;
5952 enum bfd_architecture arch
;
5955 enum auto_boolean soft_float_flag
= powerpc_soft_float_global
;
5957 enum powerpc_vector_abi vector_abi
= powerpc_vector_abi_global
;
5958 enum powerpc_elf_abi elf_abi
= POWERPC_ELF_AUTO
;
5959 int have_fpu
= 1, have_spe
= 0, have_mq
= 0, have_altivec
= 0, have_dfp
= 0,
5961 int tdesc_wordsize
= -1;
5962 const struct target_desc
*tdesc
= info
.target_desc
;
5963 struct tdesc_arch_data
*tdesc_data
= NULL
;
5964 int num_pseudoregs
= 0;
5967 /* INFO may refer to a binary that is not of the PowerPC architecture,
5968 e.g. when debugging a stand-alone SPE executable on a Cell/B.E. system.
5969 In this case, we must not attempt to infer properties of the (PowerPC
5970 side) of the target system from properties of that executable. Trust
5971 the target description instead. */
5973 && bfd_get_arch (info
.abfd
) != bfd_arch_powerpc
5974 && bfd_get_arch (info
.abfd
) != bfd_arch_rs6000
)
5977 from_xcoff_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
5978 bfd_get_flavour (info
.abfd
) == bfd_target_xcoff_flavour
;
5980 from_elf_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
5981 bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
;
5983 /* Check word size. If INFO is from a binary file, infer it from
5984 that, else choose a likely default. */
5985 if (from_xcoff_exec
)
5987 if (bfd_xcoff_is_xcoff64 (info
.abfd
))
5992 else if (from_elf_exec
)
5994 if (elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5999 else if (tdesc_has_registers (tdesc
))
6003 if (info
.bfd_arch_info
!= NULL
&& info
.bfd_arch_info
->bits_per_word
!= 0)
6004 wordsize
= (info
.bfd_arch_info
->bits_per_word
6005 / info
.bfd_arch_info
->bits_per_byte
);
6010 /* Get the architecture and machine from the BFD. */
6011 arch
= info
.bfd_arch_info
->arch
;
6012 mach
= info
.bfd_arch_info
->mach
;
6014 /* For e500 executables, the apuinfo section is of help here. Such
6015 section contains the identifier and revision number of each
6016 Application-specific Processing Unit that is present on the
6017 chip. The content of the section is determined by the assembler
6018 which looks at each instruction and determines which unit (and
6019 which version of it) can execute it. Grovel through the section
6020 looking for relevant e500 APUs. */
6022 if (bfd_uses_spe_extensions (info
.abfd
))
6024 arch
= info
.bfd_arch_info
->arch
;
6025 mach
= bfd_mach_ppc_e500
;
6026 bfd_default_set_arch_mach (&abfd
, arch
, mach
);
6027 info
.bfd_arch_info
= bfd_get_arch_info (&abfd
);
6030 /* Find a default target description which describes our register
6031 layout, if we do not already have one. */
6032 if (! tdesc_has_registers (tdesc
))
6034 const struct variant
*v
;
6036 /* Choose variant. */
6037 v
= find_variant_by_arch (arch
, mach
);
6044 gdb_assert (tdesc_has_registers (tdesc
));
6046 /* Check any target description for validity. */
6047 if (tdesc_has_registers (tdesc
))
6049 static const char *const gprs
[] = {
6050 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6051 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
6052 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
6053 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
6055 const struct tdesc_feature
*feature
;
6057 static const char *const msr_names
[] = { "msr", "ps" };
6058 static const char *const cr_names
[] = { "cr", "cnd" };
6059 static const char *const ctr_names
[] = { "ctr", "cnt" };
6061 feature
= tdesc_find_feature (tdesc
,
6062 "org.gnu.gdb.power.core");
6063 if (feature
== NULL
)
6066 tdesc_data
= tdesc_data_alloc ();
6069 for (i
= 0; i
< ppc_num_gprs
; i
++)
6070 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
, gprs
[i
]);
6071 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_PC_REGNUM
,
6073 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_LR_REGNUM
,
6075 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_XER_REGNUM
,
6078 /* Allow alternate names for these registers, to accomodate GDB's
6080 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
6081 PPC_MSR_REGNUM
, msr_names
);
6082 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
6083 PPC_CR_REGNUM
, cr_names
);
6084 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
6085 PPC_CTR_REGNUM
, ctr_names
);
6089 tdesc_data_cleanup (tdesc_data
);
6093 have_mq
= tdesc_numbered_register (feature
, tdesc_data
, PPC_MQ_REGNUM
,
6096 tdesc_wordsize
= tdesc_register_size (feature
, "pc") / 8;
6098 wordsize
= tdesc_wordsize
;
6100 feature
= tdesc_find_feature (tdesc
,
6101 "org.gnu.gdb.power.fpu");
6102 if (feature
!= NULL
)
6104 static const char *const fprs
[] = {
6105 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
6106 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
6107 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
6108 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
6111 for (i
= 0; i
< ppc_num_fprs
; i
++)
6112 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6113 PPC_F0_REGNUM
+ i
, fprs
[i
]);
6114 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6115 PPC_FPSCR_REGNUM
, "fpscr");
6119 tdesc_data_cleanup (tdesc_data
);
6127 /* The DFP pseudo-registers will be available when there are floating
6129 have_dfp
= have_fpu
;
6131 feature
= tdesc_find_feature (tdesc
,
6132 "org.gnu.gdb.power.altivec");
6133 if (feature
!= NULL
)
6135 static const char *const vector_regs
[] = {
6136 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
6137 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
6138 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
6139 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31"
6143 for (i
= 0; i
< ppc_num_gprs
; i
++)
6144 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6147 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6148 PPC_VSCR_REGNUM
, "vscr");
6149 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6150 PPC_VRSAVE_REGNUM
, "vrsave");
6152 if (have_spe
|| !valid_p
)
6154 tdesc_data_cleanup (tdesc_data
);
6162 /* Check for POWER7 VSX registers support. */
6163 feature
= tdesc_find_feature (tdesc
,
6164 "org.gnu.gdb.power.vsx");
6166 if (feature
!= NULL
)
6168 static const char *const vsx_regs
[] = {
6169 "vs0h", "vs1h", "vs2h", "vs3h", "vs4h", "vs5h",
6170 "vs6h", "vs7h", "vs8h", "vs9h", "vs10h", "vs11h",
6171 "vs12h", "vs13h", "vs14h", "vs15h", "vs16h", "vs17h",
6172 "vs18h", "vs19h", "vs20h", "vs21h", "vs22h", "vs23h",
6173 "vs24h", "vs25h", "vs26h", "vs27h", "vs28h", "vs29h",
6179 for (i
= 0; i
< ppc_num_vshrs
; i
++)
6180 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6181 PPC_VSR0_UPPER_REGNUM
+ i
,
6185 tdesc_data_cleanup (tdesc_data
);
6194 /* On machines supporting the SPE APU, the general-purpose registers
6195 are 64 bits long. There are SIMD vector instructions to treat them
6196 as pairs of floats, but the rest of the instruction set treats them
6197 as 32-bit registers, and only operates on their lower halves.
6199 In the GDB regcache, we treat their high and low halves as separate
6200 registers. The low halves we present as the general-purpose
6201 registers, and then we have pseudo-registers that stitch together
6202 the upper and lower halves and present them as pseudo-registers.
6204 Thus, the target description is expected to supply the upper
6205 halves separately. */
6207 feature
= tdesc_find_feature (tdesc
,
6208 "org.gnu.gdb.power.spe");
6209 if (feature
!= NULL
)
6211 static const char *const upper_spe
[] = {
6212 "ev0h", "ev1h", "ev2h", "ev3h",
6213 "ev4h", "ev5h", "ev6h", "ev7h",
6214 "ev8h", "ev9h", "ev10h", "ev11h",
6215 "ev12h", "ev13h", "ev14h", "ev15h",
6216 "ev16h", "ev17h", "ev18h", "ev19h",
6217 "ev20h", "ev21h", "ev22h", "ev23h",
6218 "ev24h", "ev25h", "ev26h", "ev27h",
6219 "ev28h", "ev29h", "ev30h", "ev31h"
6223 for (i
= 0; i
< ppc_num_gprs
; i
++)
6224 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6225 PPC_SPE_UPPER_GP0_REGNUM
+ i
,
6227 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6228 PPC_SPE_ACC_REGNUM
, "acc");
6229 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6230 PPC_SPE_FSCR_REGNUM
, "spefscr");
6232 if (have_mq
|| have_fpu
|| !valid_p
)
6234 tdesc_data_cleanup (tdesc_data
);
6243 /* If we have a 64-bit binary on a 32-bit target, complain. Also
6244 complain for a 32-bit binary on a 64-bit target; we do not yet
6245 support that. For instance, the 32-bit ABI routines expect
6248 As long as there isn't an explicit target description, we'll
6249 choose one based on the BFD architecture and get a word size
6250 matching the binary (probably powerpc:common or
6251 powerpc:common64). So there is only trouble if a 64-bit target
6252 supplies a 64-bit description while debugging a 32-bit
6254 if (tdesc_wordsize
!= -1 && tdesc_wordsize
!= wordsize
)
6256 tdesc_data_cleanup (tdesc_data
);
6263 switch (elf_elfheader (info
.abfd
)->e_flags
& EF_PPC64_ABI
)
6266 elf_abi
= POWERPC_ELF_V1
;
6269 elf_abi
= POWERPC_ELF_V2
;
6276 if (soft_float_flag
== AUTO_BOOLEAN_AUTO
&& from_elf_exec
)
6278 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6279 Tag_GNU_Power_ABI_FP
))
6282 soft_float_flag
= AUTO_BOOLEAN_FALSE
;
6285 soft_float_flag
= AUTO_BOOLEAN_TRUE
;
6292 if (vector_abi
== POWERPC_VEC_AUTO
&& from_elf_exec
)
6294 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6295 Tag_GNU_Power_ABI_Vector
))
6298 vector_abi
= POWERPC_VEC_GENERIC
;
6301 vector_abi
= POWERPC_VEC_ALTIVEC
;
6304 vector_abi
= POWERPC_VEC_SPE
;
6312 /* At this point, the only supported ELF-based 64-bit little-endian
6313 operating system is GNU/Linux, and this uses the ELFv2 ABI by
6314 default. All other supported ELF-based operating systems use the
6315 ELFv1 ABI by default. Therefore, if the ABI marker is missing,
6316 e.g. because we run a legacy binary, or have attached to a process
6317 and have not found any associated binary file, set the default
6318 according to this heuristic. */
6319 if (elf_abi
== POWERPC_ELF_AUTO
)
6321 if (wordsize
== 8 && info
.byte_order
== BFD_ENDIAN_LITTLE
)
6322 elf_abi
= POWERPC_ELF_V2
;
6324 elf_abi
= POWERPC_ELF_V1
;
6327 if (soft_float_flag
== AUTO_BOOLEAN_TRUE
)
6329 else if (soft_float_flag
== AUTO_BOOLEAN_FALSE
)
6332 soft_float
= !have_fpu
;
6334 /* If we have a hard float binary or setting but no floating point
6335 registers, downgrade to soft float anyway. We're still somewhat
6336 useful in this scenario. */
6337 if (!soft_float
&& !have_fpu
)
6340 /* Similarly for vector registers. */
6341 if (vector_abi
== POWERPC_VEC_ALTIVEC
&& !have_altivec
)
6342 vector_abi
= POWERPC_VEC_GENERIC
;
6344 if (vector_abi
== POWERPC_VEC_SPE
&& !have_spe
)
6345 vector_abi
= POWERPC_VEC_GENERIC
;
6347 if (vector_abi
== POWERPC_VEC_AUTO
)
6350 vector_abi
= POWERPC_VEC_ALTIVEC
;
6352 vector_abi
= POWERPC_VEC_SPE
;
6354 vector_abi
= POWERPC_VEC_GENERIC
;
6357 /* Do not limit the vector ABI based on available hardware, since we
6358 do not yet know what hardware we'll decide we have. Yuck! FIXME! */
6360 /* Find a candidate among extant architectures. */
6361 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
6363 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
6365 /* Word size in the various PowerPC bfd_arch_info structs isn't
6366 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
6367 separate word size check. */
6368 tdep
= gdbarch_tdep (arches
->gdbarch
);
6369 if (tdep
&& tdep
->elf_abi
!= elf_abi
)
6371 if (tdep
&& tdep
->soft_float
!= soft_float
)
6373 if (tdep
&& tdep
->vector_abi
!= vector_abi
)
6375 if (tdep
&& tdep
->wordsize
== wordsize
)
6377 if (tdesc_data
!= NULL
)
6378 tdesc_data_cleanup (tdesc_data
);
6379 return arches
->gdbarch
;
6383 /* None found, create a new architecture from INFO, whose bfd_arch_info
6384 validity depends on the source:
6385 - executable useless
6386 - rs6000_host_arch() good
6388 - "set arch" trust blindly
6389 - GDB startup useless but harmless */
6391 tdep
= XCNEW (struct gdbarch_tdep
);
6392 tdep
->wordsize
= wordsize
;
6393 tdep
->elf_abi
= elf_abi
;
6394 tdep
->soft_float
= soft_float
;
6395 tdep
->vector_abi
= vector_abi
;
6397 gdbarch
= gdbarch_alloc (&info
, tdep
);
6399 tdep
->ppc_gp0_regnum
= PPC_R0_REGNUM
;
6400 tdep
->ppc_toc_regnum
= PPC_R0_REGNUM
+ 2;
6401 tdep
->ppc_ps_regnum
= PPC_MSR_REGNUM
;
6402 tdep
->ppc_cr_regnum
= PPC_CR_REGNUM
;
6403 tdep
->ppc_lr_regnum
= PPC_LR_REGNUM
;
6404 tdep
->ppc_ctr_regnum
= PPC_CTR_REGNUM
;
6405 tdep
->ppc_xer_regnum
= PPC_XER_REGNUM
;
6406 tdep
->ppc_mq_regnum
= have_mq
? PPC_MQ_REGNUM
: -1;
6408 tdep
->ppc_fp0_regnum
= have_fpu
? PPC_F0_REGNUM
: -1;
6409 tdep
->ppc_fpscr_regnum
= have_fpu
? PPC_FPSCR_REGNUM
: -1;
6410 tdep
->ppc_vsr0_upper_regnum
= have_vsx
? PPC_VSR0_UPPER_REGNUM
: -1;
6411 tdep
->ppc_vr0_regnum
= have_altivec
? PPC_VR0_REGNUM
: -1;
6412 tdep
->ppc_vrsave_regnum
= have_altivec
? PPC_VRSAVE_REGNUM
: -1;
6413 tdep
->ppc_ev0_upper_regnum
= have_spe
? PPC_SPE_UPPER_GP0_REGNUM
: -1;
6414 tdep
->ppc_acc_regnum
= have_spe
? PPC_SPE_ACC_REGNUM
: -1;
6415 tdep
->ppc_spefscr_regnum
= have_spe
? PPC_SPE_FSCR_REGNUM
: -1;
6417 set_gdbarch_pc_regnum (gdbarch
, PPC_PC_REGNUM
);
6418 set_gdbarch_sp_regnum (gdbarch
, PPC_R0_REGNUM
+ 1);
6419 set_gdbarch_fp0_regnum (gdbarch
, tdep
->ppc_fp0_regnum
);
6420 set_gdbarch_register_sim_regno (gdbarch
, rs6000_register_sim_regno
);
6422 /* The XML specification for PowerPC sensibly calls the MSR "msr".
6423 GDB traditionally called it "ps", though, so let GDB add an
6425 set_gdbarch_ps_regnum (gdbarch
, tdep
->ppc_ps_regnum
);
6428 set_gdbarch_return_value (gdbarch
, ppc64_sysv_abi_return_value
);
6430 set_gdbarch_return_value (gdbarch
, ppc_sysv_abi_return_value
);
6432 /* Set lr_frame_offset. */
6434 tdep
->lr_frame_offset
= 16;
6436 tdep
->lr_frame_offset
= 4;
6438 if (have_spe
|| have_dfp
|| have_vsx
)
6440 set_gdbarch_pseudo_register_read (gdbarch
, rs6000_pseudo_register_read
);
6441 set_gdbarch_pseudo_register_write (gdbarch
,
6442 rs6000_pseudo_register_write
);
6443 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
6444 rs6000_ax_pseudo_register_collect
);
6447 set_gdbarch_gen_return_address (gdbarch
, rs6000_gen_return_address
);
6449 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6451 /* Select instruction printer. */
6452 if (arch
== bfd_arch_rs6000
)
6453 set_gdbarch_print_insn (gdbarch
, print_insn_rs6000
);
6455 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_powerpc
);
6457 set_gdbarch_num_regs (gdbarch
, PPC_NUM_REGS
);
6460 num_pseudoregs
+= 32;
6462 num_pseudoregs
+= 16;
6464 /* Include both VSX and Extended FP registers. */
6465 num_pseudoregs
+= 96;
6467 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudoregs
);
6469 set_gdbarch_ptr_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
6470 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
6471 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
6472 set_gdbarch_long_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
6473 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
6474 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
6475 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
6476 set_gdbarch_long_double_bit (gdbarch
, 16 * TARGET_CHAR_BIT
);
6477 set_gdbarch_char_signed (gdbarch
, 0);
6479 set_gdbarch_frame_align (gdbarch
, rs6000_frame_align
);
6482 set_gdbarch_frame_red_zone_size (gdbarch
, 288);
6484 set_gdbarch_convert_register_p (gdbarch
, rs6000_convert_register_p
);
6485 set_gdbarch_register_to_value (gdbarch
, rs6000_register_to_value
);
6486 set_gdbarch_value_to_register (gdbarch
, rs6000_value_to_register
);
6488 set_gdbarch_stab_reg_to_regnum (gdbarch
, rs6000_stab_reg_to_regnum
);
6489 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, rs6000_dwarf2_reg_to_regnum
);
6492 set_gdbarch_push_dummy_call (gdbarch
, ppc_sysv_abi_push_dummy_call
);
6493 else if (wordsize
== 8)
6494 set_gdbarch_push_dummy_call (gdbarch
, ppc64_sysv_abi_push_dummy_call
);
6496 set_gdbarch_skip_prologue (gdbarch
, rs6000_skip_prologue
);
6497 set_gdbarch_stack_frame_destroyed_p (gdbarch
, rs6000_stack_frame_destroyed_p
);
6498 set_gdbarch_skip_main_prologue (gdbarch
, rs6000_skip_main_prologue
);
6500 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6502 set_gdbarch_breakpoint_kind_from_pc (gdbarch
,
6503 rs6000_breakpoint::kind_from_pc
);
6504 set_gdbarch_sw_breakpoint_from_kind (gdbarch
,
6505 rs6000_breakpoint::bp_from_kind
);
6507 /* The value of symbols of type N_SO and N_FUN maybe null when
6509 set_gdbarch_sofun_address_maybe_missing (gdbarch
, 1);
6511 /* Handles single stepping of atomic sequences. */
6512 set_gdbarch_software_single_step (gdbarch
, ppc_deal_with_atomic_sequence
);
6514 /* Not sure on this. FIXMEmgo */
6515 set_gdbarch_frame_args_skip (gdbarch
, 8);
6517 /* Helpers for function argument information. */
6518 set_gdbarch_fetch_pointer_argument (gdbarch
, rs6000_fetch_pointer_argument
);
6521 set_gdbarch_in_solib_return_trampoline
6522 (gdbarch
, rs6000_in_solib_return_trampoline
);
6523 set_gdbarch_skip_trampoline_code (gdbarch
, rs6000_skip_trampoline_code
);
6525 /* Hook in the DWARF CFI frame unwinder. */
6526 dwarf2_append_unwinders (gdbarch
);
6527 dwarf2_frame_set_adjust_regnum (gdbarch
, rs6000_adjust_frame_regnum
);
6529 /* Frame handling. */
6530 dwarf2_frame_set_init_reg (gdbarch
, ppc_dwarf2_frame_init_reg
);
6532 /* Setup displaced stepping. */
6533 set_gdbarch_displaced_step_copy_insn (gdbarch
,
6534 ppc_displaced_step_copy_insn
);
6535 set_gdbarch_displaced_step_hw_singlestep (gdbarch
,
6536 ppc_displaced_step_hw_singlestep
);
6537 set_gdbarch_displaced_step_fixup (gdbarch
, ppc_displaced_step_fixup
);
6538 set_gdbarch_displaced_step_free_closure (gdbarch
,
6539 simple_displaced_step_free_closure
);
6540 set_gdbarch_displaced_step_location (gdbarch
,
6541 displaced_step_at_entry_point
);
6543 set_gdbarch_max_insn_length (gdbarch
, PPC_INSN_SIZE
);
6545 /* Hook in ABI-specific overrides, if they have been registered. */
6546 info
.target_desc
= tdesc
;
6547 info
.tdep_info
= tdesc_data
;
6548 gdbarch_init_osabi (info
, gdbarch
);
6552 case GDB_OSABI_LINUX
:
6553 case GDB_OSABI_NETBSD
:
6554 case GDB_OSABI_UNKNOWN
:
6555 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
6556 frame_unwind_append_unwinder (gdbarch
, &rs6000_epilogue_frame_unwind
);
6557 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
6558 set_gdbarch_dummy_id (gdbarch
, rs6000_dummy_id
);
6559 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
6562 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
6564 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
6565 frame_unwind_append_unwinder (gdbarch
, &rs6000_epilogue_frame_unwind
);
6566 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
6567 set_gdbarch_dummy_id (gdbarch
, rs6000_dummy_id
);
6568 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
6571 set_tdesc_pseudo_register_type (gdbarch
, rs6000_pseudo_register_type
);
6572 set_tdesc_pseudo_register_reggroup_p (gdbarch
,
6573 rs6000_pseudo_register_reggroup_p
);
6574 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
6576 /* Override the normal target description method to make the SPE upper
6577 halves anonymous. */
6578 set_gdbarch_register_name (gdbarch
, rs6000_register_name
);
6580 /* Choose register numbers for all supported pseudo-registers. */
6581 tdep
->ppc_ev0_regnum
= -1;
6582 tdep
->ppc_dl0_regnum
= -1;
6583 tdep
->ppc_vsr0_regnum
= -1;
6584 tdep
->ppc_efpr0_regnum
= -1;
6586 cur_reg
= gdbarch_num_regs (gdbarch
);
6590 tdep
->ppc_ev0_regnum
= cur_reg
;
6595 tdep
->ppc_dl0_regnum
= cur_reg
;
6600 tdep
->ppc_vsr0_regnum
= cur_reg
;
6602 tdep
->ppc_efpr0_regnum
= cur_reg
;
6606 gdb_assert (gdbarch_num_regs (gdbarch
)
6607 + gdbarch_num_pseudo_regs (gdbarch
) == cur_reg
);
6609 /* Register the ravenscar_arch_ops. */
6610 if (mach
== bfd_mach_ppc_e500
)
6611 register_e500_ravenscar_ops (gdbarch
);
6613 register_ppc_ravenscar_ops (gdbarch
);
6615 set_gdbarch_disassembler_options (gdbarch
, &powerpc_disassembler_options
);
6616 set_gdbarch_valid_disassembler_options (gdbarch
,
6617 disassembler_options_powerpc ());
6623 rs6000_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
6625 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6630 /* FIXME: Dump gdbarch_tdep. */
6633 /* PowerPC-specific commands. */
6636 set_powerpc_command (char *args
, int from_tty
)
6638 printf_unfiltered (_("\
6639 \"set powerpc\" must be followed by an appropriate subcommand.\n"));
6640 help_list (setpowerpccmdlist
, "set powerpc ", all_commands
, gdb_stdout
);
6644 show_powerpc_command (char *args
, int from_tty
)
6646 cmd_show_list (showpowerpccmdlist
, from_tty
, "");
6650 powerpc_set_soft_float (char *args
, int from_tty
,
6651 struct cmd_list_element
*c
)
6653 struct gdbarch_info info
;
6655 /* Update the architecture. */
6656 gdbarch_info_init (&info
);
6657 if (!gdbarch_update_p (info
))
6658 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
6662 powerpc_set_vector_abi (char *args
, int from_tty
,
6663 struct cmd_list_element
*c
)
6665 struct gdbarch_info info
;
6668 for (vector_abi
= POWERPC_VEC_AUTO
;
6669 vector_abi
!= POWERPC_VEC_LAST
;
6671 if (strcmp (powerpc_vector_abi_string
,
6672 powerpc_vector_strings
[vector_abi
]) == 0)
6674 powerpc_vector_abi_global
= (enum powerpc_vector_abi
) vector_abi
;
6678 if (vector_abi
== POWERPC_VEC_LAST
)
6679 internal_error (__FILE__
, __LINE__
, _("Invalid vector ABI accepted: %s."),
6680 powerpc_vector_abi_string
);
6682 /* Update the architecture. */
6683 gdbarch_info_init (&info
);
6684 if (!gdbarch_update_p (info
))
6685 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
6688 /* Show the current setting of the exact watchpoints flag. */
6691 show_powerpc_exact_watchpoints (struct ui_file
*file
, int from_tty
,
6692 struct cmd_list_element
*c
,
6695 fprintf_filtered (file
, _("Use of exact watchpoints is %s.\n"), value
);
6698 /* Read a PPC instruction from memory. */
6701 read_insn (struct frame_info
*frame
, CORE_ADDR pc
)
6703 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6704 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6706 return read_memory_unsigned_integer (pc
, 4, byte_order
);
6709 /* Return non-zero if the instructions at PC match the series
6710 described in PATTERN, or zero otherwise. PATTERN is an array of
6711 'struct ppc_insn_pattern' objects, terminated by an entry whose
6714 When the match is successful, fill INSN[i] with what PATTERN[i]
6715 matched. If PATTERN[i] is optional, and the instruction wasn't
6716 present, set INSN[i] to 0 (which is not a valid PPC instruction).
6717 INSN should have as many elements as PATTERN. Note that, if
6718 PATTERN contains optional instructions which aren't present in
6719 memory, then INSN will have holes, so INSN[i] isn't necessarily the
6720 i'th instruction in memory. */
6723 ppc_insns_match_pattern (struct frame_info
*frame
, CORE_ADDR pc
,
6724 struct ppc_insn_pattern
*pattern
,
6725 unsigned int *insns
)
6730 for (i
= 0, insn
= 0; pattern
[i
].mask
; i
++)
6733 insn
= read_insn (frame
, pc
);
6735 if ((insn
& pattern
[i
].mask
) == pattern
[i
].data
)
6741 else if (!pattern
[i
].optional
)
6748 /* Return the 'd' field of the d-form instruction INSN, properly
6752 ppc_insn_d_field (unsigned int insn
)
6754 return ((((CORE_ADDR
) insn
& 0xffff) ^ 0x8000) - 0x8000);
6757 /* Return the 'ds' field of the ds-form instruction INSN, with the two
6758 zero bits concatenated at the right, and properly
6762 ppc_insn_ds_field (unsigned int insn
)
6764 return ((((CORE_ADDR
) insn
& 0xfffc) ^ 0x8000) - 0x8000);
6767 /* Initialization code. */
6769 /* -Wmissing-prototypes */
6770 extern initialize_file_ftype _initialize_rs6000_tdep
;
6773 _initialize_rs6000_tdep (void)
6775 gdbarch_register (bfd_arch_rs6000
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
6776 gdbarch_register (bfd_arch_powerpc
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
6778 /* Initialize the standard target descriptions. */
6779 initialize_tdesc_powerpc_32 ();
6780 initialize_tdesc_powerpc_altivec32 ();
6781 initialize_tdesc_powerpc_vsx32 ();
6782 initialize_tdesc_powerpc_403 ();
6783 initialize_tdesc_powerpc_403gc ();
6784 initialize_tdesc_powerpc_405 ();
6785 initialize_tdesc_powerpc_505 ();
6786 initialize_tdesc_powerpc_601 ();
6787 initialize_tdesc_powerpc_602 ();
6788 initialize_tdesc_powerpc_603 ();
6789 initialize_tdesc_powerpc_604 ();
6790 initialize_tdesc_powerpc_64 ();
6791 initialize_tdesc_powerpc_altivec64 ();
6792 initialize_tdesc_powerpc_vsx64 ();
6793 initialize_tdesc_powerpc_7400 ();
6794 initialize_tdesc_powerpc_750 ();
6795 initialize_tdesc_powerpc_860 ();
6796 initialize_tdesc_powerpc_e500 ();
6797 initialize_tdesc_rs6000 ();
6799 /* Add root prefix command for all "set powerpc"/"show powerpc"
6801 add_prefix_cmd ("powerpc", no_class
, set_powerpc_command
,
6802 _("Various PowerPC-specific commands."),
6803 &setpowerpccmdlist
, "set powerpc ", 0, &setlist
);
6805 add_prefix_cmd ("powerpc", no_class
, show_powerpc_command
,
6806 _("Various PowerPC-specific commands."),
6807 &showpowerpccmdlist
, "show powerpc ", 0, &showlist
);
6809 /* Add a command to allow the user to force the ABI. */
6810 add_setshow_auto_boolean_cmd ("soft-float", class_support
,
6811 &powerpc_soft_float_global
,
6812 _("Set whether to use a soft-float ABI."),
6813 _("Show whether to use a soft-float ABI."),
6815 powerpc_set_soft_float
, NULL
,
6816 &setpowerpccmdlist
, &showpowerpccmdlist
);
6818 add_setshow_enum_cmd ("vector-abi", class_support
, powerpc_vector_strings
,
6819 &powerpc_vector_abi_string
,
6820 _("Set the vector ABI."),
6821 _("Show the vector ABI."),
6822 NULL
, powerpc_set_vector_abi
, NULL
,
6823 &setpowerpccmdlist
, &showpowerpccmdlist
);
6825 add_setshow_boolean_cmd ("exact-watchpoints", class_support
,
6826 &target_exact_watchpoints
,
6828 Set whether to use just one debug register for watchpoints on scalars."),
6830 Show whether to use just one debug register for watchpoints on scalars."),
6832 If true, GDB will use only one debug register when watching a variable of\n\
6833 scalar type, thus assuming that the variable is accessed through the address\n\
6834 of its first byte."),
6835 NULL
, show_powerpc_exact_watchpoints
,
6836 &setpowerpccmdlist
, &showpowerpccmdlist
);