1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 1986-2015 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
29 #include "arch-utils.h"
34 #include "parser-defs.h"
37 #include "sim-regno.h"
38 #include "gdb/sim-ppc.h"
39 #include "reggroups.h"
40 #include "dwarf2-frame.h"
41 #include "target-descriptions.h"
42 #include "user-regs.h"
43 #include "record-full.h"
46 #include "libbfd.h" /* for bfd_default_set_arch_mach */
47 #include "coff/internal.h" /* for libcoff.h */
48 #include "libcoff.h" /* for xcoff_data */
49 #include "coff/xcoff.h"
54 #include "elf/ppc64.h"
56 #include "solib-svr4.h"
58 #include "ppc-ravenscar-thread.h"
62 #include "trad-frame.h"
63 #include "frame-unwind.h"
64 #include "frame-base.h"
66 #include "features/rs6000/powerpc-32.c"
67 #include "features/rs6000/powerpc-altivec32.c"
68 #include "features/rs6000/powerpc-vsx32.c"
69 #include "features/rs6000/powerpc-403.c"
70 #include "features/rs6000/powerpc-403gc.c"
71 #include "features/rs6000/powerpc-405.c"
72 #include "features/rs6000/powerpc-505.c"
73 #include "features/rs6000/powerpc-601.c"
74 #include "features/rs6000/powerpc-602.c"
75 #include "features/rs6000/powerpc-603.c"
76 #include "features/rs6000/powerpc-604.c"
77 #include "features/rs6000/powerpc-64.c"
78 #include "features/rs6000/powerpc-altivec64.c"
79 #include "features/rs6000/powerpc-vsx64.c"
80 #include "features/rs6000/powerpc-7400.c"
81 #include "features/rs6000/powerpc-750.c"
82 #include "features/rs6000/powerpc-860.c"
83 #include "features/rs6000/powerpc-e500.c"
84 #include "features/rs6000/rs6000.c"
86 /* Determine if regnum is an SPE pseudo-register. */
87 #define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \
88 && (regnum) >= (tdep)->ppc_ev0_regnum \
89 && (regnum) < (tdep)->ppc_ev0_regnum + 32)
91 /* Determine if regnum is a decimal float pseudo-register. */
92 #define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \
93 && (regnum) >= (tdep)->ppc_dl0_regnum \
94 && (regnum) < (tdep)->ppc_dl0_regnum + 16)
96 /* Determine if regnum is a POWER7 VSX register. */
97 #define IS_VSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_vsr0_regnum >= 0 \
98 && (regnum) >= (tdep)->ppc_vsr0_regnum \
99 && (regnum) < (tdep)->ppc_vsr0_regnum + ppc_num_vsrs)
101 /* Determine if regnum is a POWER7 Extended FP register. */
102 #define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \
103 && (regnum) >= (tdep)->ppc_efpr0_regnum \
104 && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_efprs)
106 /* The list of available "set powerpc ..." and "show powerpc ..."
108 static struct cmd_list_element
*setpowerpccmdlist
= NULL
;
109 static struct cmd_list_element
*showpowerpccmdlist
= NULL
;
111 static enum auto_boolean powerpc_soft_float_global
= AUTO_BOOLEAN_AUTO
;
113 /* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */
114 static const char *const powerpc_vector_strings
[] =
123 /* A variable that can be configured by the user. */
124 static enum powerpc_vector_abi powerpc_vector_abi_global
= POWERPC_VEC_AUTO
;
125 static const char *powerpc_vector_abi_string
= "auto";
127 /* To be used by skip_prologue. */
129 struct rs6000_framedata
131 int offset
; /* total size of frame --- the distance
132 by which we decrement sp to allocate
134 int saved_gpr
; /* smallest # of saved gpr */
135 unsigned int gpr_mask
; /* Each bit is an individual saved GPR. */
136 int saved_fpr
; /* smallest # of saved fpr */
137 int saved_vr
; /* smallest # of saved vr */
138 int saved_ev
; /* smallest # of saved ev */
139 int alloca_reg
; /* alloca register number (frame ptr) */
140 char frameless
; /* true if frameless functions. */
141 char nosavedpc
; /* true if pc not saved. */
142 char used_bl
; /* true if link register clobbered */
143 int gpr_offset
; /* offset of saved gprs from prev sp */
144 int fpr_offset
; /* offset of saved fprs from prev sp */
145 int vr_offset
; /* offset of saved vrs from prev sp */
146 int ev_offset
; /* offset of saved evs from prev sp */
147 int lr_offset
; /* offset of saved lr */
148 int lr_register
; /* register of saved lr, if trustworthy */
149 int cr_offset
; /* offset of saved cr */
150 int vrsave_offset
; /* offset of saved vrsave register */
154 /* Is REGNO a VSX register? Return 1 if so, 0 otherwise. */
156 vsx_register_p (struct gdbarch
*gdbarch
, int regno
)
158 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
159 if (tdep
->ppc_vsr0_regnum
< 0)
162 return (regno
>= tdep
->ppc_vsr0_upper_regnum
&& regno
163 <= tdep
->ppc_vsr0_upper_regnum
+ 31);
166 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
168 altivec_register_p (struct gdbarch
*gdbarch
, int regno
)
170 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
171 if (tdep
->ppc_vr0_regnum
< 0 || tdep
->ppc_vrsave_regnum
< 0)
174 return (regno
>= tdep
->ppc_vr0_regnum
&& regno
<= tdep
->ppc_vrsave_regnum
);
178 /* Return true if REGNO is an SPE register, false otherwise. */
180 spe_register_p (struct gdbarch
*gdbarch
, int regno
)
182 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
184 /* Is it a reference to EV0 -- EV31, and do we have those? */
185 if (IS_SPE_PSEUDOREG (tdep
, regno
))
188 /* Is it a reference to one of the raw upper GPR halves? */
189 if (tdep
->ppc_ev0_upper_regnum
>= 0
190 && tdep
->ppc_ev0_upper_regnum
<= regno
191 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
194 /* Is it a reference to the 64-bit accumulator, and do we have that? */
195 if (tdep
->ppc_acc_regnum
>= 0
196 && tdep
->ppc_acc_regnum
== regno
)
199 /* Is it a reference to the SPE floating-point status and control register,
200 and do we have that? */
201 if (tdep
->ppc_spefscr_regnum
>= 0
202 && tdep
->ppc_spefscr_regnum
== regno
)
209 /* Return non-zero if the architecture described by GDBARCH has
210 floating-point registers (f0 --- f31 and fpscr). */
212 ppc_floating_point_unit_p (struct gdbarch
*gdbarch
)
214 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
216 return (tdep
->ppc_fp0_regnum
>= 0
217 && tdep
->ppc_fpscr_regnum
>= 0);
220 /* Return non-zero if the architecture described by GDBARCH has
221 VSX registers (vsr0 --- vsr63). */
223 ppc_vsx_support_p (struct gdbarch
*gdbarch
)
225 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
227 return tdep
->ppc_vsr0_regnum
>= 0;
230 /* Return non-zero if the architecture described by GDBARCH has
231 Altivec registers (vr0 --- vr31, vrsave and vscr). */
233 ppc_altivec_support_p (struct gdbarch
*gdbarch
)
235 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
237 return (tdep
->ppc_vr0_regnum
>= 0
238 && tdep
->ppc_vrsave_regnum
>= 0);
241 /* Check that TABLE[GDB_REGNO] is not already initialized, and then
244 This is a helper function for init_sim_regno_table, constructing
245 the table mapping GDB register numbers to sim register numbers; we
246 initialize every element in that table to -1 before we start
249 set_sim_regno (int *table
, int gdb_regno
, int sim_regno
)
251 /* Make sure we don't try to assign any given GDB register a sim
252 register number more than once. */
253 gdb_assert (table
[gdb_regno
] == -1);
254 table
[gdb_regno
] = sim_regno
;
258 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
259 numbers to simulator register numbers, based on the values placed
260 in the ARCH->tdep->ppc_foo_regnum members. */
262 init_sim_regno_table (struct gdbarch
*arch
)
264 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
265 int total_regs
= gdbarch_num_regs (arch
);
266 int *sim_regno
= GDBARCH_OBSTACK_CALLOC (arch
, total_regs
, int);
268 static const char *const segment_regs
[] = {
269 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
270 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
273 /* Presume that all registers not explicitly mentioned below are
274 unavailable from the sim. */
275 for (i
= 0; i
< total_regs
; i
++)
278 /* General-purpose registers. */
279 for (i
= 0; i
< ppc_num_gprs
; i
++)
280 set_sim_regno (sim_regno
, tdep
->ppc_gp0_regnum
+ i
, sim_ppc_r0_regnum
+ i
);
282 /* Floating-point registers. */
283 if (tdep
->ppc_fp0_regnum
>= 0)
284 for (i
= 0; i
< ppc_num_fprs
; i
++)
285 set_sim_regno (sim_regno
,
286 tdep
->ppc_fp0_regnum
+ i
,
287 sim_ppc_f0_regnum
+ i
);
288 if (tdep
->ppc_fpscr_regnum
>= 0)
289 set_sim_regno (sim_regno
, tdep
->ppc_fpscr_regnum
, sim_ppc_fpscr_regnum
);
291 set_sim_regno (sim_regno
, gdbarch_pc_regnum (arch
), sim_ppc_pc_regnum
);
292 set_sim_regno (sim_regno
, tdep
->ppc_ps_regnum
, sim_ppc_ps_regnum
);
293 set_sim_regno (sim_regno
, tdep
->ppc_cr_regnum
, sim_ppc_cr_regnum
);
295 /* Segment registers. */
296 for (i
= 0; i
< ppc_num_srs
; i
++)
300 gdb_regno
= user_reg_map_name_to_regnum (arch
, segment_regs
[i
], -1);
302 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_sr0_regnum
+ i
);
305 /* Altivec registers. */
306 if (tdep
->ppc_vr0_regnum
>= 0)
308 for (i
= 0; i
< ppc_num_vrs
; i
++)
309 set_sim_regno (sim_regno
,
310 tdep
->ppc_vr0_regnum
+ i
,
311 sim_ppc_vr0_regnum
+ i
);
313 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
314 we can treat this more like the other cases. */
315 set_sim_regno (sim_regno
,
316 tdep
->ppc_vr0_regnum
+ ppc_num_vrs
,
317 sim_ppc_vscr_regnum
);
319 /* vsave is a special-purpose register, so the code below handles it. */
321 /* SPE APU (E500) registers. */
322 if (tdep
->ppc_ev0_upper_regnum
>= 0)
323 for (i
= 0; i
< ppc_num_gprs
; i
++)
324 set_sim_regno (sim_regno
,
325 tdep
->ppc_ev0_upper_regnum
+ i
,
326 sim_ppc_rh0_regnum
+ i
);
327 if (tdep
->ppc_acc_regnum
>= 0)
328 set_sim_regno (sim_regno
, tdep
->ppc_acc_regnum
, sim_ppc_acc_regnum
);
329 /* spefscr is a special-purpose register, so the code below handles it. */
332 /* Now handle all special-purpose registers. Verify that they
333 haven't mistakenly been assigned numbers by any of the above
335 for (i
= 0; i
< sim_ppc_num_sprs
; i
++)
337 const char *spr_name
= sim_spr_register_name (i
);
340 if (spr_name
!= NULL
)
341 gdb_regno
= user_reg_map_name_to_regnum (arch
, spr_name
, -1);
344 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_spr0_regnum
+ i
);
348 /* Drop the initialized array into place. */
349 tdep
->sim_regno
= sim_regno
;
353 /* Given a GDB register number REG, return the corresponding SIM
356 rs6000_register_sim_regno (struct gdbarch
*gdbarch
, int reg
)
358 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
361 if (tdep
->sim_regno
== NULL
)
362 init_sim_regno_table (gdbarch
);
365 && reg
<= gdbarch_num_regs (gdbarch
)
366 + gdbarch_num_pseudo_regs (gdbarch
));
367 sim_regno
= tdep
->sim_regno
[reg
];
372 return LEGACY_SIM_REGNO_IGNORE
;
377 /* Register set support functions. */
379 /* REGS + OFFSET contains register REGNUM in a field REGSIZE wide.
380 Write the register to REGCACHE. */
383 ppc_supply_reg (struct regcache
*regcache
, int regnum
,
384 const gdb_byte
*regs
, size_t offset
, int regsize
)
386 if (regnum
!= -1 && offset
!= -1)
390 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
391 int gdb_regsize
= register_size (gdbarch
, regnum
);
392 if (gdb_regsize
< regsize
393 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
394 offset
+= regsize
- gdb_regsize
;
396 regcache_raw_supply (regcache
, regnum
, regs
+ offset
);
400 /* Read register REGNUM from REGCACHE and store to REGS + OFFSET
401 in a field REGSIZE wide. Zero pad as necessary. */
404 ppc_collect_reg (const struct regcache
*regcache
, int regnum
,
405 gdb_byte
*regs
, size_t offset
, int regsize
)
407 if (regnum
!= -1 && offset
!= -1)
411 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
412 int gdb_regsize
= register_size (gdbarch
, regnum
);
413 if (gdb_regsize
< regsize
)
415 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
417 memset (regs
+ offset
, 0, regsize
- gdb_regsize
);
418 offset
+= regsize
- gdb_regsize
;
421 memset (regs
+ offset
+ regsize
- gdb_regsize
, 0,
422 regsize
- gdb_regsize
);
425 regcache_raw_collect (regcache
, regnum
, regs
+ offset
);
430 ppc_greg_offset (struct gdbarch
*gdbarch
,
431 struct gdbarch_tdep
*tdep
,
432 const struct ppc_reg_offsets
*offsets
,
436 *regsize
= offsets
->gpr_size
;
437 if (regnum
>= tdep
->ppc_gp0_regnum
438 && regnum
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
)
439 return (offsets
->r0_offset
440 + (regnum
- tdep
->ppc_gp0_regnum
) * offsets
->gpr_size
);
442 if (regnum
== gdbarch_pc_regnum (gdbarch
))
443 return offsets
->pc_offset
;
445 if (regnum
== tdep
->ppc_ps_regnum
)
446 return offsets
->ps_offset
;
448 if (regnum
== tdep
->ppc_lr_regnum
)
449 return offsets
->lr_offset
;
451 if (regnum
== tdep
->ppc_ctr_regnum
)
452 return offsets
->ctr_offset
;
454 *regsize
= offsets
->xr_size
;
455 if (regnum
== tdep
->ppc_cr_regnum
)
456 return offsets
->cr_offset
;
458 if (regnum
== tdep
->ppc_xer_regnum
)
459 return offsets
->xer_offset
;
461 if (regnum
== tdep
->ppc_mq_regnum
)
462 return offsets
->mq_offset
;
468 ppc_fpreg_offset (struct gdbarch_tdep
*tdep
,
469 const struct ppc_reg_offsets
*offsets
,
472 if (regnum
>= tdep
->ppc_fp0_regnum
473 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
)
474 return offsets
->f0_offset
+ (regnum
- tdep
->ppc_fp0_regnum
) * 8;
476 if (regnum
== tdep
->ppc_fpscr_regnum
)
477 return offsets
->fpscr_offset
;
483 ppc_vrreg_offset (struct gdbarch_tdep
*tdep
,
484 const struct ppc_reg_offsets
*offsets
,
487 if (regnum
>= tdep
->ppc_vr0_regnum
488 && regnum
< tdep
->ppc_vr0_regnum
+ ppc_num_vrs
)
489 return offsets
->vr0_offset
+ (regnum
- tdep
->ppc_vr0_regnum
) * 16;
491 if (regnum
== tdep
->ppc_vrsave_regnum
- 1)
492 return offsets
->vscr_offset
;
494 if (regnum
== tdep
->ppc_vrsave_regnum
)
495 return offsets
->vrsave_offset
;
500 /* Supply register REGNUM in the general-purpose register set REGSET
501 from the buffer specified by GREGS and LEN to register cache
502 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
505 ppc_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
506 int regnum
, const void *gregs
, size_t len
)
508 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
509 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
510 const struct ppc_reg_offsets
*offsets
= regset
->regmap
;
517 int gpr_size
= offsets
->gpr_size
;
519 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
520 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
521 i
++, offset
+= gpr_size
)
522 ppc_supply_reg (regcache
, i
, gregs
, offset
, gpr_size
);
524 ppc_supply_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
525 gregs
, offsets
->pc_offset
, gpr_size
);
526 ppc_supply_reg (regcache
, tdep
->ppc_ps_regnum
,
527 gregs
, offsets
->ps_offset
, gpr_size
);
528 ppc_supply_reg (regcache
, tdep
->ppc_lr_regnum
,
529 gregs
, offsets
->lr_offset
, gpr_size
);
530 ppc_supply_reg (regcache
, tdep
->ppc_ctr_regnum
,
531 gregs
, offsets
->ctr_offset
, gpr_size
);
532 ppc_supply_reg (regcache
, tdep
->ppc_cr_regnum
,
533 gregs
, offsets
->cr_offset
, offsets
->xr_size
);
534 ppc_supply_reg (regcache
, tdep
->ppc_xer_regnum
,
535 gregs
, offsets
->xer_offset
, offsets
->xr_size
);
536 ppc_supply_reg (regcache
, tdep
->ppc_mq_regnum
,
537 gregs
, offsets
->mq_offset
, offsets
->xr_size
);
541 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
542 ppc_supply_reg (regcache
, regnum
, gregs
, offset
, regsize
);
545 /* Supply register REGNUM in the floating-point register set REGSET
546 from the buffer specified by FPREGS and LEN to register cache
547 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
550 ppc_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
551 int regnum
, const void *fpregs
, size_t len
)
553 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
554 struct gdbarch_tdep
*tdep
;
555 const struct ppc_reg_offsets
*offsets
;
558 if (!ppc_floating_point_unit_p (gdbarch
))
561 tdep
= gdbarch_tdep (gdbarch
);
562 offsets
= regset
->regmap
;
567 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
568 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
570 ppc_supply_reg (regcache
, i
, fpregs
, offset
, 8);
572 ppc_supply_reg (regcache
, tdep
->ppc_fpscr_regnum
,
573 fpregs
, offsets
->fpscr_offset
, offsets
->fpscr_size
);
577 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
578 ppc_supply_reg (regcache
, regnum
, fpregs
, offset
,
579 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
582 /* Supply register REGNUM in the VSX register set REGSET
583 from the buffer specified by VSXREGS and LEN to register cache
584 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
587 ppc_supply_vsxregset (const struct regset
*regset
, struct regcache
*regcache
,
588 int regnum
, const void *vsxregs
, size_t len
)
590 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
591 struct gdbarch_tdep
*tdep
;
593 if (!ppc_vsx_support_p (gdbarch
))
596 tdep
= gdbarch_tdep (gdbarch
);
602 for (i
= tdep
->ppc_vsr0_upper_regnum
;
603 i
< tdep
->ppc_vsr0_upper_regnum
+ 32;
605 ppc_supply_reg (regcache
, i
, vsxregs
, 0, 8);
610 ppc_supply_reg (regcache
, regnum
, vsxregs
, 0, 8);
613 /* Supply register REGNUM in the Altivec register set REGSET
614 from the buffer specified by VRREGS and LEN to register cache
615 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
618 ppc_supply_vrregset (const struct regset
*regset
, struct regcache
*regcache
,
619 int regnum
, const void *vrregs
, size_t len
)
621 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
622 struct gdbarch_tdep
*tdep
;
623 const struct ppc_reg_offsets
*offsets
;
626 if (!ppc_altivec_support_p (gdbarch
))
629 tdep
= gdbarch_tdep (gdbarch
);
630 offsets
= regset
->regmap
;
635 for (i
= tdep
->ppc_vr0_regnum
, offset
= offsets
->vr0_offset
;
636 i
< tdep
->ppc_vr0_regnum
+ ppc_num_vrs
;
638 ppc_supply_reg (regcache
, i
, vrregs
, offset
, 16);
640 ppc_supply_reg (regcache
, (tdep
->ppc_vrsave_regnum
- 1),
641 vrregs
, offsets
->vscr_offset
, 4);
643 ppc_supply_reg (regcache
, tdep
->ppc_vrsave_regnum
,
644 vrregs
, offsets
->vrsave_offset
, 4);
648 offset
= ppc_vrreg_offset (tdep
, offsets
, regnum
);
649 if (regnum
!= tdep
->ppc_vrsave_regnum
650 && regnum
!= tdep
->ppc_vrsave_regnum
- 1)
651 ppc_supply_reg (regcache
, regnum
, vrregs
, offset
, 16);
653 ppc_supply_reg (regcache
, regnum
,
657 /* Collect register REGNUM in the general-purpose register set
658 REGSET from register cache REGCACHE into the buffer specified by
659 GREGS and LEN. If REGNUM is -1, do this for all registers in
663 ppc_collect_gregset (const struct regset
*regset
,
664 const struct regcache
*regcache
,
665 int regnum
, void *gregs
, size_t len
)
667 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
668 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
669 const struct ppc_reg_offsets
*offsets
= regset
->regmap
;
676 int gpr_size
= offsets
->gpr_size
;
678 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
679 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
680 i
++, offset
+= gpr_size
)
681 ppc_collect_reg (regcache
, i
, gregs
, offset
, gpr_size
);
683 ppc_collect_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
684 gregs
, offsets
->pc_offset
, gpr_size
);
685 ppc_collect_reg (regcache
, tdep
->ppc_ps_regnum
,
686 gregs
, offsets
->ps_offset
, gpr_size
);
687 ppc_collect_reg (regcache
, tdep
->ppc_lr_regnum
,
688 gregs
, offsets
->lr_offset
, gpr_size
);
689 ppc_collect_reg (regcache
, tdep
->ppc_ctr_regnum
,
690 gregs
, offsets
->ctr_offset
, gpr_size
);
691 ppc_collect_reg (regcache
, tdep
->ppc_cr_regnum
,
692 gregs
, offsets
->cr_offset
, offsets
->xr_size
);
693 ppc_collect_reg (regcache
, tdep
->ppc_xer_regnum
,
694 gregs
, offsets
->xer_offset
, offsets
->xr_size
);
695 ppc_collect_reg (regcache
, tdep
->ppc_mq_regnum
,
696 gregs
, offsets
->mq_offset
, offsets
->xr_size
);
700 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
701 ppc_collect_reg (regcache
, regnum
, gregs
, offset
, regsize
);
704 /* Collect register REGNUM in the floating-point register set
705 REGSET from register cache REGCACHE into the buffer specified by
706 FPREGS and LEN. If REGNUM is -1, do this for all registers in
710 ppc_collect_fpregset (const struct regset
*regset
,
711 const struct regcache
*regcache
,
712 int regnum
, void *fpregs
, size_t len
)
714 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
715 struct gdbarch_tdep
*tdep
;
716 const struct ppc_reg_offsets
*offsets
;
719 if (!ppc_floating_point_unit_p (gdbarch
))
722 tdep
= gdbarch_tdep (gdbarch
);
723 offsets
= regset
->regmap
;
728 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
729 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
731 ppc_collect_reg (regcache
, i
, fpregs
, offset
, 8);
733 ppc_collect_reg (regcache
, tdep
->ppc_fpscr_regnum
,
734 fpregs
, offsets
->fpscr_offset
, offsets
->fpscr_size
);
738 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
739 ppc_collect_reg (regcache
, regnum
, fpregs
, offset
,
740 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
743 /* Collect register REGNUM in the VSX register set
744 REGSET from register cache REGCACHE into the buffer specified by
745 VSXREGS and LEN. If REGNUM is -1, do this for all registers in
749 ppc_collect_vsxregset (const struct regset
*regset
,
750 const struct regcache
*regcache
,
751 int regnum
, void *vsxregs
, size_t len
)
753 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
754 struct gdbarch_tdep
*tdep
;
756 if (!ppc_vsx_support_p (gdbarch
))
759 tdep
= gdbarch_tdep (gdbarch
);
765 for (i
= tdep
->ppc_vsr0_upper_regnum
;
766 i
< tdep
->ppc_vsr0_upper_regnum
+ 32;
768 ppc_collect_reg (regcache
, i
, vsxregs
, 0, 8);
773 ppc_collect_reg (regcache
, regnum
, vsxregs
, 0, 8);
777 /* Collect register REGNUM in the Altivec register set
778 REGSET from register cache REGCACHE into the buffer specified by
779 VRREGS and LEN. If REGNUM is -1, do this for all registers in
783 ppc_collect_vrregset (const struct regset
*regset
,
784 const struct regcache
*regcache
,
785 int regnum
, void *vrregs
, size_t len
)
787 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
788 struct gdbarch_tdep
*tdep
;
789 const struct ppc_reg_offsets
*offsets
;
792 if (!ppc_altivec_support_p (gdbarch
))
795 tdep
= gdbarch_tdep (gdbarch
);
796 offsets
= regset
->regmap
;
801 for (i
= tdep
->ppc_vr0_regnum
, offset
= offsets
->vr0_offset
;
802 i
< tdep
->ppc_vr0_regnum
+ ppc_num_vrs
;
804 ppc_collect_reg (regcache
, i
, vrregs
, offset
, 16);
806 ppc_collect_reg (regcache
, (tdep
->ppc_vrsave_regnum
- 1),
807 vrregs
, offsets
->vscr_offset
, 4);
809 ppc_collect_reg (regcache
, tdep
->ppc_vrsave_regnum
,
810 vrregs
, offsets
->vrsave_offset
, 4);
814 offset
= ppc_vrreg_offset (tdep
, offsets
, regnum
);
815 if (regnum
!= tdep
->ppc_vrsave_regnum
816 && regnum
!= tdep
->ppc_vrsave_regnum
- 1)
817 ppc_collect_reg (regcache
, regnum
, vrregs
, offset
, 16);
819 ppc_collect_reg (regcache
, regnum
,
825 insn_changes_sp_or_jumps (unsigned long insn
)
827 int opcode
= (insn
>> 26) & 0x03f;
828 int sd
= (insn
>> 21) & 0x01f;
829 int a
= (insn
>> 16) & 0x01f;
830 int subcode
= (insn
>> 1) & 0x3ff;
832 /* Changes the stack pointer. */
834 /* NOTE: There are many ways to change the value of a given register.
835 The ways below are those used when the register is R1, the SP,
836 in a funtion's epilogue. */
838 if (opcode
== 31 && subcode
== 444 && a
== 1)
839 return 1; /* mr R1,Rn */
840 if (opcode
== 14 && sd
== 1)
841 return 1; /* addi R1,Rn,simm */
842 if (opcode
== 58 && sd
== 1)
843 return 1; /* ld R1,ds(Rn) */
845 /* Transfers control. */
851 if (opcode
== 19 && subcode
== 16)
853 if (opcode
== 19 && subcode
== 528)
854 return 1; /* bcctr */
859 /* Return true if we are in the function's epilogue, i.e. after the
860 instruction that destroyed the function's stack frame.
862 1) scan forward from the point of execution:
863 a) If you find an instruction that modifies the stack pointer
864 or transfers control (except a return), execution is not in
866 b) Stop scanning if you find a return instruction or reach the
867 end of the function or reach the hard limit for the size of
869 2) scan backward from the point of execution:
870 a) If you find an instruction that modifies the stack pointer,
871 execution *is* in an epilogue, return.
872 b) Stop scanning if you reach an instruction that transfers
873 control or the beginning of the function or reach the hard
874 limit for the size of an epilogue. */
877 rs6000_in_function_epilogue_frame_p (struct frame_info
*curfrm
,
878 struct gdbarch
*gdbarch
, CORE_ADDR pc
)
880 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
881 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
882 bfd_byte insn_buf
[PPC_INSN_SIZE
];
883 CORE_ADDR scan_pc
, func_start
, func_end
, epilogue_start
, epilogue_end
;
886 /* Find the search limits based on function boundaries and hard limit. */
888 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
891 epilogue_start
= pc
- PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
892 if (epilogue_start
< func_start
) epilogue_start
= func_start
;
894 epilogue_end
= pc
+ PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
895 if (epilogue_end
> func_end
) epilogue_end
= func_end
;
897 /* Scan forward until next 'blr'. */
899 for (scan_pc
= pc
; scan_pc
< epilogue_end
; scan_pc
+= PPC_INSN_SIZE
)
901 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
903 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
904 if (insn
== 0x4e800020)
906 /* Assume a bctr is a tail call unless it points strictly within
908 if (insn
== 0x4e800420)
910 CORE_ADDR ctr
= get_frame_register_unsigned (curfrm
,
911 tdep
->ppc_ctr_regnum
);
912 if (ctr
> func_start
&& ctr
< func_end
)
917 if (insn_changes_sp_or_jumps (insn
))
921 /* Scan backward until adjustment to stack pointer (R1). */
923 for (scan_pc
= pc
- PPC_INSN_SIZE
;
924 scan_pc
>= epilogue_start
;
925 scan_pc
-= PPC_INSN_SIZE
)
927 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
929 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
930 if (insn_changes_sp_or_jumps (insn
))
937 /* Implement the stack_frame_destroyed_p gdbarch method. */
940 rs6000_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
942 return rs6000_in_function_epilogue_frame_p (get_current_frame (),
946 /* Get the ith function argument for the current function. */
948 rs6000_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
951 return get_frame_register_unsigned (frame
, 3 + argi
);
954 /* Sequence of bytes for breakpoint instruction. */
956 static const unsigned char *
957 rs6000_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*bp_addr
,
960 static unsigned char big_breakpoint
[] = { 0x7d, 0x82, 0x10, 0x08 };
961 static unsigned char little_breakpoint
[] = { 0x08, 0x10, 0x82, 0x7d };
963 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
964 return big_breakpoint
;
966 return little_breakpoint
;
969 /* Instruction masks for displaced stepping. */
970 #define BRANCH_MASK 0xfc000000
971 #define BP_MASK 0xFC0007FE
972 #define B_INSN 0x48000000
973 #define BC_INSN 0x40000000
974 #define BXL_INSN 0x4c000000
975 #define BP_INSN 0x7C000008
977 /* Instruction masks used during single-stepping of atomic
979 #define LWARX_MASK 0xfc0007fe
980 #define LWARX_INSTRUCTION 0x7c000028
981 #define LDARX_INSTRUCTION 0x7c0000A8
982 #define STWCX_MASK 0xfc0007ff
983 #define STWCX_INSTRUCTION 0x7c00012d
984 #define STDCX_INSTRUCTION 0x7c0001ad
986 /* We can't displaced step atomic sequences. Otherwise this is just
987 like simple_displaced_step_copy_insn. */
989 static struct displaced_step_closure
*
990 ppc_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
991 CORE_ADDR from
, CORE_ADDR to
,
992 struct regcache
*regs
)
994 size_t len
= gdbarch_max_insn_length (gdbarch
);
995 gdb_byte
*buf
= xmalloc (len
);
996 struct cleanup
*old_chain
= make_cleanup (xfree
, buf
);
997 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1000 read_memory (from
, buf
, len
);
1002 insn
= extract_signed_integer (buf
, PPC_INSN_SIZE
, byte_order
);
1004 /* Assume all atomic sequences start with a lwarx/ldarx instruction. */
1005 if ((insn
& LWARX_MASK
) == LWARX_INSTRUCTION
1006 || (insn
& LWARX_MASK
) == LDARX_INSTRUCTION
)
1008 if (debug_displaced
)
1010 fprintf_unfiltered (gdb_stdlog
,
1011 "displaced: can't displaced step "
1012 "atomic sequence at %s\n",
1013 paddress (gdbarch
, from
));
1015 do_cleanups (old_chain
);
1019 write_memory (to
, buf
, len
);
1021 if (debug_displaced
)
1023 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
1024 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
1025 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
1028 discard_cleanups (old_chain
);
1029 return (struct displaced_step_closure
*) buf
;
1032 /* Fix up the state of registers and memory after having single-stepped
1033 a displaced instruction. */
1035 ppc_displaced_step_fixup (struct gdbarch
*gdbarch
,
1036 struct displaced_step_closure
*closure
,
1037 CORE_ADDR from
, CORE_ADDR to
,
1038 struct regcache
*regs
)
1040 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1041 /* Our closure is a copy of the instruction. */
1042 ULONGEST insn
= extract_unsigned_integer ((gdb_byte
*) closure
,
1043 PPC_INSN_SIZE
, byte_order
);
1044 ULONGEST opcode
= 0;
1045 /* Offset for non PC-relative instructions. */
1046 LONGEST offset
= PPC_INSN_SIZE
;
1048 opcode
= insn
& BRANCH_MASK
;
1050 if (debug_displaced
)
1051 fprintf_unfiltered (gdb_stdlog
,
1052 "displaced: (ppc) fixup (%s, %s)\n",
1053 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
1056 /* Handle PC-relative branch instructions. */
1057 if (opcode
== B_INSN
|| opcode
== BC_INSN
|| opcode
== BXL_INSN
)
1059 ULONGEST current_pc
;
1061 /* Read the current PC value after the instruction has been executed
1062 in a displaced location. Calculate the offset to be applied to the
1063 original PC value before the displaced stepping. */
1064 regcache_cooked_read_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1066 offset
= current_pc
- to
;
1068 if (opcode
!= BXL_INSN
)
1070 /* Check for AA bit indicating whether this is an absolute
1071 addressing or PC-relative (1: absolute, 0: relative). */
1074 /* PC-relative addressing is being used in the branch. */
1075 if (debug_displaced
)
1078 "displaced: (ppc) branch instruction: %s\n"
1079 "displaced: (ppc) adjusted PC from %s to %s\n",
1080 paddress (gdbarch
, insn
), paddress (gdbarch
, current_pc
),
1081 paddress (gdbarch
, from
+ offset
));
1083 regcache_cooked_write_unsigned (regs
,
1084 gdbarch_pc_regnum (gdbarch
),
1090 /* If we're here, it means we have a branch to LR or CTR. If the
1091 branch was taken, the offset is probably greater than 4 (the next
1092 instruction), so it's safe to assume that an offset of 4 means we
1093 did not take the branch. */
1094 if (offset
== PPC_INSN_SIZE
)
1095 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1096 from
+ PPC_INSN_SIZE
);
1099 /* Check for LK bit indicating whether we should set the link
1100 register to point to the next instruction
1101 (1: Set, 0: Don't set). */
1104 /* Link register needs to be set to the next instruction's PC. */
1105 regcache_cooked_write_unsigned (regs
,
1106 gdbarch_tdep (gdbarch
)->ppc_lr_regnum
,
1107 from
+ PPC_INSN_SIZE
);
1108 if (debug_displaced
)
1109 fprintf_unfiltered (gdb_stdlog
,
1110 "displaced: (ppc) adjusted LR to %s\n",
1111 paddress (gdbarch
, from
+ PPC_INSN_SIZE
));
1115 /* Check for breakpoints in the inferior. If we've found one, place the PC
1116 right at the breakpoint instruction. */
1117 else if ((insn
& BP_MASK
) == BP_INSN
)
1118 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
), from
);
1120 /* Handle any other instructions that do not fit in the categories above. */
1121 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1125 /* Always use hardware single-stepping to execute the
1126 displaced instruction. */
1128 ppc_displaced_step_hw_singlestep (struct gdbarch
*gdbarch
,
1129 struct displaced_step_closure
*closure
)
1134 /* Checks for an atomic sequence of instructions beginning with a LWARX/LDARX
1135 instruction and ending with a STWCX/STDCX instruction. If such a sequence
1136 is found, attempt to step through it. A breakpoint is placed at the end of
1140 ppc_deal_with_atomic_sequence (struct frame_info
*frame
)
1142 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1143 struct address_space
*aspace
= get_frame_address_space (frame
);
1144 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1145 CORE_ADDR pc
= get_frame_pc (frame
);
1146 CORE_ADDR breaks
[2] = {-1, -1};
1148 CORE_ADDR closing_insn
; /* Instruction that closes the atomic sequence. */
1149 int insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1152 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
1153 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
1154 int opcode
; /* Branch instruction's OPcode. */
1155 int bc_insn_count
= 0; /* Conditional branch instruction count. */
1157 /* Assume all atomic sequences start with a lwarx/ldarx instruction. */
1158 if ((insn
& LWARX_MASK
) != LWARX_INSTRUCTION
1159 && (insn
& LWARX_MASK
) != LDARX_INSTRUCTION
)
1162 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
1164 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
1166 loc
+= PPC_INSN_SIZE
;
1167 insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1169 /* Assume that there is at most one conditional branch in the atomic
1170 sequence. If a conditional branch is found, put a breakpoint in
1171 its destination address. */
1172 if ((insn
& BRANCH_MASK
) == BC_INSN
)
1174 int immediate
= ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
1175 int absolute
= insn
& 2;
1177 if (bc_insn_count
>= 1)
1178 return 0; /* More than one conditional branch found, fallback
1179 to the standard single-step code. */
1182 breaks
[1] = immediate
;
1184 breaks
[1] = loc
+ immediate
;
1190 if ((insn
& STWCX_MASK
) == STWCX_INSTRUCTION
1191 || (insn
& STWCX_MASK
) == STDCX_INSTRUCTION
)
1195 /* Assume that the atomic sequence ends with a stwcx/stdcx instruction. */
1196 if ((insn
& STWCX_MASK
) != STWCX_INSTRUCTION
1197 && (insn
& STWCX_MASK
) != STDCX_INSTRUCTION
)
1201 loc
+= PPC_INSN_SIZE
;
1202 insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1204 /* Insert a breakpoint right after the end of the atomic sequence. */
1207 /* Check for duplicated breakpoints. Check also for a breakpoint
1208 placed (branch instruction's destination) anywhere in sequence. */
1210 && (breaks
[1] == breaks
[0]
1211 || (breaks
[1] >= pc
&& breaks
[1] <= closing_insn
)))
1212 last_breakpoint
= 0;
1214 /* Effectively inserts the breakpoints. */
1215 for (index
= 0; index
<= last_breakpoint
; index
++)
1216 insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
1222 #define SIGNED_SHORT(x) \
1223 ((sizeof (short) == 2) \
1224 ? ((int)(short)(x)) \
1225 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
1227 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
1229 /* Limit the number of skipped non-prologue instructions, as the examining
1230 of the prologue is expensive. */
1231 static int max_skip_non_prologue_insns
= 10;
1233 /* Return nonzero if the given instruction OP can be part of the prologue
1234 of a function and saves a parameter on the stack. FRAMEP should be
1235 set if one of the previous instructions in the function has set the
1239 store_param_on_stack_p (unsigned long op
, int framep
, int *r0_contains_arg
)
1241 /* Move parameters from argument registers to temporary register. */
1242 if ((op
& 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
1244 /* Rx must be scratch register r0. */
1245 const int rx_regno
= (op
>> 16) & 31;
1246 /* Ry: Only r3 - r10 are used for parameter passing. */
1247 const int ry_regno
= GET_SRC_REG (op
);
1249 if (rx_regno
== 0 && ry_regno
>= 3 && ry_regno
<= 10)
1251 *r0_contains_arg
= 1;
1258 /* Save a General Purpose Register on stack. */
1260 if ((op
& 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
1261 (op
& 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
1263 /* Rx: Only r3 - r10 are used for parameter passing. */
1264 const int rx_regno
= GET_SRC_REG (op
);
1266 return (rx_regno
>= 3 && rx_regno
<= 10);
1269 /* Save a General Purpose Register on stack via the Frame Pointer. */
1272 ((op
& 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
1273 (op
& 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
1274 (op
& 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
1276 /* Rx: Usually, only r3 - r10 are used for parameter passing.
1277 However, the compiler sometimes uses r0 to hold an argument. */
1278 const int rx_regno
= GET_SRC_REG (op
);
1280 return ((rx_regno
>= 3 && rx_regno
<= 10)
1281 || (rx_regno
== 0 && *r0_contains_arg
));
1284 if ((op
& 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
1286 /* Only f2 - f8 are used for parameter passing. */
1287 const int src_regno
= GET_SRC_REG (op
);
1289 return (src_regno
>= 2 && src_regno
<= 8);
1292 if (framep
&& ((op
& 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
1294 /* Only f2 - f8 are used for parameter passing. */
1295 const int src_regno
= GET_SRC_REG (op
);
1297 return (src_regno
>= 2 && src_regno
<= 8);
1300 /* Not an insn that saves a parameter on stack. */
1304 /* Assuming that INSN is a "bl" instruction located at PC, return
1305 nonzero if the destination of the branch is a "blrl" instruction.
1307 This sequence is sometimes found in certain function prologues.
1308 It allows the function to load the LR register with a value that
1309 they can use to access PIC data using PC-relative offsets. */
1312 bl_to_blrl_insn_p (CORE_ADDR pc
, int insn
, enum bfd_endian byte_order
)
1319 absolute
= (int) ((insn
>> 1) & 1);
1320 immediate
= ((insn
& ~3) << 6) >> 6;
1324 dest
= pc
+ immediate
;
1326 dest_insn
= read_memory_integer (dest
, 4, byte_order
);
1327 if ((dest_insn
& 0xfc00ffff) == 0x4c000021) /* blrl */
1333 /* Masks for decoding a branch-and-link (bl) instruction.
1335 BL_MASK and BL_INSTRUCTION are used in combination with each other.
1336 The former is anded with the opcode in question; if the result of
1337 this masking operation is equal to BL_INSTRUCTION, then the opcode in
1338 question is a ``bl'' instruction.
1340 BL_DISPLACMENT_MASK is anded with the opcode in order to extract
1341 the branch displacement. */
1343 #define BL_MASK 0xfc000001
1344 #define BL_INSTRUCTION 0x48000001
1345 #define BL_DISPLACEMENT_MASK 0x03fffffc
1347 static unsigned long
1348 rs6000_fetch_instruction (struct gdbarch
*gdbarch
, const CORE_ADDR pc
)
1350 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1354 /* Fetch the instruction and convert it to an integer. */
1355 if (target_read_memory (pc
, buf
, 4))
1357 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1362 /* GCC generates several well-known sequences of instructions at the begining
1363 of each function prologue when compiling with -fstack-check. If one of
1364 such sequences starts at START_PC, then return the address of the
1365 instruction immediately past this sequence. Otherwise, return START_PC. */
1368 rs6000_skip_stack_check (struct gdbarch
*gdbarch
, const CORE_ADDR start_pc
)
1370 CORE_ADDR pc
= start_pc
;
1371 unsigned long op
= rs6000_fetch_instruction (gdbarch
, pc
);
1373 /* First possible sequence: A small number of probes.
1374 stw 0, -<some immediate>(1)
1375 [repeat this instruction any (small) number of times]. */
1377 if ((op
& 0xffff0000) == 0x90010000)
1379 while ((op
& 0xffff0000) == 0x90010000)
1382 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1387 /* Second sequence: A probing loop.
1388 addi 12,1,-<some immediate>
1389 lis 0,-<some immediate>
1390 [possibly ori 0,0,<some immediate>]
1394 addi 12,12,-<some immediate>
1397 [possibly one last probe: stw 0,<some immediate>(12)]. */
1401 /* addi 12,1,-<some immediate> */
1402 if ((op
& 0xffff0000) != 0x39810000)
1405 /* lis 0,-<some immediate> */
1407 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1408 if ((op
& 0xffff0000) != 0x3c000000)
1412 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1413 /* [possibly ori 0,0,<some immediate>] */
1414 if ((op
& 0xffff0000) == 0x60000000)
1417 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1420 if (op
!= 0x7c0c0214)
1425 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1426 if (op
!= 0x7c0c0000)
1431 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1432 if ((op
& 0xff9f0001) != 0x41820000)
1435 /* addi 12,12,-<some immediate> */
1437 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1438 if ((op
& 0xffff0000) != 0x398c0000)
1443 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1444 if (op
!= 0x900c0000)
1449 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1450 if ((op
& 0xfc000001) != 0x48000000)
1453 /* [possibly one last probe: stw 0,<some immediate>(12)]. */
1455 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1456 if ((op
& 0xffff0000) == 0x900c0000)
1459 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1462 /* We found a valid stack-check sequence, return the new PC. */
1466 /* Third sequence: No probe; instead, a comparizon between the stack size
1467 limit (saved in a run-time global variable) and the current stack
1470 addi 0,1,-<some immediate>
1471 lis 12,__gnat_stack_limit@ha
1472 lwz 12,__gnat_stack_limit@l(12)
1475 or, with a small variant in the case of a bigger stack frame:
1476 addis 0,1,<some immediate>
1477 addic 0,0,-<some immediate>
1478 lis 12,__gnat_stack_limit@ha
1479 lwz 12,__gnat_stack_limit@l(12)
1484 /* addi 0,1,-<some immediate> */
1485 if ((op
& 0xffff0000) != 0x38010000)
1487 /* small stack frame variant not recognized; try the
1488 big stack frame variant: */
1490 /* addis 0,1,<some immediate> */
1491 if ((op
& 0xffff0000) != 0x3c010000)
1494 /* addic 0,0,-<some immediate> */
1496 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1497 if ((op
& 0xffff0000) != 0x30000000)
1501 /* lis 12,<some immediate> */
1503 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1504 if ((op
& 0xffff0000) != 0x3d800000)
1507 /* lwz 12,<some immediate>(12) */
1509 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1510 if ((op
& 0xffff0000) != 0x818c0000)
1515 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1516 if ((op
& 0xfffffffe) != 0x7c406008)
1519 /* We found a valid stack-check sequence, return the new PC. */
1523 /* No stack check code in our prologue, return the start_pc. */
1527 /* return pc value after skipping a function prologue and also return
1528 information about a function frame.
1530 in struct rs6000_framedata fdata:
1531 - frameless is TRUE, if function does not have a frame.
1532 - nosavedpc is TRUE, if function does not save %pc value in its frame.
1533 - offset is the initial size of this stack frame --- the amount by
1534 which we decrement the sp to allocate the frame.
1535 - saved_gpr is the number of the first saved gpr.
1536 - saved_fpr is the number of the first saved fpr.
1537 - saved_vr is the number of the first saved vr.
1538 - saved_ev is the number of the first saved ev.
1539 - alloca_reg is the number of the register used for alloca() handling.
1541 - gpr_offset is the offset of the first saved gpr from the previous frame.
1542 - fpr_offset is the offset of the first saved fpr from the previous frame.
1543 - vr_offset is the offset of the first saved vr from the previous frame.
1544 - ev_offset is the offset of the first saved ev from the previous frame.
1545 - lr_offset is the offset of the saved lr
1546 - cr_offset is the offset of the saved cr
1547 - vrsave_offset is the offset of the saved vrsave register. */
1550 skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
, CORE_ADDR lim_pc
,
1551 struct rs6000_framedata
*fdata
)
1553 CORE_ADDR orig_pc
= pc
;
1554 CORE_ADDR last_prologue_pc
= pc
;
1555 CORE_ADDR li_found_pc
= 0;
1559 long vr_saved_offset
= 0;
1565 int vrsave_reg
= -1;
1568 int minimal_toc_loaded
= 0;
1569 int prev_insn_was_prologue_insn
= 1;
1570 int num_skip_non_prologue_insns
= 0;
1571 int r0_contains_arg
= 0;
1572 const struct bfd_arch_info
*arch_info
= gdbarch_bfd_arch_info (gdbarch
);
1573 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1574 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1576 memset (fdata
, 0, sizeof (struct rs6000_framedata
));
1577 fdata
->saved_gpr
= -1;
1578 fdata
->saved_fpr
= -1;
1579 fdata
->saved_vr
= -1;
1580 fdata
->saved_ev
= -1;
1581 fdata
->alloca_reg
= -1;
1582 fdata
->frameless
= 1;
1583 fdata
->nosavedpc
= 1;
1584 fdata
->lr_register
= -1;
1586 pc
= rs6000_skip_stack_check (gdbarch
, pc
);
1592 /* Sometimes it isn't clear if an instruction is a prologue
1593 instruction or not. When we encounter one of these ambiguous
1594 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
1595 Otherwise, we'll assume that it really is a prologue instruction. */
1596 if (prev_insn_was_prologue_insn
)
1597 last_prologue_pc
= pc
;
1599 /* Stop scanning if we've hit the limit. */
1603 prev_insn_was_prologue_insn
= 1;
1605 /* Fetch the instruction and convert it to an integer. */
1606 if (target_read_memory (pc
, buf
, 4))
1608 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1610 if ((op
& 0xfc1fffff) == 0x7c0802a6)
1612 /* Since shared library / PIC code, which needs to get its
1613 address at runtime, can appear to save more than one link
1627 remember just the first one, but skip over additional
1630 lr_reg
= (op
& 0x03e00000) >> 21;
1632 r0_contains_arg
= 0;
1635 else if ((op
& 0xfc1fffff) == 0x7c000026)
1637 cr_reg
= (op
& 0x03e00000);
1639 r0_contains_arg
= 0;
1643 else if ((op
& 0xfc1f0000) == 0xd8010000)
1644 { /* stfd Rx,NUM(r1) */
1645 reg
= GET_SRC_REG (op
);
1646 if (fdata
->saved_fpr
== -1 || fdata
->saved_fpr
> reg
)
1648 fdata
->saved_fpr
= reg
;
1649 fdata
->fpr_offset
= SIGNED_SHORT (op
) + offset
;
1654 else if (((op
& 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
1655 (((op
& 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1656 (op
& 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1657 (op
& 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
1660 reg
= GET_SRC_REG (op
);
1661 if ((op
& 0xfc1f0000) == 0xbc010000)
1662 fdata
->gpr_mask
|= ~((1U << reg
) - 1);
1664 fdata
->gpr_mask
|= 1U << reg
;
1665 if (fdata
->saved_gpr
== -1 || fdata
->saved_gpr
> reg
)
1667 fdata
->saved_gpr
= reg
;
1668 if ((op
& 0xfc1f0003) == 0xf8010000)
1670 fdata
->gpr_offset
= SIGNED_SHORT (op
) + offset
;
1675 else if ((op
& 0xffff0000) == 0x3c4c0000
1676 || (op
& 0xffff0000) == 0x3c400000
1677 || (op
& 0xffff0000) == 0x38420000)
1679 /* . 0: addis 2,12,.TOC.-0b@ha
1680 . addi 2,2,.TOC.-0b@l
1684 used by ELFv2 global entry points to set up r2. */
1687 else if (op
== 0x60000000)
1690 /* Allow nops in the prologue, but do not consider them to
1691 be part of the prologue unless followed by other prologue
1693 prev_insn_was_prologue_insn
= 0;
1697 else if ((op
& 0xffff0000) == 0x3c000000)
1698 { /* addis 0,0,NUM, used for >= 32k frames */
1699 fdata
->offset
= (op
& 0x0000ffff) << 16;
1700 fdata
->frameless
= 0;
1701 r0_contains_arg
= 0;
1705 else if ((op
& 0xffff0000) == 0x60000000)
1706 { /* ori 0,0,NUM, 2nd half of >= 32k frames */
1707 fdata
->offset
|= (op
& 0x0000ffff);
1708 fdata
->frameless
= 0;
1709 r0_contains_arg
= 0;
1713 else if (lr_reg
>= 0 &&
1714 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1715 (((op
& 0xffff0000) == (lr_reg
| 0xf8010000)) ||
1716 /* stw Rx, NUM(r1) */
1717 ((op
& 0xffff0000) == (lr_reg
| 0x90010000)) ||
1718 /* stwu Rx, NUM(r1) */
1719 ((op
& 0xffff0000) == (lr_reg
| 0x94010000))))
1720 { /* where Rx == lr */
1721 fdata
->lr_offset
= offset
;
1722 fdata
->nosavedpc
= 0;
1723 /* Invalidate lr_reg, but don't set it to -1.
1724 That would mean that it had never been set. */
1726 if ((op
& 0xfc000003) == 0xf8000000 || /* std */
1727 (op
& 0xfc000000) == 0x90000000) /* stw */
1729 /* Does not update r1, so add displacement to lr_offset. */
1730 fdata
->lr_offset
+= SIGNED_SHORT (op
);
1735 else if (cr_reg
>= 0 &&
1736 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1737 (((op
& 0xffff0000) == (cr_reg
| 0xf8010000)) ||
1738 /* stw Rx, NUM(r1) */
1739 ((op
& 0xffff0000) == (cr_reg
| 0x90010000)) ||
1740 /* stwu Rx, NUM(r1) */
1741 ((op
& 0xffff0000) == (cr_reg
| 0x94010000))))
1742 { /* where Rx == cr */
1743 fdata
->cr_offset
= offset
;
1744 /* Invalidate cr_reg, but don't set it to -1.
1745 That would mean that it had never been set. */
1747 if ((op
& 0xfc000003) == 0xf8000000 ||
1748 (op
& 0xfc000000) == 0x90000000)
1750 /* Does not update r1, so add displacement to cr_offset. */
1751 fdata
->cr_offset
+= SIGNED_SHORT (op
);
1756 else if ((op
& 0xfe80ffff) == 0x42800005 && lr_reg
!= -1)
1758 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1759 prediction bits. If the LR has already been saved, we can
1763 else if (op
== 0x48000005)
1770 else if (op
== 0x48000004)
1775 else if ((op
& 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1776 in V.4 -mminimal-toc */
1777 (op
& 0xffff0000) == 0x3bde0000)
1778 { /* addi 30,30,foo@l */
1782 else if ((op
& 0xfc000001) == 0x48000001)
1786 fdata
->frameless
= 0;
1788 /* If the return address has already been saved, we can skip
1789 calls to blrl (for PIC). */
1790 if (lr_reg
!= -1 && bl_to_blrl_insn_p (pc
, op
, byte_order
))
1796 /* Don't skip over the subroutine call if it is not within
1797 the first three instructions of the prologue and either
1798 we have no line table information or the line info tells
1799 us that the subroutine call is not part of the line
1800 associated with the prologue. */
1801 if ((pc
- orig_pc
) > 8)
1803 struct symtab_and_line prologue_sal
= find_pc_line (orig_pc
, 0);
1804 struct symtab_and_line this_sal
= find_pc_line (pc
, 0);
1806 if ((prologue_sal
.line
== 0)
1807 || (prologue_sal
.line
!= this_sal
.line
))
1811 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
1813 /* At this point, make sure this is not a trampoline
1814 function (a function that simply calls another functions,
1815 and nothing else). If the next is not a nop, this branch
1816 was part of the function prologue. */
1818 if (op
== 0x4def7b82 || op
== 0) /* crorc 15, 15, 15 */
1819 break; /* Don't skip over
1825 /* update stack pointer */
1826 else if ((op
& 0xfc1f0000) == 0x94010000)
1827 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
1828 fdata
->frameless
= 0;
1829 fdata
->offset
= SIGNED_SHORT (op
);
1830 offset
= fdata
->offset
;
1833 else if ((op
& 0xfc1f016a) == 0x7c01016e)
1834 { /* stwux rX,r1,rY */
1835 /* No way to figure out what r1 is going to be. */
1836 fdata
->frameless
= 0;
1837 offset
= fdata
->offset
;
1840 else if ((op
& 0xfc1f0003) == 0xf8010001)
1841 { /* stdu rX,NUM(r1) */
1842 fdata
->frameless
= 0;
1843 fdata
->offset
= SIGNED_SHORT (op
& ~3UL);
1844 offset
= fdata
->offset
;
1847 else if ((op
& 0xfc1f016a) == 0x7c01016a)
1848 { /* stdux rX,r1,rY */
1849 /* No way to figure out what r1 is going to be. */
1850 fdata
->frameless
= 0;
1851 offset
= fdata
->offset
;
1854 else if ((op
& 0xffff0000) == 0x38210000)
1855 { /* addi r1,r1,SIMM */
1856 fdata
->frameless
= 0;
1857 fdata
->offset
+= SIGNED_SHORT (op
);
1858 offset
= fdata
->offset
;
1861 /* Load up minimal toc pointer. Do not treat an epilogue restore
1862 of r31 as a minimal TOC load. */
1863 else if (((op
>> 22) == 0x20f || /* l r31,... or l r30,... */
1864 (op
>> 22) == 0x3af) /* ld r31,... or ld r30,... */
1866 && !minimal_toc_loaded
)
1868 minimal_toc_loaded
= 1;
1871 /* move parameters from argument registers to local variable
1874 else if ((op
& 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1875 (((op
>> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1876 (((op
>> 21) & 31) <= 10) &&
1877 ((long) ((op
>> 16) & 31)
1878 >= fdata
->saved_gpr
)) /* Rx: local var reg */
1882 /* store parameters in stack */
1884 /* Move parameters from argument registers to temporary register. */
1885 else if (store_param_on_stack_p (op
, framep
, &r0_contains_arg
))
1889 /* Set up frame pointer */
1891 else if (op
== 0x603d0000) /* oril r29, r1, 0x0 */
1893 fdata
->frameless
= 0;
1895 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 29);
1898 /* Another way to set up the frame pointer. */
1900 else if (op
== 0x603f0000 /* oril r31, r1, 0x0 */
1901 || op
== 0x7c3f0b78)
1903 fdata
->frameless
= 0;
1905 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 31);
1908 /* Another way to set up the frame pointer. */
1910 else if ((op
& 0xfc1fffff) == 0x38010000)
1911 { /* addi rX, r1, 0x0 */
1912 fdata
->frameless
= 0;
1914 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
1915 + ((op
& ~0x38010000) >> 21));
1918 /* AltiVec related instructions. */
1919 /* Store the vrsave register (spr 256) in another register for
1920 later manipulation, or load a register into the vrsave
1921 register. 2 instructions are used: mfvrsave and
1922 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1923 and mtspr SPR256, Rn. */
1924 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1925 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1926 else if ((op
& 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1928 vrsave_reg
= GET_SRC_REG (op
);
1931 else if ((op
& 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1935 /* Store the register where vrsave was saved to onto the stack:
1936 rS is the register where vrsave was stored in a previous
1938 /* 100100 sssss 00001 dddddddd dddddddd */
1939 else if ((op
& 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1941 if (vrsave_reg
== GET_SRC_REG (op
))
1943 fdata
->vrsave_offset
= SIGNED_SHORT (op
) + offset
;
1948 /* Compute the new value of vrsave, by modifying the register
1949 where vrsave was saved to. */
1950 else if (((op
& 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1951 || ((op
& 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1955 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1956 in a pair of insns to save the vector registers on the
1958 /* 001110 00000 00000 iiii iiii iiii iiii */
1959 /* 001110 01110 00000 iiii iiii iiii iiii */
1960 else if ((op
& 0xffff0000) == 0x38000000 /* li r0, SIMM */
1961 || (op
& 0xffff0000) == 0x39c00000) /* li r14, SIMM */
1963 if ((op
& 0xffff0000) == 0x38000000)
1964 r0_contains_arg
= 0;
1966 vr_saved_offset
= SIGNED_SHORT (op
);
1968 /* This insn by itself is not part of the prologue, unless
1969 if part of the pair of insns mentioned above. So do not
1970 record this insn as part of the prologue yet. */
1971 prev_insn_was_prologue_insn
= 0;
1973 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1974 /* 011111 sssss 11111 00000 00111001110 */
1975 else if ((op
& 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1977 if (pc
== (li_found_pc
+ 4))
1979 vr_reg
= GET_SRC_REG (op
);
1980 /* If this is the first vector reg to be saved, or if
1981 it has a lower number than others previously seen,
1982 reupdate the frame info. */
1983 if (fdata
->saved_vr
== -1 || fdata
->saved_vr
> vr_reg
)
1985 fdata
->saved_vr
= vr_reg
;
1986 fdata
->vr_offset
= vr_saved_offset
+ offset
;
1988 vr_saved_offset
= -1;
1993 /* End AltiVec related instructions. */
1995 /* Start BookE related instructions. */
1996 /* Store gen register S at (r31+uimm).
1997 Any register less than r13 is volatile, so we don't care. */
1998 /* 000100 sssss 11111 iiiii 01100100001 */
1999 else if (arch_info
->mach
== bfd_mach_ppc_e500
2000 && (op
& 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
2002 if ((op
& 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
2005 ev_reg
= GET_SRC_REG (op
);
2006 imm
= (op
>> 11) & 0x1f;
2007 ev_offset
= imm
* 8;
2008 /* If this is the first vector reg to be saved, or if
2009 it has a lower number than others previously seen,
2010 reupdate the frame info. */
2011 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2013 fdata
->saved_ev
= ev_reg
;
2014 fdata
->ev_offset
= ev_offset
+ offset
;
2019 /* Store gen register rS at (r1+rB). */
2020 /* 000100 sssss 00001 bbbbb 01100100000 */
2021 else if (arch_info
->mach
== bfd_mach_ppc_e500
2022 && (op
& 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
2024 if (pc
== (li_found_pc
+ 4))
2026 ev_reg
= GET_SRC_REG (op
);
2027 /* If this is the first vector reg to be saved, or if
2028 it has a lower number than others previously seen,
2029 reupdate the frame info. */
2030 /* We know the contents of rB from the previous instruction. */
2031 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2033 fdata
->saved_ev
= ev_reg
;
2034 fdata
->ev_offset
= vr_saved_offset
+ offset
;
2036 vr_saved_offset
= -1;
2042 /* Store gen register r31 at (rA+uimm). */
2043 /* 000100 11111 aaaaa iiiii 01100100001 */
2044 else if (arch_info
->mach
== bfd_mach_ppc_e500
2045 && (op
& 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
2047 /* Wwe know that the source register is 31 already, but
2048 it can't hurt to compute it. */
2049 ev_reg
= GET_SRC_REG (op
);
2050 ev_offset
= ((op
>> 11) & 0x1f) * 8;
2051 /* If this is the first vector reg to be saved, or if
2052 it has a lower number than others previously seen,
2053 reupdate the frame info. */
2054 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2056 fdata
->saved_ev
= ev_reg
;
2057 fdata
->ev_offset
= ev_offset
+ offset
;
2062 /* Store gen register S at (r31+r0).
2063 Store param on stack when offset from SP bigger than 4 bytes. */
2064 /* 000100 sssss 11111 00000 01100100000 */
2065 else if (arch_info
->mach
== bfd_mach_ppc_e500
2066 && (op
& 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
2068 if (pc
== (li_found_pc
+ 4))
2070 if ((op
& 0x03e00000) >= 0x01a00000)
2072 ev_reg
= GET_SRC_REG (op
);
2073 /* If this is the first vector reg to be saved, or if
2074 it has a lower number than others previously seen,
2075 reupdate the frame info. */
2076 /* We know the contents of r0 from the previous
2078 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2080 fdata
->saved_ev
= ev_reg
;
2081 fdata
->ev_offset
= vr_saved_offset
+ offset
;
2085 vr_saved_offset
= -1;
2090 /* End BookE related instructions. */
2094 unsigned int all_mask
= ~((1U << fdata
->saved_gpr
) - 1);
2096 /* Not a recognized prologue instruction.
2097 Handle optimizer code motions into the prologue by continuing
2098 the search if we have no valid frame yet or if the return
2099 address is not yet saved in the frame. Also skip instructions
2100 if some of the GPRs expected to be saved are not yet saved. */
2101 if (fdata
->frameless
== 0 && fdata
->nosavedpc
== 0
2102 && (fdata
->gpr_mask
& all_mask
) == all_mask
)
2105 if (op
== 0x4e800020 /* blr */
2106 || op
== 0x4e800420) /* bctr */
2107 /* Do not scan past epilogue in frameless functions or
2110 if ((op
& 0xf4000000) == 0x40000000) /* bxx */
2111 /* Never skip branches. */
2114 if (num_skip_non_prologue_insns
++ > max_skip_non_prologue_insns
)
2115 /* Do not scan too many insns, scanning insns is expensive with
2119 /* Continue scanning. */
2120 prev_insn_was_prologue_insn
= 0;
2126 /* I have problems with skipping over __main() that I need to address
2127 * sometime. Previously, I used to use misc_function_vector which
2128 * didn't work as well as I wanted to be. -MGO */
2130 /* If the first thing after skipping a prolog is a branch to a function,
2131 this might be a call to an initializer in main(), introduced by gcc2.
2132 We'd like to skip over it as well. Fortunately, xlc does some extra
2133 work before calling a function right after a prologue, thus we can
2134 single out such gcc2 behaviour. */
2137 if ((op
& 0xfc000001) == 0x48000001)
2138 { /* bl foo, an initializer function? */
2139 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
2141 if (op
== 0x4def7b82)
2142 { /* cror 0xf, 0xf, 0xf (nop) */
2144 /* Check and see if we are in main. If so, skip over this
2145 initializer function as well. */
2147 tmp
= find_pc_misc_function (pc
);
2149 && strcmp (misc_function_vector
[tmp
].name
, main_name ()) == 0)
2155 if (pc
== lim_pc
&& lr_reg
>= 0)
2156 fdata
->lr_register
= lr_reg
;
2158 fdata
->offset
= -fdata
->offset
;
2159 return last_prologue_pc
;
2163 rs6000_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2165 struct rs6000_framedata frame
;
2166 CORE_ADDR limit_pc
, func_addr
, func_end_addr
= 0;
2168 /* See if we can determine the end of the prologue via the symbol table.
2169 If so, then return either PC, or the PC after the prologue, whichever
2171 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end_addr
))
2173 CORE_ADDR post_prologue_pc
2174 = skip_prologue_using_sal (gdbarch
, func_addr
);
2175 if (post_prologue_pc
!= 0)
2176 return max (pc
, post_prologue_pc
);
2179 /* Can't determine prologue from the symbol table, need to examine
2182 /* Find an upper limit on the function prologue using the debug
2183 information. If the debug information could not be used to provide
2184 that bound, then use an arbitrary large number as the upper bound. */
2185 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
2187 limit_pc
= pc
+ 100; /* Magic. */
2189 /* Do not allow limit_pc to be past the function end, if we know
2190 where that end is... */
2191 if (func_end_addr
&& limit_pc
> func_end_addr
)
2192 limit_pc
= func_end_addr
;
2194 pc
= skip_prologue (gdbarch
, pc
, limit_pc
, &frame
);
2198 /* When compiling for EABI, some versions of GCC emit a call to __eabi
2199 in the prologue of main().
2201 The function below examines the code pointed at by PC and checks to
2202 see if it corresponds to a call to __eabi. If so, it returns the
2203 address of the instruction following that call. Otherwise, it simply
2207 rs6000_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2209 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2213 if (target_read_memory (pc
, buf
, 4))
2215 op
= extract_unsigned_integer (buf
, 4, byte_order
);
2217 if ((op
& BL_MASK
) == BL_INSTRUCTION
)
2219 CORE_ADDR displ
= op
& BL_DISPLACEMENT_MASK
;
2220 CORE_ADDR call_dest
= pc
+ 4 + displ
;
2221 struct bound_minimal_symbol s
= lookup_minimal_symbol_by_pc (call_dest
);
2223 /* We check for ___eabi (three leading underscores) in addition
2224 to __eabi in case the GCC option "-fleading-underscore" was
2225 used to compile the program. */
2226 if (s
.minsym
!= NULL
2227 && MSYMBOL_LINKAGE_NAME (s
.minsym
) != NULL
2228 && (strcmp (MSYMBOL_LINKAGE_NAME (s
.minsym
), "__eabi") == 0
2229 || strcmp (MSYMBOL_LINKAGE_NAME (s
.minsym
), "___eabi") == 0))
2235 /* All the ABI's require 16 byte alignment. */
2237 rs6000_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2239 return (addr
& -16);
2242 /* Return whether handle_inferior_event() should proceed through code
2243 starting at PC in function NAME when stepping.
2245 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
2246 handle memory references that are too distant to fit in instructions
2247 generated by the compiler. For example, if 'foo' in the following
2252 is greater than 32767, the linker might replace the lwz with a branch to
2253 somewhere in @FIX1 that does the load in 2 instructions and then branches
2254 back to where execution should continue.
2256 GDB should silently step over @FIX code, just like AIX dbx does.
2257 Unfortunately, the linker uses the "b" instruction for the
2258 branches, meaning that the link register doesn't get set.
2259 Therefore, GDB's usual step_over_function () mechanism won't work.
2261 Instead, use the gdbarch_skip_trampoline_code and
2262 gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past
2266 rs6000_in_solib_return_trampoline (struct gdbarch
*gdbarch
,
2267 CORE_ADDR pc
, const char *name
)
2269 return name
&& startswith (name
, "@FIX");
2272 /* Skip code that the user doesn't want to see when stepping:
2274 1. Indirect function calls use a piece of trampoline code to do context
2275 switching, i.e. to set the new TOC table. Skip such code if we are on
2276 its first instruction (as when we have single-stepped to here).
2278 2. Skip shared library trampoline code (which is different from
2279 indirect function call trampolines).
2281 3. Skip bigtoc fixup code.
2283 Result is desired PC to step until, or NULL if we are not in
2284 code that should be skipped. */
2287 rs6000_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
2289 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2290 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2291 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2292 unsigned int ii
, op
;
2294 CORE_ADDR solib_target_pc
;
2295 struct bound_minimal_symbol msymbol
;
2297 static unsigned trampoline_code
[] =
2299 0x800b0000, /* l r0,0x0(r11) */
2300 0x90410014, /* st r2,0x14(r1) */
2301 0x7c0903a6, /* mtctr r0 */
2302 0x804b0004, /* l r2,0x4(r11) */
2303 0x816b0008, /* l r11,0x8(r11) */
2304 0x4e800420, /* bctr */
2305 0x4e800020, /* br */
2309 /* Check for bigtoc fixup code. */
2310 msymbol
= lookup_minimal_symbol_by_pc (pc
);
2312 && rs6000_in_solib_return_trampoline (gdbarch
, pc
,
2313 MSYMBOL_LINKAGE_NAME (msymbol
.minsym
)))
2315 /* Double-check that the third instruction from PC is relative "b". */
2316 op
= read_memory_integer (pc
+ 8, 4, byte_order
);
2317 if ((op
& 0xfc000003) == 0x48000000)
2319 /* Extract bits 6-29 as a signed 24-bit relative word address and
2320 add it to the containing PC. */
2321 rel
= ((int)(op
<< 6) >> 6);
2322 return pc
+ 8 + rel
;
2326 /* If pc is in a shared library trampoline, return its target. */
2327 solib_target_pc
= find_solib_trampoline_target (frame
, pc
);
2328 if (solib_target_pc
)
2329 return solib_target_pc
;
2331 for (ii
= 0; trampoline_code
[ii
]; ++ii
)
2333 op
= read_memory_integer (pc
+ (ii
* 4), 4, byte_order
);
2334 if (op
!= trampoline_code
[ii
])
2337 ii
= get_frame_register_unsigned (frame
, 11); /* r11 holds destination
2339 pc
= read_memory_unsigned_integer (ii
, tdep
->wordsize
, byte_order
);
2343 /* ISA-specific vector types. */
2345 static struct type
*
2346 rs6000_builtin_type_vec64 (struct gdbarch
*gdbarch
)
2348 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2350 if (!tdep
->ppc_builtin_type_vec64
)
2352 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2354 /* The type we're building is this: */
2356 union __gdb_builtin_type_vec64
2360 int32_t v2_int32
[2];
2361 int16_t v4_int16
[4];
2368 t
= arch_composite_type (gdbarch
,
2369 "__ppc_builtin_type_vec64", TYPE_CODE_UNION
);
2370 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2371 append_composite_type_field (t
, "v2_float",
2372 init_vector_type (bt
->builtin_float
, 2));
2373 append_composite_type_field (t
, "v2_int32",
2374 init_vector_type (bt
->builtin_int32
, 2));
2375 append_composite_type_field (t
, "v4_int16",
2376 init_vector_type (bt
->builtin_int16
, 4));
2377 append_composite_type_field (t
, "v8_int8",
2378 init_vector_type (bt
->builtin_int8
, 8));
2380 TYPE_VECTOR (t
) = 1;
2381 TYPE_NAME (t
) = "ppc_builtin_type_vec64";
2382 tdep
->ppc_builtin_type_vec64
= t
;
2385 return tdep
->ppc_builtin_type_vec64
;
2388 /* Vector 128 type. */
2390 static struct type
*
2391 rs6000_builtin_type_vec128 (struct gdbarch
*gdbarch
)
2393 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2395 if (!tdep
->ppc_builtin_type_vec128
)
2397 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2399 /* The type we're building is this
2401 type = union __ppc_builtin_type_vec128 {
2403 double v2_double[2];
2405 int32_t v4_int32[4];
2406 int16_t v8_int16[8];
2407 int8_t v16_int8[16];
2413 t
= arch_composite_type (gdbarch
,
2414 "__ppc_builtin_type_vec128", TYPE_CODE_UNION
);
2415 append_composite_type_field (t
, "uint128", bt
->builtin_uint128
);
2416 append_composite_type_field (t
, "v2_double",
2417 init_vector_type (bt
->builtin_double
, 2));
2418 append_composite_type_field (t
, "v4_float",
2419 init_vector_type (bt
->builtin_float
, 4));
2420 append_composite_type_field (t
, "v4_int32",
2421 init_vector_type (bt
->builtin_int32
, 4));
2422 append_composite_type_field (t
, "v8_int16",
2423 init_vector_type (bt
->builtin_int16
, 8));
2424 append_composite_type_field (t
, "v16_int8",
2425 init_vector_type (bt
->builtin_int8
, 16));
2427 TYPE_VECTOR (t
) = 1;
2428 TYPE_NAME (t
) = "ppc_builtin_type_vec128";
2429 tdep
->ppc_builtin_type_vec128
= t
;
2432 return tdep
->ppc_builtin_type_vec128
;
2435 /* Return the name of register number REGNO, or the empty string if it
2436 is an anonymous register. */
2439 rs6000_register_name (struct gdbarch
*gdbarch
, int regno
)
2441 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2443 /* The upper half "registers" have names in the XML description,
2444 but we present only the low GPRs and the full 64-bit registers
2446 if (tdep
->ppc_ev0_upper_regnum
>= 0
2447 && tdep
->ppc_ev0_upper_regnum
<= regno
2448 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
2451 /* Hide the upper halves of the vs0~vs31 registers. */
2452 if (tdep
->ppc_vsr0_regnum
>= 0
2453 && tdep
->ppc_vsr0_upper_regnum
<= regno
2454 && regno
< tdep
->ppc_vsr0_upper_regnum
+ ppc_num_gprs
)
2457 /* Check if the SPE pseudo registers are available. */
2458 if (IS_SPE_PSEUDOREG (tdep
, regno
))
2460 static const char *const spe_regnames
[] = {
2461 "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7",
2462 "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15",
2463 "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23",
2464 "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31",
2466 return spe_regnames
[regno
- tdep
->ppc_ev0_regnum
];
2469 /* Check if the decimal128 pseudo-registers are available. */
2470 if (IS_DFP_PSEUDOREG (tdep
, regno
))
2472 static const char *const dfp128_regnames
[] = {
2473 "dl0", "dl1", "dl2", "dl3",
2474 "dl4", "dl5", "dl6", "dl7",
2475 "dl8", "dl9", "dl10", "dl11",
2476 "dl12", "dl13", "dl14", "dl15"
2478 return dfp128_regnames
[regno
- tdep
->ppc_dl0_regnum
];
2481 /* Check if this is a VSX pseudo-register. */
2482 if (IS_VSX_PSEUDOREG (tdep
, regno
))
2484 static const char *const vsx_regnames
[] = {
2485 "vs0", "vs1", "vs2", "vs3", "vs4", "vs5", "vs6", "vs7",
2486 "vs8", "vs9", "vs10", "vs11", "vs12", "vs13", "vs14",
2487 "vs15", "vs16", "vs17", "vs18", "vs19", "vs20", "vs21",
2488 "vs22", "vs23", "vs24", "vs25", "vs26", "vs27", "vs28",
2489 "vs29", "vs30", "vs31", "vs32", "vs33", "vs34", "vs35",
2490 "vs36", "vs37", "vs38", "vs39", "vs40", "vs41", "vs42",
2491 "vs43", "vs44", "vs45", "vs46", "vs47", "vs48", "vs49",
2492 "vs50", "vs51", "vs52", "vs53", "vs54", "vs55", "vs56",
2493 "vs57", "vs58", "vs59", "vs60", "vs61", "vs62", "vs63"
2495 return vsx_regnames
[regno
- tdep
->ppc_vsr0_regnum
];
2498 /* Check if the this is a Extended FP pseudo-register. */
2499 if (IS_EFP_PSEUDOREG (tdep
, regno
))
2501 static const char *const efpr_regnames
[] = {
2502 "f32", "f33", "f34", "f35", "f36", "f37", "f38",
2503 "f39", "f40", "f41", "f42", "f43", "f44", "f45",
2504 "f46", "f47", "f48", "f49", "f50", "f51",
2505 "f52", "f53", "f54", "f55", "f56", "f57",
2506 "f58", "f59", "f60", "f61", "f62", "f63"
2508 return efpr_regnames
[regno
- tdep
->ppc_efpr0_regnum
];
2511 return tdesc_register_name (gdbarch
, regno
);
2514 /* Return the GDB type object for the "standard" data type of data in
2517 static struct type
*
2518 rs6000_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2520 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2522 /* These are the only pseudo-registers we support. */
2523 gdb_assert (IS_SPE_PSEUDOREG (tdep
, regnum
)
2524 || IS_DFP_PSEUDOREG (tdep
, regnum
)
2525 || IS_VSX_PSEUDOREG (tdep
, regnum
)
2526 || IS_EFP_PSEUDOREG (tdep
, regnum
));
2528 /* These are the e500 pseudo-registers. */
2529 if (IS_SPE_PSEUDOREG (tdep
, regnum
))
2530 return rs6000_builtin_type_vec64 (gdbarch
);
2531 else if (IS_DFP_PSEUDOREG (tdep
, regnum
))
2532 /* PPC decimal128 pseudo-registers. */
2533 return builtin_type (gdbarch
)->builtin_declong
;
2534 else if (IS_VSX_PSEUDOREG (tdep
, regnum
))
2535 /* POWER7 VSX pseudo-registers. */
2536 return rs6000_builtin_type_vec128 (gdbarch
);
2538 /* POWER7 Extended FP pseudo-registers. */
2539 return builtin_type (gdbarch
)->builtin_double
;
2542 /* Is REGNUM a member of REGGROUP? */
2544 rs6000_pseudo_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2545 struct reggroup
*group
)
2547 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2549 /* These are the only pseudo-registers we support. */
2550 gdb_assert (IS_SPE_PSEUDOREG (tdep
, regnum
)
2551 || IS_DFP_PSEUDOREG (tdep
, regnum
)
2552 || IS_VSX_PSEUDOREG (tdep
, regnum
)
2553 || IS_EFP_PSEUDOREG (tdep
, regnum
));
2555 /* These are the e500 pseudo-registers or the POWER7 VSX registers. */
2556 if (IS_SPE_PSEUDOREG (tdep
, regnum
) || IS_VSX_PSEUDOREG (tdep
, regnum
))
2557 return group
== all_reggroup
|| group
== vector_reggroup
;
2559 /* PPC decimal128 or Extended FP pseudo-registers. */
2560 return group
== all_reggroup
|| group
== float_reggroup
;
2563 /* The register format for RS/6000 floating point registers is always
2564 double, we need a conversion if the memory format is float. */
2567 rs6000_convert_register_p (struct gdbarch
*gdbarch
, int regnum
,
2570 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2572 return (tdep
->ppc_fp0_regnum
>= 0
2573 && regnum
>= tdep
->ppc_fp0_regnum
2574 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
2575 && TYPE_CODE (type
) == TYPE_CODE_FLT
2576 && TYPE_LENGTH (type
)
2577 != TYPE_LENGTH (builtin_type (gdbarch
)->builtin_double
));
2581 rs6000_register_to_value (struct frame_info
*frame
,
2585 int *optimizedp
, int *unavailablep
)
2587 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2588 gdb_byte from
[MAX_REGISTER_SIZE
];
2590 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
2592 if (!get_frame_register_bytes (frame
, regnum
, 0,
2593 register_size (gdbarch
, regnum
),
2594 from
, optimizedp
, unavailablep
))
2597 convert_typed_floating (from
, builtin_type (gdbarch
)->builtin_double
,
2599 *optimizedp
= *unavailablep
= 0;
2604 rs6000_value_to_register (struct frame_info
*frame
,
2607 const gdb_byte
*from
)
2609 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2610 gdb_byte to
[MAX_REGISTER_SIZE
];
2612 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
2614 convert_typed_floating (from
, type
,
2615 to
, builtin_type (gdbarch
)->builtin_double
);
2616 put_frame_register (frame
, regnum
, to
);
2619 /* The type of a function that moves the value of REG between CACHE
2620 or BUF --- in either direction. */
2621 typedef enum register_status (*move_ev_register_func
) (struct regcache
*,
2624 /* Move SPE vector register values between a 64-bit buffer and the two
2625 32-bit raw register halves in a regcache. This function handles
2626 both splitting a 64-bit value into two 32-bit halves, and joining
2627 two halves into a whole 64-bit value, depending on the function
2628 passed as the MOVE argument.
2630 EV_REG must be the number of an SPE evN vector register --- a
2631 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2634 Call MOVE once for each 32-bit half of that register, passing
2635 REGCACHE, the number of the raw register corresponding to that
2636 half, and the address of the appropriate half of BUFFER.
2638 For example, passing 'regcache_raw_read' as the MOVE function will
2639 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2640 'regcache_raw_supply' will supply the contents of BUFFER to the
2641 appropriate pair of raw registers in REGCACHE.
2643 You may need to cast away some 'const' qualifiers when passing
2644 MOVE, since this function can't tell at compile-time which of
2645 REGCACHE or BUFFER is acting as the source of the data. If C had
2646 co-variant type qualifiers, ... */
2648 static enum register_status
2649 e500_move_ev_register (move_ev_register_func move
,
2650 struct regcache
*regcache
, int ev_reg
, void *buffer
)
2652 struct gdbarch
*arch
= get_regcache_arch (regcache
);
2653 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
2655 gdb_byte
*byte_buffer
= buffer
;
2656 enum register_status status
;
2658 gdb_assert (IS_SPE_PSEUDOREG (tdep
, ev_reg
));
2660 reg_index
= ev_reg
- tdep
->ppc_ev0_regnum
;
2662 if (gdbarch_byte_order (arch
) == BFD_ENDIAN_BIG
)
2664 status
= move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2666 if (status
== REG_VALID
)
2667 status
= move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
,
2672 status
= move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
, byte_buffer
);
2673 if (status
== REG_VALID
)
2674 status
= move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2681 static enum register_status
2682 do_regcache_raw_read (struct regcache
*regcache
, int regnum
, void *buffer
)
2684 return regcache_raw_read (regcache
, regnum
, buffer
);
2687 static enum register_status
2688 do_regcache_raw_write (struct regcache
*regcache
, int regnum
, void *buffer
)
2690 regcache_raw_write (regcache
, regnum
, buffer
);
2695 static enum register_status
2696 e500_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2697 int reg_nr
, gdb_byte
*buffer
)
2699 return e500_move_ev_register (do_regcache_raw_read
, regcache
, reg_nr
, buffer
);
2703 e500_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2704 int reg_nr
, const gdb_byte
*buffer
)
2706 e500_move_ev_register (do_regcache_raw_write
, regcache
,
2707 reg_nr
, (void *) buffer
);
2710 /* Read method for DFP pseudo-registers. */
2711 static enum register_status
2712 dfp_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2713 int reg_nr
, gdb_byte
*buffer
)
2715 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2716 int reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2717 enum register_status status
;
2719 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2721 /* Read two FP registers to form a whole dl register. */
2722 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2723 2 * reg_index
, buffer
);
2724 if (status
== REG_VALID
)
2725 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2726 2 * reg_index
+ 1, buffer
+ 8);
2730 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2731 2 * reg_index
+ 1, buffer
);
2732 if (status
== REG_VALID
)
2733 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2734 2 * reg_index
, buffer
+ 8);
2740 /* Write method for DFP pseudo-registers. */
2742 dfp_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2743 int reg_nr
, const gdb_byte
*buffer
)
2745 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2746 int reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2748 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2750 /* Write each half of the dl register into a separate
2752 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2753 2 * reg_index
, buffer
);
2754 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2755 2 * reg_index
+ 1, buffer
+ 8);
2759 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2760 2 * reg_index
+ 1, buffer
);
2761 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2762 2 * reg_index
, buffer
+ 8);
2766 /* Read method for POWER7 VSX pseudo-registers. */
2767 static enum register_status
2768 vsx_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2769 int reg_nr
, gdb_byte
*buffer
)
2771 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2772 int reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2773 enum register_status status
;
2775 /* Read the portion that overlaps the VMX registers. */
2777 status
= regcache_raw_read (regcache
, tdep
->ppc_vr0_regnum
+
2778 reg_index
- 32, buffer
);
2780 /* Read the portion that overlaps the FPR registers. */
2781 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2783 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2785 if (status
== REG_VALID
)
2786 status
= regcache_raw_read (regcache
, tdep
->ppc_vsr0_upper_regnum
+
2787 reg_index
, buffer
+ 8);
2791 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2792 reg_index
, buffer
+ 8);
2793 if (status
== REG_VALID
)
2794 status
= regcache_raw_read (regcache
, tdep
->ppc_vsr0_upper_regnum
+
2801 /* Write method for POWER7 VSX pseudo-registers. */
2803 vsx_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2804 int reg_nr
, const gdb_byte
*buffer
)
2806 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2807 int reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2809 /* Write the portion that overlaps the VMX registers. */
2811 regcache_raw_write (regcache
, tdep
->ppc_vr0_regnum
+
2812 reg_index
- 32, buffer
);
2814 /* Write the portion that overlaps the FPR registers. */
2815 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2817 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2819 regcache_raw_write (regcache
, tdep
->ppc_vsr0_upper_regnum
+
2820 reg_index
, buffer
+ 8);
2824 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2825 reg_index
, buffer
+ 8);
2826 regcache_raw_write (regcache
, tdep
->ppc_vsr0_upper_regnum
+
2831 /* Read method for POWER7 Extended FP pseudo-registers. */
2832 static enum register_status
2833 efpr_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2834 int reg_nr
, gdb_byte
*buffer
)
2836 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2837 int reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
2838 int offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 0 : 8;
2840 /* Read the portion that overlaps the VMX register. */
2841 return regcache_raw_read_part (regcache
, tdep
->ppc_vr0_regnum
+ reg_index
,
2842 offset
, register_size (gdbarch
, reg_nr
),
2846 /* Write method for POWER7 Extended FP pseudo-registers. */
2848 efpr_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2849 int reg_nr
, const gdb_byte
*buffer
)
2851 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2852 int reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
2853 int offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 0 : 8;
2855 /* Write the portion that overlaps the VMX register. */
2856 regcache_raw_write_part (regcache
, tdep
->ppc_vr0_regnum
+ reg_index
,
2857 offset
, register_size (gdbarch
, reg_nr
),
2861 static enum register_status
2862 rs6000_pseudo_register_read (struct gdbarch
*gdbarch
,
2863 struct regcache
*regcache
,
2864 int reg_nr
, gdb_byte
*buffer
)
2866 struct gdbarch
*regcache_arch
= get_regcache_arch (regcache
);
2867 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2869 gdb_assert (regcache_arch
== gdbarch
);
2871 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2872 return e500_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2873 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2874 return dfp_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2875 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2876 return vsx_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2877 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
2878 return efpr_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2880 internal_error (__FILE__
, __LINE__
,
2881 _("rs6000_pseudo_register_read: "
2882 "called on unexpected register '%s' (%d)"),
2883 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2887 rs6000_pseudo_register_write (struct gdbarch
*gdbarch
,
2888 struct regcache
*regcache
,
2889 int reg_nr
, const gdb_byte
*buffer
)
2891 struct gdbarch
*regcache_arch
= get_regcache_arch (regcache
);
2892 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2894 gdb_assert (regcache_arch
== gdbarch
);
2896 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2897 e500_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2898 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2899 dfp_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2900 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2901 vsx_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2902 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
2903 efpr_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2905 internal_error (__FILE__
, __LINE__
,
2906 _("rs6000_pseudo_register_write: "
2907 "called on unexpected register '%s' (%d)"),
2908 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2911 /* Convert a DBX STABS register number to a GDB register number. */
2913 rs6000_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
2915 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2917 if (0 <= num
&& num
<= 31)
2918 return tdep
->ppc_gp0_regnum
+ num
;
2919 else if (32 <= num
&& num
<= 63)
2920 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2921 specifies registers the architecture doesn't have? Our
2922 callers don't check the value we return. */
2923 return tdep
->ppc_fp0_regnum
+ (num
- 32);
2924 else if (77 <= num
&& num
<= 108)
2925 return tdep
->ppc_vr0_regnum
+ (num
- 77);
2926 else if (1200 <= num
&& num
< 1200 + 32)
2927 return tdep
->ppc_ev0_upper_regnum
+ (num
- 1200);
2932 return tdep
->ppc_mq_regnum
;
2934 return tdep
->ppc_lr_regnum
;
2936 return tdep
->ppc_ctr_regnum
;
2938 return tdep
->ppc_xer_regnum
;
2940 return tdep
->ppc_vrsave_regnum
;
2942 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
2944 return tdep
->ppc_acc_regnum
;
2946 return tdep
->ppc_spefscr_regnum
;
2953 /* Convert a Dwarf 2 register number to a GDB register number. */
2955 rs6000_dwarf2_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
2957 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2959 if (0 <= num
&& num
<= 31)
2960 return tdep
->ppc_gp0_regnum
+ num
;
2961 else if (32 <= num
&& num
<= 63)
2962 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2963 specifies registers the architecture doesn't have? Our
2964 callers don't check the value we return. */
2965 return tdep
->ppc_fp0_regnum
+ (num
- 32);
2966 else if (1124 <= num
&& num
< 1124 + 32)
2967 return tdep
->ppc_vr0_regnum
+ (num
- 1124);
2968 else if (1200 <= num
&& num
< 1200 + 32)
2969 return tdep
->ppc_ev0_upper_regnum
+ (num
- 1200);
2974 return tdep
->ppc_cr_regnum
;
2976 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
2978 return tdep
->ppc_acc_regnum
;
2980 return tdep
->ppc_mq_regnum
;
2982 return tdep
->ppc_xer_regnum
;
2984 return tdep
->ppc_lr_regnum
;
2986 return tdep
->ppc_ctr_regnum
;
2988 return tdep
->ppc_vrsave_regnum
;
2990 return tdep
->ppc_spefscr_regnum
;
2996 /* Translate a .eh_frame register to DWARF register, or adjust a
2997 .debug_frame register. */
3000 rs6000_adjust_frame_regnum (struct gdbarch
*gdbarch
, int num
, int eh_frame_p
)
3002 /* GCC releases before 3.4 use GCC internal register numbering in
3003 .debug_frame (and .debug_info, et cetera). The numbering is
3004 different from the standard SysV numbering for everything except
3005 for GPRs and FPRs. We can not detect this problem in most cases
3006 - to get accurate debug info for variables living in lr, ctr, v0,
3007 et cetera, use a newer version of GCC. But we must detect
3008 one important case - lr is in column 65 in .debug_frame output,
3011 GCC 3.4, and the "hammer" branch, have a related problem. They
3012 record lr register saves in .debug_frame as 108, but still record
3013 the return column as 65. We fix that up too.
3015 We can do this because 65 is assigned to fpsr, and GCC never
3016 generates debug info referring to it. To add support for
3017 handwritten debug info that restores fpsr, we would need to add a
3018 producer version check to this. */
3027 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
3028 internal register numbering; translate that to the standard DWARF2
3029 register numbering. */
3030 if (0 <= num
&& num
<= 63) /* r0-r31,fp0-fp31 */
3032 else if (68 <= num
&& num
<= 75) /* cr0-cr8 */
3033 return num
- 68 + 86;
3034 else if (77 <= num
&& num
<= 108) /* vr0-vr31 */
3035 return num
- 77 + 1124;
3047 case 109: /* vrsave */
3049 case 110: /* vscr */
3051 case 111: /* spe_acc */
3053 case 112: /* spefscr */
3061 /* Handling the various POWER/PowerPC variants. */
3063 /* Information about a particular processor variant. */
3067 /* Name of this variant. */
3070 /* English description of the variant. */
3073 /* bfd_arch_info.arch corresponding to variant. */
3074 enum bfd_architecture arch
;
3076 /* bfd_arch_info.mach corresponding to variant. */
3079 /* Target description for this variant. */
3080 struct target_desc
**tdesc
;
3083 static struct variant variants
[] =
3085 {"powerpc", "PowerPC user-level", bfd_arch_powerpc
,
3086 bfd_mach_ppc
, &tdesc_powerpc_altivec32
},
3087 {"power", "POWER user-level", bfd_arch_rs6000
,
3088 bfd_mach_rs6k
, &tdesc_rs6000
},
3089 {"403", "IBM PowerPC 403", bfd_arch_powerpc
,
3090 bfd_mach_ppc_403
, &tdesc_powerpc_403
},
3091 {"405", "IBM PowerPC 405", bfd_arch_powerpc
,
3092 bfd_mach_ppc_405
, &tdesc_powerpc_405
},
3093 {"601", "Motorola PowerPC 601", bfd_arch_powerpc
,
3094 bfd_mach_ppc_601
, &tdesc_powerpc_601
},
3095 {"602", "Motorola PowerPC 602", bfd_arch_powerpc
,
3096 bfd_mach_ppc_602
, &tdesc_powerpc_602
},
3097 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc
,
3098 bfd_mach_ppc_603
, &tdesc_powerpc_603
},
3099 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc
,
3100 604, &tdesc_powerpc_604
},
3101 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc
,
3102 bfd_mach_ppc_403gc
, &tdesc_powerpc_403gc
},
3103 {"505", "Motorola PowerPC 505", bfd_arch_powerpc
,
3104 bfd_mach_ppc_505
, &tdesc_powerpc_505
},
3105 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc
,
3106 bfd_mach_ppc_860
, &tdesc_powerpc_860
},
3107 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc
,
3108 bfd_mach_ppc_750
, &tdesc_powerpc_750
},
3109 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc
,
3110 bfd_mach_ppc_7400
, &tdesc_powerpc_7400
},
3111 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc
,
3112 bfd_mach_ppc_e500
, &tdesc_powerpc_e500
},
3115 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc
,
3116 bfd_mach_ppc64
, &tdesc_powerpc_altivec64
},
3117 {"620", "Motorola PowerPC 620", bfd_arch_powerpc
,
3118 bfd_mach_ppc_620
, &tdesc_powerpc_64
},
3119 {"630", "Motorola PowerPC 630", bfd_arch_powerpc
,
3120 bfd_mach_ppc_630
, &tdesc_powerpc_64
},
3121 {"a35", "PowerPC A35", bfd_arch_powerpc
,
3122 bfd_mach_ppc_a35
, &tdesc_powerpc_64
},
3123 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc
,
3124 bfd_mach_ppc_rs64ii
, &tdesc_powerpc_64
},
3125 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc
,
3126 bfd_mach_ppc_rs64iii
, &tdesc_powerpc_64
},
3128 /* FIXME: I haven't checked the register sets of the following. */
3129 {"rs1", "IBM POWER RS1", bfd_arch_rs6000
,
3130 bfd_mach_rs6k_rs1
, &tdesc_rs6000
},
3131 {"rsc", "IBM POWER RSC", bfd_arch_rs6000
,
3132 bfd_mach_rs6k_rsc
, &tdesc_rs6000
},
3133 {"rs2", "IBM POWER RS2", bfd_arch_rs6000
,
3134 bfd_mach_rs6k_rs2
, &tdesc_rs6000
},
3139 /* Return the variant corresponding to architecture ARCH and machine number
3140 MACH. If no such variant exists, return null. */
3142 static const struct variant
*
3143 find_variant_by_arch (enum bfd_architecture arch
, unsigned long mach
)
3145 const struct variant
*v
;
3147 for (v
= variants
; v
->name
; v
++)
3148 if (arch
== v
->arch
&& mach
== v
->mach
)
3155 gdb_print_insn_powerpc (bfd_vma memaddr
, disassemble_info
*info
)
3157 if (info
->endian
== BFD_ENDIAN_BIG
)
3158 return print_insn_big_powerpc (memaddr
, info
);
3160 return print_insn_little_powerpc (memaddr
, info
);
3164 rs6000_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
3166 return frame_unwind_register_unsigned (next_frame
,
3167 gdbarch_pc_regnum (gdbarch
));
3170 static struct frame_id
3171 rs6000_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3173 return frame_id_build (get_frame_register_unsigned
3174 (this_frame
, gdbarch_sp_regnum (gdbarch
)),
3175 get_frame_pc (this_frame
));
3178 struct rs6000_frame_cache
3181 CORE_ADDR initial_sp
;
3182 struct trad_frame_saved_reg
*saved_regs
;
3185 static struct rs6000_frame_cache
*
3186 rs6000_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3188 struct rs6000_frame_cache
*cache
;
3189 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3190 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3191 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3192 struct rs6000_framedata fdata
;
3193 int wordsize
= tdep
->wordsize
;
3196 if ((*this_cache
) != NULL
)
3197 return (*this_cache
);
3198 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
3199 (*this_cache
) = cache
;
3200 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3202 func
= get_frame_func (this_frame
);
3203 pc
= get_frame_pc (this_frame
);
3204 skip_prologue (gdbarch
, func
, pc
, &fdata
);
3206 /* Figure out the parent's stack pointer. */
3208 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
3209 address of the current frame. Things might be easier if the
3210 ->frame pointed to the outer-most address of the frame. In
3211 the mean time, the address of the prev frame is used as the
3212 base address of this frame. */
3213 cache
->base
= get_frame_register_unsigned
3214 (this_frame
, gdbarch_sp_regnum (gdbarch
));
3216 /* If the function appears to be frameless, check a couple of likely
3217 indicators that we have simply failed to find the frame setup.
3218 Two common cases of this are missing symbols (i.e.
3219 get_frame_func returns the wrong address or 0), and assembly
3220 stubs which have a fast exit path but set up a frame on the slow
3223 If the LR appears to return to this function, then presume that
3224 we have an ABI compliant frame that we failed to find. */
3225 if (fdata
.frameless
&& fdata
.lr_offset
== 0)
3230 saved_lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
3231 if (func
== 0 && saved_lr
== pc
)
3235 CORE_ADDR saved_func
= get_pc_function_start (saved_lr
);
3236 if (func
== saved_func
)
3242 fdata
.frameless
= 0;
3243 fdata
.lr_offset
= tdep
->lr_frame_offset
;
3247 if (!fdata
.frameless
)
3249 /* Frameless really means stackless. */
3252 if (safe_read_memory_integer (cache
->base
, wordsize
,
3253 byte_order
, &backchain
))
3254 cache
->base
= (CORE_ADDR
) backchain
;
3257 trad_frame_set_value (cache
->saved_regs
,
3258 gdbarch_sp_regnum (gdbarch
), cache
->base
);
3260 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
3261 All fpr's from saved_fpr to fp31 are saved. */
3263 if (fdata
.saved_fpr
>= 0)
3266 CORE_ADDR fpr_addr
= cache
->base
+ fdata
.fpr_offset
;
3268 /* If skip_prologue says floating-point registers were saved,
3269 but the current architecture has no floating-point registers,
3270 then that's strange. But we have no indices to even record
3271 the addresses under, so we just ignore it. */
3272 if (ppc_floating_point_unit_p (gdbarch
))
3273 for (i
= fdata
.saved_fpr
; i
< ppc_num_fprs
; i
++)
3275 cache
->saved_regs
[tdep
->ppc_fp0_regnum
+ i
].addr
= fpr_addr
;
3280 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
3281 All gpr's from saved_gpr to gpr31 are saved (except during the
3284 if (fdata
.saved_gpr
>= 0)
3287 CORE_ADDR gpr_addr
= cache
->base
+ fdata
.gpr_offset
;
3288 for (i
= fdata
.saved_gpr
; i
< ppc_num_gprs
; i
++)
3290 if (fdata
.gpr_mask
& (1U << i
))
3291 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= gpr_addr
;
3292 gpr_addr
+= wordsize
;
3296 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
3297 All vr's from saved_vr to vr31 are saved. */
3298 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
3300 if (fdata
.saved_vr
>= 0)
3303 CORE_ADDR vr_addr
= cache
->base
+ fdata
.vr_offset
;
3304 for (i
= fdata
.saved_vr
; i
< 32; i
++)
3306 cache
->saved_regs
[tdep
->ppc_vr0_regnum
+ i
].addr
= vr_addr
;
3307 vr_addr
+= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
3312 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
3313 All vr's from saved_ev to ev31 are saved. ????? */
3314 if (tdep
->ppc_ev0_regnum
!= -1)
3316 if (fdata
.saved_ev
>= 0)
3319 CORE_ADDR ev_addr
= cache
->base
+ fdata
.ev_offset
;
3320 CORE_ADDR off
= (byte_order
== BFD_ENDIAN_BIG
? 4 : 0);
3322 for (i
= fdata
.saved_ev
; i
< ppc_num_gprs
; i
++)
3324 cache
->saved_regs
[tdep
->ppc_ev0_regnum
+ i
].addr
= ev_addr
;
3325 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= ev_addr
+ off
;
3326 ev_addr
+= register_size (gdbarch
, tdep
->ppc_ev0_regnum
);
3331 /* If != 0, fdata.cr_offset is the offset from the frame that
3333 if (fdata
.cr_offset
!= 0)
3334 cache
->saved_regs
[tdep
->ppc_cr_regnum
].addr
3335 = cache
->base
+ fdata
.cr_offset
;
3337 /* If != 0, fdata.lr_offset is the offset from the frame that
3339 if (fdata
.lr_offset
!= 0)
3340 cache
->saved_regs
[tdep
->ppc_lr_regnum
].addr
3341 = cache
->base
+ fdata
.lr_offset
;
3342 else if (fdata
.lr_register
!= -1)
3343 cache
->saved_regs
[tdep
->ppc_lr_regnum
].realreg
= fdata
.lr_register
;
3344 /* The PC is found in the link register. */
3345 cache
->saved_regs
[gdbarch_pc_regnum (gdbarch
)] =
3346 cache
->saved_regs
[tdep
->ppc_lr_regnum
];
3348 /* If != 0, fdata.vrsave_offset is the offset from the frame that
3349 holds the VRSAVE. */
3350 if (fdata
.vrsave_offset
!= 0)
3351 cache
->saved_regs
[tdep
->ppc_vrsave_regnum
].addr
3352 = cache
->base
+ fdata
.vrsave_offset
;
3354 if (fdata
.alloca_reg
< 0)
3355 /* If no alloca register used, then fi->frame is the value of the
3356 %sp for this frame, and it is good enough. */
3358 = get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
3361 = get_frame_register_unsigned (this_frame
, fdata
.alloca_reg
);
3367 rs6000_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3368 struct frame_id
*this_id
)
3370 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3372 /* This marks the outermost frame. */
3373 if (info
->base
== 0)
3376 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3379 static struct value
*
3380 rs6000_frame_prev_register (struct frame_info
*this_frame
,
3381 void **this_cache
, int regnum
)
3383 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3385 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3388 static const struct frame_unwind rs6000_frame_unwind
=
3391 default_frame_unwind_stop_reason
,
3392 rs6000_frame_this_id
,
3393 rs6000_frame_prev_register
,
3395 default_frame_sniffer
3398 /* Allocate and initialize a frame cache for an epilogue frame.
3399 SP is restored and prev-PC is stored in LR. */
3401 static struct rs6000_frame_cache
*
3402 rs6000_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3404 struct rs6000_frame_cache
*cache
;
3405 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3406 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3411 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
3412 (*this_cache
) = cache
;
3413 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3417 /* At this point the stack looks as if we just entered the
3418 function, and the return address is stored in LR. */
3421 sp
= get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
3422 lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
3425 cache
->initial_sp
= sp
;
3427 trad_frame_set_value (cache
->saved_regs
,
3428 gdbarch_pc_regnum (gdbarch
), lr
);
3430 CATCH (ex
, RETURN_MASK_ERROR
)
3432 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
3433 throw_exception (ex
);
3440 /* Implementation of frame_unwind.this_id, as defined in frame_unwind.h.
3441 Return the frame ID of an epilogue frame. */
3444 rs6000_epilogue_frame_this_id (struct frame_info
*this_frame
,
3445 void **this_cache
, struct frame_id
*this_id
)
3448 struct rs6000_frame_cache
*info
=
3449 rs6000_epilogue_frame_cache (this_frame
, this_cache
);
3451 pc
= get_frame_func (this_frame
);
3452 if (info
->base
== 0)
3453 (*this_id
) = frame_id_build_unavailable_stack (pc
);
3455 (*this_id
) = frame_id_build (info
->base
, pc
);
3458 /* Implementation of frame_unwind.prev_register, as defined in frame_unwind.h.
3459 Return the register value of REGNUM in previous frame. */
3461 static struct value
*
3462 rs6000_epilogue_frame_prev_register (struct frame_info
*this_frame
,
3463 void **this_cache
, int regnum
)
3465 struct rs6000_frame_cache
*info
=
3466 rs6000_epilogue_frame_cache (this_frame
, this_cache
);
3467 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3470 /* Implementation of frame_unwind.sniffer, as defined in frame_unwind.h.
3471 Check whether this an epilogue frame. */
3474 rs6000_epilogue_frame_sniffer (const struct frame_unwind
*self
,
3475 struct frame_info
*this_frame
,
3476 void **this_prologue_cache
)
3478 if (frame_relative_level (this_frame
) == 0)
3479 return rs6000_in_function_epilogue_frame_p (this_frame
,
3480 get_frame_arch (this_frame
),
3481 get_frame_pc (this_frame
));
3486 /* Frame unwinder for epilogue frame. This is required for reverse step-over
3487 a function without debug information. */
3489 static const struct frame_unwind rs6000_epilogue_frame_unwind
=
3492 default_frame_unwind_stop_reason
,
3493 rs6000_epilogue_frame_this_id
, rs6000_epilogue_frame_prev_register
,
3495 rs6000_epilogue_frame_sniffer
3500 rs6000_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
3502 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3504 return info
->initial_sp
;
3507 static const struct frame_base rs6000_frame_base
= {
3508 &rs6000_frame_unwind
,
3509 rs6000_frame_base_address
,
3510 rs6000_frame_base_address
,
3511 rs6000_frame_base_address
3514 static const struct frame_base
*
3515 rs6000_frame_base_sniffer (struct frame_info
*this_frame
)
3517 return &rs6000_frame_base
;
3520 /* DWARF-2 frame support. Used to handle the detection of
3521 clobbered registers during function calls. */
3524 ppc_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
3525 struct dwarf2_frame_state_reg
*reg
,
3526 struct frame_info
*this_frame
)
3528 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3530 /* PPC32 and PPC64 ABI's are the same regarding volatile and
3531 non-volatile registers. We will use the same code for both. */
3533 /* Call-saved GP registers. */
3534 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 14
3535 && regnum
<= tdep
->ppc_gp0_regnum
+ 31)
3536 || (regnum
== tdep
->ppc_gp0_regnum
+ 1))
3537 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3539 /* Call-clobbered GP registers. */
3540 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 3
3541 && regnum
<= tdep
->ppc_gp0_regnum
+ 12)
3542 || (regnum
== tdep
->ppc_gp0_regnum
))
3543 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3545 /* Deal with FP registers, if supported. */
3546 if (tdep
->ppc_fp0_regnum
>= 0)
3548 /* Call-saved FP registers. */
3549 if ((regnum
>= tdep
->ppc_fp0_regnum
+ 14
3550 && regnum
<= tdep
->ppc_fp0_regnum
+ 31))
3551 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3553 /* Call-clobbered FP registers. */
3554 if ((regnum
>= tdep
->ppc_fp0_regnum
3555 && regnum
<= tdep
->ppc_fp0_regnum
+ 13))
3556 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3559 /* Deal with ALTIVEC registers, if supported. */
3560 if (tdep
->ppc_vr0_regnum
> 0 && tdep
->ppc_vrsave_regnum
> 0)
3562 /* Call-saved Altivec registers. */
3563 if ((regnum
>= tdep
->ppc_vr0_regnum
+ 20
3564 && regnum
<= tdep
->ppc_vr0_regnum
+ 31)
3565 || regnum
== tdep
->ppc_vrsave_regnum
)
3566 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3568 /* Call-clobbered Altivec registers. */
3569 if ((regnum
>= tdep
->ppc_vr0_regnum
3570 && regnum
<= tdep
->ppc_vr0_regnum
+ 19))
3571 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3574 /* Handle PC register and Stack Pointer correctly. */
3575 if (regnum
== gdbarch_pc_regnum (gdbarch
))
3576 reg
->how
= DWARF2_FRAME_REG_RA
;
3577 else if (regnum
== gdbarch_sp_regnum (gdbarch
))
3578 reg
->how
= DWARF2_FRAME_REG_CFA
;
3582 /* Return true if a .gnu_attributes section exists in BFD and it
3583 indicates we are using SPE extensions OR if a .PPC.EMB.apuinfo
3584 section exists in BFD and it indicates that SPE extensions are in
3585 use. Check the .gnu.attributes section first, as the binary might be
3586 compiled for SPE, but not actually using SPE instructions. */
3589 bfd_uses_spe_extensions (bfd
*abfd
)
3592 gdb_byte
*contents
= NULL
;
3602 /* Using Tag_GNU_Power_ABI_Vector here is a bit of a hack, as the user
3603 could be using the SPE vector abi without actually using any spe
3604 bits whatsoever. But it's close enough for now. */
3605 vector_abi
= bfd_elf_get_obj_attr_int (abfd
, OBJ_ATTR_GNU
,
3606 Tag_GNU_Power_ABI_Vector
);
3607 if (vector_abi
== 3)
3611 sect
= bfd_get_section_by_name (abfd
, ".PPC.EMB.apuinfo");
3615 size
= bfd_get_section_size (sect
);
3616 contents
= xmalloc (size
);
3617 if (!bfd_get_section_contents (abfd
, sect
, contents
, 0, size
))
3623 /* Parse the .PPC.EMB.apuinfo section. The layout is as follows:
3629 char name[name_len rounded up to 4-byte alignment];
3630 char data[data_len];
3633 Technically, there's only supposed to be one such structure in a
3634 given apuinfo section, but the linker is not always vigilant about
3635 merging apuinfo sections from input files. Just go ahead and parse
3636 them all, exiting early when we discover the binary uses SPE
3639 It's not specified in what endianness the information in this
3640 section is stored. Assume that it's the endianness of the BFD. */
3644 unsigned int name_len
;
3645 unsigned int data_len
;
3648 /* If we can't read the first three fields, we're done. */
3652 name_len
= bfd_get_32 (abfd
, ptr
);
3653 name_len
= (name_len
+ 3) & ~3U; /* Round to 4 bytes. */
3654 data_len
= bfd_get_32 (abfd
, ptr
+ 4);
3655 type
= bfd_get_32 (abfd
, ptr
+ 8);
3658 /* The name must be "APUinfo\0". */
3660 && strcmp ((const char *) ptr
, "APUinfo") != 0)
3664 /* The type must be 2. */
3668 /* The data is stored as a series of uint32. The upper half of
3669 each uint32 indicates the particular APU used and the lower
3670 half indicates the revision of that APU. We just care about
3673 /* Not 4-byte quantities. */
3679 unsigned int apuinfo
= bfd_get_32 (abfd
, ptr
);
3680 unsigned int apu
= apuinfo
>> 16;
3684 /* The SPE APU is 0x100; the SPEFP APU is 0x101. Accept
3686 if (apu
== 0x100 || apu
== 0x101)
3701 /* These are macros for parsing instruction fields (I.1.6.28) */
3703 #define PPC_FIELD(value, from, len) \
3704 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
3705 #define PPC_SEXT(v, bs) \
3706 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
3707 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
3708 - ((CORE_ADDR) 1 << ((bs) - 1)))
3709 #define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
3710 #define PPC_EXTOP(insn) PPC_FIELD (insn, 21, 10)
3711 #define PPC_RT(insn) PPC_FIELD (insn, 6, 5)
3712 #define PPC_RS(insn) PPC_FIELD (insn, 6, 5)
3713 #define PPC_RA(insn) PPC_FIELD (insn, 11, 5)
3714 #define PPC_RB(insn) PPC_FIELD (insn, 16, 5)
3715 #define PPC_NB(insn) PPC_FIELD (insn, 16, 5)
3716 #define PPC_VRT(insn) PPC_FIELD (insn, 6, 5)
3717 #define PPC_FRT(insn) PPC_FIELD (insn, 6, 5)
3718 #define PPC_SPR(insn) (PPC_FIELD (insn, 11, 5) \
3719 | (PPC_FIELD (insn, 16, 5) << 5))
3720 #define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
3721 #define PPC_T(insn) PPC_FIELD (insn, 6, 5)
3722 #define PPC_D(insn) PPC_SEXT (PPC_FIELD (insn, 16, 16), 16)
3723 #define PPC_DS(insn) PPC_SEXT (PPC_FIELD (insn, 16, 14), 14)
3724 #define PPC_BIT(insn,n) ((insn & (1 << (31 - (n)))) ? 1 : 0)
3725 #define PPC_OE(insn) PPC_BIT (insn, 21)
3726 #define PPC_RC(insn) PPC_BIT (insn, 31)
3727 #define PPC_Rc(insn) PPC_BIT (insn, 21)
3728 #define PPC_LK(insn) PPC_BIT (insn, 31)
3729 #define PPC_TX(insn) PPC_BIT (insn, 31)
3730 #define PPC_LEV(insn) PPC_FIELD (insn, 20, 7)
3732 #define PPC_XT(insn) ((PPC_TX (insn) << 5) | PPC_T (insn))
3733 #define PPC_XER_NB(xer) (xer & 0x7f)
3735 /* Record Vector-Scalar Registers.
3736 For VSR less than 32, it's represented by an FPR and an VSR-upper register.
3737 Otherwise, it's just a VR register. Record them accordingly. */
3740 ppc_record_vsr (struct regcache
*regcache
, struct gdbarch_tdep
*tdep
, int vsr
)
3742 if (vsr
< 0 || vsr
>= 64)
3747 if (tdep
->ppc_vr0_regnum
>= 0)
3748 record_full_arch_list_add_reg (regcache
, tdep
->ppc_vr0_regnum
+ vsr
- 32);
3752 if (tdep
->ppc_fp0_regnum
>= 0)
3753 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fp0_regnum
+ vsr
);
3754 if (tdep
->ppc_vsr0_upper_regnum
>= 0)
3755 record_full_arch_list_add_reg (regcache
,
3756 tdep
->ppc_vsr0_upper_regnum
+ vsr
);
3762 /* Parse and record instructions primary opcode-4 at ADDR.
3763 Return 0 if successful. */
3766 ppc_process_record_op4 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3767 CORE_ADDR addr
, uint32_t insn
)
3769 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3770 int ext
= PPC_FIELD (insn
, 21, 11);
3774 case 32: /* Vector Multiply-High-Add Signed Halfword Saturate */
3775 case 33: /* Vector Multiply-High-Round-Add Signed Halfword Saturate */
3776 case 39: /* Vector Multiply-Sum Unsigned Halfword Saturate */
3777 case 41: /* Vector Multiply-Sum Signed Halfword Saturate */
3778 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
3780 case 42: /* Vector Select */
3781 case 43: /* Vector Permute */
3782 case 44: /* Vector Shift Left Double by Octet Immediate */
3783 case 45: /* Vector Permute and Exclusive-OR */
3784 case 60: /* Vector Add Extended Unsigned Quadword Modulo */
3785 case 61: /* Vector Add Extended & write Carry Unsigned Quadword */
3786 case 62: /* Vector Subtract Extended Unsigned Quadword Modulo */
3787 case 63: /* Vector Subtract Extended & write Carry Unsigned Quadword */
3788 case 34: /* Vector Multiply-Low-Add Unsigned Halfword Modulo */
3789 case 36: /* Vector Multiply-Sum Unsigned Byte Modulo */
3790 case 37: /* Vector Multiply-Sum Mixed Byte Modulo */
3791 case 38: /* Vector Multiply-Sum Unsigned Halfword Modulo */
3792 case 40: /* Vector Multiply-Sum Signed Halfword Modulo */
3793 case 46: /* Vector Multiply-Add Single-Precision */
3794 case 47: /* Vector Negative Multiply-Subtract Single-Precision */
3795 record_full_arch_list_add_reg (regcache
,
3796 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
3800 switch ((ext
& 0x1ff))
3802 /* 5.16 Decimal Integer Arithmetic Instructions */
3803 case 1: /* Decimal Add Modulo */
3804 case 65: /* Decimal Subtract Modulo */
3806 /* Bit-21 should be set. */
3807 if (!PPC_BIT (insn
, 21))
3810 record_full_arch_list_add_reg (regcache
,
3811 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
3812 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
3816 /* Bit-21 is used for RC */
3817 switch (ext
& 0x3ff)
3819 case 6: /* Vector Compare Equal To Unsigned Byte */
3820 case 70: /* Vector Compare Equal To Unsigned Halfword */
3821 case 134: /* Vector Compare Equal To Unsigned Word */
3822 case 199: /* Vector Compare Equal To Unsigned Doubleword */
3823 case 774: /* Vector Compare Greater Than Signed Byte */
3824 case 838: /* Vector Compare Greater Than Signed Halfword */
3825 case 902: /* Vector Compare Greater Than Signed Word */
3826 case 967: /* Vector Compare Greater Than Signed Doubleword */
3827 case 518: /* Vector Compare Greater Than Unsigned Byte */
3828 case 646: /* Vector Compare Greater Than Unsigned Word */
3829 case 582: /* Vector Compare Greater Than Unsigned Halfword */
3830 case 711: /* Vector Compare Greater Than Unsigned Doubleword */
3831 case 966: /* Vector Compare Bounds Single-Precision */
3832 case 198: /* Vector Compare Equal To Single-Precision */
3833 case 454: /* Vector Compare Greater Than or Equal To Single-Precision */
3834 case 710: /* Vector Compare Greater Than Single-Precision */
3836 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
3837 record_full_arch_list_add_reg (regcache
,
3838 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
3844 case 142: /* Vector Pack Unsigned Halfword Unsigned Saturate */
3845 case 206: /* Vector Pack Unsigned Word Unsigned Saturate */
3846 case 270: /* Vector Pack Signed Halfword Unsigned Saturate */
3847 case 334: /* Vector Pack Signed Word Unsigned Saturate */
3848 case 398: /* Vector Pack Signed Halfword Signed Saturate */
3849 case 462: /* Vector Pack Signed Word Signed Saturate */
3850 case 1230: /* Vector Pack Unsigned Doubleword Unsigned Saturate */
3851 case 1358: /* Vector Pack Signed Doubleword Unsigned Saturate */
3852 case 1486: /* Vector Pack Signed Doubleword Signed Saturate */
3853 case 512: /* Vector Add Unsigned Byte Saturate */
3854 case 576: /* Vector Add Unsigned Halfword Saturate */
3855 case 640: /* Vector Add Unsigned Word Saturate */
3856 case 768: /* Vector Add Signed Byte Saturate */
3857 case 832: /* Vector Add Signed Halfword Saturate */
3858 case 896: /* Vector Add Signed Word Saturate */
3859 case 1536: /* Vector Subtract Unsigned Byte Saturate */
3860 case 1600: /* Vector Subtract Unsigned Halfword Saturate */
3861 case 1664: /* Vector Subtract Unsigned Word Saturate */
3862 case 1792: /* Vector Subtract Signed Byte Saturate */
3863 case 1856: /* Vector Subtract Signed Halfword Saturate */
3864 case 1920: /* Vector Subtract Signed Word Saturate */
3866 case 1544: /* Vector Sum across Quarter Unsigned Byte Saturate */
3867 case 1800: /* Vector Sum across Quarter Signed Byte Saturate */
3868 case 1608: /* Vector Sum across Quarter Signed Halfword Saturate */
3869 case 1672: /* Vector Sum across Half Signed Word Saturate */
3870 case 1928: /* Vector Sum across Signed Word Saturate */
3871 case 970: /* Vector Convert To Signed Fixed-Point Word Saturate */
3872 case 906: /* Vector Convert To Unsigned Fixed-Point Word Saturate */
3873 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
3875 case 12: /* Vector Merge High Byte */
3876 case 14: /* Vector Pack Unsigned Halfword Unsigned Modulo */
3877 case 76: /* Vector Merge High Halfword */
3878 case 78: /* Vector Pack Unsigned Word Unsigned Modulo */
3879 case 140: /* Vector Merge High Word */
3880 case 268: /* Vector Merge Low Byte */
3881 case 332: /* Vector Merge Low Halfword */
3882 case 396: /* Vector Merge Low Word */
3883 case 526: /* Vector Unpack High Signed Byte */
3884 case 590: /* Vector Unpack High Signed Halfword */
3885 case 654: /* Vector Unpack Low Signed Byte */
3886 case 718: /* Vector Unpack Low Signed Halfword */
3887 case 782: /* Vector Pack Pixel */
3888 case 846: /* Vector Unpack High Pixel */
3889 case 974: /* Vector Unpack Low Pixel */
3890 case 1102: /* Vector Pack Unsigned Doubleword Unsigned Modulo */
3891 case 1614: /* Vector Unpack High Signed Word */
3892 case 1676: /* Vector Merge Odd Word */
3893 case 1742: /* Vector Unpack Low Signed Word */
3894 case 1932: /* Vector Merge Even Word */
3895 case 524: /* Vector Splat Byte */
3896 case 588: /* Vector Splat Halfword */
3897 case 652: /* Vector Splat Word */
3898 case 780: /* Vector Splat Immediate Signed Byte */
3899 case 844: /* Vector Splat Immediate Signed Halfword */
3900 case 908: /* Vector Splat Immediate Signed Word */
3901 case 452: /* Vector Shift Left */
3902 case 708: /* Vector Shift Right */
3903 case 1036: /* Vector Shift Left by Octet */
3904 case 1100: /* Vector Shift Right by Octet */
3905 case 0: /* Vector Add Unsigned Byte Modulo */
3906 case 64: /* Vector Add Unsigned Halfword Modulo */
3907 case 128: /* Vector Add Unsigned Word Modulo */
3908 case 192: /* Vector Add Unsigned Doubleword Modulo */
3909 case 256: /* Vector Add Unsigned Quadword Modulo */
3910 case 320: /* Vector Add & write Carry Unsigned Quadword */
3911 case 384: /* Vector Add and Write Carry-Out Unsigned Word */
3912 case 8: /* Vector Multiply Odd Unsigned Byte */
3913 case 72: /* Vector Multiply Odd Unsigned Halfword */
3914 case 136: /* Vector Multiply Odd Unsigned Word */
3915 case 264: /* Vector Multiply Odd Signed Byte */
3916 case 328: /* Vector Multiply Odd Signed Halfword */
3917 case 392: /* Vector Multiply Odd Signed Word */
3918 case 520: /* Vector Multiply Even Unsigned Byte */
3919 case 584: /* Vector Multiply Even Unsigned Halfword */
3920 case 648: /* Vector Multiply Even Unsigned Word */
3921 case 776: /* Vector Multiply Even Signed Byte */
3922 case 840: /* Vector Multiply Even Signed Halfword */
3923 case 904: /* Vector Multiply Even Signed Word */
3924 case 137: /* Vector Multiply Unsigned Word Modulo */
3925 case 1024: /* Vector Subtract Unsigned Byte Modulo */
3926 case 1088: /* Vector Subtract Unsigned Halfword Modulo */
3927 case 1152: /* Vector Subtract Unsigned Word Modulo */
3928 case 1216: /* Vector Subtract Unsigned Doubleword Modulo */
3929 case 1280: /* Vector Subtract Unsigned Quadword Modulo */
3930 case 1344: /* Vector Subtract & write Carry Unsigned Quadword */
3931 case 1408: /* Vector Subtract and Write Carry-Out Unsigned Word */
3932 case 1282: /* Vector Average Signed Byte */
3933 case 1346: /* Vector Average Signed Halfword */
3934 case 1410: /* Vector Average Signed Word */
3935 case 1026: /* Vector Average Unsigned Byte */
3936 case 1090: /* Vector Average Unsigned Halfword */
3937 case 1154: /* Vector Average Unsigned Word */
3938 case 258: /* Vector Maximum Signed Byte */
3939 case 322: /* Vector Maximum Signed Halfword */
3940 case 386: /* Vector Maximum Signed Word */
3941 case 450: /* Vector Maximum Signed Doubleword */
3942 case 2: /* Vector Maximum Unsigned Byte */
3943 case 66: /* Vector Maximum Unsigned Halfword */
3944 case 130: /* Vector Maximum Unsigned Word */
3945 case 194: /* Vector Maximum Unsigned Doubleword */
3946 case 770: /* Vector Minimum Signed Byte */
3947 case 834: /* Vector Minimum Signed Halfword */
3948 case 898: /* Vector Minimum Signed Word */
3949 case 962: /* Vector Minimum Signed Doubleword */
3950 case 514: /* Vector Minimum Unsigned Byte */
3951 case 578: /* Vector Minimum Unsigned Halfword */
3952 case 642: /* Vector Minimum Unsigned Word */
3953 case 706: /* Vector Minimum Unsigned Doubleword */
3954 case 1028: /* Vector Logical AND */
3955 case 1668: /* Vector Logical Equivalent */
3956 case 1092: /* Vector Logical AND with Complement */
3957 case 1412: /* Vector Logical NAND */
3958 case 1348: /* Vector Logical OR with Complement */
3959 case 1156: /* Vector Logical OR */
3960 case 1284: /* Vector Logical NOR */
3961 case 1220: /* Vector Logical XOR */
3962 case 4: /* Vector Rotate Left Byte */
3963 case 132: /* Vector Rotate Left Word VX-form */
3964 case 68: /* Vector Rotate Left Halfword */
3965 case 196: /* Vector Rotate Left Doubleword */
3966 case 260: /* Vector Shift Left Byte */
3967 case 388: /* Vector Shift Left Word */
3968 case 324: /* Vector Shift Left Halfword */
3969 case 1476: /* Vector Shift Left Doubleword */
3970 case 516: /* Vector Shift Right Byte */
3971 case 644: /* Vector Shift Right Word */
3972 case 580: /* Vector Shift Right Halfword */
3973 case 1732: /* Vector Shift Right Doubleword */
3974 case 772: /* Vector Shift Right Algebraic Byte */
3975 case 900: /* Vector Shift Right Algebraic Word */
3976 case 836: /* Vector Shift Right Algebraic Halfword */
3977 case 964: /* Vector Shift Right Algebraic Doubleword */
3978 case 10: /* Vector Add Single-Precision */
3979 case 74: /* Vector Subtract Single-Precision */
3980 case 1034: /* Vector Maximum Single-Precision */
3981 case 1098: /* Vector Minimum Single-Precision */
3982 case 842: /* Vector Convert From Signed Fixed-Point Word */
3983 case 778: /* Vector Convert From Unsigned Fixed-Point Word */
3984 case 714: /* Vector Round to Single-Precision Integer toward -Infinity */
3985 case 522: /* Vector Round to Single-Precision Integer Nearest */
3986 case 650: /* Vector Round to Single-Precision Integer toward +Infinity */
3987 case 586: /* Vector Round to Single-Precision Integer toward Zero */
3988 case 394: /* Vector 2 Raised to the Exponent Estimate Floating-Point */
3989 case 458: /* Vector Log Base 2 Estimate Floating-Point */
3990 case 266: /* Vector Reciprocal Estimate Single-Precision */
3991 case 330: /* Vector Reciprocal Square Root Estimate Single-Precision */
3992 case 1288: /* Vector AES Cipher */
3993 case 1289: /* Vector AES Cipher Last */
3994 case 1352: /* Vector AES Inverse Cipher */
3995 case 1353: /* Vector AES Inverse Cipher Last */
3996 case 1480: /* Vector AES SubBytes */
3997 case 1730: /* Vector SHA-512 Sigma Doubleword */
3998 case 1666: /* Vector SHA-256 Sigma Word */
3999 case 1032: /* Vector Polynomial Multiply-Sum Byte */
4000 case 1160: /* Vector Polynomial Multiply-Sum Word */
4001 case 1096: /* Vector Polynomial Multiply-Sum Halfword */
4002 case 1224: /* Vector Polynomial Multiply-Sum Doubleword */
4003 case 1292: /* Vector Gather Bits by Bytes by Doubleword */
4004 case 1794: /* Vector Count Leading Zeros Byte */
4005 case 1858: /* Vector Count Leading Zeros Halfword */
4006 case 1922: /* Vector Count Leading Zeros Word */
4007 case 1986: /* Vector Count Leading Zeros Doubleword */
4008 case 1795: /* Vector Population Count Byte */
4009 case 1859: /* Vector Population Count Halfword */
4010 case 1923: /* Vector Population Count Word */
4011 case 1987: /* Vector Population Count Doubleword */
4012 case 1356: /* Vector Bit Permute Quadword */
4013 record_full_arch_list_add_reg (regcache
,
4014 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4017 case 1604: /* Move To Vector Status and Control Register */
4018 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
4020 case 1540: /* Move From Vector Status and Control Register */
4021 record_full_arch_list_add_reg (regcache
,
4022 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4026 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4027 "at %s, 4-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4031 /* Parse and record instructions of primary opcode-19 at ADDR.
4032 Return 0 if successful. */
4035 ppc_process_record_op19 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4036 CORE_ADDR addr
, uint32_t insn
)
4038 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4039 int ext
= PPC_EXTOP (insn
);
4043 case 0: /* Move Condition Register Field */
4044 case 33: /* Condition Register NOR */
4045 case 129: /* Condition Register AND with Complement */
4046 case 193: /* Condition Register XOR */
4047 case 225: /* Condition Register NAND */
4048 case 257: /* Condition Register AND */
4049 case 289: /* Condition Register Equivalent */
4050 case 417: /* Condition Register OR with Complement */
4051 case 449: /* Condition Register OR */
4052 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4055 case 16: /* Branch Conditional */
4056 case 560: /* Branch Conditional to Branch Target Address Register */
4057 if ((PPC_BO (insn
) & 0x4) == 0)
4058 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
4060 case 528: /* Branch Conditional to Count Register */
4062 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
4065 case 150: /* Instruction Synchronize */
4070 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4071 "at %s, 19-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4075 /* Parse and record instructions of primary opcode-31 at ADDR.
4076 Return 0 if successful. */
4079 ppc_process_record_op31 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4080 CORE_ADDR addr
, uint32_t insn
)
4082 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4083 int ext
= PPC_EXTOP (insn
);
4085 CORE_ADDR at_dcsz
, ea
= 0;
4086 ULONGEST rb
, ra
, xer
;
4089 /* These instructions have OE bit. */
4090 switch (ext
& 0x1ff)
4092 /* These write RT and XER. Update CR if RC is set. */
4093 case 8: /* Subtract from carrying */
4094 case 10: /* Add carrying */
4095 case 136: /* Subtract from extended */
4096 case 138: /* Add extended */
4097 case 200: /* Subtract from zero extended */
4098 case 202: /* Add to zero extended */
4099 case 232: /* Subtract from minus one extended */
4100 case 234: /* Add to minus one extended */
4101 /* CA is always altered, but SO/OV are only altered when OE=1.
4102 In any case, XER is always altered. */
4103 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4105 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4106 record_full_arch_list_add_reg (regcache
,
4107 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4110 /* These write RT. Update CR if RC is set and update XER if OE is set. */
4111 case 40: /* Subtract from */
4112 case 104: /* Negate */
4113 case 233: /* Multiply low doubleword */
4114 case 235: /* Multiply low word */
4116 case 393: /* Divide Doubleword Extended Unsigned */
4117 case 395: /* Divide Word Extended Unsigned */
4118 case 425: /* Divide Doubleword Extended */
4119 case 427: /* Divide Word Extended */
4120 case 457: /* Divide Doubleword Unsigned */
4121 case 459: /* Divide Word Unsigned */
4122 case 489: /* Divide Doubleword */
4123 case 491: /* Divide Word */
4125 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4127 case 9: /* Multiply High Doubleword Unsigned */
4128 case 11: /* Multiply High Word Unsigned */
4129 case 73: /* Multiply High Doubleword */
4130 case 75: /* Multiply High Word */
4132 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4133 record_full_arch_list_add_reg (regcache
,
4134 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4138 if ((ext
& 0x1f) == 15)
4140 /* Integer Select. bit[16:20] is used for BC. */
4141 record_full_arch_list_add_reg (regcache
,
4142 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4148 case 78: /* Determine Leftmost Zero Byte */
4150 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4151 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4152 record_full_arch_list_add_reg (regcache
,
4153 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4156 /* These only write RT. */
4157 case 19: /* Move from condition register */
4158 /* Move From One Condition Register Field */
4159 case 74: /* Add and Generate Sixes */
4160 case 74 | 0x200: /* Add and Generate Sixes (bit-21 dont-care) */
4161 case 302: /* Move From Branch History Rolling Buffer */
4162 case 339: /* Move From Special Purpose Register */
4163 case 371: /* Move From Time Base [Phased-Out] */
4164 record_full_arch_list_add_reg (regcache
,
4165 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4168 /* These only write to RA. */
4169 case 51: /* Move From VSR Doubleword */
4170 case 115: /* Move From VSR Word and Zero */
4171 case 122: /* Population count bytes */
4172 case 378: /* Population count words */
4173 case 506: /* Population count doublewords */
4174 case 154: /* Parity Word */
4175 case 186: /* Parity Doubleword */
4176 case 252: /* Bit Permute Doubleword */
4177 case 282: /* Convert Declets To Binary Coded Decimal */
4178 case 314: /* Convert Binary Coded Decimal To Declets */
4179 case 508: /* Compare bytes */
4180 record_full_arch_list_add_reg (regcache
,
4181 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4184 /* These write CR and optional RA. */
4185 case 792: /* Shift Right Algebraic Word */
4186 case 794: /* Shift Right Algebraic Doubleword */
4187 case 824: /* Shift Right Algebraic Word Immediate */
4188 case 826: /* Shift Right Algebraic Doubleword Immediate (413) */
4189 case 826 | 1: /* Shift Right Algebraic Doubleword Immediate (413) */
4190 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4191 record_full_arch_list_add_reg (regcache
,
4192 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4194 case 0: /* Compare */
4195 case 32: /* Compare logical */
4196 case 144: /* Move To Condition Register Fields */
4197 /* Move To One Condition Register Field */
4198 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4201 /* These write to RT. Update RA if 'update indexed.' */
4202 case 53: /* Load Doubleword with Update Indexed */
4203 case 119: /* Load Byte and Zero with Update Indexed */
4204 case 311: /* Load Halfword and Zero with Update Indexed */
4205 case 55: /* Load Word and Zero with Update Indexed */
4206 case 375: /* Load Halfword Algebraic with Update Indexed */
4207 case 373: /* Load Word Algebraic with Update Indexed */
4208 record_full_arch_list_add_reg (regcache
,
4209 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4211 case 21: /* Load Doubleword Indexed */
4212 case 52: /* Load Byte And Reserve Indexed */
4213 case 116: /* Load Halfword And Reserve Indexed */
4214 case 20: /* Load Word And Reserve Indexed */
4215 case 84: /* Load Doubleword And Reserve Indexed */
4216 case 87: /* Load Byte and Zero Indexed */
4217 case 279: /* Load Halfword and Zero Indexed */
4218 case 23: /* Load Word and Zero Indexed */
4219 case 343: /* Load Halfword Algebraic Indexed */
4220 case 341: /* Load Word Algebraic Indexed */
4221 case 790: /* Load Halfword Byte-Reverse Indexed */
4222 case 534: /* Load Word Byte-Reverse Indexed */
4223 case 532: /* Load Doubleword Byte-Reverse Indexed */
4224 record_full_arch_list_add_reg (regcache
,
4225 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4228 case 597: /* Load String Word Immediate */
4229 case 533: /* Load String Word Indexed */
4238 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &xer
);
4239 nr
= PPC_XER_NB (xer
);
4244 /* If n=0, the contents of register RT are undefined. */
4248 for (i
= 0; i
< nr
; i
++)
4249 record_full_arch_list_add_reg (regcache
,
4250 tdep
->ppc_gp0_regnum
4251 + ((PPC_RT (insn
) + i
) & 0x1f));
4254 case 276: /* Load Quadword And Reserve Indexed */
4255 tmp
= tdep
->ppc_gp0_regnum
+ (PPC_RT (insn
) & ~1);
4256 record_full_arch_list_add_reg (regcache
, tmp
);
4257 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
4260 /* These write VRT. */
4261 case 6: /* Load Vector for Shift Left Indexed */
4262 case 38: /* Load Vector for Shift Right Indexed */
4263 case 7: /* Load Vector Element Byte Indexed */
4264 case 39: /* Load Vector Element Halfword Indexed */
4265 case 71: /* Load Vector Element Word Indexed */
4266 case 103: /* Load Vector Indexed */
4267 case 359: /* Load Vector Indexed LRU */
4268 record_full_arch_list_add_reg (regcache
,
4269 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4272 /* These write FRT. Update RA if 'update indexed.' */
4273 case 567: /* Load Floating-Point Single with Update Indexed */
4274 case 631: /* Load Floating-Point Double with Update Indexed */
4275 record_full_arch_list_add_reg (regcache
,
4276 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4278 case 535: /* Load Floating-Point Single Indexed */
4279 case 599: /* Load Floating-Point Double Indexed */
4280 case 855: /* Load Floating-Point as Integer Word Algebraic Indexed */
4281 case 887: /* Load Floating-Point as Integer Word and Zero Indexed */
4282 record_full_arch_list_add_reg (regcache
,
4283 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4286 case 791: /* Load Floating-Point Double Pair Indexed */
4287 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
4288 record_full_arch_list_add_reg (regcache
, tmp
);
4289 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
4292 case 179: /* Move To VSR Doubleword */
4293 case 211: /* Move To VSR Word Algebraic */
4294 case 243: /* Move To VSR Word and Zero */
4295 case 588: /* Load VSX Scalar Doubleword Indexed */
4296 case 524: /* Load VSX Scalar Single-Precision Indexed */
4297 case 76: /* Load VSX Scalar as Integer Word Algebraic Indexed */
4298 case 12: /* Load VSX Scalar as Integer Word and Zero Indexed */
4299 case 844: /* Load VSX Vector Doubleword*2 Indexed */
4300 case 332: /* Load VSX Vector Doubleword & Splat Indexed */
4301 case 780: /* Load VSX Vector Word*4 Indexed */
4302 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
4305 /* These write RA. Update CR if RC is set. */
4306 case 24: /* Shift Left Word */
4307 case 26: /* Count Leading Zeros Word */
4308 case 27: /* Shift Left Doubleword */
4310 case 58: /* Count Leading Zeros Doubleword */
4311 case 60: /* AND with Complement */
4313 case 284: /* Equivalent */
4315 case 476: /* NAND */
4316 case 412: /* OR with Complement */
4318 case 536: /* Shift Right Word */
4319 case 539: /* Shift Right Doubleword */
4320 case 922: /* Extend Sign Halfword */
4321 case 954: /* Extend Sign Byte */
4322 case 986: /* Extend Sign Word */
4324 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4325 record_full_arch_list_add_reg (regcache
,
4326 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4330 case 181: /* Store Doubleword with Update Indexed */
4331 case 183: /* Store Word with Update Indexed */
4332 case 247: /* Store Byte with Update Indexed */
4333 case 439: /* Store Half Word with Update Indexed */
4334 case 695: /* Store Floating-Point Single with Update Indexed */
4335 case 759: /* Store Floating-Point Double with Update Indexed */
4336 record_full_arch_list_add_reg (regcache
,
4337 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4339 case 135: /* Store Vector Element Byte Indexed */
4340 case 167: /* Store Vector Element Halfword Indexed */
4341 case 199: /* Store Vector Element Word Indexed */
4342 case 231: /* Store Vector Indexed */
4343 case 487: /* Store Vector Indexed LRU */
4344 case 716: /* Store VSX Scalar Doubleword Indexed */
4345 case 140: /* Store VSX Scalar as Integer Word Indexed */
4346 case 652: /* Store VSX Scalar Single-Precision Indexed */
4347 case 972: /* Store VSX Vector Doubleword*2 Indexed */
4348 case 908: /* Store VSX Vector Word*4 Indexed */
4349 case 149: /* Store Doubleword Indexed */
4350 case 151: /* Store Word Indexed */
4351 case 215: /* Store Byte Indexed */
4352 case 407: /* Store Half Word Indexed */
4353 case 694: /* Store Byte Conditional Indexed */
4354 case 726: /* Store Halfword Conditional Indexed */
4355 case 150: /* Store Word Conditional Indexed */
4356 case 214: /* Store Doubleword Conditional Indexed */
4357 case 182: /* Store Quadword Conditional Indexed */
4358 case 662: /* Store Word Byte-Reverse Indexed */
4359 case 918: /* Store Halfword Byte-Reverse Indexed */
4360 case 660: /* Store Doubleword Byte-Reverse Indexed */
4361 case 663: /* Store Floating-Point Single Indexed */
4362 case 727: /* Store Floating-Point Double Indexed */
4363 case 919: /* Store Floating-Point Double Pair Indexed */
4364 case 983: /* Store Floating-Point as Integer Word Indexed */
4365 if (ext
== 694 || ext
== 726 || ext
== 150 || ext
== 214 || ext
== 182)
4366 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4369 if (PPC_RA (insn
) != 0)
4370 regcache_raw_read_unsigned (regcache
,
4371 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4372 regcache_raw_read_unsigned (regcache
,
4373 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
4378 case 183: /* Store Word with Update Indexed */
4379 case 199: /* Store Vector Element Word Indexed */
4380 case 140: /* Store VSX Scalar as Integer Word Indexed */
4381 case 652: /* Store VSX Scalar Single-Precision Indexed */
4382 case 151: /* Store Word Indexed */
4383 case 150: /* Store Word Conditional Indexed */
4384 case 662: /* Store Word Byte-Reverse Indexed */
4385 case 663: /* Store Floating-Point Single Indexed */
4386 case 695: /* Store Floating-Point Single with Update Indexed */
4387 case 983: /* Store Floating-Point as Integer Word Indexed */
4390 case 247: /* Store Byte with Update Indexed */
4391 case 135: /* Store Vector Element Byte Indexed */
4392 case 215: /* Store Byte Indexed */
4393 case 694: /* Store Byte Conditional Indexed */
4396 case 439: /* Store Halfword with Update Indexed */
4397 case 167: /* Store Vector Element Halfword Indexed */
4398 case 407: /* Store Halfword Indexed */
4399 case 726: /* Store Halfword Conditional Indexed */
4400 case 918: /* Store Halfword Byte-Reverse Indexed */
4403 case 181: /* Store Doubleword with Update Indexed */
4404 case 716: /* Store VSX Scalar Doubleword Indexed */
4405 case 149: /* Store Doubleword Indexed */
4406 case 214: /* Store Doubleword Conditional Indexed */
4407 case 660: /* Store Doubleword Byte-Reverse Indexed */
4408 case 727: /* Store Floating-Point Double Indexed */
4409 case 759: /* Store Floating-Point Double with Update Indexed */
4412 case 972: /* Store VSX Vector Doubleword*2 Indexed */
4413 case 908: /* Store VSX Vector Word*4 Indexed */
4414 case 182: /* Store Quadword Conditional Indexed */
4415 case 231: /* Store Vector Indexed */
4416 case 487: /* Store Vector Indexed LRU */
4417 case 919: /* Store Floating-Point Double Pair Indexed */
4424 /* Align address for Store Vector instructions. */
4427 case 167: /* Store Vector Element Halfword Indexed */
4428 addr
= addr
& ~0x1ULL
;
4431 case 199: /* Store Vector Element Word Indexed */
4432 addr
= addr
& ~0x3ULL
;
4435 case 231: /* Store Vector Indexed */
4436 case 487: /* Store Vector Indexed LRU */
4437 addr
= addr
& ~0xfULL
;
4441 record_full_arch_list_add_mem (addr
, size
);
4444 case 725: /* Store String Word Immediate */
4446 if (PPC_RA (insn
) != 0)
4447 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &ra
);
4454 record_full_arch_list_add_mem (ea
, nb
);
4458 case 661: /* Store String Word Indexed */
4460 if (PPC_RA (insn
) != 0)
4461 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &ra
);
4464 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &xer
);
4465 nb
= PPC_XER_NB (xer
);
4469 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &rb
);
4471 record_full_arch_list_add_mem (ea
, nb
);
4476 case 467: /* Move To Special Purpose Register */
4477 switch (PPC_SPR (insn
))
4480 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4483 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
4486 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
4488 case 256: /* VRSAVE */
4489 record_full_arch_list_add_reg (regcache
, tdep
->ppc_vrsave_regnum
);
4495 case 147: /* Move To Split Little Endian */
4496 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ps_regnum
);
4499 case 512: /* Move to Condition Register from XER */
4500 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4501 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4504 case 4: /* Trap Word */
4505 case 68: /* Trap Doubleword */
4506 case 430: /* Clear BHRB */
4507 case 598: /* Synchronize */
4508 case 62: /* Wait for Interrupt */
4509 case 22: /* Instruction Cache Block Touch */
4510 case 854: /* Enforce In-order Execution of I/O */
4511 case 246: /* Data Cache Block Touch for Store */
4512 case 54: /* Data Cache Block Store */
4513 case 86: /* Data Cache Block Flush */
4514 case 278: /* Data Cache Block Touch */
4515 case 758: /* Data Cache Block Allocate */
4516 case 982: /* Instruction Cache Block Invalidate */
4519 case 654: /* Transaction Begin */
4520 case 686: /* Transaction End */
4521 case 718: /* Transaction Check */
4522 case 750: /* Transaction Suspend or Resume */
4523 case 782: /* Transaction Abort Word Conditional */
4524 case 814: /* Transaction Abort Doubleword Conditional */
4525 case 846: /* Transaction Abort Word Conditional Immediate */
4526 case 878: /* Transaction Abort Doubleword Conditional Immediate */
4527 case 910: /* Transaction Abort */
4528 fprintf_unfiltered (gdb_stdlog
, "Cannot record Transaction instructions. "
4529 "%08x at %s, 31-%d.\n",
4530 insn
, paddress (gdbarch
, addr
), ext
);
4533 case 1014: /* Data Cache Block set to Zero */
4534 if (target_auxv_search (¤t_target
, AT_DCACHEBSIZE
, &at_dcsz
) <= 0
4536 at_dcsz
= 128; /* Assume 128-byte cache line size (POWER8) */
4538 if (PPC_RA (insn
) != 0)
4539 regcache_raw_read_unsigned (regcache
,
4540 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4541 regcache_raw_read_unsigned (regcache
,
4542 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
4543 ea
= (ra
+ rb
) & ~((ULONGEST
) (at_dcsz
- 1));
4544 record_full_arch_list_add_mem (ea
, at_dcsz
);
4549 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4550 "at %s, 31-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4554 /* Parse and record instructions of primary opcode-59 at ADDR.
4555 Return 0 if successful. */
4558 ppc_process_record_op59 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4559 CORE_ADDR addr
, uint32_t insn
)
4561 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4562 int ext
= PPC_EXTOP (insn
);
4566 case 18: /* Floating Divide */
4567 case 20: /* Floating Subtract */
4568 case 21: /* Floating Add */
4569 case 22: /* Floating Square Root */
4570 case 24: /* Floating Reciprocal Estimate */
4571 case 25: /* Floating Multiply */
4572 case 26: /* Floating Reciprocal Square Root Estimate */
4573 case 28: /* Floating Multiply-Subtract */
4574 case 29: /* Floating Multiply-Add */
4575 case 30: /* Floating Negative Multiply-Subtract */
4576 case 31: /* Floating Negative Multiply-Add */
4577 record_full_arch_list_add_reg (regcache
,
4578 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4580 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4581 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4588 case 2: /* DFP Add */
4589 case 3: /* DFP Quantize */
4590 case 34: /* DFP Multiply */
4591 case 35: /* DFP Reround */
4592 case 67: /* DFP Quantize Immediate */
4593 case 99: /* DFP Round To FP Integer With Inexact */
4594 case 227: /* DFP Round To FP Integer Without Inexact */
4595 case 258: /* DFP Convert To DFP Long! */
4596 case 290: /* DFP Convert To Fixed */
4597 case 514: /* DFP Subtract */
4598 case 546: /* DFP Divide */
4599 case 770: /* DFP Round To DFP Short! */
4600 case 802: /* DFP Convert From Fixed */
4601 case 834: /* DFP Encode BCD To DPD */
4603 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4604 record_full_arch_list_add_reg (regcache
,
4605 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4606 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4609 case 130: /* DFP Compare Ordered */
4610 case 162: /* DFP Test Exponent */
4611 case 194: /* DFP Test Data Class */
4612 case 226: /* DFP Test Data Group */
4613 case 642: /* DFP Compare Unordered */
4614 case 674: /* DFP Test Significance */
4615 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4616 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4619 case 66: /* DFP Shift Significand Left Immediate */
4620 case 98: /* DFP Shift Significand Right Immediate */
4621 case 322: /* DFP Decode DPD To BCD */
4622 case 354: /* DFP Extract Biased Exponent */
4623 case 866: /* DFP Insert Biased Exponent */
4624 record_full_arch_list_add_reg (regcache
,
4625 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4627 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4630 case 846: /* Floating Convert From Integer Doubleword Single */
4631 case 974: /* Floating Convert From Integer Doubleword Unsigned
4633 record_full_arch_list_add_reg (regcache
,
4634 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4636 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4637 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4642 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4643 "at %s, 59-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4647 /* Parse and record instructions of primary opcode-60 at ADDR.
4648 Return 0 if successful. */
4651 ppc_process_record_op60 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4652 CORE_ADDR addr
, uint32_t insn
)
4654 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4655 int ext
= PPC_EXTOP (insn
);
4659 case 0: /* VSX Scalar Add Single-Precision */
4660 case 32: /* VSX Scalar Add Double-Precision */
4661 case 24: /* VSX Scalar Divide Single-Precision */
4662 case 56: /* VSX Scalar Divide Double-Precision */
4663 case 176: /* VSX Scalar Copy Sign Double-Precision */
4664 case 33: /* VSX Scalar Multiply-Add Double-Precision */
4665 case 41: /* ditto */
4666 case 1: /* VSX Scalar Multiply-Add Single-Precision */
4668 case 160: /* VSX Scalar Maximum Double-Precision */
4669 case 168: /* VSX Scalar Minimum Double-Precision */
4670 case 49: /* VSX Scalar Multiply-Subtract Double-Precision */
4671 case 57: /* ditto */
4672 case 17: /* VSX Scalar Multiply-Subtract Single-Precision */
4673 case 25: /* ditto */
4674 case 48: /* VSX Scalar Multiply Double-Precision */
4675 case 16: /* VSX Scalar Multiply Single-Precision */
4676 case 161: /* VSX Scalar Negative Multiply-Add Double-Precision */
4677 case 169: /* ditto */
4678 case 129: /* VSX Scalar Negative Multiply-Add Single-Precision */
4679 case 137: /* ditto */
4680 case 177: /* VSX Scalar Negative Multiply-Subtract Double-Precision */
4681 case 185: /* ditto */
4682 case 145: /* VSX Scalar Negative Multiply-Subtract Single-Precision */
4683 case 153: /* ditto */
4684 case 40: /* VSX Scalar Subtract Double-Precision */
4685 case 8: /* VSX Scalar Subtract Single-Precision */
4686 case 96: /* VSX Vector Add Double-Precision */
4687 case 64: /* VSX Vector Add Single-Precision */
4688 case 120: /* VSX Vector Divide Double-Precision */
4689 case 88: /* VSX Vector Divide Single-Precision */
4690 case 97: /* VSX Vector Multiply-Add Double-Precision */
4691 case 105: /* ditto */
4692 case 65: /* VSX Vector Multiply-Add Single-Precision */
4693 case 73: /* ditto */
4694 case 224: /* VSX Vector Maximum Double-Precision */
4695 case 192: /* VSX Vector Maximum Single-Precision */
4696 case 232: /* VSX Vector Minimum Double-Precision */
4697 case 200: /* VSX Vector Minimum Single-Precision */
4698 case 113: /* VSX Vector Multiply-Subtract Double-Precision */
4699 case 121: /* ditto */
4700 case 81: /* VSX Vector Multiply-Subtract Single-Precision */
4701 case 89: /* ditto */
4702 case 112: /* VSX Vector Multiply Double-Precision */
4703 case 80: /* VSX Vector Multiply Single-Precision */
4704 case 225: /* VSX Vector Negative Multiply-Add Double-Precision */
4705 case 233: /* ditto */
4706 case 193: /* VSX Vector Negative Multiply-Add Single-Precision */
4707 case 201: /* ditto */
4708 case 241: /* VSX Vector Negative Multiply-Subtract Double-Precision */
4709 case 249: /* ditto */
4710 case 209: /* VSX Vector Negative Multiply-Subtract Single-Precision */
4711 case 217: /* ditto */
4712 case 104: /* VSX Vector Subtract Double-Precision */
4713 case 72: /* VSX Vector Subtract Single-Precision */
4714 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4715 case 240: /* VSX Vector Copy Sign Double-Precision */
4716 case 208: /* VSX Vector Copy Sign Single-Precision */
4717 case 130: /* VSX Logical AND */
4718 case 138: /* VSX Logical AND with Complement */
4719 case 186: /* VSX Logical Equivalence */
4720 case 178: /* VSX Logical NAND */
4721 case 170: /* VSX Logical OR with Complement */
4722 case 162: /* VSX Logical NOR */
4723 case 146: /* VSX Logical OR */
4724 case 154: /* VSX Logical XOR */
4725 case 18: /* VSX Merge High Word */
4726 case 50: /* VSX Merge Low Word */
4727 case 10: /* VSX Permute Doubleword Immediate (DM=0) */
4728 case 10 | 0x20: /* VSX Permute Doubleword Immediate (DM=1) */
4729 case 10 | 0x40: /* VSX Permute Doubleword Immediate (DM=2) */
4730 case 10 | 0x60: /* VSX Permute Doubleword Immediate (DM=3) */
4731 case 2: /* VSX Shift Left Double by Word Immediate (SHW=0) */
4732 case 2 | 0x20: /* VSX Shift Left Double by Word Immediate (SHW=1) */
4733 case 2 | 0x40: /* VSX Shift Left Double by Word Immediate (SHW=2) */
4734 case 2 | 0x60: /* VSX Shift Left Double by Word Immediate (SHW=3) */
4735 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
4738 case 61: /* VSX Scalar Test for software Divide Double-Precision */
4739 case 125: /* VSX Vector Test for software Divide Double-Precision */
4740 case 93: /* VSX Vector Test for software Divide Single-Precision */
4741 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4744 case 35: /* VSX Scalar Compare Unordered Double-Precision */
4745 case 43: /* VSX Scalar Compare Ordered Double-Precision */
4746 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4747 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4751 switch ((ext
>> 2) & 0x7f) /* Mask out Rc-bit. */
4753 case 99: /* VSX Vector Compare Equal To Double-Precision */
4754 case 67: /* VSX Vector Compare Equal To Single-Precision */
4755 case 115: /* VSX Vector Compare Greater Than or
4756 Equal To Double-Precision */
4757 case 83: /* VSX Vector Compare Greater Than or
4758 Equal To Single-Precision */
4759 case 107: /* VSX Vector Compare Greater Than Double-Precision */
4760 case 75: /* VSX Vector Compare Greater Than Single-Precision */
4762 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4763 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4764 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
4770 case 265: /* VSX Scalar round Double-Precision to
4771 Single-Precision and Convert to
4772 Single-Precision format */
4773 case 344: /* VSX Scalar truncate Double-Precision to
4774 Integer and Convert to Signed Integer
4775 Doubleword format with Saturate */
4776 case 88: /* VSX Scalar truncate Double-Precision to
4777 Integer and Convert to Signed Integer Word
4778 Format with Saturate */
4779 case 328: /* VSX Scalar truncate Double-Precision integer
4780 and Convert to Unsigned Integer Doubleword
4781 Format with Saturate */
4782 case 72: /* VSX Scalar truncate Double-Precision to
4783 Integer and Convert to Unsigned Integer Word
4784 Format with Saturate */
4785 case 329: /* VSX Scalar Convert Single-Precision to
4786 Double-Precision format */
4787 case 376: /* VSX Scalar Convert Signed Integer
4788 Doubleword to floating-point format and
4789 Round to Double-Precision format */
4790 case 312: /* VSX Scalar Convert Signed Integer
4791 Doubleword to floating-point format and
4792 round to Single-Precision */
4793 case 360: /* VSX Scalar Convert Unsigned Integer
4794 Doubleword to floating-point format and
4795 Round to Double-Precision format */
4796 case 296: /* VSX Scalar Convert Unsigned Integer
4797 Doubleword to floating-point format and
4798 Round to Single-Precision */
4799 case 73: /* VSX Scalar Round to Double-Precision Integer
4800 Using Round to Nearest Away */
4801 case 107: /* VSX Scalar Round to Double-Precision Integer
4802 Exact using Current rounding mode */
4803 case 121: /* VSX Scalar Round to Double-Precision Integer
4804 Using Round toward -Infinity */
4805 case 105: /* VSX Scalar Round to Double-Precision Integer
4806 Using Round toward +Infinity */
4807 case 89: /* VSX Scalar Round to Double-Precision Integer
4808 Using Round toward Zero */
4809 case 90: /* VSX Scalar Reciprocal Estimate Double-Precision */
4810 case 26: /* VSX Scalar Reciprocal Estimate Single-Precision */
4811 case 281: /* VSX Scalar Round to Single-Precision */
4812 case 74: /* VSX Scalar Reciprocal Square Root Estimate
4814 case 10: /* VSX Scalar Reciprocal Square Root Estimate
4816 case 75: /* VSX Scalar Square Root Double-Precision */
4817 case 11: /* VSX Scalar Square Root Single-Precision */
4818 case 393: /* VSX Vector round Double-Precision to
4819 Single-Precision and Convert to
4820 Single-Precision format */
4821 case 472: /* VSX Vector truncate Double-Precision to
4822 Integer and Convert to Signed Integer
4823 Doubleword format with Saturate */
4824 case 216: /* VSX Vector truncate Double-Precision to
4825 Integer and Convert to Signed Integer Word
4826 Format with Saturate */
4827 case 456: /* VSX Vector truncate Double-Precision to
4828 Integer and Convert to Unsigned Integer
4829 Doubleword format with Saturate */
4830 case 200: /* VSX Vector truncate Double-Precision to
4831 Integer and Convert to Unsigned Integer Word
4832 Format with Saturate */
4833 case 457: /* VSX Vector Convert Single-Precision to
4834 Double-Precision format */
4835 case 408: /* VSX Vector truncate Single-Precision to
4836 Integer and Convert to Signed Integer
4837 Doubleword format with Saturate */
4838 case 152: /* VSX Vector truncate Single-Precision to
4839 Integer and Convert to Signed Integer Word
4840 Format with Saturate */
4841 case 392: /* VSX Vector truncate Single-Precision to
4842 Integer and Convert to Unsigned Integer
4843 Doubleword format with Saturate */
4844 case 136: /* VSX Vector truncate Single-Precision to
4845 Integer and Convert to Unsigned Integer Word
4846 Format with Saturate */
4847 case 504: /* VSX Vector Convert and round Signed Integer
4848 Doubleword to Double-Precision format */
4849 case 440: /* VSX Vector Convert and round Signed Integer
4850 Doubleword to Single-Precision format */
4851 case 248: /* VSX Vector Convert Signed Integer Word to
4852 Double-Precision format */
4853 case 184: /* VSX Vector Convert and round Signed Integer
4854 Word to Single-Precision format */
4855 case 488: /* VSX Vector Convert and round Unsigned
4856 Integer Doubleword to Double-Precision format */
4857 case 424: /* VSX Vector Convert and round Unsigned
4858 Integer Doubleword to Single-Precision format */
4859 case 232: /* VSX Vector Convert and round Unsigned
4860 Integer Word to Double-Precision format */
4861 case 168: /* VSX Vector Convert and round Unsigned
4862 Integer Word to Single-Precision format */
4863 case 201: /* VSX Vector Round to Double-Precision
4864 Integer using round to Nearest Away */
4865 case 235: /* VSX Vector Round to Double-Precision
4866 Integer Exact using Current rounding mode */
4867 case 249: /* VSX Vector Round to Double-Precision
4868 Integer using round toward -Infinity */
4869 case 233: /* VSX Vector Round to Double-Precision
4870 Integer using round toward +Infinity */
4871 case 217: /* VSX Vector Round to Double-Precision
4872 Integer using round toward Zero */
4873 case 218: /* VSX Vector Reciprocal Estimate Double-Precision */
4874 case 154: /* VSX Vector Reciprocal Estimate Single-Precision */
4875 case 137: /* VSX Vector Round to Single-Precision Integer
4876 Using Round to Nearest Away */
4877 case 171: /* VSX Vector Round to Single-Precision Integer
4878 Exact Using Current rounding mode */
4879 case 185: /* VSX Vector Round to Single-Precision Integer
4880 Using Round toward -Infinity */
4881 case 169: /* VSX Vector Round to Single-Precision Integer
4882 Using Round toward +Infinity */
4883 case 153: /* VSX Vector Round to Single-Precision Integer
4884 Using round toward Zero */
4885 case 202: /* VSX Vector Reciprocal Square Root Estimate
4887 case 138: /* VSX Vector Reciprocal Square Root Estimate
4889 case 203: /* VSX Vector Square Root Double-Precision */
4890 case 139: /* VSX Vector Square Root Single-Precision */
4891 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4892 case 345: /* VSX Scalar Absolute Value Double-Precision */
4893 case 267: /* VSX Scalar Convert Scalar Single-Precision to
4894 Vector Single-Precision format Non-signalling */
4895 case 331: /* VSX Scalar Convert Single-Precision to
4896 Double-Precision format Non-signalling */
4897 case 361: /* VSX Scalar Negative Absolute Value Double-Precision */
4898 case 377: /* VSX Scalar Negate Double-Precision */
4899 case 473: /* VSX Vector Absolute Value Double-Precision */
4900 case 409: /* VSX Vector Absolute Value Single-Precision */
4901 case 489: /* VSX Vector Negative Absolute Value Double-Precision */
4902 case 425: /* VSX Vector Negative Absolute Value Single-Precision */
4903 case 505: /* VSX Vector Negate Double-Precision */
4904 case 441: /* VSX Vector Negate Single-Precision */
4905 case 164: /* VSX Splat Word */
4906 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
4909 case 106: /* VSX Scalar Test for software Square Root
4911 case 234: /* VSX Vector Test for software Square Root
4913 case 170: /* VSX Vector Test for software Square Root
4915 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4919 if (((ext
>> 3) & 0x3) == 3) /* VSX Select */
4921 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
4925 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4926 "at %s, 60-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4930 /* Parse and record instructions of primary opcode-63 at ADDR.
4931 Return 0 if successful. */
4934 ppc_process_record_op63 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4935 CORE_ADDR addr
, uint32_t insn
)
4937 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4938 int ext
= PPC_EXTOP (insn
);
4943 case 18: /* Floating Divide */
4944 case 20: /* Floating Subtract */
4945 case 21: /* Floating Add */
4946 case 22: /* Floating Square Root */
4947 case 24: /* Floating Reciprocal Estimate */
4948 case 25: /* Floating Multiply */
4949 case 26: /* Floating Reciprocal Square Root Estimate */
4950 case 28: /* Floating Multiply-Subtract */
4951 case 29: /* Floating Multiply-Add */
4952 case 30: /* Floating Negative Multiply-Subtract */
4953 case 31: /* Floating Negative Multiply-Add */
4954 record_full_arch_list_add_reg (regcache
,
4955 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4957 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4958 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4961 case 23: /* Floating Select */
4962 record_full_arch_list_add_reg (regcache
,
4963 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4965 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4970 case 2: /* DFP Add Quad */
4971 case 3: /* DFP Quantize Quad */
4972 case 34: /* DFP Multiply Quad */
4973 case 35: /* DFP Reround Quad */
4974 case 67: /* DFP Quantize Immediate Quad */
4975 case 99: /* DFP Round To FP Integer With Inexact Quad */
4976 case 227: /* DFP Round To FP Integer Without Inexact Quad */
4977 case 258: /* DFP Convert To DFP Extended Quad */
4978 case 514: /* DFP Subtract Quad */
4979 case 546: /* DFP Divide Quad */
4980 case 770: /* DFP Round To DFP Long Quad */
4981 case 802: /* DFP Convert From Fixed Quad */
4982 case 834: /* DFP Encode BCD To DPD Quad */
4984 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4985 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
4986 record_full_arch_list_add_reg (regcache
, tmp
);
4987 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
4988 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4991 case 130: /* DFP Compare Ordered Quad */
4992 case 162: /* DFP Test Exponent Quad */
4993 case 194: /* DFP Test Data Class Quad */
4994 case 226: /* DFP Test Data Group Quad */
4995 case 642: /* DFP Compare Unordered Quad */
4996 case 674: /* DFP Test Significance Quad */
4997 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4998 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5001 case 66: /* DFP Shift Significand Left Immediate Quad */
5002 case 98: /* DFP Shift Significand Right Immediate Quad */
5003 case 322: /* DFP Decode DPD To BCD Quad */
5004 case 866: /* DFP Insert Biased Exponent Quad */
5005 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
5006 record_full_arch_list_add_reg (regcache
, tmp
);
5007 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5009 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5012 case 290: /* DFP Convert To Fixed Quad */
5013 record_full_arch_list_add_reg (regcache
,
5014 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5016 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5017 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5020 case 354: /* DFP Extract Biased Exponent Quad */
5021 record_full_arch_list_add_reg (regcache
,
5022 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5024 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5027 case 12: /* Floating Round to Single-Precision */
5028 case 14: /* Floating Convert To Integer Word */
5029 case 15: /* Floating Convert To Integer Word
5030 with round toward Zero */
5031 case 142: /* Floating Convert To Integer Word Unsigned */
5032 case 143: /* Floating Convert To Integer Word Unsigned
5033 with round toward Zero */
5034 case 392: /* Floating Round to Integer Nearest */
5035 case 424: /* Floating Round to Integer Toward Zero */
5036 case 456: /* Floating Round to Integer Plus */
5037 case 488: /* Floating Round to Integer Minus */
5038 case 814: /* Floating Convert To Integer Doubleword */
5039 case 815: /* Floating Convert To Integer Doubleword
5040 with round toward Zero */
5041 case 846: /* Floating Convert From Integer Doubleword */
5042 case 942: /* Floating Convert To Integer Doubleword Unsigned */
5043 case 943: /* Floating Convert To Integer Doubleword Unsigned
5044 with round toward Zero */
5045 case 974: /* Floating Convert From Integer Doubleword Unsigned */
5046 record_full_arch_list_add_reg (regcache
,
5047 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5049 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5050 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5053 case 583: /* Move From FPSCR */
5054 case 8: /* Floating Copy Sign */
5055 case 40: /* Floating Negate */
5056 case 72: /* Floating Move Register */
5057 case 136: /* Floating Negative Absolute Value */
5058 case 264: /* Floating Absolute Value */
5059 record_full_arch_list_add_reg (regcache
,
5060 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5062 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5065 case 838: /* Floating Merge Odd Word */
5066 case 966: /* Floating Merge Even Word */
5067 record_full_arch_list_add_reg (regcache
,
5068 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5071 case 38: /* Move To FPSCR Bit 1 */
5072 case 70: /* Move To FPSCR Bit 0 */
5073 case 134: /* Move To FPSCR Field Immediate */
5074 case 711: /* Move To FPSCR Fields */
5076 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5077 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5080 case 0: /* Floating Compare Unordered */
5081 case 32: /* Floating Compare Ordered */
5082 case 64: /* Move to Condition Register from FPSCR */
5083 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5085 case 128: /* Floating Test for software Divide */
5086 case 160: /* Floating Test for software Square Root */
5087 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5092 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5093 "at %s, 59-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5097 /* Parse the current instruction and record the values of the registers and
5098 memory that will be changed in current instruction to "record_arch_list".
5099 Return -1 if something wrong. */
5102 ppc_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5105 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5106 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5110 insn
= read_memory_unsigned_integer (addr
, 4, byte_order
);
5111 op6
= PPC_OP6 (insn
);
5115 case 2: /* Trap Doubleword Immediate */
5116 case 3: /* Trap Word Immediate */
5121 if (ppc_process_record_op4 (gdbarch
, regcache
, addr
, insn
) != 0)
5125 case 17: /* System call */
5126 if (PPC_LEV (insn
) != 0)
5129 if (tdep
->ppc_syscall_record
!= NULL
)
5131 if (tdep
->ppc_syscall_record (regcache
) != 0)
5136 printf_unfiltered (_("no syscall record support\n"));
5141 case 7: /* Multiply Low Immediate */
5142 record_full_arch_list_add_reg (regcache
,
5143 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5146 case 8: /* Subtract From Immediate Carrying */
5147 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5148 record_full_arch_list_add_reg (regcache
,
5149 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5152 case 10: /* Compare Logical Immediate */
5153 case 11: /* Compare Immediate */
5154 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5157 case 13: /* Add Immediate Carrying and Record */
5158 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5160 case 12: /* Add Immediate Carrying */
5161 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5163 case 14: /* Add Immediate */
5164 case 15: /* Add Immediate Shifted */
5165 record_full_arch_list_add_reg (regcache
,
5166 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5169 case 16: /* Branch Conditional */
5170 if ((PPC_BO (insn
) & 0x4) == 0)
5171 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
5173 case 18: /* Branch */
5175 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
5179 if (ppc_process_record_op19 (gdbarch
, regcache
, addr
, insn
) != 0)
5183 case 20: /* Rotate Left Word Immediate then Mask Insert */
5184 case 21: /* Rotate Left Word Immediate then AND with Mask */
5185 case 23: /* Rotate Left Word then AND with Mask */
5186 case 30: /* Rotate Left Doubleword Immediate then Clear Left */
5187 /* Rotate Left Doubleword Immediate then Clear Right */
5188 /* Rotate Left Doubleword Immediate then Clear */
5189 /* Rotate Left Doubleword then Clear Left */
5190 /* Rotate Left Doubleword then Clear Right */
5191 /* Rotate Left Doubleword Immediate then Mask Insert */
5193 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5194 record_full_arch_list_add_reg (regcache
,
5195 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5198 case 28: /* AND Immediate */
5199 case 29: /* AND Immediate Shifted */
5200 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5202 case 24: /* OR Immediate */
5203 case 25: /* OR Immediate Shifted */
5204 case 26: /* XOR Immediate */
5205 case 27: /* XOR Immediate Shifted */
5206 record_full_arch_list_add_reg (regcache
,
5207 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5211 if (ppc_process_record_op31 (gdbarch
, regcache
, addr
, insn
) != 0)
5215 case 33: /* Load Word and Zero with Update */
5216 case 35: /* Load Byte and Zero with Update */
5217 case 41: /* Load Halfword and Zero with Update */
5218 case 43: /* Load Halfword Algebraic with Update */
5219 record_full_arch_list_add_reg (regcache
,
5220 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5222 case 32: /* Load Word and Zero */
5223 case 34: /* Load Byte and Zero */
5224 case 40: /* Load Halfword and Zero */
5225 case 42: /* Load Halfword Algebraic */
5226 record_full_arch_list_add_reg (regcache
,
5227 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5230 case 46: /* Load Multiple Word */
5231 for (i
= PPC_RT (insn
); i
< 32; i
++)
5232 record_full_arch_list_add_reg (regcache
, tdep
->ppc_gp0_regnum
+ i
);
5235 case 56: /* Load Quadword */
5236 tmp
= tdep
->ppc_gp0_regnum
+ (PPC_RT (insn
) & ~1);
5237 record_full_arch_list_add_reg (regcache
, tmp
);
5238 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5241 case 49: /* Load Floating-Point Single with Update */
5242 case 51: /* Load Floating-Point Double with Update */
5243 record_full_arch_list_add_reg (regcache
,
5244 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5246 case 48: /* Load Floating-Point Single */
5247 case 50: /* Load Floating-Point Double */
5248 record_full_arch_list_add_reg (regcache
,
5249 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5252 case 47: /* Store Multiple Word */
5256 if (PPC_RA (insn
) != 0)
5257 regcache_raw_read_unsigned (regcache
,
5258 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5261 addr
+= PPC_D (insn
);
5262 record_full_arch_list_add_mem (addr
, 4 * (32 - PPC_RS (insn
)));
5266 case 37: /* Store Word with Update */
5267 case 39: /* Store Byte with Update */
5268 case 45: /* Store Halfword with Update */
5269 case 53: /* Store Floating-Point Single with Update */
5270 case 55: /* Store Floating-Point Double with Update */
5271 record_full_arch_list_add_reg (regcache
,
5272 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5274 case 36: /* Store Word */
5275 case 38: /* Store Byte */
5276 case 44: /* Store Halfword */
5277 case 52: /* Store Floating-Point Single */
5278 case 54: /* Store Floating-Point Double */
5283 if (PPC_RA (insn
) != 0)
5284 regcache_raw_read_unsigned (regcache
,
5285 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5287 addr
+= PPC_D (insn
);
5289 if (op6
== 36 || op6
== 37 || op6
== 52 || op6
== 53)
5291 else if (op6
== 54 || op6
== 55)
5293 else if (op6
== 44 || op6
== 45)
5295 else if (op6
== 38 || op6
== 39)
5300 record_full_arch_list_add_mem (addr
, size
);
5304 case 57: /* Load Floating-Point Double Pair */
5305 if (PPC_FIELD (insn
, 30, 2) != 0)
5307 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_RT (insn
) & ~1);
5308 record_full_arch_list_add_reg (regcache
, tmp
);
5309 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5312 case 58: /* Load Doubleword */
5313 /* Load Doubleword with Update */
5314 /* Load Word Algebraic */
5315 if (PPC_FIELD (insn
, 30, 2) > 2)
5318 record_full_arch_list_add_reg (regcache
,
5319 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5320 if (PPC_BIT (insn
, 31))
5321 record_full_arch_list_add_reg (regcache
,
5322 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5326 if (ppc_process_record_op59 (gdbarch
, regcache
, addr
, insn
) != 0)
5331 if (ppc_process_record_op60 (gdbarch
, regcache
, addr
, insn
) != 0)
5335 case 61: /* Store Floating-Point Double Pair */
5336 case 62: /* Store Doubleword */
5337 /* Store Doubleword with Update */
5338 /* Store Quadword with Update */
5342 int sub2
= PPC_FIELD (insn
, 30, 2);
5344 if ((op6
== 61 && sub2
!= 0) || (op6
== 62 && sub2
> 2))
5347 if (PPC_RA (insn
) != 0)
5348 regcache_raw_read_unsigned (regcache
,
5349 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5352 size
= ((op6
== 61) || sub2
== 2) ? 16 : 8;
5354 addr
+= PPC_DS (insn
) << 2;
5355 record_full_arch_list_add_mem (addr
, size
);
5357 if (op6
== 62 && sub2
== 1)
5358 record_full_arch_list_add_reg (regcache
,
5359 tdep
->ppc_gp0_regnum
+
5366 if (ppc_process_record_op63 (gdbarch
, regcache
, addr
, insn
) != 0)
5372 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5373 "at %s, %d.\n", insn
, paddress (gdbarch
, addr
), op6
);
5377 if (record_full_arch_list_add_reg (regcache
, PPC_PC_REGNUM
))
5379 if (record_full_arch_list_add_end ())
5384 /* Initialize the current architecture based on INFO. If possible, re-use an
5385 architecture from ARCHES, which is a list of architectures already created
5386 during this debugging session.
5388 Called e.g. at program startup, when reading a core file, and when reading
5391 static struct gdbarch
*
5392 rs6000_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5394 struct gdbarch
*gdbarch
;
5395 struct gdbarch_tdep
*tdep
;
5396 int wordsize
, from_xcoff_exec
, from_elf_exec
;
5397 enum bfd_architecture arch
;
5400 enum auto_boolean soft_float_flag
= powerpc_soft_float_global
;
5402 enum powerpc_vector_abi vector_abi
= powerpc_vector_abi_global
;
5403 enum powerpc_elf_abi elf_abi
= POWERPC_ELF_AUTO
;
5404 int have_fpu
= 1, have_spe
= 0, have_mq
= 0, have_altivec
= 0, have_dfp
= 0,
5406 int tdesc_wordsize
= -1;
5407 const struct target_desc
*tdesc
= info
.target_desc
;
5408 struct tdesc_arch_data
*tdesc_data
= NULL
;
5409 int num_pseudoregs
= 0;
5412 /* INFO may refer to a binary that is not of the PowerPC architecture,
5413 e.g. when debugging a stand-alone SPE executable on a Cell/B.E. system.
5414 In this case, we must not attempt to infer properties of the (PowerPC
5415 side) of the target system from properties of that executable. Trust
5416 the target description instead. */
5418 && bfd_get_arch (info
.abfd
) != bfd_arch_powerpc
5419 && bfd_get_arch (info
.abfd
) != bfd_arch_rs6000
)
5422 from_xcoff_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
5423 bfd_get_flavour (info
.abfd
) == bfd_target_xcoff_flavour
;
5425 from_elf_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
5426 bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
;
5428 /* Check word size. If INFO is from a binary file, infer it from
5429 that, else choose a likely default. */
5430 if (from_xcoff_exec
)
5432 if (bfd_xcoff_is_xcoff64 (info
.abfd
))
5437 else if (from_elf_exec
)
5439 if (elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5444 else if (tdesc_has_registers (tdesc
))
5448 if (info
.bfd_arch_info
!= NULL
&& info
.bfd_arch_info
->bits_per_word
!= 0)
5449 wordsize
= (info
.bfd_arch_info
->bits_per_word
5450 / info
.bfd_arch_info
->bits_per_byte
);
5455 /* Get the architecture and machine from the BFD. */
5456 arch
= info
.bfd_arch_info
->arch
;
5457 mach
= info
.bfd_arch_info
->mach
;
5459 /* For e500 executables, the apuinfo section is of help here. Such
5460 section contains the identifier and revision number of each
5461 Application-specific Processing Unit that is present on the
5462 chip. The content of the section is determined by the assembler
5463 which looks at each instruction and determines which unit (and
5464 which version of it) can execute it. Grovel through the section
5465 looking for relevant e500 APUs. */
5467 if (bfd_uses_spe_extensions (info
.abfd
))
5469 arch
= info
.bfd_arch_info
->arch
;
5470 mach
= bfd_mach_ppc_e500
;
5471 bfd_default_set_arch_mach (&abfd
, arch
, mach
);
5472 info
.bfd_arch_info
= bfd_get_arch_info (&abfd
);
5475 /* Find a default target description which describes our register
5476 layout, if we do not already have one. */
5477 if (! tdesc_has_registers (tdesc
))
5479 const struct variant
*v
;
5481 /* Choose variant. */
5482 v
= find_variant_by_arch (arch
, mach
);
5489 gdb_assert (tdesc_has_registers (tdesc
));
5491 /* Check any target description for validity. */
5492 if (tdesc_has_registers (tdesc
))
5494 static const char *const gprs
[] = {
5495 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5496 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5497 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5498 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5500 const struct tdesc_feature
*feature
;
5502 static const char *const msr_names
[] = { "msr", "ps" };
5503 static const char *const cr_names
[] = { "cr", "cnd" };
5504 static const char *const ctr_names
[] = { "ctr", "cnt" };
5506 feature
= tdesc_find_feature (tdesc
,
5507 "org.gnu.gdb.power.core");
5508 if (feature
== NULL
)
5511 tdesc_data
= tdesc_data_alloc ();
5514 for (i
= 0; i
< ppc_num_gprs
; i
++)
5515 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
, gprs
[i
]);
5516 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_PC_REGNUM
,
5518 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_LR_REGNUM
,
5520 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_XER_REGNUM
,
5523 /* Allow alternate names for these registers, to accomodate GDB's
5525 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
5526 PPC_MSR_REGNUM
, msr_names
);
5527 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
5528 PPC_CR_REGNUM
, cr_names
);
5529 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
5530 PPC_CTR_REGNUM
, ctr_names
);
5534 tdesc_data_cleanup (tdesc_data
);
5538 have_mq
= tdesc_numbered_register (feature
, tdesc_data
, PPC_MQ_REGNUM
,
5541 tdesc_wordsize
= tdesc_register_size (feature
, "pc") / 8;
5543 wordsize
= tdesc_wordsize
;
5545 feature
= tdesc_find_feature (tdesc
,
5546 "org.gnu.gdb.power.fpu");
5547 if (feature
!= NULL
)
5549 static const char *const fprs
[] = {
5550 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
5551 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
5552 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
5553 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
5556 for (i
= 0; i
< ppc_num_fprs
; i
++)
5557 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5558 PPC_F0_REGNUM
+ i
, fprs
[i
]);
5559 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5560 PPC_FPSCR_REGNUM
, "fpscr");
5564 tdesc_data_cleanup (tdesc_data
);
5572 /* The DFP pseudo-registers will be available when there are floating
5574 have_dfp
= have_fpu
;
5576 feature
= tdesc_find_feature (tdesc
,
5577 "org.gnu.gdb.power.altivec");
5578 if (feature
!= NULL
)
5580 static const char *const vector_regs
[] = {
5581 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
5582 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
5583 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
5584 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31"
5588 for (i
= 0; i
< ppc_num_gprs
; i
++)
5589 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5592 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5593 PPC_VSCR_REGNUM
, "vscr");
5594 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5595 PPC_VRSAVE_REGNUM
, "vrsave");
5597 if (have_spe
|| !valid_p
)
5599 tdesc_data_cleanup (tdesc_data
);
5607 /* Check for POWER7 VSX registers support. */
5608 feature
= tdesc_find_feature (tdesc
,
5609 "org.gnu.gdb.power.vsx");
5611 if (feature
!= NULL
)
5613 static const char *const vsx_regs
[] = {
5614 "vs0h", "vs1h", "vs2h", "vs3h", "vs4h", "vs5h",
5615 "vs6h", "vs7h", "vs8h", "vs9h", "vs10h", "vs11h",
5616 "vs12h", "vs13h", "vs14h", "vs15h", "vs16h", "vs17h",
5617 "vs18h", "vs19h", "vs20h", "vs21h", "vs22h", "vs23h",
5618 "vs24h", "vs25h", "vs26h", "vs27h", "vs28h", "vs29h",
5624 for (i
= 0; i
< ppc_num_vshrs
; i
++)
5625 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5626 PPC_VSR0_UPPER_REGNUM
+ i
,
5630 tdesc_data_cleanup (tdesc_data
);
5639 /* On machines supporting the SPE APU, the general-purpose registers
5640 are 64 bits long. There are SIMD vector instructions to treat them
5641 as pairs of floats, but the rest of the instruction set treats them
5642 as 32-bit registers, and only operates on their lower halves.
5644 In the GDB regcache, we treat their high and low halves as separate
5645 registers. The low halves we present as the general-purpose
5646 registers, and then we have pseudo-registers that stitch together
5647 the upper and lower halves and present them as pseudo-registers.
5649 Thus, the target description is expected to supply the upper
5650 halves separately. */
5652 feature
= tdesc_find_feature (tdesc
,
5653 "org.gnu.gdb.power.spe");
5654 if (feature
!= NULL
)
5656 static const char *const upper_spe
[] = {
5657 "ev0h", "ev1h", "ev2h", "ev3h",
5658 "ev4h", "ev5h", "ev6h", "ev7h",
5659 "ev8h", "ev9h", "ev10h", "ev11h",
5660 "ev12h", "ev13h", "ev14h", "ev15h",
5661 "ev16h", "ev17h", "ev18h", "ev19h",
5662 "ev20h", "ev21h", "ev22h", "ev23h",
5663 "ev24h", "ev25h", "ev26h", "ev27h",
5664 "ev28h", "ev29h", "ev30h", "ev31h"
5668 for (i
= 0; i
< ppc_num_gprs
; i
++)
5669 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5670 PPC_SPE_UPPER_GP0_REGNUM
+ i
,
5672 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5673 PPC_SPE_ACC_REGNUM
, "acc");
5674 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5675 PPC_SPE_FSCR_REGNUM
, "spefscr");
5677 if (have_mq
|| have_fpu
|| !valid_p
)
5679 tdesc_data_cleanup (tdesc_data
);
5688 /* If we have a 64-bit binary on a 32-bit target, complain. Also
5689 complain for a 32-bit binary on a 64-bit target; we do not yet
5690 support that. For instance, the 32-bit ABI routines expect
5693 As long as there isn't an explicit target description, we'll
5694 choose one based on the BFD architecture and get a word size
5695 matching the binary (probably powerpc:common or
5696 powerpc:common64). So there is only trouble if a 64-bit target
5697 supplies a 64-bit description while debugging a 32-bit
5699 if (tdesc_wordsize
!= -1 && tdesc_wordsize
!= wordsize
)
5701 tdesc_data_cleanup (tdesc_data
);
5708 switch (elf_elfheader (info
.abfd
)->e_flags
& EF_PPC64_ABI
)
5711 elf_abi
= POWERPC_ELF_V1
;
5714 elf_abi
= POWERPC_ELF_V2
;
5721 if (soft_float_flag
== AUTO_BOOLEAN_AUTO
&& from_elf_exec
)
5723 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
5724 Tag_GNU_Power_ABI_FP
))
5727 soft_float_flag
= AUTO_BOOLEAN_FALSE
;
5730 soft_float_flag
= AUTO_BOOLEAN_TRUE
;
5737 if (vector_abi
== POWERPC_VEC_AUTO
&& from_elf_exec
)
5739 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
5740 Tag_GNU_Power_ABI_Vector
))
5743 vector_abi
= POWERPC_VEC_GENERIC
;
5746 vector_abi
= POWERPC_VEC_ALTIVEC
;
5749 vector_abi
= POWERPC_VEC_SPE
;
5757 /* At this point, the only supported ELF-based 64-bit little-endian
5758 operating system is GNU/Linux, and this uses the ELFv2 ABI by
5759 default. All other supported ELF-based operating systems use the
5760 ELFv1 ABI by default. Therefore, if the ABI marker is missing,
5761 e.g. because we run a legacy binary, or have attached to a process
5762 and have not found any associated binary file, set the default
5763 according to this heuristic. */
5764 if (elf_abi
== POWERPC_ELF_AUTO
)
5766 if (wordsize
== 8 && info
.byte_order
== BFD_ENDIAN_LITTLE
)
5767 elf_abi
= POWERPC_ELF_V2
;
5769 elf_abi
= POWERPC_ELF_V1
;
5772 if (soft_float_flag
== AUTO_BOOLEAN_TRUE
)
5774 else if (soft_float_flag
== AUTO_BOOLEAN_FALSE
)
5777 soft_float
= !have_fpu
;
5779 /* If we have a hard float binary or setting but no floating point
5780 registers, downgrade to soft float anyway. We're still somewhat
5781 useful in this scenario. */
5782 if (!soft_float
&& !have_fpu
)
5785 /* Similarly for vector registers. */
5786 if (vector_abi
== POWERPC_VEC_ALTIVEC
&& !have_altivec
)
5787 vector_abi
= POWERPC_VEC_GENERIC
;
5789 if (vector_abi
== POWERPC_VEC_SPE
&& !have_spe
)
5790 vector_abi
= POWERPC_VEC_GENERIC
;
5792 if (vector_abi
== POWERPC_VEC_AUTO
)
5795 vector_abi
= POWERPC_VEC_ALTIVEC
;
5797 vector_abi
= POWERPC_VEC_SPE
;
5799 vector_abi
= POWERPC_VEC_GENERIC
;
5802 /* Do not limit the vector ABI based on available hardware, since we
5803 do not yet know what hardware we'll decide we have. Yuck! FIXME! */
5805 /* Find a candidate among extant architectures. */
5806 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5808 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5810 /* Word size in the various PowerPC bfd_arch_info structs isn't
5811 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
5812 separate word size check. */
5813 tdep
= gdbarch_tdep (arches
->gdbarch
);
5814 if (tdep
&& tdep
->elf_abi
!= elf_abi
)
5816 if (tdep
&& tdep
->soft_float
!= soft_float
)
5818 if (tdep
&& tdep
->vector_abi
!= vector_abi
)
5820 if (tdep
&& tdep
->wordsize
== wordsize
)
5822 if (tdesc_data
!= NULL
)
5823 tdesc_data_cleanup (tdesc_data
);
5824 return arches
->gdbarch
;
5828 /* None found, create a new architecture from INFO, whose bfd_arch_info
5829 validity depends on the source:
5830 - executable useless
5831 - rs6000_host_arch() good
5833 - "set arch" trust blindly
5834 - GDB startup useless but harmless */
5836 tdep
= XCNEW (struct gdbarch_tdep
);
5837 tdep
->wordsize
= wordsize
;
5838 tdep
->elf_abi
= elf_abi
;
5839 tdep
->soft_float
= soft_float
;
5840 tdep
->vector_abi
= vector_abi
;
5842 gdbarch
= gdbarch_alloc (&info
, tdep
);
5844 tdep
->ppc_gp0_regnum
= PPC_R0_REGNUM
;
5845 tdep
->ppc_toc_regnum
= PPC_R0_REGNUM
+ 2;
5846 tdep
->ppc_ps_regnum
= PPC_MSR_REGNUM
;
5847 tdep
->ppc_cr_regnum
= PPC_CR_REGNUM
;
5848 tdep
->ppc_lr_regnum
= PPC_LR_REGNUM
;
5849 tdep
->ppc_ctr_regnum
= PPC_CTR_REGNUM
;
5850 tdep
->ppc_xer_regnum
= PPC_XER_REGNUM
;
5851 tdep
->ppc_mq_regnum
= have_mq
? PPC_MQ_REGNUM
: -1;
5853 tdep
->ppc_fp0_regnum
= have_fpu
? PPC_F0_REGNUM
: -1;
5854 tdep
->ppc_fpscr_regnum
= have_fpu
? PPC_FPSCR_REGNUM
: -1;
5855 tdep
->ppc_vsr0_upper_regnum
= have_vsx
? PPC_VSR0_UPPER_REGNUM
: -1;
5856 tdep
->ppc_vr0_regnum
= have_altivec
? PPC_VR0_REGNUM
: -1;
5857 tdep
->ppc_vrsave_regnum
= have_altivec
? PPC_VRSAVE_REGNUM
: -1;
5858 tdep
->ppc_ev0_upper_regnum
= have_spe
? PPC_SPE_UPPER_GP0_REGNUM
: -1;
5859 tdep
->ppc_acc_regnum
= have_spe
? PPC_SPE_ACC_REGNUM
: -1;
5860 tdep
->ppc_spefscr_regnum
= have_spe
? PPC_SPE_FSCR_REGNUM
: -1;
5862 set_gdbarch_pc_regnum (gdbarch
, PPC_PC_REGNUM
);
5863 set_gdbarch_sp_regnum (gdbarch
, PPC_R0_REGNUM
+ 1);
5864 set_gdbarch_deprecated_fp_regnum (gdbarch
, PPC_R0_REGNUM
+ 1);
5865 set_gdbarch_fp0_regnum (gdbarch
, tdep
->ppc_fp0_regnum
);
5866 set_gdbarch_register_sim_regno (gdbarch
, rs6000_register_sim_regno
);
5868 /* The XML specification for PowerPC sensibly calls the MSR "msr".
5869 GDB traditionally called it "ps", though, so let GDB add an
5871 set_gdbarch_ps_regnum (gdbarch
, tdep
->ppc_ps_regnum
);
5874 set_gdbarch_return_value (gdbarch
, ppc64_sysv_abi_return_value
);
5876 set_gdbarch_return_value (gdbarch
, ppc_sysv_abi_return_value
);
5878 /* Set lr_frame_offset. */
5880 tdep
->lr_frame_offset
= 16;
5882 tdep
->lr_frame_offset
= 4;
5884 if (have_spe
|| have_dfp
|| have_vsx
)
5886 set_gdbarch_pseudo_register_read (gdbarch
, rs6000_pseudo_register_read
);
5887 set_gdbarch_pseudo_register_write (gdbarch
,
5888 rs6000_pseudo_register_write
);
5891 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
5893 /* Select instruction printer. */
5894 if (arch
== bfd_arch_rs6000
)
5895 set_gdbarch_print_insn (gdbarch
, print_insn_rs6000
);
5897 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_powerpc
);
5899 set_gdbarch_num_regs (gdbarch
, PPC_NUM_REGS
);
5902 num_pseudoregs
+= 32;
5904 num_pseudoregs
+= 16;
5906 /* Include both VSX and Extended FP registers. */
5907 num_pseudoregs
+= 96;
5909 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudoregs
);
5911 set_gdbarch_ptr_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
5912 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
5913 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
5914 set_gdbarch_long_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
5915 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
5916 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
5917 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
5918 set_gdbarch_long_double_bit (gdbarch
, 16 * TARGET_CHAR_BIT
);
5919 set_gdbarch_char_signed (gdbarch
, 0);
5921 set_gdbarch_frame_align (gdbarch
, rs6000_frame_align
);
5924 set_gdbarch_frame_red_zone_size (gdbarch
, 288);
5926 set_gdbarch_convert_register_p (gdbarch
, rs6000_convert_register_p
);
5927 set_gdbarch_register_to_value (gdbarch
, rs6000_register_to_value
);
5928 set_gdbarch_value_to_register (gdbarch
, rs6000_value_to_register
);
5930 set_gdbarch_stab_reg_to_regnum (gdbarch
, rs6000_stab_reg_to_regnum
);
5931 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, rs6000_dwarf2_reg_to_regnum
);
5934 set_gdbarch_push_dummy_call (gdbarch
, ppc_sysv_abi_push_dummy_call
);
5935 else if (wordsize
== 8)
5936 set_gdbarch_push_dummy_call (gdbarch
, ppc64_sysv_abi_push_dummy_call
);
5938 set_gdbarch_skip_prologue (gdbarch
, rs6000_skip_prologue
);
5939 set_gdbarch_stack_frame_destroyed_p (gdbarch
, rs6000_stack_frame_destroyed_p
);
5940 set_gdbarch_skip_main_prologue (gdbarch
, rs6000_skip_main_prologue
);
5942 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
5943 set_gdbarch_breakpoint_from_pc (gdbarch
, rs6000_breakpoint_from_pc
);
5945 /* The value of symbols of type N_SO and N_FUN maybe null when
5947 set_gdbarch_sofun_address_maybe_missing (gdbarch
, 1);
5949 /* Handles single stepping of atomic sequences. */
5950 set_gdbarch_software_single_step (gdbarch
, ppc_deal_with_atomic_sequence
);
5952 /* Not sure on this. FIXMEmgo */
5953 set_gdbarch_frame_args_skip (gdbarch
, 8);
5955 /* Helpers for function argument information. */
5956 set_gdbarch_fetch_pointer_argument (gdbarch
, rs6000_fetch_pointer_argument
);
5959 set_gdbarch_in_solib_return_trampoline
5960 (gdbarch
, rs6000_in_solib_return_trampoline
);
5961 set_gdbarch_skip_trampoline_code (gdbarch
, rs6000_skip_trampoline_code
);
5963 /* Hook in the DWARF CFI frame unwinder. */
5964 dwarf2_append_unwinders (gdbarch
);
5965 dwarf2_frame_set_adjust_regnum (gdbarch
, rs6000_adjust_frame_regnum
);
5967 /* Frame handling. */
5968 dwarf2_frame_set_init_reg (gdbarch
, ppc_dwarf2_frame_init_reg
);
5970 /* Setup displaced stepping. */
5971 set_gdbarch_displaced_step_copy_insn (gdbarch
,
5972 ppc_displaced_step_copy_insn
);
5973 set_gdbarch_displaced_step_hw_singlestep (gdbarch
,
5974 ppc_displaced_step_hw_singlestep
);
5975 set_gdbarch_displaced_step_fixup (gdbarch
, ppc_displaced_step_fixup
);
5976 set_gdbarch_displaced_step_free_closure (gdbarch
,
5977 simple_displaced_step_free_closure
);
5978 set_gdbarch_displaced_step_location (gdbarch
,
5979 displaced_step_at_entry_point
);
5981 set_gdbarch_max_insn_length (gdbarch
, PPC_INSN_SIZE
);
5983 /* Hook in ABI-specific overrides, if they have been registered. */
5984 info
.target_desc
= tdesc
;
5985 info
.tdep_info
= (void *) tdesc_data
;
5986 gdbarch_init_osabi (info
, gdbarch
);
5990 case GDB_OSABI_LINUX
:
5991 case GDB_OSABI_NETBSD_AOUT
:
5992 case GDB_OSABI_NETBSD_ELF
:
5993 case GDB_OSABI_UNKNOWN
:
5994 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
5995 frame_unwind_append_unwinder (gdbarch
, &rs6000_epilogue_frame_unwind
);
5996 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
5997 set_gdbarch_dummy_id (gdbarch
, rs6000_dummy_id
);
5998 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
6001 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
6003 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
6004 frame_unwind_append_unwinder (gdbarch
, &rs6000_epilogue_frame_unwind
);
6005 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
6006 set_gdbarch_dummy_id (gdbarch
, rs6000_dummy_id
);
6007 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
6010 set_tdesc_pseudo_register_type (gdbarch
, rs6000_pseudo_register_type
);
6011 set_tdesc_pseudo_register_reggroup_p (gdbarch
,
6012 rs6000_pseudo_register_reggroup_p
);
6013 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
6015 /* Override the normal target description method to make the SPE upper
6016 halves anonymous. */
6017 set_gdbarch_register_name (gdbarch
, rs6000_register_name
);
6019 /* Choose register numbers for all supported pseudo-registers. */
6020 tdep
->ppc_ev0_regnum
= -1;
6021 tdep
->ppc_dl0_regnum
= -1;
6022 tdep
->ppc_vsr0_regnum
= -1;
6023 tdep
->ppc_efpr0_regnum
= -1;
6025 cur_reg
= gdbarch_num_regs (gdbarch
);
6029 tdep
->ppc_ev0_regnum
= cur_reg
;
6034 tdep
->ppc_dl0_regnum
= cur_reg
;
6039 tdep
->ppc_vsr0_regnum
= cur_reg
;
6041 tdep
->ppc_efpr0_regnum
= cur_reg
;
6045 gdb_assert (gdbarch_num_regs (gdbarch
)
6046 + gdbarch_num_pseudo_regs (gdbarch
) == cur_reg
);
6048 /* Register the ravenscar_arch_ops. */
6049 if (mach
== bfd_mach_ppc_e500
)
6050 register_e500_ravenscar_ops (gdbarch
);
6052 register_ppc_ravenscar_ops (gdbarch
);
6058 rs6000_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
6060 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6065 /* FIXME: Dump gdbarch_tdep. */
6068 /* PowerPC-specific commands. */
6071 set_powerpc_command (char *args
, int from_tty
)
6073 printf_unfiltered (_("\
6074 \"set powerpc\" must be followed by an appropriate subcommand.\n"));
6075 help_list (setpowerpccmdlist
, "set powerpc ", all_commands
, gdb_stdout
);
6079 show_powerpc_command (char *args
, int from_tty
)
6081 cmd_show_list (showpowerpccmdlist
, from_tty
, "");
6085 powerpc_set_soft_float (char *args
, int from_tty
,
6086 struct cmd_list_element
*c
)
6088 struct gdbarch_info info
;
6090 /* Update the architecture. */
6091 gdbarch_info_init (&info
);
6092 if (!gdbarch_update_p (info
))
6093 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
6097 powerpc_set_vector_abi (char *args
, int from_tty
,
6098 struct cmd_list_element
*c
)
6100 struct gdbarch_info info
;
6103 for (vector_abi
= POWERPC_VEC_AUTO
;
6104 vector_abi
!= POWERPC_VEC_LAST
;
6106 if (strcmp (powerpc_vector_abi_string
,
6107 powerpc_vector_strings
[vector_abi
]) == 0)
6109 powerpc_vector_abi_global
= (enum powerpc_vector_abi
) vector_abi
;
6113 if (vector_abi
== POWERPC_VEC_LAST
)
6114 internal_error (__FILE__
, __LINE__
, _("Invalid vector ABI accepted: %s."),
6115 powerpc_vector_abi_string
);
6117 /* Update the architecture. */
6118 gdbarch_info_init (&info
);
6119 if (!gdbarch_update_p (info
))
6120 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
6123 /* Show the current setting of the exact watchpoints flag. */
6126 show_powerpc_exact_watchpoints (struct ui_file
*file
, int from_tty
,
6127 struct cmd_list_element
*c
,
6130 fprintf_filtered (file
, _("Use of exact watchpoints is %s.\n"), value
);
6133 /* Read a PPC instruction from memory. */
6136 read_insn (struct frame_info
*frame
, CORE_ADDR pc
)
6138 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6139 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6141 return read_memory_unsigned_integer (pc
, 4, byte_order
);
6144 /* Return non-zero if the instructions at PC match the series
6145 described in PATTERN, or zero otherwise. PATTERN is an array of
6146 'struct ppc_insn_pattern' objects, terminated by an entry whose
6149 When the match is successful, fill INSN[i] with what PATTERN[i]
6150 matched. If PATTERN[i] is optional, and the instruction wasn't
6151 present, set INSN[i] to 0 (which is not a valid PPC instruction).
6152 INSN should have as many elements as PATTERN. Note that, if
6153 PATTERN contains optional instructions which aren't present in
6154 memory, then INSN will have holes, so INSN[i] isn't necessarily the
6155 i'th instruction in memory. */
6158 ppc_insns_match_pattern (struct frame_info
*frame
, CORE_ADDR pc
,
6159 struct ppc_insn_pattern
*pattern
,
6160 unsigned int *insns
)
6165 for (i
= 0, insn
= 0; pattern
[i
].mask
; i
++)
6168 insn
= read_insn (frame
, pc
);
6170 if ((insn
& pattern
[i
].mask
) == pattern
[i
].data
)
6176 else if (!pattern
[i
].optional
)
6183 /* Return the 'd' field of the d-form instruction INSN, properly
6187 ppc_insn_d_field (unsigned int insn
)
6189 return ((((CORE_ADDR
) insn
& 0xffff) ^ 0x8000) - 0x8000);
6192 /* Return the 'ds' field of the ds-form instruction INSN, with the two
6193 zero bits concatenated at the right, and properly
6197 ppc_insn_ds_field (unsigned int insn
)
6199 return ((((CORE_ADDR
) insn
& 0xfffc) ^ 0x8000) - 0x8000);
6202 /* Initialization code. */
6204 /* -Wmissing-prototypes */
6205 extern initialize_file_ftype _initialize_rs6000_tdep
;
6208 _initialize_rs6000_tdep (void)
6210 gdbarch_register (bfd_arch_rs6000
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
6211 gdbarch_register (bfd_arch_powerpc
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
6213 /* Initialize the standard target descriptions. */
6214 initialize_tdesc_powerpc_32 ();
6215 initialize_tdesc_powerpc_altivec32 ();
6216 initialize_tdesc_powerpc_vsx32 ();
6217 initialize_tdesc_powerpc_403 ();
6218 initialize_tdesc_powerpc_403gc ();
6219 initialize_tdesc_powerpc_405 ();
6220 initialize_tdesc_powerpc_505 ();
6221 initialize_tdesc_powerpc_601 ();
6222 initialize_tdesc_powerpc_602 ();
6223 initialize_tdesc_powerpc_603 ();
6224 initialize_tdesc_powerpc_604 ();
6225 initialize_tdesc_powerpc_64 ();
6226 initialize_tdesc_powerpc_altivec64 ();
6227 initialize_tdesc_powerpc_vsx64 ();
6228 initialize_tdesc_powerpc_7400 ();
6229 initialize_tdesc_powerpc_750 ();
6230 initialize_tdesc_powerpc_860 ();
6231 initialize_tdesc_powerpc_e500 ();
6232 initialize_tdesc_rs6000 ();
6234 /* Add root prefix command for all "set powerpc"/"show powerpc"
6236 add_prefix_cmd ("powerpc", no_class
, set_powerpc_command
,
6237 _("Various PowerPC-specific commands."),
6238 &setpowerpccmdlist
, "set powerpc ", 0, &setlist
);
6240 add_prefix_cmd ("powerpc", no_class
, show_powerpc_command
,
6241 _("Various PowerPC-specific commands."),
6242 &showpowerpccmdlist
, "show powerpc ", 0, &showlist
);
6244 /* Add a command to allow the user to force the ABI. */
6245 add_setshow_auto_boolean_cmd ("soft-float", class_support
,
6246 &powerpc_soft_float_global
,
6247 _("Set whether to use a soft-float ABI."),
6248 _("Show whether to use a soft-float ABI."),
6250 powerpc_set_soft_float
, NULL
,
6251 &setpowerpccmdlist
, &showpowerpccmdlist
);
6253 add_setshow_enum_cmd ("vector-abi", class_support
, powerpc_vector_strings
,
6254 &powerpc_vector_abi_string
,
6255 _("Set the vector ABI."),
6256 _("Show the vector ABI."),
6257 NULL
, powerpc_set_vector_abi
, NULL
,
6258 &setpowerpccmdlist
, &showpowerpccmdlist
);
6260 add_setshow_boolean_cmd ("exact-watchpoints", class_support
,
6261 &target_exact_watchpoints
,
6263 Set whether to use just one debug register for watchpoints on scalars."),
6265 Show whether to use just one debug register for watchpoints on scalars."),
6267 If true, GDB will use only one debug register when watching a variable of\n\
6268 scalar type, thus assuming that the variable is accessed through the address\n\
6269 of its first byte."),
6270 NULL
, show_powerpc_exact_watchpoints
,
6271 &setpowerpccmdlist
, &showpowerpccmdlist
);