1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 Boston, MA 02110-1301, USA. */
32 #include "arch-utils.h"
37 #include "parser-defs.h"
40 #include "sim-regno.h"
41 #include "gdb/sim-ppc.h"
42 #include "reggroups.h"
44 #include "libbfd.h" /* for bfd_default_set_arch_mach */
45 #include "coff/internal.h" /* for libcoff.h */
46 #include "libcoff.h" /* for xcoff_data */
47 #include "coff/xcoff.h"
52 #include "solib-svr4.h"
55 #include "gdb_assert.h"
58 #include "trad-frame.h"
59 #include "frame-unwind.h"
60 #include "frame-base.h"
62 #include "rs6000-tdep.h"
64 /* If the kernel has to deliver a signal, it pushes a sigcontext
65 structure on the stack and then calls the signal handler, passing
66 the address of the sigcontext in an argument register. Usually
67 the signal handler doesn't save this register, so we have to
68 access the sigcontext structure via an offset from the signal handler
70 The following constants were determined by experimentation on AIX 3.2. */
71 #define SIG_FRAME_PC_OFFSET 96
72 #define SIG_FRAME_LR_OFFSET 108
73 #define SIG_FRAME_FP_OFFSET 284
75 /* To be used by skip_prologue. */
77 struct rs6000_framedata
79 int offset
; /* total size of frame --- the distance
80 by which we decrement sp to allocate
82 int saved_gpr
; /* smallest # of saved gpr */
83 int saved_fpr
; /* smallest # of saved fpr */
84 int saved_vr
; /* smallest # of saved vr */
85 int saved_ev
; /* smallest # of saved ev */
86 int alloca_reg
; /* alloca register number (frame ptr) */
87 char frameless
; /* true if frameless functions. */
88 char nosavedpc
; /* true if pc not saved. */
89 int gpr_offset
; /* offset of saved gprs from prev sp */
90 int fpr_offset
; /* offset of saved fprs from prev sp */
91 int vr_offset
; /* offset of saved vrs from prev sp */
92 int ev_offset
; /* offset of saved evs from prev sp */
93 int lr_offset
; /* offset of saved lr */
94 int cr_offset
; /* offset of saved cr */
95 int vrsave_offset
; /* offset of saved vrsave register */
98 /* Description of a single register. */
102 char *name
; /* name of register */
103 unsigned char sz32
; /* size on 32-bit arch, 0 if nonexistent */
104 unsigned char sz64
; /* size on 64-bit arch, 0 if nonexistent */
105 unsigned char fpr
; /* whether register is floating-point */
106 unsigned char pseudo
; /* whether register is pseudo */
107 int spr_num
; /* PowerPC SPR number, or -1 if not an SPR.
108 This is an ISA SPR number, not a GDB
112 /* Hook for determining the TOC address when calling functions in the
113 inferior under AIX. The initialization code in rs6000-nat.c sets
114 this hook to point to find_toc_address. */
116 CORE_ADDR (*rs6000_find_toc_address_hook
) (CORE_ADDR
) = NULL
;
118 /* Hook to set the current architecture when starting a child process.
119 rs6000-nat.c sets this. */
121 void (*rs6000_set_host_arch_hook
) (int) = NULL
;
123 /* Static function prototypes */
125 static CORE_ADDR
branch_dest (int opcode
, int instr
, CORE_ADDR pc
,
127 static CORE_ADDR
skip_prologue (CORE_ADDR
, CORE_ADDR
,
128 struct rs6000_framedata
*);
130 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
132 altivec_register_p (int regno
)
134 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
135 if (tdep
->ppc_vr0_regnum
< 0 || tdep
->ppc_vrsave_regnum
< 0)
138 return (regno
>= tdep
->ppc_vr0_regnum
&& regno
<= tdep
->ppc_vrsave_regnum
);
142 /* Return true if REGNO is an SPE register, false otherwise. */
144 spe_register_p (int regno
)
146 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
148 /* Is it a reference to EV0 -- EV31, and do we have those? */
149 if (tdep
->ppc_ev0_regnum
>= 0
150 && tdep
->ppc_ev31_regnum
>= 0
151 && tdep
->ppc_ev0_regnum
<= regno
&& regno
<= tdep
->ppc_ev31_regnum
)
154 /* Is it a reference to one of the raw upper GPR halves? */
155 if (tdep
->ppc_ev0_upper_regnum
>= 0
156 && tdep
->ppc_ev0_upper_regnum
<= regno
157 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
160 /* Is it a reference to the 64-bit accumulator, and do we have that? */
161 if (tdep
->ppc_acc_regnum
>= 0
162 && tdep
->ppc_acc_regnum
== regno
)
165 /* Is it a reference to the SPE floating-point status and control register,
166 and do we have that? */
167 if (tdep
->ppc_spefscr_regnum
>= 0
168 && tdep
->ppc_spefscr_regnum
== regno
)
175 /* Return non-zero if the architecture described by GDBARCH has
176 floating-point registers (f0 --- f31 and fpscr). */
178 ppc_floating_point_unit_p (struct gdbarch
*gdbarch
)
180 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
182 return (tdep
->ppc_fp0_regnum
>= 0
183 && tdep
->ppc_fpscr_regnum
>= 0);
187 /* Check that TABLE[GDB_REGNO] is not already initialized, and then
190 This is a helper function for init_sim_regno_table, constructing
191 the table mapping GDB register numbers to sim register numbers; we
192 initialize every element in that table to -1 before we start
195 set_sim_regno (int *table
, int gdb_regno
, int sim_regno
)
197 /* Make sure we don't try to assign any given GDB register a sim
198 register number more than once. */
199 gdb_assert (table
[gdb_regno
] == -1);
200 table
[gdb_regno
] = sim_regno
;
204 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
205 numbers to simulator register numbers, based on the values placed
206 in the ARCH->tdep->ppc_foo_regnum members. */
208 init_sim_regno_table (struct gdbarch
*arch
)
210 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
211 int total_regs
= gdbarch_num_regs (arch
) + gdbarch_num_pseudo_regs (arch
);
212 const struct reg
*regs
= tdep
->regs
;
213 int *sim_regno
= GDBARCH_OBSTACK_CALLOC (arch
, total_regs
, int);
216 /* Presume that all registers not explicitly mentioned below are
217 unavailable from the sim. */
218 for (i
= 0; i
< total_regs
; i
++)
221 /* General-purpose registers. */
222 for (i
= 0; i
< ppc_num_gprs
; i
++)
223 set_sim_regno (sim_regno
, tdep
->ppc_gp0_regnum
+ i
, sim_ppc_r0_regnum
+ i
);
225 /* Floating-point registers. */
226 if (tdep
->ppc_fp0_regnum
>= 0)
227 for (i
= 0; i
< ppc_num_fprs
; i
++)
228 set_sim_regno (sim_regno
,
229 tdep
->ppc_fp0_regnum
+ i
,
230 sim_ppc_f0_regnum
+ i
);
231 if (tdep
->ppc_fpscr_regnum
>= 0)
232 set_sim_regno (sim_regno
, tdep
->ppc_fpscr_regnum
, sim_ppc_fpscr_regnum
);
234 set_sim_regno (sim_regno
, gdbarch_pc_regnum (arch
), sim_ppc_pc_regnum
);
235 set_sim_regno (sim_regno
, tdep
->ppc_ps_regnum
, sim_ppc_ps_regnum
);
236 set_sim_regno (sim_regno
, tdep
->ppc_cr_regnum
, sim_ppc_cr_regnum
);
238 /* Segment registers. */
239 if (tdep
->ppc_sr0_regnum
>= 0)
240 for (i
= 0; i
< ppc_num_srs
; i
++)
241 set_sim_regno (sim_regno
,
242 tdep
->ppc_sr0_regnum
+ i
,
243 sim_ppc_sr0_regnum
+ i
);
245 /* Altivec registers. */
246 if (tdep
->ppc_vr0_regnum
>= 0)
248 for (i
= 0; i
< ppc_num_vrs
; i
++)
249 set_sim_regno (sim_regno
,
250 tdep
->ppc_vr0_regnum
+ i
,
251 sim_ppc_vr0_regnum
+ i
);
253 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
254 we can treat this more like the other cases. */
255 set_sim_regno (sim_regno
,
256 tdep
->ppc_vr0_regnum
+ ppc_num_vrs
,
257 sim_ppc_vscr_regnum
);
259 /* vsave is a special-purpose register, so the code below handles it. */
261 /* SPE APU (E500) registers. */
262 if (tdep
->ppc_ev0_regnum
>= 0)
263 for (i
= 0; i
< ppc_num_gprs
; i
++)
264 set_sim_regno (sim_regno
,
265 tdep
->ppc_ev0_regnum
+ i
,
266 sim_ppc_ev0_regnum
+ i
);
267 if (tdep
->ppc_ev0_upper_regnum
>= 0)
268 for (i
= 0; i
< ppc_num_gprs
; i
++)
269 set_sim_regno (sim_regno
,
270 tdep
->ppc_ev0_upper_regnum
+ i
,
271 sim_ppc_rh0_regnum
+ i
);
272 if (tdep
->ppc_acc_regnum
>= 0)
273 set_sim_regno (sim_regno
, tdep
->ppc_acc_regnum
, sim_ppc_acc_regnum
);
274 /* spefscr is a special-purpose register, so the code below handles it. */
276 /* Now handle all special-purpose registers. Verify that they
277 haven't mistakenly been assigned numbers by any of the above
279 for (i
= 0; i
< total_regs
; i
++)
280 if (regs
[i
].spr_num
>= 0)
281 set_sim_regno (sim_regno
, i
, regs
[i
].spr_num
+ sim_ppc_spr0_regnum
);
283 /* Drop the initialized array into place. */
284 tdep
->sim_regno
= sim_regno
;
288 /* Given a GDB register number REG, return the corresponding SIM
291 rs6000_register_sim_regno (int reg
)
293 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
296 gdb_assert (0 <= reg
&& reg
<= NUM_REGS
+ NUM_PSEUDO_REGS
);
297 sim_regno
= tdep
->sim_regno
[reg
];
302 return LEGACY_SIM_REGNO_IGNORE
;
307 /* Register set support functions. */
310 ppc_supply_reg (struct regcache
*regcache
, int regnum
,
311 const gdb_byte
*regs
, size_t offset
)
313 if (regnum
!= -1 && offset
!= -1)
314 regcache_raw_supply (regcache
, regnum
, regs
+ offset
);
318 ppc_collect_reg (const struct regcache
*regcache
, int regnum
,
319 gdb_byte
*regs
, size_t offset
)
321 if (regnum
!= -1 && offset
!= -1)
322 regcache_raw_collect (regcache
, regnum
, regs
+ offset
);
325 /* Supply register REGNUM in the general-purpose register set REGSET
326 from the buffer specified by GREGS and LEN to register cache
327 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
330 ppc_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
331 int regnum
, const void *gregs
, size_t len
)
333 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
334 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
335 const struct ppc_reg_offsets
*offsets
= regset
->descr
;
339 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
340 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
343 if (regnum
== -1 || regnum
== i
)
344 ppc_supply_reg (regcache
, i
, gregs
, offset
);
347 if (regnum
== -1 || regnum
== PC_REGNUM
)
348 ppc_supply_reg (regcache
, PC_REGNUM
, gregs
, offsets
->pc_offset
);
349 if (regnum
== -1 || regnum
== tdep
->ppc_ps_regnum
)
350 ppc_supply_reg (regcache
, tdep
->ppc_ps_regnum
,
351 gregs
, offsets
->ps_offset
);
352 if (regnum
== -1 || regnum
== tdep
->ppc_cr_regnum
)
353 ppc_supply_reg (regcache
, tdep
->ppc_cr_regnum
,
354 gregs
, offsets
->cr_offset
);
355 if (regnum
== -1 || regnum
== tdep
->ppc_lr_regnum
)
356 ppc_supply_reg (regcache
, tdep
->ppc_lr_regnum
,
357 gregs
, offsets
->lr_offset
);
358 if (regnum
== -1 || regnum
== tdep
->ppc_ctr_regnum
)
359 ppc_supply_reg (regcache
, tdep
->ppc_ctr_regnum
,
360 gregs
, offsets
->ctr_offset
);
361 if (regnum
== -1 || regnum
== tdep
->ppc_xer_regnum
)
362 ppc_supply_reg (regcache
, tdep
->ppc_xer_regnum
,
363 gregs
, offsets
->cr_offset
);
364 if (regnum
== -1 || regnum
== tdep
->ppc_mq_regnum
)
365 ppc_supply_reg (regcache
, tdep
->ppc_mq_regnum
, gregs
, offsets
->mq_offset
);
368 /* Supply register REGNUM in the floating-point register set REGSET
369 from the buffer specified by FPREGS and LEN to register cache
370 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
373 ppc_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
374 int regnum
, const void *fpregs
, size_t len
)
376 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
377 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
378 const struct ppc_reg_offsets
*offsets
= regset
->descr
;
382 gdb_assert (ppc_floating_point_unit_p (gdbarch
));
384 offset
= offsets
->f0_offset
;
385 for (i
= tdep
->ppc_fp0_regnum
;
386 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
389 if (regnum
== -1 || regnum
== i
)
390 ppc_supply_reg (regcache
, i
, fpregs
, offset
);
393 if (regnum
== -1 || regnum
== tdep
->ppc_fpscr_regnum
)
394 ppc_supply_reg (regcache
, tdep
->ppc_fpscr_regnum
,
395 fpregs
, offsets
->fpscr_offset
);
398 /* Collect register REGNUM in the general-purpose register set
399 REGSET. from register cache REGCACHE into the buffer specified by
400 GREGS and LEN. If REGNUM is -1, do this for all registers in
404 ppc_collect_gregset (const struct regset
*regset
,
405 const struct regcache
*regcache
,
406 int regnum
, void *gregs
, size_t len
)
408 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
409 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
410 const struct ppc_reg_offsets
*offsets
= regset
->descr
;
414 offset
= offsets
->r0_offset
;
415 for (i
= tdep
->ppc_gp0_regnum
;
416 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
419 if (regnum
== -1 || regnum
== i
)
420 ppc_collect_reg (regcache
, i
, gregs
, offset
);
423 if (regnum
== -1 || regnum
== PC_REGNUM
)
424 ppc_collect_reg (regcache
, PC_REGNUM
, gregs
, offsets
->pc_offset
);
425 if (regnum
== -1 || regnum
== tdep
->ppc_ps_regnum
)
426 ppc_collect_reg (regcache
, tdep
->ppc_ps_regnum
,
427 gregs
, offsets
->ps_offset
);
428 if (regnum
== -1 || regnum
== tdep
->ppc_cr_regnum
)
429 ppc_collect_reg (regcache
, tdep
->ppc_cr_regnum
,
430 gregs
, offsets
->cr_offset
);
431 if (regnum
== -1 || regnum
== tdep
->ppc_lr_regnum
)
432 ppc_collect_reg (regcache
, tdep
->ppc_lr_regnum
,
433 gregs
, offsets
->lr_offset
);
434 if (regnum
== -1 || regnum
== tdep
->ppc_ctr_regnum
)
435 ppc_collect_reg (regcache
, tdep
->ppc_ctr_regnum
,
436 gregs
, offsets
->ctr_offset
);
437 if (regnum
== -1 || regnum
== tdep
->ppc_xer_regnum
)
438 ppc_collect_reg (regcache
, tdep
->ppc_xer_regnum
,
439 gregs
, offsets
->xer_offset
);
440 if (regnum
== -1 || regnum
== tdep
->ppc_mq_regnum
)
441 ppc_collect_reg (regcache
, tdep
->ppc_mq_regnum
,
442 gregs
, offsets
->mq_offset
);
445 /* Collect register REGNUM in the floating-point register set
446 REGSET. from register cache REGCACHE into the buffer specified by
447 FPREGS and LEN. If REGNUM is -1, do this for all registers in
451 ppc_collect_fpregset (const struct regset
*regset
,
452 const struct regcache
*regcache
,
453 int regnum
, void *fpregs
, size_t len
)
455 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
456 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
457 const struct ppc_reg_offsets
*offsets
= regset
->descr
;
461 gdb_assert (ppc_floating_point_unit_p (gdbarch
));
463 offset
= offsets
->f0_offset
;
464 for (i
= tdep
->ppc_fp0_regnum
;
465 i
<= tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
468 if (regnum
== -1 || regnum
== i
)
469 ppc_collect_reg (regcache
, i
, fpregs
, offset
);
472 if (regnum
== -1 || regnum
== tdep
->ppc_fpscr_regnum
)
473 ppc_collect_reg (regcache
, tdep
->ppc_fpscr_regnum
,
474 fpregs
, offsets
->fpscr_offset
);
478 /* Read a LEN-byte address from debugged memory address MEMADDR. */
481 read_memory_addr (CORE_ADDR memaddr
, int len
)
483 return read_memory_unsigned_integer (memaddr
, len
);
487 rs6000_skip_prologue (CORE_ADDR pc
)
489 struct rs6000_framedata frame
;
490 pc
= skip_prologue (pc
, 0, &frame
);
495 insn_changes_sp_or_jumps (unsigned long insn
)
497 int opcode
= (insn
>> 26) & 0x03f;
498 int sd
= (insn
>> 21) & 0x01f;
499 int a
= (insn
>> 16) & 0x01f;
500 int subcode
= (insn
>> 1) & 0x3ff;
502 /* Changes the stack pointer. */
504 /* NOTE: There are many ways to change the value of a given register.
505 The ways below are those used when the register is R1, the SP,
506 in a funtion's epilogue. */
508 if (opcode
== 31 && subcode
== 444 && a
== 1)
509 return 1; /* mr R1,Rn */
510 if (opcode
== 14 && sd
== 1)
511 return 1; /* addi R1,Rn,simm */
512 if (opcode
== 58 && sd
== 1)
513 return 1; /* ld R1,ds(Rn) */
515 /* Transfers control. */
521 if (opcode
== 19 && subcode
== 16)
523 if (opcode
== 19 && subcode
== 528)
524 return 1; /* bcctr */
529 /* Return true if we are in the function's epilogue, i.e. after the
530 instruction that destroyed the function's stack frame.
532 1) scan forward from the point of execution:
533 a) If you find an instruction that modifies the stack pointer
534 or transfers control (except a return), execution is not in
536 b) Stop scanning if you find a return instruction or reach the
537 end of the function or reach the hard limit for the size of
539 2) scan backward from the point of execution:
540 a) If you find an instruction that modifies the stack pointer,
541 execution *is* in an epilogue, return.
542 b) Stop scanning if you reach an instruction that transfers
543 control or the beginning of the function or reach the hard
544 limit for the size of an epilogue. */
547 rs6000_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
549 bfd_byte insn_buf
[PPC_INSN_SIZE
];
550 CORE_ADDR scan_pc
, func_start
, func_end
, epilogue_start
, epilogue_end
;
552 struct frame_info
*curfrm
;
554 /* Find the search limits based on function boundaries and hard limit. */
556 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
559 epilogue_start
= pc
- PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
560 if (epilogue_start
< func_start
) epilogue_start
= func_start
;
562 epilogue_end
= pc
+ PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
563 if (epilogue_end
> func_end
) epilogue_end
= func_end
;
565 curfrm
= get_current_frame ();
567 /* Scan forward until next 'blr'. */
569 for (scan_pc
= pc
; scan_pc
< epilogue_end
; scan_pc
+= PPC_INSN_SIZE
)
571 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
573 insn
= extract_signed_integer (insn_buf
, PPC_INSN_SIZE
);
574 if (insn
== 0x4e800020)
576 if (insn_changes_sp_or_jumps (insn
))
580 /* Scan backward until adjustment to stack pointer (R1). */
582 for (scan_pc
= pc
- PPC_INSN_SIZE
;
583 scan_pc
>= epilogue_start
;
584 scan_pc
-= PPC_INSN_SIZE
)
586 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
588 insn
= extract_signed_integer (insn_buf
, PPC_INSN_SIZE
);
589 if (insn_changes_sp_or_jumps (insn
))
597 /* Fill in fi->saved_regs */
599 struct frame_extra_info
601 /* Functions calling alloca() change the value of the stack
602 pointer. We need to use initial stack pointer (which is saved in
603 r31 by gcc) in such cases. If a compiler emits traceback table,
604 then we should use the alloca register specified in traceback
606 CORE_ADDR initial_sp
; /* initial stack pointer. */
609 /* Get the ith function argument for the current function. */
611 rs6000_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
614 return get_frame_register_unsigned (frame
, 3 + argi
);
617 /* Calculate the destination of a branch/jump. Return -1 if not a branch. */
620 branch_dest (int opcode
, int instr
, CORE_ADDR pc
, CORE_ADDR safety
)
627 absolute
= (int) ((instr
>> 1) & 1);
632 immediate
= ((instr
& ~3) << 6) >> 6; /* br unconditional */
636 dest
= pc
+ immediate
;
640 immediate
= ((instr
& ~3) << 16) >> 16; /* br conditional */
644 dest
= pc
+ immediate
;
648 ext_op
= (instr
>> 1) & 0x3ff;
650 if (ext_op
== 16) /* br conditional register */
652 dest
= read_register (gdbarch_tdep (current_gdbarch
)->ppc_lr_regnum
) & ~3;
654 /* If we are about to return from a signal handler, dest is
655 something like 0x3c90. The current frame is a signal handler
656 caller frame, upon completion of the sigreturn system call
657 execution will return to the saved PC in the frame. */
658 if (dest
< TEXT_SEGMENT_BASE
)
660 struct frame_info
*fi
;
662 fi
= get_current_frame ();
664 dest
= read_memory_addr (get_frame_base (fi
) + SIG_FRAME_PC_OFFSET
,
665 gdbarch_tdep (current_gdbarch
)->wordsize
);
669 else if (ext_op
== 528) /* br cond to count reg */
671 dest
= read_register (gdbarch_tdep (current_gdbarch
)->ppc_ctr_regnum
) & ~3;
673 /* If we are about to execute a system call, dest is something
674 like 0x22fc or 0x3b00. Upon completion the system call
675 will return to the address in the link register. */
676 if (dest
< TEXT_SEGMENT_BASE
)
677 dest
= read_register (gdbarch_tdep (current_gdbarch
)->ppc_lr_regnum
) & ~3;
686 return (dest
< TEXT_SEGMENT_BASE
) ? safety
: dest
;
690 /* Sequence of bytes for breakpoint instruction. */
692 const static unsigned char *
693 rs6000_breakpoint_from_pc (CORE_ADDR
*bp_addr
, int *bp_size
)
695 static unsigned char big_breakpoint
[] = { 0x7d, 0x82, 0x10, 0x08 };
696 static unsigned char little_breakpoint
[] = { 0x08, 0x10, 0x82, 0x7d };
698 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
699 return big_breakpoint
;
701 return little_breakpoint
;
705 /* AIX does not support PT_STEP. Simulate it. */
708 rs6000_software_single_step (enum target_signal signal
,
709 int insert_breakpoints_p
)
713 const gdb_byte
*breakp
= rs6000_breakpoint_from_pc (&dummy
, &breakp_sz
);
719 if (insert_breakpoints_p
)
723 insn
= read_memory_integer (loc
, 4);
725 breaks
[0] = loc
+ breakp_sz
;
727 breaks
[1] = branch_dest (opcode
, insn
, loc
, breaks
[0]);
729 /* Don't put two breakpoints on the same address. */
730 if (breaks
[1] == breaks
[0])
733 for (ii
= 0; ii
< 2; ++ii
)
735 /* ignore invalid breakpoint. */
736 if (breaks
[ii
] == -1)
738 insert_single_step_breakpoint (breaks
[ii
]);
742 remove_single_step_breakpoints ();
744 errno
= 0; /* FIXME, don't ignore errors! */
745 /* What errors? {read,write}_memory call error(). */
749 /* return pc value after skipping a function prologue and also return
750 information about a function frame.
752 in struct rs6000_framedata fdata:
753 - frameless is TRUE, if function does not have a frame.
754 - nosavedpc is TRUE, if function does not save %pc value in its frame.
755 - offset is the initial size of this stack frame --- the amount by
756 which we decrement the sp to allocate the frame.
757 - saved_gpr is the number of the first saved gpr.
758 - saved_fpr is the number of the first saved fpr.
759 - saved_vr is the number of the first saved vr.
760 - saved_ev is the number of the first saved ev.
761 - alloca_reg is the number of the register used for alloca() handling.
763 - gpr_offset is the offset of the first saved gpr from the previous frame.
764 - fpr_offset is the offset of the first saved fpr from the previous frame.
765 - vr_offset is the offset of the first saved vr from the previous frame.
766 - ev_offset is the offset of the first saved ev from the previous frame.
767 - lr_offset is the offset of the saved lr
768 - cr_offset is the offset of the saved cr
769 - vrsave_offset is the offset of the saved vrsave register
772 #define SIGNED_SHORT(x) \
773 ((sizeof (short) == 2) \
774 ? ((int)(short)(x)) \
775 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
777 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
779 /* Limit the number of skipped non-prologue instructions, as the examining
780 of the prologue is expensive. */
781 static int max_skip_non_prologue_insns
= 10;
783 /* Given PC representing the starting address of a function, and
784 LIM_PC which is the (sloppy) limit to which to scan when looking
785 for a prologue, attempt to further refine this limit by using
786 the line data in the symbol table. If successful, a better guess
787 on where the prologue ends is returned, otherwise the previous
788 value of lim_pc is returned. */
790 /* FIXME: cagney/2004-02-14: This function and logic have largely been
791 superseded by skip_prologue_using_sal. */
794 refine_prologue_limit (CORE_ADDR pc
, CORE_ADDR lim_pc
)
796 struct symtab_and_line prologue_sal
;
798 prologue_sal
= find_pc_line (pc
, 0);
799 if (prologue_sal
.line
!= 0)
802 CORE_ADDR addr
= prologue_sal
.end
;
804 /* Handle the case in which compiler's optimizer/scheduler
805 has moved instructions into the prologue. We scan ahead
806 in the function looking for address ranges whose corresponding
807 line number is less than or equal to the first one that we
808 found for the function. (It can be less than when the
809 scheduler puts a body instruction before the first prologue
811 for (i
= 2 * max_skip_non_prologue_insns
;
812 i
> 0 && (lim_pc
== 0 || addr
< lim_pc
);
815 struct symtab_and_line sal
;
817 sal
= find_pc_line (addr
, 0);
820 if (sal
.line
<= prologue_sal
.line
821 && sal
.symtab
== prologue_sal
.symtab
)
828 if (lim_pc
== 0 || prologue_sal
.end
< lim_pc
)
829 lim_pc
= prologue_sal
.end
;
834 /* Return nonzero if the given instruction OP can be part of the prologue
835 of a function and saves a parameter on the stack. FRAMEP should be
836 set if one of the previous instructions in the function has set the
840 store_param_on_stack_p (unsigned long op
, int framep
, int *r0_contains_arg
)
842 /* Move parameters from argument registers to temporary register. */
843 if ((op
& 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
845 /* Rx must be scratch register r0. */
846 const int rx_regno
= (op
>> 16) & 31;
847 /* Ry: Only r3 - r10 are used for parameter passing. */
848 const int ry_regno
= GET_SRC_REG (op
);
850 if (rx_regno
== 0 && ry_regno
>= 3 && ry_regno
<= 10)
852 *r0_contains_arg
= 1;
859 /* Save a General Purpose Register on stack. */
861 if ((op
& 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
862 (op
& 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
864 /* Rx: Only r3 - r10 are used for parameter passing. */
865 const int rx_regno
= GET_SRC_REG (op
);
867 return (rx_regno
>= 3 && rx_regno
<= 10);
870 /* Save a General Purpose Register on stack via the Frame Pointer. */
873 ((op
& 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
874 (op
& 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
875 (op
& 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
877 /* Rx: Usually, only r3 - r10 are used for parameter passing.
878 However, the compiler sometimes uses r0 to hold an argument. */
879 const int rx_regno
= GET_SRC_REG (op
);
881 return ((rx_regno
>= 3 && rx_regno
<= 10)
882 || (rx_regno
== 0 && *r0_contains_arg
));
885 if ((op
& 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
887 /* Only f2 - f8 are used for parameter passing. */
888 const int src_regno
= GET_SRC_REG (op
);
890 return (src_regno
>= 2 && src_regno
<= 8);
893 if (framep
&& ((op
& 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
895 /* Only f2 - f8 are used for parameter passing. */
896 const int src_regno
= GET_SRC_REG (op
);
898 return (src_regno
>= 2 && src_regno
<= 8);
901 /* Not an insn that saves a parameter on stack. */
906 skip_prologue (CORE_ADDR pc
, CORE_ADDR lim_pc
, struct rs6000_framedata
*fdata
)
908 CORE_ADDR orig_pc
= pc
;
909 CORE_ADDR last_prologue_pc
= pc
;
910 CORE_ADDR li_found_pc
= 0;
914 long vr_saved_offset
= 0;
923 int minimal_toc_loaded
= 0;
924 int prev_insn_was_prologue_insn
= 1;
925 int num_skip_non_prologue_insns
= 0;
926 int r0_contains_arg
= 0;
927 const struct bfd_arch_info
*arch_info
= gdbarch_bfd_arch_info (current_gdbarch
);
928 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
930 /* Attempt to find the end of the prologue when no limit is specified.
931 Note that refine_prologue_limit() has been written so that it may
932 be used to "refine" the limits of non-zero PC values too, but this
933 is only safe if we 1) trust the line information provided by the
934 compiler and 2) iterate enough to actually find the end of the
937 It may become a good idea at some point (for both performance and
938 accuracy) to unconditionally call refine_prologue_limit(). But,
939 until we can make a clear determination that this is beneficial,
940 we'll play it safe and only use it to obtain a limit when none
941 has been specified. */
943 lim_pc
= refine_prologue_limit (pc
, lim_pc
);
945 memset (fdata
, 0, sizeof (struct rs6000_framedata
));
946 fdata
->saved_gpr
= -1;
947 fdata
->saved_fpr
= -1;
948 fdata
->saved_vr
= -1;
949 fdata
->saved_ev
= -1;
950 fdata
->alloca_reg
= -1;
951 fdata
->frameless
= 1;
952 fdata
->nosavedpc
= 1;
956 /* Sometimes it isn't clear if an instruction is a prologue
957 instruction or not. When we encounter one of these ambiguous
958 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
959 Otherwise, we'll assume that it really is a prologue instruction. */
960 if (prev_insn_was_prologue_insn
)
961 last_prologue_pc
= pc
;
963 /* Stop scanning if we've hit the limit. */
964 if (lim_pc
!= 0 && pc
>= lim_pc
)
967 prev_insn_was_prologue_insn
= 1;
969 /* Fetch the instruction and convert it to an integer. */
970 if (target_read_memory (pc
, buf
, 4))
972 op
= extract_signed_integer (buf
, 4);
974 if ((op
& 0xfc1fffff) == 0x7c0802a6)
976 /* Since shared library / PIC code, which needs to get its
977 address at runtime, can appear to save more than one link
991 remember just the first one, but skip over additional
994 lr_reg
= (op
& 0x03e00000);
999 else if ((op
& 0xfc1fffff) == 0x7c000026)
1001 cr_reg
= (op
& 0x03e00000);
1003 r0_contains_arg
= 0;
1007 else if ((op
& 0xfc1f0000) == 0xd8010000)
1008 { /* stfd Rx,NUM(r1) */
1009 reg
= GET_SRC_REG (op
);
1010 if (fdata
->saved_fpr
== -1 || fdata
->saved_fpr
> reg
)
1012 fdata
->saved_fpr
= reg
;
1013 fdata
->fpr_offset
= SIGNED_SHORT (op
) + offset
;
1018 else if (((op
& 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
1019 (((op
& 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1020 (op
& 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1021 (op
& 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
1024 reg
= GET_SRC_REG (op
);
1025 if (fdata
->saved_gpr
== -1 || fdata
->saved_gpr
> reg
)
1027 fdata
->saved_gpr
= reg
;
1028 if ((op
& 0xfc1f0003) == 0xf8010000)
1030 fdata
->gpr_offset
= SIGNED_SHORT (op
) + offset
;
1035 else if ((op
& 0xffff0000) == 0x60000000)
1038 /* Allow nops in the prologue, but do not consider them to
1039 be part of the prologue unless followed by other prologue
1041 prev_insn_was_prologue_insn
= 0;
1045 else if ((op
& 0xffff0000) == 0x3c000000)
1046 { /* addis 0,0,NUM, used
1047 for >= 32k frames */
1048 fdata
->offset
= (op
& 0x0000ffff) << 16;
1049 fdata
->frameless
= 0;
1050 r0_contains_arg
= 0;
1054 else if ((op
& 0xffff0000) == 0x60000000)
1055 { /* ori 0,0,NUM, 2nd ha
1056 lf of >= 32k frames */
1057 fdata
->offset
|= (op
& 0x0000ffff);
1058 fdata
->frameless
= 0;
1059 r0_contains_arg
= 0;
1063 else if (lr_reg
>= 0 &&
1064 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1065 (((op
& 0xffff0000) == (lr_reg
| 0xf8010000)) ||
1066 /* stw Rx, NUM(r1) */
1067 ((op
& 0xffff0000) == (lr_reg
| 0x90010000)) ||
1068 /* stwu Rx, NUM(r1) */
1069 ((op
& 0xffff0000) == (lr_reg
| 0x94010000))))
1070 { /* where Rx == lr */
1071 fdata
->lr_offset
= offset
;
1072 fdata
->nosavedpc
= 0;
1073 /* Invalidate lr_reg, but don't set it to -1.
1074 That would mean that it had never been set. */
1076 if ((op
& 0xfc000003) == 0xf8000000 || /* std */
1077 (op
& 0xfc000000) == 0x90000000) /* stw */
1079 /* Does not update r1, so add displacement to lr_offset. */
1080 fdata
->lr_offset
+= SIGNED_SHORT (op
);
1085 else if (cr_reg
>= 0 &&
1086 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1087 (((op
& 0xffff0000) == (cr_reg
| 0xf8010000)) ||
1088 /* stw Rx, NUM(r1) */
1089 ((op
& 0xffff0000) == (cr_reg
| 0x90010000)) ||
1090 /* stwu Rx, NUM(r1) */
1091 ((op
& 0xffff0000) == (cr_reg
| 0x94010000))))
1092 { /* where Rx == cr */
1093 fdata
->cr_offset
= offset
;
1094 /* Invalidate cr_reg, but don't set it to -1.
1095 That would mean that it had never been set. */
1097 if ((op
& 0xfc000003) == 0xf8000000 ||
1098 (op
& 0xfc000000) == 0x90000000)
1100 /* Does not update r1, so add displacement to cr_offset. */
1101 fdata
->cr_offset
+= SIGNED_SHORT (op
);
1106 else if ((op
& 0xfe80ffff) == 0x42800005 && lr_reg
!= -1)
1108 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1109 prediction bits. If the LR has already been saved, we can
1113 else if (op
== 0x48000005)
1119 else if (op
== 0x48000004)
1124 else if ((op
& 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1125 in V.4 -mminimal-toc */
1126 (op
& 0xffff0000) == 0x3bde0000)
1127 { /* addi 30,30,foo@l */
1131 else if ((op
& 0xfc000001) == 0x48000001)
1135 fdata
->frameless
= 0;
1136 /* Don't skip over the subroutine call if it is not within
1137 the first three instructions of the prologue and either
1138 we have no line table information or the line info tells
1139 us that the subroutine call is not part of the line
1140 associated with the prologue. */
1141 if ((pc
- orig_pc
) > 8)
1143 struct symtab_and_line prologue_sal
= find_pc_line (orig_pc
, 0);
1144 struct symtab_and_line this_sal
= find_pc_line (pc
, 0);
1146 if ((prologue_sal
.line
== 0) || (prologue_sal
.line
!= this_sal
.line
))
1150 op
= read_memory_integer (pc
+ 4, 4);
1152 /* At this point, make sure this is not a trampoline
1153 function (a function that simply calls another functions,
1154 and nothing else). If the next is not a nop, this branch
1155 was part of the function prologue. */
1157 if (op
== 0x4def7b82 || op
== 0) /* crorc 15, 15, 15 */
1158 break; /* don't skip over
1163 /* update stack pointer */
1164 else if ((op
& 0xfc1f0000) == 0x94010000)
1165 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
1166 fdata
->frameless
= 0;
1167 fdata
->offset
= SIGNED_SHORT (op
);
1168 offset
= fdata
->offset
;
1171 else if ((op
& 0xfc1f016a) == 0x7c01016e)
1172 { /* stwux rX,r1,rY */
1173 /* no way to figure out what r1 is going to be */
1174 fdata
->frameless
= 0;
1175 offset
= fdata
->offset
;
1178 else if ((op
& 0xfc1f0003) == 0xf8010001)
1179 { /* stdu rX,NUM(r1) */
1180 fdata
->frameless
= 0;
1181 fdata
->offset
= SIGNED_SHORT (op
& ~3UL);
1182 offset
= fdata
->offset
;
1185 else if ((op
& 0xfc1f016a) == 0x7c01016a)
1186 { /* stdux rX,r1,rY */
1187 /* no way to figure out what r1 is going to be */
1188 fdata
->frameless
= 0;
1189 offset
= fdata
->offset
;
1192 /* Load up minimal toc pointer */
1193 else if (((op
>> 22) == 0x20f || /* l r31,... or l r30,... */
1194 (op
>> 22) == 0x3af) /* ld r31,... or ld r30,... */
1195 && !minimal_toc_loaded
)
1197 minimal_toc_loaded
= 1;
1200 /* move parameters from argument registers to local variable
1203 else if ((op
& 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1204 (((op
>> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1205 (((op
>> 21) & 31) <= 10) &&
1206 ((long) ((op
>> 16) & 31) >= fdata
->saved_gpr
)) /* Rx: local var reg */
1210 /* store parameters in stack */
1212 /* Move parameters from argument registers to temporary register. */
1213 else if (store_param_on_stack_p (op
, framep
, &r0_contains_arg
))
1217 /* Set up frame pointer */
1219 else if (op
== 0x603f0000 /* oril r31, r1, 0x0 */
1220 || op
== 0x7c3f0b78)
1222 fdata
->frameless
= 0;
1224 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 31);
1227 /* Another way to set up the frame pointer. */
1229 else if ((op
& 0xfc1fffff) == 0x38010000)
1230 { /* addi rX, r1, 0x0 */
1231 fdata
->frameless
= 0;
1233 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
1234 + ((op
& ~0x38010000) >> 21));
1237 /* AltiVec related instructions. */
1238 /* Store the vrsave register (spr 256) in another register for
1239 later manipulation, or load a register into the vrsave
1240 register. 2 instructions are used: mfvrsave and
1241 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1242 and mtspr SPR256, Rn. */
1243 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1244 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1245 else if ((op
& 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1247 vrsave_reg
= GET_SRC_REG (op
);
1250 else if ((op
& 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1254 /* Store the register where vrsave was saved to onto the stack:
1255 rS is the register where vrsave was stored in a previous
1257 /* 100100 sssss 00001 dddddddd dddddddd */
1258 else if ((op
& 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1260 if (vrsave_reg
== GET_SRC_REG (op
))
1262 fdata
->vrsave_offset
= SIGNED_SHORT (op
) + offset
;
1267 /* Compute the new value of vrsave, by modifying the register
1268 where vrsave was saved to. */
1269 else if (((op
& 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1270 || ((op
& 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1274 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1275 in a pair of insns to save the vector registers on the
1277 /* 001110 00000 00000 iiii iiii iiii iiii */
1278 /* 001110 01110 00000 iiii iiii iiii iiii */
1279 else if ((op
& 0xffff0000) == 0x38000000 /* li r0, SIMM */
1280 || (op
& 0xffff0000) == 0x39c00000) /* li r14, SIMM */
1282 if ((op
& 0xffff0000) == 0x38000000)
1283 r0_contains_arg
= 0;
1285 vr_saved_offset
= SIGNED_SHORT (op
);
1287 /* This insn by itself is not part of the prologue, unless
1288 if part of the pair of insns mentioned above. So do not
1289 record this insn as part of the prologue yet. */
1290 prev_insn_was_prologue_insn
= 0;
1292 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1293 /* 011111 sssss 11111 00000 00111001110 */
1294 else if ((op
& 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1296 if (pc
== (li_found_pc
+ 4))
1298 vr_reg
= GET_SRC_REG (op
);
1299 /* If this is the first vector reg to be saved, or if
1300 it has a lower number than others previously seen,
1301 reupdate the frame info. */
1302 if (fdata
->saved_vr
== -1 || fdata
->saved_vr
> vr_reg
)
1304 fdata
->saved_vr
= vr_reg
;
1305 fdata
->vr_offset
= vr_saved_offset
+ offset
;
1307 vr_saved_offset
= -1;
1312 /* End AltiVec related instructions. */
1314 /* Start BookE related instructions. */
1315 /* Store gen register S at (r31+uimm).
1316 Any register less than r13 is volatile, so we don't care. */
1317 /* 000100 sssss 11111 iiiii 01100100001 */
1318 else if (arch_info
->mach
== bfd_mach_ppc_e500
1319 && (op
& 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
1321 if ((op
& 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
1324 ev_reg
= GET_SRC_REG (op
);
1325 imm
= (op
>> 11) & 0x1f;
1326 ev_offset
= imm
* 8;
1327 /* If this is the first vector reg to be saved, or if
1328 it has a lower number than others previously seen,
1329 reupdate the frame info. */
1330 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1332 fdata
->saved_ev
= ev_reg
;
1333 fdata
->ev_offset
= ev_offset
+ offset
;
1338 /* Store gen register rS at (r1+rB). */
1339 /* 000100 sssss 00001 bbbbb 01100100000 */
1340 else if (arch_info
->mach
== bfd_mach_ppc_e500
1341 && (op
& 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1343 if (pc
== (li_found_pc
+ 4))
1345 ev_reg
= GET_SRC_REG (op
);
1346 /* If this is the first vector reg to be saved, or if
1347 it has a lower number than others previously seen,
1348 reupdate the frame info. */
1349 /* We know the contents of rB from the previous instruction. */
1350 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1352 fdata
->saved_ev
= ev_reg
;
1353 fdata
->ev_offset
= vr_saved_offset
+ offset
;
1355 vr_saved_offset
= -1;
1361 /* Store gen register r31 at (rA+uimm). */
1362 /* 000100 11111 aaaaa iiiii 01100100001 */
1363 else if (arch_info
->mach
== bfd_mach_ppc_e500
1364 && (op
& 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
1366 /* Wwe know that the source register is 31 already, but
1367 it can't hurt to compute it. */
1368 ev_reg
= GET_SRC_REG (op
);
1369 ev_offset
= ((op
>> 11) & 0x1f) * 8;
1370 /* If this is the first vector reg to be saved, or if
1371 it has a lower number than others previously seen,
1372 reupdate the frame info. */
1373 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1375 fdata
->saved_ev
= ev_reg
;
1376 fdata
->ev_offset
= ev_offset
+ offset
;
1381 /* Store gen register S at (r31+r0).
1382 Store param on stack when offset from SP bigger than 4 bytes. */
1383 /* 000100 sssss 11111 00000 01100100000 */
1384 else if (arch_info
->mach
== bfd_mach_ppc_e500
1385 && (op
& 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
1387 if (pc
== (li_found_pc
+ 4))
1389 if ((op
& 0x03e00000) >= 0x01a00000)
1391 ev_reg
= GET_SRC_REG (op
);
1392 /* If this is the first vector reg to be saved, or if
1393 it has a lower number than others previously seen,
1394 reupdate the frame info. */
1395 /* We know the contents of r0 from the previous
1397 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1399 fdata
->saved_ev
= ev_reg
;
1400 fdata
->ev_offset
= vr_saved_offset
+ offset
;
1404 vr_saved_offset
= -1;
1409 /* End BookE related instructions. */
1413 /* Not a recognized prologue instruction.
1414 Handle optimizer code motions into the prologue by continuing
1415 the search if we have no valid frame yet or if the return
1416 address is not yet saved in the frame. */
1417 if (fdata
->frameless
== 0
1418 && (lr_reg
== -1 || fdata
->nosavedpc
== 0))
1421 if (op
== 0x4e800020 /* blr */
1422 || op
== 0x4e800420) /* bctr */
1423 /* Do not scan past epilogue in frameless functions or
1426 if ((op
& 0xf4000000) == 0x40000000) /* bxx */
1427 /* Never skip branches. */
1430 if (num_skip_non_prologue_insns
++ > max_skip_non_prologue_insns
)
1431 /* Do not scan too many insns, scanning insns is expensive with
1435 /* Continue scanning. */
1436 prev_insn_was_prologue_insn
= 0;
1442 /* I have problems with skipping over __main() that I need to address
1443 * sometime. Previously, I used to use misc_function_vector which
1444 * didn't work as well as I wanted to be. -MGO */
1446 /* If the first thing after skipping a prolog is a branch to a function,
1447 this might be a call to an initializer in main(), introduced by gcc2.
1448 We'd like to skip over it as well. Fortunately, xlc does some extra
1449 work before calling a function right after a prologue, thus we can
1450 single out such gcc2 behaviour. */
1453 if ((op
& 0xfc000001) == 0x48000001)
1454 { /* bl foo, an initializer function? */
1455 op
= read_memory_integer (pc
+ 4, 4);
1457 if (op
== 0x4def7b82)
1458 { /* cror 0xf, 0xf, 0xf (nop) */
1460 /* Check and see if we are in main. If so, skip over this
1461 initializer function as well. */
1463 tmp
= find_pc_misc_function (pc
);
1465 && strcmp (misc_function_vector
[tmp
].name
, main_name ()) == 0)
1471 fdata
->offset
= -fdata
->offset
;
1472 return last_prologue_pc
;
1476 /*************************************************************************
1477 Support for creating pushing a dummy frame into the stack, and popping
1479 *************************************************************************/
1482 /* All the ABI's require 16 byte alignment. */
1484 rs6000_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1486 return (addr
& -16);
1489 /* Pass the arguments in either registers, or in the stack. In RS/6000,
1490 the first eight words of the argument list (that might be less than
1491 eight parameters if some parameters occupy more than one word) are
1492 passed in r3..r10 registers. float and double parameters are
1493 passed in fpr's, in addition to that. Rest of the parameters if any
1494 are passed in user stack. There might be cases in which half of the
1495 parameter is copied into registers, the other half is pushed into
1498 Stack must be aligned on 64-bit boundaries when synthesizing
1501 If the function is returning a structure, then the return address is passed
1502 in r3, then the first 7 words of the parameters can be passed in registers,
1503 starting from r4. */
1506 rs6000_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1507 struct regcache
*regcache
, CORE_ADDR bp_addr
,
1508 int nargs
, struct value
**args
, CORE_ADDR sp
,
1509 int struct_return
, CORE_ADDR struct_addr
)
1511 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1514 int argno
; /* current argument number */
1515 int argbytes
; /* current argument byte */
1516 gdb_byte tmp_buffer
[50];
1517 int f_argno
= 0; /* current floating point argno */
1518 int wordsize
= gdbarch_tdep (current_gdbarch
)->wordsize
;
1519 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
1521 struct value
*arg
= 0;
1526 /* The calling convention this function implements assumes the
1527 processor has floating-point registers. We shouldn't be using it
1528 on PPC variants that lack them. */
1529 gdb_assert (ppc_floating_point_unit_p (current_gdbarch
));
1531 /* The first eight words of ther arguments are passed in registers.
1532 Copy them appropriately. */
1535 /* If the function is returning a `struct', then the first word
1536 (which will be passed in r3) is used for struct return address.
1537 In that case we should advance one word and start from r4
1538 register to copy parameters. */
1541 regcache_raw_write_unsigned (regcache
, tdep
->ppc_gp0_regnum
+ 3,
1547 effectively indirect call... gcc does...
1549 return_val example( float, int);
1552 float in fp0, int in r3
1553 offset of stack on overflow 8/16
1554 for varargs, must go by type.
1556 float in r3&r4, int in r5
1557 offset of stack on overflow different
1559 return in r3 or f0. If no float, must study how gcc emulates floats;
1560 pay attention to arg promotion.
1561 User may have to cast\args to handle promotion correctly
1562 since gdb won't know if prototype supplied or not.
1565 for (argno
= 0, argbytes
= 0; argno
< nargs
&& ii
< 8; ++ii
)
1567 int reg_size
= register_size (current_gdbarch
, ii
+ 3);
1570 type
= check_typedef (value_type (arg
));
1571 len
= TYPE_LENGTH (type
);
1573 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1576 /* Floating point arguments are passed in fpr's, as well as gpr's.
1577 There are 13 fpr's reserved for passing parameters. At this point
1578 there is no way we would run out of them. */
1580 gdb_assert (len
<= 8);
1582 regcache_cooked_write (regcache
,
1583 tdep
->ppc_fp0_regnum
+ 1 + f_argno
,
1584 value_contents (arg
));
1591 /* Argument takes more than one register. */
1592 while (argbytes
< len
)
1594 gdb_byte word
[MAX_REGISTER_SIZE
];
1595 memset (word
, 0, reg_size
);
1597 ((char *) value_contents (arg
)) + argbytes
,
1598 (len
- argbytes
) > reg_size
1599 ? reg_size
: len
- argbytes
);
1600 regcache_cooked_write (regcache
,
1601 tdep
->ppc_gp0_regnum
+ 3 + ii
,
1603 ++ii
, argbytes
+= reg_size
;
1606 goto ran_out_of_registers_for_arguments
;
1613 /* Argument can fit in one register. No problem. */
1614 int adj
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? reg_size
- len
: 0;
1615 gdb_byte word
[MAX_REGISTER_SIZE
];
1617 memset (word
, 0, reg_size
);
1618 memcpy (word
, value_contents (arg
), len
);
1619 regcache_cooked_write (regcache
, tdep
->ppc_gp0_regnum
+ 3 +ii
, word
);
1624 ran_out_of_registers_for_arguments
:
1626 saved_sp
= read_sp ();
1628 /* Location for 8 parameters are always reserved. */
1631 /* Another six words for back chain, TOC register, link register, etc. */
1634 /* Stack pointer must be quadword aligned. */
1637 /* If there are more arguments, allocate space for them in
1638 the stack, then push them starting from the ninth one. */
1640 if ((argno
< nargs
) || argbytes
)
1646 space
+= ((len
- argbytes
+ 3) & -4);
1652 for (; jj
< nargs
; ++jj
)
1654 struct value
*val
= args
[jj
];
1655 space
+= ((TYPE_LENGTH (value_type (val
))) + 3) & -4;
1658 /* Add location required for the rest of the parameters. */
1659 space
= (space
+ 15) & -16;
1662 /* This is another instance we need to be concerned about
1663 securing our stack space. If we write anything underneath %sp
1664 (r1), we might conflict with the kernel who thinks he is free
1665 to use this area. So, update %sp first before doing anything
1668 regcache_raw_write_signed (regcache
, SP_REGNUM
, sp
);
1670 /* If the last argument copied into the registers didn't fit there
1671 completely, push the rest of it into stack. */
1675 write_memory (sp
+ 24 + (ii
* 4),
1676 value_contents (arg
) + argbytes
,
1679 ii
+= ((len
- argbytes
+ 3) & -4) / 4;
1682 /* Push the rest of the arguments into stack. */
1683 for (; argno
< nargs
; ++argno
)
1687 type
= check_typedef (value_type (arg
));
1688 len
= TYPE_LENGTH (type
);
1691 /* Float types should be passed in fpr's, as well as in the
1693 if (TYPE_CODE (type
) == TYPE_CODE_FLT
&& f_argno
< 13)
1696 gdb_assert (len
<= 8);
1698 regcache_cooked_write (regcache
,
1699 tdep
->ppc_fp0_regnum
+ 1 + f_argno
,
1700 value_contents (arg
));
1704 write_memory (sp
+ 24 + (ii
* 4), value_contents (arg
), len
);
1705 ii
+= ((len
+ 3) & -4) / 4;
1709 /* Set the stack pointer. According to the ABI, the SP is meant to
1710 be set _before_ the corresponding stack space is used. On AIX,
1711 this even applies when the target has been completely stopped!
1712 Not doing this can lead to conflicts with the kernel which thinks
1713 that it still has control over this not-yet-allocated stack
1715 regcache_raw_write_signed (regcache
, SP_REGNUM
, sp
);
1717 /* Set back chain properly. */
1718 store_unsigned_integer (tmp_buffer
, wordsize
, saved_sp
);
1719 write_memory (sp
, tmp_buffer
, wordsize
);
1721 /* Point the inferior function call's return address at the dummy's
1723 regcache_raw_write_signed (regcache
, tdep
->ppc_lr_regnum
, bp_addr
);
1725 /* Set the TOC register, get the value from the objfile reader
1726 which, in turn, gets it from the VMAP table. */
1727 if (rs6000_find_toc_address_hook
!= NULL
)
1729 CORE_ADDR tocvalue
= (*rs6000_find_toc_address_hook
) (func_addr
);
1730 regcache_raw_write_signed (regcache
, tdep
->ppc_toc_regnum
, tocvalue
);
1733 target_store_registers (-1);
1737 static enum return_value_convention
1738 rs6000_return_value (struct gdbarch
*gdbarch
, struct type
*valtype
,
1739 struct regcache
*regcache
, gdb_byte
*readbuf
,
1740 const gdb_byte
*writebuf
)
1742 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1745 /* The calling convention this function implements assumes the
1746 processor has floating-point registers. We shouldn't be using it
1747 on PowerPC variants that lack them. */
1748 gdb_assert (ppc_floating_point_unit_p (current_gdbarch
));
1750 /* AltiVec extension: Functions that declare a vector data type as a
1751 return value place that return value in VR2. */
1752 if (TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (valtype
)
1753 && TYPE_LENGTH (valtype
) == 16)
1756 regcache_cooked_read (regcache
, tdep
->ppc_vr0_regnum
+ 2, readbuf
);
1758 regcache_cooked_write (regcache
, tdep
->ppc_vr0_regnum
+ 2, writebuf
);
1760 return RETURN_VALUE_REGISTER_CONVENTION
;
1763 /* If the called subprogram returns an aggregate, there exists an
1764 implicit first argument, whose value is the address of a caller-
1765 allocated buffer into which the callee is assumed to store its
1766 return value. All explicit parameters are appropriately
1768 if (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
1769 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
1770 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
1771 return RETURN_VALUE_STRUCT_CONVENTION
;
1773 /* Scalar floating-point values are returned in FPR1 for float or
1774 double, and in FPR1:FPR2 for quadword precision. Fortran
1775 complex*8 and complex*16 are returned in FPR1:FPR2, and
1776 complex*32 is returned in FPR1:FPR4. */
1777 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
1778 && (TYPE_LENGTH (valtype
) == 4 || TYPE_LENGTH (valtype
) == 8))
1780 struct type
*regtype
= register_type (gdbarch
, tdep
->ppc_fp0_regnum
);
1783 /* FIXME: kettenis/2007-01-01: Add support for quadword
1784 precision and complex. */
1788 regcache_cooked_read (regcache
, tdep
->ppc_fp0_regnum
+ 1, regval
);
1789 convert_typed_floating (regval
, regtype
, readbuf
, valtype
);
1793 convert_typed_floating (writebuf
, valtype
, regval
, regtype
);
1794 regcache_cooked_write (regcache
, tdep
->ppc_fp0_regnum
+ 1, regval
);
1797 return RETURN_VALUE_REGISTER_CONVENTION
;
1800 /* Values of the types int, long, short, pointer, and char (length
1801 is less than or equal to four bytes), as well as bit values of
1802 lengths less than or equal to 32 bits, must be returned right
1803 justified in GPR3 with signed values sign extended and unsigned
1804 values zero extended, as necessary. */
1805 if (TYPE_LENGTH (valtype
) <= tdep
->wordsize
)
1811 /* For reading we don't have to worry about sign extension. */
1812 regcache_cooked_read_unsigned (regcache
, tdep
->ppc_gp0_regnum
+ 3,
1814 store_unsigned_integer (readbuf
, TYPE_LENGTH (valtype
), regval
);
1818 /* For writing, use unpack_long since that should handle any
1819 required sign extension. */
1820 regcache_cooked_write_unsigned (regcache
, tdep
->ppc_gp0_regnum
+ 3,
1821 unpack_long (valtype
, writebuf
));
1824 return RETURN_VALUE_REGISTER_CONVENTION
;
1827 /* Eight-byte non-floating-point scalar values must be returned in
1830 if (TYPE_LENGTH (valtype
) == 8)
1832 gdb_assert (TYPE_CODE (valtype
) != TYPE_CODE_FLT
);
1833 gdb_assert (tdep
->wordsize
== 4);
1839 regcache_cooked_read (regcache
, tdep
->ppc_gp0_regnum
+ 3, regval
);
1840 regcache_cooked_read (regcache
, tdep
->ppc_gp0_regnum
+ 4,
1842 memcpy (readbuf
, regval
, 8);
1846 regcache_cooked_write (regcache
, tdep
->ppc_gp0_regnum
+ 3, writebuf
);
1847 regcache_cooked_write (regcache
, tdep
->ppc_gp0_regnum
+ 4,
1851 return RETURN_VALUE_REGISTER_CONVENTION
;
1854 return RETURN_VALUE_STRUCT_CONVENTION
;
1857 /* Return whether handle_inferior_event() should proceed through code
1858 starting at PC in function NAME when stepping.
1860 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
1861 handle memory references that are too distant to fit in instructions
1862 generated by the compiler. For example, if 'foo' in the following
1867 is greater than 32767, the linker might replace the lwz with a branch to
1868 somewhere in @FIX1 that does the load in 2 instructions and then branches
1869 back to where execution should continue.
1871 GDB should silently step over @FIX code, just like AIX dbx does.
1872 Unfortunately, the linker uses the "b" instruction for the
1873 branches, meaning that the link register doesn't get set.
1874 Therefore, GDB's usual step_over_function () mechanism won't work.
1876 Instead, use the IN_SOLIB_RETURN_TRAMPOLINE and
1877 SKIP_TRAMPOLINE_CODE hooks in handle_inferior_event() to skip past
1881 rs6000_in_solib_return_trampoline (CORE_ADDR pc
, char *name
)
1883 return name
&& !strncmp (name
, "@FIX", 4);
1886 /* Skip code that the user doesn't want to see when stepping:
1888 1. Indirect function calls use a piece of trampoline code to do context
1889 switching, i.e. to set the new TOC table. Skip such code if we are on
1890 its first instruction (as when we have single-stepped to here).
1892 2. Skip shared library trampoline code (which is different from
1893 indirect function call trampolines).
1895 3. Skip bigtoc fixup code.
1897 Result is desired PC to step until, or NULL if we are not in
1898 code that should be skipped. */
1901 rs6000_skip_trampoline_code (CORE_ADDR pc
)
1903 unsigned int ii
, op
;
1905 CORE_ADDR solib_target_pc
;
1906 struct minimal_symbol
*msymbol
;
1908 static unsigned trampoline_code
[] =
1910 0x800b0000, /* l r0,0x0(r11) */
1911 0x90410014, /* st r2,0x14(r1) */
1912 0x7c0903a6, /* mtctr r0 */
1913 0x804b0004, /* l r2,0x4(r11) */
1914 0x816b0008, /* l r11,0x8(r11) */
1915 0x4e800420, /* bctr */
1916 0x4e800020, /* br */
1920 /* Check for bigtoc fixup code. */
1921 msymbol
= lookup_minimal_symbol_by_pc (pc
);
1923 && rs6000_in_solib_return_trampoline (pc
,
1924 DEPRECATED_SYMBOL_NAME (msymbol
)))
1926 /* Double-check that the third instruction from PC is relative "b". */
1927 op
= read_memory_integer (pc
+ 8, 4);
1928 if ((op
& 0xfc000003) == 0x48000000)
1930 /* Extract bits 6-29 as a signed 24-bit relative word address and
1931 add it to the containing PC. */
1932 rel
= ((int)(op
<< 6) >> 6);
1933 return pc
+ 8 + rel
;
1937 /* If pc is in a shared library trampoline, return its target. */
1938 solib_target_pc
= find_solib_trampoline_target (pc
);
1939 if (solib_target_pc
)
1940 return solib_target_pc
;
1942 for (ii
= 0; trampoline_code
[ii
]; ++ii
)
1944 op
= read_memory_integer (pc
+ (ii
* 4), 4);
1945 if (op
!= trampoline_code
[ii
])
1948 ii
= read_register (11); /* r11 holds destination addr */
1949 pc
= read_memory_addr (ii
, gdbarch_tdep (current_gdbarch
)->wordsize
); /* (r11) value */
1953 /* Return the size of register REG when words are WORDSIZE bytes long. If REG
1954 isn't available with that word size, return 0. */
1957 regsize (const struct reg
*reg
, int wordsize
)
1959 return wordsize
== 8 ? reg
->sz64
: reg
->sz32
;
1962 /* Return the name of register number N, or null if no such register exists
1963 in the current architecture. */
1966 rs6000_register_name (int n
)
1968 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1969 const struct reg
*reg
= tdep
->regs
+ n
;
1971 if (!regsize (reg
, tdep
->wordsize
))
1976 /* Return the GDB type object for the "standard" data type
1977 of data in register N. */
1979 static struct type
*
1980 rs6000_register_type (struct gdbarch
*gdbarch
, int n
)
1982 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1983 const struct reg
*reg
= tdep
->regs
+ n
;
1986 return builtin_type_double
;
1989 int size
= regsize (reg
, tdep
->wordsize
);
1993 return builtin_type_int0
;
1995 return builtin_type_uint32
;
1997 if (tdep
->ppc_ev0_regnum
<= n
&& n
<= tdep
->ppc_ev31_regnum
)
1998 return builtin_type_vec64
;
2000 return builtin_type_uint64
;
2003 return builtin_type_vec128
;
2006 internal_error (__FILE__
, __LINE__
, _("Register %d size %d unknown"),
2012 /* Is REGNUM a member of REGGROUP? */
2014 rs6000_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2015 struct reggroup
*group
)
2017 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2022 if (REGISTER_NAME (regnum
) == NULL
2023 || *REGISTER_NAME (regnum
) == '\0')
2025 if (group
== all_reggroup
)
2028 float_p
= (regnum
== tdep
->ppc_fpscr_regnum
2029 || (regnum
>= tdep
->ppc_fp0_regnum
2030 && regnum
< tdep
->ppc_fp0_regnum
+ 32));
2031 if (group
== float_reggroup
)
2034 vector_p
= ((tdep
->ppc_vr0_regnum
>= 0
2035 && regnum
>= tdep
->ppc_vr0_regnum
2036 && regnum
< tdep
->ppc_vr0_regnum
+ 32)
2037 || (tdep
->ppc_ev0_regnum
>= 0
2038 && regnum
>= tdep
->ppc_ev0_regnum
2039 && regnum
< tdep
->ppc_ev0_regnum
+ 32)
2040 || regnum
== tdep
->ppc_vrsave_regnum
- 1 /* vscr */
2041 || regnum
== tdep
->ppc_vrsave_regnum
2042 || regnum
== tdep
->ppc_acc_regnum
2043 || regnum
== tdep
->ppc_spefscr_regnum
);
2044 if (group
== vector_reggroup
)
2047 /* Note that PS aka MSR isn't included - it's a system register (and
2048 besides, due to GCC's CFI foobar you do not want to restore
2050 general_p
= ((regnum
>= tdep
->ppc_gp0_regnum
2051 && regnum
< tdep
->ppc_gp0_regnum
+ 32)
2052 || regnum
== tdep
->ppc_toc_regnum
2053 || regnum
== tdep
->ppc_cr_regnum
2054 || regnum
== tdep
->ppc_lr_regnum
2055 || regnum
== tdep
->ppc_ctr_regnum
2056 || regnum
== tdep
->ppc_xer_regnum
2057 || regnum
== PC_REGNUM
);
2058 if (group
== general_reggroup
)
2061 if (group
== save_reggroup
|| group
== restore_reggroup
)
2062 return general_p
|| vector_p
|| float_p
;
2067 /* The register format for RS/6000 floating point registers is always
2068 double, we need a conversion if the memory format is float. */
2071 rs6000_convert_register_p (int regnum
, struct type
*type
)
2073 const struct reg
*reg
= gdbarch_tdep (current_gdbarch
)->regs
+ regnum
;
2076 && TYPE_CODE (type
) == TYPE_CODE_FLT
2077 && TYPE_LENGTH (type
) != TYPE_LENGTH (builtin_type_double
));
2081 rs6000_register_to_value (struct frame_info
*frame
,
2086 const struct reg
*reg
= gdbarch_tdep (current_gdbarch
)->regs
+ regnum
;
2087 gdb_byte from
[MAX_REGISTER_SIZE
];
2089 gdb_assert (reg
->fpr
);
2090 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
2092 get_frame_register (frame
, regnum
, from
);
2093 convert_typed_floating (from
, builtin_type_double
, to
, type
);
2097 rs6000_value_to_register (struct frame_info
*frame
,
2100 const gdb_byte
*from
)
2102 const struct reg
*reg
= gdbarch_tdep (current_gdbarch
)->regs
+ regnum
;
2103 gdb_byte to
[MAX_REGISTER_SIZE
];
2105 gdb_assert (reg
->fpr
);
2106 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
2108 convert_typed_floating (from
, type
, to
, builtin_type_double
);
2109 put_frame_register (frame
, regnum
, to
);
2112 /* Move SPE vector register values between a 64-bit buffer and the two
2113 32-bit raw register halves in a regcache. This function handles
2114 both splitting a 64-bit value into two 32-bit halves, and joining
2115 two halves into a whole 64-bit value, depending on the function
2116 passed as the MOVE argument.
2118 EV_REG must be the number of an SPE evN vector register --- a
2119 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2122 Call MOVE once for each 32-bit half of that register, passing
2123 REGCACHE, the number of the raw register corresponding to that
2124 half, and the address of the appropriate half of BUFFER.
2126 For example, passing 'regcache_raw_read' as the MOVE function will
2127 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2128 'regcache_raw_supply' will supply the contents of BUFFER to the
2129 appropriate pair of raw registers in REGCACHE.
2131 You may need to cast away some 'const' qualifiers when passing
2132 MOVE, since this function can't tell at compile-time which of
2133 REGCACHE or BUFFER is acting as the source of the data. If C had
2134 co-variant type qualifiers, ... */
2136 e500_move_ev_register (void (*move
) (struct regcache
*regcache
,
2137 int regnum
, gdb_byte
*buf
),
2138 struct regcache
*regcache
, int ev_reg
,
2141 struct gdbarch
*arch
= get_regcache_arch (regcache
);
2142 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
2144 gdb_byte
*byte_buffer
= buffer
;
2146 gdb_assert (tdep
->ppc_ev0_regnum
<= ev_reg
2147 && ev_reg
< tdep
->ppc_ev0_regnum
+ ppc_num_gprs
);
2149 reg_index
= ev_reg
- tdep
->ppc_ev0_regnum
;
2151 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2153 move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
, byte_buffer
);
2154 move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
, byte_buffer
+ 4);
2158 move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
, byte_buffer
);
2159 move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
, byte_buffer
+ 4);
2164 e500_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2165 int reg_nr
, gdb_byte
*buffer
)
2167 struct gdbarch
*regcache_arch
= get_regcache_arch (regcache
);
2168 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2170 gdb_assert (regcache_arch
== gdbarch
);
2172 if (tdep
->ppc_ev0_regnum
<= reg_nr
2173 && reg_nr
< tdep
->ppc_ev0_regnum
+ ppc_num_gprs
)
2174 e500_move_ev_register (regcache_raw_read
, regcache
, reg_nr
, buffer
);
2176 internal_error (__FILE__
, __LINE__
,
2177 _("e500_pseudo_register_read: "
2178 "called on unexpected register '%s' (%d)"),
2179 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2183 e500_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2184 int reg_nr
, const gdb_byte
*buffer
)
2186 struct gdbarch
*regcache_arch
= get_regcache_arch (regcache
);
2187 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2189 gdb_assert (regcache_arch
== gdbarch
);
2191 if (tdep
->ppc_ev0_regnum
<= reg_nr
2192 && reg_nr
< tdep
->ppc_ev0_regnum
+ ppc_num_gprs
)
2193 e500_move_ev_register ((void (*) (struct regcache
*, int, gdb_byte
*))
2195 regcache
, reg_nr
, (gdb_byte
*) buffer
);
2197 internal_error (__FILE__
, __LINE__
,
2198 _("e500_pseudo_register_read: "
2199 "called on unexpected register '%s' (%d)"),
2200 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2203 /* The E500 needs a custom reggroup function: it has anonymous raw
2204 registers, and default_register_reggroup_p assumes that anonymous
2205 registers are not members of any reggroup. */
2207 e500_register_reggroup_p (struct gdbarch
*gdbarch
,
2209 struct reggroup
*group
)
2211 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2213 /* The save and restore register groups need to include the
2214 upper-half registers, even though they're anonymous. */
2215 if ((group
== save_reggroup
2216 || group
== restore_reggroup
)
2217 && (tdep
->ppc_ev0_upper_regnum
<= regnum
2218 && regnum
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
))
2221 /* In all other regards, the default reggroup definition is fine. */
2222 return default_register_reggroup_p (gdbarch
, regnum
, group
);
2225 /* Convert a DBX STABS register number to a GDB register number. */
2227 rs6000_stab_reg_to_regnum (int num
)
2229 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2231 if (0 <= num
&& num
<= 31)
2232 return tdep
->ppc_gp0_regnum
+ num
;
2233 else if (32 <= num
&& num
<= 63)
2234 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2235 specifies registers the architecture doesn't have? Our
2236 callers don't check the value we return. */
2237 return tdep
->ppc_fp0_regnum
+ (num
- 32);
2238 else if (77 <= num
&& num
<= 108)
2239 return tdep
->ppc_vr0_regnum
+ (num
- 77);
2240 else if (1200 <= num
&& num
< 1200 + 32)
2241 return tdep
->ppc_ev0_regnum
+ (num
- 1200);
2246 return tdep
->ppc_mq_regnum
;
2248 return tdep
->ppc_lr_regnum
;
2250 return tdep
->ppc_ctr_regnum
;
2252 return tdep
->ppc_xer_regnum
;
2254 return tdep
->ppc_vrsave_regnum
;
2256 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
2258 return tdep
->ppc_acc_regnum
;
2260 return tdep
->ppc_spefscr_regnum
;
2267 /* Convert a Dwarf 2 register number to a GDB register number. */
2269 rs6000_dwarf2_reg_to_regnum (int num
)
2271 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2273 if (0 <= num
&& num
<= 31)
2274 return tdep
->ppc_gp0_regnum
+ num
;
2275 else if (32 <= num
&& num
<= 63)
2276 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2277 specifies registers the architecture doesn't have? Our
2278 callers don't check the value we return. */
2279 return tdep
->ppc_fp0_regnum
+ (num
- 32);
2280 else if (1124 <= num
&& num
< 1124 + 32)
2281 return tdep
->ppc_vr0_regnum
+ (num
- 1124);
2282 else if (1200 <= num
&& num
< 1200 + 32)
2283 return tdep
->ppc_ev0_regnum
+ (num
- 1200);
2288 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
2290 return tdep
->ppc_acc_regnum
;
2292 return tdep
->ppc_mq_regnum
;
2294 return tdep
->ppc_xer_regnum
;
2296 return tdep
->ppc_lr_regnum
;
2298 return tdep
->ppc_ctr_regnum
;
2300 return tdep
->ppc_vrsave_regnum
;
2302 return tdep
->ppc_spefscr_regnum
;
2308 /* Hook called when a new child process is started. */
2311 rs6000_create_inferior (int pid
)
2313 if (rs6000_set_host_arch_hook
)
2314 rs6000_set_host_arch_hook (pid
);
2317 /* Support for CONVERT_FROM_FUNC_PTR_ADDR (ARCH, ADDR, TARG).
2319 Usually a function pointer's representation is simply the address
2320 of the function. On the RS/6000 however, a function pointer is
2321 represented by a pointer to an OPD entry. This OPD entry contains
2322 three words, the first word is the address of the function, the
2323 second word is the TOC pointer (r2), and the third word is the
2324 static chain value. Throughout GDB it is currently assumed that a
2325 function pointer contains the address of the function, which is not
2326 easy to fix. In addition, the conversion of a function address to
2327 a function pointer would require allocation of an OPD entry in the
2328 inferior's memory space, with all its drawbacks. To be able to
2329 call C++ virtual methods in the inferior (which are called via
2330 function pointers), find_function_addr uses this function to get the
2331 function address from a function pointer. */
2333 /* Return real function address if ADDR (a function pointer) is in the data
2334 space and is therefore a special function pointer. */
2337 rs6000_convert_from_func_ptr_addr (struct gdbarch
*gdbarch
,
2339 struct target_ops
*targ
)
2341 struct obj_section
*s
;
2343 s
= find_pc_section (addr
);
2344 if (s
&& s
->the_bfd_section
->flags
& SEC_CODE
)
2347 /* ADDR is in the data space, so it's a special function pointer. */
2348 return read_memory_addr (addr
, gdbarch_tdep (current_gdbarch
)->wordsize
);
2352 /* Handling the various POWER/PowerPC variants. */
2355 /* The arrays here called registers_MUMBLE hold information about available
2358 For each family of PPC variants, I've tried to isolate out the
2359 common registers and put them up front, so that as long as you get
2360 the general family right, GDB will correctly identify the registers
2361 common to that family. The common register sets are:
2363 For the 60x family: hid0 hid1 iabr dabr pir
2365 For the 505 and 860 family: eie eid nri
2367 For the 403 and 403GC: icdbdr esr dear evpr cdbcr tsr tcr pit tbhi
2368 tblo srr2 srr3 dbsr dbcr iac1 iac2 dac1 dac2 dccr iccr pbl1
2371 Most of these register groups aren't anything formal. I arrived at
2372 them by looking at the registers that occurred in more than one
2375 Note: kevinb/2002-04-30: Support for the fpscr register was added
2376 during April, 2002. Slot 70 is being used for PowerPC and slot 71
2377 for Power. For PowerPC, slot 70 was unused and was already in the
2378 PPC_UISA_SPRS which is ideally where fpscr should go. For Power,
2379 slot 70 was being used for "mq", so the next available slot (71)
2380 was chosen. It would have been nice to be able to make the
2381 register numbers the same across processor cores, but this wasn't
2382 possible without either 1) renumbering some registers for some
2383 processors or 2) assigning fpscr to a really high slot that's
2384 larger than any current register number. Doing (1) is bad because
2385 existing stubs would break. Doing (2) is undesirable because it
2386 would introduce a really large gap between fpscr and the rest of
2387 the registers for most processors. */
2389 /* Convenience macros for populating register arrays. */
2391 /* Within another macro, convert S to a string. */
2395 /* Return a struct reg defining register NAME that's 32 bits on 32-bit systems
2396 and 64 bits on 64-bit systems. */
2397 #define R(name) { STR(name), 4, 8, 0, 0, -1 }
2399 /* Return a struct reg defining register NAME that's 32 bits on all
2401 #define R4(name) { STR(name), 4, 4, 0, 0, -1 }
2403 /* Return a struct reg defining register NAME that's 64 bits on all
2405 #define R8(name) { STR(name), 8, 8, 0, 0, -1 }
2407 /* Return a struct reg defining register NAME that's 128 bits on all
2409 #define R16(name) { STR(name), 16, 16, 0, 0, -1 }
2411 /* Return a struct reg defining floating-point register NAME. */
2412 #define F(name) { STR(name), 8, 8, 1, 0, -1 }
2414 /* Return a struct reg defining a pseudo register NAME that is 64 bits
2415 long on all systems. */
2416 #define P8(name) { STR(name), 8, 8, 0, 1, -1 }
2418 /* Return a struct reg defining register NAME that's 32 bits on 32-bit
2419 systems and that doesn't exist on 64-bit systems. */
2420 #define R32(name) { STR(name), 4, 0, 0, 0, -1 }
2422 /* Return a struct reg defining register NAME that's 64 bits on 64-bit
2423 systems and that doesn't exist on 32-bit systems. */
2424 #define R64(name) { STR(name), 0, 8, 0, 0, -1 }
2426 /* Return a struct reg placeholder for a register that doesn't exist. */
2427 #define R0 { 0, 0, 0, 0, 0, -1 }
2429 /* Return a struct reg defining an anonymous raw register that's 32
2430 bits on all systems. */
2431 #define A4 { 0, 4, 4, 0, 0, -1 }
2433 /* Return a struct reg defining an SPR named NAME that is 32 bits on
2434 32-bit systems and 64 bits on 64-bit systems. */
2435 #define S(name) { STR(name), 4, 8, 0, 0, ppc_spr_ ## name }
2437 /* Return a struct reg defining an SPR named NAME that is 32 bits on
2439 #define S4(name) { STR(name), 4, 4, 0, 0, ppc_spr_ ## name }
2441 /* Return a struct reg defining an SPR named NAME that is 32 bits on
2442 all systems, and whose SPR number is NUMBER. */
2443 #define SN4(name, number) { STR(name), 4, 4, 0, 0, (number) }
2445 /* Return a struct reg defining an SPR named NAME that's 64 bits on
2446 64-bit systems and that doesn't exist on 32-bit systems. */
2447 #define S64(name) { STR(name), 0, 8, 0, 0, ppc_spr_ ## name }
2449 /* UISA registers common across all architectures, including POWER. */
2451 #define COMMON_UISA_REGS \
2452 /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \
2453 /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \
2454 /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \
2455 /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \
2456 /* 32 */ F(f0), F(f1), F(f2), F(f3), F(f4), F(f5), F(f6), F(f7), \
2457 /* 40 */ F(f8), F(f9), F(f10),F(f11),F(f12),F(f13),F(f14),F(f15), \
2458 /* 48 */ F(f16),F(f17),F(f18),F(f19),F(f20),F(f21),F(f22),F(f23), \
2459 /* 56 */ F(f24),F(f25),F(f26),F(f27),F(f28),F(f29),F(f30),F(f31), \
2460 /* 64 */ R(pc), R(ps)
2462 /* UISA-level SPRs for PowerPC. */
2463 #define PPC_UISA_SPRS \
2464 /* 66 */ R4(cr), S(lr), S(ctr), S4(xer), R4(fpscr)
2466 /* UISA-level SPRs for PowerPC without floating point support. */
2467 #define PPC_UISA_NOFP_SPRS \
2468 /* 66 */ R4(cr), S(lr), S(ctr), S4(xer), R0
2470 /* Segment registers, for PowerPC. */
2471 #define PPC_SEGMENT_REGS \
2472 /* 71 */ R32(sr0), R32(sr1), R32(sr2), R32(sr3), \
2473 /* 75 */ R32(sr4), R32(sr5), R32(sr6), R32(sr7), \
2474 /* 79 */ R32(sr8), R32(sr9), R32(sr10), R32(sr11), \
2475 /* 83 */ R32(sr12), R32(sr13), R32(sr14), R32(sr15)
2477 /* OEA SPRs for PowerPC. */
2478 #define PPC_OEA_SPRS \
2480 /* 88 */ S(ibat0u), S(ibat0l), S(ibat1u), S(ibat1l), \
2481 /* 92 */ S(ibat2u), S(ibat2l), S(ibat3u), S(ibat3l), \
2482 /* 96 */ S(dbat0u), S(dbat0l), S(dbat1u), S(dbat1l), \
2483 /* 100 */ S(dbat2u), S(dbat2l), S(dbat3u), S(dbat3l), \
2484 /* 104 */ S(sdr1), S64(asr), S(dar), S4(dsisr), \
2485 /* 108 */ S(sprg0), S(sprg1), S(sprg2), S(sprg3), \
2486 /* 112 */ S(srr0), S(srr1), S(tbl), S(tbu), \
2487 /* 116 */ S4(dec), S(dabr), S4(ear)
2489 /* AltiVec registers. */
2490 #define PPC_ALTIVEC_REGS \
2491 /*119*/R16(vr0), R16(vr1), R16(vr2), R16(vr3), R16(vr4), R16(vr5), R16(vr6), R16(vr7), \
2492 /*127*/R16(vr8), R16(vr9), R16(vr10),R16(vr11),R16(vr12),R16(vr13),R16(vr14),R16(vr15), \
2493 /*135*/R16(vr16),R16(vr17),R16(vr18),R16(vr19),R16(vr20),R16(vr21),R16(vr22),R16(vr23), \
2494 /*143*/R16(vr24),R16(vr25),R16(vr26),R16(vr27),R16(vr28),R16(vr29),R16(vr30),R16(vr31), \
2495 /*151*/R4(vscr), R4(vrsave)
2498 /* On machines supporting the SPE APU, the general-purpose registers
2499 are 64 bits long. There are SIMD vector instructions to treat them
2500 as pairs of floats, but the rest of the instruction set treats them
2501 as 32-bit registers, and only operates on their lower halves.
2503 In the GDB regcache, we treat their high and low halves as separate
2504 registers. The low halves we present as the general-purpose
2505 registers, and then we have pseudo-registers that stitch together
2506 the upper and lower halves and present them as pseudo-registers. */
2508 /* SPE GPR lower halves --- raw registers. */
2509 #define PPC_SPE_GP_REGS \
2510 /* 0 */ R4(r0), R4(r1), R4(r2), R4(r3), R4(r4), R4(r5), R4(r6), R4(r7), \
2511 /* 8 */ R4(r8), R4(r9), R4(r10),R4(r11),R4(r12),R4(r13),R4(r14),R4(r15), \
2512 /* 16 */ R4(r16),R4(r17),R4(r18),R4(r19),R4(r20),R4(r21),R4(r22),R4(r23), \
2513 /* 24 */ R4(r24),R4(r25),R4(r26),R4(r27),R4(r28),R4(r29),R4(r30),R4(r31)
2515 /* SPE GPR upper halves --- anonymous raw registers. */
2516 #define PPC_SPE_UPPER_GP_REGS \
2517 /* 0 */ A4, A4, A4, A4, A4, A4, A4, A4, \
2518 /* 8 */ A4, A4, A4, A4, A4, A4, A4, A4, \
2519 /* 16 */ A4, A4, A4, A4, A4, A4, A4, A4, \
2520 /* 24 */ A4, A4, A4, A4, A4, A4, A4, A4
2522 /* SPE GPR vector registers --- pseudo registers based on underlying
2523 gprs and the anonymous upper half raw registers. */
2524 #define PPC_EV_PSEUDO_REGS \
2525 /* 0*/P8(ev0), P8(ev1), P8(ev2), P8(ev3), P8(ev4), P8(ev5), P8(ev6), P8(ev7), \
2526 /* 8*/P8(ev8), P8(ev9), P8(ev10),P8(ev11),P8(ev12),P8(ev13),P8(ev14),P8(ev15),\
2527 /*16*/P8(ev16),P8(ev17),P8(ev18),P8(ev19),P8(ev20),P8(ev21),P8(ev22),P8(ev23),\
2528 /*24*/P8(ev24),P8(ev25),P8(ev26),P8(ev27),P8(ev28),P8(ev29),P8(ev30),P8(ev31)
2530 /* IBM POWER (pre-PowerPC) architecture, user-level view. We only cover
2531 user-level SPR's. */
2532 static const struct reg registers_power
[] =
2535 /* 66 */ R4(cnd
), S(lr
), S(cnt
), S4(xer
), S4(mq
),
2539 /* PowerPC UISA - a PPC processor as viewed by user-level code. A UISA-only
2540 view of the PowerPC. */
2541 static const struct reg registers_powerpc
[] =
2550 Some notes about the "tcr" special-purpose register:
2551 - On the 403 and 403GC, SPR 986 is named "tcr", and it controls the
2552 403's programmable interval timer, fixed interval timer, and
2554 - On the 602, SPR 984 is named "tcr", and it controls the 602's
2555 watchdog timer, and nothing else.
2557 Some of the fields are similar between the two, but they're not
2558 compatible with each other. Since the two variants have different
2559 registers, with different numbers, but the same name, we can't
2560 splice the register name to get the SPR number. */
2561 static const struct reg registers_403
[] =
2567 /* 119 */ S(icdbdr
), S(esr
), S(dear
), S(evpr
),
2568 /* 123 */ S(cdbcr
), S(tsr
), SN4(tcr
, ppc_spr_403_tcr
), S(pit
),
2569 /* 127 */ S(tbhi
), S(tblo
), S(srr2
), S(srr3
),
2570 /* 131 */ S(dbsr
), S(dbcr
), S(iac1
), S(iac2
),
2571 /* 135 */ S(dac1
), S(dac2
), S(dccr
), S(iccr
),
2572 /* 139 */ S(pbl1
), S(pbu1
), S(pbl2
), S(pbu2
)
2575 /* IBM PowerPC 403GC.
2576 See the comments about 'tcr' for the 403, above. */
2577 static const struct reg registers_403GC
[] =
2583 /* 119 */ S(icdbdr
), S(esr
), S(dear
), S(evpr
),
2584 /* 123 */ S(cdbcr
), S(tsr
), SN4(tcr
, ppc_spr_403_tcr
), S(pit
),
2585 /* 127 */ S(tbhi
), S(tblo
), S(srr2
), S(srr3
),
2586 /* 131 */ S(dbsr
), S(dbcr
), S(iac1
), S(iac2
),
2587 /* 135 */ S(dac1
), S(dac2
), S(dccr
), S(iccr
),
2588 /* 139 */ S(pbl1
), S(pbu1
), S(pbl2
), S(pbu2
),
2589 /* 143 */ S(zpr
), S(pid
), S(sgr
), S(dcwr
),
2590 /* 147 */ S(tbhu
), S(tblu
)
2593 /* Motorola PowerPC 505. */
2594 static const struct reg registers_505
[] =
2600 /* 119 */ S(eie
), S(eid
), S(nri
)
2603 /* Motorola PowerPC 860 or 850. */
2604 static const struct reg registers_860
[] =
2610 /* 119 */ S(eie
), S(eid
), S(nri
), S(cmpa
),
2611 /* 123 */ S(cmpb
), S(cmpc
), S(cmpd
), S(icr
),
2612 /* 127 */ S(der
), S(counta
), S(countb
), S(cmpe
),
2613 /* 131 */ S(cmpf
), S(cmpg
), S(cmph
), S(lctrl1
),
2614 /* 135 */ S(lctrl2
), S(ictrl
), S(bar
), S(ic_cst
),
2615 /* 139 */ S(ic_adr
), S(ic_dat
), S(dc_cst
), S(dc_adr
),
2616 /* 143 */ S(dc_dat
), S(dpdr
), S(dpir
), S(immr
),
2617 /* 147 */ S(mi_ctr
), S(mi_ap
), S(mi_epn
), S(mi_twc
),
2618 /* 151 */ S(mi_rpn
), S(md_ctr
), S(m_casid
), S(md_ap
),
2619 /* 155 */ S(md_epn
), S(m_twb
), S(md_twc
), S(md_rpn
),
2620 /* 159 */ S(m_tw
), S(mi_dbcam
), S(mi_dbram0
), S(mi_dbram1
),
2621 /* 163 */ S(md_dbcam
), S(md_dbram0
), S(md_dbram1
)
2624 /* Motorola PowerPC 601. Note that the 601 has different register numbers
2625 for reading and writing RTCU and RTCL. However, how one reads and writes a
2626 register is the stub's problem. */
2627 static const struct reg registers_601
[] =
2633 /* 119 */ S(hid0
), S(hid1
), S(iabr
), S(dabr
),
2634 /* 123 */ S(pir
), S(mq
), S(rtcu
), S(rtcl
)
2637 /* Motorola PowerPC 602.
2638 See the notes under the 403 about 'tcr'. */
2639 static const struct reg registers_602
[] =
2645 /* 119 */ S(hid0
), S(hid1
), S(iabr
), R0
,
2646 /* 123 */ R0
, SN4(tcr
, ppc_spr_602_tcr
), S(ibr
), S(esasrr
),
2647 /* 127 */ S(sebr
), S(ser
), S(sp
), S(lt
)
2650 /* Motorola/IBM PowerPC 603 or 603e. */
2651 static const struct reg registers_603
[] =
2657 /* 119 */ S(hid0
), S(hid1
), S(iabr
), R0
,
2658 /* 123 */ R0
, S(dmiss
), S(dcmp
), S(hash1
),
2659 /* 127 */ S(hash2
), S(imiss
), S(icmp
), S(rpa
)
2662 /* Motorola PowerPC 604 or 604e. */
2663 static const struct reg registers_604
[] =
2669 /* 119 */ S(hid0
), S(hid1
), S(iabr
), S(dabr
),
2670 /* 123 */ S(pir
), S(mmcr0
), S(pmc1
), S(pmc2
),
2671 /* 127 */ S(sia
), S(sda
)
2674 /* Motorola/IBM PowerPC 750 or 740. */
2675 static const struct reg registers_750
[] =
2681 /* 119 */ S(hid0
), S(hid1
), S(iabr
), S(dabr
),
2682 /* 123 */ R0
, S(ummcr0
), S(upmc1
), S(upmc2
),
2683 /* 127 */ S(usia
), S(ummcr1
), S(upmc3
), S(upmc4
),
2684 /* 131 */ S(mmcr0
), S(pmc1
), S(pmc2
), S(sia
),
2685 /* 135 */ S(mmcr1
), S(pmc3
), S(pmc4
), S(l2cr
),
2686 /* 139 */ S(ictc
), S(thrm1
), S(thrm2
), S(thrm3
)
2690 /* Motorola PowerPC 7400. */
2691 static const struct reg registers_7400
[] =
2693 /* gpr0-gpr31, fpr0-fpr31 */
2695 /* cr, lr, ctr, xer, fpscr */
2700 /* vr0-vr31, vrsave, vscr */
2702 /* FIXME? Add more registers? */
2705 /* Motorola e500. */
2706 static const struct reg registers_e500
[] =
2708 /* 0 .. 31 */ PPC_SPE_GP_REGS
,
2709 /* 32 .. 63 */ PPC_SPE_UPPER_GP_REGS
,
2710 /* 64 .. 65 */ R(pc
), R(ps
),
2711 /* 66 .. 70 */ PPC_UISA_NOFP_SPRS
,
2712 /* 71 .. 72 */ R8(acc
), S4(spefscr
),
2713 /* NOTE: Add new registers here the end of the raw register
2714 list and just before the first pseudo register. */
2715 /* 73 .. 104 */ PPC_EV_PSEUDO_REGS
2718 /* Information about a particular processor variant. */
2722 /* Name of this variant. */
2725 /* English description of the variant. */
2728 /* bfd_arch_info.arch corresponding to variant. */
2729 enum bfd_architecture arch
;
2731 /* bfd_arch_info.mach corresponding to variant. */
2734 /* Number of real registers. */
2737 /* Number of pseudo registers. */
2740 /* Number of total registers (the sum of nregs and npregs). */
2743 /* Table of register names; registers[R] is the name of the register
2745 const struct reg
*regs
;
2748 #define tot_num_registers(list) (sizeof (list) / sizeof((list)[0]))
2751 num_registers (const struct reg
*reg_list
, int num_tot_regs
)
2756 for (i
= 0; i
< num_tot_regs
; i
++)
2757 if (!reg_list
[i
].pseudo
)
2764 num_pseudo_registers (const struct reg
*reg_list
, int num_tot_regs
)
2769 for (i
= 0; i
< num_tot_regs
; i
++)
2770 if (reg_list
[i
].pseudo
)
2776 /* Information in this table comes from the following web sites:
2777 IBM: http://www.chips.ibm.com:80/products/embedded/
2778 Motorola: http://www.mot.com/SPS/PowerPC/
2780 I'm sure I've got some of the variant descriptions not quite right.
2781 Please report any inaccuracies you find to GDB's maintainer.
2783 If you add entries to this table, please be sure to allow the new
2784 value as an argument to the --with-cpu flag, in configure.in. */
2786 static struct variant variants
[] =
2789 {"powerpc", "PowerPC user-level", bfd_arch_powerpc
,
2790 bfd_mach_ppc
, -1, -1, tot_num_registers (registers_powerpc
),
2792 {"power", "POWER user-level", bfd_arch_rs6000
,
2793 bfd_mach_rs6k
, -1, -1, tot_num_registers (registers_power
),
2795 {"403", "IBM PowerPC 403", bfd_arch_powerpc
,
2796 bfd_mach_ppc_403
, -1, -1, tot_num_registers (registers_403
),
2798 {"601", "Motorola PowerPC 601", bfd_arch_powerpc
,
2799 bfd_mach_ppc_601
, -1, -1, tot_num_registers (registers_601
),
2801 {"602", "Motorola PowerPC 602", bfd_arch_powerpc
,
2802 bfd_mach_ppc_602
, -1, -1, tot_num_registers (registers_602
),
2804 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc
,
2805 bfd_mach_ppc_603
, -1, -1, tot_num_registers (registers_603
),
2807 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc
,
2808 604, -1, -1, tot_num_registers (registers_604
),
2810 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc
,
2811 bfd_mach_ppc_403gc
, -1, -1, tot_num_registers (registers_403GC
),
2813 {"505", "Motorola PowerPC 505", bfd_arch_powerpc
,
2814 bfd_mach_ppc_505
, -1, -1, tot_num_registers (registers_505
),
2816 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc
,
2817 bfd_mach_ppc_860
, -1, -1, tot_num_registers (registers_860
),
2819 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc
,
2820 bfd_mach_ppc_750
, -1, -1, tot_num_registers (registers_750
),
2822 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc
,
2823 bfd_mach_ppc_7400
, -1, -1, tot_num_registers (registers_7400
),
2825 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc
,
2826 bfd_mach_ppc_e500
, -1, -1, tot_num_registers (registers_e500
),
2830 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc
,
2831 bfd_mach_ppc64
, -1, -1, tot_num_registers (registers_powerpc
),
2833 {"620", "Motorola PowerPC 620", bfd_arch_powerpc
,
2834 bfd_mach_ppc_620
, -1, -1, tot_num_registers (registers_powerpc
),
2836 {"630", "Motorola PowerPC 630", bfd_arch_powerpc
,
2837 bfd_mach_ppc_630
, -1, -1, tot_num_registers (registers_powerpc
),
2839 {"a35", "PowerPC A35", bfd_arch_powerpc
,
2840 bfd_mach_ppc_a35
, -1, -1, tot_num_registers (registers_powerpc
),
2842 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc
,
2843 bfd_mach_ppc_rs64ii
, -1, -1, tot_num_registers (registers_powerpc
),
2845 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc
,
2846 bfd_mach_ppc_rs64iii
, -1, -1, tot_num_registers (registers_powerpc
),
2849 /* FIXME: I haven't checked the register sets of the following. */
2850 {"rs1", "IBM POWER RS1", bfd_arch_rs6000
,
2851 bfd_mach_rs6k_rs1
, -1, -1, tot_num_registers (registers_power
),
2853 {"rsc", "IBM POWER RSC", bfd_arch_rs6000
,
2854 bfd_mach_rs6k_rsc
, -1, -1, tot_num_registers (registers_power
),
2856 {"rs2", "IBM POWER RS2", bfd_arch_rs6000
,
2857 bfd_mach_rs6k_rs2
, -1, -1, tot_num_registers (registers_power
),
2860 {0, 0, 0, 0, 0, 0, 0, 0}
2863 /* Initialize the number of registers and pseudo registers in each variant. */
2866 init_variants (void)
2870 for (v
= variants
; v
->name
; v
++)
2873 v
->nregs
= num_registers (v
->regs
, v
->num_tot_regs
);
2874 if (v
->npregs
== -1)
2875 v
->npregs
= num_pseudo_registers (v
->regs
, v
->num_tot_regs
);
2879 /* Return the variant corresponding to architecture ARCH and machine number
2880 MACH. If no such variant exists, return null. */
2882 static const struct variant
*
2883 find_variant_by_arch (enum bfd_architecture arch
, unsigned long mach
)
2885 const struct variant
*v
;
2887 for (v
= variants
; v
->name
; v
++)
2888 if (arch
== v
->arch
&& mach
== v
->mach
)
2895 gdb_print_insn_powerpc (bfd_vma memaddr
, disassemble_info
*info
)
2897 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2898 return print_insn_big_powerpc (memaddr
, info
);
2900 return print_insn_little_powerpc (memaddr
, info
);
2904 rs6000_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2906 return frame_unwind_register_unsigned (next_frame
, PC_REGNUM
);
2909 static struct frame_id
2910 rs6000_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2912 return frame_id_build (frame_unwind_register_unsigned (next_frame
,
2914 frame_pc_unwind (next_frame
));
2917 struct rs6000_frame_cache
2920 CORE_ADDR initial_sp
;
2921 struct trad_frame_saved_reg
*saved_regs
;
2924 static struct rs6000_frame_cache
*
2925 rs6000_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2927 struct rs6000_frame_cache
*cache
;
2928 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
2929 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2930 struct rs6000_framedata fdata
;
2931 int wordsize
= tdep
->wordsize
;
2934 if ((*this_cache
) != NULL
)
2935 return (*this_cache
);
2936 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
2937 (*this_cache
) = cache
;
2938 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
2940 func
= frame_func_unwind (next_frame
);
2941 pc
= frame_pc_unwind (next_frame
);
2942 skip_prologue (func
, pc
, &fdata
);
2944 /* Figure out the parent's stack pointer. */
2946 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
2947 address of the current frame. Things might be easier if the
2948 ->frame pointed to the outer-most address of the frame. In
2949 the mean time, the address of the prev frame is used as the
2950 base address of this frame. */
2951 cache
->base
= frame_unwind_register_unsigned (next_frame
, SP_REGNUM
);
2953 /* If the function appears to be frameless, check a couple of likely
2954 indicators that we have simply failed to find the frame setup.
2955 Two common cases of this are missing symbols (i.e.
2956 frame_func_unwind returns the wrong address or 0), and assembly
2957 stubs which have a fast exit path but set up a frame on the slow
2960 If the LR appears to return to this function, then presume that
2961 we have an ABI compliant frame that we failed to find. */
2962 if (fdata
.frameless
&& fdata
.lr_offset
== 0)
2967 saved_lr
= frame_unwind_register_unsigned (next_frame
,
2968 tdep
->ppc_lr_regnum
);
2969 if (func
== 0 && saved_lr
== pc
)
2973 CORE_ADDR saved_func
= get_pc_function_start (saved_lr
);
2974 if (func
== saved_func
)
2980 fdata
.frameless
= 0;
2981 fdata
.lr_offset
= wordsize
;
2985 if (!fdata
.frameless
)
2986 /* Frameless really means stackless. */
2987 cache
->base
= read_memory_addr (cache
->base
, wordsize
);
2989 trad_frame_set_value (cache
->saved_regs
, SP_REGNUM
, cache
->base
);
2991 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
2992 All fpr's from saved_fpr to fp31 are saved. */
2994 if (fdata
.saved_fpr
>= 0)
2997 CORE_ADDR fpr_addr
= cache
->base
+ fdata
.fpr_offset
;
2999 /* If skip_prologue says floating-point registers were saved,
3000 but the current architecture has no floating-point registers,
3001 then that's strange. But we have no indices to even record
3002 the addresses under, so we just ignore it. */
3003 if (ppc_floating_point_unit_p (gdbarch
))
3004 for (i
= fdata
.saved_fpr
; i
< ppc_num_fprs
; i
++)
3006 cache
->saved_regs
[tdep
->ppc_fp0_regnum
+ i
].addr
= fpr_addr
;
3011 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
3012 All gpr's from saved_gpr to gpr31 are saved. */
3014 if (fdata
.saved_gpr
>= 0)
3017 CORE_ADDR gpr_addr
= cache
->base
+ fdata
.gpr_offset
;
3018 for (i
= fdata
.saved_gpr
; i
< ppc_num_gprs
; i
++)
3020 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= gpr_addr
;
3021 gpr_addr
+= wordsize
;
3025 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
3026 All vr's from saved_vr to vr31 are saved. */
3027 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
3029 if (fdata
.saved_vr
>= 0)
3032 CORE_ADDR vr_addr
= cache
->base
+ fdata
.vr_offset
;
3033 for (i
= fdata
.saved_vr
; i
< 32; i
++)
3035 cache
->saved_regs
[tdep
->ppc_vr0_regnum
+ i
].addr
= vr_addr
;
3036 vr_addr
+= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
3041 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
3042 All vr's from saved_ev to ev31 are saved. ????? */
3043 if (tdep
->ppc_ev0_regnum
!= -1 && tdep
->ppc_ev31_regnum
!= -1)
3045 if (fdata
.saved_ev
>= 0)
3048 CORE_ADDR ev_addr
= cache
->base
+ fdata
.ev_offset
;
3049 for (i
= fdata
.saved_ev
; i
< ppc_num_gprs
; i
++)
3051 cache
->saved_regs
[tdep
->ppc_ev0_regnum
+ i
].addr
= ev_addr
;
3052 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= ev_addr
+ 4;
3053 ev_addr
+= register_size (gdbarch
, tdep
->ppc_ev0_regnum
);
3058 /* If != 0, fdata.cr_offset is the offset from the frame that
3060 if (fdata
.cr_offset
!= 0)
3061 cache
->saved_regs
[tdep
->ppc_cr_regnum
].addr
= cache
->base
+ fdata
.cr_offset
;
3063 /* If != 0, fdata.lr_offset is the offset from the frame that
3065 if (fdata
.lr_offset
!= 0)
3066 cache
->saved_regs
[tdep
->ppc_lr_regnum
].addr
= cache
->base
+ fdata
.lr_offset
;
3067 /* The PC is found in the link register. */
3068 cache
->saved_regs
[PC_REGNUM
] = cache
->saved_regs
[tdep
->ppc_lr_regnum
];
3070 /* If != 0, fdata.vrsave_offset is the offset from the frame that
3071 holds the VRSAVE. */
3072 if (fdata
.vrsave_offset
!= 0)
3073 cache
->saved_regs
[tdep
->ppc_vrsave_regnum
].addr
= cache
->base
+ fdata
.vrsave_offset
;
3075 if (fdata
.alloca_reg
< 0)
3076 /* If no alloca register used, then fi->frame is the value of the
3077 %sp for this frame, and it is good enough. */
3078 cache
->initial_sp
= frame_unwind_register_unsigned (next_frame
, SP_REGNUM
);
3080 cache
->initial_sp
= frame_unwind_register_unsigned (next_frame
,
3087 rs6000_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
3088 struct frame_id
*this_id
)
3090 struct rs6000_frame_cache
*info
= rs6000_frame_cache (next_frame
,
3092 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
3096 rs6000_frame_prev_register (struct frame_info
*next_frame
,
3098 int regnum
, int *optimizedp
,
3099 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
3100 int *realnump
, gdb_byte
*valuep
)
3102 struct rs6000_frame_cache
*info
= rs6000_frame_cache (next_frame
,
3104 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
3105 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
3108 static const struct frame_unwind rs6000_frame_unwind
=
3111 rs6000_frame_this_id
,
3112 rs6000_frame_prev_register
3115 static const struct frame_unwind
*
3116 rs6000_frame_sniffer (struct frame_info
*next_frame
)
3118 return &rs6000_frame_unwind
;
3124 rs6000_frame_base_address (struct frame_info
*next_frame
,
3127 struct rs6000_frame_cache
*info
= rs6000_frame_cache (next_frame
,
3129 return info
->initial_sp
;
3132 static const struct frame_base rs6000_frame_base
= {
3133 &rs6000_frame_unwind
,
3134 rs6000_frame_base_address
,
3135 rs6000_frame_base_address
,
3136 rs6000_frame_base_address
3139 static const struct frame_base
*
3140 rs6000_frame_base_sniffer (struct frame_info
*next_frame
)
3142 return &rs6000_frame_base
;
3145 /* Initialize the current architecture based on INFO. If possible, re-use an
3146 architecture from ARCHES, which is a list of architectures already created
3147 during this debugging session.
3149 Called e.g. at program startup, when reading a core file, and when reading
3152 static struct gdbarch
*
3153 rs6000_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
3155 struct gdbarch
*gdbarch
;
3156 struct gdbarch_tdep
*tdep
;
3157 int wordsize
, from_xcoff_exec
, from_elf_exec
, i
, off
;
3159 const struct variant
*v
;
3160 enum bfd_architecture arch
;
3166 from_xcoff_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
3167 bfd_get_flavour (info
.abfd
) == bfd_target_xcoff_flavour
;
3169 from_elf_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
3170 bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
;
3172 sysv_abi
= info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
;
3174 /* Check word size. If INFO is from a binary file, infer it from
3175 that, else choose a likely default. */
3176 if (from_xcoff_exec
)
3178 if (bfd_xcoff_is_xcoff64 (info
.abfd
))
3183 else if (from_elf_exec
)
3185 if (elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
3192 if (info
.bfd_arch_info
!= NULL
&& info
.bfd_arch_info
->bits_per_word
!= 0)
3193 wordsize
= info
.bfd_arch_info
->bits_per_word
/
3194 info
.bfd_arch_info
->bits_per_byte
;
3199 /* Find a candidate among extant architectures. */
3200 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
3202 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
3204 /* Word size in the various PowerPC bfd_arch_info structs isn't
3205 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
3206 separate word size check. */
3207 tdep
= gdbarch_tdep (arches
->gdbarch
);
3208 if (tdep
&& tdep
->wordsize
== wordsize
)
3209 return arches
->gdbarch
;
3212 /* None found, create a new architecture from INFO, whose bfd_arch_info
3213 validity depends on the source:
3214 - executable useless
3215 - rs6000_host_arch() good
3217 - "set arch" trust blindly
3218 - GDB startup useless but harmless */
3220 if (!from_xcoff_exec
)
3222 arch
= info
.bfd_arch_info
->arch
;
3223 mach
= info
.bfd_arch_info
->mach
;
3227 arch
= bfd_arch_powerpc
;
3228 bfd_default_set_arch_mach (&abfd
, arch
, 0);
3229 info
.bfd_arch_info
= bfd_get_arch_info (&abfd
);
3230 mach
= info
.bfd_arch_info
->mach
;
3232 tdep
= xmalloc (sizeof (struct gdbarch_tdep
));
3233 tdep
->wordsize
= wordsize
;
3235 /* For e500 executables, the apuinfo section is of help here. Such
3236 section contains the identifier and revision number of each
3237 Application-specific Processing Unit that is present on the
3238 chip. The content of the section is determined by the assembler
3239 which looks at each instruction and determines which unit (and
3240 which version of it) can execute it. In our case we just look for
3241 the existance of the section. */
3245 sect
= bfd_get_section_by_name (info
.abfd
, ".PPC.EMB.apuinfo");
3248 arch
= info
.bfd_arch_info
->arch
;
3249 mach
= bfd_mach_ppc_e500
;
3250 bfd_default_set_arch_mach (&abfd
, arch
, mach
);
3251 info
.bfd_arch_info
= bfd_get_arch_info (&abfd
);
3255 gdbarch
= gdbarch_alloc (&info
, tdep
);
3257 /* Initialize the number of real and pseudo registers in each variant. */
3260 /* Choose variant. */
3261 v
= find_variant_by_arch (arch
, mach
);
3265 tdep
->regs
= v
->regs
;
3267 tdep
->ppc_gp0_regnum
= 0;
3268 tdep
->ppc_toc_regnum
= 2;
3269 tdep
->ppc_ps_regnum
= 65;
3270 tdep
->ppc_cr_regnum
= 66;
3271 tdep
->ppc_lr_regnum
= 67;
3272 tdep
->ppc_ctr_regnum
= 68;
3273 tdep
->ppc_xer_regnum
= 69;
3274 if (v
->mach
== bfd_mach_ppc_601
)
3275 tdep
->ppc_mq_regnum
= 124;
3276 else if (arch
== bfd_arch_rs6000
)
3277 tdep
->ppc_mq_regnum
= 70;
3279 tdep
->ppc_mq_regnum
= -1;
3280 tdep
->ppc_fp0_regnum
= 32;
3281 tdep
->ppc_fpscr_regnum
= (arch
== bfd_arch_rs6000
) ? 71 : 70;
3282 tdep
->ppc_sr0_regnum
= 71;
3283 tdep
->ppc_vr0_regnum
= -1;
3284 tdep
->ppc_vrsave_regnum
= -1;
3285 tdep
->ppc_ev0_upper_regnum
= -1;
3286 tdep
->ppc_ev0_regnum
= -1;
3287 tdep
->ppc_ev31_regnum
= -1;
3288 tdep
->ppc_acc_regnum
= -1;
3289 tdep
->ppc_spefscr_regnum
= -1;
3291 set_gdbarch_pc_regnum (gdbarch
, 64);
3292 set_gdbarch_sp_regnum (gdbarch
, 1);
3293 set_gdbarch_deprecated_fp_regnum (gdbarch
, 1);
3294 set_gdbarch_register_sim_regno (gdbarch
, rs6000_register_sim_regno
);
3295 if (sysv_abi
&& wordsize
== 8)
3296 set_gdbarch_return_value (gdbarch
, ppc64_sysv_abi_return_value
);
3297 else if (sysv_abi
&& wordsize
== 4)
3298 set_gdbarch_return_value (gdbarch
, ppc_sysv_abi_return_value
);
3300 set_gdbarch_return_value (gdbarch
, rs6000_return_value
);
3302 /* Set lr_frame_offset. */
3304 tdep
->lr_frame_offset
= 16;
3306 tdep
->lr_frame_offset
= 4;
3308 tdep
->lr_frame_offset
= 8;
3310 if (v
->arch
== bfd_arch_rs6000
)
3311 tdep
->ppc_sr0_regnum
= -1;
3312 else if (v
->arch
== bfd_arch_powerpc
)
3316 tdep
->ppc_sr0_regnum
= -1;
3317 tdep
->ppc_vr0_regnum
= 71;
3318 tdep
->ppc_vrsave_regnum
= 104;
3320 case bfd_mach_ppc_7400
:
3321 tdep
->ppc_vr0_regnum
= 119;
3322 tdep
->ppc_vrsave_regnum
= 152;
3324 case bfd_mach_ppc_e500
:
3325 tdep
->ppc_toc_regnum
= -1;
3326 tdep
->ppc_ev0_upper_regnum
= 32;
3327 tdep
->ppc_ev0_regnum
= 73;
3328 tdep
->ppc_ev31_regnum
= 104;
3329 tdep
->ppc_acc_regnum
= 71;
3330 tdep
->ppc_spefscr_regnum
= 72;
3331 tdep
->ppc_fp0_regnum
= -1;
3332 tdep
->ppc_fpscr_regnum
= -1;
3333 tdep
->ppc_sr0_regnum
= -1;
3334 set_gdbarch_pseudo_register_read (gdbarch
, e500_pseudo_register_read
);
3335 set_gdbarch_pseudo_register_write (gdbarch
, e500_pseudo_register_write
);
3336 set_gdbarch_register_reggroup_p (gdbarch
, e500_register_reggroup_p
);
3339 case bfd_mach_ppc64
:
3340 case bfd_mach_ppc_620
:
3341 case bfd_mach_ppc_630
:
3342 case bfd_mach_ppc_a35
:
3343 case bfd_mach_ppc_rs64ii
:
3344 case bfd_mach_ppc_rs64iii
:
3345 /* These processor's register sets don't have segment registers. */
3346 tdep
->ppc_sr0_regnum
= -1;
3350 internal_error (__FILE__
, __LINE__
,
3351 _("rs6000_gdbarch_init: "
3352 "received unexpected BFD 'arch' value"));
3354 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
3356 /* Sanity check on registers. */
3357 gdb_assert (strcmp (tdep
->regs
[tdep
->ppc_gp0_regnum
].name
, "r0") == 0);
3359 /* Select instruction printer. */
3360 if (arch
== bfd_arch_rs6000
)
3361 set_gdbarch_print_insn (gdbarch
, print_insn_rs6000
);
3363 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_powerpc
);
3365 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
3367 set_gdbarch_num_regs (gdbarch
, v
->nregs
);
3368 set_gdbarch_num_pseudo_regs (gdbarch
, v
->npregs
);
3369 set_gdbarch_register_name (gdbarch
, rs6000_register_name
);
3370 set_gdbarch_register_type (gdbarch
, rs6000_register_type
);
3371 set_gdbarch_register_reggroup_p (gdbarch
, rs6000_register_reggroup_p
);
3373 set_gdbarch_ptr_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
3374 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
3375 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
3376 set_gdbarch_long_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
3377 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
3378 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
3379 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
3381 set_gdbarch_long_double_bit (gdbarch
, 16 * TARGET_CHAR_BIT
);
3383 set_gdbarch_long_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
3384 set_gdbarch_char_signed (gdbarch
, 0);
3386 set_gdbarch_frame_align (gdbarch
, rs6000_frame_align
);
3387 if (sysv_abi
&& wordsize
== 8)
3389 set_gdbarch_frame_red_zone_size (gdbarch
, 288);
3390 else if (!sysv_abi
&& wordsize
== 4)
3391 /* PowerOpen / AIX 32 bit. The saved area or red zone consists of
3392 19 4 byte GPRS + 18 8 byte FPRs giving a total of 220 bytes.
3393 Problem is, 220 isn't frame (16 byte) aligned. Round it up to
3395 set_gdbarch_frame_red_zone_size (gdbarch
, 224);
3397 set_gdbarch_convert_register_p (gdbarch
, rs6000_convert_register_p
);
3398 set_gdbarch_register_to_value (gdbarch
, rs6000_register_to_value
);
3399 set_gdbarch_value_to_register (gdbarch
, rs6000_value_to_register
);
3401 set_gdbarch_stab_reg_to_regnum (gdbarch
, rs6000_stab_reg_to_regnum
);
3402 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, rs6000_dwarf2_reg_to_regnum
);
3404 if (sysv_abi
&& wordsize
== 4)
3405 set_gdbarch_push_dummy_call (gdbarch
, ppc_sysv_abi_push_dummy_call
);
3406 else if (sysv_abi
&& wordsize
== 8)
3407 set_gdbarch_push_dummy_call (gdbarch
, ppc64_sysv_abi_push_dummy_call
);
3409 set_gdbarch_push_dummy_call (gdbarch
, rs6000_push_dummy_call
);
3411 set_gdbarch_skip_prologue (gdbarch
, rs6000_skip_prologue
);
3412 set_gdbarch_in_function_epilogue_p (gdbarch
, rs6000_in_function_epilogue_p
);
3414 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3415 set_gdbarch_breakpoint_from_pc (gdbarch
, rs6000_breakpoint_from_pc
);
3417 /* Handle the 64-bit SVR4 minimal-symbol convention of using "FN"
3418 for the descriptor and ".FN" for the entry-point -- a user
3419 specifying "break FN" will unexpectedly end up with a breakpoint
3420 on the descriptor and not the function. This architecture method
3421 transforms any breakpoints on descriptors into breakpoints on the
3422 corresponding entry point. */
3423 if (sysv_abi
&& wordsize
== 8)
3424 set_gdbarch_adjust_breakpoint_address (gdbarch
, ppc64_sysv_abi_adjust_breakpoint_address
);
3426 /* Not sure on this. FIXMEmgo */
3427 set_gdbarch_frame_args_skip (gdbarch
, 8);
3431 /* Handle RS/6000 function pointers (which are really function
3433 set_gdbarch_convert_from_func_ptr_addr (gdbarch
,
3434 rs6000_convert_from_func_ptr_addr
);
3437 /* Helpers for function argument information. */
3438 set_gdbarch_fetch_pointer_argument (gdbarch
, rs6000_fetch_pointer_argument
);
3440 /* Hook in ABI-specific overrides, if they have been registered. */
3441 gdbarch_init_osabi (info
, gdbarch
);
3445 case GDB_OSABI_LINUX
:
3446 /* FIXME: pgilliam/2005-10-21: Assume all PowerPC 64-bit linux systems
3447 have altivec registers. If not, ptrace will fail the first time it's
3448 called to access one and will not be called again. This wart will
3449 be removed when Daniel Jacobowitz's proposal for autodetecting target
3450 registers is implemented. */
3451 if ((v
->arch
== bfd_arch_powerpc
) && ((v
->mach
)== bfd_mach_ppc64
))
3453 tdep
->ppc_vr0_regnum
= 71;
3454 tdep
->ppc_vrsave_regnum
= 104;
3457 case GDB_OSABI_NETBSD_AOUT
:
3458 case GDB_OSABI_NETBSD_ELF
:
3459 case GDB_OSABI_UNKNOWN
:
3460 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
3461 frame_unwind_append_sniffer (gdbarch
, rs6000_frame_sniffer
);
3462 set_gdbarch_unwind_dummy_id (gdbarch
, rs6000_unwind_dummy_id
);
3463 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
3466 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
3468 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
3469 frame_unwind_append_sniffer (gdbarch
, rs6000_frame_sniffer
);
3470 set_gdbarch_unwind_dummy_id (gdbarch
, rs6000_unwind_dummy_id
);
3471 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
3474 init_sim_regno_table (gdbarch
);
3480 rs6000_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
3482 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3487 /* FIXME: Dump gdbarch_tdep. */
3490 /* Initialization code. */
3492 extern initialize_file_ftype _initialize_rs6000_tdep
; /* -Wmissing-prototypes */
3495 _initialize_rs6000_tdep (void)
3497 gdbarch_register (bfd_arch_rs6000
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
3498 gdbarch_register (bfd_arch_powerpc
, rs6000_gdbarch_init
, rs6000_dump_tdep
);