1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 1986-2018 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
29 #include "arch-utils.h"
32 #include "target-float.h"
34 #include "parser-defs.h"
37 #include "sim-regno.h"
38 #include "gdb/sim-ppc.h"
39 #include "reggroups.h"
40 #include "dwarf2-frame.h"
41 #include "target-descriptions.h"
42 #include "user-regs.h"
43 #include "record-full.h"
46 #include "coff/internal.h" /* for libcoff.h */
47 #include "libcoff.h" /* for xcoff_data */
48 #include "coff/xcoff.h"
53 #include "elf/ppc64.h"
55 #include "solib-svr4.h"
57 #include "ppc-ravenscar-thread.h"
61 #include "trad-frame.h"
62 #include "frame-unwind.h"
63 #include "frame-base.h"
69 #include "features/rs6000/powerpc-32.c"
70 #include "features/rs6000/powerpc-altivec32.c"
71 #include "features/rs6000/powerpc-vsx32.c"
72 #include "features/rs6000/powerpc-403.c"
73 #include "features/rs6000/powerpc-403gc.c"
74 #include "features/rs6000/powerpc-405.c"
75 #include "features/rs6000/powerpc-505.c"
76 #include "features/rs6000/powerpc-601.c"
77 #include "features/rs6000/powerpc-602.c"
78 #include "features/rs6000/powerpc-603.c"
79 #include "features/rs6000/powerpc-604.c"
80 #include "features/rs6000/powerpc-64.c"
81 #include "features/rs6000/powerpc-altivec64.c"
82 #include "features/rs6000/powerpc-vsx64.c"
83 #include "features/rs6000/powerpc-7400.c"
84 #include "features/rs6000/powerpc-750.c"
85 #include "features/rs6000/powerpc-860.c"
86 #include "features/rs6000/powerpc-e500.c"
87 #include "features/rs6000/rs6000.c"
89 /* Determine if regnum is an SPE pseudo-register. */
90 #define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \
91 && (regnum) >= (tdep)->ppc_ev0_regnum \
92 && (regnum) < (tdep)->ppc_ev0_regnum + 32)
94 /* Determine if regnum is a decimal float pseudo-register. */
95 #define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \
96 && (regnum) >= (tdep)->ppc_dl0_regnum \
97 && (regnum) < (tdep)->ppc_dl0_regnum + 16)
99 /* Determine if regnum is a POWER7 VSX register. */
100 #define IS_VSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_vsr0_regnum >= 0 \
101 && (regnum) >= (tdep)->ppc_vsr0_regnum \
102 && (regnum) < (tdep)->ppc_vsr0_regnum + ppc_num_vsrs)
104 /* Determine if regnum is a POWER7 Extended FP register. */
105 #define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \
106 && (regnum) >= (tdep)->ppc_efpr0_regnum \
107 && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_efprs)
109 /* Holds the current set of options to be passed to the disassembler. */
110 static char *powerpc_disassembler_options
;
112 /* The list of available "set powerpc ..." and "show powerpc ..."
114 static struct cmd_list_element
*setpowerpccmdlist
= NULL
;
115 static struct cmd_list_element
*showpowerpccmdlist
= NULL
;
117 static enum auto_boolean powerpc_soft_float_global
= AUTO_BOOLEAN_AUTO
;
119 /* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */
120 static const char *const powerpc_vector_strings
[] =
129 /* A variable that can be configured by the user. */
130 static enum powerpc_vector_abi powerpc_vector_abi_global
= POWERPC_VEC_AUTO
;
131 static const char *powerpc_vector_abi_string
= "auto";
133 /* To be used by skip_prologue. */
135 struct rs6000_framedata
137 int offset
; /* total size of frame --- the distance
138 by which we decrement sp to allocate
140 int saved_gpr
; /* smallest # of saved gpr */
141 unsigned int gpr_mask
; /* Each bit is an individual saved GPR. */
142 int saved_fpr
; /* smallest # of saved fpr */
143 int saved_vr
; /* smallest # of saved vr */
144 int saved_ev
; /* smallest # of saved ev */
145 int alloca_reg
; /* alloca register number (frame ptr) */
146 char frameless
; /* true if frameless functions. */
147 char nosavedpc
; /* true if pc not saved. */
148 char used_bl
; /* true if link register clobbered */
149 int gpr_offset
; /* offset of saved gprs from prev sp */
150 int fpr_offset
; /* offset of saved fprs from prev sp */
151 int vr_offset
; /* offset of saved vrs from prev sp */
152 int ev_offset
; /* offset of saved evs from prev sp */
153 int lr_offset
; /* offset of saved lr */
154 int lr_register
; /* register of saved lr, if trustworthy */
155 int cr_offset
; /* offset of saved cr */
156 int vrsave_offset
; /* offset of saved vrsave register */
160 /* Is REGNO a VSX register? Return 1 if so, 0 otherwise. */
162 vsx_register_p (struct gdbarch
*gdbarch
, int regno
)
164 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
165 if (tdep
->ppc_vsr0_regnum
< 0)
168 return (regno
>= tdep
->ppc_vsr0_upper_regnum
&& regno
169 <= tdep
->ppc_vsr0_upper_regnum
+ 31);
172 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
174 altivec_register_p (struct gdbarch
*gdbarch
, int regno
)
176 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
177 if (tdep
->ppc_vr0_regnum
< 0 || tdep
->ppc_vrsave_regnum
< 0)
180 return (regno
>= tdep
->ppc_vr0_regnum
&& regno
<= tdep
->ppc_vrsave_regnum
);
184 /* Return true if REGNO is an SPE register, false otherwise. */
186 spe_register_p (struct gdbarch
*gdbarch
, int regno
)
188 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
190 /* Is it a reference to EV0 -- EV31, and do we have those? */
191 if (IS_SPE_PSEUDOREG (tdep
, regno
))
194 /* Is it a reference to one of the raw upper GPR halves? */
195 if (tdep
->ppc_ev0_upper_regnum
>= 0
196 && tdep
->ppc_ev0_upper_regnum
<= regno
197 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
200 /* Is it a reference to the 64-bit accumulator, and do we have that? */
201 if (tdep
->ppc_acc_regnum
>= 0
202 && tdep
->ppc_acc_regnum
== regno
)
205 /* Is it a reference to the SPE floating-point status and control register,
206 and do we have that? */
207 if (tdep
->ppc_spefscr_regnum
>= 0
208 && tdep
->ppc_spefscr_regnum
== regno
)
215 /* Return non-zero if the architecture described by GDBARCH has
216 floating-point registers (f0 --- f31 and fpscr). */
218 ppc_floating_point_unit_p (struct gdbarch
*gdbarch
)
220 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
222 return (tdep
->ppc_fp0_regnum
>= 0
223 && tdep
->ppc_fpscr_regnum
>= 0);
226 /* Return non-zero if the architecture described by GDBARCH has
227 Altivec registers (vr0 --- vr31, vrsave and vscr). */
229 ppc_altivec_support_p (struct gdbarch
*gdbarch
)
231 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
233 return (tdep
->ppc_vr0_regnum
>= 0
234 && tdep
->ppc_vrsave_regnum
>= 0);
237 /* Check that TABLE[GDB_REGNO] is not already initialized, and then
240 This is a helper function for init_sim_regno_table, constructing
241 the table mapping GDB register numbers to sim register numbers; we
242 initialize every element in that table to -1 before we start
245 set_sim_regno (int *table
, int gdb_regno
, int sim_regno
)
247 /* Make sure we don't try to assign any given GDB register a sim
248 register number more than once. */
249 gdb_assert (table
[gdb_regno
] == -1);
250 table
[gdb_regno
] = sim_regno
;
254 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
255 numbers to simulator register numbers, based on the values placed
256 in the ARCH->tdep->ppc_foo_regnum members. */
258 init_sim_regno_table (struct gdbarch
*arch
)
260 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
261 int total_regs
= gdbarch_num_regs (arch
);
262 int *sim_regno
= GDBARCH_OBSTACK_CALLOC (arch
, total_regs
, int);
264 static const char *const segment_regs
[] = {
265 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
266 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
269 /* Presume that all registers not explicitly mentioned below are
270 unavailable from the sim. */
271 for (i
= 0; i
< total_regs
; i
++)
274 /* General-purpose registers. */
275 for (i
= 0; i
< ppc_num_gprs
; i
++)
276 set_sim_regno (sim_regno
, tdep
->ppc_gp0_regnum
+ i
, sim_ppc_r0_regnum
+ i
);
278 /* Floating-point registers. */
279 if (tdep
->ppc_fp0_regnum
>= 0)
280 for (i
= 0; i
< ppc_num_fprs
; i
++)
281 set_sim_regno (sim_regno
,
282 tdep
->ppc_fp0_regnum
+ i
,
283 sim_ppc_f0_regnum
+ i
);
284 if (tdep
->ppc_fpscr_regnum
>= 0)
285 set_sim_regno (sim_regno
, tdep
->ppc_fpscr_regnum
, sim_ppc_fpscr_regnum
);
287 set_sim_regno (sim_regno
, gdbarch_pc_regnum (arch
), sim_ppc_pc_regnum
);
288 set_sim_regno (sim_regno
, tdep
->ppc_ps_regnum
, sim_ppc_ps_regnum
);
289 set_sim_regno (sim_regno
, tdep
->ppc_cr_regnum
, sim_ppc_cr_regnum
);
291 /* Segment registers. */
292 for (i
= 0; i
< ppc_num_srs
; i
++)
296 gdb_regno
= user_reg_map_name_to_regnum (arch
, segment_regs
[i
], -1);
298 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_sr0_regnum
+ i
);
301 /* Altivec registers. */
302 if (tdep
->ppc_vr0_regnum
>= 0)
304 for (i
= 0; i
< ppc_num_vrs
; i
++)
305 set_sim_regno (sim_regno
,
306 tdep
->ppc_vr0_regnum
+ i
,
307 sim_ppc_vr0_regnum
+ i
);
309 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
310 we can treat this more like the other cases. */
311 set_sim_regno (sim_regno
,
312 tdep
->ppc_vr0_regnum
+ ppc_num_vrs
,
313 sim_ppc_vscr_regnum
);
315 /* vsave is a special-purpose register, so the code below handles it. */
317 /* SPE APU (E500) registers. */
318 if (tdep
->ppc_ev0_upper_regnum
>= 0)
319 for (i
= 0; i
< ppc_num_gprs
; i
++)
320 set_sim_regno (sim_regno
,
321 tdep
->ppc_ev0_upper_regnum
+ i
,
322 sim_ppc_rh0_regnum
+ i
);
323 if (tdep
->ppc_acc_regnum
>= 0)
324 set_sim_regno (sim_regno
, tdep
->ppc_acc_regnum
, sim_ppc_acc_regnum
);
325 /* spefscr is a special-purpose register, so the code below handles it. */
328 /* Now handle all special-purpose registers. Verify that they
329 haven't mistakenly been assigned numbers by any of the above
331 for (i
= 0; i
< sim_ppc_num_sprs
; i
++)
333 const char *spr_name
= sim_spr_register_name (i
);
336 if (spr_name
!= NULL
)
337 gdb_regno
= user_reg_map_name_to_regnum (arch
, spr_name
, -1);
340 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_spr0_regnum
+ i
);
344 /* Drop the initialized array into place. */
345 tdep
->sim_regno
= sim_regno
;
349 /* Given a GDB register number REG, return the corresponding SIM
352 rs6000_register_sim_regno (struct gdbarch
*gdbarch
, int reg
)
354 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
357 if (tdep
->sim_regno
== NULL
)
358 init_sim_regno_table (gdbarch
);
360 gdb_assert (0 <= reg
&& reg
<= gdbarch_num_cooked_regs (gdbarch
));
361 sim_regno
= tdep
->sim_regno
[reg
];
366 return LEGACY_SIM_REGNO_IGNORE
;
371 /* Register set support functions. */
373 /* REGS + OFFSET contains register REGNUM in a field REGSIZE wide.
374 Write the register to REGCACHE. */
377 ppc_supply_reg (struct regcache
*regcache
, int regnum
,
378 const gdb_byte
*regs
, size_t offset
, int regsize
)
380 if (regnum
!= -1 && offset
!= -1)
384 struct gdbarch
*gdbarch
= regcache
->arch ();
385 int gdb_regsize
= register_size (gdbarch
, regnum
);
386 if (gdb_regsize
< regsize
387 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
388 offset
+= regsize
- gdb_regsize
;
390 regcache
->raw_supply (regnum
, regs
+ offset
);
394 /* Read register REGNUM from REGCACHE and store to REGS + OFFSET
395 in a field REGSIZE wide. Zero pad as necessary. */
398 ppc_collect_reg (const struct regcache
*regcache
, int regnum
,
399 gdb_byte
*regs
, size_t offset
, int regsize
)
401 if (regnum
!= -1 && offset
!= -1)
405 struct gdbarch
*gdbarch
= regcache
->arch ();
406 int gdb_regsize
= register_size (gdbarch
, regnum
);
407 if (gdb_regsize
< regsize
)
409 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
411 memset (regs
+ offset
, 0, regsize
- gdb_regsize
);
412 offset
+= regsize
- gdb_regsize
;
415 memset (regs
+ offset
+ regsize
- gdb_regsize
, 0,
416 regsize
- gdb_regsize
);
419 regcache
->raw_collect (regnum
, regs
+ offset
);
424 ppc_greg_offset (struct gdbarch
*gdbarch
,
425 struct gdbarch_tdep
*tdep
,
426 const struct ppc_reg_offsets
*offsets
,
430 *regsize
= offsets
->gpr_size
;
431 if (regnum
>= tdep
->ppc_gp0_regnum
432 && regnum
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
)
433 return (offsets
->r0_offset
434 + (regnum
- tdep
->ppc_gp0_regnum
) * offsets
->gpr_size
);
436 if (regnum
== gdbarch_pc_regnum (gdbarch
))
437 return offsets
->pc_offset
;
439 if (regnum
== tdep
->ppc_ps_regnum
)
440 return offsets
->ps_offset
;
442 if (regnum
== tdep
->ppc_lr_regnum
)
443 return offsets
->lr_offset
;
445 if (regnum
== tdep
->ppc_ctr_regnum
)
446 return offsets
->ctr_offset
;
448 *regsize
= offsets
->xr_size
;
449 if (regnum
== tdep
->ppc_cr_regnum
)
450 return offsets
->cr_offset
;
452 if (regnum
== tdep
->ppc_xer_regnum
)
453 return offsets
->xer_offset
;
455 if (regnum
== tdep
->ppc_mq_regnum
)
456 return offsets
->mq_offset
;
462 ppc_fpreg_offset (struct gdbarch_tdep
*tdep
,
463 const struct ppc_reg_offsets
*offsets
,
466 if (regnum
>= tdep
->ppc_fp0_regnum
467 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
)
468 return offsets
->f0_offset
+ (regnum
- tdep
->ppc_fp0_regnum
) * 8;
470 if (regnum
== tdep
->ppc_fpscr_regnum
)
471 return offsets
->fpscr_offset
;
476 /* Supply register REGNUM in the general-purpose register set REGSET
477 from the buffer specified by GREGS and LEN to register cache
478 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
481 ppc_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
482 int regnum
, const void *gregs
, size_t len
)
484 struct gdbarch
*gdbarch
= regcache
->arch ();
485 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
486 const struct ppc_reg_offsets
*offsets
487 = (const struct ppc_reg_offsets
*) regset
->regmap
;
494 int gpr_size
= offsets
->gpr_size
;
496 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
497 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
498 i
++, offset
+= gpr_size
)
499 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) gregs
, offset
,
502 ppc_supply_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
503 (const gdb_byte
*) gregs
, offsets
->pc_offset
, gpr_size
);
504 ppc_supply_reg (regcache
, tdep
->ppc_ps_regnum
,
505 (const gdb_byte
*) gregs
, offsets
->ps_offset
, gpr_size
);
506 ppc_supply_reg (regcache
, tdep
->ppc_lr_regnum
,
507 (const gdb_byte
*) gregs
, offsets
->lr_offset
, gpr_size
);
508 ppc_supply_reg (regcache
, tdep
->ppc_ctr_regnum
,
509 (const gdb_byte
*) gregs
, offsets
->ctr_offset
, gpr_size
);
510 ppc_supply_reg (regcache
, tdep
->ppc_cr_regnum
,
511 (const gdb_byte
*) gregs
, offsets
->cr_offset
,
513 ppc_supply_reg (regcache
, tdep
->ppc_xer_regnum
,
514 (const gdb_byte
*) gregs
, offsets
->xer_offset
,
516 ppc_supply_reg (regcache
, tdep
->ppc_mq_regnum
,
517 (const gdb_byte
*) gregs
, offsets
->mq_offset
,
522 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
523 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) gregs
, offset
, regsize
);
526 /* Supply register REGNUM in the floating-point register set REGSET
527 from the buffer specified by FPREGS and LEN to register cache
528 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
531 ppc_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
532 int regnum
, const void *fpregs
, size_t len
)
534 struct gdbarch
*gdbarch
= regcache
->arch ();
535 struct gdbarch_tdep
*tdep
;
536 const struct ppc_reg_offsets
*offsets
;
539 if (!ppc_floating_point_unit_p (gdbarch
))
542 tdep
= gdbarch_tdep (gdbarch
);
543 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
548 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
549 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
551 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) fpregs
, offset
, 8);
553 ppc_supply_reg (regcache
, tdep
->ppc_fpscr_regnum
,
554 (const gdb_byte
*) fpregs
, offsets
->fpscr_offset
,
555 offsets
->fpscr_size
);
559 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
560 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) fpregs
, offset
,
561 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
564 /* Collect register REGNUM in the general-purpose register set
565 REGSET from register cache REGCACHE into the buffer specified by
566 GREGS and LEN. If REGNUM is -1, do this for all registers in
570 ppc_collect_gregset (const struct regset
*regset
,
571 const struct regcache
*regcache
,
572 int regnum
, void *gregs
, size_t len
)
574 struct gdbarch
*gdbarch
= regcache
->arch ();
575 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
576 const struct ppc_reg_offsets
*offsets
577 = (const struct ppc_reg_offsets
*) regset
->regmap
;
584 int gpr_size
= offsets
->gpr_size
;
586 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
587 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
588 i
++, offset
+= gpr_size
)
589 ppc_collect_reg (regcache
, i
, (gdb_byte
*) gregs
, offset
, gpr_size
);
591 ppc_collect_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
592 (gdb_byte
*) gregs
, offsets
->pc_offset
, gpr_size
);
593 ppc_collect_reg (regcache
, tdep
->ppc_ps_regnum
,
594 (gdb_byte
*) gregs
, offsets
->ps_offset
, gpr_size
);
595 ppc_collect_reg (regcache
, tdep
->ppc_lr_regnum
,
596 (gdb_byte
*) gregs
, offsets
->lr_offset
, gpr_size
);
597 ppc_collect_reg (regcache
, tdep
->ppc_ctr_regnum
,
598 (gdb_byte
*) gregs
, offsets
->ctr_offset
, gpr_size
);
599 ppc_collect_reg (regcache
, tdep
->ppc_cr_regnum
,
600 (gdb_byte
*) gregs
, offsets
->cr_offset
,
602 ppc_collect_reg (regcache
, tdep
->ppc_xer_regnum
,
603 (gdb_byte
*) gregs
, offsets
->xer_offset
,
605 ppc_collect_reg (regcache
, tdep
->ppc_mq_regnum
,
606 (gdb_byte
*) gregs
, offsets
->mq_offset
,
611 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
612 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) gregs
, offset
, regsize
);
615 /* Collect register REGNUM in the floating-point register set
616 REGSET from register cache REGCACHE into the buffer specified by
617 FPREGS and LEN. If REGNUM is -1, do this for all registers in
621 ppc_collect_fpregset (const struct regset
*regset
,
622 const struct regcache
*regcache
,
623 int regnum
, void *fpregs
, size_t len
)
625 struct gdbarch
*gdbarch
= regcache
->arch ();
626 struct gdbarch_tdep
*tdep
;
627 const struct ppc_reg_offsets
*offsets
;
630 if (!ppc_floating_point_unit_p (gdbarch
))
633 tdep
= gdbarch_tdep (gdbarch
);
634 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
639 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
640 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
642 ppc_collect_reg (regcache
, i
, (gdb_byte
*) fpregs
, offset
, 8);
644 ppc_collect_reg (regcache
, tdep
->ppc_fpscr_regnum
,
645 (gdb_byte
*) fpregs
, offsets
->fpscr_offset
,
646 offsets
->fpscr_size
);
650 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
651 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) fpregs
, offset
,
652 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
656 insn_changes_sp_or_jumps (unsigned long insn
)
658 int opcode
= (insn
>> 26) & 0x03f;
659 int sd
= (insn
>> 21) & 0x01f;
660 int a
= (insn
>> 16) & 0x01f;
661 int subcode
= (insn
>> 1) & 0x3ff;
663 /* Changes the stack pointer. */
665 /* NOTE: There are many ways to change the value of a given register.
666 The ways below are those used when the register is R1, the SP,
667 in a funtion's epilogue. */
669 if (opcode
== 31 && subcode
== 444 && a
== 1)
670 return 1; /* mr R1,Rn */
671 if (opcode
== 14 && sd
== 1)
672 return 1; /* addi R1,Rn,simm */
673 if (opcode
== 58 && sd
== 1)
674 return 1; /* ld R1,ds(Rn) */
676 /* Transfers control. */
682 if (opcode
== 19 && subcode
== 16)
684 if (opcode
== 19 && subcode
== 528)
685 return 1; /* bcctr */
690 /* Return true if we are in the function's epilogue, i.e. after the
691 instruction that destroyed the function's stack frame.
693 1) scan forward from the point of execution:
694 a) If you find an instruction that modifies the stack pointer
695 or transfers control (except a return), execution is not in
697 b) Stop scanning if you find a return instruction or reach the
698 end of the function or reach the hard limit for the size of
700 2) scan backward from the point of execution:
701 a) If you find an instruction that modifies the stack pointer,
702 execution *is* in an epilogue, return.
703 b) Stop scanning if you reach an instruction that transfers
704 control or the beginning of the function or reach the hard
705 limit for the size of an epilogue. */
708 rs6000_in_function_epilogue_frame_p (struct frame_info
*curfrm
,
709 struct gdbarch
*gdbarch
, CORE_ADDR pc
)
711 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
712 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
713 bfd_byte insn_buf
[PPC_INSN_SIZE
];
714 CORE_ADDR scan_pc
, func_start
, func_end
, epilogue_start
, epilogue_end
;
717 /* Find the search limits based on function boundaries and hard limit. */
719 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
722 epilogue_start
= pc
- PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
723 if (epilogue_start
< func_start
) epilogue_start
= func_start
;
725 epilogue_end
= pc
+ PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
726 if (epilogue_end
> func_end
) epilogue_end
= func_end
;
728 /* Scan forward until next 'blr'. */
730 for (scan_pc
= pc
; scan_pc
< epilogue_end
; scan_pc
+= PPC_INSN_SIZE
)
732 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
734 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
735 if (insn
== 0x4e800020)
737 /* Assume a bctr is a tail call unless it points strictly within
739 if (insn
== 0x4e800420)
741 CORE_ADDR ctr
= get_frame_register_unsigned (curfrm
,
742 tdep
->ppc_ctr_regnum
);
743 if (ctr
> func_start
&& ctr
< func_end
)
748 if (insn_changes_sp_or_jumps (insn
))
752 /* Scan backward until adjustment to stack pointer (R1). */
754 for (scan_pc
= pc
- PPC_INSN_SIZE
;
755 scan_pc
>= epilogue_start
;
756 scan_pc
-= PPC_INSN_SIZE
)
758 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
760 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
761 if (insn_changes_sp_or_jumps (insn
))
768 /* Implement the stack_frame_destroyed_p gdbarch method. */
771 rs6000_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
773 return rs6000_in_function_epilogue_frame_p (get_current_frame (),
777 /* Get the ith function argument for the current function. */
779 rs6000_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
782 return get_frame_register_unsigned (frame
, 3 + argi
);
785 /* Sequence of bytes for breakpoint instruction. */
787 constexpr gdb_byte big_breakpoint
[] = { 0x7d, 0x82, 0x10, 0x08 };
788 constexpr gdb_byte little_breakpoint
[] = { 0x08, 0x10, 0x82, 0x7d };
790 typedef BP_MANIPULATION_ENDIAN (little_breakpoint
, big_breakpoint
)
793 /* Instruction masks for displaced stepping. */
794 #define BRANCH_MASK 0xfc000000
795 #define BP_MASK 0xFC0007FE
796 #define B_INSN 0x48000000
797 #define BC_INSN 0x40000000
798 #define BXL_INSN 0x4c000000
799 #define BP_INSN 0x7C000008
801 /* Instruction masks used during single-stepping of atomic
803 #define LOAD_AND_RESERVE_MASK 0xfc0007fe
804 #define LWARX_INSTRUCTION 0x7c000028
805 #define LDARX_INSTRUCTION 0x7c0000A8
806 #define LBARX_INSTRUCTION 0x7c000068
807 #define LHARX_INSTRUCTION 0x7c0000e8
808 #define LQARX_INSTRUCTION 0x7c000228
809 #define STORE_CONDITIONAL_MASK 0xfc0007ff
810 #define STWCX_INSTRUCTION 0x7c00012d
811 #define STDCX_INSTRUCTION 0x7c0001ad
812 #define STBCX_INSTRUCTION 0x7c00056d
813 #define STHCX_INSTRUCTION 0x7c0005ad
814 #define STQCX_INSTRUCTION 0x7c00016d
816 /* Check if insn is one of the Load And Reserve instructions used for atomic
818 #define IS_LOAD_AND_RESERVE_INSN(insn) ((insn & LOAD_AND_RESERVE_MASK) == LWARX_INSTRUCTION \
819 || (insn & LOAD_AND_RESERVE_MASK) == LDARX_INSTRUCTION \
820 || (insn & LOAD_AND_RESERVE_MASK) == LBARX_INSTRUCTION \
821 || (insn & LOAD_AND_RESERVE_MASK) == LHARX_INSTRUCTION \
822 || (insn & LOAD_AND_RESERVE_MASK) == LQARX_INSTRUCTION)
823 /* Check if insn is one of the Store Conditional instructions used for atomic
825 #define IS_STORE_CONDITIONAL_INSN(insn) ((insn & STORE_CONDITIONAL_MASK) == STWCX_INSTRUCTION \
826 || (insn & STORE_CONDITIONAL_MASK) == STDCX_INSTRUCTION \
827 || (insn & STORE_CONDITIONAL_MASK) == STBCX_INSTRUCTION \
828 || (insn & STORE_CONDITIONAL_MASK) == STHCX_INSTRUCTION \
829 || (insn & STORE_CONDITIONAL_MASK) == STQCX_INSTRUCTION)
831 typedef buf_displaced_step_closure ppc_displaced_step_closure
;
833 /* We can't displaced step atomic sequences. */
835 static struct displaced_step_closure
*
836 ppc_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
837 CORE_ADDR from
, CORE_ADDR to
,
838 struct regcache
*regs
)
840 size_t len
= gdbarch_max_insn_length (gdbarch
);
841 std::unique_ptr
<ppc_displaced_step_closure
> closure
842 (new ppc_displaced_step_closure (len
));
843 gdb_byte
*buf
= closure
->buf
.data ();
844 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
847 read_memory (from
, buf
, len
);
849 insn
= extract_signed_integer (buf
, PPC_INSN_SIZE
, byte_order
);
851 /* Assume all atomic sequences start with a Load and Reserve instruction. */
852 if (IS_LOAD_AND_RESERVE_INSN (insn
))
856 fprintf_unfiltered (gdb_stdlog
,
857 "displaced: can't displaced step "
858 "atomic sequence at %s\n",
859 paddress (gdbarch
, from
));
865 write_memory (to
, buf
, len
);
869 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
870 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
871 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
874 return closure
.release ();
877 /* Fix up the state of registers and memory after having single-stepped
878 a displaced instruction. */
880 ppc_displaced_step_fixup (struct gdbarch
*gdbarch
,
881 struct displaced_step_closure
*closure_
,
882 CORE_ADDR from
, CORE_ADDR to
,
883 struct regcache
*regs
)
885 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
886 /* Our closure is a copy of the instruction. */
887 ppc_displaced_step_closure
*closure
= (ppc_displaced_step_closure
*) closure_
;
888 ULONGEST insn
= extract_unsigned_integer (closure
->buf
.data (),
889 PPC_INSN_SIZE
, byte_order
);
891 /* Offset for non PC-relative instructions. */
892 LONGEST offset
= PPC_INSN_SIZE
;
894 opcode
= insn
& BRANCH_MASK
;
897 fprintf_unfiltered (gdb_stdlog
,
898 "displaced: (ppc) fixup (%s, %s)\n",
899 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
902 /* Handle PC-relative branch instructions. */
903 if (opcode
== B_INSN
|| opcode
== BC_INSN
|| opcode
== BXL_INSN
)
907 /* Read the current PC value after the instruction has been executed
908 in a displaced location. Calculate the offset to be applied to the
909 original PC value before the displaced stepping. */
910 regcache_cooked_read_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
912 offset
= current_pc
- to
;
914 if (opcode
!= BXL_INSN
)
916 /* Check for AA bit indicating whether this is an absolute
917 addressing or PC-relative (1: absolute, 0: relative). */
920 /* PC-relative addressing is being used in the branch. */
924 "displaced: (ppc) branch instruction: %s\n"
925 "displaced: (ppc) adjusted PC from %s to %s\n",
926 paddress (gdbarch
, insn
), paddress (gdbarch
, current_pc
),
927 paddress (gdbarch
, from
+ offset
));
929 regcache_cooked_write_unsigned (regs
,
930 gdbarch_pc_regnum (gdbarch
),
936 /* If we're here, it means we have a branch to LR or CTR. If the
937 branch was taken, the offset is probably greater than 4 (the next
938 instruction), so it's safe to assume that an offset of 4 means we
939 did not take the branch. */
940 if (offset
== PPC_INSN_SIZE
)
941 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
942 from
+ PPC_INSN_SIZE
);
945 /* Check for LK bit indicating whether we should set the link
946 register to point to the next instruction
947 (1: Set, 0: Don't set). */
950 /* Link register needs to be set to the next instruction's PC. */
951 regcache_cooked_write_unsigned (regs
,
952 gdbarch_tdep (gdbarch
)->ppc_lr_regnum
,
953 from
+ PPC_INSN_SIZE
);
955 fprintf_unfiltered (gdb_stdlog
,
956 "displaced: (ppc) adjusted LR to %s\n",
957 paddress (gdbarch
, from
+ PPC_INSN_SIZE
));
961 /* Check for breakpoints in the inferior. If we've found one, place the PC
962 right at the breakpoint instruction. */
963 else if ((insn
& BP_MASK
) == BP_INSN
)
964 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
), from
);
966 /* Handle any other instructions that do not fit in the categories above. */
967 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
971 /* Always use hardware single-stepping to execute the
972 displaced instruction. */
974 ppc_displaced_step_hw_singlestep (struct gdbarch
*gdbarch
,
975 struct displaced_step_closure
*closure
)
980 /* Checks for an atomic sequence of instructions beginning with a
981 Load And Reserve instruction and ending with a Store Conditional
982 instruction. If such a sequence is found, attempt to step through it.
983 A breakpoint is placed at the end of the sequence. */
984 std::vector
<CORE_ADDR
>
985 ppc_deal_with_atomic_sequence (struct regcache
*regcache
)
987 struct gdbarch
*gdbarch
= regcache
->arch ();
988 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
989 CORE_ADDR pc
= regcache_read_pc (regcache
);
990 CORE_ADDR breaks
[2] = {CORE_ADDR_MAX
, CORE_ADDR_MAX
};
992 CORE_ADDR closing_insn
; /* Instruction that closes the atomic sequence. */
993 int insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
996 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
997 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
998 int bc_insn_count
= 0; /* Conditional branch instruction count. */
1000 /* Assume all atomic sequences start with a Load And Reserve instruction. */
1001 if (!IS_LOAD_AND_RESERVE_INSN (insn
))
1004 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
1006 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
1008 loc
+= PPC_INSN_SIZE
;
1009 insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1011 /* Assume that there is at most one conditional branch in the atomic
1012 sequence. If a conditional branch is found, put a breakpoint in
1013 its destination address. */
1014 if ((insn
& BRANCH_MASK
) == BC_INSN
)
1016 int immediate
= ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
1017 int absolute
= insn
& 2;
1019 if (bc_insn_count
>= 1)
1020 return {}; /* More than one conditional branch found, fallback
1021 to the standard single-step code. */
1024 breaks
[1] = immediate
;
1026 breaks
[1] = loc
+ immediate
;
1032 if (IS_STORE_CONDITIONAL_INSN (insn
))
1036 /* Assume that the atomic sequence ends with a Store Conditional
1038 if (!IS_STORE_CONDITIONAL_INSN (insn
))
1042 loc
+= PPC_INSN_SIZE
;
1044 /* Insert a breakpoint right after the end of the atomic sequence. */
1047 /* Check for duplicated breakpoints. Check also for a breakpoint
1048 placed (branch instruction's destination) anywhere in sequence. */
1050 && (breaks
[1] == breaks
[0]
1051 || (breaks
[1] >= pc
&& breaks
[1] <= closing_insn
)))
1052 last_breakpoint
= 0;
1054 std::vector
<CORE_ADDR
> next_pcs
;
1056 for (index
= 0; index
<= last_breakpoint
; index
++)
1057 next_pcs
.push_back (breaks
[index
]);
1063 #define SIGNED_SHORT(x) \
1064 ((sizeof (short) == 2) \
1065 ? ((int)(short)(x)) \
1066 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
1068 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
1070 /* Limit the number of skipped non-prologue instructions, as the examining
1071 of the prologue is expensive. */
1072 static int max_skip_non_prologue_insns
= 10;
1074 /* Return nonzero if the given instruction OP can be part of the prologue
1075 of a function and saves a parameter on the stack. FRAMEP should be
1076 set if one of the previous instructions in the function has set the
1080 store_param_on_stack_p (unsigned long op
, int framep
, int *r0_contains_arg
)
1082 /* Move parameters from argument registers to temporary register. */
1083 if ((op
& 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
1085 /* Rx must be scratch register r0. */
1086 const int rx_regno
= (op
>> 16) & 31;
1087 /* Ry: Only r3 - r10 are used for parameter passing. */
1088 const int ry_regno
= GET_SRC_REG (op
);
1090 if (rx_regno
== 0 && ry_regno
>= 3 && ry_regno
<= 10)
1092 *r0_contains_arg
= 1;
1099 /* Save a General Purpose Register on stack. */
1101 if ((op
& 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
1102 (op
& 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
1104 /* Rx: Only r3 - r10 are used for parameter passing. */
1105 const int rx_regno
= GET_SRC_REG (op
);
1107 return (rx_regno
>= 3 && rx_regno
<= 10);
1110 /* Save a General Purpose Register on stack via the Frame Pointer. */
1113 ((op
& 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
1114 (op
& 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
1115 (op
& 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
1117 /* Rx: Usually, only r3 - r10 are used for parameter passing.
1118 However, the compiler sometimes uses r0 to hold an argument. */
1119 const int rx_regno
= GET_SRC_REG (op
);
1121 return ((rx_regno
>= 3 && rx_regno
<= 10)
1122 || (rx_regno
== 0 && *r0_contains_arg
));
1125 if ((op
& 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
1127 /* Only f2 - f8 are used for parameter passing. */
1128 const int src_regno
= GET_SRC_REG (op
);
1130 return (src_regno
>= 2 && src_regno
<= 8);
1133 if (framep
&& ((op
& 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
1135 /* Only f2 - f8 are used for parameter passing. */
1136 const int src_regno
= GET_SRC_REG (op
);
1138 return (src_regno
>= 2 && src_regno
<= 8);
1141 /* Not an insn that saves a parameter on stack. */
1145 /* Assuming that INSN is a "bl" instruction located at PC, return
1146 nonzero if the destination of the branch is a "blrl" instruction.
1148 This sequence is sometimes found in certain function prologues.
1149 It allows the function to load the LR register with a value that
1150 they can use to access PIC data using PC-relative offsets. */
1153 bl_to_blrl_insn_p (CORE_ADDR pc
, int insn
, enum bfd_endian byte_order
)
1160 absolute
= (int) ((insn
>> 1) & 1);
1161 immediate
= ((insn
& ~3) << 6) >> 6;
1165 dest
= pc
+ immediate
;
1167 dest_insn
= read_memory_integer (dest
, 4, byte_order
);
1168 if ((dest_insn
& 0xfc00ffff) == 0x4c000021) /* blrl */
1174 /* Return true if OP is a stw or std instruction with
1175 register operands RS and RA and any immediate offset.
1177 If WITH_UPDATE is true, also return true if OP is
1178 a stwu or stdu instruction with the same operands.
1180 Return false otherwise.
1183 store_insn_p (unsigned long op
, unsigned long rs
,
1184 unsigned long ra
, bool with_update
)
1189 if (/* std RS, SIMM(RA) */
1190 ((op
& 0xffff0003) == (rs
| ra
| 0xf8000000)) ||
1191 /* stw RS, SIMM(RA) */
1192 ((op
& 0xffff0000) == (rs
| ra
| 0x90000000)))
1197 if (/* stdu RS, SIMM(RA) */
1198 ((op
& 0xffff0003) == (rs
| ra
| 0xf8000001)) ||
1199 /* stwu RS, SIMM(RA) */
1200 ((op
& 0xffff0000) == (rs
| ra
| 0x94000000)))
1207 /* Masks for decoding a branch-and-link (bl) instruction.
1209 BL_MASK and BL_INSTRUCTION are used in combination with each other.
1210 The former is anded with the opcode in question; if the result of
1211 this masking operation is equal to BL_INSTRUCTION, then the opcode in
1212 question is a ``bl'' instruction.
1214 BL_DISPLACMENT_MASK is anded with the opcode in order to extract
1215 the branch displacement. */
1217 #define BL_MASK 0xfc000001
1218 #define BL_INSTRUCTION 0x48000001
1219 #define BL_DISPLACEMENT_MASK 0x03fffffc
1221 static unsigned long
1222 rs6000_fetch_instruction (struct gdbarch
*gdbarch
, const CORE_ADDR pc
)
1224 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1228 /* Fetch the instruction and convert it to an integer. */
1229 if (target_read_memory (pc
, buf
, 4))
1231 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1236 /* GCC generates several well-known sequences of instructions at the begining
1237 of each function prologue when compiling with -fstack-check. If one of
1238 such sequences starts at START_PC, then return the address of the
1239 instruction immediately past this sequence. Otherwise, return START_PC. */
1242 rs6000_skip_stack_check (struct gdbarch
*gdbarch
, const CORE_ADDR start_pc
)
1244 CORE_ADDR pc
= start_pc
;
1245 unsigned long op
= rs6000_fetch_instruction (gdbarch
, pc
);
1247 /* First possible sequence: A small number of probes.
1248 stw 0, -<some immediate>(1)
1249 [repeat this instruction any (small) number of times]. */
1251 if ((op
& 0xffff0000) == 0x90010000)
1253 while ((op
& 0xffff0000) == 0x90010000)
1256 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1261 /* Second sequence: A probing loop.
1262 addi 12,1,-<some immediate>
1263 lis 0,-<some immediate>
1264 [possibly ori 0,0,<some immediate>]
1268 addi 12,12,-<some immediate>
1271 [possibly one last probe: stw 0,<some immediate>(12)]. */
1275 /* addi 12,1,-<some immediate> */
1276 if ((op
& 0xffff0000) != 0x39810000)
1279 /* lis 0,-<some immediate> */
1281 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1282 if ((op
& 0xffff0000) != 0x3c000000)
1286 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1287 /* [possibly ori 0,0,<some immediate>] */
1288 if ((op
& 0xffff0000) == 0x60000000)
1291 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1294 if (op
!= 0x7c0c0214)
1299 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1300 if (op
!= 0x7c0c0000)
1305 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1306 if ((op
& 0xff9f0001) != 0x41820000)
1309 /* addi 12,12,-<some immediate> */
1311 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1312 if ((op
& 0xffff0000) != 0x398c0000)
1317 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1318 if (op
!= 0x900c0000)
1323 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1324 if ((op
& 0xfc000001) != 0x48000000)
1327 /* [possibly one last probe: stw 0,<some immediate>(12)]. */
1329 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1330 if ((op
& 0xffff0000) == 0x900c0000)
1333 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1336 /* We found a valid stack-check sequence, return the new PC. */
1340 /* Third sequence: No probe; instead, a comparizon between the stack size
1341 limit (saved in a run-time global variable) and the current stack
1344 addi 0,1,-<some immediate>
1345 lis 12,__gnat_stack_limit@ha
1346 lwz 12,__gnat_stack_limit@l(12)
1349 or, with a small variant in the case of a bigger stack frame:
1350 addis 0,1,<some immediate>
1351 addic 0,0,-<some immediate>
1352 lis 12,__gnat_stack_limit@ha
1353 lwz 12,__gnat_stack_limit@l(12)
1358 /* addi 0,1,-<some immediate> */
1359 if ((op
& 0xffff0000) != 0x38010000)
1361 /* small stack frame variant not recognized; try the
1362 big stack frame variant: */
1364 /* addis 0,1,<some immediate> */
1365 if ((op
& 0xffff0000) != 0x3c010000)
1368 /* addic 0,0,-<some immediate> */
1370 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1371 if ((op
& 0xffff0000) != 0x30000000)
1375 /* lis 12,<some immediate> */
1377 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1378 if ((op
& 0xffff0000) != 0x3d800000)
1381 /* lwz 12,<some immediate>(12) */
1383 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1384 if ((op
& 0xffff0000) != 0x818c0000)
1389 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1390 if ((op
& 0xfffffffe) != 0x7c406008)
1393 /* We found a valid stack-check sequence, return the new PC. */
1397 /* No stack check code in our prologue, return the start_pc. */
1401 /* return pc value after skipping a function prologue and also return
1402 information about a function frame.
1404 in struct rs6000_framedata fdata:
1405 - frameless is TRUE, if function does not have a frame.
1406 - nosavedpc is TRUE, if function does not save %pc value in its frame.
1407 - offset is the initial size of this stack frame --- the amount by
1408 which we decrement the sp to allocate the frame.
1409 - saved_gpr is the number of the first saved gpr.
1410 - saved_fpr is the number of the first saved fpr.
1411 - saved_vr is the number of the first saved vr.
1412 - saved_ev is the number of the first saved ev.
1413 - alloca_reg is the number of the register used for alloca() handling.
1415 - gpr_offset is the offset of the first saved gpr from the previous frame.
1416 - fpr_offset is the offset of the first saved fpr from the previous frame.
1417 - vr_offset is the offset of the first saved vr from the previous frame.
1418 - ev_offset is the offset of the first saved ev from the previous frame.
1419 - lr_offset is the offset of the saved lr
1420 - cr_offset is the offset of the saved cr
1421 - vrsave_offset is the offset of the saved vrsave register. */
1424 skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
, CORE_ADDR lim_pc
,
1425 struct rs6000_framedata
*fdata
)
1427 CORE_ADDR orig_pc
= pc
;
1428 CORE_ADDR last_prologue_pc
= pc
;
1429 CORE_ADDR li_found_pc
= 0;
1433 long alloca_reg_offset
= 0;
1434 long vr_saved_offset
= 0;
1440 int vrsave_reg
= -1;
1443 int minimal_toc_loaded
= 0;
1444 int prev_insn_was_prologue_insn
= 1;
1445 int num_skip_non_prologue_insns
= 0;
1446 int r0_contains_arg
= 0;
1447 const struct bfd_arch_info
*arch_info
= gdbarch_bfd_arch_info (gdbarch
);
1448 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1449 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1451 memset (fdata
, 0, sizeof (struct rs6000_framedata
));
1452 fdata
->saved_gpr
= -1;
1453 fdata
->saved_fpr
= -1;
1454 fdata
->saved_vr
= -1;
1455 fdata
->saved_ev
= -1;
1456 fdata
->alloca_reg
= -1;
1457 fdata
->frameless
= 1;
1458 fdata
->nosavedpc
= 1;
1459 fdata
->lr_register
= -1;
1461 pc
= rs6000_skip_stack_check (gdbarch
, pc
);
1467 /* Sometimes it isn't clear if an instruction is a prologue
1468 instruction or not. When we encounter one of these ambiguous
1469 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
1470 Otherwise, we'll assume that it really is a prologue instruction. */
1471 if (prev_insn_was_prologue_insn
)
1472 last_prologue_pc
= pc
;
1474 /* Stop scanning if we've hit the limit. */
1478 prev_insn_was_prologue_insn
= 1;
1480 /* Fetch the instruction and convert it to an integer. */
1481 if (target_read_memory (pc
, buf
, 4))
1483 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1485 if ((op
& 0xfc1fffff) == 0x7c0802a6)
1487 /* Since shared library / PIC code, which needs to get its
1488 address at runtime, can appear to save more than one link
1502 remember just the first one, but skip over additional
1505 lr_reg
= (op
& 0x03e00000) >> 21;
1507 r0_contains_arg
= 0;
1510 else if ((op
& 0xfc1fffff) == 0x7c000026)
1512 cr_reg
= (op
& 0x03e00000) >> 21;
1514 r0_contains_arg
= 0;
1518 else if ((op
& 0xfc1f0000) == 0xd8010000)
1519 { /* stfd Rx,NUM(r1) */
1520 reg
= GET_SRC_REG (op
);
1521 if (fdata
->saved_fpr
== -1 || fdata
->saved_fpr
> reg
)
1523 fdata
->saved_fpr
= reg
;
1524 fdata
->fpr_offset
= SIGNED_SHORT (op
) + offset
;
1529 else if (((op
& 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
1530 (((op
& 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1531 (op
& 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1532 (op
& 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
1535 reg
= GET_SRC_REG (op
);
1536 if ((op
& 0xfc1f0000) == 0xbc010000)
1537 fdata
->gpr_mask
|= ~((1U << reg
) - 1);
1539 fdata
->gpr_mask
|= 1U << reg
;
1540 if (fdata
->saved_gpr
== -1 || fdata
->saved_gpr
> reg
)
1542 fdata
->saved_gpr
= reg
;
1543 if ((op
& 0xfc1f0003) == 0xf8010000)
1545 fdata
->gpr_offset
= SIGNED_SHORT (op
) + offset
;
1550 else if ((op
& 0xffff0000) == 0x3c4c0000
1551 || (op
& 0xffff0000) == 0x3c400000
1552 || (op
& 0xffff0000) == 0x38420000)
1554 /* . 0: addis 2,12,.TOC.-0b@ha
1555 . addi 2,2,.TOC.-0b@l
1559 used by ELFv2 global entry points to set up r2. */
1562 else if (op
== 0x60000000)
1565 /* Allow nops in the prologue, but do not consider them to
1566 be part of the prologue unless followed by other prologue
1568 prev_insn_was_prologue_insn
= 0;
1572 else if ((op
& 0xffff0000) == 0x3c000000)
1573 { /* addis 0,0,NUM, used for >= 32k frames */
1574 fdata
->offset
= (op
& 0x0000ffff) << 16;
1575 fdata
->frameless
= 0;
1576 r0_contains_arg
= 0;
1580 else if ((op
& 0xffff0000) == 0x60000000)
1581 { /* ori 0,0,NUM, 2nd half of >= 32k frames */
1582 fdata
->offset
|= (op
& 0x0000ffff);
1583 fdata
->frameless
= 0;
1584 r0_contains_arg
= 0;
1588 else if (lr_reg
>= 0 &&
1589 ((store_insn_p (op
, lr_reg
, 1, true)) ||
1591 (store_insn_p (op
, lr_reg
,
1592 fdata
->alloca_reg
- tdep
->ppc_gp0_regnum
,
1595 if (store_insn_p (op
, lr_reg
, 1, true))
1596 fdata
->lr_offset
= offset
;
1597 else /* LR save through frame pointer. */
1598 fdata
->lr_offset
= alloca_reg_offset
;
1600 fdata
->nosavedpc
= 0;
1601 /* Invalidate lr_reg, but don't set it to -1.
1602 That would mean that it had never been set. */
1604 if ((op
& 0xfc000003) == 0xf8000000 || /* std */
1605 (op
& 0xfc000000) == 0x90000000) /* stw */
1607 /* Does not update r1, so add displacement to lr_offset. */
1608 fdata
->lr_offset
+= SIGNED_SHORT (op
);
1613 else if (cr_reg
>= 0 &&
1614 (store_insn_p (op
, cr_reg
, 1, true)))
1616 fdata
->cr_offset
= offset
;
1617 /* Invalidate cr_reg, but don't set it to -1.
1618 That would mean that it had never been set. */
1620 if ((op
& 0xfc000003) == 0xf8000000 ||
1621 (op
& 0xfc000000) == 0x90000000)
1623 /* Does not update r1, so add displacement to cr_offset. */
1624 fdata
->cr_offset
+= SIGNED_SHORT (op
);
1629 else if ((op
& 0xfe80ffff) == 0x42800005 && lr_reg
!= -1)
1631 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1632 prediction bits. If the LR has already been saved, we can
1636 else if (op
== 0x48000005)
1643 else if (op
== 0x48000004)
1648 else if ((op
& 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1649 in V.4 -mminimal-toc */
1650 (op
& 0xffff0000) == 0x3bde0000)
1651 { /* addi 30,30,foo@l */
1655 else if ((op
& 0xfc000001) == 0x48000001)
1659 fdata
->frameless
= 0;
1661 /* If the return address has already been saved, we can skip
1662 calls to blrl (for PIC). */
1663 if (lr_reg
!= -1 && bl_to_blrl_insn_p (pc
, op
, byte_order
))
1669 /* Don't skip over the subroutine call if it is not within
1670 the first three instructions of the prologue and either
1671 we have no line table information or the line info tells
1672 us that the subroutine call is not part of the line
1673 associated with the prologue. */
1674 if ((pc
- orig_pc
) > 8)
1676 struct symtab_and_line prologue_sal
= find_pc_line (orig_pc
, 0);
1677 struct symtab_and_line this_sal
= find_pc_line (pc
, 0);
1679 if ((prologue_sal
.line
== 0)
1680 || (prologue_sal
.line
!= this_sal
.line
))
1684 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
1686 /* At this point, make sure this is not a trampoline
1687 function (a function that simply calls another functions,
1688 and nothing else). If the next is not a nop, this branch
1689 was part of the function prologue. */
1691 if (op
== 0x4def7b82 || op
== 0) /* crorc 15, 15, 15 */
1692 break; /* Don't skip over
1698 /* update stack pointer */
1699 else if ((op
& 0xfc1f0000) == 0x94010000)
1700 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
1701 fdata
->frameless
= 0;
1702 fdata
->offset
= SIGNED_SHORT (op
);
1703 offset
= fdata
->offset
;
1706 else if ((op
& 0xfc1f07fa) == 0x7c01016a)
1707 { /* stwux rX,r1,rY || stdux rX,r1,rY */
1708 /* No way to figure out what r1 is going to be. */
1709 fdata
->frameless
= 0;
1710 offset
= fdata
->offset
;
1713 else if ((op
& 0xfc1f0003) == 0xf8010001)
1714 { /* stdu rX,NUM(r1) */
1715 fdata
->frameless
= 0;
1716 fdata
->offset
= SIGNED_SHORT (op
& ~3UL);
1717 offset
= fdata
->offset
;
1720 else if ((op
& 0xffff0000) == 0x38210000)
1721 { /* addi r1,r1,SIMM */
1722 fdata
->frameless
= 0;
1723 fdata
->offset
+= SIGNED_SHORT (op
);
1724 offset
= fdata
->offset
;
1727 /* Load up minimal toc pointer. Do not treat an epilogue restore
1728 of r31 as a minimal TOC load. */
1729 else if (((op
>> 22) == 0x20f || /* l r31,... or l r30,... */
1730 (op
>> 22) == 0x3af) /* ld r31,... or ld r30,... */
1732 && !minimal_toc_loaded
)
1734 minimal_toc_loaded
= 1;
1737 /* move parameters from argument registers to local variable
1740 else if ((op
& 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1741 (((op
>> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1742 (((op
>> 21) & 31) <= 10) &&
1743 ((long) ((op
>> 16) & 31)
1744 >= fdata
->saved_gpr
)) /* Rx: local var reg */
1748 /* store parameters in stack */
1750 /* Move parameters from argument registers to temporary register. */
1751 else if (store_param_on_stack_p (op
, framep
, &r0_contains_arg
))
1755 /* Set up frame pointer */
1757 else if (op
== 0x603d0000) /* oril r29, r1, 0x0 */
1759 fdata
->frameless
= 0;
1761 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 29);
1762 alloca_reg_offset
= offset
;
1765 /* Another way to set up the frame pointer. */
1767 else if (op
== 0x603f0000 /* oril r31, r1, 0x0 */
1768 || op
== 0x7c3f0b78)
1770 fdata
->frameless
= 0;
1772 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 31);
1773 alloca_reg_offset
= offset
;
1776 /* Another way to set up the frame pointer. */
1778 else if ((op
& 0xfc1fffff) == 0x38010000)
1779 { /* addi rX, r1, 0x0 */
1780 fdata
->frameless
= 0;
1782 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
1783 + ((op
& ~0x38010000) >> 21));
1784 alloca_reg_offset
= offset
;
1787 /* AltiVec related instructions. */
1788 /* Store the vrsave register (spr 256) in another register for
1789 later manipulation, or load a register into the vrsave
1790 register. 2 instructions are used: mfvrsave and
1791 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1792 and mtspr SPR256, Rn. */
1793 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1794 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1795 else if ((op
& 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1797 vrsave_reg
= GET_SRC_REG (op
);
1800 else if ((op
& 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1804 /* Store the register where vrsave was saved to onto the stack:
1805 rS is the register where vrsave was stored in a previous
1807 /* 100100 sssss 00001 dddddddd dddddddd */
1808 else if ((op
& 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1810 if (vrsave_reg
== GET_SRC_REG (op
))
1812 fdata
->vrsave_offset
= SIGNED_SHORT (op
) + offset
;
1817 /* Compute the new value of vrsave, by modifying the register
1818 where vrsave was saved to. */
1819 else if (((op
& 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1820 || ((op
& 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1824 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1825 in a pair of insns to save the vector registers on the
1827 /* 001110 00000 00000 iiii iiii iiii iiii */
1828 /* 001110 01110 00000 iiii iiii iiii iiii */
1829 else if ((op
& 0xffff0000) == 0x38000000 /* li r0, SIMM */
1830 || (op
& 0xffff0000) == 0x39c00000) /* li r14, SIMM */
1832 if ((op
& 0xffff0000) == 0x38000000)
1833 r0_contains_arg
= 0;
1835 vr_saved_offset
= SIGNED_SHORT (op
);
1837 /* This insn by itself is not part of the prologue, unless
1838 if part of the pair of insns mentioned above. So do not
1839 record this insn as part of the prologue yet. */
1840 prev_insn_was_prologue_insn
= 0;
1842 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1843 /* 011111 sssss 11111 00000 00111001110 */
1844 else if ((op
& 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1846 if (pc
== (li_found_pc
+ 4))
1848 vr_reg
= GET_SRC_REG (op
);
1849 /* If this is the first vector reg to be saved, or if
1850 it has a lower number than others previously seen,
1851 reupdate the frame info. */
1852 if (fdata
->saved_vr
== -1 || fdata
->saved_vr
> vr_reg
)
1854 fdata
->saved_vr
= vr_reg
;
1855 fdata
->vr_offset
= vr_saved_offset
+ offset
;
1857 vr_saved_offset
= -1;
1862 /* End AltiVec related instructions. */
1864 /* Start BookE related instructions. */
1865 /* Store gen register S at (r31+uimm).
1866 Any register less than r13 is volatile, so we don't care. */
1867 /* 000100 sssss 11111 iiiii 01100100001 */
1868 else if (arch_info
->mach
== bfd_mach_ppc_e500
1869 && (op
& 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
1871 if ((op
& 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
1874 ev_reg
= GET_SRC_REG (op
);
1875 imm
= (op
>> 11) & 0x1f;
1876 ev_offset
= imm
* 8;
1877 /* If this is the first vector reg to be saved, or if
1878 it has a lower number than others previously seen,
1879 reupdate the frame info. */
1880 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1882 fdata
->saved_ev
= ev_reg
;
1883 fdata
->ev_offset
= ev_offset
+ offset
;
1888 /* Store gen register rS at (r1+rB). */
1889 /* 000100 sssss 00001 bbbbb 01100100000 */
1890 else if (arch_info
->mach
== bfd_mach_ppc_e500
1891 && (op
& 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1893 if (pc
== (li_found_pc
+ 4))
1895 ev_reg
= GET_SRC_REG (op
);
1896 /* If this is the first vector reg to be saved, or if
1897 it has a lower number than others previously seen,
1898 reupdate the frame info. */
1899 /* We know the contents of rB from the previous instruction. */
1900 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1902 fdata
->saved_ev
= ev_reg
;
1903 fdata
->ev_offset
= vr_saved_offset
+ offset
;
1905 vr_saved_offset
= -1;
1911 /* Store gen register r31 at (rA+uimm). */
1912 /* 000100 11111 aaaaa iiiii 01100100001 */
1913 else if (arch_info
->mach
== bfd_mach_ppc_e500
1914 && (op
& 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
1916 /* Wwe know that the source register is 31 already, but
1917 it can't hurt to compute it. */
1918 ev_reg
= GET_SRC_REG (op
);
1919 ev_offset
= ((op
>> 11) & 0x1f) * 8;
1920 /* If this is the first vector reg to be saved, or if
1921 it has a lower number than others previously seen,
1922 reupdate the frame info. */
1923 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1925 fdata
->saved_ev
= ev_reg
;
1926 fdata
->ev_offset
= ev_offset
+ offset
;
1931 /* Store gen register S at (r31+r0).
1932 Store param on stack when offset from SP bigger than 4 bytes. */
1933 /* 000100 sssss 11111 00000 01100100000 */
1934 else if (arch_info
->mach
== bfd_mach_ppc_e500
1935 && (op
& 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
1937 if (pc
== (li_found_pc
+ 4))
1939 if ((op
& 0x03e00000) >= 0x01a00000)
1941 ev_reg
= GET_SRC_REG (op
);
1942 /* If this is the first vector reg to be saved, or if
1943 it has a lower number than others previously seen,
1944 reupdate the frame info. */
1945 /* We know the contents of r0 from the previous
1947 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1949 fdata
->saved_ev
= ev_reg
;
1950 fdata
->ev_offset
= vr_saved_offset
+ offset
;
1954 vr_saved_offset
= -1;
1959 /* End BookE related instructions. */
1963 unsigned int all_mask
= ~((1U << fdata
->saved_gpr
) - 1);
1965 /* Not a recognized prologue instruction.
1966 Handle optimizer code motions into the prologue by continuing
1967 the search if we have no valid frame yet or if the return
1968 address is not yet saved in the frame. Also skip instructions
1969 if some of the GPRs expected to be saved are not yet saved. */
1970 if (fdata
->frameless
== 0 && fdata
->nosavedpc
== 0
1971 && (fdata
->gpr_mask
& all_mask
) == all_mask
)
1974 if (op
== 0x4e800020 /* blr */
1975 || op
== 0x4e800420) /* bctr */
1976 /* Do not scan past epilogue in frameless functions or
1979 if ((op
& 0xf4000000) == 0x40000000) /* bxx */
1980 /* Never skip branches. */
1983 if (num_skip_non_prologue_insns
++ > max_skip_non_prologue_insns
)
1984 /* Do not scan too many insns, scanning insns is expensive with
1988 /* Continue scanning. */
1989 prev_insn_was_prologue_insn
= 0;
1995 /* I have problems with skipping over __main() that I need to address
1996 * sometime. Previously, I used to use misc_function_vector which
1997 * didn't work as well as I wanted to be. -MGO */
1999 /* If the first thing after skipping a prolog is a branch to a function,
2000 this might be a call to an initializer in main(), introduced by gcc2.
2001 We'd like to skip over it as well. Fortunately, xlc does some extra
2002 work before calling a function right after a prologue, thus we can
2003 single out such gcc2 behaviour. */
2006 if ((op
& 0xfc000001) == 0x48000001)
2007 { /* bl foo, an initializer function? */
2008 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
2010 if (op
== 0x4def7b82)
2011 { /* cror 0xf, 0xf, 0xf (nop) */
2013 /* Check and see if we are in main. If so, skip over this
2014 initializer function as well. */
2016 tmp
= find_pc_misc_function (pc
);
2018 && strcmp (misc_function_vector
[tmp
].name
, main_name ()) == 0)
2024 if (pc
== lim_pc
&& lr_reg
>= 0)
2025 fdata
->lr_register
= lr_reg
;
2027 fdata
->offset
= -fdata
->offset
;
2028 return last_prologue_pc
;
2032 rs6000_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2034 struct rs6000_framedata frame
;
2035 CORE_ADDR limit_pc
, func_addr
, func_end_addr
= 0;
2037 /* See if we can determine the end of the prologue via the symbol table.
2038 If so, then return either PC, or the PC after the prologue, whichever
2040 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end_addr
))
2042 CORE_ADDR post_prologue_pc
2043 = skip_prologue_using_sal (gdbarch
, func_addr
);
2044 if (post_prologue_pc
!= 0)
2045 return std::max (pc
, post_prologue_pc
);
2048 /* Can't determine prologue from the symbol table, need to examine
2051 /* Find an upper limit on the function prologue using the debug
2052 information. If the debug information could not be used to provide
2053 that bound, then use an arbitrary large number as the upper bound. */
2054 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
2056 limit_pc
= pc
+ 100; /* Magic. */
2058 /* Do not allow limit_pc to be past the function end, if we know
2059 where that end is... */
2060 if (func_end_addr
&& limit_pc
> func_end_addr
)
2061 limit_pc
= func_end_addr
;
2063 pc
= skip_prologue (gdbarch
, pc
, limit_pc
, &frame
);
2067 /* When compiling for EABI, some versions of GCC emit a call to __eabi
2068 in the prologue of main().
2070 The function below examines the code pointed at by PC and checks to
2071 see if it corresponds to a call to __eabi. If so, it returns the
2072 address of the instruction following that call. Otherwise, it simply
2076 rs6000_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2078 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2082 if (target_read_memory (pc
, buf
, 4))
2084 op
= extract_unsigned_integer (buf
, 4, byte_order
);
2086 if ((op
& BL_MASK
) == BL_INSTRUCTION
)
2088 CORE_ADDR displ
= op
& BL_DISPLACEMENT_MASK
;
2089 CORE_ADDR call_dest
= pc
+ 4 + displ
;
2090 struct bound_minimal_symbol s
= lookup_minimal_symbol_by_pc (call_dest
);
2092 /* We check for ___eabi (three leading underscores) in addition
2093 to __eabi in case the GCC option "-fleading-underscore" was
2094 used to compile the program. */
2095 if (s
.minsym
!= NULL
2096 && MSYMBOL_LINKAGE_NAME (s
.minsym
) != NULL
2097 && (strcmp (MSYMBOL_LINKAGE_NAME (s
.minsym
), "__eabi") == 0
2098 || strcmp (MSYMBOL_LINKAGE_NAME (s
.minsym
), "___eabi") == 0))
2104 /* All the ABI's require 16 byte alignment. */
2106 rs6000_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2108 return (addr
& -16);
2111 /* Return whether handle_inferior_event() should proceed through code
2112 starting at PC in function NAME when stepping.
2114 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
2115 handle memory references that are too distant to fit in instructions
2116 generated by the compiler. For example, if 'foo' in the following
2121 is greater than 32767, the linker might replace the lwz with a branch to
2122 somewhere in @FIX1 that does the load in 2 instructions and then branches
2123 back to where execution should continue.
2125 GDB should silently step over @FIX code, just like AIX dbx does.
2126 Unfortunately, the linker uses the "b" instruction for the
2127 branches, meaning that the link register doesn't get set.
2128 Therefore, GDB's usual step_over_function () mechanism won't work.
2130 Instead, use the gdbarch_skip_trampoline_code and
2131 gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past
2135 rs6000_in_solib_return_trampoline (struct gdbarch
*gdbarch
,
2136 CORE_ADDR pc
, const char *name
)
2138 return name
&& startswith (name
, "@FIX");
2141 /* Skip code that the user doesn't want to see when stepping:
2143 1. Indirect function calls use a piece of trampoline code to do context
2144 switching, i.e. to set the new TOC table. Skip such code if we are on
2145 its first instruction (as when we have single-stepped to here).
2147 2. Skip shared library trampoline code (which is different from
2148 indirect function call trampolines).
2150 3. Skip bigtoc fixup code.
2152 Result is desired PC to step until, or NULL if we are not in
2153 code that should be skipped. */
2156 rs6000_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
2158 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2159 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2160 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2161 unsigned int ii
, op
;
2163 CORE_ADDR solib_target_pc
;
2164 struct bound_minimal_symbol msymbol
;
2166 static unsigned trampoline_code
[] =
2168 0x800b0000, /* l r0,0x0(r11) */
2169 0x90410014, /* st r2,0x14(r1) */
2170 0x7c0903a6, /* mtctr r0 */
2171 0x804b0004, /* l r2,0x4(r11) */
2172 0x816b0008, /* l r11,0x8(r11) */
2173 0x4e800420, /* bctr */
2174 0x4e800020, /* br */
2178 /* Check for bigtoc fixup code. */
2179 msymbol
= lookup_minimal_symbol_by_pc (pc
);
2181 && rs6000_in_solib_return_trampoline (gdbarch
, pc
,
2182 MSYMBOL_LINKAGE_NAME (msymbol
.minsym
)))
2184 /* Double-check that the third instruction from PC is relative "b". */
2185 op
= read_memory_integer (pc
+ 8, 4, byte_order
);
2186 if ((op
& 0xfc000003) == 0x48000000)
2188 /* Extract bits 6-29 as a signed 24-bit relative word address and
2189 add it to the containing PC. */
2190 rel
= ((int)(op
<< 6) >> 6);
2191 return pc
+ 8 + rel
;
2195 /* If pc is in a shared library trampoline, return its target. */
2196 solib_target_pc
= find_solib_trampoline_target (frame
, pc
);
2197 if (solib_target_pc
)
2198 return solib_target_pc
;
2200 for (ii
= 0; trampoline_code
[ii
]; ++ii
)
2202 op
= read_memory_integer (pc
+ (ii
* 4), 4, byte_order
);
2203 if (op
!= trampoline_code
[ii
])
2206 ii
= get_frame_register_unsigned (frame
, 11); /* r11 holds destination
2208 pc
= read_memory_unsigned_integer (ii
, tdep
->wordsize
, byte_order
);
2212 /* ISA-specific vector types. */
2214 static struct type
*
2215 rs6000_builtin_type_vec64 (struct gdbarch
*gdbarch
)
2217 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2219 if (!tdep
->ppc_builtin_type_vec64
)
2221 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2223 /* The type we're building is this: */
2225 union __gdb_builtin_type_vec64
2229 int32_t v2_int32
[2];
2230 int16_t v4_int16
[4];
2237 t
= arch_composite_type (gdbarch
,
2238 "__ppc_builtin_type_vec64", TYPE_CODE_UNION
);
2239 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2240 append_composite_type_field (t
, "v2_float",
2241 init_vector_type (bt
->builtin_float
, 2));
2242 append_composite_type_field (t
, "v2_int32",
2243 init_vector_type (bt
->builtin_int32
, 2));
2244 append_composite_type_field (t
, "v4_int16",
2245 init_vector_type (bt
->builtin_int16
, 4));
2246 append_composite_type_field (t
, "v8_int8",
2247 init_vector_type (bt
->builtin_int8
, 8));
2249 TYPE_VECTOR (t
) = 1;
2250 TYPE_NAME (t
) = "ppc_builtin_type_vec64";
2251 tdep
->ppc_builtin_type_vec64
= t
;
2254 return tdep
->ppc_builtin_type_vec64
;
2257 /* Vector 128 type. */
2259 static struct type
*
2260 rs6000_builtin_type_vec128 (struct gdbarch
*gdbarch
)
2262 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2264 if (!tdep
->ppc_builtin_type_vec128
)
2266 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2268 /* The type we're building is this
2270 type = union __ppc_builtin_type_vec128 {
2272 double v2_double[2];
2274 int32_t v4_int32[4];
2275 int16_t v8_int16[8];
2276 int8_t v16_int8[16];
2282 t
= arch_composite_type (gdbarch
,
2283 "__ppc_builtin_type_vec128", TYPE_CODE_UNION
);
2284 append_composite_type_field (t
, "uint128", bt
->builtin_uint128
);
2285 append_composite_type_field (t
, "v2_double",
2286 init_vector_type (bt
->builtin_double
, 2));
2287 append_composite_type_field (t
, "v4_float",
2288 init_vector_type (bt
->builtin_float
, 4));
2289 append_composite_type_field (t
, "v4_int32",
2290 init_vector_type (bt
->builtin_int32
, 4));
2291 append_composite_type_field (t
, "v8_int16",
2292 init_vector_type (bt
->builtin_int16
, 8));
2293 append_composite_type_field (t
, "v16_int8",
2294 init_vector_type (bt
->builtin_int8
, 16));
2296 TYPE_VECTOR (t
) = 1;
2297 TYPE_NAME (t
) = "ppc_builtin_type_vec128";
2298 tdep
->ppc_builtin_type_vec128
= t
;
2301 return tdep
->ppc_builtin_type_vec128
;
2304 /* Return the name of register number REGNO, or the empty string if it
2305 is an anonymous register. */
2308 rs6000_register_name (struct gdbarch
*gdbarch
, int regno
)
2310 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2312 /* The upper half "registers" have names in the XML description,
2313 but we present only the low GPRs and the full 64-bit registers
2315 if (tdep
->ppc_ev0_upper_regnum
>= 0
2316 && tdep
->ppc_ev0_upper_regnum
<= regno
2317 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
2320 /* Hide the upper halves of the vs0~vs31 registers. */
2321 if (tdep
->ppc_vsr0_regnum
>= 0
2322 && tdep
->ppc_vsr0_upper_regnum
<= regno
2323 && regno
< tdep
->ppc_vsr0_upper_regnum
+ ppc_num_gprs
)
2326 /* Check if the SPE pseudo registers are available. */
2327 if (IS_SPE_PSEUDOREG (tdep
, regno
))
2329 static const char *const spe_regnames
[] = {
2330 "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7",
2331 "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15",
2332 "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23",
2333 "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31",
2335 return spe_regnames
[regno
- tdep
->ppc_ev0_regnum
];
2338 /* Check if the decimal128 pseudo-registers are available. */
2339 if (IS_DFP_PSEUDOREG (tdep
, regno
))
2341 static const char *const dfp128_regnames
[] = {
2342 "dl0", "dl1", "dl2", "dl3",
2343 "dl4", "dl5", "dl6", "dl7",
2344 "dl8", "dl9", "dl10", "dl11",
2345 "dl12", "dl13", "dl14", "dl15"
2347 return dfp128_regnames
[regno
- tdep
->ppc_dl0_regnum
];
2350 /* Check if this is a VSX pseudo-register. */
2351 if (IS_VSX_PSEUDOREG (tdep
, regno
))
2353 static const char *const vsx_regnames
[] = {
2354 "vs0", "vs1", "vs2", "vs3", "vs4", "vs5", "vs6", "vs7",
2355 "vs8", "vs9", "vs10", "vs11", "vs12", "vs13", "vs14",
2356 "vs15", "vs16", "vs17", "vs18", "vs19", "vs20", "vs21",
2357 "vs22", "vs23", "vs24", "vs25", "vs26", "vs27", "vs28",
2358 "vs29", "vs30", "vs31", "vs32", "vs33", "vs34", "vs35",
2359 "vs36", "vs37", "vs38", "vs39", "vs40", "vs41", "vs42",
2360 "vs43", "vs44", "vs45", "vs46", "vs47", "vs48", "vs49",
2361 "vs50", "vs51", "vs52", "vs53", "vs54", "vs55", "vs56",
2362 "vs57", "vs58", "vs59", "vs60", "vs61", "vs62", "vs63"
2364 return vsx_regnames
[regno
- tdep
->ppc_vsr0_regnum
];
2367 /* Check if the this is a Extended FP pseudo-register. */
2368 if (IS_EFP_PSEUDOREG (tdep
, regno
))
2370 static const char *const efpr_regnames
[] = {
2371 "f32", "f33", "f34", "f35", "f36", "f37", "f38",
2372 "f39", "f40", "f41", "f42", "f43", "f44", "f45",
2373 "f46", "f47", "f48", "f49", "f50", "f51",
2374 "f52", "f53", "f54", "f55", "f56", "f57",
2375 "f58", "f59", "f60", "f61", "f62", "f63"
2377 return efpr_regnames
[regno
- tdep
->ppc_efpr0_regnum
];
2380 return tdesc_register_name (gdbarch
, regno
);
2383 /* Return the GDB type object for the "standard" data type of data in
2386 static struct type
*
2387 rs6000_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2389 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2391 /* These are the only pseudo-registers we support. */
2392 gdb_assert (IS_SPE_PSEUDOREG (tdep
, regnum
)
2393 || IS_DFP_PSEUDOREG (tdep
, regnum
)
2394 || IS_VSX_PSEUDOREG (tdep
, regnum
)
2395 || IS_EFP_PSEUDOREG (tdep
, regnum
));
2397 /* These are the e500 pseudo-registers. */
2398 if (IS_SPE_PSEUDOREG (tdep
, regnum
))
2399 return rs6000_builtin_type_vec64 (gdbarch
);
2400 else if (IS_DFP_PSEUDOREG (tdep
, regnum
))
2401 /* PPC decimal128 pseudo-registers. */
2402 return builtin_type (gdbarch
)->builtin_declong
;
2403 else if (IS_VSX_PSEUDOREG (tdep
, regnum
))
2404 /* POWER7 VSX pseudo-registers. */
2405 return rs6000_builtin_type_vec128 (gdbarch
);
2407 /* POWER7 Extended FP pseudo-registers. */
2408 return builtin_type (gdbarch
)->builtin_double
;
2411 /* Is REGNUM a member of REGGROUP? */
2413 rs6000_pseudo_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2414 struct reggroup
*group
)
2416 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2418 /* These are the only pseudo-registers we support. */
2419 gdb_assert (IS_SPE_PSEUDOREG (tdep
, regnum
)
2420 || IS_DFP_PSEUDOREG (tdep
, regnum
)
2421 || IS_VSX_PSEUDOREG (tdep
, regnum
)
2422 || IS_EFP_PSEUDOREG (tdep
, regnum
));
2424 /* These are the e500 pseudo-registers or the POWER7 VSX registers. */
2425 if (IS_SPE_PSEUDOREG (tdep
, regnum
) || IS_VSX_PSEUDOREG (tdep
, regnum
))
2426 return group
== all_reggroup
|| group
== vector_reggroup
;
2428 /* PPC decimal128 or Extended FP pseudo-registers. */
2429 return group
== all_reggroup
|| group
== float_reggroup
;
2432 /* The register format for RS/6000 floating point registers is always
2433 double, we need a conversion if the memory format is float. */
2436 rs6000_convert_register_p (struct gdbarch
*gdbarch
, int regnum
,
2439 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2441 return (tdep
->ppc_fp0_regnum
>= 0
2442 && regnum
>= tdep
->ppc_fp0_regnum
2443 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
2444 && TYPE_CODE (type
) == TYPE_CODE_FLT
2445 && TYPE_LENGTH (type
)
2446 != TYPE_LENGTH (builtin_type (gdbarch
)->builtin_double
));
2450 rs6000_register_to_value (struct frame_info
*frame
,
2454 int *optimizedp
, int *unavailablep
)
2456 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2457 gdb_byte from
[PPC_MAX_REGISTER_SIZE
];
2459 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
2461 if (!get_frame_register_bytes (frame
, regnum
, 0,
2462 register_size (gdbarch
, regnum
),
2463 from
, optimizedp
, unavailablep
))
2466 target_float_convert (from
, builtin_type (gdbarch
)->builtin_double
,
2468 *optimizedp
= *unavailablep
= 0;
2473 rs6000_value_to_register (struct frame_info
*frame
,
2476 const gdb_byte
*from
)
2478 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2479 gdb_byte to
[PPC_MAX_REGISTER_SIZE
];
2481 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
2483 target_float_convert (from
, type
,
2484 to
, builtin_type (gdbarch
)->builtin_double
);
2485 put_frame_register (frame
, regnum
, to
);
2488 /* The type of a function that moves the value of REG between CACHE
2489 or BUF --- in either direction. */
2490 typedef enum register_status (*move_ev_register_func
) (struct regcache
*,
2493 /* Move SPE vector register values between a 64-bit buffer and the two
2494 32-bit raw register halves in a regcache. This function handles
2495 both splitting a 64-bit value into two 32-bit halves, and joining
2496 two halves into a whole 64-bit value, depending on the function
2497 passed as the MOVE argument.
2499 EV_REG must be the number of an SPE evN vector register --- a
2500 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2503 Call MOVE once for each 32-bit half of that register, passing
2504 REGCACHE, the number of the raw register corresponding to that
2505 half, and the address of the appropriate half of BUFFER.
2507 For example, passing 'regcache_raw_read' as the MOVE function will
2508 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2509 'regcache_raw_supply' will supply the contents of BUFFER to the
2510 appropriate pair of raw registers in REGCACHE.
2512 You may need to cast away some 'const' qualifiers when passing
2513 MOVE, since this function can't tell at compile-time which of
2514 REGCACHE or BUFFER is acting as the source of the data. If C had
2515 co-variant type qualifiers, ... */
2517 static enum register_status
2518 e500_move_ev_register (move_ev_register_func move
,
2519 struct regcache
*regcache
, int ev_reg
, void *buffer
)
2521 struct gdbarch
*arch
= regcache
->arch ();
2522 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
2524 gdb_byte
*byte_buffer
= (gdb_byte
*) buffer
;
2525 enum register_status status
;
2527 gdb_assert (IS_SPE_PSEUDOREG (tdep
, ev_reg
));
2529 reg_index
= ev_reg
- tdep
->ppc_ev0_regnum
;
2531 if (gdbarch_byte_order (arch
) == BFD_ENDIAN_BIG
)
2533 status
= move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2535 if (status
== REG_VALID
)
2536 status
= move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
,
2541 status
= move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
, byte_buffer
);
2542 if (status
== REG_VALID
)
2543 status
= move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2550 static enum register_status
2551 do_regcache_raw_write (struct regcache
*regcache
, int regnum
, void *buffer
)
2553 regcache
->raw_write (regnum
, (const gdb_byte
*) buffer
);
2558 static enum register_status
2559 e500_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2560 int ev_reg
, gdb_byte
*buffer
)
2562 struct gdbarch
*arch
= regcache
->arch ();
2563 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
2565 enum register_status status
;
2567 gdb_assert (IS_SPE_PSEUDOREG (tdep
, ev_reg
));
2569 reg_index
= ev_reg
- tdep
->ppc_ev0_regnum
;
2571 if (gdbarch_byte_order (arch
) == BFD_ENDIAN_BIG
)
2573 status
= regcache
->raw_read (tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2575 if (status
== REG_VALID
)
2576 status
= regcache
->raw_read (tdep
->ppc_gp0_regnum
+ reg_index
,
2581 status
= regcache
->raw_read (tdep
->ppc_gp0_regnum
+ reg_index
, buffer
);
2582 if (status
== REG_VALID
)
2583 status
= regcache
->raw_read (tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2592 e500_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2593 int reg_nr
, const gdb_byte
*buffer
)
2595 e500_move_ev_register (do_regcache_raw_write
, regcache
,
2596 reg_nr
, (void *) buffer
);
2599 /* Read method for DFP pseudo-registers. */
2600 static enum register_status
2601 dfp_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2602 int reg_nr
, gdb_byte
*buffer
)
2604 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2605 int reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2606 enum register_status status
;
2608 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2610 /* Read two FP registers to form a whole dl register. */
2611 status
= regcache
->raw_read (tdep
->ppc_fp0_regnum
+
2612 2 * reg_index
, buffer
);
2613 if (status
== REG_VALID
)
2614 status
= regcache
->raw_read (tdep
->ppc_fp0_regnum
+
2615 2 * reg_index
+ 1, buffer
+ 8);
2619 status
= regcache
->raw_read (tdep
->ppc_fp0_regnum
+
2620 2 * reg_index
+ 1, buffer
);
2621 if (status
== REG_VALID
)
2622 status
= regcache
->raw_read (tdep
->ppc_fp0_regnum
+
2623 2 * reg_index
, buffer
+ 8);
2629 /* Write method for DFP pseudo-registers. */
2631 dfp_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2632 int reg_nr
, const gdb_byte
*buffer
)
2634 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2635 int reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2637 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2639 /* Write each half of the dl register into a separate
2641 regcache
->raw_write (tdep
->ppc_fp0_regnum
+
2642 2 * reg_index
, buffer
);
2643 regcache
->raw_write (tdep
->ppc_fp0_regnum
+
2644 2 * reg_index
+ 1, buffer
+ 8);
2648 regcache
->raw_write (tdep
->ppc_fp0_regnum
+
2649 2 * reg_index
+ 1, buffer
);
2650 regcache
->raw_write (tdep
->ppc_fp0_regnum
+
2651 2 * reg_index
, buffer
+ 8);
2655 /* Read method for POWER7 VSX pseudo-registers. */
2656 static enum register_status
2657 vsx_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2658 int reg_nr
, gdb_byte
*buffer
)
2660 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2661 int reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2662 enum register_status status
;
2664 /* Read the portion that overlaps the VMX registers. */
2666 status
= regcache
->raw_read (tdep
->ppc_vr0_regnum
+
2667 reg_index
- 32, buffer
);
2669 /* Read the portion that overlaps the FPR registers. */
2670 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2672 status
= regcache
->raw_read (tdep
->ppc_fp0_regnum
+
2674 if (status
== REG_VALID
)
2675 status
= regcache
->raw_read (tdep
->ppc_vsr0_upper_regnum
+
2676 reg_index
, buffer
+ 8);
2680 status
= regcache
->raw_read (tdep
->ppc_fp0_regnum
+
2681 reg_index
, buffer
+ 8);
2682 if (status
== REG_VALID
)
2683 status
= regcache
->raw_read (tdep
->ppc_vsr0_upper_regnum
+
2690 /* Write method for POWER7 VSX pseudo-registers. */
2692 vsx_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2693 int reg_nr
, const gdb_byte
*buffer
)
2695 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2696 int reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2698 /* Write the portion that overlaps the VMX registers. */
2700 regcache
->raw_write (tdep
->ppc_vr0_regnum
+
2701 reg_index
- 32, buffer
);
2703 /* Write the portion that overlaps the FPR registers. */
2704 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2706 regcache
->raw_write (tdep
->ppc_fp0_regnum
+
2708 regcache
->raw_write (tdep
->ppc_vsr0_upper_regnum
+
2709 reg_index
, buffer
+ 8);
2713 regcache
->raw_write (tdep
->ppc_fp0_regnum
+
2714 reg_index
, buffer
+ 8);
2715 regcache
->raw_write (tdep
->ppc_vsr0_upper_regnum
+
2720 /* Read method for POWER7 Extended FP pseudo-registers. */
2721 static enum register_status
2722 efpr_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2723 int reg_nr
, gdb_byte
*buffer
)
2725 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2726 int reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
2727 int offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 0 : 8;
2729 /* Read the portion that overlaps the VMX register. */
2730 return regcache
->raw_read_part (tdep
->ppc_vr0_regnum
+ reg_index
,
2731 offset
, register_size (gdbarch
, reg_nr
),
2735 /* Write method for POWER7 Extended FP pseudo-registers. */
2737 efpr_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2738 int reg_nr
, const gdb_byte
*buffer
)
2740 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2741 int reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
2742 int offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 0 : 8;
2744 /* Write the portion that overlaps the VMX register. */
2745 regcache
->raw_write_part (tdep
->ppc_vr0_regnum
+ reg_index
, offset
,
2746 register_size (gdbarch
, reg_nr
), buffer
);
2749 static enum register_status
2750 rs6000_pseudo_register_read (struct gdbarch
*gdbarch
,
2751 readable_regcache
*regcache
,
2752 int reg_nr
, gdb_byte
*buffer
)
2754 struct gdbarch
*regcache_arch
= regcache
->arch ();
2755 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2757 gdb_assert (regcache_arch
== gdbarch
);
2759 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2760 return e500_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2761 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2762 return dfp_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2763 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2764 return vsx_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2765 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
2766 return efpr_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2768 internal_error (__FILE__
, __LINE__
,
2769 _("rs6000_pseudo_register_read: "
2770 "called on unexpected register '%s' (%d)"),
2771 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2775 rs6000_pseudo_register_write (struct gdbarch
*gdbarch
,
2776 struct regcache
*regcache
,
2777 int reg_nr
, const gdb_byte
*buffer
)
2779 struct gdbarch
*regcache_arch
= regcache
->arch ();
2780 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2782 gdb_assert (regcache_arch
== gdbarch
);
2784 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2785 e500_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2786 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2787 dfp_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2788 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2789 vsx_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2790 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
2791 efpr_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2793 internal_error (__FILE__
, __LINE__
,
2794 _("rs6000_pseudo_register_write: "
2795 "called on unexpected register '%s' (%d)"),
2796 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2800 rs6000_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
2801 struct agent_expr
*ax
, int reg_nr
)
2803 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2804 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2806 int reg_index
= reg_nr
- tdep
->ppc_ev0_regnum
;
2807 ax_reg_mask (ax
, tdep
->ppc_gp0_regnum
+ reg_index
);
2808 ax_reg_mask (ax
, tdep
->ppc_ev0_upper_regnum
+ reg_index
);
2810 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2812 int reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2813 ax_reg_mask (ax
, tdep
->ppc_fp0_regnum
+ 2 * reg_index
);
2814 ax_reg_mask (ax
, tdep
->ppc_fp0_regnum
+ 2 * reg_index
+ 1);
2816 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2818 int reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2821 ax_reg_mask (ax
, tdep
->ppc_vr0_regnum
+ reg_index
- 32);
2825 ax_reg_mask (ax
, tdep
->ppc_fp0_regnum
+ reg_index
);
2826 ax_reg_mask (ax
, tdep
->ppc_vsr0_upper_regnum
+ reg_index
);
2829 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
2831 int reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
2832 ax_reg_mask (ax
, tdep
->ppc_vr0_regnum
+ reg_index
);
2835 internal_error (__FILE__
, __LINE__
,
2836 _("rs6000_pseudo_register_collect: "
2837 "called on unexpected register '%s' (%d)"),
2838 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2844 rs6000_gen_return_address (struct gdbarch
*gdbarch
,
2845 struct agent_expr
*ax
, struct axs_value
*value
,
2848 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2849 value
->type
= register_type (gdbarch
, tdep
->ppc_lr_regnum
);
2850 value
->kind
= axs_lvalue_register
;
2851 value
->u
.reg
= tdep
->ppc_lr_regnum
;
2855 /* Convert a DBX STABS register number to a GDB register number. */
2857 rs6000_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
2859 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2861 if (0 <= num
&& num
<= 31)
2862 return tdep
->ppc_gp0_regnum
+ num
;
2863 else if (32 <= num
&& num
<= 63)
2864 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2865 specifies registers the architecture doesn't have? Our
2866 callers don't check the value we return. */
2867 return tdep
->ppc_fp0_regnum
+ (num
- 32);
2868 else if (77 <= num
&& num
<= 108)
2869 return tdep
->ppc_vr0_regnum
+ (num
- 77);
2870 else if (1200 <= num
&& num
< 1200 + 32)
2871 return tdep
->ppc_ev0_upper_regnum
+ (num
- 1200);
2876 return tdep
->ppc_mq_regnum
;
2878 return tdep
->ppc_lr_regnum
;
2880 return tdep
->ppc_ctr_regnum
;
2882 return tdep
->ppc_xer_regnum
;
2884 return tdep
->ppc_vrsave_regnum
;
2886 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
2888 return tdep
->ppc_acc_regnum
;
2890 return tdep
->ppc_spefscr_regnum
;
2897 /* Convert a Dwarf 2 register number to a GDB register number. */
2899 rs6000_dwarf2_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
2901 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2903 if (0 <= num
&& num
<= 31)
2904 return tdep
->ppc_gp0_regnum
+ num
;
2905 else if (32 <= num
&& num
<= 63)
2906 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2907 specifies registers the architecture doesn't have? Our
2908 callers don't check the value we return. */
2909 return tdep
->ppc_fp0_regnum
+ (num
- 32);
2910 else if (1124 <= num
&& num
< 1124 + 32)
2911 return tdep
->ppc_vr0_regnum
+ (num
- 1124);
2912 else if (1200 <= num
&& num
< 1200 + 32)
2913 return tdep
->ppc_ev0_upper_regnum
+ (num
- 1200);
2918 return tdep
->ppc_cr_regnum
;
2920 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
2922 return tdep
->ppc_acc_regnum
;
2924 return tdep
->ppc_mq_regnum
;
2926 return tdep
->ppc_xer_regnum
;
2928 return tdep
->ppc_lr_regnum
;
2930 return tdep
->ppc_ctr_regnum
;
2932 return tdep
->ppc_vrsave_regnum
;
2934 return tdep
->ppc_spefscr_regnum
;
2940 /* Translate a .eh_frame register to DWARF register, or adjust a
2941 .debug_frame register. */
2944 rs6000_adjust_frame_regnum (struct gdbarch
*gdbarch
, int num
, int eh_frame_p
)
2946 /* GCC releases before 3.4 use GCC internal register numbering in
2947 .debug_frame (and .debug_info, et cetera). The numbering is
2948 different from the standard SysV numbering for everything except
2949 for GPRs and FPRs. We can not detect this problem in most cases
2950 - to get accurate debug info for variables living in lr, ctr, v0,
2951 et cetera, use a newer version of GCC. But we must detect
2952 one important case - lr is in column 65 in .debug_frame output,
2955 GCC 3.4, and the "hammer" branch, have a related problem. They
2956 record lr register saves in .debug_frame as 108, but still record
2957 the return column as 65. We fix that up too.
2959 We can do this because 65 is assigned to fpsr, and GCC never
2960 generates debug info referring to it. To add support for
2961 handwritten debug info that restores fpsr, we would need to add a
2962 producer version check to this. */
2971 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
2972 internal register numbering; translate that to the standard DWARF2
2973 register numbering. */
2974 if (0 <= num
&& num
<= 63) /* r0-r31,fp0-fp31 */
2976 else if (68 <= num
&& num
<= 75) /* cr0-cr8 */
2977 return num
- 68 + 86;
2978 else if (77 <= num
&& num
<= 108) /* vr0-vr31 */
2979 return num
- 77 + 1124;
2991 case 109: /* vrsave */
2993 case 110: /* vscr */
2995 case 111: /* spe_acc */
2997 case 112: /* spefscr */
3005 /* Handling the various POWER/PowerPC variants. */
3007 /* Information about a particular processor variant. */
3011 /* Name of this variant. */
3014 /* English description of the variant. */
3015 const char *description
;
3017 /* bfd_arch_info.arch corresponding to variant. */
3018 enum bfd_architecture arch
;
3020 /* bfd_arch_info.mach corresponding to variant. */
3023 /* Target description for this variant. */
3024 struct target_desc
**tdesc
;
3027 static struct variant variants
[] =
3029 {"powerpc", "PowerPC user-level", bfd_arch_powerpc
,
3030 bfd_mach_ppc
, &tdesc_powerpc_altivec32
},
3031 {"power", "POWER user-level", bfd_arch_rs6000
,
3032 bfd_mach_rs6k
, &tdesc_rs6000
},
3033 {"403", "IBM PowerPC 403", bfd_arch_powerpc
,
3034 bfd_mach_ppc_403
, &tdesc_powerpc_403
},
3035 {"405", "IBM PowerPC 405", bfd_arch_powerpc
,
3036 bfd_mach_ppc_405
, &tdesc_powerpc_405
},
3037 {"601", "Motorola PowerPC 601", bfd_arch_powerpc
,
3038 bfd_mach_ppc_601
, &tdesc_powerpc_601
},
3039 {"602", "Motorola PowerPC 602", bfd_arch_powerpc
,
3040 bfd_mach_ppc_602
, &tdesc_powerpc_602
},
3041 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc
,
3042 bfd_mach_ppc_603
, &tdesc_powerpc_603
},
3043 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc
,
3044 604, &tdesc_powerpc_604
},
3045 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc
,
3046 bfd_mach_ppc_403gc
, &tdesc_powerpc_403gc
},
3047 {"505", "Motorola PowerPC 505", bfd_arch_powerpc
,
3048 bfd_mach_ppc_505
, &tdesc_powerpc_505
},
3049 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc
,
3050 bfd_mach_ppc_860
, &tdesc_powerpc_860
},
3051 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc
,
3052 bfd_mach_ppc_750
, &tdesc_powerpc_750
},
3053 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc
,
3054 bfd_mach_ppc_7400
, &tdesc_powerpc_7400
},
3055 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc
,
3056 bfd_mach_ppc_e500
, &tdesc_powerpc_e500
},
3059 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc
,
3060 bfd_mach_ppc64
, &tdesc_powerpc_altivec64
},
3061 {"620", "Motorola PowerPC 620", bfd_arch_powerpc
,
3062 bfd_mach_ppc_620
, &tdesc_powerpc_64
},
3063 {"630", "Motorola PowerPC 630", bfd_arch_powerpc
,
3064 bfd_mach_ppc_630
, &tdesc_powerpc_64
},
3065 {"a35", "PowerPC A35", bfd_arch_powerpc
,
3066 bfd_mach_ppc_a35
, &tdesc_powerpc_64
},
3067 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc
,
3068 bfd_mach_ppc_rs64ii
, &tdesc_powerpc_64
},
3069 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc
,
3070 bfd_mach_ppc_rs64iii
, &tdesc_powerpc_64
},
3072 /* FIXME: I haven't checked the register sets of the following. */
3073 {"rs1", "IBM POWER RS1", bfd_arch_rs6000
,
3074 bfd_mach_rs6k_rs1
, &tdesc_rs6000
},
3075 {"rsc", "IBM POWER RSC", bfd_arch_rs6000
,
3076 bfd_mach_rs6k_rsc
, &tdesc_rs6000
},
3077 {"rs2", "IBM POWER RS2", bfd_arch_rs6000
,
3078 bfd_mach_rs6k_rs2
, &tdesc_rs6000
},
3080 {0, 0, (enum bfd_architecture
) 0, 0, 0}
3083 /* Return the variant corresponding to architecture ARCH and machine number
3084 MACH. If no such variant exists, return null. */
3086 static const struct variant
*
3087 find_variant_by_arch (enum bfd_architecture arch
, unsigned long mach
)
3089 const struct variant
*v
;
3091 for (v
= variants
; v
->name
; v
++)
3092 if (arch
== v
->arch
&& mach
== v
->mach
)
3100 rs6000_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
3102 return frame_unwind_register_unsigned (next_frame
,
3103 gdbarch_pc_regnum (gdbarch
));
3106 static struct frame_id
3107 rs6000_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3109 return frame_id_build (get_frame_register_unsigned
3110 (this_frame
, gdbarch_sp_regnum (gdbarch
)),
3111 get_frame_pc (this_frame
));
3114 struct rs6000_frame_cache
3117 CORE_ADDR initial_sp
;
3118 struct trad_frame_saved_reg
*saved_regs
;
3120 /* Set BASE_P to true if this frame cache is properly initialized.
3121 Otherwise set to false because some registers or memory cannot
3124 /* Cache PC for building unavailable frame. */
3128 static struct rs6000_frame_cache
*
3129 rs6000_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3131 struct rs6000_frame_cache
*cache
;
3132 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3133 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3134 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3135 struct rs6000_framedata fdata
;
3136 int wordsize
= tdep
->wordsize
;
3137 CORE_ADDR func
= 0, pc
= 0;
3139 if ((*this_cache
) != NULL
)
3140 return (struct rs6000_frame_cache
*) (*this_cache
);
3141 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
3142 (*this_cache
) = cache
;
3144 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3148 func
= get_frame_func (this_frame
);
3150 pc
= get_frame_pc (this_frame
);
3151 skip_prologue (gdbarch
, func
, pc
, &fdata
);
3153 /* Figure out the parent's stack pointer. */
3155 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
3156 address of the current frame. Things might be easier if the
3157 ->frame pointed to the outer-most address of the frame. In
3158 the mean time, the address of the prev frame is used as the
3159 base address of this frame. */
3160 cache
->base
= get_frame_register_unsigned
3161 (this_frame
, gdbarch_sp_regnum (gdbarch
));
3163 CATCH (ex
, RETURN_MASK_ERROR
)
3165 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
3166 throw_exception (ex
);
3167 return (struct rs6000_frame_cache
*) (*this_cache
);
3171 /* If the function appears to be frameless, check a couple of likely
3172 indicators that we have simply failed to find the frame setup.
3173 Two common cases of this are missing symbols (i.e.
3174 get_frame_func returns the wrong address or 0), and assembly
3175 stubs which have a fast exit path but set up a frame on the slow
3178 If the LR appears to return to this function, then presume that
3179 we have an ABI compliant frame that we failed to find. */
3180 if (fdata
.frameless
&& fdata
.lr_offset
== 0)
3185 saved_lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
3186 if (func
== 0 && saved_lr
== pc
)
3190 CORE_ADDR saved_func
= get_pc_function_start (saved_lr
);
3191 if (func
== saved_func
)
3197 fdata
.frameless
= 0;
3198 fdata
.lr_offset
= tdep
->lr_frame_offset
;
3202 if (!fdata
.frameless
)
3204 /* Frameless really means stackless. */
3207 if (safe_read_memory_unsigned_integer (cache
->base
, wordsize
,
3208 byte_order
, &backchain
))
3209 cache
->base
= (CORE_ADDR
) backchain
;
3212 trad_frame_set_value (cache
->saved_regs
,
3213 gdbarch_sp_regnum (gdbarch
), cache
->base
);
3215 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
3216 All fpr's from saved_fpr to fp31 are saved. */
3218 if (fdata
.saved_fpr
>= 0)
3221 CORE_ADDR fpr_addr
= cache
->base
+ fdata
.fpr_offset
;
3223 /* If skip_prologue says floating-point registers were saved,
3224 but the current architecture has no floating-point registers,
3225 then that's strange. But we have no indices to even record
3226 the addresses under, so we just ignore it. */
3227 if (ppc_floating_point_unit_p (gdbarch
))
3228 for (i
= fdata
.saved_fpr
; i
< ppc_num_fprs
; i
++)
3230 cache
->saved_regs
[tdep
->ppc_fp0_regnum
+ i
].addr
= fpr_addr
;
3235 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
3236 All gpr's from saved_gpr to gpr31 are saved (except during the
3239 if (fdata
.saved_gpr
>= 0)
3242 CORE_ADDR gpr_addr
= cache
->base
+ fdata
.gpr_offset
;
3243 for (i
= fdata
.saved_gpr
; i
< ppc_num_gprs
; i
++)
3245 if (fdata
.gpr_mask
& (1U << i
))
3246 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= gpr_addr
;
3247 gpr_addr
+= wordsize
;
3251 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
3252 All vr's from saved_vr to vr31 are saved. */
3253 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
3255 if (fdata
.saved_vr
>= 0)
3258 CORE_ADDR vr_addr
= cache
->base
+ fdata
.vr_offset
;
3259 for (i
= fdata
.saved_vr
; i
< 32; i
++)
3261 cache
->saved_regs
[tdep
->ppc_vr0_regnum
+ i
].addr
= vr_addr
;
3262 vr_addr
+= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
3267 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
3268 All vr's from saved_ev to ev31 are saved. ????? */
3269 if (tdep
->ppc_ev0_regnum
!= -1)
3271 if (fdata
.saved_ev
>= 0)
3274 CORE_ADDR ev_addr
= cache
->base
+ fdata
.ev_offset
;
3275 CORE_ADDR off
= (byte_order
== BFD_ENDIAN_BIG
? 4 : 0);
3277 for (i
= fdata
.saved_ev
; i
< ppc_num_gprs
; i
++)
3279 cache
->saved_regs
[tdep
->ppc_ev0_regnum
+ i
].addr
= ev_addr
;
3280 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= ev_addr
+ off
;
3281 ev_addr
+= register_size (gdbarch
, tdep
->ppc_ev0_regnum
);
3286 /* If != 0, fdata.cr_offset is the offset from the frame that
3288 if (fdata
.cr_offset
!= 0)
3289 cache
->saved_regs
[tdep
->ppc_cr_regnum
].addr
3290 = cache
->base
+ fdata
.cr_offset
;
3292 /* If != 0, fdata.lr_offset is the offset from the frame that
3294 if (fdata
.lr_offset
!= 0)
3295 cache
->saved_regs
[tdep
->ppc_lr_regnum
].addr
3296 = cache
->base
+ fdata
.lr_offset
;
3297 else if (fdata
.lr_register
!= -1)
3298 cache
->saved_regs
[tdep
->ppc_lr_regnum
].realreg
= fdata
.lr_register
;
3299 /* The PC is found in the link register. */
3300 cache
->saved_regs
[gdbarch_pc_regnum (gdbarch
)] =
3301 cache
->saved_regs
[tdep
->ppc_lr_regnum
];
3303 /* If != 0, fdata.vrsave_offset is the offset from the frame that
3304 holds the VRSAVE. */
3305 if (fdata
.vrsave_offset
!= 0)
3306 cache
->saved_regs
[tdep
->ppc_vrsave_regnum
].addr
3307 = cache
->base
+ fdata
.vrsave_offset
;
3309 if (fdata
.alloca_reg
< 0)
3310 /* If no alloca register used, then fi->frame is the value of the
3311 %sp for this frame, and it is good enough. */
3313 = get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
3316 = get_frame_register_unsigned (this_frame
, fdata
.alloca_reg
);
3323 rs6000_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3324 struct frame_id
*this_id
)
3326 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3331 (*this_id
) = frame_id_build_unavailable_stack (info
->pc
);
3335 /* This marks the outermost frame. */
3336 if (info
->base
== 0)
3339 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3342 static struct value
*
3343 rs6000_frame_prev_register (struct frame_info
*this_frame
,
3344 void **this_cache
, int regnum
)
3346 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3348 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3351 static const struct frame_unwind rs6000_frame_unwind
=
3354 default_frame_unwind_stop_reason
,
3355 rs6000_frame_this_id
,
3356 rs6000_frame_prev_register
,
3358 default_frame_sniffer
3361 /* Allocate and initialize a frame cache for an epilogue frame.
3362 SP is restored and prev-PC is stored in LR. */
3364 static struct rs6000_frame_cache
*
3365 rs6000_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3367 struct rs6000_frame_cache
*cache
;
3368 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3369 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3372 return (struct rs6000_frame_cache
*) *this_cache
;
3374 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
3375 (*this_cache
) = cache
;
3376 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3380 /* At this point the stack looks as if we just entered the
3381 function, and the return address is stored in LR. */
3384 sp
= get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
3385 lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
3388 cache
->initial_sp
= sp
;
3390 trad_frame_set_value (cache
->saved_regs
,
3391 gdbarch_pc_regnum (gdbarch
), lr
);
3393 CATCH (ex
, RETURN_MASK_ERROR
)
3395 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
3396 throw_exception (ex
);
3403 /* Implementation of frame_unwind.this_id, as defined in frame_unwind.h.
3404 Return the frame ID of an epilogue frame. */
3407 rs6000_epilogue_frame_this_id (struct frame_info
*this_frame
,
3408 void **this_cache
, struct frame_id
*this_id
)
3411 struct rs6000_frame_cache
*info
=
3412 rs6000_epilogue_frame_cache (this_frame
, this_cache
);
3414 pc
= get_frame_func (this_frame
);
3415 if (info
->base
== 0)
3416 (*this_id
) = frame_id_build_unavailable_stack (pc
);
3418 (*this_id
) = frame_id_build (info
->base
, pc
);
3421 /* Implementation of frame_unwind.prev_register, as defined in frame_unwind.h.
3422 Return the register value of REGNUM in previous frame. */
3424 static struct value
*
3425 rs6000_epilogue_frame_prev_register (struct frame_info
*this_frame
,
3426 void **this_cache
, int regnum
)
3428 struct rs6000_frame_cache
*info
=
3429 rs6000_epilogue_frame_cache (this_frame
, this_cache
);
3430 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3433 /* Implementation of frame_unwind.sniffer, as defined in frame_unwind.h.
3434 Check whether this an epilogue frame. */
3437 rs6000_epilogue_frame_sniffer (const struct frame_unwind
*self
,
3438 struct frame_info
*this_frame
,
3439 void **this_prologue_cache
)
3441 if (frame_relative_level (this_frame
) == 0)
3442 return rs6000_in_function_epilogue_frame_p (this_frame
,
3443 get_frame_arch (this_frame
),
3444 get_frame_pc (this_frame
));
3449 /* Frame unwinder for epilogue frame. This is required for reverse step-over
3450 a function without debug information. */
3452 static const struct frame_unwind rs6000_epilogue_frame_unwind
=
3455 default_frame_unwind_stop_reason
,
3456 rs6000_epilogue_frame_this_id
, rs6000_epilogue_frame_prev_register
,
3458 rs6000_epilogue_frame_sniffer
3463 rs6000_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
3465 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3467 return info
->initial_sp
;
3470 static const struct frame_base rs6000_frame_base
= {
3471 &rs6000_frame_unwind
,
3472 rs6000_frame_base_address
,
3473 rs6000_frame_base_address
,
3474 rs6000_frame_base_address
3477 static const struct frame_base
*
3478 rs6000_frame_base_sniffer (struct frame_info
*this_frame
)
3480 return &rs6000_frame_base
;
3483 /* DWARF-2 frame support. Used to handle the detection of
3484 clobbered registers during function calls. */
3487 ppc_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
3488 struct dwarf2_frame_state_reg
*reg
,
3489 struct frame_info
*this_frame
)
3491 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3493 /* PPC32 and PPC64 ABI's are the same regarding volatile and
3494 non-volatile registers. We will use the same code for both. */
3496 /* Call-saved GP registers. */
3497 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 14
3498 && regnum
<= tdep
->ppc_gp0_regnum
+ 31)
3499 || (regnum
== tdep
->ppc_gp0_regnum
+ 1))
3500 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3502 /* Call-clobbered GP registers. */
3503 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 3
3504 && regnum
<= tdep
->ppc_gp0_regnum
+ 12)
3505 || (regnum
== tdep
->ppc_gp0_regnum
))
3506 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3508 /* Deal with FP registers, if supported. */
3509 if (tdep
->ppc_fp0_regnum
>= 0)
3511 /* Call-saved FP registers. */
3512 if ((regnum
>= tdep
->ppc_fp0_regnum
+ 14
3513 && regnum
<= tdep
->ppc_fp0_regnum
+ 31))
3514 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3516 /* Call-clobbered FP registers. */
3517 if ((regnum
>= tdep
->ppc_fp0_regnum
3518 && regnum
<= tdep
->ppc_fp0_regnum
+ 13))
3519 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3522 /* Deal with ALTIVEC registers, if supported. */
3523 if (tdep
->ppc_vr0_regnum
> 0 && tdep
->ppc_vrsave_regnum
> 0)
3525 /* Call-saved Altivec registers. */
3526 if ((regnum
>= tdep
->ppc_vr0_regnum
+ 20
3527 && regnum
<= tdep
->ppc_vr0_regnum
+ 31)
3528 || regnum
== tdep
->ppc_vrsave_regnum
)
3529 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3531 /* Call-clobbered Altivec registers. */
3532 if ((regnum
>= tdep
->ppc_vr0_regnum
3533 && regnum
<= tdep
->ppc_vr0_regnum
+ 19))
3534 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3537 /* Handle PC register and Stack Pointer correctly. */
3538 if (regnum
== gdbarch_pc_regnum (gdbarch
))
3539 reg
->how
= DWARF2_FRAME_REG_RA
;
3540 else if (regnum
== gdbarch_sp_regnum (gdbarch
))
3541 reg
->how
= DWARF2_FRAME_REG_CFA
;
3545 /* Return true if a .gnu_attributes section exists in BFD and it
3546 indicates we are using SPE extensions OR if a .PPC.EMB.apuinfo
3547 section exists in BFD and it indicates that SPE extensions are in
3548 use. Check the .gnu.attributes section first, as the binary might be
3549 compiled for SPE, but not actually using SPE instructions. */
3552 bfd_uses_spe_extensions (bfd
*abfd
)
3555 gdb_byte
*contents
= NULL
;
3564 /* Using Tag_GNU_Power_ABI_Vector here is a bit of a hack, as the user
3565 could be using the SPE vector abi without actually using any spe
3566 bits whatsoever. But it's close enough for now. */
3567 int vector_abi
= bfd_elf_get_obj_attr_int (abfd
, OBJ_ATTR_GNU
,
3568 Tag_GNU_Power_ABI_Vector
);
3569 if (vector_abi
== 3)
3573 sect
= bfd_get_section_by_name (abfd
, ".PPC.EMB.apuinfo");
3577 size
= bfd_get_section_size (sect
);
3578 contents
= (gdb_byte
*) xmalloc (size
);
3579 if (!bfd_get_section_contents (abfd
, sect
, contents
, 0, size
))
3585 /* Parse the .PPC.EMB.apuinfo section. The layout is as follows:
3591 char name[name_len rounded up to 4-byte alignment];
3592 char data[data_len];
3595 Technically, there's only supposed to be one such structure in a
3596 given apuinfo section, but the linker is not always vigilant about
3597 merging apuinfo sections from input files. Just go ahead and parse
3598 them all, exiting early when we discover the binary uses SPE
3601 It's not specified in what endianness the information in this
3602 section is stored. Assume that it's the endianness of the BFD. */
3606 unsigned int name_len
;
3607 unsigned int data_len
;
3610 /* If we can't read the first three fields, we're done. */
3614 name_len
= bfd_get_32 (abfd
, ptr
);
3615 name_len
= (name_len
+ 3) & ~3U; /* Round to 4 bytes. */
3616 data_len
= bfd_get_32 (abfd
, ptr
+ 4);
3617 type
= bfd_get_32 (abfd
, ptr
+ 8);
3620 /* The name must be "APUinfo\0". */
3622 && strcmp ((const char *) ptr
, "APUinfo") != 0)
3626 /* The type must be 2. */
3630 /* The data is stored as a series of uint32. The upper half of
3631 each uint32 indicates the particular APU used and the lower
3632 half indicates the revision of that APU. We just care about
3635 /* Not 4-byte quantities. */
3641 unsigned int apuinfo
= bfd_get_32 (abfd
, ptr
);
3642 unsigned int apu
= apuinfo
>> 16;
3646 /* The SPE APU is 0x100; the SPEFP APU is 0x101. Accept
3648 if (apu
== 0x100 || apu
== 0x101)
3663 /* These are macros for parsing instruction fields (I.1.6.28) */
3665 #define PPC_FIELD(value, from, len) \
3666 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
3667 #define PPC_SEXT(v, bs) \
3668 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
3669 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
3670 - ((CORE_ADDR) 1 << ((bs) - 1)))
3671 #define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
3672 #define PPC_EXTOP(insn) PPC_FIELD (insn, 21, 10)
3673 #define PPC_RT(insn) PPC_FIELD (insn, 6, 5)
3674 #define PPC_RS(insn) PPC_FIELD (insn, 6, 5)
3675 #define PPC_RA(insn) PPC_FIELD (insn, 11, 5)
3676 #define PPC_RB(insn) PPC_FIELD (insn, 16, 5)
3677 #define PPC_NB(insn) PPC_FIELD (insn, 16, 5)
3678 #define PPC_VRT(insn) PPC_FIELD (insn, 6, 5)
3679 #define PPC_FRT(insn) PPC_FIELD (insn, 6, 5)
3680 #define PPC_SPR(insn) (PPC_FIELD (insn, 11, 5) \
3681 | (PPC_FIELD (insn, 16, 5) << 5))
3682 #define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
3683 #define PPC_T(insn) PPC_FIELD (insn, 6, 5)
3684 #define PPC_D(insn) PPC_SEXT (PPC_FIELD (insn, 16, 16), 16)
3685 #define PPC_DS(insn) PPC_SEXT (PPC_FIELD (insn, 16, 14), 14)
3686 #define PPC_DQ(insn) PPC_SEXT (PPC_FIELD (insn, 16, 12), 12)
3687 #define PPC_BIT(insn,n) ((insn & (1 << (31 - (n)))) ? 1 : 0)
3688 #define PPC_OE(insn) PPC_BIT (insn, 21)
3689 #define PPC_RC(insn) PPC_BIT (insn, 31)
3690 #define PPC_Rc(insn) PPC_BIT (insn, 21)
3691 #define PPC_LK(insn) PPC_BIT (insn, 31)
3692 #define PPC_TX(insn) PPC_BIT (insn, 31)
3693 #define PPC_LEV(insn) PPC_FIELD (insn, 20, 7)
3695 #define PPC_XT(insn) ((PPC_TX (insn) << 5) | PPC_T (insn))
3696 #define PPC_XER_NB(xer) (xer & 0x7f)
3698 /* Record Vector-Scalar Registers.
3699 For VSR less than 32, it's represented by an FPR and an VSR-upper register.
3700 Otherwise, it's just a VR register. Record them accordingly. */
3703 ppc_record_vsr (struct regcache
*regcache
, struct gdbarch_tdep
*tdep
, int vsr
)
3705 if (vsr
< 0 || vsr
>= 64)
3710 if (tdep
->ppc_vr0_regnum
>= 0)
3711 record_full_arch_list_add_reg (regcache
, tdep
->ppc_vr0_regnum
+ vsr
- 32);
3715 if (tdep
->ppc_fp0_regnum
>= 0)
3716 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fp0_regnum
+ vsr
);
3717 if (tdep
->ppc_vsr0_upper_regnum
>= 0)
3718 record_full_arch_list_add_reg (regcache
,
3719 tdep
->ppc_vsr0_upper_regnum
+ vsr
);
3725 /* Parse and record instructions primary opcode-4 at ADDR.
3726 Return 0 if successful. */
3729 ppc_process_record_op4 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3730 CORE_ADDR addr
, uint32_t insn
)
3732 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3733 int ext
= PPC_FIELD (insn
, 21, 11);
3734 int vra
= PPC_FIELD (insn
, 11, 5);
3738 case 32: /* Vector Multiply-High-Add Signed Halfword Saturate */
3739 case 33: /* Vector Multiply-High-Round-Add Signed Halfword Saturate */
3740 case 39: /* Vector Multiply-Sum Unsigned Halfword Saturate */
3741 case 41: /* Vector Multiply-Sum Signed Halfword Saturate */
3742 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
3744 case 42: /* Vector Select */
3745 case 43: /* Vector Permute */
3746 case 59: /* Vector Permute Right-indexed */
3747 case 44: /* Vector Shift Left Double by Octet Immediate */
3748 case 45: /* Vector Permute and Exclusive-OR */
3749 case 60: /* Vector Add Extended Unsigned Quadword Modulo */
3750 case 61: /* Vector Add Extended & write Carry Unsigned Quadword */
3751 case 62: /* Vector Subtract Extended Unsigned Quadword Modulo */
3752 case 63: /* Vector Subtract Extended & write Carry Unsigned Quadword */
3753 case 34: /* Vector Multiply-Low-Add Unsigned Halfword Modulo */
3754 case 35: /* Vector Multiply-Sum Unsigned Doubleword Modulo */
3755 case 36: /* Vector Multiply-Sum Unsigned Byte Modulo */
3756 case 37: /* Vector Multiply-Sum Mixed Byte Modulo */
3757 case 38: /* Vector Multiply-Sum Unsigned Halfword Modulo */
3758 case 40: /* Vector Multiply-Sum Signed Halfword Modulo */
3759 case 46: /* Vector Multiply-Add Single-Precision */
3760 case 47: /* Vector Negative Multiply-Subtract Single-Precision */
3761 record_full_arch_list_add_reg (regcache
,
3762 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
3765 case 48: /* Multiply-Add High Doubleword */
3766 case 49: /* Multiply-Add High Doubleword Unsigned */
3767 case 51: /* Multiply-Add Low Doubleword */
3768 record_full_arch_list_add_reg (regcache
,
3769 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
3773 switch ((ext
& 0x1ff))
3776 if (vra
!= 0 /* Decimal Convert To Signed Quadword */
3777 && vra
!= 2 /* Decimal Convert From Signed Quadword */
3778 && vra
!= 4 /* Decimal Convert To Zoned */
3779 && vra
!= 5 /* Decimal Convert To National */
3780 && vra
!= 6 /* Decimal Convert From Zoned */
3781 && vra
!= 7 /* Decimal Convert From National */
3782 && vra
!= 31) /* Decimal Set Sign */
3785 /* 5.16 Decimal Integer Arithmetic Instructions */
3786 case 1: /* Decimal Add Modulo */
3787 case 65: /* Decimal Subtract Modulo */
3789 case 193: /* Decimal Shift */
3790 case 129: /* Decimal Unsigned Shift */
3791 case 449: /* Decimal Shift and Round */
3793 case 257: /* Decimal Truncate */
3794 case 321: /* Decimal Unsigned Truncate */
3796 /* Bit-21 should be set. */
3797 if (!PPC_BIT (insn
, 21))
3800 record_full_arch_list_add_reg (regcache
,
3801 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
3802 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
3806 /* Bit-21 is used for RC */
3807 switch (ext
& 0x3ff)
3809 case 6: /* Vector Compare Equal To Unsigned Byte */
3810 case 70: /* Vector Compare Equal To Unsigned Halfword */
3811 case 134: /* Vector Compare Equal To Unsigned Word */
3812 case 199: /* Vector Compare Equal To Unsigned Doubleword */
3813 case 774: /* Vector Compare Greater Than Signed Byte */
3814 case 838: /* Vector Compare Greater Than Signed Halfword */
3815 case 902: /* Vector Compare Greater Than Signed Word */
3816 case 967: /* Vector Compare Greater Than Signed Doubleword */
3817 case 518: /* Vector Compare Greater Than Unsigned Byte */
3818 case 646: /* Vector Compare Greater Than Unsigned Word */
3819 case 582: /* Vector Compare Greater Than Unsigned Halfword */
3820 case 711: /* Vector Compare Greater Than Unsigned Doubleword */
3821 case 966: /* Vector Compare Bounds Single-Precision */
3822 case 198: /* Vector Compare Equal To Single-Precision */
3823 case 454: /* Vector Compare Greater Than or Equal To Single-Precision */
3824 case 710: /* Vector Compare Greater Than Single-Precision */
3825 case 7: /* Vector Compare Not Equal Byte */
3826 case 71: /* Vector Compare Not Equal Halfword */
3827 case 135: /* Vector Compare Not Equal Word */
3828 case 263: /* Vector Compare Not Equal or Zero Byte */
3829 case 327: /* Vector Compare Not Equal or Zero Halfword */
3830 case 391: /* Vector Compare Not Equal or Zero Word */
3832 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
3833 record_full_arch_list_add_reg (regcache
,
3834 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
3842 case 0: /* Vector Count Leading Zero Least-Significant Bits
3844 case 1: /* Vector Count Trailing Zero Least-Significant Bits
3846 record_full_arch_list_add_reg (regcache
,
3847 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
3850 case 6: /* Vector Negate Word */
3851 case 7: /* Vector Negate Doubleword */
3852 case 8: /* Vector Parity Byte Word */
3853 case 9: /* Vector Parity Byte Doubleword */
3854 case 10: /* Vector Parity Byte Quadword */
3855 case 16: /* Vector Extend Sign Byte To Word */
3856 case 17: /* Vector Extend Sign Halfword To Word */
3857 case 24: /* Vector Extend Sign Byte To Doubleword */
3858 case 25: /* Vector Extend Sign Halfword To Doubleword */
3859 case 26: /* Vector Extend Sign Word To Doubleword */
3860 case 28: /* Vector Count Trailing Zeros Byte */
3861 case 29: /* Vector Count Trailing Zeros Halfword */
3862 case 30: /* Vector Count Trailing Zeros Word */
3863 case 31: /* Vector Count Trailing Zeros Doubleword */
3864 record_full_arch_list_add_reg (regcache
,
3865 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
3872 case 142: /* Vector Pack Unsigned Halfword Unsigned Saturate */
3873 case 206: /* Vector Pack Unsigned Word Unsigned Saturate */
3874 case 270: /* Vector Pack Signed Halfword Unsigned Saturate */
3875 case 334: /* Vector Pack Signed Word Unsigned Saturate */
3876 case 398: /* Vector Pack Signed Halfword Signed Saturate */
3877 case 462: /* Vector Pack Signed Word Signed Saturate */
3878 case 1230: /* Vector Pack Unsigned Doubleword Unsigned Saturate */
3879 case 1358: /* Vector Pack Signed Doubleword Unsigned Saturate */
3880 case 1486: /* Vector Pack Signed Doubleword Signed Saturate */
3881 case 512: /* Vector Add Unsigned Byte Saturate */
3882 case 576: /* Vector Add Unsigned Halfword Saturate */
3883 case 640: /* Vector Add Unsigned Word Saturate */
3884 case 768: /* Vector Add Signed Byte Saturate */
3885 case 832: /* Vector Add Signed Halfword Saturate */
3886 case 896: /* Vector Add Signed Word Saturate */
3887 case 1536: /* Vector Subtract Unsigned Byte Saturate */
3888 case 1600: /* Vector Subtract Unsigned Halfword Saturate */
3889 case 1664: /* Vector Subtract Unsigned Word Saturate */
3890 case 1792: /* Vector Subtract Signed Byte Saturate */
3891 case 1856: /* Vector Subtract Signed Halfword Saturate */
3892 case 1920: /* Vector Subtract Signed Word Saturate */
3894 case 1544: /* Vector Sum across Quarter Unsigned Byte Saturate */
3895 case 1800: /* Vector Sum across Quarter Signed Byte Saturate */
3896 case 1608: /* Vector Sum across Quarter Signed Halfword Saturate */
3897 case 1672: /* Vector Sum across Half Signed Word Saturate */
3898 case 1928: /* Vector Sum across Signed Word Saturate */
3899 case 970: /* Vector Convert To Signed Fixed-Point Word Saturate */
3900 case 906: /* Vector Convert To Unsigned Fixed-Point Word Saturate */
3901 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
3903 case 12: /* Vector Merge High Byte */
3904 case 14: /* Vector Pack Unsigned Halfword Unsigned Modulo */
3905 case 76: /* Vector Merge High Halfword */
3906 case 78: /* Vector Pack Unsigned Word Unsigned Modulo */
3907 case 140: /* Vector Merge High Word */
3908 case 268: /* Vector Merge Low Byte */
3909 case 332: /* Vector Merge Low Halfword */
3910 case 396: /* Vector Merge Low Word */
3911 case 526: /* Vector Unpack High Signed Byte */
3912 case 590: /* Vector Unpack High Signed Halfword */
3913 case 654: /* Vector Unpack Low Signed Byte */
3914 case 718: /* Vector Unpack Low Signed Halfword */
3915 case 782: /* Vector Pack Pixel */
3916 case 846: /* Vector Unpack High Pixel */
3917 case 974: /* Vector Unpack Low Pixel */
3918 case 1102: /* Vector Pack Unsigned Doubleword Unsigned Modulo */
3919 case 1614: /* Vector Unpack High Signed Word */
3920 case 1676: /* Vector Merge Odd Word */
3921 case 1742: /* Vector Unpack Low Signed Word */
3922 case 1932: /* Vector Merge Even Word */
3923 case 524: /* Vector Splat Byte */
3924 case 588: /* Vector Splat Halfword */
3925 case 652: /* Vector Splat Word */
3926 case 780: /* Vector Splat Immediate Signed Byte */
3927 case 844: /* Vector Splat Immediate Signed Halfword */
3928 case 908: /* Vector Splat Immediate Signed Word */
3929 case 452: /* Vector Shift Left */
3930 case 708: /* Vector Shift Right */
3931 case 1036: /* Vector Shift Left by Octet */
3932 case 1100: /* Vector Shift Right by Octet */
3933 case 0: /* Vector Add Unsigned Byte Modulo */
3934 case 64: /* Vector Add Unsigned Halfword Modulo */
3935 case 128: /* Vector Add Unsigned Word Modulo */
3936 case 192: /* Vector Add Unsigned Doubleword Modulo */
3937 case 256: /* Vector Add Unsigned Quadword Modulo */
3938 case 320: /* Vector Add & write Carry Unsigned Quadword */
3939 case 384: /* Vector Add and Write Carry-Out Unsigned Word */
3940 case 8: /* Vector Multiply Odd Unsigned Byte */
3941 case 72: /* Vector Multiply Odd Unsigned Halfword */
3942 case 136: /* Vector Multiply Odd Unsigned Word */
3943 case 264: /* Vector Multiply Odd Signed Byte */
3944 case 328: /* Vector Multiply Odd Signed Halfword */
3945 case 392: /* Vector Multiply Odd Signed Word */
3946 case 520: /* Vector Multiply Even Unsigned Byte */
3947 case 584: /* Vector Multiply Even Unsigned Halfword */
3948 case 648: /* Vector Multiply Even Unsigned Word */
3949 case 776: /* Vector Multiply Even Signed Byte */
3950 case 840: /* Vector Multiply Even Signed Halfword */
3951 case 904: /* Vector Multiply Even Signed Word */
3952 case 137: /* Vector Multiply Unsigned Word Modulo */
3953 case 1024: /* Vector Subtract Unsigned Byte Modulo */
3954 case 1088: /* Vector Subtract Unsigned Halfword Modulo */
3955 case 1152: /* Vector Subtract Unsigned Word Modulo */
3956 case 1216: /* Vector Subtract Unsigned Doubleword Modulo */
3957 case 1280: /* Vector Subtract Unsigned Quadword Modulo */
3958 case 1344: /* Vector Subtract & write Carry Unsigned Quadword */
3959 case 1408: /* Vector Subtract and Write Carry-Out Unsigned Word */
3960 case 1282: /* Vector Average Signed Byte */
3961 case 1346: /* Vector Average Signed Halfword */
3962 case 1410: /* Vector Average Signed Word */
3963 case 1026: /* Vector Average Unsigned Byte */
3964 case 1090: /* Vector Average Unsigned Halfword */
3965 case 1154: /* Vector Average Unsigned Word */
3966 case 258: /* Vector Maximum Signed Byte */
3967 case 322: /* Vector Maximum Signed Halfword */
3968 case 386: /* Vector Maximum Signed Word */
3969 case 450: /* Vector Maximum Signed Doubleword */
3970 case 2: /* Vector Maximum Unsigned Byte */
3971 case 66: /* Vector Maximum Unsigned Halfword */
3972 case 130: /* Vector Maximum Unsigned Word */
3973 case 194: /* Vector Maximum Unsigned Doubleword */
3974 case 770: /* Vector Minimum Signed Byte */
3975 case 834: /* Vector Minimum Signed Halfword */
3976 case 898: /* Vector Minimum Signed Word */
3977 case 962: /* Vector Minimum Signed Doubleword */
3978 case 514: /* Vector Minimum Unsigned Byte */
3979 case 578: /* Vector Minimum Unsigned Halfword */
3980 case 642: /* Vector Minimum Unsigned Word */
3981 case 706: /* Vector Minimum Unsigned Doubleword */
3982 case 1028: /* Vector Logical AND */
3983 case 1668: /* Vector Logical Equivalent */
3984 case 1092: /* Vector Logical AND with Complement */
3985 case 1412: /* Vector Logical NAND */
3986 case 1348: /* Vector Logical OR with Complement */
3987 case 1156: /* Vector Logical OR */
3988 case 1284: /* Vector Logical NOR */
3989 case 1220: /* Vector Logical XOR */
3990 case 4: /* Vector Rotate Left Byte */
3991 case 132: /* Vector Rotate Left Word VX-form */
3992 case 68: /* Vector Rotate Left Halfword */
3993 case 196: /* Vector Rotate Left Doubleword */
3994 case 260: /* Vector Shift Left Byte */
3995 case 388: /* Vector Shift Left Word */
3996 case 324: /* Vector Shift Left Halfword */
3997 case 1476: /* Vector Shift Left Doubleword */
3998 case 516: /* Vector Shift Right Byte */
3999 case 644: /* Vector Shift Right Word */
4000 case 580: /* Vector Shift Right Halfword */
4001 case 1732: /* Vector Shift Right Doubleword */
4002 case 772: /* Vector Shift Right Algebraic Byte */
4003 case 900: /* Vector Shift Right Algebraic Word */
4004 case 836: /* Vector Shift Right Algebraic Halfword */
4005 case 964: /* Vector Shift Right Algebraic Doubleword */
4006 case 10: /* Vector Add Single-Precision */
4007 case 74: /* Vector Subtract Single-Precision */
4008 case 1034: /* Vector Maximum Single-Precision */
4009 case 1098: /* Vector Minimum Single-Precision */
4010 case 842: /* Vector Convert From Signed Fixed-Point Word */
4011 case 778: /* Vector Convert From Unsigned Fixed-Point Word */
4012 case 714: /* Vector Round to Single-Precision Integer toward -Infinity */
4013 case 522: /* Vector Round to Single-Precision Integer Nearest */
4014 case 650: /* Vector Round to Single-Precision Integer toward +Infinity */
4015 case 586: /* Vector Round to Single-Precision Integer toward Zero */
4016 case 394: /* Vector 2 Raised to the Exponent Estimate Floating-Point */
4017 case 458: /* Vector Log Base 2 Estimate Floating-Point */
4018 case 266: /* Vector Reciprocal Estimate Single-Precision */
4019 case 330: /* Vector Reciprocal Square Root Estimate Single-Precision */
4020 case 1288: /* Vector AES Cipher */
4021 case 1289: /* Vector AES Cipher Last */
4022 case 1352: /* Vector AES Inverse Cipher */
4023 case 1353: /* Vector AES Inverse Cipher Last */
4024 case 1480: /* Vector AES SubBytes */
4025 case 1730: /* Vector SHA-512 Sigma Doubleword */
4026 case 1666: /* Vector SHA-256 Sigma Word */
4027 case 1032: /* Vector Polynomial Multiply-Sum Byte */
4028 case 1160: /* Vector Polynomial Multiply-Sum Word */
4029 case 1096: /* Vector Polynomial Multiply-Sum Halfword */
4030 case 1224: /* Vector Polynomial Multiply-Sum Doubleword */
4031 case 1292: /* Vector Gather Bits by Bytes by Doubleword */
4032 case 1794: /* Vector Count Leading Zeros Byte */
4033 case 1858: /* Vector Count Leading Zeros Halfword */
4034 case 1922: /* Vector Count Leading Zeros Word */
4035 case 1986: /* Vector Count Leading Zeros Doubleword */
4036 case 1795: /* Vector Population Count Byte */
4037 case 1859: /* Vector Population Count Halfword */
4038 case 1923: /* Vector Population Count Word */
4039 case 1987: /* Vector Population Count Doubleword */
4040 case 1356: /* Vector Bit Permute Quadword */
4041 case 1484: /* Vector Bit Permute Doubleword */
4042 case 513: /* Vector Multiply-by-10 Unsigned Quadword */
4043 case 1: /* Vector Multiply-by-10 & write Carry Unsigned
4045 case 577: /* Vector Multiply-by-10 Extended Unsigned Quadword */
4046 case 65: /* Vector Multiply-by-10 Extended & write Carry
4047 Unsigned Quadword */
4048 case 1027: /* Vector Absolute Difference Unsigned Byte */
4049 case 1091: /* Vector Absolute Difference Unsigned Halfword */
4050 case 1155: /* Vector Absolute Difference Unsigned Word */
4051 case 1796: /* Vector Shift Right Variable */
4052 case 1860: /* Vector Shift Left Variable */
4053 case 133: /* Vector Rotate Left Word then Mask Insert */
4054 case 197: /* Vector Rotate Left Doubleword then Mask Insert */
4055 case 389: /* Vector Rotate Left Word then AND with Mask */
4056 case 453: /* Vector Rotate Left Doubleword then AND with Mask */
4057 case 525: /* Vector Extract Unsigned Byte */
4058 case 589: /* Vector Extract Unsigned Halfword */
4059 case 653: /* Vector Extract Unsigned Word */
4060 case 717: /* Vector Extract Doubleword */
4061 case 781: /* Vector Insert Byte */
4062 case 845: /* Vector Insert Halfword */
4063 case 909: /* Vector Insert Word */
4064 case 973: /* Vector Insert Doubleword */
4065 record_full_arch_list_add_reg (regcache
,
4066 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4069 case 1549: /* Vector Extract Unsigned Byte Left-Indexed */
4070 case 1613: /* Vector Extract Unsigned Halfword Left-Indexed */
4071 case 1677: /* Vector Extract Unsigned Word Left-Indexed */
4072 case 1805: /* Vector Extract Unsigned Byte Right-Indexed */
4073 case 1869: /* Vector Extract Unsigned Halfword Right-Indexed */
4074 case 1933: /* Vector Extract Unsigned Word Right-Indexed */
4075 record_full_arch_list_add_reg (regcache
,
4076 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4079 case 1604: /* Move To Vector Status and Control Register */
4080 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
4082 case 1540: /* Move From Vector Status and Control Register */
4083 record_full_arch_list_add_reg (regcache
,
4084 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4086 case 833: /* Decimal Copy Sign */
4087 record_full_arch_list_add_reg (regcache
,
4088 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4089 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4093 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4094 "at %s, 4-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4098 /* Parse and record instructions of primary opcode-19 at ADDR.
4099 Return 0 if successful. */
4102 ppc_process_record_op19 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4103 CORE_ADDR addr
, uint32_t insn
)
4105 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4106 int ext
= PPC_EXTOP (insn
);
4108 switch (ext
& 0x01f)
4110 case 2: /* Add PC Immediate Shifted */
4111 record_full_arch_list_add_reg (regcache
,
4112 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4118 case 0: /* Move Condition Register Field */
4119 case 33: /* Condition Register NOR */
4120 case 129: /* Condition Register AND with Complement */
4121 case 193: /* Condition Register XOR */
4122 case 225: /* Condition Register NAND */
4123 case 257: /* Condition Register AND */
4124 case 289: /* Condition Register Equivalent */
4125 case 417: /* Condition Register OR with Complement */
4126 case 449: /* Condition Register OR */
4127 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4130 case 16: /* Branch Conditional */
4131 case 560: /* Branch Conditional to Branch Target Address Register */
4132 if ((PPC_BO (insn
) & 0x4) == 0)
4133 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
4135 case 528: /* Branch Conditional to Count Register */
4137 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
4140 case 150: /* Instruction Synchronize */
4145 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4146 "at %s, 19-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4150 /* Parse and record instructions of primary opcode-31 at ADDR.
4151 Return 0 if successful. */
4154 ppc_process_record_op31 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4155 CORE_ADDR addr
, uint32_t insn
)
4157 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4158 int ext
= PPC_EXTOP (insn
);
4160 CORE_ADDR at_dcsz
, ea
= 0;
4161 ULONGEST rb
, ra
, xer
;
4164 /* These instructions have OE bit. */
4165 switch (ext
& 0x1ff)
4167 /* These write RT and XER. Update CR if RC is set. */
4168 case 8: /* Subtract from carrying */
4169 case 10: /* Add carrying */
4170 case 136: /* Subtract from extended */
4171 case 138: /* Add extended */
4172 case 200: /* Subtract from zero extended */
4173 case 202: /* Add to zero extended */
4174 case 232: /* Subtract from minus one extended */
4175 case 234: /* Add to minus one extended */
4176 /* CA is always altered, but SO/OV are only altered when OE=1.
4177 In any case, XER is always altered. */
4178 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4180 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4181 record_full_arch_list_add_reg (regcache
,
4182 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4185 /* These write RT. Update CR if RC is set and update XER if OE is set. */
4186 case 40: /* Subtract from */
4187 case 104: /* Negate */
4188 case 233: /* Multiply low doubleword */
4189 case 235: /* Multiply low word */
4191 case 393: /* Divide Doubleword Extended Unsigned */
4192 case 395: /* Divide Word Extended Unsigned */
4193 case 425: /* Divide Doubleword Extended */
4194 case 427: /* Divide Word Extended */
4195 case 457: /* Divide Doubleword Unsigned */
4196 case 459: /* Divide Word Unsigned */
4197 case 489: /* Divide Doubleword */
4198 case 491: /* Divide Word */
4200 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4202 case 9: /* Multiply High Doubleword Unsigned */
4203 case 11: /* Multiply High Word Unsigned */
4204 case 73: /* Multiply High Doubleword */
4205 case 75: /* Multiply High Word */
4207 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4208 record_full_arch_list_add_reg (regcache
,
4209 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4213 if ((ext
& 0x1f) == 15)
4215 /* Integer Select. bit[16:20] is used for BC. */
4216 record_full_arch_list_add_reg (regcache
,
4217 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4221 if ((ext
& 0xff) == 170)
4223 /* Add Extended using alternate carry bits */
4224 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4225 record_full_arch_list_add_reg (regcache
,
4226 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4232 case 78: /* Determine Leftmost Zero Byte */
4234 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4235 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4236 record_full_arch_list_add_reg (regcache
,
4237 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4240 /* These only write RT. */
4241 case 19: /* Move from condition register */
4242 /* Move From One Condition Register Field */
4243 case 74: /* Add and Generate Sixes */
4244 case 74 | 0x200: /* Add and Generate Sixes (bit-21 dont-care) */
4245 case 302: /* Move From Branch History Rolling Buffer */
4246 case 339: /* Move From Special Purpose Register */
4247 case 371: /* Move From Time Base [Phased-Out] */
4248 case 309: /* Load Doubleword Monitored Indexed */
4249 case 128: /* Set Boolean */
4250 case 755: /* Deliver A Random Number */
4251 record_full_arch_list_add_reg (regcache
,
4252 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4255 /* These only write to RA. */
4256 case 51: /* Move From VSR Doubleword */
4257 case 115: /* Move From VSR Word and Zero */
4258 case 122: /* Population count bytes */
4259 case 378: /* Population count words */
4260 case 506: /* Population count doublewords */
4261 case 154: /* Parity Word */
4262 case 186: /* Parity Doubleword */
4263 case 252: /* Bit Permute Doubleword */
4264 case 282: /* Convert Declets To Binary Coded Decimal */
4265 case 314: /* Convert Binary Coded Decimal To Declets */
4266 case 508: /* Compare bytes */
4267 case 307: /* Move From VSR Lower Doubleword */
4268 record_full_arch_list_add_reg (regcache
,
4269 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4272 /* These write CR and optional RA. */
4273 case 792: /* Shift Right Algebraic Word */
4274 case 794: /* Shift Right Algebraic Doubleword */
4275 case 824: /* Shift Right Algebraic Word Immediate */
4276 case 826: /* Shift Right Algebraic Doubleword Immediate (413) */
4277 case 826 | 1: /* Shift Right Algebraic Doubleword Immediate (413) */
4278 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4279 record_full_arch_list_add_reg (regcache
,
4280 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4282 case 0: /* Compare */
4283 case 32: /* Compare logical */
4284 case 144: /* Move To Condition Register Fields */
4285 /* Move To One Condition Register Field */
4286 case 192: /* Compare Ranged Byte */
4287 case 224: /* Compare Equal Byte */
4288 case 576: /* Move XER to CR Extended */
4289 case 902: /* Paste (should always fail due to single-stepping and
4290 the memory location might not be accessible, so
4292 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4295 /* These write to RT. Update RA if 'update indexed.' */
4296 case 53: /* Load Doubleword with Update Indexed */
4297 case 119: /* Load Byte and Zero with Update Indexed */
4298 case 311: /* Load Halfword and Zero with Update Indexed */
4299 case 55: /* Load Word and Zero with Update Indexed */
4300 case 375: /* Load Halfword Algebraic with Update Indexed */
4301 case 373: /* Load Word Algebraic with Update Indexed */
4302 record_full_arch_list_add_reg (regcache
,
4303 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4305 case 21: /* Load Doubleword Indexed */
4306 case 52: /* Load Byte And Reserve Indexed */
4307 case 116: /* Load Halfword And Reserve Indexed */
4308 case 20: /* Load Word And Reserve Indexed */
4309 case 84: /* Load Doubleword And Reserve Indexed */
4310 case 87: /* Load Byte and Zero Indexed */
4311 case 279: /* Load Halfword and Zero Indexed */
4312 case 23: /* Load Word and Zero Indexed */
4313 case 343: /* Load Halfword Algebraic Indexed */
4314 case 341: /* Load Word Algebraic Indexed */
4315 case 790: /* Load Halfword Byte-Reverse Indexed */
4316 case 534: /* Load Word Byte-Reverse Indexed */
4317 case 532: /* Load Doubleword Byte-Reverse Indexed */
4318 case 582: /* Load Word Atomic */
4319 case 614: /* Load Doubleword Atomic */
4320 case 265: /* Modulo Unsigned Doubleword */
4321 case 777: /* Modulo Signed Doubleword */
4322 case 267: /* Modulo Unsigned Word */
4323 case 779: /* Modulo Signed Word */
4324 record_full_arch_list_add_reg (regcache
,
4325 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4328 case 597: /* Load String Word Immediate */
4329 case 533: /* Load String Word Indexed */
4338 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &xer
);
4339 nr
= PPC_XER_NB (xer
);
4344 /* If n=0, the contents of register RT are undefined. */
4348 for (i
= 0; i
< nr
; i
++)
4349 record_full_arch_list_add_reg (regcache
,
4350 tdep
->ppc_gp0_regnum
4351 + ((PPC_RT (insn
) + i
) & 0x1f));
4354 case 276: /* Load Quadword And Reserve Indexed */
4355 tmp
= tdep
->ppc_gp0_regnum
+ (PPC_RT (insn
) & ~1);
4356 record_full_arch_list_add_reg (regcache
, tmp
);
4357 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
4360 /* These write VRT. */
4361 case 6: /* Load Vector for Shift Left Indexed */
4362 case 38: /* Load Vector for Shift Right Indexed */
4363 case 7: /* Load Vector Element Byte Indexed */
4364 case 39: /* Load Vector Element Halfword Indexed */
4365 case 71: /* Load Vector Element Word Indexed */
4366 case 103: /* Load Vector Indexed */
4367 case 359: /* Load Vector Indexed LRU */
4368 record_full_arch_list_add_reg (regcache
,
4369 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4372 /* These write FRT. Update RA if 'update indexed.' */
4373 case 567: /* Load Floating-Point Single with Update Indexed */
4374 case 631: /* Load Floating-Point Double with Update Indexed */
4375 record_full_arch_list_add_reg (regcache
,
4376 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4378 case 535: /* Load Floating-Point Single Indexed */
4379 case 599: /* Load Floating-Point Double Indexed */
4380 case 855: /* Load Floating-Point as Integer Word Algebraic Indexed */
4381 case 887: /* Load Floating-Point as Integer Word and Zero Indexed */
4382 record_full_arch_list_add_reg (regcache
,
4383 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4386 case 791: /* Load Floating-Point Double Pair Indexed */
4387 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
4388 record_full_arch_list_add_reg (regcache
, tmp
);
4389 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
4392 case 179: /* Move To VSR Doubleword */
4393 case 211: /* Move To VSR Word Algebraic */
4394 case 243: /* Move To VSR Word and Zero */
4395 case 588: /* Load VSX Scalar Doubleword Indexed */
4396 case 524: /* Load VSX Scalar Single-Precision Indexed */
4397 case 76: /* Load VSX Scalar as Integer Word Algebraic Indexed */
4398 case 12: /* Load VSX Scalar as Integer Word and Zero Indexed */
4399 case 844: /* Load VSX Vector Doubleword*2 Indexed */
4400 case 332: /* Load VSX Vector Doubleword & Splat Indexed */
4401 case 780: /* Load VSX Vector Word*4 Indexed */
4402 case 268: /* Load VSX Vector Indexed */
4403 case 364: /* Load VSX Vector Word & Splat Indexed */
4404 case 812: /* Load VSX Vector Halfword*8 Indexed */
4405 case 876: /* Load VSX Vector Byte*16 Indexed */
4406 case 269: /* Load VSX Vector with Length */
4407 case 301: /* Load VSX Vector Left-justified with Length */
4408 case 781: /* Load VSX Scalar as Integer Byte & Zero Indexed */
4409 case 813: /* Load VSX Scalar as Integer Halfword & Zero Indexed */
4410 case 403: /* Move To VSR Word & Splat */
4411 case 435: /* Move To VSR Double Doubleword */
4412 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
4415 /* These write RA. Update CR if RC is set. */
4416 case 24: /* Shift Left Word */
4417 case 26: /* Count Leading Zeros Word */
4418 case 27: /* Shift Left Doubleword */
4420 case 58: /* Count Leading Zeros Doubleword */
4421 case 60: /* AND with Complement */
4423 case 284: /* Equivalent */
4425 case 476: /* NAND */
4426 case 412: /* OR with Complement */
4428 case 536: /* Shift Right Word */
4429 case 539: /* Shift Right Doubleword */
4430 case 922: /* Extend Sign Halfword */
4431 case 954: /* Extend Sign Byte */
4432 case 986: /* Extend Sign Word */
4433 case 538: /* Count Trailing Zeros Word */
4434 case 570: /* Count Trailing Zeros Doubleword */
4435 case 890: /* Extend-Sign Word and Shift Left Immediate (445) */
4436 case 890 | 1: /* Extend-Sign Word and Shift Left Immediate (445) */
4438 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4439 record_full_arch_list_add_reg (regcache
,
4440 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4444 case 181: /* Store Doubleword with Update Indexed */
4445 case 183: /* Store Word with Update Indexed */
4446 case 247: /* Store Byte with Update Indexed */
4447 case 439: /* Store Half Word with Update Indexed */
4448 case 695: /* Store Floating-Point Single with Update Indexed */
4449 case 759: /* Store Floating-Point Double with Update Indexed */
4450 record_full_arch_list_add_reg (regcache
,
4451 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4453 case 135: /* Store Vector Element Byte Indexed */
4454 case 167: /* Store Vector Element Halfword Indexed */
4455 case 199: /* Store Vector Element Word Indexed */
4456 case 231: /* Store Vector Indexed */
4457 case 487: /* Store Vector Indexed LRU */
4458 case 716: /* Store VSX Scalar Doubleword Indexed */
4459 case 140: /* Store VSX Scalar as Integer Word Indexed */
4460 case 652: /* Store VSX Scalar Single-Precision Indexed */
4461 case 972: /* Store VSX Vector Doubleword*2 Indexed */
4462 case 908: /* Store VSX Vector Word*4 Indexed */
4463 case 149: /* Store Doubleword Indexed */
4464 case 151: /* Store Word Indexed */
4465 case 215: /* Store Byte Indexed */
4466 case 407: /* Store Half Word Indexed */
4467 case 694: /* Store Byte Conditional Indexed */
4468 case 726: /* Store Halfword Conditional Indexed */
4469 case 150: /* Store Word Conditional Indexed */
4470 case 214: /* Store Doubleword Conditional Indexed */
4471 case 182: /* Store Quadword Conditional Indexed */
4472 case 662: /* Store Word Byte-Reverse Indexed */
4473 case 918: /* Store Halfword Byte-Reverse Indexed */
4474 case 660: /* Store Doubleword Byte-Reverse Indexed */
4475 case 663: /* Store Floating-Point Single Indexed */
4476 case 727: /* Store Floating-Point Double Indexed */
4477 case 919: /* Store Floating-Point Double Pair Indexed */
4478 case 983: /* Store Floating-Point as Integer Word Indexed */
4479 case 396: /* Store VSX Vector Indexed */
4480 case 940: /* Store VSX Vector Halfword*8 Indexed */
4481 case 1004: /* Store VSX Vector Byte*16 Indexed */
4482 case 909: /* Store VSX Scalar as Integer Byte Indexed */
4483 case 941: /* Store VSX Scalar as Integer Halfword Indexed */
4484 if (ext
== 694 || ext
== 726 || ext
== 150 || ext
== 214 || ext
== 182)
4485 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4488 if (PPC_RA (insn
) != 0)
4489 regcache_raw_read_unsigned (regcache
,
4490 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4491 regcache_raw_read_unsigned (regcache
,
4492 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
4497 case 183: /* Store Word with Update Indexed */
4498 case 199: /* Store Vector Element Word Indexed */
4499 case 140: /* Store VSX Scalar as Integer Word Indexed */
4500 case 652: /* Store VSX Scalar Single-Precision Indexed */
4501 case 151: /* Store Word Indexed */
4502 case 150: /* Store Word Conditional Indexed */
4503 case 662: /* Store Word Byte-Reverse Indexed */
4504 case 663: /* Store Floating-Point Single Indexed */
4505 case 695: /* Store Floating-Point Single with Update Indexed */
4506 case 983: /* Store Floating-Point as Integer Word Indexed */
4509 case 247: /* Store Byte with Update Indexed */
4510 case 135: /* Store Vector Element Byte Indexed */
4511 case 215: /* Store Byte Indexed */
4512 case 694: /* Store Byte Conditional Indexed */
4513 case 909: /* Store VSX Scalar as Integer Byte Indexed */
4516 case 439: /* Store Halfword with Update Indexed */
4517 case 167: /* Store Vector Element Halfword Indexed */
4518 case 407: /* Store Halfword Indexed */
4519 case 726: /* Store Halfword Conditional Indexed */
4520 case 918: /* Store Halfword Byte-Reverse Indexed */
4521 case 941: /* Store VSX Scalar as Integer Halfword Indexed */
4524 case 181: /* Store Doubleword with Update Indexed */
4525 case 716: /* Store VSX Scalar Doubleword Indexed */
4526 case 149: /* Store Doubleword Indexed */
4527 case 214: /* Store Doubleword Conditional Indexed */
4528 case 660: /* Store Doubleword Byte-Reverse Indexed */
4529 case 727: /* Store Floating-Point Double Indexed */
4530 case 759: /* Store Floating-Point Double with Update Indexed */
4533 case 972: /* Store VSX Vector Doubleword*2 Indexed */
4534 case 908: /* Store VSX Vector Word*4 Indexed */
4535 case 182: /* Store Quadword Conditional Indexed */
4536 case 231: /* Store Vector Indexed */
4537 case 487: /* Store Vector Indexed LRU */
4538 case 919: /* Store Floating-Point Double Pair Indexed */
4539 case 396: /* Store VSX Vector Indexed */
4540 case 940: /* Store VSX Vector Halfword*8 Indexed */
4541 case 1004: /* Store VSX Vector Byte*16 Indexed */
4548 /* Align address for Store Vector instructions. */
4551 case 167: /* Store Vector Element Halfword Indexed */
4552 addr
= addr
& ~0x1ULL
;
4555 case 199: /* Store Vector Element Word Indexed */
4556 addr
= addr
& ~0x3ULL
;
4559 case 231: /* Store Vector Indexed */
4560 case 487: /* Store Vector Indexed LRU */
4561 addr
= addr
& ~0xfULL
;
4565 record_full_arch_list_add_mem (addr
, size
);
4568 case 397: /* Store VSX Vector with Length */
4569 case 429: /* Store VSX Vector Left-justified with Length */
4571 if (PPC_RA (insn
) != 0)
4572 regcache_raw_read_unsigned (regcache
,
4573 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4575 regcache_raw_read_unsigned (regcache
,
4576 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
4577 /* Store up to 16 bytes. */
4578 nb
= (rb
& 0xff) > 16 ? 16 : (rb
& 0xff);
4580 record_full_arch_list_add_mem (ea
, nb
);
4583 case 710: /* Store Word Atomic */
4584 case 742: /* Store Doubleword Atomic */
4586 if (PPC_RA (insn
) != 0)
4587 regcache_raw_read_unsigned (regcache
,
4588 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4592 case 710: /* Store Word Atomic */
4595 case 742: /* Store Doubleword Atomic */
4601 record_full_arch_list_add_mem (ea
, size
);
4604 case 725: /* Store String Word Immediate */
4606 if (PPC_RA (insn
) != 0)
4607 regcache_raw_read_unsigned (regcache
,
4608 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4615 record_full_arch_list_add_mem (ea
, nb
);
4619 case 661: /* Store String Word Indexed */
4621 if (PPC_RA (insn
) != 0)
4622 regcache_raw_read_unsigned (regcache
,
4623 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4626 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &xer
);
4627 nb
= PPC_XER_NB (xer
);
4631 regcache_raw_read_unsigned (regcache
,
4632 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
),
4635 record_full_arch_list_add_mem (ea
, nb
);
4640 case 467: /* Move To Special Purpose Register */
4641 switch (PPC_SPR (insn
))
4644 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4647 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
4650 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
4652 case 256: /* VRSAVE */
4653 record_full_arch_list_add_reg (regcache
, tdep
->ppc_vrsave_regnum
);
4659 case 147: /* Move To Split Little Endian */
4660 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ps_regnum
);
4663 case 512: /* Move to Condition Register from XER */
4664 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4665 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4668 case 4: /* Trap Word */
4669 case 68: /* Trap Doubleword */
4670 case 430: /* Clear BHRB */
4671 case 598: /* Synchronize */
4672 case 62: /* Wait for Interrupt */
4674 case 22: /* Instruction Cache Block Touch */
4675 case 854: /* Enforce In-order Execution of I/O */
4676 case 246: /* Data Cache Block Touch for Store */
4677 case 54: /* Data Cache Block Store */
4678 case 86: /* Data Cache Block Flush */
4679 case 278: /* Data Cache Block Touch */
4680 case 758: /* Data Cache Block Allocate */
4681 case 982: /* Instruction Cache Block Invalidate */
4682 case 774: /* Copy */
4683 case 838: /* CP_Abort */
4686 case 654: /* Transaction Begin */
4687 case 686: /* Transaction End */
4688 case 750: /* Transaction Suspend or Resume */
4689 case 782: /* Transaction Abort Word Conditional */
4690 case 814: /* Transaction Abort Doubleword Conditional */
4691 case 846: /* Transaction Abort Word Conditional Immediate */
4692 case 878: /* Transaction Abort Doubleword Conditional Immediate */
4693 case 910: /* Transaction Abort */
4694 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ps_regnum
);
4696 case 718: /* Transaction Check */
4697 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4700 case 1014: /* Data Cache Block set to Zero */
4701 if (target_auxv_search (current_top_target (), AT_DCACHEBSIZE
, &at_dcsz
) <= 0
4703 at_dcsz
= 128; /* Assume 128-byte cache line size (POWER8) */
4706 if (PPC_RA (insn
) != 0)
4707 regcache_raw_read_unsigned (regcache
,
4708 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4709 regcache_raw_read_unsigned (regcache
,
4710 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
4711 ea
= (ra
+ rb
) & ~((ULONGEST
) (at_dcsz
- 1));
4712 record_full_arch_list_add_mem (ea
, at_dcsz
);
4717 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4718 "at %s, 31-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4722 /* Parse and record instructions of primary opcode-59 at ADDR.
4723 Return 0 if successful. */
4726 ppc_process_record_op59 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4727 CORE_ADDR addr
, uint32_t insn
)
4729 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4730 int ext
= PPC_EXTOP (insn
);
4734 case 18: /* Floating Divide */
4735 case 20: /* Floating Subtract */
4736 case 21: /* Floating Add */
4737 case 22: /* Floating Square Root */
4738 case 24: /* Floating Reciprocal Estimate */
4739 case 25: /* Floating Multiply */
4740 case 26: /* Floating Reciprocal Square Root Estimate */
4741 case 28: /* Floating Multiply-Subtract */
4742 case 29: /* Floating Multiply-Add */
4743 case 30: /* Floating Negative Multiply-Subtract */
4744 case 31: /* Floating Negative Multiply-Add */
4745 record_full_arch_list_add_reg (regcache
,
4746 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4748 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4749 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4756 case 2: /* DFP Add */
4757 case 3: /* DFP Quantize */
4758 case 34: /* DFP Multiply */
4759 case 35: /* DFP Reround */
4760 case 67: /* DFP Quantize Immediate */
4761 case 99: /* DFP Round To FP Integer With Inexact */
4762 case 227: /* DFP Round To FP Integer Without Inexact */
4763 case 258: /* DFP Convert To DFP Long! */
4764 case 290: /* DFP Convert To Fixed */
4765 case 514: /* DFP Subtract */
4766 case 546: /* DFP Divide */
4767 case 770: /* DFP Round To DFP Short! */
4768 case 802: /* DFP Convert From Fixed */
4769 case 834: /* DFP Encode BCD To DPD */
4771 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4772 record_full_arch_list_add_reg (regcache
,
4773 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4774 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4777 case 130: /* DFP Compare Ordered */
4778 case 162: /* DFP Test Exponent */
4779 case 194: /* DFP Test Data Class */
4780 case 226: /* DFP Test Data Group */
4781 case 642: /* DFP Compare Unordered */
4782 case 674: /* DFP Test Significance */
4783 case 675: /* DFP Test Significance Immediate */
4784 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4785 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4788 case 66: /* DFP Shift Significand Left Immediate */
4789 case 98: /* DFP Shift Significand Right Immediate */
4790 case 322: /* DFP Decode DPD To BCD */
4791 case 354: /* DFP Extract Biased Exponent */
4792 case 866: /* DFP Insert Biased Exponent */
4793 record_full_arch_list_add_reg (regcache
,
4794 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4796 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4799 case 846: /* Floating Convert From Integer Doubleword Single */
4800 case 974: /* Floating Convert From Integer Doubleword Unsigned
4802 record_full_arch_list_add_reg (regcache
,
4803 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4805 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4806 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4811 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4812 "at %s, 59-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4816 /* Parse and record instructions of primary opcode-60 at ADDR.
4817 Return 0 if successful. */
4820 ppc_process_record_op60 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4821 CORE_ADDR addr
, uint32_t insn
)
4823 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4824 int ext
= PPC_EXTOP (insn
);
4828 case 0: /* VSX Scalar Add Single-Precision */
4829 case 32: /* VSX Scalar Add Double-Precision */
4830 case 24: /* VSX Scalar Divide Single-Precision */
4831 case 56: /* VSX Scalar Divide Double-Precision */
4832 case 176: /* VSX Scalar Copy Sign Double-Precision */
4833 case 33: /* VSX Scalar Multiply-Add Double-Precision */
4834 case 41: /* ditto */
4835 case 1: /* VSX Scalar Multiply-Add Single-Precision */
4837 case 160: /* VSX Scalar Maximum Double-Precision */
4838 case 168: /* VSX Scalar Minimum Double-Precision */
4839 case 49: /* VSX Scalar Multiply-Subtract Double-Precision */
4840 case 57: /* ditto */
4841 case 17: /* VSX Scalar Multiply-Subtract Single-Precision */
4842 case 25: /* ditto */
4843 case 48: /* VSX Scalar Multiply Double-Precision */
4844 case 16: /* VSX Scalar Multiply Single-Precision */
4845 case 161: /* VSX Scalar Negative Multiply-Add Double-Precision */
4846 case 169: /* ditto */
4847 case 129: /* VSX Scalar Negative Multiply-Add Single-Precision */
4848 case 137: /* ditto */
4849 case 177: /* VSX Scalar Negative Multiply-Subtract Double-Precision */
4850 case 185: /* ditto */
4851 case 145: /* VSX Scalar Negative Multiply-Subtract Single-Precision */
4852 case 153: /* ditto */
4853 case 40: /* VSX Scalar Subtract Double-Precision */
4854 case 8: /* VSX Scalar Subtract Single-Precision */
4855 case 96: /* VSX Vector Add Double-Precision */
4856 case 64: /* VSX Vector Add Single-Precision */
4857 case 120: /* VSX Vector Divide Double-Precision */
4858 case 88: /* VSX Vector Divide Single-Precision */
4859 case 97: /* VSX Vector Multiply-Add Double-Precision */
4860 case 105: /* ditto */
4861 case 65: /* VSX Vector Multiply-Add Single-Precision */
4862 case 73: /* ditto */
4863 case 224: /* VSX Vector Maximum Double-Precision */
4864 case 192: /* VSX Vector Maximum Single-Precision */
4865 case 232: /* VSX Vector Minimum Double-Precision */
4866 case 200: /* VSX Vector Minimum Single-Precision */
4867 case 113: /* VSX Vector Multiply-Subtract Double-Precision */
4868 case 121: /* ditto */
4869 case 81: /* VSX Vector Multiply-Subtract Single-Precision */
4870 case 89: /* ditto */
4871 case 112: /* VSX Vector Multiply Double-Precision */
4872 case 80: /* VSX Vector Multiply Single-Precision */
4873 case 225: /* VSX Vector Negative Multiply-Add Double-Precision */
4874 case 233: /* ditto */
4875 case 193: /* VSX Vector Negative Multiply-Add Single-Precision */
4876 case 201: /* ditto */
4877 case 241: /* VSX Vector Negative Multiply-Subtract Double-Precision */
4878 case 249: /* ditto */
4879 case 209: /* VSX Vector Negative Multiply-Subtract Single-Precision */
4880 case 217: /* ditto */
4881 case 104: /* VSX Vector Subtract Double-Precision */
4882 case 72: /* VSX Vector Subtract Single-Precision */
4883 case 128: /* VSX Scalar Maximum Type-C Double-Precision */
4884 case 136: /* VSX Scalar Minimum Type-C Double-Precision */
4885 case 144: /* VSX Scalar Maximum Type-J Double-Precision */
4886 case 152: /* VSX Scalar Minimum Type-J Double-Precision */
4887 case 3: /* VSX Scalar Compare Equal Double-Precision */
4888 case 11: /* VSX Scalar Compare Greater Than Double-Precision */
4889 case 19: /* VSX Scalar Compare Greater Than or Equal
4891 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4893 case 240: /* VSX Vector Copy Sign Double-Precision */
4894 case 208: /* VSX Vector Copy Sign Single-Precision */
4895 case 130: /* VSX Logical AND */
4896 case 138: /* VSX Logical AND with Complement */
4897 case 186: /* VSX Logical Equivalence */
4898 case 178: /* VSX Logical NAND */
4899 case 170: /* VSX Logical OR with Complement */
4900 case 162: /* VSX Logical NOR */
4901 case 146: /* VSX Logical OR */
4902 case 154: /* VSX Logical XOR */
4903 case 18: /* VSX Merge High Word */
4904 case 50: /* VSX Merge Low Word */
4905 case 10: /* VSX Permute Doubleword Immediate (DM=0) */
4906 case 10 | 0x20: /* VSX Permute Doubleword Immediate (DM=1) */
4907 case 10 | 0x40: /* VSX Permute Doubleword Immediate (DM=2) */
4908 case 10 | 0x60: /* VSX Permute Doubleword Immediate (DM=3) */
4909 case 2: /* VSX Shift Left Double by Word Immediate (SHW=0) */
4910 case 2 | 0x20: /* VSX Shift Left Double by Word Immediate (SHW=1) */
4911 case 2 | 0x40: /* VSX Shift Left Double by Word Immediate (SHW=2) */
4912 case 2 | 0x60: /* VSX Shift Left Double by Word Immediate (SHW=3) */
4913 case 216: /* VSX Vector Insert Exponent Single-Precision */
4914 case 248: /* VSX Vector Insert Exponent Double-Precision */
4915 case 26: /* VSX Vector Permute */
4916 case 58: /* VSX Vector Permute Right-indexed */
4917 case 213: /* VSX Vector Test Data Class Single-Precision (DC=0) */
4918 case 213 | 0x8: /* VSX Vector Test Data Class Single-Precision (DC=1) */
4919 case 245: /* VSX Vector Test Data Class Double-Precision (DC=0) */
4920 case 245 | 0x8: /* VSX Vector Test Data Class Double-Precision (DC=1) */
4921 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
4924 case 61: /* VSX Scalar Test for software Divide Double-Precision */
4925 case 125: /* VSX Vector Test for software Divide Double-Precision */
4926 case 93: /* VSX Vector Test for software Divide Single-Precision */
4927 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4930 case 35: /* VSX Scalar Compare Unordered Double-Precision */
4931 case 43: /* VSX Scalar Compare Ordered Double-Precision */
4932 case 59: /* VSX Scalar Compare Exponents Double-Precision */
4933 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4934 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4938 switch ((ext
>> 2) & 0x7f) /* Mask out Rc-bit. */
4940 case 99: /* VSX Vector Compare Equal To Double-Precision */
4941 case 67: /* VSX Vector Compare Equal To Single-Precision */
4942 case 115: /* VSX Vector Compare Greater Than or
4943 Equal To Double-Precision */
4944 case 83: /* VSX Vector Compare Greater Than or
4945 Equal To Single-Precision */
4946 case 107: /* VSX Vector Compare Greater Than Double-Precision */
4947 case 75: /* VSX Vector Compare Greater Than Single-Precision */
4949 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4950 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4951 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
4957 case 265: /* VSX Scalar round Double-Precision to
4958 Single-Precision and Convert to
4959 Single-Precision format */
4960 case 344: /* VSX Scalar truncate Double-Precision to
4961 Integer and Convert to Signed Integer
4962 Doubleword format with Saturate */
4963 case 88: /* VSX Scalar truncate Double-Precision to
4964 Integer and Convert to Signed Integer Word
4965 Format with Saturate */
4966 case 328: /* VSX Scalar truncate Double-Precision integer
4967 and Convert to Unsigned Integer Doubleword
4968 Format with Saturate */
4969 case 72: /* VSX Scalar truncate Double-Precision to
4970 Integer and Convert to Unsigned Integer Word
4971 Format with Saturate */
4972 case 329: /* VSX Scalar Convert Single-Precision to
4973 Double-Precision format */
4974 case 376: /* VSX Scalar Convert Signed Integer
4975 Doubleword to floating-point format and
4976 Round to Double-Precision format */
4977 case 312: /* VSX Scalar Convert Signed Integer
4978 Doubleword to floating-point format and
4979 round to Single-Precision */
4980 case 360: /* VSX Scalar Convert Unsigned Integer
4981 Doubleword to floating-point format and
4982 Round to Double-Precision format */
4983 case 296: /* VSX Scalar Convert Unsigned Integer
4984 Doubleword to floating-point format and
4985 Round to Single-Precision */
4986 case 73: /* VSX Scalar Round to Double-Precision Integer
4987 Using Round to Nearest Away */
4988 case 107: /* VSX Scalar Round to Double-Precision Integer
4989 Exact using Current rounding mode */
4990 case 121: /* VSX Scalar Round to Double-Precision Integer
4991 Using Round toward -Infinity */
4992 case 105: /* VSX Scalar Round to Double-Precision Integer
4993 Using Round toward +Infinity */
4994 case 89: /* VSX Scalar Round to Double-Precision Integer
4995 Using Round toward Zero */
4996 case 90: /* VSX Scalar Reciprocal Estimate Double-Precision */
4997 case 26: /* VSX Scalar Reciprocal Estimate Single-Precision */
4998 case 281: /* VSX Scalar Round to Single-Precision */
4999 case 74: /* VSX Scalar Reciprocal Square Root Estimate
5001 case 10: /* VSX Scalar Reciprocal Square Root Estimate
5003 case 75: /* VSX Scalar Square Root Double-Precision */
5004 case 11: /* VSX Scalar Square Root Single-Precision */
5005 case 393: /* VSX Vector round Double-Precision to
5006 Single-Precision and Convert to
5007 Single-Precision format */
5008 case 472: /* VSX Vector truncate Double-Precision to
5009 Integer and Convert to Signed Integer
5010 Doubleword format with Saturate */
5011 case 216: /* VSX Vector truncate Double-Precision to
5012 Integer and Convert to Signed Integer Word
5013 Format with Saturate */
5014 case 456: /* VSX Vector truncate Double-Precision to
5015 Integer and Convert to Unsigned Integer
5016 Doubleword format with Saturate */
5017 case 200: /* VSX Vector truncate Double-Precision to
5018 Integer and Convert to Unsigned Integer Word
5019 Format with Saturate */
5020 case 457: /* VSX Vector Convert Single-Precision to
5021 Double-Precision format */
5022 case 408: /* VSX Vector truncate Single-Precision to
5023 Integer and Convert to Signed Integer
5024 Doubleword format with Saturate */
5025 case 152: /* VSX Vector truncate Single-Precision to
5026 Integer and Convert to Signed Integer Word
5027 Format with Saturate */
5028 case 392: /* VSX Vector truncate Single-Precision to
5029 Integer and Convert to Unsigned Integer
5030 Doubleword format with Saturate */
5031 case 136: /* VSX Vector truncate Single-Precision to
5032 Integer and Convert to Unsigned Integer Word
5033 Format with Saturate */
5034 case 504: /* VSX Vector Convert and round Signed Integer
5035 Doubleword to Double-Precision format */
5036 case 440: /* VSX Vector Convert and round Signed Integer
5037 Doubleword to Single-Precision format */
5038 case 248: /* VSX Vector Convert Signed Integer Word to
5039 Double-Precision format */
5040 case 184: /* VSX Vector Convert and round Signed Integer
5041 Word to Single-Precision format */
5042 case 488: /* VSX Vector Convert and round Unsigned
5043 Integer Doubleword to Double-Precision format */
5044 case 424: /* VSX Vector Convert and round Unsigned
5045 Integer Doubleword to Single-Precision format */
5046 case 232: /* VSX Vector Convert and round Unsigned
5047 Integer Word to Double-Precision format */
5048 case 168: /* VSX Vector Convert and round Unsigned
5049 Integer Word to Single-Precision format */
5050 case 201: /* VSX Vector Round to Double-Precision
5051 Integer using round to Nearest Away */
5052 case 235: /* VSX Vector Round to Double-Precision
5053 Integer Exact using Current rounding mode */
5054 case 249: /* VSX Vector Round to Double-Precision
5055 Integer using round toward -Infinity */
5056 case 233: /* VSX Vector Round to Double-Precision
5057 Integer using round toward +Infinity */
5058 case 217: /* VSX Vector Round to Double-Precision
5059 Integer using round toward Zero */
5060 case 218: /* VSX Vector Reciprocal Estimate Double-Precision */
5061 case 154: /* VSX Vector Reciprocal Estimate Single-Precision */
5062 case 137: /* VSX Vector Round to Single-Precision Integer
5063 Using Round to Nearest Away */
5064 case 171: /* VSX Vector Round to Single-Precision Integer
5065 Exact Using Current rounding mode */
5066 case 185: /* VSX Vector Round to Single-Precision Integer
5067 Using Round toward -Infinity */
5068 case 169: /* VSX Vector Round to Single-Precision Integer
5069 Using Round toward +Infinity */
5070 case 153: /* VSX Vector Round to Single-Precision Integer
5071 Using round toward Zero */
5072 case 202: /* VSX Vector Reciprocal Square Root Estimate
5074 case 138: /* VSX Vector Reciprocal Square Root Estimate
5076 case 203: /* VSX Vector Square Root Double-Precision */
5077 case 139: /* VSX Vector Square Root Single-Precision */
5078 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5080 case 345: /* VSX Scalar Absolute Value Double-Precision */
5081 case 267: /* VSX Scalar Convert Scalar Single-Precision to
5082 Vector Single-Precision format Non-signalling */
5083 case 331: /* VSX Scalar Convert Single-Precision to
5084 Double-Precision format Non-signalling */
5085 case 361: /* VSX Scalar Negative Absolute Value Double-Precision */
5086 case 377: /* VSX Scalar Negate Double-Precision */
5087 case 473: /* VSX Vector Absolute Value Double-Precision */
5088 case 409: /* VSX Vector Absolute Value Single-Precision */
5089 case 489: /* VSX Vector Negative Absolute Value Double-Precision */
5090 case 425: /* VSX Vector Negative Absolute Value Single-Precision */
5091 case 505: /* VSX Vector Negate Double-Precision */
5092 case 441: /* VSX Vector Negate Single-Precision */
5093 case 164: /* VSX Splat Word */
5094 case 165: /* VSX Vector Extract Unsigned Word */
5095 case 181: /* VSX Vector Insert Word */
5096 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5099 case 298: /* VSX Scalar Test Data Class Single-Precision */
5100 case 362: /* VSX Scalar Test Data Class Double-Precision */
5101 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5103 case 106: /* VSX Scalar Test for software Square Root
5105 case 234: /* VSX Vector Test for software Square Root
5107 case 170: /* VSX Vector Test for software Square Root
5109 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5113 switch (PPC_FIELD (insn
, 11, 5))
5115 case 0: /* VSX Scalar Extract Exponent Double-Precision */
5116 case 1: /* VSX Scalar Extract Significand Double-Precision */
5117 record_full_arch_list_add_reg (regcache
,
5118 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5120 case 16: /* VSX Scalar Convert Half-Precision format to
5121 Double-Precision format */
5122 case 17: /* VSX Scalar round & Convert Double-Precision format
5123 to Half-Precision format */
5124 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5125 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5131 switch (PPC_FIELD (insn
, 11, 5))
5133 case 24: /* VSX Vector Convert Half-Precision format to
5134 Single-Precision format */
5135 case 25: /* VSX Vector round and Convert Single-Precision format
5136 to Half-Precision format */
5137 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5139 case 0: /* VSX Vector Extract Exponent Double-Precision */
5140 case 1: /* VSX Vector Extract Significand Double-Precision */
5141 case 7: /* VSX Vector Byte-Reverse Halfword */
5142 case 8: /* VSX Vector Extract Exponent Single-Precision */
5143 case 9: /* VSX Vector Extract Significand Single-Precision */
5144 case 15: /* VSX Vector Byte-Reverse Word */
5145 case 23: /* VSX Vector Byte-Reverse Doubleword */
5146 case 31: /* VSX Vector Byte-Reverse Quadword */
5147 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5155 case 360: /* VSX Vector Splat Immediate Byte */
5156 if (PPC_FIELD (insn
, 11, 2) == 0)
5158 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5162 case 918: /* VSX Scalar Insert Exponent Double-Precision */
5163 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5167 if (((ext
>> 3) & 0x3) == 3) /* VSX Select */
5169 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5173 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5174 "at %s, 60-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5178 /* Parse and record instructions of primary opcode-61 at ADDR.
5179 Return 0 if successful. */
5182 ppc_process_record_op61 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5183 CORE_ADDR addr
, uint32_t insn
)
5185 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5191 case 0: /* Store Floating-Point Double Pair */
5192 case 2: /* Store VSX Scalar Doubleword */
5193 case 3: /* Store VSX Scalar Single */
5194 if (PPC_RA (insn
) != 0)
5195 regcache_raw_read_unsigned (regcache
,
5196 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5198 ea
+= PPC_DS (insn
) << 2;
5201 case 0: /* Store Floating-Point Double Pair */
5204 case 2: /* Store VSX Scalar Doubleword */
5207 case 3: /* Store VSX Scalar Single */
5213 record_full_arch_list_add_mem (ea
, size
);
5219 case 1: /* Load VSX Vector */
5220 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5222 case 5: /* Store VSX Vector */
5223 if (PPC_RA (insn
) != 0)
5224 regcache_raw_read_unsigned (regcache
,
5225 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5227 ea
+= PPC_DQ (insn
) << 4;
5228 record_full_arch_list_add_mem (ea
, 16);
5232 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5233 "at %s.\n", insn
, paddress (gdbarch
, addr
));
5237 /* Parse and record instructions of primary opcode-63 at ADDR.
5238 Return 0 if successful. */
5241 ppc_process_record_op63 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5242 CORE_ADDR addr
, uint32_t insn
)
5244 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5245 int ext
= PPC_EXTOP (insn
);
5250 case 18: /* Floating Divide */
5251 case 20: /* Floating Subtract */
5252 case 21: /* Floating Add */
5253 case 22: /* Floating Square Root */
5254 case 24: /* Floating Reciprocal Estimate */
5255 case 25: /* Floating Multiply */
5256 case 26: /* Floating Reciprocal Square Root Estimate */
5257 case 28: /* Floating Multiply-Subtract */
5258 case 29: /* Floating Multiply-Add */
5259 case 30: /* Floating Negative Multiply-Subtract */
5260 case 31: /* Floating Negative Multiply-Add */
5261 record_full_arch_list_add_reg (regcache
,
5262 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5264 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5265 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5268 case 23: /* Floating Select */
5269 record_full_arch_list_add_reg (regcache
,
5270 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5272 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5278 case 5: /* VSX Scalar Round to Quad-Precision Integer */
5279 case 37: /* VSX Scalar Round Quad-Precision to Double-Extended
5281 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5282 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5288 case 2: /* DFP Add Quad */
5289 case 3: /* DFP Quantize Quad */
5290 case 34: /* DFP Multiply Quad */
5291 case 35: /* DFP Reround Quad */
5292 case 67: /* DFP Quantize Immediate Quad */
5293 case 99: /* DFP Round To FP Integer With Inexact Quad */
5294 case 227: /* DFP Round To FP Integer Without Inexact Quad */
5295 case 258: /* DFP Convert To DFP Extended Quad */
5296 case 514: /* DFP Subtract Quad */
5297 case 546: /* DFP Divide Quad */
5298 case 770: /* DFP Round To DFP Long Quad */
5299 case 802: /* DFP Convert From Fixed Quad */
5300 case 834: /* DFP Encode BCD To DPD Quad */
5302 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5303 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
5304 record_full_arch_list_add_reg (regcache
, tmp
);
5305 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5306 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5309 case 130: /* DFP Compare Ordered Quad */
5310 case 162: /* DFP Test Exponent Quad */
5311 case 194: /* DFP Test Data Class Quad */
5312 case 226: /* DFP Test Data Group Quad */
5313 case 642: /* DFP Compare Unordered Quad */
5314 case 674: /* DFP Test Significance Quad */
5315 case 675: /* DFP Test Significance Immediate Quad */
5316 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5317 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5320 case 66: /* DFP Shift Significand Left Immediate Quad */
5321 case 98: /* DFP Shift Significand Right Immediate Quad */
5322 case 322: /* DFP Decode DPD To BCD Quad */
5323 case 866: /* DFP Insert Biased Exponent Quad */
5324 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
5325 record_full_arch_list_add_reg (regcache
, tmp
);
5326 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5328 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5331 case 290: /* DFP Convert To Fixed Quad */
5332 record_full_arch_list_add_reg (regcache
,
5333 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5335 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5336 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5339 case 354: /* DFP Extract Biased Exponent Quad */
5340 record_full_arch_list_add_reg (regcache
,
5341 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5343 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5346 case 12: /* Floating Round to Single-Precision */
5347 case 14: /* Floating Convert To Integer Word */
5348 case 15: /* Floating Convert To Integer Word
5349 with round toward Zero */
5350 case 142: /* Floating Convert To Integer Word Unsigned */
5351 case 143: /* Floating Convert To Integer Word Unsigned
5352 with round toward Zero */
5353 case 392: /* Floating Round to Integer Nearest */
5354 case 424: /* Floating Round to Integer Toward Zero */
5355 case 456: /* Floating Round to Integer Plus */
5356 case 488: /* Floating Round to Integer Minus */
5357 case 814: /* Floating Convert To Integer Doubleword */
5358 case 815: /* Floating Convert To Integer Doubleword
5359 with round toward Zero */
5360 case 846: /* Floating Convert From Integer Doubleword */
5361 case 942: /* Floating Convert To Integer Doubleword Unsigned */
5362 case 943: /* Floating Convert To Integer Doubleword Unsigned
5363 with round toward Zero */
5364 case 974: /* Floating Convert From Integer Doubleword Unsigned */
5365 record_full_arch_list_add_reg (regcache
,
5366 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5368 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5369 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5373 switch (PPC_FIELD (insn
, 11, 5))
5375 case 1: /* Move From FPSCR & Clear Enables */
5376 case 20: /* Move From FPSCR Control & set DRN */
5377 case 21: /* Move From FPSCR Control & set DRN Immediate */
5378 case 22: /* Move From FPSCR Control & set RN */
5379 case 23: /* Move From FPSCR Control & set RN Immediate */
5380 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5382 case 0: /* Move From FPSCR */
5383 case 24: /* Move From FPSCR Lightweight */
5384 if (PPC_FIELD (insn
, 11, 5) == 0 && PPC_RC (insn
))
5385 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5386 record_full_arch_list_add_reg (regcache
,
5387 tdep
->ppc_fp0_regnum
5393 case 8: /* Floating Copy Sign */
5394 case 40: /* Floating Negate */
5395 case 72: /* Floating Move Register */
5396 case 136: /* Floating Negative Absolute Value */
5397 case 264: /* Floating Absolute Value */
5398 record_full_arch_list_add_reg (regcache
,
5399 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5401 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5404 case 838: /* Floating Merge Odd Word */
5405 case 966: /* Floating Merge Even Word */
5406 record_full_arch_list_add_reg (regcache
,
5407 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5410 case 38: /* Move To FPSCR Bit 1 */
5411 case 70: /* Move To FPSCR Bit 0 */
5412 case 134: /* Move To FPSCR Field Immediate */
5413 case 711: /* Move To FPSCR Fields */
5415 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5416 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5419 case 0: /* Floating Compare Unordered */
5420 case 32: /* Floating Compare Ordered */
5421 case 64: /* Move to Condition Register from FPSCR */
5422 case 132: /* VSX Scalar Compare Ordered Quad-Precision */
5423 case 164: /* VSX Scalar Compare Exponents Quad-Precision */
5424 case 644: /* VSX Scalar Compare Unordered Quad-Precision */
5425 case 708: /* VSX Scalar Test Data Class Quad-Precision */
5426 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5428 case 128: /* Floating Test for software Divide */
5429 case 160: /* Floating Test for software Square Root */
5430 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5433 case 4: /* VSX Scalar Add Quad-Precision */
5434 case 36: /* VSX Scalar Multiply Quad-Precision */
5435 case 388: /* VSX Scalar Multiply-Add Quad-Precision */
5436 case 420: /* VSX Scalar Multiply-Subtract Quad-Precision */
5437 case 452: /* VSX Scalar Negative Multiply-Add Quad-Precision */
5438 case 484: /* VSX Scalar Negative Multiply-Subtract
5440 case 516: /* VSX Scalar Subtract Quad-Precision */
5441 case 548: /* VSX Scalar Divide Quad-Precision */
5442 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5444 case 100: /* VSX Scalar Copy Sign Quad-Precision */
5445 case 868: /* VSX Scalar Insert Exponent Quad-Precision */
5446 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5450 switch (PPC_FIELD (insn
, 11, 5))
5452 case 27: /* VSX Scalar Square Root Quad-Precision */
5453 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5455 case 0: /* VSX Scalar Absolute Quad-Precision */
5456 case 2: /* VSX Scalar Extract Exponent Quad-Precision */
5457 case 8: /* VSX Scalar Negative Absolute Quad-Precision */
5458 case 16: /* VSX Scalar Negate Quad-Precision */
5459 case 18: /* VSX Scalar Extract Significand Quad-Precision */
5460 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5466 switch (PPC_FIELD (insn
, 11, 5))
5468 case 1: /* VSX Scalar truncate & Convert Quad-Precision format
5469 to Unsigned Word format */
5470 case 2: /* VSX Scalar Convert Unsigned Doubleword format to
5471 Quad-Precision format */
5472 case 9: /* VSX Scalar truncate & Convert Quad-Precision format
5473 to Signed Word format */
5474 case 10: /* VSX Scalar Convert Signed Doubleword format to
5475 Quad-Precision format */
5476 case 17: /* VSX Scalar truncate & Convert Quad-Precision format
5477 to Unsigned Doubleword format */
5478 case 20: /* VSX Scalar round & Convert Quad-Precision format to
5479 Double-Precision format */
5480 case 22: /* VSX Scalar Convert Double-Precision format to
5481 Quad-Precision format */
5482 case 25: /* VSX Scalar truncate & Convert Quad-Precision format
5483 to Signed Doubleword format */
5484 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5485 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5490 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5491 "at %s, 63-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5495 /* Parse the current instruction and record the values of the registers and
5496 memory that will be changed in current instruction to "record_arch_list".
5497 Return -1 if something wrong. */
5500 ppc_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5503 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5504 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5508 insn
= read_memory_unsigned_integer (addr
, 4, byte_order
);
5509 op6
= PPC_OP6 (insn
);
5513 case 2: /* Trap Doubleword Immediate */
5514 case 3: /* Trap Word Immediate */
5519 if (ppc_process_record_op4 (gdbarch
, regcache
, addr
, insn
) != 0)
5523 case 17: /* System call */
5524 if (PPC_LEV (insn
) != 0)
5527 if (tdep
->ppc_syscall_record
!= NULL
)
5529 if (tdep
->ppc_syscall_record (regcache
) != 0)
5534 printf_unfiltered (_("no syscall record support\n"));
5539 case 7: /* Multiply Low Immediate */
5540 record_full_arch_list_add_reg (regcache
,
5541 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5544 case 8: /* Subtract From Immediate Carrying */
5545 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5546 record_full_arch_list_add_reg (regcache
,
5547 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5550 case 10: /* Compare Logical Immediate */
5551 case 11: /* Compare Immediate */
5552 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5555 case 13: /* Add Immediate Carrying and Record */
5556 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5558 case 12: /* Add Immediate Carrying */
5559 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5561 case 14: /* Add Immediate */
5562 case 15: /* Add Immediate Shifted */
5563 record_full_arch_list_add_reg (regcache
,
5564 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5567 case 16: /* Branch Conditional */
5568 if ((PPC_BO (insn
) & 0x4) == 0)
5569 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
5571 case 18: /* Branch */
5573 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
5577 if (ppc_process_record_op19 (gdbarch
, regcache
, addr
, insn
) != 0)
5581 case 20: /* Rotate Left Word Immediate then Mask Insert */
5582 case 21: /* Rotate Left Word Immediate then AND with Mask */
5583 case 23: /* Rotate Left Word then AND with Mask */
5584 case 30: /* Rotate Left Doubleword Immediate then Clear Left */
5585 /* Rotate Left Doubleword Immediate then Clear Right */
5586 /* Rotate Left Doubleword Immediate then Clear */
5587 /* Rotate Left Doubleword then Clear Left */
5588 /* Rotate Left Doubleword then Clear Right */
5589 /* Rotate Left Doubleword Immediate then Mask Insert */
5591 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5592 record_full_arch_list_add_reg (regcache
,
5593 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5596 case 28: /* AND Immediate */
5597 case 29: /* AND Immediate Shifted */
5598 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5600 case 24: /* OR Immediate */
5601 case 25: /* OR Immediate Shifted */
5602 case 26: /* XOR Immediate */
5603 case 27: /* XOR Immediate Shifted */
5604 record_full_arch_list_add_reg (regcache
,
5605 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5609 if (ppc_process_record_op31 (gdbarch
, regcache
, addr
, insn
) != 0)
5613 case 33: /* Load Word and Zero with Update */
5614 case 35: /* Load Byte and Zero with Update */
5615 case 41: /* Load Halfword and Zero with Update */
5616 case 43: /* Load Halfword Algebraic with Update */
5617 record_full_arch_list_add_reg (regcache
,
5618 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5620 case 32: /* Load Word and Zero */
5621 case 34: /* Load Byte and Zero */
5622 case 40: /* Load Halfword and Zero */
5623 case 42: /* Load Halfword Algebraic */
5624 record_full_arch_list_add_reg (regcache
,
5625 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5628 case 46: /* Load Multiple Word */
5629 for (i
= PPC_RT (insn
); i
< 32; i
++)
5630 record_full_arch_list_add_reg (regcache
, tdep
->ppc_gp0_regnum
+ i
);
5633 case 56: /* Load Quadword */
5634 tmp
= tdep
->ppc_gp0_regnum
+ (PPC_RT (insn
) & ~1);
5635 record_full_arch_list_add_reg (regcache
, tmp
);
5636 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5639 case 49: /* Load Floating-Point Single with Update */
5640 case 51: /* Load Floating-Point Double with Update */
5641 record_full_arch_list_add_reg (regcache
,
5642 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5644 case 48: /* Load Floating-Point Single */
5645 case 50: /* Load Floating-Point Double */
5646 record_full_arch_list_add_reg (regcache
,
5647 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5650 case 47: /* Store Multiple Word */
5654 if (PPC_RA (insn
) != 0)
5655 regcache_raw_read_unsigned (regcache
,
5656 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5659 iaddr
+= PPC_D (insn
);
5660 record_full_arch_list_add_mem (iaddr
, 4 * (32 - PPC_RS (insn
)));
5664 case 37: /* Store Word with Update */
5665 case 39: /* Store Byte with Update */
5666 case 45: /* Store Halfword with Update */
5667 case 53: /* Store Floating-Point Single with Update */
5668 case 55: /* Store Floating-Point Double with Update */
5669 record_full_arch_list_add_reg (regcache
,
5670 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5672 case 36: /* Store Word */
5673 case 38: /* Store Byte */
5674 case 44: /* Store Halfword */
5675 case 52: /* Store Floating-Point Single */
5676 case 54: /* Store Floating-Point Double */
5681 if (PPC_RA (insn
) != 0)
5682 regcache_raw_read_unsigned (regcache
,
5683 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5685 iaddr
+= PPC_D (insn
);
5687 if (op6
== 36 || op6
== 37 || op6
== 52 || op6
== 53)
5689 else if (op6
== 54 || op6
== 55)
5691 else if (op6
== 44 || op6
== 45)
5693 else if (op6
== 38 || op6
== 39)
5698 record_full_arch_list_add_mem (iaddr
, size
);
5705 case 0: /* Load Floating-Point Double Pair */
5706 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_RT (insn
) & ~1);
5707 record_full_arch_list_add_reg (regcache
, tmp
);
5708 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5710 case 2: /* Load VSX Scalar Doubleword */
5711 case 3: /* Load VSX Scalar Single */
5712 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5719 case 58: /* Load Doubleword */
5720 /* Load Doubleword with Update */
5721 /* Load Word Algebraic */
5722 if (PPC_FIELD (insn
, 30, 2) > 2)
5725 record_full_arch_list_add_reg (regcache
,
5726 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5727 if (PPC_BIT (insn
, 31))
5728 record_full_arch_list_add_reg (regcache
,
5729 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5733 if (ppc_process_record_op59 (gdbarch
, regcache
, addr
, insn
) != 0)
5738 if (ppc_process_record_op60 (gdbarch
, regcache
, addr
, insn
) != 0)
5743 if (ppc_process_record_op61 (gdbarch
, regcache
, addr
, insn
) != 0)
5747 case 62: /* Store Doubleword */
5748 /* Store Doubleword with Update */
5749 /* Store Quadword with Update */
5753 int sub2
= PPC_FIELD (insn
, 30, 2);
5758 if (PPC_RA (insn
) != 0)
5759 regcache_raw_read_unsigned (regcache
,
5760 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5763 size
= (sub2
== 2) ? 16 : 8;
5765 iaddr
+= PPC_DS (insn
) << 2;
5766 record_full_arch_list_add_mem (iaddr
, size
);
5768 if (op6
== 62 && sub2
== 1)
5769 record_full_arch_list_add_reg (regcache
,
5770 tdep
->ppc_gp0_regnum
+
5777 if (ppc_process_record_op63 (gdbarch
, regcache
, addr
, insn
) != 0)
5783 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5784 "at %s, %d.\n", insn
, paddress (gdbarch
, addr
), op6
);
5788 if (record_full_arch_list_add_reg (regcache
, PPC_PC_REGNUM
))
5790 if (record_full_arch_list_add_end ())
5795 /* Initialize the current architecture based on INFO. If possible, re-use an
5796 architecture from ARCHES, which is a list of architectures already created
5797 during this debugging session.
5799 Called e.g. at program startup, when reading a core file, and when reading
5802 static struct gdbarch
*
5803 rs6000_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5805 struct gdbarch
*gdbarch
;
5806 struct gdbarch_tdep
*tdep
;
5807 int wordsize
, from_xcoff_exec
, from_elf_exec
;
5808 enum bfd_architecture arch
;
5811 enum auto_boolean soft_float_flag
= powerpc_soft_float_global
;
5813 enum powerpc_long_double_abi long_double_abi
= POWERPC_LONG_DOUBLE_AUTO
;
5814 enum powerpc_vector_abi vector_abi
= powerpc_vector_abi_global
;
5815 enum powerpc_elf_abi elf_abi
= POWERPC_ELF_AUTO
;
5816 int have_fpu
= 1, have_spe
= 0, have_mq
= 0, have_altivec
= 0, have_dfp
= 0,
5818 int tdesc_wordsize
= -1;
5819 const struct target_desc
*tdesc
= info
.target_desc
;
5820 struct tdesc_arch_data
*tdesc_data
= NULL
;
5821 int num_pseudoregs
= 0;
5824 /* INFO may refer to a binary that is not of the PowerPC architecture,
5825 e.g. when debugging a stand-alone SPE executable on a Cell/B.E. system.
5826 In this case, we must not attempt to infer properties of the (PowerPC
5827 side) of the target system from properties of that executable. Trust
5828 the target description instead. */
5830 && bfd_get_arch (info
.abfd
) != bfd_arch_powerpc
5831 && bfd_get_arch (info
.abfd
) != bfd_arch_rs6000
)
5834 from_xcoff_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
5835 bfd_get_flavour (info
.abfd
) == bfd_target_xcoff_flavour
;
5837 from_elf_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
5838 bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
;
5840 /* Check word size. If INFO is from a binary file, infer it from
5841 that, else choose a likely default. */
5842 if (from_xcoff_exec
)
5844 if (bfd_xcoff_is_xcoff64 (info
.abfd
))
5849 else if (from_elf_exec
)
5851 if (elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5856 else if (tdesc_has_registers (tdesc
))
5860 if (info
.bfd_arch_info
!= NULL
&& info
.bfd_arch_info
->bits_per_word
!= 0)
5861 wordsize
= (info
.bfd_arch_info
->bits_per_word
5862 / info
.bfd_arch_info
->bits_per_byte
);
5867 /* Get the architecture and machine from the BFD. */
5868 arch
= info
.bfd_arch_info
->arch
;
5869 mach
= info
.bfd_arch_info
->mach
;
5871 /* For e500 executables, the apuinfo section is of help here. Such
5872 section contains the identifier and revision number of each
5873 Application-specific Processing Unit that is present on the
5874 chip. The content of the section is determined by the assembler
5875 which looks at each instruction and determines which unit (and
5876 which version of it) can execute it. Grovel through the section
5877 looking for relevant e500 APUs. */
5879 if (bfd_uses_spe_extensions (info
.abfd
))
5881 arch
= info
.bfd_arch_info
->arch
;
5882 mach
= bfd_mach_ppc_e500
;
5883 bfd_default_set_arch_mach (&abfd
, arch
, mach
);
5884 info
.bfd_arch_info
= bfd_get_arch_info (&abfd
);
5887 /* Find a default target description which describes our register
5888 layout, if we do not already have one. */
5889 if (! tdesc_has_registers (tdesc
))
5891 const struct variant
*v
;
5893 /* Choose variant. */
5894 v
= find_variant_by_arch (arch
, mach
);
5901 gdb_assert (tdesc_has_registers (tdesc
));
5903 /* Check any target description for validity. */
5904 if (tdesc_has_registers (tdesc
))
5906 static const char *const gprs
[] = {
5907 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5908 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5909 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5910 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5912 const struct tdesc_feature
*feature
;
5914 static const char *const msr_names
[] = { "msr", "ps" };
5915 static const char *const cr_names
[] = { "cr", "cnd" };
5916 static const char *const ctr_names
[] = { "ctr", "cnt" };
5918 feature
= tdesc_find_feature (tdesc
,
5919 "org.gnu.gdb.power.core");
5920 if (feature
== NULL
)
5923 tdesc_data
= tdesc_data_alloc ();
5926 for (i
= 0; i
< ppc_num_gprs
; i
++)
5927 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
, gprs
[i
]);
5928 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_PC_REGNUM
,
5930 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_LR_REGNUM
,
5932 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_XER_REGNUM
,
5935 /* Allow alternate names for these registers, to accomodate GDB's
5937 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
5938 PPC_MSR_REGNUM
, msr_names
);
5939 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
5940 PPC_CR_REGNUM
, cr_names
);
5941 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
5942 PPC_CTR_REGNUM
, ctr_names
);
5946 tdesc_data_cleanup (tdesc_data
);
5950 have_mq
= tdesc_numbered_register (feature
, tdesc_data
, PPC_MQ_REGNUM
,
5953 tdesc_wordsize
= tdesc_register_bitsize (feature
, "pc") / 8;
5955 wordsize
= tdesc_wordsize
;
5957 feature
= tdesc_find_feature (tdesc
,
5958 "org.gnu.gdb.power.fpu");
5959 if (feature
!= NULL
)
5961 static const char *const fprs
[] = {
5962 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
5963 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
5964 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
5965 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
5968 for (i
= 0; i
< ppc_num_fprs
; i
++)
5969 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5970 PPC_F0_REGNUM
+ i
, fprs
[i
]);
5971 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5972 PPC_FPSCR_REGNUM
, "fpscr");
5976 tdesc_data_cleanup (tdesc_data
);
5981 /* The fpscr register was expanded in isa 2.05 to 64 bits
5982 along with the addition of the decimal floating point
5984 if (tdesc_register_bitsize (feature
, "fpscr") > 32)
5990 feature
= tdesc_find_feature (tdesc
,
5991 "org.gnu.gdb.power.altivec");
5992 if (feature
!= NULL
)
5994 static const char *const vector_regs
[] = {
5995 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
5996 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
5997 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
5998 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31"
6002 for (i
= 0; i
< ppc_num_gprs
; i
++)
6003 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6006 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6007 PPC_VSCR_REGNUM
, "vscr");
6008 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6009 PPC_VRSAVE_REGNUM
, "vrsave");
6011 if (have_spe
|| !valid_p
)
6013 tdesc_data_cleanup (tdesc_data
);
6021 /* Check for POWER7 VSX registers support. */
6022 feature
= tdesc_find_feature (tdesc
,
6023 "org.gnu.gdb.power.vsx");
6025 if (feature
!= NULL
)
6027 static const char *const vsx_regs
[] = {
6028 "vs0h", "vs1h", "vs2h", "vs3h", "vs4h", "vs5h",
6029 "vs6h", "vs7h", "vs8h", "vs9h", "vs10h", "vs11h",
6030 "vs12h", "vs13h", "vs14h", "vs15h", "vs16h", "vs17h",
6031 "vs18h", "vs19h", "vs20h", "vs21h", "vs22h", "vs23h",
6032 "vs24h", "vs25h", "vs26h", "vs27h", "vs28h", "vs29h",
6038 for (i
= 0; i
< ppc_num_vshrs
; i
++)
6039 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6040 PPC_VSR0_UPPER_REGNUM
+ i
,
6044 tdesc_data_cleanup (tdesc_data
);
6053 /* On machines supporting the SPE APU, the general-purpose registers
6054 are 64 bits long. There are SIMD vector instructions to treat them
6055 as pairs of floats, but the rest of the instruction set treats them
6056 as 32-bit registers, and only operates on their lower halves.
6058 In the GDB regcache, we treat their high and low halves as separate
6059 registers. The low halves we present as the general-purpose
6060 registers, and then we have pseudo-registers that stitch together
6061 the upper and lower halves and present them as pseudo-registers.
6063 Thus, the target description is expected to supply the upper
6064 halves separately. */
6066 feature
= tdesc_find_feature (tdesc
,
6067 "org.gnu.gdb.power.spe");
6068 if (feature
!= NULL
)
6070 static const char *const upper_spe
[] = {
6071 "ev0h", "ev1h", "ev2h", "ev3h",
6072 "ev4h", "ev5h", "ev6h", "ev7h",
6073 "ev8h", "ev9h", "ev10h", "ev11h",
6074 "ev12h", "ev13h", "ev14h", "ev15h",
6075 "ev16h", "ev17h", "ev18h", "ev19h",
6076 "ev20h", "ev21h", "ev22h", "ev23h",
6077 "ev24h", "ev25h", "ev26h", "ev27h",
6078 "ev28h", "ev29h", "ev30h", "ev31h"
6082 for (i
= 0; i
< ppc_num_gprs
; i
++)
6083 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6084 PPC_SPE_UPPER_GP0_REGNUM
+ i
,
6086 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6087 PPC_SPE_ACC_REGNUM
, "acc");
6088 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6089 PPC_SPE_FSCR_REGNUM
, "spefscr");
6091 if (have_mq
|| have_fpu
|| !valid_p
)
6093 tdesc_data_cleanup (tdesc_data
);
6102 /* If we have a 64-bit binary on a 32-bit target, complain. Also
6103 complain for a 32-bit binary on a 64-bit target; we do not yet
6104 support that. For instance, the 32-bit ABI routines expect
6107 As long as there isn't an explicit target description, we'll
6108 choose one based on the BFD architecture and get a word size
6109 matching the binary (probably powerpc:common or
6110 powerpc:common64). So there is only trouble if a 64-bit target
6111 supplies a 64-bit description while debugging a 32-bit
6113 if (tdesc_wordsize
!= -1 && tdesc_wordsize
!= wordsize
)
6115 tdesc_data_cleanup (tdesc_data
);
6122 switch (elf_elfheader (info
.abfd
)->e_flags
& EF_PPC64_ABI
)
6125 elf_abi
= POWERPC_ELF_V1
;
6128 elf_abi
= POWERPC_ELF_V2
;
6135 if (soft_float_flag
== AUTO_BOOLEAN_AUTO
&& from_elf_exec
)
6137 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6138 Tag_GNU_Power_ABI_FP
) & 3)
6141 soft_float_flag
= AUTO_BOOLEAN_FALSE
;
6144 soft_float_flag
= AUTO_BOOLEAN_TRUE
;
6151 if (long_double_abi
== POWERPC_LONG_DOUBLE_AUTO
&& from_elf_exec
)
6153 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6154 Tag_GNU_Power_ABI_FP
) >> 2)
6157 long_double_abi
= POWERPC_LONG_DOUBLE_IBM128
;
6160 long_double_abi
= POWERPC_LONG_DOUBLE_IEEE128
;
6167 if (vector_abi
== POWERPC_VEC_AUTO
&& from_elf_exec
)
6169 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6170 Tag_GNU_Power_ABI_Vector
))
6173 vector_abi
= POWERPC_VEC_GENERIC
;
6176 vector_abi
= POWERPC_VEC_ALTIVEC
;
6179 vector_abi
= POWERPC_VEC_SPE
;
6187 /* At this point, the only supported ELF-based 64-bit little-endian
6188 operating system is GNU/Linux, and this uses the ELFv2 ABI by
6189 default. All other supported ELF-based operating systems use the
6190 ELFv1 ABI by default. Therefore, if the ABI marker is missing,
6191 e.g. because we run a legacy binary, or have attached to a process
6192 and have not found any associated binary file, set the default
6193 according to this heuristic. */
6194 if (elf_abi
== POWERPC_ELF_AUTO
)
6196 if (wordsize
== 8 && info
.byte_order
== BFD_ENDIAN_LITTLE
)
6197 elf_abi
= POWERPC_ELF_V2
;
6199 elf_abi
= POWERPC_ELF_V1
;
6202 if (soft_float_flag
== AUTO_BOOLEAN_TRUE
)
6204 else if (soft_float_flag
== AUTO_BOOLEAN_FALSE
)
6207 soft_float
= !have_fpu
;
6209 /* If we have a hard float binary or setting but no floating point
6210 registers, downgrade to soft float anyway. We're still somewhat
6211 useful in this scenario. */
6212 if (!soft_float
&& !have_fpu
)
6215 /* Similarly for vector registers. */
6216 if (vector_abi
== POWERPC_VEC_ALTIVEC
&& !have_altivec
)
6217 vector_abi
= POWERPC_VEC_GENERIC
;
6219 if (vector_abi
== POWERPC_VEC_SPE
&& !have_spe
)
6220 vector_abi
= POWERPC_VEC_GENERIC
;
6222 if (vector_abi
== POWERPC_VEC_AUTO
)
6225 vector_abi
= POWERPC_VEC_ALTIVEC
;
6227 vector_abi
= POWERPC_VEC_SPE
;
6229 vector_abi
= POWERPC_VEC_GENERIC
;
6232 /* Do not limit the vector ABI based on available hardware, since we
6233 do not yet know what hardware we'll decide we have. Yuck! FIXME! */
6235 /* Find a candidate among extant architectures. */
6236 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
6238 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
6240 /* Word size in the various PowerPC bfd_arch_info structs isn't
6241 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
6242 separate word size check. */
6243 tdep
= gdbarch_tdep (arches
->gdbarch
);
6244 if (tdep
&& tdep
->elf_abi
!= elf_abi
)
6246 if (tdep
&& tdep
->soft_float
!= soft_float
)
6248 if (tdep
&& tdep
->long_double_abi
!= long_double_abi
)
6250 if (tdep
&& tdep
->vector_abi
!= vector_abi
)
6252 if (tdep
&& tdep
->wordsize
== wordsize
)
6254 if (tdesc_data
!= NULL
)
6255 tdesc_data_cleanup (tdesc_data
);
6256 return arches
->gdbarch
;
6260 /* None found, create a new architecture from INFO, whose bfd_arch_info
6261 validity depends on the source:
6262 - executable useless
6263 - rs6000_host_arch() good
6265 - "set arch" trust blindly
6266 - GDB startup useless but harmless */
6268 tdep
= XCNEW (struct gdbarch_tdep
);
6269 tdep
->wordsize
= wordsize
;
6270 tdep
->elf_abi
= elf_abi
;
6271 tdep
->soft_float
= soft_float
;
6272 tdep
->long_double_abi
= long_double_abi
;
6273 tdep
->vector_abi
= vector_abi
;
6275 gdbarch
= gdbarch_alloc (&info
, tdep
);
6277 tdep
->ppc_gp0_regnum
= PPC_R0_REGNUM
;
6278 tdep
->ppc_toc_regnum
= PPC_R0_REGNUM
+ 2;
6279 tdep
->ppc_ps_regnum
= PPC_MSR_REGNUM
;
6280 tdep
->ppc_cr_regnum
= PPC_CR_REGNUM
;
6281 tdep
->ppc_lr_regnum
= PPC_LR_REGNUM
;
6282 tdep
->ppc_ctr_regnum
= PPC_CTR_REGNUM
;
6283 tdep
->ppc_xer_regnum
= PPC_XER_REGNUM
;
6284 tdep
->ppc_mq_regnum
= have_mq
? PPC_MQ_REGNUM
: -1;
6286 tdep
->ppc_fp0_regnum
= have_fpu
? PPC_F0_REGNUM
: -1;
6287 tdep
->ppc_fpscr_regnum
= have_fpu
? PPC_FPSCR_REGNUM
: -1;
6288 tdep
->ppc_vsr0_upper_regnum
= have_vsx
? PPC_VSR0_UPPER_REGNUM
: -1;
6289 tdep
->ppc_vr0_regnum
= have_altivec
? PPC_VR0_REGNUM
: -1;
6290 tdep
->ppc_vrsave_regnum
= have_altivec
? PPC_VRSAVE_REGNUM
: -1;
6291 tdep
->ppc_ev0_upper_regnum
= have_spe
? PPC_SPE_UPPER_GP0_REGNUM
: -1;
6292 tdep
->ppc_acc_regnum
= have_spe
? PPC_SPE_ACC_REGNUM
: -1;
6293 tdep
->ppc_spefscr_regnum
= have_spe
? PPC_SPE_FSCR_REGNUM
: -1;
6295 set_gdbarch_pc_regnum (gdbarch
, PPC_PC_REGNUM
);
6296 set_gdbarch_sp_regnum (gdbarch
, PPC_R0_REGNUM
+ 1);
6297 set_gdbarch_fp0_regnum (gdbarch
, tdep
->ppc_fp0_regnum
);
6298 set_gdbarch_register_sim_regno (gdbarch
, rs6000_register_sim_regno
);
6300 /* The XML specification for PowerPC sensibly calls the MSR "msr".
6301 GDB traditionally called it "ps", though, so let GDB add an
6303 set_gdbarch_ps_regnum (gdbarch
, tdep
->ppc_ps_regnum
);
6306 set_gdbarch_return_value (gdbarch
, ppc64_sysv_abi_return_value
);
6308 set_gdbarch_return_value (gdbarch
, ppc_sysv_abi_return_value
);
6310 /* Set lr_frame_offset. */
6312 tdep
->lr_frame_offset
= 16;
6314 tdep
->lr_frame_offset
= 4;
6316 if (have_spe
|| have_dfp
|| have_vsx
)
6318 set_gdbarch_pseudo_register_read (gdbarch
, rs6000_pseudo_register_read
);
6319 set_gdbarch_pseudo_register_write (gdbarch
,
6320 rs6000_pseudo_register_write
);
6321 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
6322 rs6000_ax_pseudo_register_collect
);
6325 set_gdbarch_gen_return_address (gdbarch
, rs6000_gen_return_address
);
6327 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6329 set_gdbarch_num_regs (gdbarch
, PPC_NUM_REGS
);
6332 num_pseudoregs
+= 32;
6334 num_pseudoregs
+= 16;
6336 /* Include both VSX and Extended FP registers. */
6337 num_pseudoregs
+= 96;
6339 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudoregs
);
6341 set_gdbarch_ptr_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
6342 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
6343 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
6344 set_gdbarch_long_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
6345 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
6346 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
6347 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
6348 set_gdbarch_long_double_bit (gdbarch
, 16 * TARGET_CHAR_BIT
);
6349 set_gdbarch_char_signed (gdbarch
, 0);
6351 set_gdbarch_frame_align (gdbarch
, rs6000_frame_align
);
6354 set_gdbarch_frame_red_zone_size (gdbarch
, 288);
6356 set_gdbarch_convert_register_p (gdbarch
, rs6000_convert_register_p
);
6357 set_gdbarch_register_to_value (gdbarch
, rs6000_register_to_value
);
6358 set_gdbarch_value_to_register (gdbarch
, rs6000_value_to_register
);
6360 set_gdbarch_stab_reg_to_regnum (gdbarch
, rs6000_stab_reg_to_regnum
);
6361 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, rs6000_dwarf2_reg_to_regnum
);
6364 set_gdbarch_push_dummy_call (gdbarch
, ppc_sysv_abi_push_dummy_call
);
6365 else if (wordsize
== 8)
6366 set_gdbarch_push_dummy_call (gdbarch
, ppc64_sysv_abi_push_dummy_call
);
6368 set_gdbarch_skip_prologue (gdbarch
, rs6000_skip_prologue
);
6369 set_gdbarch_stack_frame_destroyed_p (gdbarch
, rs6000_stack_frame_destroyed_p
);
6370 set_gdbarch_skip_main_prologue (gdbarch
, rs6000_skip_main_prologue
);
6372 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6374 set_gdbarch_breakpoint_kind_from_pc (gdbarch
,
6375 rs6000_breakpoint::kind_from_pc
);
6376 set_gdbarch_sw_breakpoint_from_kind (gdbarch
,
6377 rs6000_breakpoint::bp_from_kind
);
6379 /* The value of symbols of type N_SO and N_FUN maybe null when
6381 set_gdbarch_sofun_address_maybe_missing (gdbarch
, 1);
6383 /* Handles single stepping of atomic sequences. */
6384 set_gdbarch_software_single_step (gdbarch
, ppc_deal_with_atomic_sequence
);
6386 /* Not sure on this. FIXMEmgo */
6387 set_gdbarch_frame_args_skip (gdbarch
, 8);
6389 /* Helpers for function argument information. */
6390 set_gdbarch_fetch_pointer_argument (gdbarch
, rs6000_fetch_pointer_argument
);
6393 set_gdbarch_in_solib_return_trampoline
6394 (gdbarch
, rs6000_in_solib_return_trampoline
);
6395 set_gdbarch_skip_trampoline_code (gdbarch
, rs6000_skip_trampoline_code
);
6397 /* Hook in the DWARF CFI frame unwinder. */
6398 dwarf2_append_unwinders (gdbarch
);
6399 dwarf2_frame_set_adjust_regnum (gdbarch
, rs6000_adjust_frame_regnum
);
6401 /* Frame handling. */
6402 dwarf2_frame_set_init_reg (gdbarch
, ppc_dwarf2_frame_init_reg
);
6404 /* Setup displaced stepping. */
6405 set_gdbarch_displaced_step_copy_insn (gdbarch
,
6406 ppc_displaced_step_copy_insn
);
6407 set_gdbarch_displaced_step_hw_singlestep (gdbarch
,
6408 ppc_displaced_step_hw_singlestep
);
6409 set_gdbarch_displaced_step_fixup (gdbarch
, ppc_displaced_step_fixup
);
6410 set_gdbarch_displaced_step_location (gdbarch
,
6411 displaced_step_at_entry_point
);
6413 set_gdbarch_max_insn_length (gdbarch
, PPC_INSN_SIZE
);
6415 /* Hook in ABI-specific overrides, if they have been registered. */
6416 info
.target_desc
= tdesc
;
6417 info
.tdesc_data
= tdesc_data
;
6418 gdbarch_init_osabi (info
, gdbarch
);
6422 case GDB_OSABI_LINUX
:
6423 case GDB_OSABI_NETBSD
:
6424 case GDB_OSABI_UNKNOWN
:
6425 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
6426 frame_unwind_append_unwinder (gdbarch
, &rs6000_epilogue_frame_unwind
);
6427 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
6428 set_gdbarch_dummy_id (gdbarch
, rs6000_dummy_id
);
6429 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
6432 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
6434 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
6435 frame_unwind_append_unwinder (gdbarch
, &rs6000_epilogue_frame_unwind
);
6436 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
6437 set_gdbarch_dummy_id (gdbarch
, rs6000_dummy_id
);
6438 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
6441 set_tdesc_pseudo_register_type (gdbarch
, rs6000_pseudo_register_type
);
6442 set_tdesc_pseudo_register_reggroup_p (gdbarch
,
6443 rs6000_pseudo_register_reggroup_p
);
6444 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
6446 /* Override the normal target description method to make the SPE upper
6447 halves anonymous. */
6448 set_gdbarch_register_name (gdbarch
, rs6000_register_name
);
6450 /* Choose register numbers for all supported pseudo-registers. */
6451 tdep
->ppc_ev0_regnum
= -1;
6452 tdep
->ppc_dl0_regnum
= -1;
6453 tdep
->ppc_vsr0_regnum
= -1;
6454 tdep
->ppc_efpr0_regnum
= -1;
6456 cur_reg
= gdbarch_num_regs (gdbarch
);
6460 tdep
->ppc_ev0_regnum
= cur_reg
;
6465 tdep
->ppc_dl0_regnum
= cur_reg
;
6470 tdep
->ppc_vsr0_regnum
= cur_reg
;
6472 tdep
->ppc_efpr0_regnum
= cur_reg
;
6476 gdb_assert (gdbarch_num_cooked_regs (gdbarch
) == cur_reg
);
6478 /* Register the ravenscar_arch_ops. */
6479 if (mach
== bfd_mach_ppc_e500
)
6480 register_e500_ravenscar_ops (gdbarch
);
6482 register_ppc_ravenscar_ops (gdbarch
);
6484 set_gdbarch_disassembler_options (gdbarch
, &powerpc_disassembler_options
);
6485 set_gdbarch_valid_disassembler_options (gdbarch
,
6486 disassembler_options_powerpc ());
6492 rs6000_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
6494 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6499 /* FIXME: Dump gdbarch_tdep. */
6502 /* PowerPC-specific commands. */
6505 set_powerpc_command (const char *args
, int from_tty
)
6507 printf_unfiltered (_("\
6508 \"set powerpc\" must be followed by an appropriate subcommand.\n"));
6509 help_list (setpowerpccmdlist
, "set powerpc ", all_commands
, gdb_stdout
);
6513 show_powerpc_command (const char *args
, int from_tty
)
6515 cmd_show_list (showpowerpccmdlist
, from_tty
, "");
6519 powerpc_set_soft_float (const char *args
, int from_tty
,
6520 struct cmd_list_element
*c
)
6522 struct gdbarch_info info
;
6524 /* Update the architecture. */
6525 gdbarch_info_init (&info
);
6526 if (!gdbarch_update_p (info
))
6527 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
6531 powerpc_set_vector_abi (const char *args
, int from_tty
,
6532 struct cmd_list_element
*c
)
6534 struct gdbarch_info info
;
6537 for (vector_abi
= POWERPC_VEC_AUTO
;
6538 vector_abi
!= POWERPC_VEC_LAST
;
6540 if (strcmp (powerpc_vector_abi_string
,
6541 powerpc_vector_strings
[vector_abi
]) == 0)
6543 powerpc_vector_abi_global
= (enum powerpc_vector_abi
) vector_abi
;
6547 if (vector_abi
== POWERPC_VEC_LAST
)
6548 internal_error (__FILE__
, __LINE__
, _("Invalid vector ABI accepted: %s."),
6549 powerpc_vector_abi_string
);
6551 /* Update the architecture. */
6552 gdbarch_info_init (&info
);
6553 if (!gdbarch_update_p (info
))
6554 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
6557 /* Show the current setting of the exact watchpoints flag. */
6560 show_powerpc_exact_watchpoints (struct ui_file
*file
, int from_tty
,
6561 struct cmd_list_element
*c
,
6564 fprintf_filtered (file
, _("Use of exact watchpoints is %s.\n"), value
);
6567 /* Read a PPC instruction from memory. */
6570 read_insn (struct frame_info
*frame
, CORE_ADDR pc
)
6572 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6573 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6575 return read_memory_unsigned_integer (pc
, 4, byte_order
);
6578 /* Return non-zero if the instructions at PC match the series
6579 described in PATTERN, or zero otherwise. PATTERN is an array of
6580 'struct ppc_insn_pattern' objects, terminated by an entry whose
6583 When the match is successful, fill INSNS[i] with what PATTERN[i]
6584 matched. If PATTERN[i] is optional, and the instruction wasn't
6585 present, set INSNS[i] to 0 (which is not a valid PPC instruction).
6586 INSNS should have as many elements as PATTERN, minus the terminator.
6587 Note that, if PATTERN contains optional instructions which aren't
6588 present in memory, then INSNS will have holes, so INSNS[i] isn't
6589 necessarily the i'th instruction in memory. */
6592 ppc_insns_match_pattern (struct frame_info
*frame
, CORE_ADDR pc
,
6593 const struct ppc_insn_pattern
*pattern
,
6594 unsigned int *insns
)
6599 for (i
= 0, insn
= 0; pattern
[i
].mask
; i
++)
6602 insn
= read_insn (frame
, pc
);
6604 if ((insn
& pattern
[i
].mask
) == pattern
[i
].data
)
6610 else if (!pattern
[i
].optional
)
6617 /* Return the 'd' field of the d-form instruction INSN, properly
6621 ppc_insn_d_field (unsigned int insn
)
6623 return ((((CORE_ADDR
) insn
& 0xffff) ^ 0x8000) - 0x8000);
6626 /* Return the 'ds' field of the ds-form instruction INSN, with the two
6627 zero bits concatenated at the right, and properly
6631 ppc_insn_ds_field (unsigned int insn
)
6633 return ((((CORE_ADDR
) insn
& 0xfffc) ^ 0x8000) - 0x8000);
6636 /* Initialization code. */
6639 _initialize_rs6000_tdep (void)
6641 gdbarch_register (bfd_arch_rs6000
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
6642 gdbarch_register (bfd_arch_powerpc
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
6644 /* Initialize the standard target descriptions. */
6645 initialize_tdesc_powerpc_32 ();
6646 initialize_tdesc_powerpc_altivec32 ();
6647 initialize_tdesc_powerpc_vsx32 ();
6648 initialize_tdesc_powerpc_403 ();
6649 initialize_tdesc_powerpc_403gc ();
6650 initialize_tdesc_powerpc_405 ();
6651 initialize_tdesc_powerpc_505 ();
6652 initialize_tdesc_powerpc_601 ();
6653 initialize_tdesc_powerpc_602 ();
6654 initialize_tdesc_powerpc_603 ();
6655 initialize_tdesc_powerpc_604 ();
6656 initialize_tdesc_powerpc_64 ();
6657 initialize_tdesc_powerpc_altivec64 ();
6658 initialize_tdesc_powerpc_vsx64 ();
6659 initialize_tdesc_powerpc_7400 ();
6660 initialize_tdesc_powerpc_750 ();
6661 initialize_tdesc_powerpc_860 ();
6662 initialize_tdesc_powerpc_e500 ();
6663 initialize_tdesc_rs6000 ();
6665 /* Add root prefix command for all "set powerpc"/"show powerpc"
6667 add_prefix_cmd ("powerpc", no_class
, set_powerpc_command
,
6668 _("Various PowerPC-specific commands."),
6669 &setpowerpccmdlist
, "set powerpc ", 0, &setlist
);
6671 add_prefix_cmd ("powerpc", no_class
, show_powerpc_command
,
6672 _("Various PowerPC-specific commands."),
6673 &showpowerpccmdlist
, "show powerpc ", 0, &showlist
);
6675 /* Add a command to allow the user to force the ABI. */
6676 add_setshow_auto_boolean_cmd ("soft-float", class_support
,
6677 &powerpc_soft_float_global
,
6678 _("Set whether to use a soft-float ABI."),
6679 _("Show whether to use a soft-float ABI."),
6681 powerpc_set_soft_float
, NULL
,
6682 &setpowerpccmdlist
, &showpowerpccmdlist
);
6684 add_setshow_enum_cmd ("vector-abi", class_support
, powerpc_vector_strings
,
6685 &powerpc_vector_abi_string
,
6686 _("Set the vector ABI."),
6687 _("Show the vector ABI."),
6688 NULL
, powerpc_set_vector_abi
, NULL
,
6689 &setpowerpccmdlist
, &showpowerpccmdlist
);
6691 add_setshow_boolean_cmd ("exact-watchpoints", class_support
,
6692 &target_exact_watchpoints
,
6694 Set whether to use just one debug register for watchpoints on scalars."),
6696 Show whether to use just one debug register for watchpoints on scalars."),
6698 If true, GDB will use only one debug register when watching a variable of\n\
6699 scalar type, thus assuming that the variable is accessed through the address\n\
6700 of its first byte."),
6701 NULL
, show_powerpc_exact_watchpoints
,
6702 &setpowerpccmdlist
, &showpowerpccmdlist
);