1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
5 2010 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
30 #include "arch-utils.h"
35 #include "parser-defs.h"
38 #include "sim-regno.h"
39 #include "gdb/sim-ppc.h"
40 #include "reggroups.h"
41 #include "dwarf2-frame.h"
42 #include "target-descriptions.h"
43 #include "user-regs.h"
45 #include "libbfd.h" /* for bfd_default_set_arch_mach */
46 #include "coff/internal.h" /* for libcoff.h */
47 #include "libcoff.h" /* for xcoff_data */
48 #include "coff/xcoff.h"
54 #include "solib-svr4.h"
57 #include "gdb_assert.h"
60 #include "trad-frame.h"
61 #include "frame-unwind.h"
62 #include "frame-base.h"
64 #include "features/rs6000/powerpc-32.c"
65 #include "features/rs6000/powerpc-altivec32.c"
66 #include "features/rs6000/powerpc-vsx32.c"
67 #include "features/rs6000/powerpc-403.c"
68 #include "features/rs6000/powerpc-403gc.c"
69 #include "features/rs6000/powerpc-405.c"
70 #include "features/rs6000/powerpc-505.c"
71 #include "features/rs6000/powerpc-601.c"
72 #include "features/rs6000/powerpc-602.c"
73 #include "features/rs6000/powerpc-603.c"
74 #include "features/rs6000/powerpc-604.c"
75 #include "features/rs6000/powerpc-64.c"
76 #include "features/rs6000/powerpc-altivec64.c"
77 #include "features/rs6000/powerpc-vsx64.c"
78 #include "features/rs6000/powerpc-7400.c"
79 #include "features/rs6000/powerpc-750.c"
80 #include "features/rs6000/powerpc-860.c"
81 #include "features/rs6000/powerpc-e500.c"
82 #include "features/rs6000/rs6000.c"
84 /* Determine if regnum is an SPE pseudo-register. */
85 #define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \
86 && (regnum) >= (tdep)->ppc_ev0_regnum \
87 && (regnum) < (tdep)->ppc_ev0_regnum + 32)
89 /* Determine if regnum is a decimal float pseudo-register. */
90 #define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \
91 && (regnum) >= (tdep)->ppc_dl0_regnum \
92 && (regnum) < (tdep)->ppc_dl0_regnum + 16)
94 /* Determine if regnum is a POWER7 VSX register. */
95 #define IS_VSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_vsr0_regnum >= 0 \
96 && (regnum) >= (tdep)->ppc_vsr0_regnum \
97 && (regnum) < (tdep)->ppc_vsr0_regnum + ppc_num_vsrs)
99 /* Determine if regnum is a POWER7 Extended FP register. */
100 #define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \
101 && (regnum) >= (tdep)->ppc_efpr0_regnum \
102 && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_fprs)
104 /* The list of available "set powerpc ..." and "show powerpc ..."
106 static struct cmd_list_element
*setpowerpccmdlist
= NULL
;
107 static struct cmd_list_element
*showpowerpccmdlist
= NULL
;
109 static enum auto_boolean powerpc_soft_float_global
= AUTO_BOOLEAN_AUTO
;
111 /* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */
112 static const char *powerpc_vector_strings
[] =
121 /* A variable that can be configured by the user. */
122 static enum powerpc_vector_abi powerpc_vector_abi_global
= POWERPC_VEC_AUTO
;
123 static const char *powerpc_vector_abi_string
= "auto";
125 /* To be used by skip_prologue. */
127 struct rs6000_framedata
129 int offset
; /* total size of frame --- the distance
130 by which we decrement sp to allocate
132 int saved_gpr
; /* smallest # of saved gpr */
133 unsigned int gpr_mask
; /* Each bit is an individual saved GPR. */
134 int saved_fpr
; /* smallest # of saved fpr */
135 int saved_vr
; /* smallest # of saved vr */
136 int saved_ev
; /* smallest # of saved ev */
137 int alloca_reg
; /* alloca register number (frame ptr) */
138 char frameless
; /* true if frameless functions. */
139 char nosavedpc
; /* true if pc not saved. */
140 char used_bl
; /* true if link register clobbered */
141 int gpr_offset
; /* offset of saved gprs from prev sp */
142 int fpr_offset
; /* offset of saved fprs from prev sp */
143 int vr_offset
; /* offset of saved vrs from prev sp */
144 int ev_offset
; /* offset of saved evs from prev sp */
145 int lr_offset
; /* offset of saved lr */
146 int lr_register
; /* register of saved lr, if trustworthy */
147 int cr_offset
; /* offset of saved cr */
148 int vrsave_offset
; /* offset of saved vrsave register */
152 /* Is REGNO a VSX register? Return 1 if so, 0 otherwise. */
154 vsx_register_p (struct gdbarch
*gdbarch
, int regno
)
156 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
157 if (tdep
->ppc_vsr0_regnum
< 0)
160 return (regno
>= tdep
->ppc_vsr0_upper_regnum
&& regno
161 <= tdep
->ppc_vsr0_upper_regnum
+ 31);
164 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
166 altivec_register_p (struct gdbarch
*gdbarch
, int regno
)
168 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
169 if (tdep
->ppc_vr0_regnum
< 0 || tdep
->ppc_vrsave_regnum
< 0)
172 return (regno
>= tdep
->ppc_vr0_regnum
&& regno
<= tdep
->ppc_vrsave_regnum
);
176 /* Return true if REGNO is an SPE register, false otherwise. */
178 spe_register_p (struct gdbarch
*gdbarch
, int regno
)
180 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
182 /* Is it a reference to EV0 -- EV31, and do we have those? */
183 if (IS_SPE_PSEUDOREG (tdep
, regno
))
186 /* Is it a reference to one of the raw upper GPR halves? */
187 if (tdep
->ppc_ev0_upper_regnum
>= 0
188 && tdep
->ppc_ev0_upper_regnum
<= regno
189 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
192 /* Is it a reference to the 64-bit accumulator, and do we have that? */
193 if (tdep
->ppc_acc_regnum
>= 0
194 && tdep
->ppc_acc_regnum
== regno
)
197 /* Is it a reference to the SPE floating-point status and control register,
198 and do we have that? */
199 if (tdep
->ppc_spefscr_regnum
>= 0
200 && tdep
->ppc_spefscr_regnum
== regno
)
207 /* Return non-zero if the architecture described by GDBARCH has
208 floating-point registers (f0 --- f31 and fpscr). */
210 ppc_floating_point_unit_p (struct gdbarch
*gdbarch
)
212 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
214 return (tdep
->ppc_fp0_regnum
>= 0
215 && tdep
->ppc_fpscr_regnum
>= 0);
218 /* Return non-zero if the architecture described by GDBARCH has
219 VSX registers (vsr0 --- vsr63). */
221 ppc_vsx_support_p (struct gdbarch
*gdbarch
)
223 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
225 return tdep
->ppc_vsr0_regnum
>= 0;
228 /* Return non-zero if the architecture described by GDBARCH has
229 Altivec registers (vr0 --- vr31, vrsave and vscr). */
231 ppc_altivec_support_p (struct gdbarch
*gdbarch
)
233 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
235 return (tdep
->ppc_vr0_regnum
>= 0
236 && tdep
->ppc_vrsave_regnum
>= 0);
239 /* Check that TABLE[GDB_REGNO] is not already initialized, and then
242 This is a helper function for init_sim_regno_table, constructing
243 the table mapping GDB register numbers to sim register numbers; we
244 initialize every element in that table to -1 before we start
247 set_sim_regno (int *table
, int gdb_regno
, int sim_regno
)
249 /* Make sure we don't try to assign any given GDB register a sim
250 register number more than once. */
251 gdb_assert (table
[gdb_regno
] == -1);
252 table
[gdb_regno
] = sim_regno
;
256 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
257 numbers to simulator register numbers, based on the values placed
258 in the ARCH->tdep->ppc_foo_regnum members. */
260 init_sim_regno_table (struct gdbarch
*arch
)
262 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
263 int total_regs
= gdbarch_num_regs (arch
);
264 int *sim_regno
= GDBARCH_OBSTACK_CALLOC (arch
, total_regs
, int);
266 static const char *const segment_regs
[] = {
267 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
268 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
271 /* Presume that all registers not explicitly mentioned below are
272 unavailable from the sim. */
273 for (i
= 0; i
< total_regs
; i
++)
276 /* General-purpose registers. */
277 for (i
= 0; i
< ppc_num_gprs
; i
++)
278 set_sim_regno (sim_regno
, tdep
->ppc_gp0_regnum
+ i
, sim_ppc_r0_regnum
+ i
);
280 /* Floating-point registers. */
281 if (tdep
->ppc_fp0_regnum
>= 0)
282 for (i
= 0; i
< ppc_num_fprs
; i
++)
283 set_sim_regno (sim_regno
,
284 tdep
->ppc_fp0_regnum
+ i
,
285 sim_ppc_f0_regnum
+ i
);
286 if (tdep
->ppc_fpscr_regnum
>= 0)
287 set_sim_regno (sim_regno
, tdep
->ppc_fpscr_regnum
, sim_ppc_fpscr_regnum
);
289 set_sim_regno (sim_regno
, gdbarch_pc_regnum (arch
), sim_ppc_pc_regnum
);
290 set_sim_regno (sim_regno
, tdep
->ppc_ps_regnum
, sim_ppc_ps_regnum
);
291 set_sim_regno (sim_regno
, tdep
->ppc_cr_regnum
, sim_ppc_cr_regnum
);
293 /* Segment registers. */
294 for (i
= 0; i
< ppc_num_srs
; i
++)
298 gdb_regno
= user_reg_map_name_to_regnum (arch
, segment_regs
[i
], -1);
300 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_sr0_regnum
+ i
);
303 /* Altivec registers. */
304 if (tdep
->ppc_vr0_regnum
>= 0)
306 for (i
= 0; i
< ppc_num_vrs
; i
++)
307 set_sim_regno (sim_regno
,
308 tdep
->ppc_vr0_regnum
+ i
,
309 sim_ppc_vr0_regnum
+ i
);
311 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
312 we can treat this more like the other cases. */
313 set_sim_regno (sim_regno
,
314 tdep
->ppc_vr0_regnum
+ ppc_num_vrs
,
315 sim_ppc_vscr_regnum
);
317 /* vsave is a special-purpose register, so the code below handles it. */
319 /* SPE APU (E500) registers. */
320 if (tdep
->ppc_ev0_upper_regnum
>= 0)
321 for (i
= 0; i
< ppc_num_gprs
; i
++)
322 set_sim_regno (sim_regno
,
323 tdep
->ppc_ev0_upper_regnum
+ i
,
324 sim_ppc_rh0_regnum
+ i
);
325 if (tdep
->ppc_acc_regnum
>= 0)
326 set_sim_regno (sim_regno
, tdep
->ppc_acc_regnum
, sim_ppc_acc_regnum
);
327 /* spefscr is a special-purpose register, so the code below handles it. */
330 /* Now handle all special-purpose registers. Verify that they
331 haven't mistakenly been assigned numbers by any of the above
333 for (i
= 0; i
< sim_ppc_num_sprs
; i
++)
335 const char *spr_name
= sim_spr_register_name (i
);
338 if (spr_name
!= NULL
)
339 gdb_regno
= user_reg_map_name_to_regnum (arch
, spr_name
, -1);
342 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_spr0_regnum
+ i
);
346 /* Drop the initialized array into place. */
347 tdep
->sim_regno
= sim_regno
;
351 /* Given a GDB register number REG, return the corresponding SIM
354 rs6000_register_sim_regno (struct gdbarch
*gdbarch
, int reg
)
356 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
359 if (tdep
->sim_regno
== NULL
)
360 init_sim_regno_table (gdbarch
);
363 && reg
<= gdbarch_num_regs (gdbarch
)
364 + gdbarch_num_pseudo_regs (gdbarch
));
365 sim_regno
= tdep
->sim_regno
[reg
];
370 return LEGACY_SIM_REGNO_IGNORE
;
375 /* Register set support functions. */
377 /* REGS + OFFSET contains register REGNUM in a field REGSIZE wide.
378 Write the register to REGCACHE. */
381 ppc_supply_reg (struct regcache
*regcache
, int regnum
,
382 const gdb_byte
*regs
, size_t offset
, int regsize
)
384 if (regnum
!= -1 && offset
!= -1)
388 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
389 int gdb_regsize
= register_size (gdbarch
, regnum
);
390 if (gdb_regsize
< regsize
391 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
392 offset
+= regsize
- gdb_regsize
;
394 regcache_raw_supply (regcache
, regnum
, regs
+ offset
);
398 /* Read register REGNUM from REGCACHE and store to REGS + OFFSET
399 in a field REGSIZE wide. Zero pad as necessary. */
402 ppc_collect_reg (const struct regcache
*regcache
, int regnum
,
403 gdb_byte
*regs
, size_t offset
, int regsize
)
405 if (regnum
!= -1 && offset
!= -1)
409 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
410 int gdb_regsize
= register_size (gdbarch
, regnum
);
411 if (gdb_regsize
< regsize
)
413 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
415 memset (regs
+ offset
, 0, regsize
- gdb_regsize
);
416 offset
+= regsize
- gdb_regsize
;
419 memset (regs
+ offset
+ regsize
- gdb_regsize
, 0,
420 regsize
- gdb_regsize
);
423 regcache_raw_collect (regcache
, regnum
, regs
+ offset
);
428 ppc_greg_offset (struct gdbarch
*gdbarch
,
429 struct gdbarch_tdep
*tdep
,
430 const struct ppc_reg_offsets
*offsets
,
434 *regsize
= offsets
->gpr_size
;
435 if (regnum
>= tdep
->ppc_gp0_regnum
436 && regnum
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
)
437 return (offsets
->r0_offset
438 + (regnum
- tdep
->ppc_gp0_regnum
) * offsets
->gpr_size
);
440 if (regnum
== gdbarch_pc_regnum (gdbarch
))
441 return offsets
->pc_offset
;
443 if (regnum
== tdep
->ppc_ps_regnum
)
444 return offsets
->ps_offset
;
446 if (regnum
== tdep
->ppc_lr_regnum
)
447 return offsets
->lr_offset
;
449 if (regnum
== tdep
->ppc_ctr_regnum
)
450 return offsets
->ctr_offset
;
452 *regsize
= offsets
->xr_size
;
453 if (regnum
== tdep
->ppc_cr_regnum
)
454 return offsets
->cr_offset
;
456 if (regnum
== tdep
->ppc_xer_regnum
)
457 return offsets
->xer_offset
;
459 if (regnum
== tdep
->ppc_mq_regnum
)
460 return offsets
->mq_offset
;
466 ppc_fpreg_offset (struct gdbarch_tdep
*tdep
,
467 const struct ppc_reg_offsets
*offsets
,
470 if (regnum
>= tdep
->ppc_fp0_regnum
471 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
)
472 return offsets
->f0_offset
+ (regnum
- tdep
->ppc_fp0_regnum
) * 8;
474 if (regnum
== tdep
->ppc_fpscr_regnum
)
475 return offsets
->fpscr_offset
;
481 ppc_vrreg_offset (struct gdbarch_tdep
*tdep
,
482 const struct ppc_reg_offsets
*offsets
,
485 if (regnum
>= tdep
->ppc_vr0_regnum
486 && regnum
< tdep
->ppc_vr0_regnum
+ ppc_num_vrs
)
487 return offsets
->vr0_offset
+ (regnum
- tdep
->ppc_vr0_regnum
) * 16;
489 if (regnum
== tdep
->ppc_vrsave_regnum
- 1)
490 return offsets
->vscr_offset
;
492 if (regnum
== tdep
->ppc_vrsave_regnum
)
493 return offsets
->vrsave_offset
;
498 /* Supply register REGNUM in the general-purpose register set REGSET
499 from the buffer specified by GREGS and LEN to register cache
500 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
503 ppc_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
504 int regnum
, const void *gregs
, size_t len
)
506 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
507 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
508 const struct ppc_reg_offsets
*offsets
= regset
->descr
;
515 int gpr_size
= offsets
->gpr_size
;
517 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
518 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
519 i
++, offset
+= gpr_size
)
520 ppc_supply_reg (regcache
, i
, gregs
, offset
, gpr_size
);
522 ppc_supply_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
523 gregs
, offsets
->pc_offset
, gpr_size
);
524 ppc_supply_reg (regcache
, tdep
->ppc_ps_regnum
,
525 gregs
, offsets
->ps_offset
, gpr_size
);
526 ppc_supply_reg (regcache
, tdep
->ppc_lr_regnum
,
527 gregs
, offsets
->lr_offset
, gpr_size
);
528 ppc_supply_reg (regcache
, tdep
->ppc_ctr_regnum
,
529 gregs
, offsets
->ctr_offset
, gpr_size
);
530 ppc_supply_reg (regcache
, tdep
->ppc_cr_regnum
,
531 gregs
, offsets
->cr_offset
, offsets
->xr_size
);
532 ppc_supply_reg (regcache
, tdep
->ppc_xer_regnum
,
533 gregs
, offsets
->xer_offset
, offsets
->xr_size
);
534 ppc_supply_reg (regcache
, tdep
->ppc_mq_regnum
,
535 gregs
, offsets
->mq_offset
, offsets
->xr_size
);
539 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
540 ppc_supply_reg (regcache
, regnum
, gregs
, offset
, regsize
);
543 /* Supply register REGNUM in the floating-point register set REGSET
544 from the buffer specified by FPREGS and LEN to register cache
545 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
548 ppc_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
549 int regnum
, const void *fpregs
, size_t len
)
551 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
552 struct gdbarch_tdep
*tdep
;
553 const struct ppc_reg_offsets
*offsets
;
556 if (!ppc_floating_point_unit_p (gdbarch
))
559 tdep
= gdbarch_tdep (gdbarch
);
560 offsets
= regset
->descr
;
565 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
566 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
568 ppc_supply_reg (regcache
, i
, fpregs
, offset
, 8);
570 ppc_supply_reg (regcache
, tdep
->ppc_fpscr_regnum
,
571 fpregs
, offsets
->fpscr_offset
, offsets
->fpscr_size
);
575 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
576 ppc_supply_reg (regcache
, regnum
, fpregs
, offset
,
577 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
580 /* Supply register REGNUM in the VSX register set REGSET
581 from the buffer specified by VSXREGS and LEN to register cache
582 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
585 ppc_supply_vsxregset (const struct regset
*regset
, struct regcache
*regcache
,
586 int regnum
, const void *vsxregs
, size_t len
)
588 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
589 struct gdbarch_tdep
*tdep
;
591 if (!ppc_vsx_support_p (gdbarch
))
594 tdep
= gdbarch_tdep (gdbarch
);
600 for (i
= tdep
->ppc_vsr0_upper_regnum
;
601 i
< tdep
->ppc_vsr0_upper_regnum
+ 32;
603 ppc_supply_reg (regcache
, i
, vsxregs
, 0, 8);
608 ppc_supply_reg (regcache
, regnum
, vsxregs
, 0, 8);
611 /* Supply register REGNUM in the Altivec register set REGSET
612 from the buffer specified by VRREGS and LEN to register cache
613 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
616 ppc_supply_vrregset (const struct regset
*regset
, struct regcache
*regcache
,
617 int regnum
, const void *vrregs
, size_t len
)
619 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
620 struct gdbarch_tdep
*tdep
;
621 const struct ppc_reg_offsets
*offsets
;
624 if (!ppc_altivec_support_p (gdbarch
))
627 tdep
= gdbarch_tdep (gdbarch
);
628 offsets
= regset
->descr
;
633 for (i
= tdep
->ppc_vr0_regnum
, offset
= offsets
->vr0_offset
;
634 i
< tdep
->ppc_vr0_regnum
+ ppc_num_vrs
;
636 ppc_supply_reg (regcache
, i
, vrregs
, offset
, 16);
638 ppc_supply_reg (regcache
, (tdep
->ppc_vrsave_regnum
- 1),
639 vrregs
, offsets
->vscr_offset
, 4);
641 ppc_supply_reg (regcache
, tdep
->ppc_vrsave_regnum
,
642 vrregs
, offsets
->vrsave_offset
, 4);
646 offset
= ppc_vrreg_offset (tdep
, offsets
, regnum
);
647 if (regnum
!= tdep
->ppc_vrsave_regnum
648 && regnum
!= tdep
->ppc_vrsave_regnum
- 1)
649 ppc_supply_reg (regcache
, regnum
, vrregs
, offset
, 16);
651 ppc_supply_reg (regcache
, regnum
,
655 /* Collect register REGNUM in the general-purpose register set
656 REGSET from register cache REGCACHE into the buffer specified by
657 GREGS and LEN. If REGNUM is -1, do this for all registers in
661 ppc_collect_gregset (const struct regset
*regset
,
662 const struct regcache
*regcache
,
663 int regnum
, void *gregs
, size_t len
)
665 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
666 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
667 const struct ppc_reg_offsets
*offsets
= regset
->descr
;
674 int gpr_size
= offsets
->gpr_size
;
676 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
677 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
678 i
++, offset
+= gpr_size
)
679 ppc_collect_reg (regcache
, i
, gregs
, offset
, gpr_size
);
681 ppc_collect_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
682 gregs
, offsets
->pc_offset
, gpr_size
);
683 ppc_collect_reg (regcache
, tdep
->ppc_ps_regnum
,
684 gregs
, offsets
->ps_offset
, gpr_size
);
685 ppc_collect_reg (regcache
, tdep
->ppc_lr_regnum
,
686 gregs
, offsets
->lr_offset
, gpr_size
);
687 ppc_collect_reg (regcache
, tdep
->ppc_ctr_regnum
,
688 gregs
, offsets
->ctr_offset
, gpr_size
);
689 ppc_collect_reg (regcache
, tdep
->ppc_cr_regnum
,
690 gregs
, offsets
->cr_offset
, offsets
->xr_size
);
691 ppc_collect_reg (regcache
, tdep
->ppc_xer_regnum
,
692 gregs
, offsets
->xer_offset
, offsets
->xr_size
);
693 ppc_collect_reg (regcache
, tdep
->ppc_mq_regnum
,
694 gregs
, offsets
->mq_offset
, offsets
->xr_size
);
698 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
699 ppc_collect_reg (regcache
, regnum
, gregs
, offset
, regsize
);
702 /* Collect register REGNUM in the floating-point register set
703 REGSET from register cache REGCACHE into the buffer specified by
704 FPREGS and LEN. If REGNUM is -1, do this for all registers in
708 ppc_collect_fpregset (const struct regset
*regset
,
709 const struct regcache
*regcache
,
710 int regnum
, void *fpregs
, size_t len
)
712 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
713 struct gdbarch_tdep
*tdep
;
714 const struct ppc_reg_offsets
*offsets
;
717 if (!ppc_floating_point_unit_p (gdbarch
))
720 tdep
= gdbarch_tdep (gdbarch
);
721 offsets
= regset
->descr
;
726 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
727 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
729 ppc_collect_reg (regcache
, i
, fpregs
, offset
, 8);
731 ppc_collect_reg (regcache
, tdep
->ppc_fpscr_regnum
,
732 fpregs
, offsets
->fpscr_offset
, offsets
->fpscr_size
);
736 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
737 ppc_collect_reg (regcache
, regnum
, fpregs
, offset
,
738 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
741 /* Collect register REGNUM in the VSX register set
742 REGSET from register cache REGCACHE into the buffer specified by
743 VSXREGS and LEN. If REGNUM is -1, do this for all registers in
747 ppc_collect_vsxregset (const struct regset
*regset
,
748 const struct regcache
*regcache
,
749 int regnum
, void *vsxregs
, size_t len
)
751 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
752 struct gdbarch_tdep
*tdep
;
754 if (!ppc_vsx_support_p (gdbarch
))
757 tdep
= gdbarch_tdep (gdbarch
);
763 for (i
= tdep
->ppc_vsr0_upper_regnum
;
764 i
< tdep
->ppc_vsr0_upper_regnum
+ 32;
766 ppc_collect_reg (regcache
, i
, vsxregs
, 0, 8);
771 ppc_collect_reg (regcache
, regnum
, vsxregs
, 0, 8);
775 /* Collect register REGNUM in the Altivec register set
776 REGSET from register cache REGCACHE into the buffer specified by
777 VRREGS and LEN. If REGNUM is -1, do this for all registers in
781 ppc_collect_vrregset (const struct regset
*regset
,
782 const struct regcache
*regcache
,
783 int regnum
, void *vrregs
, size_t len
)
785 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
786 struct gdbarch_tdep
*tdep
;
787 const struct ppc_reg_offsets
*offsets
;
790 if (!ppc_altivec_support_p (gdbarch
))
793 tdep
= gdbarch_tdep (gdbarch
);
794 offsets
= regset
->descr
;
799 for (i
= tdep
->ppc_vr0_regnum
, offset
= offsets
->vr0_offset
;
800 i
< tdep
->ppc_vr0_regnum
+ ppc_num_vrs
;
802 ppc_collect_reg (regcache
, i
, vrregs
, offset
, 16);
804 ppc_collect_reg (regcache
, (tdep
->ppc_vrsave_regnum
- 1),
805 vrregs
, offsets
->vscr_offset
, 4);
807 ppc_collect_reg (regcache
, tdep
->ppc_vrsave_regnum
,
808 vrregs
, offsets
->vrsave_offset
, 4);
812 offset
= ppc_vrreg_offset (tdep
, offsets
, regnum
);
813 if (regnum
!= tdep
->ppc_vrsave_regnum
814 && regnum
!= tdep
->ppc_vrsave_regnum
- 1)
815 ppc_collect_reg (regcache
, regnum
, vrregs
, offset
, 16);
817 ppc_collect_reg (regcache
, regnum
,
823 insn_changes_sp_or_jumps (unsigned long insn
)
825 int opcode
= (insn
>> 26) & 0x03f;
826 int sd
= (insn
>> 21) & 0x01f;
827 int a
= (insn
>> 16) & 0x01f;
828 int subcode
= (insn
>> 1) & 0x3ff;
830 /* Changes the stack pointer. */
832 /* NOTE: There are many ways to change the value of a given register.
833 The ways below are those used when the register is R1, the SP,
834 in a funtion's epilogue. */
836 if (opcode
== 31 && subcode
== 444 && a
== 1)
837 return 1; /* mr R1,Rn */
838 if (opcode
== 14 && sd
== 1)
839 return 1; /* addi R1,Rn,simm */
840 if (opcode
== 58 && sd
== 1)
841 return 1; /* ld R1,ds(Rn) */
843 /* Transfers control. */
849 if (opcode
== 19 && subcode
== 16)
851 if (opcode
== 19 && subcode
== 528)
852 return 1; /* bcctr */
857 /* Return true if we are in the function's epilogue, i.e. after the
858 instruction that destroyed the function's stack frame.
860 1) scan forward from the point of execution:
861 a) If you find an instruction that modifies the stack pointer
862 or transfers control (except a return), execution is not in
864 b) Stop scanning if you find a return instruction or reach the
865 end of the function or reach the hard limit for the size of
867 2) scan backward from the point of execution:
868 a) If you find an instruction that modifies the stack pointer,
869 execution *is* in an epilogue, return.
870 b) Stop scanning if you reach an instruction that transfers
871 control or the beginning of the function or reach the hard
872 limit for the size of an epilogue. */
875 rs6000_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
877 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
878 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
879 bfd_byte insn_buf
[PPC_INSN_SIZE
];
880 CORE_ADDR scan_pc
, func_start
, func_end
, epilogue_start
, epilogue_end
;
882 struct frame_info
*curfrm
;
884 /* Find the search limits based on function boundaries and hard limit. */
886 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
889 epilogue_start
= pc
- PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
890 if (epilogue_start
< func_start
) epilogue_start
= func_start
;
892 epilogue_end
= pc
+ PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
893 if (epilogue_end
> func_end
) epilogue_end
= func_end
;
895 curfrm
= get_current_frame ();
897 /* Scan forward until next 'blr'. */
899 for (scan_pc
= pc
; scan_pc
< epilogue_end
; scan_pc
+= PPC_INSN_SIZE
)
901 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
903 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
904 if (insn
== 0x4e800020)
906 /* Assume a bctr is a tail call unless it points strictly within
908 if (insn
== 0x4e800420)
910 CORE_ADDR ctr
= get_frame_register_unsigned (curfrm
,
911 tdep
->ppc_ctr_regnum
);
912 if (ctr
> func_start
&& ctr
< func_end
)
917 if (insn_changes_sp_or_jumps (insn
))
921 /* Scan backward until adjustment to stack pointer (R1). */
923 for (scan_pc
= pc
- PPC_INSN_SIZE
;
924 scan_pc
>= epilogue_start
;
925 scan_pc
-= PPC_INSN_SIZE
)
927 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
929 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
930 if (insn_changes_sp_or_jumps (insn
))
937 /* Get the ith function argument for the current function. */
939 rs6000_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
942 return get_frame_register_unsigned (frame
, 3 + argi
);
945 /* Sequence of bytes for breakpoint instruction. */
947 const static unsigned char *
948 rs6000_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*bp_addr
,
951 static unsigned char big_breakpoint
[] = { 0x7d, 0x82, 0x10, 0x08 };
952 static unsigned char little_breakpoint
[] = { 0x08, 0x10, 0x82, 0x7d };
954 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
955 return big_breakpoint
;
957 return little_breakpoint
;
960 /* Instruction masks for displaced stepping. */
961 #define BRANCH_MASK 0xfc000000
962 #define BP_MASK 0xFC0007FE
963 #define B_INSN 0x48000000
964 #define BC_INSN 0x40000000
965 #define BXL_INSN 0x4c000000
966 #define BP_INSN 0x7C000008
968 /* Fix up the state of registers and memory after having single-stepped
969 a displaced instruction. */
971 ppc_displaced_step_fixup (struct gdbarch
*gdbarch
,
972 struct displaced_step_closure
*closure
,
973 CORE_ADDR from
, CORE_ADDR to
,
974 struct regcache
*regs
)
976 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
977 /* Since we use simple_displaced_step_copy_insn, our closure is a
978 copy of the instruction. */
979 ULONGEST insn
= extract_unsigned_integer ((gdb_byte
*) closure
,
980 PPC_INSN_SIZE
, byte_order
);
982 /* Offset for non PC-relative instructions. */
983 LONGEST offset
= PPC_INSN_SIZE
;
985 opcode
= insn
& BRANCH_MASK
;
988 fprintf_unfiltered (gdb_stdlog
,
989 "displaced: (ppc) fixup (%s, %s)\n",
990 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
993 /* Handle PC-relative branch instructions. */
994 if (opcode
== B_INSN
|| opcode
== BC_INSN
|| opcode
== BXL_INSN
)
998 /* Read the current PC value after the instruction has been executed
999 in a displaced location. Calculate the offset to be applied to the
1000 original PC value before the displaced stepping. */
1001 regcache_cooked_read_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1003 offset
= current_pc
- to
;
1005 if (opcode
!= BXL_INSN
)
1007 /* Check for AA bit indicating whether this is an absolute
1008 addressing or PC-relative (1: absolute, 0: relative). */
1011 /* PC-relative addressing is being used in the branch. */
1012 if (debug_displaced
)
1015 "displaced: (ppc) branch instruction: %s\n"
1016 "displaced: (ppc) adjusted PC from %s to %s\n",
1017 paddress (gdbarch
, insn
), paddress (gdbarch
, current_pc
),
1018 paddress (gdbarch
, from
+ offset
));
1020 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1026 /* If we're here, it means we have a branch to LR or CTR. If the
1027 branch was taken, the offset is probably greater than 4 (the next
1028 instruction), so it's safe to assume that an offset of 4 means we
1029 did not take the branch. */
1030 if (offset
== PPC_INSN_SIZE
)
1031 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1032 from
+ PPC_INSN_SIZE
);
1035 /* Check for LK bit indicating whether we should set the link
1036 register to point to the next instruction
1037 (1: Set, 0: Don't set). */
1040 /* Link register needs to be set to the next instruction's PC. */
1041 regcache_cooked_write_unsigned (regs
,
1042 gdbarch_tdep (gdbarch
)->ppc_lr_regnum
,
1043 from
+ PPC_INSN_SIZE
);
1044 if (debug_displaced
)
1045 fprintf_unfiltered (gdb_stdlog
,
1046 "displaced: (ppc) adjusted LR to %s\n",
1047 paddress (gdbarch
, from
+ PPC_INSN_SIZE
));
1051 /* Check for breakpoints in the inferior. If we've found one, place the PC
1052 right at the breakpoint instruction. */
1053 else if ((insn
& BP_MASK
) == BP_INSN
)
1054 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
), from
);
1056 /* Handle any other instructions that do not fit in the categories above. */
1057 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1061 /* Always use hardware single-stepping to execute the
1062 displaced instruction. */
1064 ppc_displaced_step_hw_singlestep (struct gdbarch
*gdbarch
,
1065 struct displaced_step_closure
*closure
)
1070 /* Instruction masks used during single-stepping of atomic sequences. */
1071 #define LWARX_MASK 0xfc0007fe
1072 #define LWARX_INSTRUCTION 0x7c000028
1073 #define LDARX_INSTRUCTION 0x7c0000A8
1074 #define STWCX_MASK 0xfc0007ff
1075 #define STWCX_INSTRUCTION 0x7c00012d
1076 #define STDCX_INSTRUCTION 0x7c0001ad
1078 /* Checks for an atomic sequence of instructions beginning with a LWARX/LDARX
1079 instruction and ending with a STWCX/STDCX instruction. If such a sequence
1080 is found, attempt to step through it. A breakpoint is placed at the end of
1084 ppc_deal_with_atomic_sequence (struct frame_info
*frame
)
1086 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1087 struct address_space
*aspace
= get_frame_address_space (frame
);
1088 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1089 CORE_ADDR pc
= get_frame_pc (frame
);
1090 CORE_ADDR breaks
[2] = {-1, -1};
1092 CORE_ADDR closing_insn
; /* Instruction that closes the atomic sequence. */
1093 int insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1096 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
1097 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
1098 int opcode
; /* Branch instruction's OPcode. */
1099 int bc_insn_count
= 0; /* Conditional branch instruction count. */
1101 /* Assume all atomic sequences start with a lwarx/ldarx instruction. */
1102 if ((insn
& LWARX_MASK
) != LWARX_INSTRUCTION
1103 && (insn
& LWARX_MASK
) != LDARX_INSTRUCTION
)
1106 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
1108 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
1110 loc
+= PPC_INSN_SIZE
;
1111 insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1113 /* Assume that there is at most one conditional branch in the atomic
1114 sequence. If a conditional branch is found, put a breakpoint in
1115 its destination address. */
1116 if ((insn
& BRANCH_MASK
) == BC_INSN
)
1118 int immediate
= ((insn
& ~3) << 16) >> 16;
1119 int absolute
= ((insn
>> 1) & 1);
1121 if (bc_insn_count
>= 1)
1122 return 0; /* More than one conditional branch found, fallback
1123 to the standard single-step code. */
1126 breaks
[1] = immediate
;
1128 breaks
[1] = pc
+ immediate
;
1134 if ((insn
& STWCX_MASK
) == STWCX_INSTRUCTION
1135 || (insn
& STWCX_MASK
) == STDCX_INSTRUCTION
)
1139 /* Assume that the atomic sequence ends with a stwcx/stdcx instruction. */
1140 if ((insn
& STWCX_MASK
) != STWCX_INSTRUCTION
1141 && (insn
& STWCX_MASK
) != STDCX_INSTRUCTION
)
1145 loc
+= PPC_INSN_SIZE
;
1146 insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1148 /* Insert a breakpoint right after the end of the atomic sequence. */
1151 /* Check for duplicated breakpoints. Check also for a breakpoint
1152 placed (branch instruction's destination) at the stwcx/stdcx
1153 instruction, this resets the reservation and take us back to the
1154 lwarx/ldarx instruction at the beginning of the atomic sequence. */
1155 if (last_breakpoint
&& ((breaks
[1] == breaks
[0])
1156 || (breaks
[1] == closing_insn
)))
1157 last_breakpoint
= 0;
1159 /* Effectively inserts the breakpoints. */
1160 for (index
= 0; index
<= last_breakpoint
; index
++)
1161 insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
1167 #define SIGNED_SHORT(x) \
1168 ((sizeof (short) == 2) \
1169 ? ((int)(short)(x)) \
1170 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
1172 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
1174 /* Limit the number of skipped non-prologue instructions, as the examining
1175 of the prologue is expensive. */
1176 static int max_skip_non_prologue_insns
= 10;
1178 /* Return nonzero if the given instruction OP can be part of the prologue
1179 of a function and saves a parameter on the stack. FRAMEP should be
1180 set if one of the previous instructions in the function has set the
1184 store_param_on_stack_p (unsigned long op
, int framep
, int *r0_contains_arg
)
1186 /* Move parameters from argument registers to temporary register. */
1187 if ((op
& 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
1189 /* Rx must be scratch register r0. */
1190 const int rx_regno
= (op
>> 16) & 31;
1191 /* Ry: Only r3 - r10 are used for parameter passing. */
1192 const int ry_regno
= GET_SRC_REG (op
);
1194 if (rx_regno
== 0 && ry_regno
>= 3 && ry_regno
<= 10)
1196 *r0_contains_arg
= 1;
1203 /* Save a General Purpose Register on stack. */
1205 if ((op
& 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
1206 (op
& 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
1208 /* Rx: Only r3 - r10 are used for parameter passing. */
1209 const int rx_regno
= GET_SRC_REG (op
);
1211 return (rx_regno
>= 3 && rx_regno
<= 10);
1214 /* Save a General Purpose Register on stack via the Frame Pointer. */
1217 ((op
& 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
1218 (op
& 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
1219 (op
& 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
1221 /* Rx: Usually, only r3 - r10 are used for parameter passing.
1222 However, the compiler sometimes uses r0 to hold an argument. */
1223 const int rx_regno
= GET_SRC_REG (op
);
1225 return ((rx_regno
>= 3 && rx_regno
<= 10)
1226 || (rx_regno
== 0 && *r0_contains_arg
));
1229 if ((op
& 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
1231 /* Only f2 - f8 are used for parameter passing. */
1232 const int src_regno
= GET_SRC_REG (op
);
1234 return (src_regno
>= 2 && src_regno
<= 8);
1237 if (framep
&& ((op
& 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
1239 /* Only f2 - f8 are used for parameter passing. */
1240 const int src_regno
= GET_SRC_REG (op
);
1242 return (src_regno
>= 2 && src_regno
<= 8);
1245 /* Not an insn that saves a parameter on stack. */
1249 /* Assuming that INSN is a "bl" instruction located at PC, return
1250 nonzero if the destination of the branch is a "blrl" instruction.
1252 This sequence is sometimes found in certain function prologues.
1253 It allows the function to load the LR register with a value that
1254 they can use to access PIC data using PC-relative offsets. */
1257 bl_to_blrl_insn_p (CORE_ADDR pc
, int insn
, enum bfd_endian byte_order
)
1264 absolute
= (int) ((insn
>> 1) & 1);
1265 immediate
= ((insn
& ~3) << 6) >> 6;
1269 dest
= pc
+ immediate
;
1271 dest_insn
= read_memory_integer (dest
, 4, byte_order
);
1272 if ((dest_insn
& 0xfc00ffff) == 0x4c000021) /* blrl */
1278 /* Masks for decoding a branch-and-link (bl) instruction.
1280 BL_MASK and BL_INSTRUCTION are used in combination with each other.
1281 The former is anded with the opcode in question; if the result of
1282 this masking operation is equal to BL_INSTRUCTION, then the opcode in
1283 question is a ``bl'' instruction.
1285 BL_DISPLACMENT_MASK is anded with the opcode in order to extract
1286 the branch displacement. */
1288 #define BL_MASK 0xfc000001
1289 #define BL_INSTRUCTION 0x48000001
1290 #define BL_DISPLACEMENT_MASK 0x03fffffc
1292 static unsigned long
1293 rs6000_fetch_instruction (struct gdbarch
*gdbarch
, const CORE_ADDR pc
)
1295 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1299 /* Fetch the instruction and convert it to an integer. */
1300 if (target_read_memory (pc
, buf
, 4))
1302 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1307 /* GCC generates several well-known sequences of instructions at the begining
1308 of each function prologue when compiling with -fstack-check. If one of
1309 such sequences starts at START_PC, then return the address of the
1310 instruction immediately past this sequence. Otherwise, return START_PC. */
1313 rs6000_skip_stack_check (struct gdbarch
*gdbarch
, const CORE_ADDR start_pc
)
1315 CORE_ADDR pc
= start_pc
;
1316 unsigned long op
= rs6000_fetch_instruction (gdbarch
, pc
);
1318 /* First possible sequence: A small number of probes.
1319 stw 0, -<some immediate>(1)
1320 [repeat this instruction any (small) number of times]
1323 if ((op
& 0xffff0000) == 0x90010000)
1325 while ((op
& 0xffff0000) == 0x90010000)
1328 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1333 /* Second sequence: A probing loop.
1334 addi 12,1,-<some immediate>
1335 lis 0,-<some immediate>
1336 [possibly ori 0,0,<some immediate>]
1340 addi 12,12,-<some immediate>
1343 [possibly one last probe: stw 0,<some immediate>(12)]
1348 /* addi 12,1,-<some immediate> */
1349 if ((op
& 0xffff0000) != 0x39810000)
1352 /* lis 0,-<some immediate> */
1354 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1355 if ((op
& 0xffff0000) != 0x3c000000)
1359 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1360 /* [possibly ori 0,0,<some immediate>] */
1361 if ((op
& 0xffff0000) == 0x60000000)
1364 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1367 if (op
!= 0x7c0c0214)
1372 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1373 if (op
!= 0x7c0c0000)
1378 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1379 if ((op
& 0xff9f0001) != 0x41820000)
1382 /* addi 12,12,-<some immediate> */
1384 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1385 if ((op
& 0xffff0000) != 0x398c0000)
1390 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1391 if (op
!= 0x900c0000)
1396 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1397 if ((op
& 0xfc000001) != 0x48000000)
1400 /* [possibly one last probe: stw 0,<some immediate>(12)] */
1402 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1403 if ((op
& 0xffff0000) == 0x900c0000)
1406 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1409 /* We found a valid stack-check sequence, return the new PC. */
1413 /* Third sequence: No probe; instead, a comparizon between the stack size
1414 limit (saved in a run-time global variable) and the current stack
1417 addi 0,1,-<some immediate>
1418 lis 12,__gnat_stack_limit@ha
1419 lwz 12,__gnat_stack_limit@l(12)
1422 or, with a small variant in the case of a bigger stack frame:
1423 addis 0,1,<some immediate>
1424 addic 0,0,-<some immediate>
1425 lis 12,__gnat_stack_limit@ha
1426 lwz 12,__gnat_stack_limit@l(12)
1431 /* addi 0,1,-<some immediate> */
1432 if ((op
& 0xffff0000) != 0x38010000)
1434 /* small stack frame variant not recognized; try the
1435 big stack frame variant: */
1437 /* addis 0,1,<some immediate> */
1438 if ((op
& 0xffff0000) != 0x3c010000)
1441 /* addic 0,0,-<some immediate> */
1443 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1444 if ((op
& 0xffff0000) != 0x30000000)
1448 /* lis 12,<some immediate> */
1450 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1451 if ((op
& 0xffff0000) != 0x3d800000)
1454 /* lwz 12,<some immediate>(12) */
1456 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1457 if ((op
& 0xffff0000) != 0x818c0000)
1462 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1463 if ((op
& 0xfffffffe) != 0x7c406008)
1466 /* We found a valid stack-check sequence, return the new PC. */
1470 /* No stack check code in our prologue, return the start_pc. */
1474 /* return pc value after skipping a function prologue and also return
1475 information about a function frame.
1477 in struct rs6000_framedata fdata:
1478 - frameless is TRUE, if function does not have a frame.
1479 - nosavedpc is TRUE, if function does not save %pc value in its frame.
1480 - offset is the initial size of this stack frame --- the amount by
1481 which we decrement the sp to allocate the frame.
1482 - saved_gpr is the number of the first saved gpr.
1483 - saved_fpr is the number of the first saved fpr.
1484 - saved_vr is the number of the first saved vr.
1485 - saved_ev is the number of the first saved ev.
1486 - alloca_reg is the number of the register used for alloca() handling.
1488 - gpr_offset is the offset of the first saved gpr from the previous frame.
1489 - fpr_offset is the offset of the first saved fpr from the previous frame.
1490 - vr_offset is the offset of the first saved vr from the previous frame.
1491 - ev_offset is the offset of the first saved ev from the previous frame.
1492 - lr_offset is the offset of the saved lr
1493 - cr_offset is the offset of the saved cr
1494 - vrsave_offset is the offset of the saved vrsave register
1498 skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
, CORE_ADDR lim_pc
,
1499 struct rs6000_framedata
*fdata
)
1501 CORE_ADDR orig_pc
= pc
;
1502 CORE_ADDR last_prologue_pc
= pc
;
1503 CORE_ADDR li_found_pc
= 0;
1507 long vr_saved_offset
= 0;
1513 int vrsave_reg
= -1;
1516 int minimal_toc_loaded
= 0;
1517 int prev_insn_was_prologue_insn
= 1;
1518 int num_skip_non_prologue_insns
= 0;
1519 int r0_contains_arg
= 0;
1520 const struct bfd_arch_info
*arch_info
= gdbarch_bfd_arch_info (gdbarch
);
1521 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1522 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1524 memset (fdata
, 0, sizeof (struct rs6000_framedata
));
1525 fdata
->saved_gpr
= -1;
1526 fdata
->saved_fpr
= -1;
1527 fdata
->saved_vr
= -1;
1528 fdata
->saved_ev
= -1;
1529 fdata
->alloca_reg
= -1;
1530 fdata
->frameless
= 1;
1531 fdata
->nosavedpc
= 1;
1532 fdata
->lr_register
= -1;
1534 pc
= rs6000_skip_stack_check (gdbarch
, pc
);
1540 /* Sometimes it isn't clear if an instruction is a prologue
1541 instruction or not. When we encounter one of these ambiguous
1542 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
1543 Otherwise, we'll assume that it really is a prologue instruction. */
1544 if (prev_insn_was_prologue_insn
)
1545 last_prologue_pc
= pc
;
1547 /* Stop scanning if we've hit the limit. */
1551 prev_insn_was_prologue_insn
= 1;
1553 /* Fetch the instruction and convert it to an integer. */
1554 if (target_read_memory (pc
, buf
, 4))
1556 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1558 if ((op
& 0xfc1fffff) == 0x7c0802a6)
1560 /* Since shared library / PIC code, which needs to get its
1561 address at runtime, can appear to save more than one link
1575 remember just the first one, but skip over additional
1578 lr_reg
= (op
& 0x03e00000) >> 21;
1580 r0_contains_arg
= 0;
1583 else if ((op
& 0xfc1fffff) == 0x7c000026)
1585 cr_reg
= (op
& 0x03e00000);
1587 r0_contains_arg
= 0;
1591 else if ((op
& 0xfc1f0000) == 0xd8010000)
1592 { /* stfd Rx,NUM(r1) */
1593 reg
= GET_SRC_REG (op
);
1594 if (fdata
->saved_fpr
== -1 || fdata
->saved_fpr
> reg
)
1596 fdata
->saved_fpr
= reg
;
1597 fdata
->fpr_offset
= SIGNED_SHORT (op
) + offset
;
1602 else if (((op
& 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
1603 (((op
& 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1604 (op
& 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1605 (op
& 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
1608 reg
= GET_SRC_REG (op
);
1609 if ((op
& 0xfc1f0000) == 0xbc010000)
1610 fdata
->gpr_mask
|= ~((1U << reg
) - 1);
1612 fdata
->gpr_mask
|= 1U << reg
;
1613 if (fdata
->saved_gpr
== -1 || fdata
->saved_gpr
> reg
)
1615 fdata
->saved_gpr
= reg
;
1616 if ((op
& 0xfc1f0003) == 0xf8010000)
1618 fdata
->gpr_offset
= SIGNED_SHORT (op
) + offset
;
1623 else if ((op
& 0xffff0000) == 0x60000000)
1626 /* Allow nops in the prologue, but do not consider them to
1627 be part of the prologue unless followed by other prologue
1629 prev_insn_was_prologue_insn
= 0;
1633 else if ((op
& 0xffff0000) == 0x3c000000)
1634 { /* addis 0,0,NUM, used
1635 for >= 32k frames */
1636 fdata
->offset
= (op
& 0x0000ffff) << 16;
1637 fdata
->frameless
= 0;
1638 r0_contains_arg
= 0;
1642 else if ((op
& 0xffff0000) == 0x60000000)
1643 { /* ori 0,0,NUM, 2nd ha
1644 lf of >= 32k frames */
1645 fdata
->offset
|= (op
& 0x0000ffff);
1646 fdata
->frameless
= 0;
1647 r0_contains_arg
= 0;
1651 else if (lr_reg
>= 0 &&
1652 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1653 (((op
& 0xffff0000) == (lr_reg
| 0xf8010000)) ||
1654 /* stw Rx, NUM(r1) */
1655 ((op
& 0xffff0000) == (lr_reg
| 0x90010000)) ||
1656 /* stwu Rx, NUM(r1) */
1657 ((op
& 0xffff0000) == (lr_reg
| 0x94010000))))
1658 { /* where Rx == lr */
1659 fdata
->lr_offset
= offset
;
1660 fdata
->nosavedpc
= 0;
1661 /* Invalidate lr_reg, but don't set it to -1.
1662 That would mean that it had never been set. */
1664 if ((op
& 0xfc000003) == 0xf8000000 || /* std */
1665 (op
& 0xfc000000) == 0x90000000) /* stw */
1667 /* Does not update r1, so add displacement to lr_offset. */
1668 fdata
->lr_offset
+= SIGNED_SHORT (op
);
1673 else if (cr_reg
>= 0 &&
1674 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1675 (((op
& 0xffff0000) == (cr_reg
| 0xf8010000)) ||
1676 /* stw Rx, NUM(r1) */
1677 ((op
& 0xffff0000) == (cr_reg
| 0x90010000)) ||
1678 /* stwu Rx, NUM(r1) */
1679 ((op
& 0xffff0000) == (cr_reg
| 0x94010000))))
1680 { /* where Rx == cr */
1681 fdata
->cr_offset
= offset
;
1682 /* Invalidate cr_reg, but don't set it to -1.
1683 That would mean that it had never been set. */
1685 if ((op
& 0xfc000003) == 0xf8000000 ||
1686 (op
& 0xfc000000) == 0x90000000)
1688 /* Does not update r1, so add displacement to cr_offset. */
1689 fdata
->cr_offset
+= SIGNED_SHORT (op
);
1694 else if ((op
& 0xfe80ffff) == 0x42800005 && lr_reg
!= -1)
1696 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1697 prediction bits. If the LR has already been saved, we can
1701 else if (op
== 0x48000005)
1708 else if (op
== 0x48000004)
1713 else if ((op
& 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1714 in V.4 -mminimal-toc */
1715 (op
& 0xffff0000) == 0x3bde0000)
1716 { /* addi 30,30,foo@l */
1720 else if ((op
& 0xfc000001) == 0x48000001)
1724 fdata
->frameless
= 0;
1726 /* If the return address has already been saved, we can skip
1727 calls to blrl (for PIC). */
1728 if (lr_reg
!= -1 && bl_to_blrl_insn_p (pc
, op
, byte_order
))
1734 /* Don't skip over the subroutine call if it is not within
1735 the first three instructions of the prologue and either
1736 we have no line table information or the line info tells
1737 us that the subroutine call is not part of the line
1738 associated with the prologue. */
1739 if ((pc
- orig_pc
) > 8)
1741 struct symtab_and_line prologue_sal
= find_pc_line (orig_pc
, 0);
1742 struct symtab_and_line this_sal
= find_pc_line (pc
, 0);
1744 if ((prologue_sal
.line
== 0) || (prologue_sal
.line
!= this_sal
.line
))
1748 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
1750 /* At this point, make sure this is not a trampoline
1751 function (a function that simply calls another functions,
1752 and nothing else). If the next is not a nop, this branch
1753 was part of the function prologue. */
1755 if (op
== 0x4def7b82 || op
== 0) /* crorc 15, 15, 15 */
1756 break; /* don't skip over
1762 /* update stack pointer */
1763 else if ((op
& 0xfc1f0000) == 0x94010000)
1764 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
1765 fdata
->frameless
= 0;
1766 fdata
->offset
= SIGNED_SHORT (op
);
1767 offset
= fdata
->offset
;
1770 else if ((op
& 0xfc1f016a) == 0x7c01016e)
1771 { /* stwux rX,r1,rY */
1772 /* no way to figure out what r1 is going to be */
1773 fdata
->frameless
= 0;
1774 offset
= fdata
->offset
;
1777 else if ((op
& 0xfc1f0003) == 0xf8010001)
1778 { /* stdu rX,NUM(r1) */
1779 fdata
->frameless
= 0;
1780 fdata
->offset
= SIGNED_SHORT (op
& ~3UL);
1781 offset
= fdata
->offset
;
1784 else if ((op
& 0xfc1f016a) == 0x7c01016a)
1785 { /* stdux rX,r1,rY */
1786 /* no way to figure out what r1 is going to be */
1787 fdata
->frameless
= 0;
1788 offset
= fdata
->offset
;
1791 else if ((op
& 0xffff0000) == 0x38210000)
1792 { /* addi r1,r1,SIMM */
1793 fdata
->frameless
= 0;
1794 fdata
->offset
+= SIGNED_SHORT (op
);
1795 offset
= fdata
->offset
;
1798 /* Load up minimal toc pointer. Do not treat an epilogue restore
1799 of r31 as a minimal TOC load. */
1800 else if (((op
>> 22) == 0x20f || /* l r31,... or l r30,... */
1801 (op
>> 22) == 0x3af) /* ld r31,... or ld r30,... */
1803 && !minimal_toc_loaded
)
1805 minimal_toc_loaded
= 1;
1808 /* move parameters from argument registers to local variable
1811 else if ((op
& 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1812 (((op
>> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1813 (((op
>> 21) & 31) <= 10) &&
1814 ((long) ((op
>> 16) & 31) >= fdata
->saved_gpr
)) /* Rx: local var reg */
1818 /* store parameters in stack */
1820 /* Move parameters from argument registers to temporary register. */
1821 else if (store_param_on_stack_p (op
, framep
, &r0_contains_arg
))
1825 /* Set up frame pointer */
1827 else if (op
== 0x603f0000 /* oril r31, r1, 0x0 */
1828 || op
== 0x7c3f0b78)
1830 fdata
->frameless
= 0;
1832 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 31);
1835 /* Another way to set up the frame pointer. */
1837 else if ((op
& 0xfc1fffff) == 0x38010000)
1838 { /* addi rX, r1, 0x0 */
1839 fdata
->frameless
= 0;
1841 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
1842 + ((op
& ~0x38010000) >> 21));
1845 /* AltiVec related instructions. */
1846 /* Store the vrsave register (spr 256) in another register for
1847 later manipulation, or load a register into the vrsave
1848 register. 2 instructions are used: mfvrsave and
1849 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1850 and mtspr SPR256, Rn. */
1851 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1852 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1853 else if ((op
& 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1855 vrsave_reg
= GET_SRC_REG (op
);
1858 else if ((op
& 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1862 /* Store the register where vrsave was saved to onto the stack:
1863 rS is the register where vrsave was stored in a previous
1865 /* 100100 sssss 00001 dddddddd dddddddd */
1866 else if ((op
& 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1868 if (vrsave_reg
== GET_SRC_REG (op
))
1870 fdata
->vrsave_offset
= SIGNED_SHORT (op
) + offset
;
1875 /* Compute the new value of vrsave, by modifying the register
1876 where vrsave was saved to. */
1877 else if (((op
& 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1878 || ((op
& 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1882 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1883 in a pair of insns to save the vector registers on the
1885 /* 001110 00000 00000 iiii iiii iiii iiii */
1886 /* 001110 01110 00000 iiii iiii iiii iiii */
1887 else if ((op
& 0xffff0000) == 0x38000000 /* li r0, SIMM */
1888 || (op
& 0xffff0000) == 0x39c00000) /* li r14, SIMM */
1890 if ((op
& 0xffff0000) == 0x38000000)
1891 r0_contains_arg
= 0;
1893 vr_saved_offset
= SIGNED_SHORT (op
);
1895 /* This insn by itself is not part of the prologue, unless
1896 if part of the pair of insns mentioned above. So do not
1897 record this insn as part of the prologue yet. */
1898 prev_insn_was_prologue_insn
= 0;
1900 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1901 /* 011111 sssss 11111 00000 00111001110 */
1902 else if ((op
& 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1904 if (pc
== (li_found_pc
+ 4))
1906 vr_reg
= GET_SRC_REG (op
);
1907 /* If this is the first vector reg to be saved, or if
1908 it has a lower number than others previously seen,
1909 reupdate the frame info. */
1910 if (fdata
->saved_vr
== -1 || fdata
->saved_vr
> vr_reg
)
1912 fdata
->saved_vr
= vr_reg
;
1913 fdata
->vr_offset
= vr_saved_offset
+ offset
;
1915 vr_saved_offset
= -1;
1920 /* End AltiVec related instructions. */
1922 /* Start BookE related instructions. */
1923 /* Store gen register S at (r31+uimm).
1924 Any register less than r13 is volatile, so we don't care. */
1925 /* 000100 sssss 11111 iiiii 01100100001 */
1926 else if (arch_info
->mach
== bfd_mach_ppc_e500
1927 && (op
& 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
1929 if ((op
& 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
1932 ev_reg
= GET_SRC_REG (op
);
1933 imm
= (op
>> 11) & 0x1f;
1934 ev_offset
= imm
* 8;
1935 /* If this is the first vector reg to be saved, or if
1936 it has a lower number than others previously seen,
1937 reupdate the frame info. */
1938 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1940 fdata
->saved_ev
= ev_reg
;
1941 fdata
->ev_offset
= ev_offset
+ offset
;
1946 /* Store gen register rS at (r1+rB). */
1947 /* 000100 sssss 00001 bbbbb 01100100000 */
1948 else if (arch_info
->mach
== bfd_mach_ppc_e500
1949 && (op
& 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1951 if (pc
== (li_found_pc
+ 4))
1953 ev_reg
= GET_SRC_REG (op
);
1954 /* If this is the first vector reg to be saved, or if
1955 it has a lower number than others previously seen,
1956 reupdate the frame info. */
1957 /* We know the contents of rB from the previous instruction. */
1958 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1960 fdata
->saved_ev
= ev_reg
;
1961 fdata
->ev_offset
= vr_saved_offset
+ offset
;
1963 vr_saved_offset
= -1;
1969 /* Store gen register r31 at (rA+uimm). */
1970 /* 000100 11111 aaaaa iiiii 01100100001 */
1971 else if (arch_info
->mach
== bfd_mach_ppc_e500
1972 && (op
& 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
1974 /* Wwe know that the source register is 31 already, but
1975 it can't hurt to compute it. */
1976 ev_reg
= GET_SRC_REG (op
);
1977 ev_offset
= ((op
>> 11) & 0x1f) * 8;
1978 /* If this is the first vector reg to be saved, or if
1979 it has a lower number than others previously seen,
1980 reupdate the frame info. */
1981 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1983 fdata
->saved_ev
= ev_reg
;
1984 fdata
->ev_offset
= ev_offset
+ offset
;
1989 /* Store gen register S at (r31+r0).
1990 Store param on stack when offset from SP bigger than 4 bytes. */
1991 /* 000100 sssss 11111 00000 01100100000 */
1992 else if (arch_info
->mach
== bfd_mach_ppc_e500
1993 && (op
& 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
1995 if (pc
== (li_found_pc
+ 4))
1997 if ((op
& 0x03e00000) >= 0x01a00000)
1999 ev_reg
= GET_SRC_REG (op
);
2000 /* If this is the first vector reg to be saved, or if
2001 it has a lower number than others previously seen,
2002 reupdate the frame info. */
2003 /* We know the contents of r0 from the previous
2005 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2007 fdata
->saved_ev
= ev_reg
;
2008 fdata
->ev_offset
= vr_saved_offset
+ offset
;
2012 vr_saved_offset
= -1;
2017 /* End BookE related instructions. */
2021 unsigned int all_mask
= ~((1U << fdata
->saved_gpr
) - 1);
2023 /* Not a recognized prologue instruction.
2024 Handle optimizer code motions into the prologue by continuing
2025 the search if we have no valid frame yet or if the return
2026 address is not yet saved in the frame. Also skip instructions
2027 if some of the GPRs expected to be saved are not yet saved. */
2028 if (fdata
->frameless
== 0 && fdata
->nosavedpc
== 0
2029 && (fdata
->gpr_mask
& all_mask
) == all_mask
)
2032 if (op
== 0x4e800020 /* blr */
2033 || op
== 0x4e800420) /* bctr */
2034 /* Do not scan past epilogue in frameless functions or
2037 if ((op
& 0xf4000000) == 0x40000000) /* bxx */
2038 /* Never skip branches. */
2041 if (num_skip_non_prologue_insns
++ > max_skip_non_prologue_insns
)
2042 /* Do not scan too many insns, scanning insns is expensive with
2046 /* Continue scanning. */
2047 prev_insn_was_prologue_insn
= 0;
2053 /* I have problems with skipping over __main() that I need to address
2054 * sometime. Previously, I used to use misc_function_vector which
2055 * didn't work as well as I wanted to be. -MGO */
2057 /* If the first thing after skipping a prolog is a branch to a function,
2058 this might be a call to an initializer in main(), introduced by gcc2.
2059 We'd like to skip over it as well. Fortunately, xlc does some extra
2060 work before calling a function right after a prologue, thus we can
2061 single out such gcc2 behaviour. */
2064 if ((op
& 0xfc000001) == 0x48000001)
2065 { /* bl foo, an initializer function? */
2066 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
2068 if (op
== 0x4def7b82)
2069 { /* cror 0xf, 0xf, 0xf (nop) */
2071 /* Check and see if we are in main. If so, skip over this
2072 initializer function as well. */
2074 tmp
= find_pc_misc_function (pc
);
2076 && strcmp (misc_function_vector
[tmp
].name
, main_name ()) == 0)
2082 if (pc
== lim_pc
&& lr_reg
>= 0)
2083 fdata
->lr_register
= lr_reg
;
2085 fdata
->offset
= -fdata
->offset
;
2086 return last_prologue_pc
;
2090 rs6000_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2092 struct rs6000_framedata frame
;
2093 CORE_ADDR limit_pc
, func_addr
;
2095 /* See if we can determine the end of the prologue via the symbol table.
2096 If so, then return either PC, or the PC after the prologue, whichever
2098 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
2100 CORE_ADDR post_prologue_pc
2101 = skip_prologue_using_sal (gdbarch
, func_addr
);
2102 if (post_prologue_pc
!= 0)
2103 return max (pc
, post_prologue_pc
);
2106 /* Can't determine prologue from the symbol table, need to examine
2109 /* Find an upper limit on the function prologue using the debug
2110 information. If the debug information could not be used to provide
2111 that bound, then use an arbitrary large number as the upper bound. */
2112 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
2114 limit_pc
= pc
+ 100; /* Magic. */
2116 pc
= skip_prologue (gdbarch
, pc
, limit_pc
, &frame
);
2120 /* When compiling for EABI, some versions of GCC emit a call to __eabi
2121 in the prologue of main().
2123 The function below examines the code pointed at by PC and checks to
2124 see if it corresponds to a call to __eabi. If so, it returns the
2125 address of the instruction following that call. Otherwise, it simply
2129 rs6000_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2131 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2135 if (target_read_memory (pc
, buf
, 4))
2137 op
= extract_unsigned_integer (buf
, 4, byte_order
);
2139 if ((op
& BL_MASK
) == BL_INSTRUCTION
)
2141 CORE_ADDR displ
= op
& BL_DISPLACEMENT_MASK
;
2142 CORE_ADDR call_dest
= pc
+ 4 + displ
;
2143 struct minimal_symbol
*s
= lookup_minimal_symbol_by_pc (call_dest
);
2145 /* We check for ___eabi (three leading underscores) in addition
2146 to __eabi in case the GCC option "-fleading-underscore" was
2147 used to compile the program. */
2149 && SYMBOL_LINKAGE_NAME (s
) != NULL
2150 && (strcmp (SYMBOL_LINKAGE_NAME (s
), "__eabi") == 0
2151 || strcmp (SYMBOL_LINKAGE_NAME (s
), "___eabi") == 0))
2157 /* All the ABI's require 16 byte alignment. */
2159 rs6000_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2161 return (addr
& -16);
2164 /* Return whether handle_inferior_event() should proceed through code
2165 starting at PC in function NAME when stepping.
2167 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
2168 handle memory references that are too distant to fit in instructions
2169 generated by the compiler. For example, if 'foo' in the following
2174 is greater than 32767, the linker might replace the lwz with a branch to
2175 somewhere in @FIX1 that does the load in 2 instructions and then branches
2176 back to where execution should continue.
2178 GDB should silently step over @FIX code, just like AIX dbx does.
2179 Unfortunately, the linker uses the "b" instruction for the
2180 branches, meaning that the link register doesn't get set.
2181 Therefore, GDB's usual step_over_function () mechanism won't work.
2183 Instead, use the gdbarch_skip_trampoline_code and
2184 gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past
2188 rs6000_in_solib_return_trampoline (struct gdbarch
*gdbarch
,
2189 CORE_ADDR pc
, char *name
)
2191 return name
&& !strncmp (name
, "@FIX", 4);
2194 /* Skip code that the user doesn't want to see when stepping:
2196 1. Indirect function calls use a piece of trampoline code to do context
2197 switching, i.e. to set the new TOC table. Skip such code if we are on
2198 its first instruction (as when we have single-stepped to here).
2200 2. Skip shared library trampoline code (which is different from
2201 indirect function call trampolines).
2203 3. Skip bigtoc fixup code.
2205 Result is desired PC to step until, or NULL if we are not in
2206 code that should be skipped. */
2209 rs6000_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
2211 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2212 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2213 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2214 unsigned int ii
, op
;
2216 CORE_ADDR solib_target_pc
;
2217 struct minimal_symbol
*msymbol
;
2219 static unsigned trampoline_code
[] =
2221 0x800b0000, /* l r0,0x0(r11) */
2222 0x90410014, /* st r2,0x14(r1) */
2223 0x7c0903a6, /* mtctr r0 */
2224 0x804b0004, /* l r2,0x4(r11) */
2225 0x816b0008, /* l r11,0x8(r11) */
2226 0x4e800420, /* bctr */
2227 0x4e800020, /* br */
2231 /* Check for bigtoc fixup code. */
2232 msymbol
= lookup_minimal_symbol_by_pc (pc
);
2234 && rs6000_in_solib_return_trampoline (gdbarch
, pc
,
2235 SYMBOL_LINKAGE_NAME (msymbol
)))
2237 /* Double-check that the third instruction from PC is relative "b". */
2238 op
= read_memory_integer (pc
+ 8, 4, byte_order
);
2239 if ((op
& 0xfc000003) == 0x48000000)
2241 /* Extract bits 6-29 as a signed 24-bit relative word address and
2242 add it to the containing PC. */
2243 rel
= ((int)(op
<< 6) >> 6);
2244 return pc
+ 8 + rel
;
2248 /* If pc is in a shared library trampoline, return its target. */
2249 solib_target_pc
= find_solib_trampoline_target (frame
, pc
);
2250 if (solib_target_pc
)
2251 return solib_target_pc
;
2253 for (ii
= 0; trampoline_code
[ii
]; ++ii
)
2255 op
= read_memory_integer (pc
+ (ii
* 4), 4, byte_order
);
2256 if (op
!= trampoline_code
[ii
])
2259 ii
= get_frame_register_unsigned (frame
, 11); /* r11 holds destination addr */
2260 pc
= read_memory_unsigned_integer (ii
, tdep
->wordsize
, byte_order
);
2264 /* ISA-specific vector types. */
2266 static struct type
*
2267 rs6000_builtin_type_vec64 (struct gdbarch
*gdbarch
)
2269 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2271 if (!tdep
->ppc_builtin_type_vec64
)
2273 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2275 /* The type we're building is this: */
2277 union __gdb_builtin_type_vec64
2281 int32_t v2_int32
[2];
2282 int16_t v4_int16
[4];
2289 t
= arch_composite_type (gdbarch
,
2290 "__ppc_builtin_type_vec64", TYPE_CODE_UNION
);
2291 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2292 append_composite_type_field (t
, "v2_float",
2293 init_vector_type (bt
->builtin_float
, 2));
2294 append_composite_type_field (t
, "v2_int32",
2295 init_vector_type (bt
->builtin_int32
, 2));
2296 append_composite_type_field (t
, "v4_int16",
2297 init_vector_type (bt
->builtin_int16
, 4));
2298 append_composite_type_field (t
, "v8_int8",
2299 init_vector_type (bt
->builtin_int8
, 8));
2301 TYPE_VECTOR (t
) = 1;
2302 TYPE_NAME (t
) = "ppc_builtin_type_vec64";
2303 tdep
->ppc_builtin_type_vec64
= t
;
2306 return tdep
->ppc_builtin_type_vec64
;
2309 /* Vector 128 type. */
2311 static struct type
*
2312 rs6000_builtin_type_vec128 (struct gdbarch
*gdbarch
)
2314 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2316 if (!tdep
->ppc_builtin_type_vec128
)
2318 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2320 /* The type we're building is this
2322 type = union __ppc_builtin_type_vec128 {
2324 double v2_double[2];
2326 int32_t v4_int32[4];
2327 int16_t v8_int16[8];
2328 int8_t v16_int8[16];
2334 t
= arch_composite_type (gdbarch
,
2335 "__ppc_builtin_type_vec128", TYPE_CODE_UNION
);
2336 append_composite_type_field (t
, "uint128", bt
->builtin_uint128
);
2337 append_composite_type_field (t
, "v2_double",
2338 init_vector_type (bt
->builtin_double
, 2));
2339 append_composite_type_field (t
, "v4_float",
2340 init_vector_type (bt
->builtin_float
, 4));
2341 append_composite_type_field (t
, "v4_int32",
2342 init_vector_type (bt
->builtin_int32
, 4));
2343 append_composite_type_field (t
, "v8_int16",
2344 init_vector_type (bt
->builtin_int16
, 8));
2345 append_composite_type_field (t
, "v16_int8",
2346 init_vector_type (bt
->builtin_int8
, 16));
2348 TYPE_VECTOR (t
) = 1;
2349 TYPE_NAME (t
) = "ppc_builtin_type_vec128";
2350 tdep
->ppc_builtin_type_vec128
= t
;
2353 return tdep
->ppc_builtin_type_vec128
;
2356 /* Return the name of register number REGNO, or the empty string if it
2357 is an anonymous register. */
2360 rs6000_register_name (struct gdbarch
*gdbarch
, int regno
)
2362 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2364 /* The upper half "registers" have names in the XML description,
2365 but we present only the low GPRs and the full 64-bit registers
2367 if (tdep
->ppc_ev0_upper_regnum
>= 0
2368 && tdep
->ppc_ev0_upper_regnum
<= regno
2369 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
2372 /* Hide the upper halves of the vs0~vs31 registers. */
2373 if (tdep
->ppc_vsr0_regnum
>= 0
2374 && tdep
->ppc_vsr0_upper_regnum
<= regno
2375 && regno
< tdep
->ppc_vsr0_upper_regnum
+ ppc_num_gprs
)
2378 /* Check if the SPE pseudo registers are available. */
2379 if (IS_SPE_PSEUDOREG (tdep
, regno
))
2381 static const char *const spe_regnames
[] = {
2382 "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7",
2383 "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15",
2384 "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23",
2385 "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31",
2387 return spe_regnames
[regno
- tdep
->ppc_ev0_regnum
];
2390 /* Check if the decimal128 pseudo-registers are available. */
2391 if (IS_DFP_PSEUDOREG (tdep
, regno
))
2393 static const char *const dfp128_regnames
[] = {
2394 "dl0", "dl1", "dl2", "dl3",
2395 "dl4", "dl5", "dl6", "dl7",
2396 "dl8", "dl9", "dl10", "dl11",
2397 "dl12", "dl13", "dl14", "dl15"
2399 return dfp128_regnames
[regno
- tdep
->ppc_dl0_regnum
];
2402 /* Check if this is a VSX pseudo-register. */
2403 if (IS_VSX_PSEUDOREG (tdep
, regno
))
2405 static const char *const vsx_regnames
[] = {
2406 "vs0", "vs1", "vs2", "vs3", "vs4", "vs5", "vs6", "vs7",
2407 "vs8", "vs9", "vs10", "vs11", "vs12", "vs13", "vs14",
2408 "vs15", "vs16", "vs17", "vs18", "vs19", "vs20", "vs21",
2409 "vs22", "vs23", "vs24", "vs25", "vs26", "vs27", "vs28",
2410 "vs29", "vs30", "vs31", "vs32", "vs33", "vs34", "vs35",
2411 "vs36", "vs37", "vs38", "vs39", "vs40", "vs41", "vs42",
2412 "vs43", "vs44", "vs45", "vs46", "vs47", "vs48", "vs49",
2413 "vs50", "vs51", "vs52", "vs53", "vs54", "vs55", "vs56",
2414 "vs57", "vs58", "vs59", "vs60", "vs61", "vs62", "vs63"
2416 return vsx_regnames
[regno
- tdep
->ppc_vsr0_regnum
];
2419 /* Check if the this is a Extended FP pseudo-register. */
2420 if (IS_EFP_PSEUDOREG (tdep
, regno
))
2422 static const char *const efpr_regnames
[] = {
2423 "f32", "f33", "f34", "f35", "f36", "f37", "f38",
2424 "f39", "f40", "f41", "f42", "f43", "f44", "f45",
2425 "f46", "f47", "f48", "f49", "f50", "f51",
2426 "f52", "f53", "f54", "f55", "f56", "f57",
2427 "f58", "f59", "f60", "f61", "f62", "f63"
2429 return efpr_regnames
[regno
- tdep
->ppc_efpr0_regnum
];
2432 return tdesc_register_name (gdbarch
, regno
);
2435 /* Return the GDB type object for the "standard" data type of data in
2438 static struct type
*
2439 rs6000_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2441 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2443 /* These are the only pseudo-registers we support. */
2444 gdb_assert (IS_SPE_PSEUDOREG (tdep
, regnum
)
2445 || IS_DFP_PSEUDOREG (tdep
, regnum
)
2446 || IS_VSX_PSEUDOREG (tdep
, regnum
)
2447 || IS_EFP_PSEUDOREG (tdep
, regnum
));
2449 /* These are the e500 pseudo-registers. */
2450 if (IS_SPE_PSEUDOREG (tdep
, regnum
))
2451 return rs6000_builtin_type_vec64 (gdbarch
);
2452 else if (IS_DFP_PSEUDOREG (tdep
, regnum
))
2453 /* PPC decimal128 pseudo-registers. */
2454 return builtin_type (gdbarch
)->builtin_declong
;
2455 else if (IS_VSX_PSEUDOREG (tdep
, regnum
))
2456 /* POWER7 VSX pseudo-registers. */
2457 return rs6000_builtin_type_vec128 (gdbarch
);
2459 /* POWER7 Extended FP pseudo-registers. */
2460 return builtin_type (gdbarch
)->builtin_double
;
2463 /* Is REGNUM a member of REGGROUP? */
2465 rs6000_pseudo_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2466 struct reggroup
*group
)
2468 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2470 /* These are the only pseudo-registers we support. */
2471 gdb_assert (IS_SPE_PSEUDOREG (tdep
, regnum
)
2472 || IS_DFP_PSEUDOREG (tdep
, regnum
)
2473 || IS_VSX_PSEUDOREG (tdep
, regnum
)
2474 || IS_EFP_PSEUDOREG (tdep
, regnum
));
2476 /* These are the e500 pseudo-registers or the POWER7 VSX registers. */
2477 if (IS_SPE_PSEUDOREG (tdep
, regnum
) || IS_VSX_PSEUDOREG (tdep
, regnum
))
2478 return group
== all_reggroup
|| group
== vector_reggroup
;
2480 /* PPC decimal128 or Extended FP pseudo-registers. */
2481 return group
== all_reggroup
|| group
== float_reggroup
;
2484 /* The register format for RS/6000 floating point registers is always
2485 double, we need a conversion if the memory format is float. */
2488 rs6000_convert_register_p (struct gdbarch
*gdbarch
, int regnum
,
2491 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2493 return (tdep
->ppc_fp0_regnum
>= 0
2494 && regnum
>= tdep
->ppc_fp0_regnum
2495 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
2496 && TYPE_CODE (type
) == TYPE_CODE_FLT
2497 && TYPE_LENGTH (type
)
2498 != TYPE_LENGTH (builtin_type (gdbarch
)->builtin_double
));
2502 rs6000_register_to_value (struct frame_info
*frame
,
2507 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2508 gdb_byte from
[MAX_REGISTER_SIZE
];
2510 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
2512 get_frame_register (frame
, regnum
, from
);
2513 convert_typed_floating (from
, builtin_type (gdbarch
)->builtin_double
,
2518 rs6000_value_to_register (struct frame_info
*frame
,
2521 const gdb_byte
*from
)
2523 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2524 gdb_byte to
[MAX_REGISTER_SIZE
];
2526 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
2528 convert_typed_floating (from
, type
,
2529 to
, builtin_type (gdbarch
)->builtin_double
);
2530 put_frame_register (frame
, regnum
, to
);
2533 /* Move SPE vector register values between a 64-bit buffer and the two
2534 32-bit raw register halves in a regcache. This function handles
2535 both splitting a 64-bit value into two 32-bit halves, and joining
2536 two halves into a whole 64-bit value, depending on the function
2537 passed as the MOVE argument.
2539 EV_REG must be the number of an SPE evN vector register --- a
2540 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2543 Call MOVE once for each 32-bit half of that register, passing
2544 REGCACHE, the number of the raw register corresponding to that
2545 half, and the address of the appropriate half of BUFFER.
2547 For example, passing 'regcache_raw_read' as the MOVE function will
2548 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2549 'regcache_raw_supply' will supply the contents of BUFFER to the
2550 appropriate pair of raw registers in REGCACHE.
2552 You may need to cast away some 'const' qualifiers when passing
2553 MOVE, since this function can't tell at compile-time which of
2554 REGCACHE or BUFFER is acting as the source of the data. If C had
2555 co-variant type qualifiers, ... */
2557 e500_move_ev_register (void (*move
) (struct regcache
*regcache
,
2558 int regnum
, gdb_byte
*buf
),
2559 struct regcache
*regcache
, int ev_reg
,
2562 struct gdbarch
*arch
= get_regcache_arch (regcache
);
2563 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
2565 gdb_byte
*byte_buffer
= buffer
;
2567 gdb_assert (IS_SPE_PSEUDOREG (tdep
, ev_reg
));
2569 reg_index
= ev_reg
- tdep
->ppc_ev0_regnum
;
2571 if (gdbarch_byte_order (arch
) == BFD_ENDIAN_BIG
)
2573 move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
, byte_buffer
);
2574 move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
, byte_buffer
+ 4);
2578 move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
, byte_buffer
);
2579 move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
, byte_buffer
+ 4);
2584 e500_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2585 int reg_nr
, gdb_byte
*buffer
)
2587 e500_move_ev_register (regcache_raw_read
, regcache
, reg_nr
, buffer
);
2591 e500_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2592 int reg_nr
, const gdb_byte
*buffer
)
2594 e500_move_ev_register ((void (*) (struct regcache
*, int, gdb_byte
*))
2596 regcache
, reg_nr
, (gdb_byte
*) buffer
);
2599 /* Read method for DFP pseudo-registers. */
2601 dfp_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2602 int reg_nr
, gdb_byte
*buffer
)
2604 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2605 int reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2607 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2609 /* Read two FP registers to form a whole dl register. */
2610 regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2611 2 * reg_index
, buffer
);
2612 regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2613 2 * reg_index
+ 1, buffer
+ 8);
2617 regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2618 2 * reg_index
+ 1, buffer
+ 8);
2619 regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2620 2 * reg_index
, buffer
);
2624 /* Write method for DFP pseudo-registers. */
2626 dfp_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2627 int reg_nr
, const gdb_byte
*buffer
)
2629 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2630 int reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2632 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2634 /* Write each half of the dl register into a separate
2636 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2637 2 * reg_index
, buffer
);
2638 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2639 2 * reg_index
+ 1, buffer
+ 8);
2643 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2644 2 * reg_index
+ 1, buffer
+ 8);
2645 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2646 2 * reg_index
, buffer
);
2650 /* Read method for POWER7 VSX pseudo-registers. */
2652 vsx_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2653 int reg_nr
, gdb_byte
*buffer
)
2655 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2656 int reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2658 /* Read the portion that overlaps the VMX registers. */
2660 regcache_raw_read (regcache
, tdep
->ppc_vr0_regnum
+
2661 reg_index
- 32, buffer
);
2663 /* Read the portion that overlaps the FPR registers. */
2664 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2666 regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2668 regcache_raw_read (regcache
, tdep
->ppc_vsr0_upper_regnum
+
2669 reg_index
, buffer
+ 8);
2673 regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2674 reg_index
, buffer
+ 8);
2675 regcache_raw_read (regcache
, tdep
->ppc_vsr0_upper_regnum
+
2680 /* Write method for POWER7 VSX pseudo-registers. */
2682 vsx_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2683 int reg_nr
, const gdb_byte
*buffer
)
2685 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2686 int reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2688 /* Write the portion that overlaps the VMX registers. */
2690 regcache_raw_write (regcache
, tdep
->ppc_vr0_regnum
+
2691 reg_index
- 32, buffer
);
2693 /* Write the portion that overlaps the FPR registers. */
2694 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2696 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2698 regcache_raw_write (regcache
, tdep
->ppc_vsr0_upper_regnum
+
2699 reg_index
, buffer
+ 8);
2703 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2704 reg_index
, buffer
+ 8);
2705 regcache_raw_write (regcache
, tdep
->ppc_vsr0_upper_regnum
+
2710 /* Read method for POWER7 Extended FP pseudo-registers. */
2712 efpr_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2713 int reg_nr
, gdb_byte
*buffer
)
2715 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2716 int reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
2718 /* Read the portion that overlaps the VMX registers. */
2719 regcache_raw_read (regcache
, tdep
->ppc_vr0_regnum
+
2723 /* Write method for POWER7 Extended FP pseudo-registers. */
2725 efpr_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2726 int reg_nr
, const gdb_byte
*buffer
)
2728 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2729 int reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
2731 /* Write the portion that overlaps the VMX registers. */
2732 regcache_raw_write (regcache
, tdep
->ppc_vr0_regnum
+
2737 rs6000_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2738 int reg_nr
, gdb_byte
*buffer
)
2740 struct gdbarch
*regcache_arch
= get_regcache_arch (regcache
);
2741 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2743 gdb_assert (regcache_arch
== gdbarch
);
2745 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2746 e500_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2747 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2748 dfp_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2749 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2750 vsx_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2751 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
2752 efpr_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2754 internal_error (__FILE__
, __LINE__
,
2755 _("rs6000_pseudo_register_read: "
2756 "called on unexpected register '%s' (%d)"),
2757 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2761 rs6000_pseudo_register_write (struct gdbarch
*gdbarch
,
2762 struct regcache
*regcache
,
2763 int reg_nr
, const gdb_byte
*buffer
)
2765 struct gdbarch
*regcache_arch
= get_regcache_arch (regcache
);
2766 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2768 gdb_assert (regcache_arch
== gdbarch
);
2770 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2771 e500_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2772 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2773 dfp_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2774 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2775 vsx_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2776 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
2777 efpr_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2779 internal_error (__FILE__
, __LINE__
,
2780 _("rs6000_pseudo_register_write: "
2781 "called on unexpected register '%s' (%d)"),
2782 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2785 /* Convert a DBX STABS register number to a GDB register number. */
2787 rs6000_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
2789 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2791 if (0 <= num
&& num
<= 31)
2792 return tdep
->ppc_gp0_regnum
+ num
;
2793 else if (32 <= num
&& num
<= 63)
2794 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2795 specifies registers the architecture doesn't have? Our
2796 callers don't check the value we return. */
2797 return tdep
->ppc_fp0_regnum
+ (num
- 32);
2798 else if (77 <= num
&& num
<= 108)
2799 return tdep
->ppc_vr0_regnum
+ (num
- 77);
2800 else if (1200 <= num
&& num
< 1200 + 32)
2801 return tdep
->ppc_ev0_regnum
+ (num
- 1200);
2806 return tdep
->ppc_mq_regnum
;
2808 return tdep
->ppc_lr_regnum
;
2810 return tdep
->ppc_ctr_regnum
;
2812 return tdep
->ppc_xer_regnum
;
2814 return tdep
->ppc_vrsave_regnum
;
2816 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
2818 return tdep
->ppc_acc_regnum
;
2820 return tdep
->ppc_spefscr_regnum
;
2827 /* Convert a Dwarf 2 register number to a GDB register number. */
2829 rs6000_dwarf2_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
2831 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2833 if (0 <= num
&& num
<= 31)
2834 return tdep
->ppc_gp0_regnum
+ num
;
2835 else if (32 <= num
&& num
<= 63)
2836 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2837 specifies registers the architecture doesn't have? Our
2838 callers don't check the value we return. */
2839 return tdep
->ppc_fp0_regnum
+ (num
- 32);
2840 else if (1124 <= num
&& num
< 1124 + 32)
2841 return tdep
->ppc_vr0_regnum
+ (num
- 1124);
2842 else if (1200 <= num
&& num
< 1200 + 32)
2843 return tdep
->ppc_ev0_regnum
+ (num
- 1200);
2848 return tdep
->ppc_cr_regnum
;
2850 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
2852 return tdep
->ppc_acc_regnum
;
2854 return tdep
->ppc_mq_regnum
;
2856 return tdep
->ppc_xer_regnum
;
2858 return tdep
->ppc_lr_regnum
;
2860 return tdep
->ppc_ctr_regnum
;
2862 return tdep
->ppc_vrsave_regnum
;
2864 return tdep
->ppc_spefscr_regnum
;
2870 /* Translate a .eh_frame register to DWARF register, or adjust a
2871 .debug_frame register. */
2874 rs6000_adjust_frame_regnum (struct gdbarch
*gdbarch
, int num
, int eh_frame_p
)
2876 /* GCC releases before 3.4 use GCC internal register numbering in
2877 .debug_frame (and .debug_info, et cetera). The numbering is
2878 different from the standard SysV numbering for everything except
2879 for GPRs and FPRs. We can not detect this problem in most cases
2880 - to get accurate debug info for variables living in lr, ctr, v0,
2881 et cetera, use a newer version of GCC. But we must detect
2882 one important case - lr is in column 65 in .debug_frame output,
2885 GCC 3.4, and the "hammer" branch, have a related problem. They
2886 record lr register saves in .debug_frame as 108, but still record
2887 the return column as 65. We fix that up too.
2889 We can do this because 65 is assigned to fpsr, and GCC never
2890 generates debug info referring to it. To add support for
2891 handwritten debug info that restores fpsr, we would need to add a
2892 producer version check to this. */
2901 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
2902 internal register numbering; translate that to the standard DWARF2
2903 register numbering. */
2904 if (0 <= num
&& num
<= 63) /* r0-r31,fp0-fp31 */
2906 else if (68 <= num
&& num
<= 75) /* cr0-cr8 */
2907 return num
- 68 + 86;
2908 else if (77 <= num
&& num
<= 108) /* vr0-vr31 */
2909 return num
- 77 + 1124;
2921 case 109: /* vrsave */
2923 case 110: /* vscr */
2925 case 111: /* spe_acc */
2927 case 112: /* spefscr */
2935 /* Handling the various POWER/PowerPC variants. */
2937 /* Information about a particular processor variant. */
2941 /* Name of this variant. */
2944 /* English description of the variant. */
2947 /* bfd_arch_info.arch corresponding to variant. */
2948 enum bfd_architecture arch
;
2950 /* bfd_arch_info.mach corresponding to variant. */
2953 /* Target description for this variant. */
2954 struct target_desc
**tdesc
;
2957 static struct variant variants
[] =
2959 {"powerpc", "PowerPC user-level", bfd_arch_powerpc
,
2960 bfd_mach_ppc
, &tdesc_powerpc_altivec32
},
2961 {"power", "POWER user-level", bfd_arch_rs6000
,
2962 bfd_mach_rs6k
, &tdesc_rs6000
},
2963 {"403", "IBM PowerPC 403", bfd_arch_powerpc
,
2964 bfd_mach_ppc_403
, &tdesc_powerpc_403
},
2965 {"405", "IBM PowerPC 405", bfd_arch_powerpc
,
2966 bfd_mach_ppc_405
, &tdesc_powerpc_405
},
2967 {"601", "Motorola PowerPC 601", bfd_arch_powerpc
,
2968 bfd_mach_ppc_601
, &tdesc_powerpc_601
},
2969 {"602", "Motorola PowerPC 602", bfd_arch_powerpc
,
2970 bfd_mach_ppc_602
, &tdesc_powerpc_602
},
2971 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc
,
2972 bfd_mach_ppc_603
, &tdesc_powerpc_603
},
2973 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc
,
2974 604, &tdesc_powerpc_604
},
2975 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc
,
2976 bfd_mach_ppc_403gc
, &tdesc_powerpc_403gc
},
2977 {"505", "Motorola PowerPC 505", bfd_arch_powerpc
,
2978 bfd_mach_ppc_505
, &tdesc_powerpc_505
},
2979 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc
,
2980 bfd_mach_ppc_860
, &tdesc_powerpc_860
},
2981 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc
,
2982 bfd_mach_ppc_750
, &tdesc_powerpc_750
},
2983 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc
,
2984 bfd_mach_ppc_7400
, &tdesc_powerpc_7400
},
2985 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc
,
2986 bfd_mach_ppc_e500
, &tdesc_powerpc_e500
},
2989 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc
,
2990 bfd_mach_ppc64
, &tdesc_powerpc_altivec64
},
2991 {"620", "Motorola PowerPC 620", bfd_arch_powerpc
,
2992 bfd_mach_ppc_620
, &tdesc_powerpc_64
},
2993 {"630", "Motorola PowerPC 630", bfd_arch_powerpc
,
2994 bfd_mach_ppc_630
, &tdesc_powerpc_64
},
2995 {"a35", "PowerPC A35", bfd_arch_powerpc
,
2996 bfd_mach_ppc_a35
, &tdesc_powerpc_64
},
2997 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc
,
2998 bfd_mach_ppc_rs64ii
, &tdesc_powerpc_64
},
2999 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc
,
3000 bfd_mach_ppc_rs64iii
, &tdesc_powerpc_64
},
3002 /* FIXME: I haven't checked the register sets of the following. */
3003 {"rs1", "IBM POWER RS1", bfd_arch_rs6000
,
3004 bfd_mach_rs6k_rs1
, &tdesc_rs6000
},
3005 {"rsc", "IBM POWER RSC", bfd_arch_rs6000
,
3006 bfd_mach_rs6k_rsc
, &tdesc_rs6000
},
3007 {"rs2", "IBM POWER RS2", bfd_arch_rs6000
,
3008 bfd_mach_rs6k_rs2
, &tdesc_rs6000
},
3013 /* Return the variant corresponding to architecture ARCH and machine number
3014 MACH. If no such variant exists, return null. */
3016 static const struct variant
*
3017 find_variant_by_arch (enum bfd_architecture arch
, unsigned long mach
)
3019 const struct variant
*v
;
3021 for (v
= variants
; v
->name
; v
++)
3022 if (arch
== v
->arch
&& mach
== v
->mach
)
3029 gdb_print_insn_powerpc (bfd_vma memaddr
, disassemble_info
*info
)
3031 if (!info
->disassembler_options
)
3033 /* When debugging E500 binaries and disassembling code containing
3034 E500-specific (SPE) instructions, one sometimes sees AltiVec
3035 instructions instead. The opcode spaces for SPE instructions
3036 and AltiVec instructions overlap, and specifiying the "any" cpu
3037 looks for AltiVec instructions first. If we know we're
3038 debugging an E500 binary, however, we can specify the "e500x2"
3039 cpu and get much more sane disassembly output. */
3040 if (info
->mach
== bfd_mach_ppc_e500
)
3041 info
->disassembler_options
= "e500x2";
3043 info
->disassembler_options
= "any";
3046 if (info
->endian
== BFD_ENDIAN_BIG
)
3047 return print_insn_big_powerpc (memaddr
, info
);
3049 return print_insn_little_powerpc (memaddr
, info
);
3053 rs6000_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
3055 return frame_unwind_register_unsigned (next_frame
,
3056 gdbarch_pc_regnum (gdbarch
));
3059 static struct frame_id
3060 rs6000_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3062 return frame_id_build (get_frame_register_unsigned
3063 (this_frame
, gdbarch_sp_regnum (gdbarch
)),
3064 get_frame_pc (this_frame
));
3067 struct rs6000_frame_cache
3070 CORE_ADDR initial_sp
;
3071 struct trad_frame_saved_reg
*saved_regs
;
3074 static struct rs6000_frame_cache
*
3075 rs6000_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3077 struct rs6000_frame_cache
*cache
;
3078 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3079 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3080 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3081 struct rs6000_framedata fdata
;
3082 int wordsize
= tdep
->wordsize
;
3085 if ((*this_cache
) != NULL
)
3086 return (*this_cache
);
3087 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
3088 (*this_cache
) = cache
;
3089 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3091 func
= get_frame_func (this_frame
);
3092 pc
= get_frame_pc (this_frame
);
3093 skip_prologue (gdbarch
, func
, pc
, &fdata
);
3095 /* Figure out the parent's stack pointer. */
3097 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
3098 address of the current frame. Things might be easier if the
3099 ->frame pointed to the outer-most address of the frame. In
3100 the mean time, the address of the prev frame is used as the
3101 base address of this frame. */
3102 cache
->base
= get_frame_register_unsigned
3103 (this_frame
, gdbarch_sp_regnum (gdbarch
));
3105 /* If the function appears to be frameless, check a couple of likely
3106 indicators that we have simply failed to find the frame setup.
3107 Two common cases of this are missing symbols (i.e.
3108 get_frame_func returns the wrong address or 0), and assembly
3109 stubs which have a fast exit path but set up a frame on the slow
3112 If the LR appears to return to this function, then presume that
3113 we have an ABI compliant frame that we failed to find. */
3114 if (fdata
.frameless
&& fdata
.lr_offset
== 0)
3119 saved_lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
3120 if (func
== 0 && saved_lr
== pc
)
3124 CORE_ADDR saved_func
= get_pc_function_start (saved_lr
);
3125 if (func
== saved_func
)
3131 fdata
.frameless
= 0;
3132 fdata
.lr_offset
= tdep
->lr_frame_offset
;
3136 if (!fdata
.frameless
)
3137 /* Frameless really means stackless. */
3139 = read_memory_unsigned_integer (cache
->base
, wordsize
, byte_order
);
3141 trad_frame_set_value (cache
->saved_regs
,
3142 gdbarch_sp_regnum (gdbarch
), cache
->base
);
3144 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
3145 All fpr's from saved_fpr to fp31 are saved. */
3147 if (fdata
.saved_fpr
>= 0)
3150 CORE_ADDR fpr_addr
= cache
->base
+ fdata
.fpr_offset
;
3152 /* If skip_prologue says floating-point registers were saved,
3153 but the current architecture has no floating-point registers,
3154 then that's strange. But we have no indices to even record
3155 the addresses under, so we just ignore it. */
3156 if (ppc_floating_point_unit_p (gdbarch
))
3157 for (i
= fdata
.saved_fpr
; i
< ppc_num_fprs
; i
++)
3159 cache
->saved_regs
[tdep
->ppc_fp0_regnum
+ i
].addr
= fpr_addr
;
3164 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
3165 All gpr's from saved_gpr to gpr31 are saved (except during the
3168 if (fdata
.saved_gpr
>= 0)
3171 CORE_ADDR gpr_addr
= cache
->base
+ fdata
.gpr_offset
;
3172 for (i
= fdata
.saved_gpr
; i
< ppc_num_gprs
; i
++)
3174 if (fdata
.gpr_mask
& (1U << i
))
3175 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= gpr_addr
;
3176 gpr_addr
+= wordsize
;
3180 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
3181 All vr's from saved_vr to vr31 are saved. */
3182 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
3184 if (fdata
.saved_vr
>= 0)
3187 CORE_ADDR vr_addr
= cache
->base
+ fdata
.vr_offset
;
3188 for (i
= fdata
.saved_vr
; i
< 32; i
++)
3190 cache
->saved_regs
[tdep
->ppc_vr0_regnum
+ i
].addr
= vr_addr
;
3191 vr_addr
+= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
3196 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
3197 All vr's from saved_ev to ev31 are saved. ????? */
3198 if (tdep
->ppc_ev0_regnum
!= -1)
3200 if (fdata
.saved_ev
>= 0)
3203 CORE_ADDR ev_addr
= cache
->base
+ fdata
.ev_offset
;
3204 for (i
= fdata
.saved_ev
; i
< ppc_num_gprs
; i
++)
3206 cache
->saved_regs
[tdep
->ppc_ev0_regnum
+ i
].addr
= ev_addr
;
3207 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= ev_addr
+ 4;
3208 ev_addr
+= register_size (gdbarch
, tdep
->ppc_ev0_regnum
);
3213 /* If != 0, fdata.cr_offset is the offset from the frame that
3215 if (fdata
.cr_offset
!= 0)
3216 cache
->saved_regs
[tdep
->ppc_cr_regnum
].addr
= cache
->base
+ fdata
.cr_offset
;
3218 /* If != 0, fdata.lr_offset is the offset from the frame that
3220 if (fdata
.lr_offset
!= 0)
3221 cache
->saved_regs
[tdep
->ppc_lr_regnum
].addr
= cache
->base
+ fdata
.lr_offset
;
3222 else if (fdata
.lr_register
!= -1)
3223 cache
->saved_regs
[tdep
->ppc_lr_regnum
].realreg
= fdata
.lr_register
;
3224 /* The PC is found in the link register. */
3225 cache
->saved_regs
[gdbarch_pc_regnum (gdbarch
)] =
3226 cache
->saved_regs
[tdep
->ppc_lr_regnum
];
3228 /* If != 0, fdata.vrsave_offset is the offset from the frame that
3229 holds the VRSAVE. */
3230 if (fdata
.vrsave_offset
!= 0)
3231 cache
->saved_regs
[tdep
->ppc_vrsave_regnum
].addr
= cache
->base
+ fdata
.vrsave_offset
;
3233 if (fdata
.alloca_reg
< 0)
3234 /* If no alloca register used, then fi->frame is the value of the
3235 %sp for this frame, and it is good enough. */
3237 = get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
3240 = get_frame_register_unsigned (this_frame
, fdata
.alloca_reg
);
3246 rs6000_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3247 struct frame_id
*this_id
)
3249 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3251 /* This marks the outermost frame. */
3252 if (info
->base
== 0)
3255 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3258 static struct value
*
3259 rs6000_frame_prev_register (struct frame_info
*this_frame
,
3260 void **this_cache
, int regnum
)
3262 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3264 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3267 static const struct frame_unwind rs6000_frame_unwind
=
3270 rs6000_frame_this_id
,
3271 rs6000_frame_prev_register
,
3273 default_frame_sniffer
3278 rs6000_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
3280 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3282 return info
->initial_sp
;
3285 static const struct frame_base rs6000_frame_base
= {
3286 &rs6000_frame_unwind
,
3287 rs6000_frame_base_address
,
3288 rs6000_frame_base_address
,
3289 rs6000_frame_base_address
3292 static const struct frame_base
*
3293 rs6000_frame_base_sniffer (struct frame_info
*this_frame
)
3295 return &rs6000_frame_base
;
3298 /* DWARF-2 frame support. Used to handle the detection of
3299 clobbered registers during function calls. */
3302 ppc_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
3303 struct dwarf2_frame_state_reg
*reg
,
3304 struct frame_info
*this_frame
)
3306 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3308 /* PPC32 and PPC64 ABI's are the same regarding volatile and
3309 non-volatile registers. We will use the same code for both. */
3311 /* Call-saved GP registers. */
3312 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 14
3313 && regnum
<= tdep
->ppc_gp0_regnum
+ 31)
3314 || (regnum
== tdep
->ppc_gp0_regnum
+ 1))
3315 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3317 /* Call-clobbered GP registers. */
3318 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 3
3319 && regnum
<= tdep
->ppc_gp0_regnum
+ 12)
3320 || (regnum
== tdep
->ppc_gp0_regnum
))
3321 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3323 /* Deal with FP registers, if supported. */
3324 if (tdep
->ppc_fp0_regnum
>= 0)
3326 /* Call-saved FP registers. */
3327 if ((regnum
>= tdep
->ppc_fp0_regnum
+ 14
3328 && regnum
<= tdep
->ppc_fp0_regnum
+ 31))
3329 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3331 /* Call-clobbered FP registers. */
3332 if ((regnum
>= tdep
->ppc_fp0_regnum
3333 && regnum
<= tdep
->ppc_fp0_regnum
+ 13))
3334 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3337 /* Deal with ALTIVEC registers, if supported. */
3338 if (tdep
->ppc_vr0_regnum
> 0 && tdep
->ppc_vrsave_regnum
> 0)
3340 /* Call-saved Altivec registers. */
3341 if ((regnum
>= tdep
->ppc_vr0_regnum
+ 20
3342 && regnum
<= tdep
->ppc_vr0_regnum
+ 31)
3343 || regnum
== tdep
->ppc_vrsave_regnum
)
3344 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3346 /* Call-clobbered Altivec registers. */
3347 if ((regnum
>= tdep
->ppc_vr0_regnum
3348 && regnum
<= tdep
->ppc_vr0_regnum
+ 19))
3349 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3352 /* Handle PC register and Stack Pointer correctly. */
3353 if (regnum
== gdbarch_pc_regnum (gdbarch
))
3354 reg
->how
= DWARF2_FRAME_REG_RA
;
3355 else if (regnum
== gdbarch_sp_regnum (gdbarch
))
3356 reg
->how
= DWARF2_FRAME_REG_CFA
;
3360 /* Return true if a .gnu_attributes section exists in BFD and it
3361 indicates we are using SPE extensions OR if a .PPC.EMB.apuinfo
3362 section exists in BFD and it indicates that SPE extensions are in
3363 use. Check the .gnu.attributes section first, as the binary might be
3364 compiled for SPE, but not actually using SPE instructions. */
3367 bfd_uses_spe_extensions (bfd
*abfd
)
3370 gdb_byte
*contents
= NULL
;
3380 /* Using Tag_GNU_Power_ABI_Vector here is a bit of a hack, as the user
3381 could be using the SPE vector abi without actually using any spe
3382 bits whatsoever. But it's close enough for now. */
3383 vector_abi
= bfd_elf_get_obj_attr_int (abfd
, OBJ_ATTR_GNU
,
3384 Tag_GNU_Power_ABI_Vector
);
3385 if (vector_abi
== 3)
3389 sect
= bfd_get_section_by_name (abfd
, ".PPC.EMB.apuinfo");
3393 size
= bfd_get_section_size (sect
);
3394 contents
= xmalloc (size
);
3395 if (!bfd_get_section_contents (abfd
, sect
, contents
, 0, size
))
3401 /* Parse the .PPC.EMB.apuinfo section. The layout is as follows:
3407 char name[name_len rounded up to 4-byte alignment];
3408 char data[data_len];
3411 Technically, there's only supposed to be one such structure in a
3412 given apuinfo section, but the linker is not always vigilant about
3413 merging apuinfo sections from input files. Just go ahead and parse
3414 them all, exiting early when we discover the binary uses SPE
3417 It's not specified in what endianness the information in this
3418 section is stored. Assume that it's the endianness of the BFD. */
3422 unsigned int name_len
;
3423 unsigned int data_len
;
3426 /* If we can't read the first three fields, we're done. */
3430 name_len
= bfd_get_32 (abfd
, ptr
);
3431 name_len
= (name_len
+ 3) & ~3U; /* Round to 4 bytes. */
3432 data_len
= bfd_get_32 (abfd
, ptr
+ 4);
3433 type
= bfd_get_32 (abfd
, ptr
+ 8);
3436 /* The name must be "APUinfo\0". */
3438 && strcmp ((const char *) ptr
, "APUinfo") != 0)
3442 /* The type must be 2. */
3446 /* The data is stored as a series of uint32. The upper half of
3447 each uint32 indicates the particular APU used and the lower
3448 half indicates the revision of that APU. We just care about
3451 /* Not 4-byte quantities. */
3457 unsigned int apuinfo
= bfd_get_32 (abfd
, ptr
);
3458 unsigned int apu
= apuinfo
>> 16;
3462 /* The SPE APU is 0x100; the SPEFP APU is 0x101. Accept
3464 if (apu
== 0x100 || apu
== 0x101)
3479 /* Initialize the current architecture based on INFO. If possible, re-use an
3480 architecture from ARCHES, which is a list of architectures already created
3481 during this debugging session.
3483 Called e.g. at program startup, when reading a core file, and when reading
3486 static struct gdbarch
*
3487 rs6000_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
3489 struct gdbarch
*gdbarch
;
3490 struct gdbarch_tdep
*tdep
;
3491 int wordsize
, from_xcoff_exec
, from_elf_exec
;
3492 enum bfd_architecture arch
;
3496 enum auto_boolean soft_float_flag
= powerpc_soft_float_global
;
3498 enum powerpc_vector_abi vector_abi
= powerpc_vector_abi_global
;
3499 int have_fpu
= 1, have_spe
= 0, have_mq
= 0, have_altivec
= 0, have_dfp
= 0,
3501 int tdesc_wordsize
= -1;
3502 const struct target_desc
*tdesc
= info
.target_desc
;
3503 struct tdesc_arch_data
*tdesc_data
= NULL
;
3504 int num_pseudoregs
= 0;
3507 /* INFO may refer to a binary that is not of the PowerPC architecture,
3508 e.g. when debugging a stand-alone SPE executable on a Cell/B.E. system.
3509 In this case, we must not attempt to infer properties of the (PowerPC
3510 side) of the target system from properties of that executable. Trust
3511 the target description instead. */
3513 && bfd_get_arch (info
.abfd
) != bfd_arch_powerpc
3514 && bfd_get_arch (info
.abfd
) != bfd_arch_rs6000
)
3517 from_xcoff_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
3518 bfd_get_flavour (info
.abfd
) == bfd_target_xcoff_flavour
;
3520 from_elf_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
3521 bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
;
3523 /* Check word size. If INFO is from a binary file, infer it from
3524 that, else choose a likely default. */
3525 if (from_xcoff_exec
)
3527 if (bfd_xcoff_is_xcoff64 (info
.abfd
))
3532 else if (from_elf_exec
)
3534 if (elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
3539 else if (tdesc_has_registers (tdesc
))
3543 if (info
.bfd_arch_info
!= NULL
&& info
.bfd_arch_info
->bits_per_word
!= 0)
3544 wordsize
= info
.bfd_arch_info
->bits_per_word
/
3545 info
.bfd_arch_info
->bits_per_byte
;
3550 /* Get the architecture and machine from the BFD. */
3551 arch
= info
.bfd_arch_info
->arch
;
3552 mach
= info
.bfd_arch_info
->mach
;
3554 /* For e500 executables, the apuinfo section is of help here. Such
3555 section contains the identifier and revision number of each
3556 Application-specific Processing Unit that is present on the
3557 chip. The content of the section is determined by the assembler
3558 which looks at each instruction and determines which unit (and
3559 which version of it) can execute it. Grovel through the section
3560 looking for relevant e500 APUs. */
3562 if (bfd_uses_spe_extensions (info
.abfd
))
3564 arch
= info
.bfd_arch_info
->arch
;
3565 mach
= bfd_mach_ppc_e500
;
3566 bfd_default_set_arch_mach (&abfd
, arch
, mach
);
3567 info
.bfd_arch_info
= bfd_get_arch_info (&abfd
);
3570 /* Find a default target description which describes our register
3571 layout, if we do not already have one. */
3572 if (! tdesc_has_registers (tdesc
))
3574 const struct variant
*v
;
3576 /* Choose variant. */
3577 v
= find_variant_by_arch (arch
, mach
);
3584 gdb_assert (tdesc_has_registers (tdesc
));
3586 /* Check any target description for validity. */
3587 if (tdesc_has_registers (tdesc
))
3589 static const char *const gprs
[] = {
3590 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
3591 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
3592 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
3593 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
3595 static const char *const segment_regs
[] = {
3596 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
3597 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
3599 const struct tdesc_feature
*feature
;
3601 static const char *const msr_names
[] = { "msr", "ps" };
3602 static const char *const cr_names
[] = { "cr", "cnd" };
3603 static const char *const ctr_names
[] = { "ctr", "cnt" };
3605 feature
= tdesc_find_feature (tdesc
,
3606 "org.gnu.gdb.power.core");
3607 if (feature
== NULL
)
3610 tdesc_data
= tdesc_data_alloc ();
3613 for (i
= 0; i
< ppc_num_gprs
; i
++)
3614 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
, gprs
[i
]);
3615 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_PC_REGNUM
,
3617 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_LR_REGNUM
,
3619 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_XER_REGNUM
,
3622 /* Allow alternate names for these registers, to accomodate GDB's
3624 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
3625 PPC_MSR_REGNUM
, msr_names
);
3626 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
3627 PPC_CR_REGNUM
, cr_names
);
3628 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
3629 PPC_CTR_REGNUM
, ctr_names
);
3633 tdesc_data_cleanup (tdesc_data
);
3637 have_mq
= tdesc_numbered_register (feature
, tdesc_data
, PPC_MQ_REGNUM
,
3640 tdesc_wordsize
= tdesc_register_size (feature
, "pc") / 8;
3642 wordsize
= tdesc_wordsize
;
3644 feature
= tdesc_find_feature (tdesc
,
3645 "org.gnu.gdb.power.fpu");
3646 if (feature
!= NULL
)
3648 static const char *const fprs
[] = {
3649 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
3650 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
3651 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
3652 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
3655 for (i
= 0; i
< ppc_num_fprs
; i
++)
3656 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
3657 PPC_F0_REGNUM
+ i
, fprs
[i
]);
3658 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
3659 PPC_FPSCR_REGNUM
, "fpscr");
3663 tdesc_data_cleanup (tdesc_data
);
3671 /* The DFP pseudo-registers will be available when there are floating
3673 have_dfp
= have_fpu
;
3675 feature
= tdesc_find_feature (tdesc
,
3676 "org.gnu.gdb.power.altivec");
3677 if (feature
!= NULL
)
3679 static const char *const vector_regs
[] = {
3680 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
3681 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
3682 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
3683 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31"
3687 for (i
= 0; i
< ppc_num_gprs
; i
++)
3688 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
3691 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
3692 PPC_VSCR_REGNUM
, "vscr");
3693 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
3694 PPC_VRSAVE_REGNUM
, "vrsave");
3696 if (have_spe
|| !valid_p
)
3698 tdesc_data_cleanup (tdesc_data
);
3706 /* Check for POWER7 VSX registers support. */
3707 feature
= tdesc_find_feature (tdesc
,
3708 "org.gnu.gdb.power.vsx");
3710 if (feature
!= NULL
)
3712 static const char *const vsx_regs
[] = {
3713 "vs0h", "vs1h", "vs2h", "vs3h", "vs4h", "vs5h",
3714 "vs6h", "vs7h", "vs8h", "vs9h", "vs10h", "vs11h",
3715 "vs12h", "vs13h", "vs14h", "vs15h", "vs16h", "vs17h",
3716 "vs18h", "vs19h", "vs20h", "vs21h", "vs22h", "vs23h",
3717 "vs24h", "vs25h", "vs26h", "vs27h", "vs28h", "vs29h",
3723 for (i
= 0; i
< ppc_num_vshrs
; i
++)
3724 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
3725 PPC_VSR0_UPPER_REGNUM
+ i
,
3729 tdesc_data_cleanup (tdesc_data
);
3738 /* On machines supporting the SPE APU, the general-purpose registers
3739 are 64 bits long. There are SIMD vector instructions to treat them
3740 as pairs of floats, but the rest of the instruction set treats them
3741 as 32-bit registers, and only operates on their lower halves.
3743 In the GDB regcache, we treat their high and low halves as separate
3744 registers. The low halves we present as the general-purpose
3745 registers, and then we have pseudo-registers that stitch together
3746 the upper and lower halves and present them as pseudo-registers.
3748 Thus, the target description is expected to supply the upper
3749 halves separately. */
3751 feature
= tdesc_find_feature (tdesc
,
3752 "org.gnu.gdb.power.spe");
3753 if (feature
!= NULL
)
3755 static const char *const upper_spe
[] = {
3756 "ev0h", "ev1h", "ev2h", "ev3h",
3757 "ev4h", "ev5h", "ev6h", "ev7h",
3758 "ev8h", "ev9h", "ev10h", "ev11h",
3759 "ev12h", "ev13h", "ev14h", "ev15h",
3760 "ev16h", "ev17h", "ev18h", "ev19h",
3761 "ev20h", "ev21h", "ev22h", "ev23h",
3762 "ev24h", "ev25h", "ev26h", "ev27h",
3763 "ev28h", "ev29h", "ev30h", "ev31h"
3767 for (i
= 0; i
< ppc_num_gprs
; i
++)
3768 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
3769 PPC_SPE_UPPER_GP0_REGNUM
+ i
,
3771 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
3772 PPC_SPE_ACC_REGNUM
, "acc");
3773 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
3774 PPC_SPE_FSCR_REGNUM
, "spefscr");
3776 if (have_mq
|| have_fpu
|| !valid_p
)
3778 tdesc_data_cleanup (tdesc_data
);
3787 /* If we have a 64-bit binary on a 32-bit target, complain. Also
3788 complain for a 32-bit binary on a 64-bit target; we do not yet
3789 support that. For instance, the 32-bit ABI routines expect
3792 As long as there isn't an explicit target description, we'll
3793 choose one based on the BFD architecture and get a word size
3794 matching the binary (probably powerpc:common or
3795 powerpc:common64). So there is only trouble if a 64-bit target
3796 supplies a 64-bit description while debugging a 32-bit
3798 if (tdesc_wordsize
!= -1 && tdesc_wordsize
!= wordsize
)
3800 tdesc_data_cleanup (tdesc_data
);
3805 if (soft_float_flag
== AUTO_BOOLEAN_AUTO
&& from_elf_exec
)
3807 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
3808 Tag_GNU_Power_ABI_FP
))
3811 soft_float_flag
= AUTO_BOOLEAN_FALSE
;
3814 soft_float_flag
= AUTO_BOOLEAN_TRUE
;
3821 if (vector_abi
== POWERPC_VEC_AUTO
&& from_elf_exec
)
3823 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
3824 Tag_GNU_Power_ABI_Vector
))
3827 vector_abi
= POWERPC_VEC_GENERIC
;
3830 vector_abi
= POWERPC_VEC_ALTIVEC
;
3833 vector_abi
= POWERPC_VEC_SPE
;
3841 if (soft_float_flag
== AUTO_BOOLEAN_TRUE
)
3843 else if (soft_float_flag
== AUTO_BOOLEAN_FALSE
)
3846 soft_float
= !have_fpu
;
3848 /* If we have a hard float binary or setting but no floating point
3849 registers, downgrade to soft float anyway. We're still somewhat
3850 useful in this scenario. */
3851 if (!soft_float
&& !have_fpu
)
3854 /* Similarly for vector registers. */
3855 if (vector_abi
== POWERPC_VEC_ALTIVEC
&& !have_altivec
)
3856 vector_abi
= POWERPC_VEC_GENERIC
;
3858 if (vector_abi
== POWERPC_VEC_SPE
&& !have_spe
)
3859 vector_abi
= POWERPC_VEC_GENERIC
;
3861 if (vector_abi
== POWERPC_VEC_AUTO
)
3864 vector_abi
= POWERPC_VEC_ALTIVEC
;
3866 vector_abi
= POWERPC_VEC_SPE
;
3868 vector_abi
= POWERPC_VEC_GENERIC
;
3871 /* Do not limit the vector ABI based on available hardware, since we
3872 do not yet know what hardware we'll decide we have. Yuck! FIXME! */
3874 /* Find a candidate among extant architectures. */
3875 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
3877 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
3879 /* Word size in the various PowerPC bfd_arch_info structs isn't
3880 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
3881 separate word size check. */
3882 tdep
= gdbarch_tdep (arches
->gdbarch
);
3883 if (tdep
&& tdep
->soft_float
!= soft_float
)
3885 if (tdep
&& tdep
->vector_abi
!= vector_abi
)
3887 if (tdep
&& tdep
->wordsize
== wordsize
)
3889 if (tdesc_data
!= NULL
)
3890 tdesc_data_cleanup (tdesc_data
);
3891 return arches
->gdbarch
;
3895 /* None found, create a new architecture from INFO, whose bfd_arch_info
3896 validity depends on the source:
3897 - executable useless
3898 - rs6000_host_arch() good
3900 - "set arch" trust blindly
3901 - GDB startup useless but harmless */
3903 tdep
= XCALLOC (1, struct gdbarch_tdep
);
3904 tdep
->wordsize
= wordsize
;
3905 tdep
->soft_float
= soft_float
;
3906 tdep
->vector_abi
= vector_abi
;
3908 gdbarch
= gdbarch_alloc (&info
, tdep
);
3910 tdep
->ppc_gp0_regnum
= PPC_R0_REGNUM
;
3911 tdep
->ppc_toc_regnum
= PPC_R0_REGNUM
+ 2;
3912 tdep
->ppc_ps_regnum
= PPC_MSR_REGNUM
;
3913 tdep
->ppc_cr_regnum
= PPC_CR_REGNUM
;
3914 tdep
->ppc_lr_regnum
= PPC_LR_REGNUM
;
3915 tdep
->ppc_ctr_regnum
= PPC_CTR_REGNUM
;
3916 tdep
->ppc_xer_regnum
= PPC_XER_REGNUM
;
3917 tdep
->ppc_mq_regnum
= have_mq
? PPC_MQ_REGNUM
: -1;
3919 tdep
->ppc_fp0_regnum
= have_fpu
? PPC_F0_REGNUM
: -1;
3920 tdep
->ppc_fpscr_regnum
= have_fpu
? PPC_FPSCR_REGNUM
: -1;
3921 tdep
->ppc_vsr0_upper_regnum
= have_vsx
? PPC_VSR0_UPPER_REGNUM
: -1;
3922 tdep
->ppc_vr0_regnum
= have_altivec
? PPC_VR0_REGNUM
: -1;
3923 tdep
->ppc_vrsave_regnum
= have_altivec
? PPC_VRSAVE_REGNUM
: -1;
3924 tdep
->ppc_ev0_upper_regnum
= have_spe
? PPC_SPE_UPPER_GP0_REGNUM
: -1;
3925 tdep
->ppc_acc_regnum
= have_spe
? PPC_SPE_ACC_REGNUM
: -1;
3926 tdep
->ppc_spefscr_regnum
= have_spe
? PPC_SPE_FSCR_REGNUM
: -1;
3928 set_gdbarch_pc_regnum (gdbarch
, PPC_PC_REGNUM
);
3929 set_gdbarch_sp_regnum (gdbarch
, PPC_R0_REGNUM
+ 1);
3930 set_gdbarch_deprecated_fp_regnum (gdbarch
, PPC_R0_REGNUM
+ 1);
3931 set_gdbarch_fp0_regnum (gdbarch
, tdep
->ppc_fp0_regnum
);
3932 set_gdbarch_register_sim_regno (gdbarch
, rs6000_register_sim_regno
);
3934 /* The XML specification for PowerPC sensibly calls the MSR "msr".
3935 GDB traditionally called it "ps", though, so let GDB add an
3937 set_gdbarch_ps_regnum (gdbarch
, tdep
->ppc_ps_regnum
);
3940 set_gdbarch_return_value (gdbarch
, ppc64_sysv_abi_return_value
);
3942 set_gdbarch_return_value (gdbarch
, ppc_sysv_abi_return_value
);
3944 /* Set lr_frame_offset. */
3946 tdep
->lr_frame_offset
= 16;
3948 tdep
->lr_frame_offset
= 4;
3950 if (have_spe
|| have_dfp
|| have_vsx
)
3952 set_gdbarch_pseudo_register_read (gdbarch
, rs6000_pseudo_register_read
);
3953 set_gdbarch_pseudo_register_write (gdbarch
, rs6000_pseudo_register_write
);
3956 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
3958 /* Select instruction printer. */
3959 if (arch
== bfd_arch_rs6000
)
3960 set_gdbarch_print_insn (gdbarch
, print_insn_rs6000
);
3962 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_powerpc
);
3964 set_gdbarch_num_regs (gdbarch
, PPC_NUM_REGS
);
3967 num_pseudoregs
+= 32;
3969 num_pseudoregs
+= 16;
3971 /* Include both VSX and Extended FP registers. */
3972 num_pseudoregs
+= 96;
3974 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudoregs
);
3976 set_gdbarch_ptr_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
3977 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
3978 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
3979 set_gdbarch_long_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
3980 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
3981 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
3982 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
3983 set_gdbarch_long_double_bit (gdbarch
, 16 * TARGET_CHAR_BIT
);
3984 set_gdbarch_char_signed (gdbarch
, 0);
3986 set_gdbarch_frame_align (gdbarch
, rs6000_frame_align
);
3989 set_gdbarch_frame_red_zone_size (gdbarch
, 288);
3991 set_gdbarch_convert_register_p (gdbarch
, rs6000_convert_register_p
);
3992 set_gdbarch_register_to_value (gdbarch
, rs6000_register_to_value
);
3993 set_gdbarch_value_to_register (gdbarch
, rs6000_value_to_register
);
3995 set_gdbarch_stab_reg_to_regnum (gdbarch
, rs6000_stab_reg_to_regnum
);
3996 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, rs6000_dwarf2_reg_to_regnum
);
3999 set_gdbarch_push_dummy_call (gdbarch
, ppc_sysv_abi_push_dummy_call
);
4000 else if (wordsize
== 8)
4001 set_gdbarch_push_dummy_call (gdbarch
, ppc64_sysv_abi_push_dummy_call
);
4003 set_gdbarch_skip_prologue (gdbarch
, rs6000_skip_prologue
);
4004 set_gdbarch_in_function_epilogue_p (gdbarch
, rs6000_in_function_epilogue_p
);
4005 set_gdbarch_skip_main_prologue (gdbarch
, rs6000_skip_main_prologue
);
4007 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
4008 set_gdbarch_breakpoint_from_pc (gdbarch
, rs6000_breakpoint_from_pc
);
4010 /* The value of symbols of type N_SO and N_FUN maybe null when
4012 set_gdbarch_sofun_address_maybe_missing (gdbarch
, 1);
4014 /* Handles single stepping of atomic sequences. */
4015 set_gdbarch_software_single_step (gdbarch
, ppc_deal_with_atomic_sequence
);
4017 /* Not sure on this. FIXMEmgo */
4018 set_gdbarch_frame_args_skip (gdbarch
, 8);
4020 /* Helpers for function argument information. */
4021 set_gdbarch_fetch_pointer_argument (gdbarch
, rs6000_fetch_pointer_argument
);
4024 set_gdbarch_in_solib_return_trampoline
4025 (gdbarch
, rs6000_in_solib_return_trampoline
);
4026 set_gdbarch_skip_trampoline_code (gdbarch
, rs6000_skip_trampoline_code
);
4028 /* Hook in the DWARF CFI frame unwinder. */
4029 dwarf2_append_unwinders (gdbarch
);
4030 dwarf2_frame_set_adjust_regnum (gdbarch
, rs6000_adjust_frame_regnum
);
4032 /* Frame handling. */
4033 dwarf2_frame_set_init_reg (gdbarch
, ppc_dwarf2_frame_init_reg
);
4035 /* Setup displaced stepping. */
4036 set_gdbarch_displaced_step_copy_insn (gdbarch
,
4037 simple_displaced_step_copy_insn
);
4038 set_gdbarch_displaced_step_hw_singlestep (gdbarch
,
4039 ppc_displaced_step_hw_singlestep
);
4040 set_gdbarch_displaced_step_fixup (gdbarch
, ppc_displaced_step_fixup
);
4041 set_gdbarch_displaced_step_free_closure (gdbarch
,
4042 simple_displaced_step_free_closure
);
4043 set_gdbarch_displaced_step_location (gdbarch
,
4044 displaced_step_at_entry_point
);
4046 set_gdbarch_max_insn_length (gdbarch
, PPC_INSN_SIZE
);
4048 /* Hook in ABI-specific overrides, if they have been registered. */
4049 info
.target_desc
= tdesc
;
4050 info
.tdep_info
= (void *) tdesc_data
;
4051 gdbarch_init_osabi (info
, gdbarch
);
4055 case GDB_OSABI_LINUX
:
4056 case GDB_OSABI_NETBSD_AOUT
:
4057 case GDB_OSABI_NETBSD_ELF
:
4058 case GDB_OSABI_UNKNOWN
:
4059 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
4060 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
4061 set_gdbarch_dummy_id (gdbarch
, rs6000_dummy_id
);
4062 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
4065 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
4067 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
4068 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
4069 set_gdbarch_dummy_id (gdbarch
, rs6000_dummy_id
);
4070 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
4073 set_tdesc_pseudo_register_type (gdbarch
, rs6000_pseudo_register_type
);
4074 set_tdesc_pseudo_register_reggroup_p (gdbarch
,
4075 rs6000_pseudo_register_reggroup_p
);
4076 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
4078 /* Override the normal target description method to make the SPE upper
4079 halves anonymous. */
4080 set_gdbarch_register_name (gdbarch
, rs6000_register_name
);
4082 /* Choose register numbers for all supported pseudo-registers. */
4083 tdep
->ppc_ev0_regnum
= -1;
4084 tdep
->ppc_dl0_regnum
= -1;
4085 tdep
->ppc_vsr0_regnum
= -1;
4086 tdep
->ppc_efpr0_regnum
= -1;
4088 cur_reg
= gdbarch_num_regs (gdbarch
);
4092 tdep
->ppc_ev0_regnum
= cur_reg
;
4097 tdep
->ppc_dl0_regnum
= cur_reg
;
4102 tdep
->ppc_vsr0_regnum
= cur_reg
;
4104 tdep
->ppc_efpr0_regnum
= cur_reg
;
4108 gdb_assert (gdbarch_num_regs (gdbarch
)
4109 + gdbarch_num_pseudo_regs (gdbarch
) == cur_reg
);
4115 rs6000_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
4117 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4122 /* FIXME: Dump gdbarch_tdep. */
4125 /* PowerPC-specific commands. */
4128 set_powerpc_command (char *args
, int from_tty
)
4130 printf_unfiltered (_("\
4131 \"set powerpc\" must be followed by an appropriate subcommand.\n"));
4132 help_list (setpowerpccmdlist
, "set powerpc ", all_commands
, gdb_stdout
);
4136 show_powerpc_command (char *args
, int from_tty
)
4138 cmd_show_list (showpowerpccmdlist
, from_tty
, "");
4142 powerpc_set_soft_float (char *args
, int from_tty
,
4143 struct cmd_list_element
*c
)
4145 struct gdbarch_info info
;
4147 /* Update the architecture. */
4148 gdbarch_info_init (&info
);
4149 if (!gdbarch_update_p (info
))
4150 internal_error (__FILE__
, __LINE__
, "could not update architecture");
4154 powerpc_set_vector_abi (char *args
, int from_tty
,
4155 struct cmd_list_element
*c
)
4157 struct gdbarch_info info
;
4158 enum powerpc_vector_abi vector_abi
;
4160 for (vector_abi
= POWERPC_VEC_AUTO
;
4161 vector_abi
!= POWERPC_VEC_LAST
;
4163 if (strcmp (powerpc_vector_abi_string
,
4164 powerpc_vector_strings
[vector_abi
]) == 0)
4166 powerpc_vector_abi_global
= vector_abi
;
4170 if (vector_abi
== POWERPC_VEC_LAST
)
4171 internal_error (__FILE__
, __LINE__
, _("Invalid vector ABI accepted: %s."),
4172 powerpc_vector_abi_string
);
4174 /* Update the architecture. */
4175 gdbarch_info_init (&info
);
4176 if (!gdbarch_update_p (info
))
4177 internal_error (__FILE__
, __LINE__
, "could not update architecture");
4180 /* Initialization code. */
4182 extern initialize_file_ftype _initialize_rs6000_tdep
; /* -Wmissing-prototypes */
4185 _initialize_rs6000_tdep (void)
4187 gdbarch_register (bfd_arch_rs6000
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
4188 gdbarch_register (bfd_arch_powerpc
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
4190 /* Initialize the standard target descriptions. */
4191 initialize_tdesc_powerpc_32 ();
4192 initialize_tdesc_powerpc_altivec32 ();
4193 initialize_tdesc_powerpc_vsx32 ();
4194 initialize_tdesc_powerpc_403 ();
4195 initialize_tdesc_powerpc_403gc ();
4196 initialize_tdesc_powerpc_405 ();
4197 initialize_tdesc_powerpc_505 ();
4198 initialize_tdesc_powerpc_601 ();
4199 initialize_tdesc_powerpc_602 ();
4200 initialize_tdesc_powerpc_603 ();
4201 initialize_tdesc_powerpc_604 ();
4202 initialize_tdesc_powerpc_64 ();
4203 initialize_tdesc_powerpc_altivec64 ();
4204 initialize_tdesc_powerpc_vsx64 ();
4205 initialize_tdesc_powerpc_7400 ();
4206 initialize_tdesc_powerpc_750 ();
4207 initialize_tdesc_powerpc_860 ();
4208 initialize_tdesc_powerpc_e500 ();
4209 initialize_tdesc_rs6000 ();
4211 /* Add root prefix command for all "set powerpc"/"show powerpc"
4213 add_prefix_cmd ("powerpc", no_class
, set_powerpc_command
,
4214 _("Various PowerPC-specific commands."),
4215 &setpowerpccmdlist
, "set powerpc ", 0, &setlist
);
4217 add_prefix_cmd ("powerpc", no_class
, show_powerpc_command
,
4218 _("Various PowerPC-specific commands."),
4219 &showpowerpccmdlist
, "show powerpc ", 0, &showlist
);
4221 /* Add a command to allow the user to force the ABI. */
4222 add_setshow_auto_boolean_cmd ("soft-float", class_support
,
4223 &powerpc_soft_float_global
,
4224 _("Set whether to use a soft-float ABI."),
4225 _("Show whether to use a soft-float ABI."),
4227 powerpc_set_soft_float
, NULL
,
4228 &setpowerpccmdlist
, &showpowerpccmdlist
);
4230 add_setshow_enum_cmd ("vector-abi", class_support
, powerpc_vector_strings
,
4231 &powerpc_vector_abi_string
,
4232 _("Set the vector ABI."),
4233 _("Show the vector ABI."),
4234 NULL
, powerpc_set_vector_abi
, NULL
,
4235 &setpowerpccmdlist
, &showpowerpccmdlist
);