1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 Boston, MA 02110-1301, USA. */
32 #include "arch-utils.h"
37 #include "parser-defs.h"
40 #include "sim-regno.h"
41 #include "gdb/sim-ppc.h"
42 #include "reggroups.h"
43 #include "dwarf2-frame.h"
45 #include "libbfd.h" /* for bfd_default_set_arch_mach */
46 #include "coff/internal.h" /* for libcoff.h */
47 #include "libcoff.h" /* for xcoff_data */
48 #include "coff/xcoff.h"
53 #include "solib-svr4.h"
56 #include "gdb_assert.h"
59 #include "trad-frame.h"
60 #include "frame-unwind.h"
61 #include "frame-base.h"
63 #include "rs6000-tdep.h"
65 /* If the kernel has to deliver a signal, it pushes a sigcontext
66 structure on the stack and then calls the signal handler, passing
67 the address of the sigcontext in an argument register. Usually
68 the signal handler doesn't save this register, so we have to
69 access the sigcontext structure via an offset from the signal handler
71 The following constants were determined by experimentation on AIX 3.2. */
72 #define SIG_FRAME_PC_OFFSET 96
73 #define SIG_FRAME_LR_OFFSET 108
74 #define SIG_FRAME_FP_OFFSET 284
76 /* To be used by skip_prologue. */
78 struct rs6000_framedata
80 int offset
; /* total size of frame --- the distance
81 by which we decrement sp to allocate
83 int saved_gpr
; /* smallest # of saved gpr */
84 int saved_fpr
; /* smallest # of saved fpr */
85 int saved_vr
; /* smallest # of saved vr */
86 int saved_ev
; /* smallest # of saved ev */
87 int alloca_reg
; /* alloca register number (frame ptr) */
88 char frameless
; /* true if frameless functions. */
89 char nosavedpc
; /* true if pc not saved. */
90 int gpr_offset
; /* offset of saved gprs from prev sp */
91 int fpr_offset
; /* offset of saved fprs from prev sp */
92 int vr_offset
; /* offset of saved vrs from prev sp */
93 int ev_offset
; /* offset of saved evs from prev sp */
94 int lr_offset
; /* offset of saved lr */
95 int cr_offset
; /* offset of saved cr */
96 int vrsave_offset
; /* offset of saved vrsave register */
99 /* Description of a single register. */
103 char *name
; /* name of register */
104 unsigned char sz32
; /* size on 32-bit arch, 0 if nonexistent */
105 unsigned char sz64
; /* size on 64-bit arch, 0 if nonexistent */
106 unsigned char fpr
; /* whether register is floating-point */
107 unsigned char pseudo
; /* whether register is pseudo */
108 int spr_num
; /* PowerPC SPR number, or -1 if not an SPR.
109 This is an ISA SPR number, not a GDB
113 /* Hook for determining the TOC address when calling functions in the
114 inferior under AIX. The initialization code in rs6000-nat.c sets
115 this hook to point to find_toc_address. */
117 CORE_ADDR (*rs6000_find_toc_address_hook
) (CORE_ADDR
) = NULL
;
119 /* Static function prototypes */
121 static CORE_ADDR
branch_dest (int opcode
, int instr
, CORE_ADDR pc
,
123 static CORE_ADDR
skip_prologue (CORE_ADDR
, CORE_ADDR
,
124 struct rs6000_framedata
*);
126 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
128 altivec_register_p (int regno
)
130 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
131 if (tdep
->ppc_vr0_regnum
< 0 || tdep
->ppc_vrsave_regnum
< 0)
134 return (regno
>= tdep
->ppc_vr0_regnum
&& regno
<= tdep
->ppc_vrsave_regnum
);
138 /* Return true if REGNO is an SPE register, false otherwise. */
140 spe_register_p (int regno
)
142 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
144 /* Is it a reference to EV0 -- EV31, and do we have those? */
145 if (tdep
->ppc_ev0_regnum
>= 0
146 && tdep
->ppc_ev31_regnum
>= 0
147 && tdep
->ppc_ev0_regnum
<= regno
&& regno
<= tdep
->ppc_ev31_regnum
)
150 /* Is it a reference to one of the raw upper GPR halves? */
151 if (tdep
->ppc_ev0_upper_regnum
>= 0
152 && tdep
->ppc_ev0_upper_regnum
<= regno
153 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
156 /* Is it a reference to the 64-bit accumulator, and do we have that? */
157 if (tdep
->ppc_acc_regnum
>= 0
158 && tdep
->ppc_acc_regnum
== regno
)
161 /* Is it a reference to the SPE floating-point status and control register,
162 and do we have that? */
163 if (tdep
->ppc_spefscr_regnum
>= 0
164 && tdep
->ppc_spefscr_regnum
== regno
)
171 /* Return non-zero if the architecture described by GDBARCH has
172 floating-point registers (f0 --- f31 and fpscr). */
174 ppc_floating_point_unit_p (struct gdbarch
*gdbarch
)
176 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
178 return (tdep
->ppc_fp0_regnum
>= 0
179 && tdep
->ppc_fpscr_regnum
>= 0);
183 /* Check that TABLE[GDB_REGNO] is not already initialized, and then
186 This is a helper function for init_sim_regno_table, constructing
187 the table mapping GDB register numbers to sim register numbers; we
188 initialize every element in that table to -1 before we start
191 set_sim_regno (int *table
, int gdb_regno
, int sim_regno
)
193 /* Make sure we don't try to assign any given GDB register a sim
194 register number more than once. */
195 gdb_assert (table
[gdb_regno
] == -1);
196 table
[gdb_regno
] = sim_regno
;
200 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
201 numbers to simulator register numbers, based on the values placed
202 in the ARCH->tdep->ppc_foo_regnum members. */
204 init_sim_regno_table (struct gdbarch
*arch
)
206 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
207 int total_regs
= gdbarch_num_regs (arch
) + gdbarch_num_pseudo_regs (arch
);
208 const struct reg
*regs
= tdep
->regs
;
209 int *sim_regno
= GDBARCH_OBSTACK_CALLOC (arch
, total_regs
, int);
212 /* Presume that all registers not explicitly mentioned below are
213 unavailable from the sim. */
214 for (i
= 0; i
< total_regs
; i
++)
217 /* General-purpose registers. */
218 for (i
= 0; i
< ppc_num_gprs
; i
++)
219 set_sim_regno (sim_regno
, tdep
->ppc_gp0_regnum
+ i
, sim_ppc_r0_regnum
+ i
);
221 /* Floating-point registers. */
222 if (tdep
->ppc_fp0_regnum
>= 0)
223 for (i
= 0; i
< ppc_num_fprs
; i
++)
224 set_sim_regno (sim_regno
,
225 tdep
->ppc_fp0_regnum
+ i
,
226 sim_ppc_f0_regnum
+ i
);
227 if (tdep
->ppc_fpscr_regnum
>= 0)
228 set_sim_regno (sim_regno
, tdep
->ppc_fpscr_regnum
, sim_ppc_fpscr_regnum
);
230 set_sim_regno (sim_regno
, gdbarch_pc_regnum (arch
), sim_ppc_pc_regnum
);
231 set_sim_regno (sim_regno
, tdep
->ppc_ps_regnum
, sim_ppc_ps_regnum
);
232 set_sim_regno (sim_regno
, tdep
->ppc_cr_regnum
, sim_ppc_cr_regnum
);
234 /* Segment registers. */
235 if (tdep
->ppc_sr0_regnum
>= 0)
236 for (i
= 0; i
< ppc_num_srs
; i
++)
237 set_sim_regno (sim_regno
,
238 tdep
->ppc_sr0_regnum
+ i
,
239 sim_ppc_sr0_regnum
+ i
);
241 /* Altivec registers. */
242 if (tdep
->ppc_vr0_regnum
>= 0)
244 for (i
= 0; i
< ppc_num_vrs
; i
++)
245 set_sim_regno (sim_regno
,
246 tdep
->ppc_vr0_regnum
+ i
,
247 sim_ppc_vr0_regnum
+ i
);
249 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
250 we can treat this more like the other cases. */
251 set_sim_regno (sim_regno
,
252 tdep
->ppc_vr0_regnum
+ ppc_num_vrs
,
253 sim_ppc_vscr_regnum
);
255 /* vsave is a special-purpose register, so the code below handles it. */
257 /* SPE APU (E500) registers. */
258 if (tdep
->ppc_ev0_regnum
>= 0)
259 for (i
= 0; i
< ppc_num_gprs
; i
++)
260 set_sim_regno (sim_regno
,
261 tdep
->ppc_ev0_regnum
+ i
,
262 sim_ppc_ev0_regnum
+ i
);
263 if (tdep
->ppc_ev0_upper_regnum
>= 0)
264 for (i
= 0; i
< ppc_num_gprs
; i
++)
265 set_sim_regno (sim_regno
,
266 tdep
->ppc_ev0_upper_regnum
+ i
,
267 sim_ppc_rh0_regnum
+ i
);
268 if (tdep
->ppc_acc_regnum
>= 0)
269 set_sim_regno (sim_regno
, tdep
->ppc_acc_regnum
, sim_ppc_acc_regnum
);
270 /* spefscr is a special-purpose register, so the code below handles it. */
272 /* Now handle all special-purpose registers. Verify that they
273 haven't mistakenly been assigned numbers by any of the above
275 for (i
= 0; i
< total_regs
; i
++)
276 if (regs
[i
].spr_num
>= 0)
277 set_sim_regno (sim_regno
, i
, regs
[i
].spr_num
+ sim_ppc_spr0_regnum
);
279 /* Drop the initialized array into place. */
280 tdep
->sim_regno
= sim_regno
;
284 /* Given a GDB register number REG, return the corresponding SIM
287 rs6000_register_sim_regno (int reg
)
289 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
293 && reg
<= gdbarch_num_regs (current_gdbarch
)
294 + gdbarch_num_pseudo_regs (current_gdbarch
));
295 sim_regno
= tdep
->sim_regno
[reg
];
300 return LEGACY_SIM_REGNO_IGNORE
;
305 /* Register set support functions. */
308 ppc_supply_reg (struct regcache
*regcache
, int regnum
,
309 const gdb_byte
*regs
, size_t offset
)
311 if (regnum
!= -1 && offset
!= -1)
312 regcache_raw_supply (regcache
, regnum
, regs
+ offset
);
316 ppc_collect_reg (const struct regcache
*regcache
, int regnum
,
317 gdb_byte
*regs
, size_t offset
)
319 if (regnum
!= -1 && offset
!= -1)
320 regcache_raw_collect (regcache
, regnum
, regs
+ offset
);
323 /* Supply register REGNUM in the general-purpose register set REGSET
324 from the buffer specified by GREGS and LEN to register cache
325 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
328 ppc_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
329 int regnum
, const void *gregs
, size_t len
)
331 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
332 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
333 const struct ppc_reg_offsets
*offsets
= regset
->descr
;
337 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
338 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
341 if (regnum
== -1 || regnum
== i
)
342 ppc_supply_reg (regcache
, i
, gregs
, offset
);
345 if (regnum
== -1 || regnum
== PC_REGNUM
)
346 ppc_supply_reg (regcache
, PC_REGNUM
, gregs
, offsets
->pc_offset
);
347 if (regnum
== -1 || regnum
== tdep
->ppc_ps_regnum
)
348 ppc_supply_reg (regcache
, tdep
->ppc_ps_regnum
,
349 gregs
, offsets
->ps_offset
);
350 if (regnum
== -1 || regnum
== tdep
->ppc_cr_regnum
)
351 ppc_supply_reg (regcache
, tdep
->ppc_cr_regnum
,
352 gregs
, offsets
->cr_offset
);
353 if (regnum
== -1 || regnum
== tdep
->ppc_lr_regnum
)
354 ppc_supply_reg (regcache
, tdep
->ppc_lr_regnum
,
355 gregs
, offsets
->lr_offset
);
356 if (regnum
== -1 || regnum
== tdep
->ppc_ctr_regnum
)
357 ppc_supply_reg (regcache
, tdep
->ppc_ctr_regnum
,
358 gregs
, offsets
->ctr_offset
);
359 if (regnum
== -1 || regnum
== tdep
->ppc_xer_regnum
)
360 ppc_supply_reg (regcache
, tdep
->ppc_xer_regnum
,
361 gregs
, offsets
->cr_offset
);
362 if (regnum
== -1 || regnum
== tdep
->ppc_mq_regnum
)
363 ppc_supply_reg (regcache
, tdep
->ppc_mq_regnum
, gregs
, offsets
->mq_offset
);
366 /* Supply register REGNUM in the floating-point register set REGSET
367 from the buffer specified by FPREGS and LEN to register cache
368 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
371 ppc_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
372 int regnum
, const void *fpregs
, size_t len
)
374 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
375 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
376 const struct ppc_reg_offsets
*offsets
= regset
->descr
;
380 gdb_assert (ppc_floating_point_unit_p (gdbarch
));
382 offset
= offsets
->f0_offset
;
383 for (i
= tdep
->ppc_fp0_regnum
;
384 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
387 if (regnum
== -1 || regnum
== i
)
388 ppc_supply_reg (regcache
, i
, fpregs
, offset
);
391 if (regnum
== -1 || regnum
== tdep
->ppc_fpscr_regnum
)
392 ppc_supply_reg (regcache
, tdep
->ppc_fpscr_regnum
,
393 fpregs
, offsets
->fpscr_offset
);
396 /* Collect register REGNUM in the general-purpose register set
397 REGSET. from register cache REGCACHE into the buffer specified by
398 GREGS and LEN. If REGNUM is -1, do this for all registers in
402 ppc_collect_gregset (const struct regset
*regset
,
403 const struct regcache
*regcache
,
404 int regnum
, void *gregs
, size_t len
)
406 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
407 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
408 const struct ppc_reg_offsets
*offsets
= regset
->descr
;
412 offset
= offsets
->r0_offset
;
413 for (i
= tdep
->ppc_gp0_regnum
;
414 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
417 if (regnum
== -1 || regnum
== i
)
418 ppc_collect_reg (regcache
, i
, gregs
, offset
);
421 if (regnum
== -1 || regnum
== PC_REGNUM
)
422 ppc_collect_reg (regcache
, PC_REGNUM
, gregs
, offsets
->pc_offset
);
423 if (regnum
== -1 || regnum
== tdep
->ppc_ps_regnum
)
424 ppc_collect_reg (regcache
, tdep
->ppc_ps_regnum
,
425 gregs
, offsets
->ps_offset
);
426 if (regnum
== -1 || regnum
== tdep
->ppc_cr_regnum
)
427 ppc_collect_reg (regcache
, tdep
->ppc_cr_regnum
,
428 gregs
, offsets
->cr_offset
);
429 if (regnum
== -1 || regnum
== tdep
->ppc_lr_regnum
)
430 ppc_collect_reg (regcache
, tdep
->ppc_lr_regnum
,
431 gregs
, offsets
->lr_offset
);
432 if (regnum
== -1 || regnum
== tdep
->ppc_ctr_regnum
)
433 ppc_collect_reg (regcache
, tdep
->ppc_ctr_regnum
,
434 gregs
, offsets
->ctr_offset
);
435 if (regnum
== -1 || regnum
== tdep
->ppc_xer_regnum
)
436 ppc_collect_reg (regcache
, tdep
->ppc_xer_regnum
,
437 gregs
, offsets
->xer_offset
);
438 if (regnum
== -1 || regnum
== tdep
->ppc_mq_regnum
)
439 ppc_collect_reg (regcache
, tdep
->ppc_mq_regnum
,
440 gregs
, offsets
->mq_offset
);
443 /* Collect register REGNUM in the floating-point register set
444 REGSET. from register cache REGCACHE into the buffer specified by
445 FPREGS and LEN. If REGNUM is -1, do this for all registers in
449 ppc_collect_fpregset (const struct regset
*regset
,
450 const struct regcache
*regcache
,
451 int regnum
, void *fpregs
, size_t len
)
453 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
454 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
455 const struct ppc_reg_offsets
*offsets
= regset
->descr
;
459 gdb_assert (ppc_floating_point_unit_p (gdbarch
));
461 offset
= offsets
->f0_offset
;
462 for (i
= tdep
->ppc_fp0_regnum
;
463 i
<= tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
466 if (regnum
== -1 || regnum
== i
)
467 ppc_collect_reg (regcache
, i
, fpregs
, offset
);
470 if (regnum
== -1 || regnum
== tdep
->ppc_fpscr_regnum
)
471 ppc_collect_reg (regcache
, tdep
->ppc_fpscr_regnum
,
472 fpregs
, offsets
->fpscr_offset
);
476 /* Read a LEN-byte address from debugged memory address MEMADDR. */
479 read_memory_addr (CORE_ADDR memaddr
, int len
)
481 return read_memory_unsigned_integer (memaddr
, len
);
485 rs6000_skip_prologue (CORE_ADDR pc
)
487 struct rs6000_framedata frame
;
488 CORE_ADDR limit_pc
, func_addr
;
490 /* See if we can determine the end of the prologue via the symbol table.
491 If so, then return either PC, or the PC after the prologue, whichever
493 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
495 CORE_ADDR post_prologue_pc
= skip_prologue_using_sal (func_addr
);
496 if (post_prologue_pc
!= 0)
497 return max (pc
, post_prologue_pc
);
500 /* Can't determine prologue from the symbol table, need to examine
503 /* Find an upper limit on the function prologue using the debug
504 information. If the debug information could not be used to provide
505 that bound, then use an arbitrary large number as the upper bound. */
506 limit_pc
= skip_prologue_using_sal (pc
);
508 limit_pc
= pc
+ 100; /* Magic. */
510 pc
= skip_prologue (pc
, limit_pc
, &frame
);
515 insn_changes_sp_or_jumps (unsigned long insn
)
517 int opcode
= (insn
>> 26) & 0x03f;
518 int sd
= (insn
>> 21) & 0x01f;
519 int a
= (insn
>> 16) & 0x01f;
520 int subcode
= (insn
>> 1) & 0x3ff;
522 /* Changes the stack pointer. */
524 /* NOTE: There are many ways to change the value of a given register.
525 The ways below are those used when the register is R1, the SP,
526 in a funtion's epilogue. */
528 if (opcode
== 31 && subcode
== 444 && a
== 1)
529 return 1; /* mr R1,Rn */
530 if (opcode
== 14 && sd
== 1)
531 return 1; /* addi R1,Rn,simm */
532 if (opcode
== 58 && sd
== 1)
533 return 1; /* ld R1,ds(Rn) */
535 /* Transfers control. */
541 if (opcode
== 19 && subcode
== 16)
543 if (opcode
== 19 && subcode
== 528)
544 return 1; /* bcctr */
549 /* Return true if we are in the function's epilogue, i.e. after the
550 instruction that destroyed the function's stack frame.
552 1) scan forward from the point of execution:
553 a) If you find an instruction that modifies the stack pointer
554 or transfers control (except a return), execution is not in
556 b) Stop scanning if you find a return instruction or reach the
557 end of the function or reach the hard limit for the size of
559 2) scan backward from the point of execution:
560 a) If you find an instruction that modifies the stack pointer,
561 execution *is* in an epilogue, return.
562 b) Stop scanning if you reach an instruction that transfers
563 control or the beginning of the function or reach the hard
564 limit for the size of an epilogue. */
567 rs6000_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
569 bfd_byte insn_buf
[PPC_INSN_SIZE
];
570 CORE_ADDR scan_pc
, func_start
, func_end
, epilogue_start
, epilogue_end
;
572 struct frame_info
*curfrm
;
574 /* Find the search limits based on function boundaries and hard limit. */
576 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
579 epilogue_start
= pc
- PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
580 if (epilogue_start
< func_start
) epilogue_start
= func_start
;
582 epilogue_end
= pc
+ PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
583 if (epilogue_end
> func_end
) epilogue_end
= func_end
;
585 curfrm
= get_current_frame ();
587 /* Scan forward until next 'blr'. */
589 for (scan_pc
= pc
; scan_pc
< epilogue_end
; scan_pc
+= PPC_INSN_SIZE
)
591 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
593 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
);
594 if (insn
== 0x4e800020)
596 if (insn_changes_sp_or_jumps (insn
))
600 /* Scan backward until adjustment to stack pointer (R1). */
602 for (scan_pc
= pc
- PPC_INSN_SIZE
;
603 scan_pc
>= epilogue_start
;
604 scan_pc
-= PPC_INSN_SIZE
)
606 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
608 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
);
609 if (insn_changes_sp_or_jumps (insn
))
616 /* Get the ith function argument for the current function. */
618 rs6000_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
621 return get_frame_register_unsigned (frame
, 3 + argi
);
624 /* Calculate the destination of a branch/jump. Return -1 if not a branch. */
627 branch_dest (int opcode
, int instr
, CORE_ADDR pc
, CORE_ADDR safety
)
634 absolute
= (int) ((instr
>> 1) & 1);
639 immediate
= ((instr
& ~3) << 6) >> 6; /* br unconditional */
643 dest
= pc
+ immediate
;
647 immediate
= ((instr
& ~3) << 16) >> 16; /* br conditional */
651 dest
= pc
+ immediate
;
655 ext_op
= (instr
>> 1) & 0x3ff;
657 if (ext_op
== 16) /* br conditional register */
659 dest
= read_register (gdbarch_tdep (current_gdbarch
)->ppc_lr_regnum
) & ~3;
661 /* If we are about to return from a signal handler, dest is
662 something like 0x3c90. The current frame is a signal handler
663 caller frame, upon completion of the sigreturn system call
664 execution will return to the saved PC in the frame. */
665 if (dest
< gdbarch_tdep (current_gdbarch
)->text_segment_base
)
667 struct frame_info
*fi
;
669 fi
= get_current_frame ();
671 dest
= read_memory_addr (get_frame_base (fi
) + SIG_FRAME_PC_OFFSET
,
672 gdbarch_tdep (current_gdbarch
)->wordsize
);
676 else if (ext_op
== 528) /* br cond to count reg */
678 dest
= read_register (gdbarch_tdep (current_gdbarch
)->ppc_ctr_regnum
) & ~3;
680 /* If we are about to execute a system call, dest is something
681 like 0x22fc or 0x3b00. Upon completion the system call
682 will return to the address in the link register. */
683 if (dest
< gdbarch_tdep (current_gdbarch
)->text_segment_base
)
684 dest
= read_register (gdbarch_tdep (current_gdbarch
)->ppc_lr_regnum
) & ~3;
693 return (dest
< gdbarch_tdep (current_gdbarch
)->text_segment_base
) ? safety
: dest
;
697 /* Sequence of bytes for breakpoint instruction. */
699 const static unsigned char *
700 rs6000_breakpoint_from_pc (CORE_ADDR
*bp_addr
, int *bp_size
)
702 static unsigned char big_breakpoint
[] = { 0x7d, 0x82, 0x10, 0x08 };
703 static unsigned char little_breakpoint
[] = { 0x08, 0x10, 0x82, 0x7d };
705 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
706 return big_breakpoint
;
708 return little_breakpoint
;
712 /* Instruction masks used during single-stepping of atomic sequences. */
713 #define LWARX_MASK 0xfc0007fe
714 #define LWARX_INSTRUCTION 0x7c000028
715 #define LDARX_INSTRUCTION 0x7c0000A8
716 #define STWCX_MASK 0xfc0007ff
717 #define STWCX_INSTRUCTION 0x7c00012d
718 #define STDCX_INSTRUCTION 0x7c0001ad
719 #define BC_MASK 0xfc000000
720 #define BC_INSTRUCTION 0x40000000
722 /* Checks for an atomic sequence of instructions beginning with a LWARX/LDARX
723 instruction and ending with a STWCX/STDCX instruction. If such a sequence
724 is found, attempt to step through it. A breakpoint is placed at the end of
728 deal_with_atomic_sequence (struct regcache
*regcache
)
730 CORE_ADDR pc
= read_pc ();
731 CORE_ADDR breaks
[2] = {-1, -1};
733 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
734 CORE_ADDR closing_insn
; /* Instruction that closes the atomic sequence. */
735 int insn
= read_memory_integer (loc
, PPC_INSN_SIZE
);
738 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
739 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
740 int opcode
; /* Branch instruction's OPcode. */
741 int bc_insn_count
= 0; /* Conditional branch instruction count. */
743 /* Assume all atomic sequences start with a lwarx/ldarx instruction. */
744 if ((insn
& LWARX_MASK
) != LWARX_INSTRUCTION
745 && (insn
& LWARX_MASK
) != LDARX_INSTRUCTION
)
748 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
750 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
752 loc
+= PPC_INSN_SIZE
;
753 insn
= read_memory_integer (loc
, PPC_INSN_SIZE
);
755 /* Assume that there is at most one conditional branch in the atomic
756 sequence. If a conditional branch is found, put a breakpoint in
757 its destination address. */
758 if ((insn
& BC_MASK
) == BC_INSTRUCTION
)
760 if (bc_insn_count
>= 1)
761 return 0; /* More than one conditional branch found, fallback
762 to the standard single-step code. */
765 branch_bp
= branch_dest (opcode
, insn
, pc
, breaks
[0]);
769 breaks
[1] = branch_bp
;
775 if ((insn
& STWCX_MASK
) == STWCX_INSTRUCTION
776 || (insn
& STWCX_MASK
) == STDCX_INSTRUCTION
)
780 /* Assume that the atomic sequence ends with a stwcx/stdcx instruction. */
781 if ((insn
& STWCX_MASK
) != STWCX_INSTRUCTION
782 && (insn
& STWCX_MASK
) != STDCX_INSTRUCTION
)
786 loc
+= PPC_INSN_SIZE
;
787 insn
= read_memory_integer (loc
, PPC_INSN_SIZE
);
789 /* Insert a breakpoint right after the end of the atomic sequence. */
792 /* Check for duplicated breakpoints. Check also for a breakpoint
793 placed (branch instruction's destination) at the stwcx/stdcx
794 instruction, this resets the reservation and take us back to the
795 lwarx/ldarx instruction at the beginning of the atomic sequence. */
796 if (last_breakpoint
&& ((breaks
[1] == breaks
[0])
797 || (breaks
[1] == closing_insn
)))
800 /* Effectively inserts the breakpoints. */
801 for (index
= 0; index
<= last_breakpoint
; index
++)
802 insert_single_step_breakpoint (breaks
[index
]);
807 /* AIX does not support PT_STEP. Simulate it. */
810 rs6000_software_single_step (struct regcache
*regcache
)
814 const gdb_byte
*breakp
= rs6000_breakpoint_from_pc (&dummy
, &breakp_sz
);
822 insn
= read_memory_integer (loc
, 4);
824 if (deal_with_atomic_sequence (regcache
))
827 breaks
[0] = loc
+ breakp_sz
;
829 breaks
[1] = branch_dest (opcode
, insn
, loc
, breaks
[0]);
831 /* Don't put two breakpoints on the same address. */
832 if (breaks
[1] == breaks
[0])
835 for (ii
= 0; ii
< 2; ++ii
)
837 /* ignore invalid breakpoint. */
838 if (breaks
[ii
] == -1)
840 insert_single_step_breakpoint (breaks
[ii
]);
843 errno
= 0; /* FIXME, don't ignore errors! */
844 /* What errors? {read,write}_memory call error(). */
849 /* return pc value after skipping a function prologue and also return
850 information about a function frame.
852 in struct rs6000_framedata fdata:
853 - frameless is TRUE, if function does not have a frame.
854 - nosavedpc is TRUE, if function does not save %pc value in its frame.
855 - offset is the initial size of this stack frame --- the amount by
856 which we decrement the sp to allocate the frame.
857 - saved_gpr is the number of the first saved gpr.
858 - saved_fpr is the number of the first saved fpr.
859 - saved_vr is the number of the first saved vr.
860 - saved_ev is the number of the first saved ev.
861 - alloca_reg is the number of the register used for alloca() handling.
863 - gpr_offset is the offset of the first saved gpr from the previous frame.
864 - fpr_offset is the offset of the first saved fpr from the previous frame.
865 - vr_offset is the offset of the first saved vr from the previous frame.
866 - ev_offset is the offset of the first saved ev from the previous frame.
867 - lr_offset is the offset of the saved lr
868 - cr_offset is the offset of the saved cr
869 - vrsave_offset is the offset of the saved vrsave register
872 #define SIGNED_SHORT(x) \
873 ((sizeof (short) == 2) \
874 ? ((int)(short)(x)) \
875 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
877 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
879 /* Limit the number of skipped non-prologue instructions, as the examining
880 of the prologue is expensive. */
881 static int max_skip_non_prologue_insns
= 10;
883 /* Return nonzero if the given instruction OP can be part of the prologue
884 of a function and saves a parameter on the stack. FRAMEP should be
885 set if one of the previous instructions in the function has set the
889 store_param_on_stack_p (unsigned long op
, int framep
, int *r0_contains_arg
)
891 /* Move parameters from argument registers to temporary register. */
892 if ((op
& 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
894 /* Rx must be scratch register r0. */
895 const int rx_regno
= (op
>> 16) & 31;
896 /* Ry: Only r3 - r10 are used for parameter passing. */
897 const int ry_regno
= GET_SRC_REG (op
);
899 if (rx_regno
== 0 && ry_regno
>= 3 && ry_regno
<= 10)
901 *r0_contains_arg
= 1;
908 /* Save a General Purpose Register on stack. */
910 if ((op
& 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
911 (op
& 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
913 /* Rx: Only r3 - r10 are used for parameter passing. */
914 const int rx_regno
= GET_SRC_REG (op
);
916 return (rx_regno
>= 3 && rx_regno
<= 10);
919 /* Save a General Purpose Register on stack via the Frame Pointer. */
922 ((op
& 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
923 (op
& 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
924 (op
& 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
926 /* Rx: Usually, only r3 - r10 are used for parameter passing.
927 However, the compiler sometimes uses r0 to hold an argument. */
928 const int rx_regno
= GET_SRC_REG (op
);
930 return ((rx_regno
>= 3 && rx_regno
<= 10)
931 || (rx_regno
== 0 && *r0_contains_arg
));
934 if ((op
& 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
936 /* Only f2 - f8 are used for parameter passing. */
937 const int src_regno
= GET_SRC_REG (op
);
939 return (src_regno
>= 2 && src_regno
<= 8);
942 if (framep
&& ((op
& 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
944 /* Only f2 - f8 are used for parameter passing. */
945 const int src_regno
= GET_SRC_REG (op
);
947 return (src_regno
>= 2 && src_regno
<= 8);
950 /* Not an insn that saves a parameter on stack. */
954 /* Assuming that INSN is a "bl" instruction located at PC, return
955 nonzero if the destination of the branch is a "blrl" instruction.
957 This sequence is sometimes found in certain function prologues.
958 It allows the function to load the LR register with a value that
959 they can use to access PIC data using PC-relative offsets. */
962 bl_to_blrl_insn_p (CORE_ADDR pc
, int insn
)
964 const int opcode
= 18;
965 const CORE_ADDR dest
= branch_dest (opcode
, insn
, pc
, -1);
969 return 0; /* Should never happen, but just return zero to be safe. */
971 dest_insn
= read_memory_integer (dest
, 4);
972 if ((dest_insn
& 0xfc00ffff) == 0x4c000021) /* blrl */
979 skip_prologue (CORE_ADDR pc
, CORE_ADDR lim_pc
, struct rs6000_framedata
*fdata
)
981 CORE_ADDR orig_pc
= pc
;
982 CORE_ADDR last_prologue_pc
= pc
;
983 CORE_ADDR li_found_pc
= 0;
987 long vr_saved_offset
= 0;
996 int minimal_toc_loaded
= 0;
997 int prev_insn_was_prologue_insn
= 1;
998 int num_skip_non_prologue_insns
= 0;
999 int r0_contains_arg
= 0;
1000 const struct bfd_arch_info
*arch_info
= gdbarch_bfd_arch_info (current_gdbarch
);
1001 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1003 memset (fdata
, 0, sizeof (struct rs6000_framedata
));
1004 fdata
->saved_gpr
= -1;
1005 fdata
->saved_fpr
= -1;
1006 fdata
->saved_vr
= -1;
1007 fdata
->saved_ev
= -1;
1008 fdata
->alloca_reg
= -1;
1009 fdata
->frameless
= 1;
1010 fdata
->nosavedpc
= 1;
1014 /* Sometimes it isn't clear if an instruction is a prologue
1015 instruction or not. When we encounter one of these ambiguous
1016 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
1017 Otherwise, we'll assume that it really is a prologue instruction. */
1018 if (prev_insn_was_prologue_insn
)
1019 last_prologue_pc
= pc
;
1021 /* Stop scanning if we've hit the limit. */
1025 prev_insn_was_prologue_insn
= 1;
1027 /* Fetch the instruction and convert it to an integer. */
1028 if (target_read_memory (pc
, buf
, 4))
1030 op
= extract_unsigned_integer (buf
, 4);
1032 if ((op
& 0xfc1fffff) == 0x7c0802a6)
1034 /* Since shared library / PIC code, which needs to get its
1035 address at runtime, can appear to save more than one link
1049 remember just the first one, but skip over additional
1052 lr_reg
= (op
& 0x03e00000);
1054 r0_contains_arg
= 0;
1057 else if ((op
& 0xfc1fffff) == 0x7c000026)
1059 cr_reg
= (op
& 0x03e00000);
1061 r0_contains_arg
= 0;
1065 else if ((op
& 0xfc1f0000) == 0xd8010000)
1066 { /* stfd Rx,NUM(r1) */
1067 reg
= GET_SRC_REG (op
);
1068 if (fdata
->saved_fpr
== -1 || fdata
->saved_fpr
> reg
)
1070 fdata
->saved_fpr
= reg
;
1071 fdata
->fpr_offset
= SIGNED_SHORT (op
) + offset
;
1076 else if (((op
& 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
1077 (((op
& 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1078 (op
& 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1079 (op
& 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
1082 reg
= GET_SRC_REG (op
);
1083 if (fdata
->saved_gpr
== -1 || fdata
->saved_gpr
> reg
)
1085 fdata
->saved_gpr
= reg
;
1086 if ((op
& 0xfc1f0003) == 0xf8010000)
1088 fdata
->gpr_offset
= SIGNED_SHORT (op
) + offset
;
1093 else if ((op
& 0xffff0000) == 0x60000000)
1096 /* Allow nops in the prologue, but do not consider them to
1097 be part of the prologue unless followed by other prologue
1099 prev_insn_was_prologue_insn
= 0;
1103 else if ((op
& 0xffff0000) == 0x3c000000)
1104 { /* addis 0,0,NUM, used
1105 for >= 32k frames */
1106 fdata
->offset
= (op
& 0x0000ffff) << 16;
1107 fdata
->frameless
= 0;
1108 r0_contains_arg
= 0;
1112 else if ((op
& 0xffff0000) == 0x60000000)
1113 { /* ori 0,0,NUM, 2nd ha
1114 lf of >= 32k frames */
1115 fdata
->offset
|= (op
& 0x0000ffff);
1116 fdata
->frameless
= 0;
1117 r0_contains_arg
= 0;
1121 else if (lr_reg
>= 0 &&
1122 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1123 (((op
& 0xffff0000) == (lr_reg
| 0xf8010000)) ||
1124 /* stw Rx, NUM(r1) */
1125 ((op
& 0xffff0000) == (lr_reg
| 0x90010000)) ||
1126 /* stwu Rx, NUM(r1) */
1127 ((op
& 0xffff0000) == (lr_reg
| 0x94010000))))
1128 { /* where Rx == lr */
1129 fdata
->lr_offset
= offset
;
1130 fdata
->nosavedpc
= 0;
1131 /* Invalidate lr_reg, but don't set it to -1.
1132 That would mean that it had never been set. */
1134 if ((op
& 0xfc000003) == 0xf8000000 || /* std */
1135 (op
& 0xfc000000) == 0x90000000) /* stw */
1137 /* Does not update r1, so add displacement to lr_offset. */
1138 fdata
->lr_offset
+= SIGNED_SHORT (op
);
1143 else if (cr_reg
>= 0 &&
1144 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1145 (((op
& 0xffff0000) == (cr_reg
| 0xf8010000)) ||
1146 /* stw Rx, NUM(r1) */
1147 ((op
& 0xffff0000) == (cr_reg
| 0x90010000)) ||
1148 /* stwu Rx, NUM(r1) */
1149 ((op
& 0xffff0000) == (cr_reg
| 0x94010000))))
1150 { /* where Rx == cr */
1151 fdata
->cr_offset
= offset
;
1152 /* Invalidate cr_reg, but don't set it to -1.
1153 That would mean that it had never been set. */
1155 if ((op
& 0xfc000003) == 0xf8000000 ||
1156 (op
& 0xfc000000) == 0x90000000)
1158 /* Does not update r1, so add displacement to cr_offset. */
1159 fdata
->cr_offset
+= SIGNED_SHORT (op
);
1164 else if ((op
& 0xfe80ffff) == 0x42800005 && lr_reg
!= -1)
1166 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1167 prediction bits. If the LR has already been saved, we can
1171 else if (op
== 0x48000005)
1177 else if (op
== 0x48000004)
1182 else if ((op
& 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1183 in V.4 -mminimal-toc */
1184 (op
& 0xffff0000) == 0x3bde0000)
1185 { /* addi 30,30,foo@l */
1189 else if ((op
& 0xfc000001) == 0x48000001)
1193 fdata
->frameless
= 0;
1195 /* If the return address has already been saved, we can skip
1196 calls to blrl (for PIC). */
1197 if (lr_reg
!= -1 && bl_to_blrl_insn_p (pc
, op
))
1200 /* Don't skip over the subroutine call if it is not within
1201 the first three instructions of the prologue and either
1202 we have no line table information or the line info tells
1203 us that the subroutine call is not part of the line
1204 associated with the prologue. */
1205 if ((pc
- orig_pc
) > 8)
1207 struct symtab_and_line prologue_sal
= find_pc_line (orig_pc
, 0);
1208 struct symtab_and_line this_sal
= find_pc_line (pc
, 0);
1210 if ((prologue_sal
.line
== 0) || (prologue_sal
.line
!= this_sal
.line
))
1214 op
= read_memory_integer (pc
+ 4, 4);
1216 /* At this point, make sure this is not a trampoline
1217 function (a function that simply calls another functions,
1218 and nothing else). If the next is not a nop, this branch
1219 was part of the function prologue. */
1221 if (op
== 0x4def7b82 || op
== 0) /* crorc 15, 15, 15 */
1222 break; /* don't skip over
1227 /* update stack pointer */
1228 else if ((op
& 0xfc1f0000) == 0x94010000)
1229 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
1230 fdata
->frameless
= 0;
1231 fdata
->offset
= SIGNED_SHORT (op
);
1232 offset
= fdata
->offset
;
1235 else if ((op
& 0xfc1f016a) == 0x7c01016e)
1236 { /* stwux rX,r1,rY */
1237 /* no way to figure out what r1 is going to be */
1238 fdata
->frameless
= 0;
1239 offset
= fdata
->offset
;
1242 else if ((op
& 0xfc1f0003) == 0xf8010001)
1243 { /* stdu rX,NUM(r1) */
1244 fdata
->frameless
= 0;
1245 fdata
->offset
= SIGNED_SHORT (op
& ~3UL);
1246 offset
= fdata
->offset
;
1249 else if ((op
& 0xfc1f016a) == 0x7c01016a)
1250 { /* stdux rX,r1,rY */
1251 /* no way to figure out what r1 is going to be */
1252 fdata
->frameless
= 0;
1253 offset
= fdata
->offset
;
1256 else if ((op
& 0xffff0000) == 0x38210000)
1257 { /* addi r1,r1,SIMM */
1258 fdata
->frameless
= 0;
1259 fdata
->offset
+= SIGNED_SHORT (op
);
1260 offset
= fdata
->offset
;
1263 /* Load up minimal toc pointer. Do not treat an epilogue restore
1264 of r31 as a minimal TOC load. */
1265 else if (((op
>> 22) == 0x20f || /* l r31,... or l r30,... */
1266 (op
>> 22) == 0x3af) /* ld r31,... or ld r30,... */
1268 && !minimal_toc_loaded
)
1270 minimal_toc_loaded
= 1;
1273 /* move parameters from argument registers to local variable
1276 else if ((op
& 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1277 (((op
>> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1278 (((op
>> 21) & 31) <= 10) &&
1279 ((long) ((op
>> 16) & 31) >= fdata
->saved_gpr
)) /* Rx: local var reg */
1283 /* store parameters in stack */
1285 /* Move parameters from argument registers to temporary register. */
1286 else if (store_param_on_stack_p (op
, framep
, &r0_contains_arg
))
1290 /* Set up frame pointer */
1292 else if (op
== 0x603f0000 /* oril r31, r1, 0x0 */
1293 || op
== 0x7c3f0b78)
1295 fdata
->frameless
= 0;
1297 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 31);
1300 /* Another way to set up the frame pointer. */
1302 else if ((op
& 0xfc1fffff) == 0x38010000)
1303 { /* addi rX, r1, 0x0 */
1304 fdata
->frameless
= 0;
1306 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
1307 + ((op
& ~0x38010000) >> 21));
1310 /* AltiVec related instructions. */
1311 /* Store the vrsave register (spr 256) in another register for
1312 later manipulation, or load a register into the vrsave
1313 register. 2 instructions are used: mfvrsave and
1314 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1315 and mtspr SPR256, Rn. */
1316 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1317 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1318 else if ((op
& 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1320 vrsave_reg
= GET_SRC_REG (op
);
1323 else if ((op
& 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1327 /* Store the register where vrsave was saved to onto the stack:
1328 rS is the register where vrsave was stored in a previous
1330 /* 100100 sssss 00001 dddddddd dddddddd */
1331 else if ((op
& 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1333 if (vrsave_reg
== GET_SRC_REG (op
))
1335 fdata
->vrsave_offset
= SIGNED_SHORT (op
) + offset
;
1340 /* Compute the new value of vrsave, by modifying the register
1341 where vrsave was saved to. */
1342 else if (((op
& 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1343 || ((op
& 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1347 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1348 in a pair of insns to save the vector registers on the
1350 /* 001110 00000 00000 iiii iiii iiii iiii */
1351 /* 001110 01110 00000 iiii iiii iiii iiii */
1352 else if ((op
& 0xffff0000) == 0x38000000 /* li r0, SIMM */
1353 || (op
& 0xffff0000) == 0x39c00000) /* li r14, SIMM */
1355 if ((op
& 0xffff0000) == 0x38000000)
1356 r0_contains_arg
= 0;
1358 vr_saved_offset
= SIGNED_SHORT (op
);
1360 /* This insn by itself is not part of the prologue, unless
1361 if part of the pair of insns mentioned above. So do not
1362 record this insn as part of the prologue yet. */
1363 prev_insn_was_prologue_insn
= 0;
1365 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1366 /* 011111 sssss 11111 00000 00111001110 */
1367 else if ((op
& 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1369 if (pc
== (li_found_pc
+ 4))
1371 vr_reg
= GET_SRC_REG (op
);
1372 /* If this is the first vector reg to be saved, or if
1373 it has a lower number than others previously seen,
1374 reupdate the frame info. */
1375 if (fdata
->saved_vr
== -1 || fdata
->saved_vr
> vr_reg
)
1377 fdata
->saved_vr
= vr_reg
;
1378 fdata
->vr_offset
= vr_saved_offset
+ offset
;
1380 vr_saved_offset
= -1;
1385 /* End AltiVec related instructions. */
1387 /* Start BookE related instructions. */
1388 /* Store gen register S at (r31+uimm).
1389 Any register less than r13 is volatile, so we don't care. */
1390 /* 000100 sssss 11111 iiiii 01100100001 */
1391 else if (arch_info
->mach
== bfd_mach_ppc_e500
1392 && (op
& 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
1394 if ((op
& 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
1397 ev_reg
= GET_SRC_REG (op
);
1398 imm
= (op
>> 11) & 0x1f;
1399 ev_offset
= imm
* 8;
1400 /* If this is the first vector reg to be saved, or if
1401 it has a lower number than others previously seen,
1402 reupdate the frame info. */
1403 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1405 fdata
->saved_ev
= ev_reg
;
1406 fdata
->ev_offset
= ev_offset
+ offset
;
1411 /* Store gen register rS at (r1+rB). */
1412 /* 000100 sssss 00001 bbbbb 01100100000 */
1413 else if (arch_info
->mach
== bfd_mach_ppc_e500
1414 && (op
& 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1416 if (pc
== (li_found_pc
+ 4))
1418 ev_reg
= GET_SRC_REG (op
);
1419 /* If this is the first vector reg to be saved, or if
1420 it has a lower number than others previously seen,
1421 reupdate the frame info. */
1422 /* We know the contents of rB from the previous instruction. */
1423 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1425 fdata
->saved_ev
= ev_reg
;
1426 fdata
->ev_offset
= vr_saved_offset
+ offset
;
1428 vr_saved_offset
= -1;
1434 /* Store gen register r31 at (rA+uimm). */
1435 /* 000100 11111 aaaaa iiiii 01100100001 */
1436 else if (arch_info
->mach
== bfd_mach_ppc_e500
1437 && (op
& 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
1439 /* Wwe know that the source register is 31 already, but
1440 it can't hurt to compute it. */
1441 ev_reg
= GET_SRC_REG (op
);
1442 ev_offset
= ((op
>> 11) & 0x1f) * 8;
1443 /* If this is the first vector reg to be saved, or if
1444 it has a lower number than others previously seen,
1445 reupdate the frame info. */
1446 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1448 fdata
->saved_ev
= ev_reg
;
1449 fdata
->ev_offset
= ev_offset
+ offset
;
1454 /* Store gen register S at (r31+r0).
1455 Store param on stack when offset from SP bigger than 4 bytes. */
1456 /* 000100 sssss 11111 00000 01100100000 */
1457 else if (arch_info
->mach
== bfd_mach_ppc_e500
1458 && (op
& 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
1460 if (pc
== (li_found_pc
+ 4))
1462 if ((op
& 0x03e00000) >= 0x01a00000)
1464 ev_reg
= GET_SRC_REG (op
);
1465 /* If this is the first vector reg to be saved, or if
1466 it has a lower number than others previously seen,
1467 reupdate the frame info. */
1468 /* We know the contents of r0 from the previous
1470 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1472 fdata
->saved_ev
= ev_reg
;
1473 fdata
->ev_offset
= vr_saved_offset
+ offset
;
1477 vr_saved_offset
= -1;
1482 /* End BookE related instructions. */
1486 /* Not a recognized prologue instruction.
1487 Handle optimizer code motions into the prologue by continuing
1488 the search if we have no valid frame yet or if the return
1489 address is not yet saved in the frame. */
1490 if (fdata
->frameless
== 0 && fdata
->nosavedpc
== 0)
1493 if (op
== 0x4e800020 /* blr */
1494 || op
== 0x4e800420) /* bctr */
1495 /* Do not scan past epilogue in frameless functions or
1498 if ((op
& 0xf4000000) == 0x40000000) /* bxx */
1499 /* Never skip branches. */
1502 if (num_skip_non_prologue_insns
++ > max_skip_non_prologue_insns
)
1503 /* Do not scan too many insns, scanning insns is expensive with
1507 /* Continue scanning. */
1508 prev_insn_was_prologue_insn
= 0;
1514 /* I have problems with skipping over __main() that I need to address
1515 * sometime. Previously, I used to use misc_function_vector which
1516 * didn't work as well as I wanted to be. -MGO */
1518 /* If the first thing after skipping a prolog is a branch to a function,
1519 this might be a call to an initializer in main(), introduced by gcc2.
1520 We'd like to skip over it as well. Fortunately, xlc does some extra
1521 work before calling a function right after a prologue, thus we can
1522 single out such gcc2 behaviour. */
1525 if ((op
& 0xfc000001) == 0x48000001)
1526 { /* bl foo, an initializer function? */
1527 op
= read_memory_integer (pc
+ 4, 4);
1529 if (op
== 0x4def7b82)
1530 { /* cror 0xf, 0xf, 0xf (nop) */
1532 /* Check and see if we are in main. If so, skip over this
1533 initializer function as well. */
1535 tmp
= find_pc_misc_function (pc
);
1537 && strcmp (misc_function_vector
[tmp
].name
, main_name ()) == 0)
1543 fdata
->offset
= -fdata
->offset
;
1544 return last_prologue_pc
;
1548 /*************************************************************************
1549 Support for creating pushing a dummy frame into the stack, and popping
1551 *************************************************************************/
1554 /* All the ABI's require 16 byte alignment. */
1556 rs6000_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1558 return (addr
& -16);
1561 /* Pass the arguments in either registers, or in the stack. In RS/6000,
1562 the first eight words of the argument list (that might be less than
1563 eight parameters if some parameters occupy more than one word) are
1564 passed in r3..r10 registers. float and double parameters are
1565 passed in fpr's, in addition to that. Rest of the parameters if any
1566 are passed in user stack. There might be cases in which half of the
1567 parameter is copied into registers, the other half is pushed into
1570 Stack must be aligned on 64-bit boundaries when synthesizing
1573 If the function is returning a structure, then the return address is passed
1574 in r3, then the first 7 words of the parameters can be passed in registers,
1575 starting from r4. */
1578 rs6000_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1579 struct regcache
*regcache
, CORE_ADDR bp_addr
,
1580 int nargs
, struct value
**args
, CORE_ADDR sp
,
1581 int struct_return
, CORE_ADDR struct_addr
)
1583 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1586 int argno
; /* current argument number */
1587 int argbytes
; /* current argument byte */
1588 gdb_byte tmp_buffer
[50];
1589 int f_argno
= 0; /* current floating point argno */
1590 int wordsize
= gdbarch_tdep (current_gdbarch
)->wordsize
;
1591 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
1593 struct value
*arg
= 0;
1598 /* The calling convention this function implements assumes the
1599 processor has floating-point registers. We shouldn't be using it
1600 on PPC variants that lack them. */
1601 gdb_assert (ppc_floating_point_unit_p (current_gdbarch
));
1603 /* The first eight words of ther arguments are passed in registers.
1604 Copy them appropriately. */
1607 /* If the function is returning a `struct', then the first word
1608 (which will be passed in r3) is used for struct return address.
1609 In that case we should advance one word and start from r4
1610 register to copy parameters. */
1613 regcache_raw_write_unsigned (regcache
, tdep
->ppc_gp0_regnum
+ 3,
1619 effectively indirect call... gcc does...
1621 return_val example( float, int);
1624 float in fp0, int in r3
1625 offset of stack on overflow 8/16
1626 for varargs, must go by type.
1628 float in r3&r4, int in r5
1629 offset of stack on overflow different
1631 return in r3 or f0. If no float, must study how gcc emulates floats;
1632 pay attention to arg promotion.
1633 User may have to cast\args to handle promotion correctly
1634 since gdb won't know if prototype supplied or not.
1637 for (argno
= 0, argbytes
= 0; argno
< nargs
&& ii
< 8; ++ii
)
1639 int reg_size
= register_size (current_gdbarch
, ii
+ 3);
1642 type
= check_typedef (value_type (arg
));
1643 len
= TYPE_LENGTH (type
);
1645 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1648 /* Floating point arguments are passed in fpr's, as well as gpr's.
1649 There are 13 fpr's reserved for passing parameters. At this point
1650 there is no way we would run out of them. */
1652 gdb_assert (len
<= 8);
1654 regcache_cooked_write (regcache
,
1655 tdep
->ppc_fp0_regnum
+ 1 + f_argno
,
1656 value_contents (arg
));
1663 /* Argument takes more than one register. */
1664 while (argbytes
< len
)
1666 gdb_byte word
[MAX_REGISTER_SIZE
];
1667 memset (word
, 0, reg_size
);
1669 ((char *) value_contents (arg
)) + argbytes
,
1670 (len
- argbytes
) > reg_size
1671 ? reg_size
: len
- argbytes
);
1672 regcache_cooked_write (regcache
,
1673 tdep
->ppc_gp0_regnum
+ 3 + ii
,
1675 ++ii
, argbytes
+= reg_size
;
1678 goto ran_out_of_registers_for_arguments
;
1685 /* Argument can fit in one register. No problem. */
1686 int adj
= gdbarch_byte_order (current_gdbarch
)
1687 == BFD_ENDIAN_BIG
? reg_size
- len
: 0;
1688 gdb_byte word
[MAX_REGISTER_SIZE
];
1690 memset (word
, 0, reg_size
);
1691 memcpy (word
, value_contents (arg
), len
);
1692 regcache_cooked_write (regcache
, tdep
->ppc_gp0_regnum
+ 3 +ii
, word
);
1697 ran_out_of_registers_for_arguments
:
1699 regcache_cooked_read_unsigned (regcache
, SP_REGNUM
, &saved_sp
);
1701 /* Location for 8 parameters are always reserved. */
1704 /* Another six words for back chain, TOC register, link register, etc. */
1707 /* Stack pointer must be quadword aligned. */
1710 /* If there are more arguments, allocate space for them in
1711 the stack, then push them starting from the ninth one. */
1713 if ((argno
< nargs
) || argbytes
)
1719 space
+= ((len
- argbytes
+ 3) & -4);
1725 for (; jj
< nargs
; ++jj
)
1727 struct value
*val
= args
[jj
];
1728 space
+= ((TYPE_LENGTH (value_type (val
))) + 3) & -4;
1731 /* Add location required for the rest of the parameters. */
1732 space
= (space
+ 15) & -16;
1735 /* This is another instance we need to be concerned about
1736 securing our stack space. If we write anything underneath %sp
1737 (r1), we might conflict with the kernel who thinks he is free
1738 to use this area. So, update %sp first before doing anything
1741 regcache_raw_write_signed (regcache
, SP_REGNUM
, sp
);
1743 /* If the last argument copied into the registers didn't fit there
1744 completely, push the rest of it into stack. */
1748 write_memory (sp
+ 24 + (ii
* 4),
1749 value_contents (arg
) + argbytes
,
1752 ii
+= ((len
- argbytes
+ 3) & -4) / 4;
1755 /* Push the rest of the arguments into stack. */
1756 for (; argno
< nargs
; ++argno
)
1760 type
= check_typedef (value_type (arg
));
1761 len
= TYPE_LENGTH (type
);
1764 /* Float types should be passed in fpr's, as well as in the
1766 if (TYPE_CODE (type
) == TYPE_CODE_FLT
&& f_argno
< 13)
1769 gdb_assert (len
<= 8);
1771 regcache_cooked_write (regcache
,
1772 tdep
->ppc_fp0_regnum
+ 1 + f_argno
,
1773 value_contents (arg
));
1777 write_memory (sp
+ 24 + (ii
* 4), value_contents (arg
), len
);
1778 ii
+= ((len
+ 3) & -4) / 4;
1782 /* Set the stack pointer. According to the ABI, the SP is meant to
1783 be set _before_ the corresponding stack space is used. On AIX,
1784 this even applies when the target has been completely stopped!
1785 Not doing this can lead to conflicts with the kernel which thinks
1786 that it still has control over this not-yet-allocated stack
1788 regcache_raw_write_signed (regcache
, SP_REGNUM
, sp
);
1790 /* Set back chain properly. */
1791 store_unsigned_integer (tmp_buffer
, wordsize
, saved_sp
);
1792 write_memory (sp
, tmp_buffer
, wordsize
);
1794 /* Point the inferior function call's return address at the dummy's
1796 regcache_raw_write_signed (regcache
, tdep
->ppc_lr_regnum
, bp_addr
);
1798 /* Set the TOC register, get the value from the objfile reader
1799 which, in turn, gets it from the VMAP table. */
1800 if (rs6000_find_toc_address_hook
!= NULL
)
1802 CORE_ADDR tocvalue
= (*rs6000_find_toc_address_hook
) (func_addr
);
1803 regcache_raw_write_signed (regcache
, tdep
->ppc_toc_regnum
, tocvalue
);
1806 target_store_registers (regcache
, -1);
1810 static enum return_value_convention
1811 rs6000_return_value (struct gdbarch
*gdbarch
, struct type
*valtype
,
1812 struct regcache
*regcache
, gdb_byte
*readbuf
,
1813 const gdb_byte
*writebuf
)
1815 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1818 /* The calling convention this function implements assumes the
1819 processor has floating-point registers. We shouldn't be using it
1820 on PowerPC variants that lack them. */
1821 gdb_assert (ppc_floating_point_unit_p (current_gdbarch
));
1823 /* AltiVec extension: Functions that declare a vector data type as a
1824 return value place that return value in VR2. */
1825 if (TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (valtype
)
1826 && TYPE_LENGTH (valtype
) == 16)
1829 regcache_cooked_read (regcache
, tdep
->ppc_vr0_regnum
+ 2, readbuf
);
1831 regcache_cooked_write (regcache
, tdep
->ppc_vr0_regnum
+ 2, writebuf
);
1833 return RETURN_VALUE_REGISTER_CONVENTION
;
1836 /* If the called subprogram returns an aggregate, there exists an
1837 implicit first argument, whose value is the address of a caller-
1838 allocated buffer into which the callee is assumed to store its
1839 return value. All explicit parameters are appropriately
1841 if (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
1842 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
1843 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
1844 return RETURN_VALUE_STRUCT_CONVENTION
;
1846 /* Scalar floating-point values are returned in FPR1 for float or
1847 double, and in FPR1:FPR2 for quadword precision. Fortran
1848 complex*8 and complex*16 are returned in FPR1:FPR2, and
1849 complex*32 is returned in FPR1:FPR4. */
1850 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
1851 && (TYPE_LENGTH (valtype
) == 4 || TYPE_LENGTH (valtype
) == 8))
1853 struct type
*regtype
= register_type (gdbarch
, tdep
->ppc_fp0_regnum
);
1856 /* FIXME: kettenis/2007-01-01: Add support for quadword
1857 precision and complex. */
1861 regcache_cooked_read (regcache
, tdep
->ppc_fp0_regnum
+ 1, regval
);
1862 convert_typed_floating (regval
, regtype
, readbuf
, valtype
);
1866 convert_typed_floating (writebuf
, valtype
, regval
, regtype
);
1867 regcache_cooked_write (regcache
, tdep
->ppc_fp0_regnum
+ 1, regval
);
1870 return RETURN_VALUE_REGISTER_CONVENTION
;
1873 /* Values of the types int, long, short, pointer, and char (length
1874 is less than or equal to four bytes), as well as bit values of
1875 lengths less than or equal to 32 bits, must be returned right
1876 justified in GPR3 with signed values sign extended and unsigned
1877 values zero extended, as necessary. */
1878 if (TYPE_LENGTH (valtype
) <= tdep
->wordsize
)
1884 /* For reading we don't have to worry about sign extension. */
1885 regcache_cooked_read_unsigned (regcache
, tdep
->ppc_gp0_regnum
+ 3,
1887 store_unsigned_integer (readbuf
, TYPE_LENGTH (valtype
), regval
);
1891 /* For writing, use unpack_long since that should handle any
1892 required sign extension. */
1893 regcache_cooked_write_unsigned (regcache
, tdep
->ppc_gp0_regnum
+ 3,
1894 unpack_long (valtype
, writebuf
));
1897 return RETURN_VALUE_REGISTER_CONVENTION
;
1900 /* Eight-byte non-floating-point scalar values must be returned in
1903 if (TYPE_LENGTH (valtype
) == 8)
1905 gdb_assert (TYPE_CODE (valtype
) != TYPE_CODE_FLT
);
1906 gdb_assert (tdep
->wordsize
== 4);
1912 regcache_cooked_read (regcache
, tdep
->ppc_gp0_regnum
+ 3, regval
);
1913 regcache_cooked_read (regcache
, tdep
->ppc_gp0_regnum
+ 4,
1915 memcpy (readbuf
, regval
, 8);
1919 regcache_cooked_write (regcache
, tdep
->ppc_gp0_regnum
+ 3, writebuf
);
1920 regcache_cooked_write (regcache
, tdep
->ppc_gp0_regnum
+ 4,
1924 return RETURN_VALUE_REGISTER_CONVENTION
;
1927 return RETURN_VALUE_STRUCT_CONVENTION
;
1930 /* Return whether handle_inferior_event() should proceed through code
1931 starting at PC in function NAME when stepping.
1933 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
1934 handle memory references that are too distant to fit in instructions
1935 generated by the compiler. For example, if 'foo' in the following
1940 is greater than 32767, the linker might replace the lwz with a branch to
1941 somewhere in @FIX1 that does the load in 2 instructions and then branches
1942 back to where execution should continue.
1944 GDB should silently step over @FIX code, just like AIX dbx does.
1945 Unfortunately, the linker uses the "b" instruction for the
1946 branches, meaning that the link register doesn't get set.
1947 Therefore, GDB's usual step_over_function () mechanism won't work.
1949 Instead, use the IN_SOLIB_RETURN_TRAMPOLINE and
1950 SKIP_TRAMPOLINE_CODE hooks in handle_inferior_event() to skip past
1954 rs6000_in_solib_return_trampoline (CORE_ADDR pc
, char *name
)
1956 return name
&& !strncmp (name
, "@FIX", 4);
1959 /* Skip code that the user doesn't want to see when stepping:
1961 1. Indirect function calls use a piece of trampoline code to do context
1962 switching, i.e. to set the new TOC table. Skip such code if we are on
1963 its first instruction (as when we have single-stepped to here).
1965 2. Skip shared library trampoline code (which is different from
1966 indirect function call trampolines).
1968 3. Skip bigtoc fixup code.
1970 Result is desired PC to step until, or NULL if we are not in
1971 code that should be skipped. */
1974 rs6000_skip_trampoline_code (CORE_ADDR pc
)
1976 unsigned int ii
, op
;
1978 CORE_ADDR solib_target_pc
;
1979 struct minimal_symbol
*msymbol
;
1981 static unsigned trampoline_code
[] =
1983 0x800b0000, /* l r0,0x0(r11) */
1984 0x90410014, /* st r2,0x14(r1) */
1985 0x7c0903a6, /* mtctr r0 */
1986 0x804b0004, /* l r2,0x4(r11) */
1987 0x816b0008, /* l r11,0x8(r11) */
1988 0x4e800420, /* bctr */
1989 0x4e800020, /* br */
1993 /* Check for bigtoc fixup code. */
1994 msymbol
= lookup_minimal_symbol_by_pc (pc
);
1996 && rs6000_in_solib_return_trampoline (pc
,
1997 DEPRECATED_SYMBOL_NAME (msymbol
)))
1999 /* Double-check that the third instruction from PC is relative "b". */
2000 op
= read_memory_integer (pc
+ 8, 4);
2001 if ((op
& 0xfc000003) == 0x48000000)
2003 /* Extract bits 6-29 as a signed 24-bit relative word address and
2004 add it to the containing PC. */
2005 rel
= ((int)(op
<< 6) >> 6);
2006 return pc
+ 8 + rel
;
2010 /* If pc is in a shared library trampoline, return its target. */
2011 solib_target_pc
= find_solib_trampoline_target (pc
);
2012 if (solib_target_pc
)
2013 return solib_target_pc
;
2015 for (ii
= 0; trampoline_code
[ii
]; ++ii
)
2017 op
= read_memory_integer (pc
+ (ii
* 4), 4);
2018 if (op
!= trampoline_code
[ii
])
2021 ii
= read_register (11); /* r11 holds destination addr */
2022 pc
= read_memory_addr (ii
, gdbarch_tdep (current_gdbarch
)->wordsize
); /* (r11) value */
2026 /* Return the size of register REG when words are WORDSIZE bytes long. If REG
2027 isn't available with that word size, return 0. */
2030 regsize (const struct reg
*reg
, int wordsize
)
2032 return wordsize
== 8 ? reg
->sz64
: reg
->sz32
;
2035 /* Return the name of register number N, or null if no such register exists
2036 in the current architecture. */
2039 rs6000_register_name (int n
)
2041 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2042 const struct reg
*reg
= tdep
->regs
+ n
;
2044 if (!regsize (reg
, tdep
->wordsize
))
2049 /* Return the GDB type object for the "standard" data type
2050 of data in register N. */
2052 static struct type
*
2053 rs6000_register_type (struct gdbarch
*gdbarch
, int n
)
2055 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2056 const struct reg
*reg
= tdep
->regs
+ n
;
2059 return builtin_type_double
;
2062 int size
= regsize (reg
, tdep
->wordsize
);
2066 return builtin_type_int0
;
2068 return builtin_type_uint32
;
2070 if (tdep
->ppc_ev0_regnum
<= n
&& n
<= tdep
->ppc_ev31_regnum
)
2071 return builtin_type_vec64
;
2073 return builtin_type_uint64
;
2076 return builtin_type_vec128
;
2079 internal_error (__FILE__
, __LINE__
, _("Register %d size %d unknown"),
2085 /* Is REGNUM a member of REGGROUP? */
2087 rs6000_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2088 struct reggroup
*group
)
2090 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2095 if (REGISTER_NAME (regnum
) == NULL
2096 || *REGISTER_NAME (regnum
) == '\0')
2098 if (group
== all_reggroup
)
2101 float_p
= (regnum
== tdep
->ppc_fpscr_regnum
2102 || (regnum
>= tdep
->ppc_fp0_regnum
2103 && regnum
< tdep
->ppc_fp0_regnum
+ 32));
2104 if (group
== float_reggroup
)
2107 vector_p
= ((tdep
->ppc_vr0_regnum
>= 0
2108 && regnum
>= tdep
->ppc_vr0_regnum
2109 && regnum
< tdep
->ppc_vr0_regnum
+ 32)
2110 || (tdep
->ppc_ev0_regnum
>= 0
2111 && regnum
>= tdep
->ppc_ev0_regnum
2112 && regnum
< tdep
->ppc_ev0_regnum
+ 32)
2113 || regnum
== tdep
->ppc_vrsave_regnum
- 1 /* vscr */
2114 || regnum
== tdep
->ppc_vrsave_regnum
2115 || regnum
== tdep
->ppc_acc_regnum
2116 || regnum
== tdep
->ppc_spefscr_regnum
);
2117 if (group
== vector_reggroup
)
2120 /* Note that PS aka MSR isn't included - it's a system register (and
2121 besides, due to GCC's CFI foobar you do not want to restore
2123 general_p
= ((regnum
>= tdep
->ppc_gp0_regnum
2124 && regnum
< tdep
->ppc_gp0_regnum
+ 32)
2125 || regnum
== tdep
->ppc_toc_regnum
2126 || regnum
== tdep
->ppc_cr_regnum
2127 || regnum
== tdep
->ppc_lr_regnum
2128 || regnum
== tdep
->ppc_ctr_regnum
2129 || regnum
== tdep
->ppc_xer_regnum
2130 || regnum
== PC_REGNUM
);
2131 if (group
== general_reggroup
)
2134 if (group
== save_reggroup
|| group
== restore_reggroup
)
2135 return general_p
|| vector_p
|| float_p
;
2140 /* The register format for RS/6000 floating point registers is always
2141 double, we need a conversion if the memory format is float. */
2144 rs6000_convert_register_p (int regnum
, struct type
*type
)
2146 const struct reg
*reg
= gdbarch_tdep (current_gdbarch
)->regs
+ regnum
;
2149 && TYPE_CODE (type
) == TYPE_CODE_FLT
2150 && TYPE_LENGTH (type
) != TYPE_LENGTH (builtin_type_double
));
2154 rs6000_register_to_value (struct frame_info
*frame
,
2159 const struct reg
*reg
= gdbarch_tdep (current_gdbarch
)->regs
+ regnum
;
2160 gdb_byte from
[MAX_REGISTER_SIZE
];
2162 gdb_assert (reg
->fpr
);
2163 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
2165 get_frame_register (frame
, regnum
, from
);
2166 convert_typed_floating (from
, builtin_type_double
, to
, type
);
2170 rs6000_value_to_register (struct frame_info
*frame
,
2173 const gdb_byte
*from
)
2175 const struct reg
*reg
= gdbarch_tdep (current_gdbarch
)->regs
+ regnum
;
2176 gdb_byte to
[MAX_REGISTER_SIZE
];
2178 gdb_assert (reg
->fpr
);
2179 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
2181 convert_typed_floating (from
, type
, to
, builtin_type_double
);
2182 put_frame_register (frame
, regnum
, to
);
2185 /* Move SPE vector register values between a 64-bit buffer and the two
2186 32-bit raw register halves in a regcache. This function handles
2187 both splitting a 64-bit value into two 32-bit halves, and joining
2188 two halves into a whole 64-bit value, depending on the function
2189 passed as the MOVE argument.
2191 EV_REG must be the number of an SPE evN vector register --- a
2192 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2195 Call MOVE once for each 32-bit half of that register, passing
2196 REGCACHE, the number of the raw register corresponding to that
2197 half, and the address of the appropriate half of BUFFER.
2199 For example, passing 'regcache_raw_read' as the MOVE function will
2200 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2201 'regcache_raw_supply' will supply the contents of BUFFER to the
2202 appropriate pair of raw registers in REGCACHE.
2204 You may need to cast away some 'const' qualifiers when passing
2205 MOVE, since this function can't tell at compile-time which of
2206 REGCACHE or BUFFER is acting as the source of the data. If C had
2207 co-variant type qualifiers, ... */
2209 e500_move_ev_register (void (*move
) (struct regcache
*regcache
,
2210 int regnum
, gdb_byte
*buf
),
2211 struct regcache
*regcache
, int ev_reg
,
2214 struct gdbarch
*arch
= get_regcache_arch (regcache
);
2215 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
2217 gdb_byte
*byte_buffer
= buffer
;
2219 gdb_assert (tdep
->ppc_ev0_regnum
<= ev_reg
2220 && ev_reg
< tdep
->ppc_ev0_regnum
+ ppc_num_gprs
);
2222 reg_index
= ev_reg
- tdep
->ppc_ev0_regnum
;
2224 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
2226 move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
, byte_buffer
);
2227 move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
, byte_buffer
+ 4);
2231 move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
, byte_buffer
);
2232 move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
, byte_buffer
+ 4);
2237 e500_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2238 int reg_nr
, gdb_byte
*buffer
)
2240 struct gdbarch
*regcache_arch
= get_regcache_arch (regcache
);
2241 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2243 gdb_assert (regcache_arch
== gdbarch
);
2245 if (tdep
->ppc_ev0_regnum
<= reg_nr
2246 && reg_nr
< tdep
->ppc_ev0_regnum
+ ppc_num_gprs
)
2247 e500_move_ev_register (regcache_raw_read
, regcache
, reg_nr
, buffer
);
2249 internal_error (__FILE__
, __LINE__
,
2250 _("e500_pseudo_register_read: "
2251 "called on unexpected register '%s' (%d)"),
2252 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2256 e500_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2257 int reg_nr
, const gdb_byte
*buffer
)
2259 struct gdbarch
*regcache_arch
= get_regcache_arch (regcache
);
2260 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2262 gdb_assert (regcache_arch
== gdbarch
);
2264 if (tdep
->ppc_ev0_regnum
<= reg_nr
2265 && reg_nr
< tdep
->ppc_ev0_regnum
+ ppc_num_gprs
)
2266 e500_move_ev_register ((void (*) (struct regcache
*, int, gdb_byte
*))
2268 regcache
, reg_nr
, (gdb_byte
*) buffer
);
2270 internal_error (__FILE__
, __LINE__
,
2271 _("e500_pseudo_register_read: "
2272 "called on unexpected register '%s' (%d)"),
2273 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2276 /* The E500 needs a custom reggroup function: it has anonymous raw
2277 registers, and default_register_reggroup_p assumes that anonymous
2278 registers are not members of any reggroup. */
2280 e500_register_reggroup_p (struct gdbarch
*gdbarch
,
2282 struct reggroup
*group
)
2284 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2286 /* The save and restore register groups need to include the
2287 upper-half registers, even though they're anonymous. */
2288 if ((group
== save_reggroup
2289 || group
== restore_reggroup
)
2290 && (tdep
->ppc_ev0_upper_regnum
<= regnum
2291 && regnum
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
))
2294 /* In all other regards, the default reggroup definition is fine. */
2295 return default_register_reggroup_p (gdbarch
, regnum
, group
);
2298 /* Convert a DBX STABS register number to a GDB register number. */
2300 rs6000_stab_reg_to_regnum (int num
)
2302 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2304 if (0 <= num
&& num
<= 31)
2305 return tdep
->ppc_gp0_regnum
+ num
;
2306 else if (32 <= num
&& num
<= 63)
2307 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2308 specifies registers the architecture doesn't have? Our
2309 callers don't check the value we return. */
2310 return tdep
->ppc_fp0_regnum
+ (num
- 32);
2311 else if (77 <= num
&& num
<= 108)
2312 return tdep
->ppc_vr0_regnum
+ (num
- 77);
2313 else if (1200 <= num
&& num
< 1200 + 32)
2314 return tdep
->ppc_ev0_regnum
+ (num
- 1200);
2319 return tdep
->ppc_mq_regnum
;
2321 return tdep
->ppc_lr_regnum
;
2323 return tdep
->ppc_ctr_regnum
;
2325 return tdep
->ppc_xer_regnum
;
2327 return tdep
->ppc_vrsave_regnum
;
2329 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
2331 return tdep
->ppc_acc_regnum
;
2333 return tdep
->ppc_spefscr_regnum
;
2340 /* Convert a Dwarf 2 register number to a GDB register number. */
2342 rs6000_dwarf2_reg_to_regnum (int num
)
2344 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2346 if (0 <= num
&& num
<= 31)
2347 return tdep
->ppc_gp0_regnum
+ num
;
2348 else if (32 <= num
&& num
<= 63)
2349 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2350 specifies registers the architecture doesn't have? Our
2351 callers don't check the value we return. */
2352 return tdep
->ppc_fp0_regnum
+ (num
- 32);
2353 else if (1124 <= num
&& num
< 1124 + 32)
2354 return tdep
->ppc_vr0_regnum
+ (num
- 1124);
2355 else if (1200 <= num
&& num
< 1200 + 32)
2356 return tdep
->ppc_ev0_regnum
+ (num
- 1200);
2361 return tdep
->ppc_cr_regnum
;
2363 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
2365 return tdep
->ppc_acc_regnum
;
2367 return tdep
->ppc_mq_regnum
;
2369 return tdep
->ppc_xer_regnum
;
2371 return tdep
->ppc_lr_regnum
;
2373 return tdep
->ppc_ctr_regnum
;
2375 return tdep
->ppc_vrsave_regnum
;
2377 return tdep
->ppc_spefscr_regnum
;
2383 /* Translate a .eh_frame register to DWARF register, or adjust a
2384 .debug_frame register. */
2387 rs6000_adjust_frame_regnum (struct gdbarch
*gdbarch
, int num
, int eh_frame_p
)
2389 /* GCC releases before 3.4 use GCC internal register numbering in
2390 .debug_frame (and .debug_info, et cetera). The numbering is
2391 different from the standard SysV numbering for everything except
2392 for GPRs and FPRs. We can not detect this problem in most cases
2393 - to get accurate debug info for variables living in lr, ctr, v0,
2394 et cetera, use a newer version of GCC. But we must detect
2395 one important case - lr is in column 65 in .debug_frame output,
2398 GCC 3.4, and the "hammer" branch, have a related problem. They
2399 record lr register saves in .debug_frame as 108, but still record
2400 the return column as 65. We fix that up too.
2402 We can do this because 65 is assigned to fpsr, and GCC never
2403 generates debug info referring to it. To add support for
2404 handwritten debug info that restores fpsr, we would need to add a
2405 producer version check to this. */
2414 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
2415 internal register numbering; translate that to the standard DWARF2
2416 register numbering. */
2417 if (0 <= num
&& num
<= 63) /* r0-r31,fp0-fp31 */
2419 else if (68 <= num
&& num
<= 75) /* cr0-cr8 */
2420 return num
- 68 + 86;
2421 else if (77 <= num
&& num
<= 108) /* vr0-vr31 */
2422 return num
- 77 + 1124;
2434 case 109: /* vrsave */
2436 case 110: /* vscr */
2438 case 111: /* spe_acc */
2440 case 112: /* spefscr */
2447 /* Support for CONVERT_FROM_FUNC_PTR_ADDR (ARCH, ADDR, TARG).
2449 Usually a function pointer's representation is simply the address
2450 of the function. On the RS/6000 however, a function pointer is
2451 represented by a pointer to an OPD entry. This OPD entry contains
2452 three words, the first word is the address of the function, the
2453 second word is the TOC pointer (r2), and the third word is the
2454 static chain value. Throughout GDB it is currently assumed that a
2455 function pointer contains the address of the function, which is not
2456 easy to fix. In addition, the conversion of a function address to
2457 a function pointer would require allocation of an OPD entry in the
2458 inferior's memory space, with all its drawbacks. To be able to
2459 call C++ virtual methods in the inferior (which are called via
2460 function pointers), find_function_addr uses this function to get the
2461 function address from a function pointer. */
2463 /* Return real function address if ADDR (a function pointer) is in the data
2464 space and is therefore a special function pointer. */
2467 rs6000_convert_from_func_ptr_addr (struct gdbarch
*gdbarch
,
2469 struct target_ops
*targ
)
2471 struct obj_section
*s
;
2473 s
= find_pc_section (addr
);
2474 if (s
&& s
->the_bfd_section
->flags
& SEC_CODE
)
2477 /* ADDR is in the data space, so it's a special function pointer. */
2478 return read_memory_addr (addr
, gdbarch_tdep (gdbarch
)->wordsize
);
2482 /* Handling the various POWER/PowerPC variants. */
2485 /* The arrays here called registers_MUMBLE hold information about available
2488 For each family of PPC variants, I've tried to isolate out the
2489 common registers and put them up front, so that as long as you get
2490 the general family right, GDB will correctly identify the registers
2491 common to that family. The common register sets are:
2493 For the 60x family: hid0 hid1 iabr dabr pir
2495 For the 505 and 860 family: eie eid nri
2497 For the 403 and 403GC: icdbdr esr dear evpr cdbcr tsr tcr pit tbhi
2498 tblo srr2 srr3 dbsr dbcr iac1 iac2 dac1 dac2 dccr iccr pbl1
2501 Most of these register groups aren't anything formal. I arrived at
2502 them by looking at the registers that occurred in more than one
2505 Note: kevinb/2002-04-30: Support for the fpscr register was added
2506 during April, 2002. Slot 70 is being used for PowerPC and slot 71
2507 for Power. For PowerPC, slot 70 was unused and was already in the
2508 PPC_UISA_SPRS which is ideally where fpscr should go. For Power,
2509 slot 70 was being used for "mq", so the next available slot (71)
2510 was chosen. It would have been nice to be able to make the
2511 register numbers the same across processor cores, but this wasn't
2512 possible without either 1) renumbering some registers for some
2513 processors or 2) assigning fpscr to a really high slot that's
2514 larger than any current register number. Doing (1) is bad because
2515 existing stubs would break. Doing (2) is undesirable because it
2516 would introduce a really large gap between fpscr and the rest of
2517 the registers for most processors. */
2519 /* Convenience macros for populating register arrays. */
2521 /* Within another macro, convert S to a string. */
2525 /* Return a struct reg defining register NAME that's 32 bits on 32-bit systems
2526 and 64 bits on 64-bit systems. */
2527 #define R(name) { STR(name), 4, 8, 0, 0, -1 }
2529 /* Return a struct reg defining register NAME that's 32 bits on all
2531 #define R4(name) { STR(name), 4, 4, 0, 0, -1 }
2533 /* Return a struct reg defining register NAME that's 64 bits on all
2535 #define R8(name) { STR(name), 8, 8, 0, 0, -1 }
2537 /* Return a struct reg defining register NAME that's 128 bits on all
2539 #define R16(name) { STR(name), 16, 16, 0, 0, -1 }
2541 /* Return a struct reg defining floating-point register NAME. */
2542 #define F(name) { STR(name), 8, 8, 1, 0, -1 }
2544 /* Return a struct reg defining a pseudo register NAME that is 64 bits
2545 long on all systems. */
2546 #define P8(name) { STR(name), 8, 8, 0, 1, -1 }
2548 /* Return a struct reg defining register NAME that's 32 bits on 32-bit
2549 systems and that doesn't exist on 64-bit systems. */
2550 #define R32(name) { STR(name), 4, 0, 0, 0, -1 }
2552 /* Return a struct reg defining register NAME that's 64 bits on 64-bit
2553 systems and that doesn't exist on 32-bit systems. */
2554 #define R64(name) { STR(name), 0, 8, 0, 0, -1 }
2556 /* Return a struct reg placeholder for a register that doesn't exist. */
2557 #define R0 { 0, 0, 0, 0, 0, -1 }
2559 /* Return a struct reg defining an anonymous raw register that's 32
2560 bits on all systems. */
2561 #define A4 { 0, 4, 4, 0, 0, -1 }
2563 /* Return a struct reg defining an SPR named NAME that is 32 bits on
2564 32-bit systems and 64 bits on 64-bit systems. */
2565 #define S(name) { STR(name), 4, 8, 0, 0, ppc_spr_ ## name }
2567 /* Return a struct reg defining an SPR named NAME that is 32 bits on
2569 #define S4(name) { STR(name), 4, 4, 0, 0, ppc_spr_ ## name }
2571 /* Return a struct reg defining an SPR named NAME that is 32 bits on
2572 all systems, and whose SPR number is NUMBER. */
2573 #define SN4(name, number) { STR(name), 4, 4, 0, 0, (number) }
2575 /* Return a struct reg defining an SPR named NAME that's 64 bits on
2576 64-bit systems and that doesn't exist on 32-bit systems. */
2577 #define S64(name) { STR(name), 0, 8, 0, 0, ppc_spr_ ## name }
2579 /* UISA registers common across all architectures, including POWER. */
2581 #define COMMON_UISA_REGS \
2582 /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \
2583 /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \
2584 /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \
2585 /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \
2586 /* 32 */ F(f0), F(f1), F(f2), F(f3), F(f4), F(f5), F(f6), F(f7), \
2587 /* 40 */ F(f8), F(f9), F(f10),F(f11),F(f12),F(f13),F(f14),F(f15), \
2588 /* 48 */ F(f16),F(f17),F(f18),F(f19),F(f20),F(f21),F(f22),F(f23), \
2589 /* 56 */ F(f24),F(f25),F(f26),F(f27),F(f28),F(f29),F(f30),F(f31), \
2590 /* 64 */ R(pc), R(ps)
2592 /* UISA-level SPRs for PowerPC. */
2593 #define PPC_UISA_SPRS \
2594 /* 66 */ R4(cr), S(lr), S(ctr), S4(xer), R4(fpscr)
2596 /* UISA-level SPRs for PowerPC without floating point support. */
2597 #define PPC_UISA_NOFP_SPRS \
2598 /* 66 */ R4(cr), S(lr), S(ctr), S4(xer), R0
2600 /* Segment registers, for PowerPC. */
2601 #define PPC_SEGMENT_REGS \
2602 /* 71 */ R32(sr0), R32(sr1), R32(sr2), R32(sr3), \
2603 /* 75 */ R32(sr4), R32(sr5), R32(sr6), R32(sr7), \
2604 /* 79 */ R32(sr8), R32(sr9), R32(sr10), R32(sr11), \
2605 /* 83 */ R32(sr12), R32(sr13), R32(sr14), R32(sr15)
2607 /* OEA SPRs for PowerPC. */
2608 #define PPC_OEA_SPRS \
2610 /* 88 */ S(ibat0u), S(ibat0l), S(ibat1u), S(ibat1l), \
2611 /* 92 */ S(ibat2u), S(ibat2l), S(ibat3u), S(ibat3l), \
2612 /* 96 */ S(dbat0u), S(dbat0l), S(dbat1u), S(dbat1l), \
2613 /* 100 */ S(dbat2u), S(dbat2l), S(dbat3u), S(dbat3l), \
2614 /* 104 */ S(sdr1), S64(asr), S(dar), S4(dsisr), \
2615 /* 108 */ S(sprg0), S(sprg1), S(sprg2), S(sprg3), \
2616 /* 112 */ S(srr0), S(srr1), S(tbl), S(tbu), \
2617 /* 116 */ S4(dec), S(dabr), S4(ear)
2619 /* AltiVec registers. */
2620 #define PPC_ALTIVEC_REGS \
2621 /*119*/R16(vr0), R16(vr1), R16(vr2), R16(vr3), R16(vr4), R16(vr5), R16(vr6), R16(vr7), \
2622 /*127*/R16(vr8), R16(vr9), R16(vr10),R16(vr11),R16(vr12),R16(vr13),R16(vr14),R16(vr15), \
2623 /*135*/R16(vr16),R16(vr17),R16(vr18),R16(vr19),R16(vr20),R16(vr21),R16(vr22),R16(vr23), \
2624 /*143*/R16(vr24),R16(vr25),R16(vr26),R16(vr27),R16(vr28),R16(vr29),R16(vr30),R16(vr31), \
2625 /*151*/R4(vscr), R4(vrsave)
2628 /* On machines supporting the SPE APU, the general-purpose registers
2629 are 64 bits long. There are SIMD vector instructions to treat them
2630 as pairs of floats, but the rest of the instruction set treats them
2631 as 32-bit registers, and only operates on their lower halves.
2633 In the GDB regcache, we treat their high and low halves as separate
2634 registers. The low halves we present as the general-purpose
2635 registers, and then we have pseudo-registers that stitch together
2636 the upper and lower halves and present them as pseudo-registers. */
2638 /* SPE GPR lower halves --- raw registers. */
2639 #define PPC_SPE_GP_REGS \
2640 /* 0 */ R4(r0), R4(r1), R4(r2), R4(r3), R4(r4), R4(r5), R4(r6), R4(r7), \
2641 /* 8 */ R4(r8), R4(r9), R4(r10),R4(r11),R4(r12),R4(r13),R4(r14),R4(r15), \
2642 /* 16 */ R4(r16),R4(r17),R4(r18),R4(r19),R4(r20),R4(r21),R4(r22),R4(r23), \
2643 /* 24 */ R4(r24),R4(r25),R4(r26),R4(r27),R4(r28),R4(r29),R4(r30),R4(r31)
2645 /* SPE GPR upper halves --- anonymous raw registers. */
2646 #define PPC_SPE_UPPER_GP_REGS \
2647 /* 0 */ A4, A4, A4, A4, A4, A4, A4, A4, \
2648 /* 8 */ A4, A4, A4, A4, A4, A4, A4, A4, \
2649 /* 16 */ A4, A4, A4, A4, A4, A4, A4, A4, \
2650 /* 24 */ A4, A4, A4, A4, A4, A4, A4, A4
2652 /* SPE GPR vector registers --- pseudo registers based on underlying
2653 gprs and the anonymous upper half raw registers. */
2654 #define PPC_EV_PSEUDO_REGS \
2655 /* 0*/P8(ev0), P8(ev1), P8(ev2), P8(ev3), P8(ev4), P8(ev5), P8(ev6), P8(ev7), \
2656 /* 8*/P8(ev8), P8(ev9), P8(ev10),P8(ev11),P8(ev12),P8(ev13),P8(ev14),P8(ev15),\
2657 /*16*/P8(ev16),P8(ev17),P8(ev18),P8(ev19),P8(ev20),P8(ev21),P8(ev22),P8(ev23),\
2658 /*24*/P8(ev24),P8(ev25),P8(ev26),P8(ev27),P8(ev28),P8(ev29),P8(ev30),P8(ev31)
2660 /* IBM POWER (pre-PowerPC) architecture, user-level view. We only cover
2661 user-level SPR's. */
2662 static const struct reg registers_power
[] =
2665 /* 66 */ R4(cnd
), S(lr
), S(cnt
), S4(xer
), S4(mq
),
2669 /* PowerPC UISA - a PPC processor as viewed by user-level code. A UISA-only
2670 view of the PowerPC. */
2671 static const struct reg registers_powerpc
[] =
2680 Some notes about the "tcr" special-purpose register:
2681 - On the 403 and 403GC, SPR 986 is named "tcr", and it controls the
2682 403's programmable interval timer, fixed interval timer, and
2684 - On the 602, SPR 984 is named "tcr", and it controls the 602's
2685 watchdog timer, and nothing else.
2687 Some of the fields are similar between the two, but they're not
2688 compatible with each other. Since the two variants have different
2689 registers, with different numbers, but the same name, we can't
2690 splice the register name to get the SPR number. */
2691 static const struct reg registers_403
[] =
2697 /* 119 */ S(icdbdr
), S(esr
), S(dear
), S(evpr
),
2698 /* 123 */ S(cdbcr
), S(tsr
), SN4(tcr
, ppc_spr_403_tcr
), S(pit
),
2699 /* 127 */ S(tbhi
), S(tblo
), S(srr2
), S(srr3
),
2700 /* 131 */ S(dbsr
), S(dbcr
), S(iac1
), S(iac2
),
2701 /* 135 */ S(dac1
), S(dac2
), S(dccr
), S(iccr
),
2702 /* 139 */ S(pbl1
), S(pbu1
), S(pbl2
), S(pbu2
)
2705 /* IBM PowerPC 403GC.
2706 See the comments about 'tcr' for the 403, above. */
2707 static const struct reg registers_403GC
[] =
2713 /* 119 */ S(icdbdr
), S(esr
), S(dear
), S(evpr
),
2714 /* 123 */ S(cdbcr
), S(tsr
), SN4(tcr
, ppc_spr_403_tcr
), S(pit
),
2715 /* 127 */ S(tbhi
), S(tblo
), S(srr2
), S(srr3
),
2716 /* 131 */ S(dbsr
), S(dbcr
), S(iac1
), S(iac2
),
2717 /* 135 */ S(dac1
), S(dac2
), S(dccr
), S(iccr
),
2718 /* 139 */ S(pbl1
), S(pbu1
), S(pbl2
), S(pbu2
),
2719 /* 143 */ S(zpr
), S(pid
), S(sgr
), S(dcwr
),
2720 /* 147 */ S(tbhu
), S(tblu
)
2723 /* Motorola PowerPC 505. */
2724 static const struct reg registers_505
[] =
2730 /* 119 */ S(eie
), S(eid
), S(nri
)
2733 /* Motorola PowerPC 860 or 850. */
2734 static const struct reg registers_860
[] =
2740 /* 119 */ S(eie
), S(eid
), S(nri
), S(cmpa
),
2741 /* 123 */ S(cmpb
), S(cmpc
), S(cmpd
), S(icr
),
2742 /* 127 */ S(der
), S(counta
), S(countb
), S(cmpe
),
2743 /* 131 */ S(cmpf
), S(cmpg
), S(cmph
), S(lctrl1
),
2744 /* 135 */ S(lctrl2
), S(ictrl
), S(bar
), S(ic_cst
),
2745 /* 139 */ S(ic_adr
), S(ic_dat
), S(dc_cst
), S(dc_adr
),
2746 /* 143 */ S(dc_dat
), S(dpdr
), S(dpir
), S(immr
),
2747 /* 147 */ S(mi_ctr
), S(mi_ap
), S(mi_epn
), S(mi_twc
),
2748 /* 151 */ S(mi_rpn
), S(md_ctr
), S(m_casid
), S(md_ap
),
2749 /* 155 */ S(md_epn
), S(m_twb
), S(md_twc
), S(md_rpn
),
2750 /* 159 */ S(m_tw
), S(mi_dbcam
), S(mi_dbram0
), S(mi_dbram1
),
2751 /* 163 */ S(md_dbcam
), S(md_dbram0
), S(md_dbram1
)
2754 /* Motorola PowerPC 601. Note that the 601 has different register numbers
2755 for reading and writing RTCU and RTCL. However, how one reads and writes a
2756 register is the stub's problem. */
2757 static const struct reg registers_601
[] =
2763 /* 119 */ S(hid0
), S(hid1
), S(iabr
), S(dabr
),
2764 /* 123 */ S(pir
), S(mq
), S(rtcu
), S(rtcl
)
2767 /* Motorola PowerPC 602.
2768 See the notes under the 403 about 'tcr'. */
2769 static const struct reg registers_602
[] =
2775 /* 119 */ S(hid0
), S(hid1
), S(iabr
), R0
,
2776 /* 123 */ R0
, SN4(tcr
, ppc_spr_602_tcr
), S(ibr
), S(esasrr
),
2777 /* 127 */ S(sebr
), S(ser
), S(sp
), S(lt
)
2780 /* Motorola/IBM PowerPC 603 or 603e. */
2781 static const struct reg registers_603
[] =
2787 /* 119 */ S(hid0
), S(hid1
), S(iabr
), R0
,
2788 /* 123 */ R0
, S(dmiss
), S(dcmp
), S(hash1
),
2789 /* 127 */ S(hash2
), S(imiss
), S(icmp
), S(rpa
)
2792 /* Motorola PowerPC 604 or 604e. */
2793 static const struct reg registers_604
[] =
2799 /* 119 */ S(hid0
), S(hid1
), S(iabr
), S(dabr
),
2800 /* 123 */ S(pir
), S(mmcr0
), S(pmc1
), S(pmc2
),
2801 /* 127 */ S(sia
), S(sda
)
2804 /* Motorola/IBM PowerPC 750 or 740. */
2805 static const struct reg registers_750
[] =
2811 /* 119 */ S(hid0
), S(hid1
), S(iabr
), S(dabr
),
2812 /* 123 */ R0
, S(ummcr0
), S(upmc1
), S(upmc2
),
2813 /* 127 */ S(usia
), S(ummcr1
), S(upmc3
), S(upmc4
),
2814 /* 131 */ S(mmcr0
), S(pmc1
), S(pmc2
), S(sia
),
2815 /* 135 */ S(mmcr1
), S(pmc3
), S(pmc4
), S(l2cr
),
2816 /* 139 */ S(ictc
), S(thrm1
), S(thrm2
), S(thrm3
)
2820 /* Motorola PowerPC 7400. */
2821 static const struct reg registers_7400
[] =
2823 /* gpr0-gpr31, fpr0-fpr31 */
2825 /* cr, lr, ctr, xer, fpscr */
2830 /* vr0-vr31, vrsave, vscr */
2832 /* FIXME? Add more registers? */
2835 /* Motorola e500. */
2836 static const struct reg registers_e500
[] =
2838 /* 0 .. 31 */ PPC_SPE_GP_REGS
,
2839 /* 32 .. 63 */ PPC_SPE_UPPER_GP_REGS
,
2840 /* 64 .. 65 */ R(pc
), R(ps
),
2841 /* 66 .. 70 */ PPC_UISA_NOFP_SPRS
,
2842 /* 71 .. 72 */ R8(acc
), S4(spefscr
),
2843 /* NOTE: Add new registers here the end of the raw register
2844 list and just before the first pseudo register. */
2845 /* 73 .. 104 */ PPC_EV_PSEUDO_REGS
2848 /* Information about a particular processor variant. */
2852 /* Name of this variant. */
2855 /* English description of the variant. */
2858 /* bfd_arch_info.arch corresponding to variant. */
2859 enum bfd_architecture arch
;
2861 /* bfd_arch_info.mach corresponding to variant. */
2864 /* Number of real registers. */
2867 /* Number of pseudo registers. */
2870 /* Number of total registers (the sum of nregs and npregs). */
2873 /* Table of register names; registers[R] is the name of the register
2875 const struct reg
*regs
;
2878 #define tot_num_registers(list) (sizeof (list) / sizeof((list)[0]))
2881 num_registers (const struct reg
*reg_list
, int num_tot_regs
)
2886 for (i
= 0; i
< num_tot_regs
; i
++)
2887 if (!reg_list
[i
].pseudo
)
2894 num_pseudo_registers (const struct reg
*reg_list
, int num_tot_regs
)
2899 for (i
= 0; i
< num_tot_regs
; i
++)
2900 if (reg_list
[i
].pseudo
)
2906 /* Information in this table comes from the following web sites:
2907 IBM: http://www.chips.ibm.com:80/products/embedded/
2908 Motorola: http://www.mot.com/SPS/PowerPC/
2910 I'm sure I've got some of the variant descriptions not quite right.
2911 Please report any inaccuracies you find to GDB's maintainer.
2913 If you add entries to this table, please be sure to allow the new
2914 value as an argument to the --with-cpu flag, in configure.in. */
2916 static struct variant variants
[] =
2919 {"powerpc", "PowerPC user-level", bfd_arch_powerpc
,
2920 bfd_mach_ppc
, -1, -1, tot_num_registers (registers_powerpc
),
2922 {"power", "POWER user-level", bfd_arch_rs6000
,
2923 bfd_mach_rs6k
, -1, -1, tot_num_registers (registers_power
),
2925 {"403", "IBM PowerPC 403", bfd_arch_powerpc
,
2926 bfd_mach_ppc_403
, -1, -1, tot_num_registers (registers_403
),
2928 {"601", "Motorola PowerPC 601", bfd_arch_powerpc
,
2929 bfd_mach_ppc_601
, -1, -1, tot_num_registers (registers_601
),
2931 {"602", "Motorola PowerPC 602", bfd_arch_powerpc
,
2932 bfd_mach_ppc_602
, -1, -1, tot_num_registers (registers_602
),
2934 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc
,
2935 bfd_mach_ppc_603
, -1, -1, tot_num_registers (registers_603
),
2937 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc
,
2938 604, -1, -1, tot_num_registers (registers_604
),
2940 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc
,
2941 bfd_mach_ppc_403gc
, -1, -1, tot_num_registers (registers_403GC
),
2943 {"505", "Motorola PowerPC 505", bfd_arch_powerpc
,
2944 bfd_mach_ppc_505
, -1, -1, tot_num_registers (registers_505
),
2946 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc
,
2947 bfd_mach_ppc_860
, -1, -1, tot_num_registers (registers_860
),
2949 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc
,
2950 bfd_mach_ppc_750
, -1, -1, tot_num_registers (registers_750
),
2952 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc
,
2953 bfd_mach_ppc_7400
, -1, -1, tot_num_registers (registers_7400
),
2955 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc
,
2956 bfd_mach_ppc_e500
, -1, -1, tot_num_registers (registers_e500
),
2960 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc
,
2961 bfd_mach_ppc64
, -1, -1, tot_num_registers (registers_powerpc
),
2963 {"620", "Motorola PowerPC 620", bfd_arch_powerpc
,
2964 bfd_mach_ppc_620
, -1, -1, tot_num_registers (registers_powerpc
),
2966 {"630", "Motorola PowerPC 630", bfd_arch_powerpc
,
2967 bfd_mach_ppc_630
, -1, -1, tot_num_registers (registers_powerpc
),
2969 {"a35", "PowerPC A35", bfd_arch_powerpc
,
2970 bfd_mach_ppc_a35
, -1, -1, tot_num_registers (registers_powerpc
),
2972 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc
,
2973 bfd_mach_ppc_rs64ii
, -1, -1, tot_num_registers (registers_powerpc
),
2975 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc
,
2976 bfd_mach_ppc_rs64iii
, -1, -1, tot_num_registers (registers_powerpc
),
2979 /* FIXME: I haven't checked the register sets of the following. */
2980 {"rs1", "IBM POWER RS1", bfd_arch_rs6000
,
2981 bfd_mach_rs6k_rs1
, -1, -1, tot_num_registers (registers_power
),
2983 {"rsc", "IBM POWER RSC", bfd_arch_rs6000
,
2984 bfd_mach_rs6k_rsc
, -1, -1, tot_num_registers (registers_power
),
2986 {"rs2", "IBM POWER RS2", bfd_arch_rs6000
,
2987 bfd_mach_rs6k_rs2
, -1, -1, tot_num_registers (registers_power
),
2990 {0, 0, 0, 0, 0, 0, 0, 0}
2993 /* Initialize the number of registers and pseudo registers in each variant. */
2996 init_variants (void)
3000 for (v
= variants
; v
->name
; v
++)
3003 v
->nregs
= num_registers (v
->regs
, v
->num_tot_regs
);
3004 if (v
->npregs
== -1)
3005 v
->npregs
= num_pseudo_registers (v
->regs
, v
->num_tot_regs
);
3009 /* Return the variant corresponding to architecture ARCH and machine number
3010 MACH. If no such variant exists, return null. */
3012 static const struct variant
*
3013 find_variant_by_arch (enum bfd_architecture arch
, unsigned long mach
)
3015 const struct variant
*v
;
3017 for (v
= variants
; v
->name
; v
++)
3018 if (arch
== v
->arch
&& mach
== v
->mach
)
3025 gdb_print_insn_powerpc (bfd_vma memaddr
, disassemble_info
*info
)
3027 if (!info
->disassembler_options
)
3028 info
->disassembler_options
= "any";
3030 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
3031 return print_insn_big_powerpc (memaddr
, info
);
3033 return print_insn_little_powerpc (memaddr
, info
);
3037 rs6000_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
3039 return frame_unwind_register_unsigned (next_frame
, PC_REGNUM
);
3042 static struct frame_id
3043 rs6000_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
3045 return frame_id_build (frame_unwind_register_unsigned (next_frame
,
3047 frame_pc_unwind (next_frame
));
3050 struct rs6000_frame_cache
3053 CORE_ADDR initial_sp
;
3054 struct trad_frame_saved_reg
*saved_regs
;
3057 static struct rs6000_frame_cache
*
3058 rs6000_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
3060 struct rs6000_frame_cache
*cache
;
3061 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
3062 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3063 struct rs6000_framedata fdata
;
3064 int wordsize
= tdep
->wordsize
;
3067 if ((*this_cache
) != NULL
)
3068 return (*this_cache
);
3069 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
3070 (*this_cache
) = cache
;
3071 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
3073 func
= frame_func_unwind (next_frame
, NORMAL_FRAME
);
3074 pc
= frame_pc_unwind (next_frame
);
3075 skip_prologue (func
, pc
, &fdata
);
3077 /* Figure out the parent's stack pointer. */
3079 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
3080 address of the current frame. Things might be easier if the
3081 ->frame pointed to the outer-most address of the frame. In
3082 the mean time, the address of the prev frame is used as the
3083 base address of this frame. */
3084 cache
->base
= frame_unwind_register_unsigned (next_frame
, SP_REGNUM
);
3086 /* If the function appears to be frameless, check a couple of likely
3087 indicators that we have simply failed to find the frame setup.
3088 Two common cases of this are missing symbols (i.e.
3089 frame_func_unwind returns the wrong address or 0), and assembly
3090 stubs which have a fast exit path but set up a frame on the slow
3093 If the LR appears to return to this function, then presume that
3094 we have an ABI compliant frame that we failed to find. */
3095 if (fdata
.frameless
&& fdata
.lr_offset
== 0)
3100 saved_lr
= frame_unwind_register_unsigned (next_frame
,
3101 tdep
->ppc_lr_regnum
);
3102 if (func
== 0 && saved_lr
== pc
)
3106 CORE_ADDR saved_func
= get_pc_function_start (saved_lr
);
3107 if (func
== saved_func
)
3113 fdata
.frameless
= 0;
3114 fdata
.lr_offset
= tdep
->lr_frame_offset
;
3118 if (!fdata
.frameless
)
3119 /* Frameless really means stackless. */
3120 cache
->base
= read_memory_addr (cache
->base
, wordsize
);
3122 trad_frame_set_value (cache
->saved_regs
, SP_REGNUM
, cache
->base
);
3124 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
3125 All fpr's from saved_fpr to fp31 are saved. */
3127 if (fdata
.saved_fpr
>= 0)
3130 CORE_ADDR fpr_addr
= cache
->base
+ fdata
.fpr_offset
;
3132 /* If skip_prologue says floating-point registers were saved,
3133 but the current architecture has no floating-point registers,
3134 then that's strange. But we have no indices to even record
3135 the addresses under, so we just ignore it. */
3136 if (ppc_floating_point_unit_p (gdbarch
))
3137 for (i
= fdata
.saved_fpr
; i
< ppc_num_fprs
; i
++)
3139 cache
->saved_regs
[tdep
->ppc_fp0_regnum
+ i
].addr
= fpr_addr
;
3144 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
3145 All gpr's from saved_gpr to gpr31 are saved. */
3147 if (fdata
.saved_gpr
>= 0)
3150 CORE_ADDR gpr_addr
= cache
->base
+ fdata
.gpr_offset
;
3151 for (i
= fdata
.saved_gpr
; i
< ppc_num_gprs
; i
++)
3153 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= gpr_addr
;
3154 gpr_addr
+= wordsize
;
3158 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
3159 All vr's from saved_vr to vr31 are saved. */
3160 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
3162 if (fdata
.saved_vr
>= 0)
3165 CORE_ADDR vr_addr
= cache
->base
+ fdata
.vr_offset
;
3166 for (i
= fdata
.saved_vr
; i
< 32; i
++)
3168 cache
->saved_regs
[tdep
->ppc_vr0_regnum
+ i
].addr
= vr_addr
;
3169 vr_addr
+= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
3174 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
3175 All vr's from saved_ev to ev31 are saved. ????? */
3176 if (tdep
->ppc_ev0_regnum
!= -1 && tdep
->ppc_ev31_regnum
!= -1)
3178 if (fdata
.saved_ev
>= 0)
3181 CORE_ADDR ev_addr
= cache
->base
+ fdata
.ev_offset
;
3182 for (i
= fdata
.saved_ev
; i
< ppc_num_gprs
; i
++)
3184 cache
->saved_regs
[tdep
->ppc_ev0_regnum
+ i
].addr
= ev_addr
;
3185 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= ev_addr
+ 4;
3186 ev_addr
+= register_size (gdbarch
, tdep
->ppc_ev0_regnum
);
3191 /* If != 0, fdata.cr_offset is the offset from the frame that
3193 if (fdata
.cr_offset
!= 0)
3194 cache
->saved_regs
[tdep
->ppc_cr_regnum
].addr
= cache
->base
+ fdata
.cr_offset
;
3196 /* If != 0, fdata.lr_offset is the offset from the frame that
3198 if (fdata
.lr_offset
!= 0)
3199 cache
->saved_regs
[tdep
->ppc_lr_regnum
].addr
= cache
->base
+ fdata
.lr_offset
;
3200 /* The PC is found in the link register. */
3201 cache
->saved_regs
[PC_REGNUM
] = cache
->saved_regs
[tdep
->ppc_lr_regnum
];
3203 /* If != 0, fdata.vrsave_offset is the offset from the frame that
3204 holds the VRSAVE. */
3205 if (fdata
.vrsave_offset
!= 0)
3206 cache
->saved_regs
[tdep
->ppc_vrsave_regnum
].addr
= cache
->base
+ fdata
.vrsave_offset
;
3208 if (fdata
.alloca_reg
< 0)
3209 /* If no alloca register used, then fi->frame is the value of the
3210 %sp for this frame, and it is good enough. */
3211 cache
->initial_sp
= frame_unwind_register_unsigned (next_frame
, SP_REGNUM
);
3213 cache
->initial_sp
= frame_unwind_register_unsigned (next_frame
,
3220 rs6000_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
3221 struct frame_id
*this_id
)
3223 struct rs6000_frame_cache
*info
= rs6000_frame_cache (next_frame
,
3225 (*this_id
) = frame_id_build (info
->base
,
3226 frame_func_unwind (next_frame
, NORMAL_FRAME
));
3230 rs6000_frame_prev_register (struct frame_info
*next_frame
,
3232 int regnum
, int *optimizedp
,
3233 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
3234 int *realnump
, gdb_byte
*valuep
)
3236 struct rs6000_frame_cache
*info
= rs6000_frame_cache (next_frame
,
3238 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
3239 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
3242 static const struct frame_unwind rs6000_frame_unwind
=
3245 rs6000_frame_this_id
,
3246 rs6000_frame_prev_register
3249 static const struct frame_unwind
*
3250 rs6000_frame_sniffer (struct frame_info
*next_frame
)
3252 return &rs6000_frame_unwind
;
3258 rs6000_frame_base_address (struct frame_info
*next_frame
,
3261 struct rs6000_frame_cache
*info
= rs6000_frame_cache (next_frame
,
3263 return info
->initial_sp
;
3266 static const struct frame_base rs6000_frame_base
= {
3267 &rs6000_frame_unwind
,
3268 rs6000_frame_base_address
,
3269 rs6000_frame_base_address
,
3270 rs6000_frame_base_address
3273 static const struct frame_base
*
3274 rs6000_frame_base_sniffer (struct frame_info
*next_frame
)
3276 return &rs6000_frame_base
;
3279 /* Initialize the current architecture based on INFO. If possible, re-use an
3280 architecture from ARCHES, which is a list of architectures already created
3281 during this debugging session.
3283 Called e.g. at program startup, when reading a core file, and when reading
3286 static struct gdbarch
*
3287 rs6000_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
3289 struct gdbarch
*gdbarch
;
3290 struct gdbarch_tdep
*tdep
;
3291 int wordsize
, from_xcoff_exec
, from_elf_exec
, i
, off
;
3293 const struct variant
*v
;
3294 enum bfd_architecture arch
;
3300 from_xcoff_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
3301 bfd_get_flavour (info
.abfd
) == bfd_target_xcoff_flavour
;
3303 from_elf_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
3304 bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
;
3306 sysv_abi
= info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
;
3308 /* Check word size. If INFO is from a binary file, infer it from
3309 that, else choose a likely default. */
3310 if (from_xcoff_exec
)
3312 if (bfd_xcoff_is_xcoff64 (info
.abfd
))
3317 else if (from_elf_exec
)
3319 if (elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
3326 if (info
.bfd_arch_info
!= NULL
&& info
.bfd_arch_info
->bits_per_word
!= 0)
3327 wordsize
= info
.bfd_arch_info
->bits_per_word
/
3328 info
.bfd_arch_info
->bits_per_byte
;
3333 /* Find a candidate among extant architectures. */
3334 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
3336 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
3338 /* Word size in the various PowerPC bfd_arch_info structs isn't
3339 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
3340 separate word size check. */
3341 tdep
= gdbarch_tdep (arches
->gdbarch
);
3342 if (tdep
&& tdep
->wordsize
== wordsize
)
3343 return arches
->gdbarch
;
3346 /* None found, create a new architecture from INFO, whose bfd_arch_info
3347 validity depends on the source:
3348 - executable useless
3349 - rs6000_host_arch() good
3351 - "set arch" trust blindly
3352 - GDB startup useless but harmless */
3354 if (!from_xcoff_exec
)
3356 arch
= info
.bfd_arch_info
->arch
;
3357 mach
= info
.bfd_arch_info
->mach
;
3361 arch
= bfd_arch_powerpc
;
3362 bfd_default_set_arch_mach (&abfd
, arch
, 0);
3363 info
.bfd_arch_info
= bfd_get_arch_info (&abfd
);
3364 mach
= info
.bfd_arch_info
->mach
;
3366 tdep
= xmalloc (sizeof (struct gdbarch_tdep
));
3367 tdep
->wordsize
= wordsize
;
3369 /* For e500 executables, the apuinfo section is of help here. Such
3370 section contains the identifier and revision number of each
3371 Application-specific Processing Unit that is present on the
3372 chip. The content of the section is determined by the assembler
3373 which looks at each instruction and determines which unit (and
3374 which version of it) can execute it. In our case we just look for
3375 the existance of the section. */
3379 sect
= bfd_get_section_by_name (info
.abfd
, ".PPC.EMB.apuinfo");
3382 arch
= info
.bfd_arch_info
->arch
;
3383 mach
= bfd_mach_ppc_e500
;
3384 bfd_default_set_arch_mach (&abfd
, arch
, mach
);
3385 info
.bfd_arch_info
= bfd_get_arch_info (&abfd
);
3389 gdbarch
= gdbarch_alloc (&info
, tdep
);
3391 /* Initialize the number of real and pseudo registers in each variant. */
3394 /* Choose variant. */
3395 v
= find_variant_by_arch (arch
, mach
);
3399 tdep
->regs
= v
->regs
;
3401 tdep
->ppc_gp0_regnum
= 0;
3402 tdep
->ppc_toc_regnum
= 2;
3403 tdep
->ppc_ps_regnum
= 65;
3404 tdep
->ppc_cr_regnum
= 66;
3405 tdep
->ppc_lr_regnum
= 67;
3406 tdep
->ppc_ctr_regnum
= 68;
3407 tdep
->ppc_xer_regnum
= 69;
3408 if (v
->mach
== bfd_mach_ppc_601
)
3409 tdep
->ppc_mq_regnum
= 124;
3410 else if (arch
== bfd_arch_rs6000
)
3411 tdep
->ppc_mq_regnum
= 70;
3413 tdep
->ppc_mq_regnum
= -1;
3414 tdep
->ppc_fp0_regnum
= 32;
3415 tdep
->ppc_fpscr_regnum
= (arch
== bfd_arch_rs6000
) ? 71 : 70;
3416 tdep
->ppc_sr0_regnum
= 71;
3417 tdep
->ppc_vr0_regnum
= -1;
3418 tdep
->ppc_vrsave_regnum
= -1;
3419 tdep
->ppc_ev0_upper_regnum
= -1;
3420 tdep
->ppc_ev0_regnum
= -1;
3421 tdep
->ppc_ev31_regnum
= -1;
3422 tdep
->ppc_acc_regnum
= -1;
3423 tdep
->ppc_spefscr_regnum
= -1;
3425 set_gdbarch_pc_regnum (gdbarch
, 64);
3426 set_gdbarch_sp_regnum (gdbarch
, 1);
3427 set_gdbarch_deprecated_fp_regnum (gdbarch
, 1);
3428 set_gdbarch_fp0_regnum (gdbarch
, 32);
3429 set_gdbarch_register_sim_regno (gdbarch
, rs6000_register_sim_regno
);
3430 if (sysv_abi
&& wordsize
== 8)
3431 set_gdbarch_return_value (gdbarch
, ppc64_sysv_abi_return_value
);
3432 else if (sysv_abi
&& wordsize
== 4)
3433 set_gdbarch_return_value (gdbarch
, ppc_sysv_abi_return_value
);
3435 set_gdbarch_return_value (gdbarch
, rs6000_return_value
);
3437 /* Set lr_frame_offset. */
3439 tdep
->lr_frame_offset
= 16;
3441 tdep
->lr_frame_offset
= 4;
3443 tdep
->lr_frame_offset
= 8;
3445 if (v
->arch
== bfd_arch_rs6000
)
3446 tdep
->ppc_sr0_regnum
= -1;
3447 else if (v
->arch
== bfd_arch_powerpc
)
3451 tdep
->ppc_sr0_regnum
= -1;
3452 tdep
->ppc_vr0_regnum
= 71;
3453 tdep
->ppc_vrsave_regnum
= 104;
3455 case bfd_mach_ppc_7400
:
3456 tdep
->ppc_vr0_regnum
= 119;
3457 tdep
->ppc_vrsave_regnum
= 152;
3459 case bfd_mach_ppc_e500
:
3460 tdep
->ppc_toc_regnum
= -1;
3461 tdep
->ppc_ev0_upper_regnum
= 32;
3462 tdep
->ppc_ev0_regnum
= 73;
3463 tdep
->ppc_ev31_regnum
= 104;
3464 tdep
->ppc_acc_regnum
= 71;
3465 tdep
->ppc_spefscr_regnum
= 72;
3466 tdep
->ppc_fp0_regnum
= -1;
3467 tdep
->ppc_fpscr_regnum
= -1;
3468 tdep
->ppc_sr0_regnum
= -1;
3469 set_gdbarch_pseudo_register_read (gdbarch
, e500_pseudo_register_read
);
3470 set_gdbarch_pseudo_register_write (gdbarch
, e500_pseudo_register_write
);
3471 set_gdbarch_register_reggroup_p (gdbarch
, e500_register_reggroup_p
);
3474 case bfd_mach_ppc64
:
3475 case bfd_mach_ppc_620
:
3476 case bfd_mach_ppc_630
:
3477 case bfd_mach_ppc_a35
:
3478 case bfd_mach_ppc_rs64ii
:
3479 case bfd_mach_ppc_rs64iii
:
3480 /* These processor's register sets don't have segment registers. */
3481 tdep
->ppc_sr0_regnum
= -1;
3485 internal_error (__FILE__
, __LINE__
,
3486 _("rs6000_gdbarch_init: "
3487 "received unexpected BFD 'arch' value"));
3489 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
3491 /* Sanity check on registers. */
3492 gdb_assert (strcmp (tdep
->regs
[tdep
->ppc_gp0_regnum
].name
, "r0") == 0);
3494 /* Select instruction printer. */
3495 if (arch
== bfd_arch_rs6000
)
3496 set_gdbarch_print_insn (gdbarch
, print_insn_rs6000
);
3498 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_powerpc
);
3500 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
3502 set_gdbarch_num_regs (gdbarch
, v
->nregs
);
3503 set_gdbarch_num_pseudo_regs (gdbarch
, v
->npregs
);
3504 set_gdbarch_register_name (gdbarch
, rs6000_register_name
);
3505 set_gdbarch_register_type (gdbarch
, rs6000_register_type
);
3506 set_gdbarch_register_reggroup_p (gdbarch
, rs6000_register_reggroup_p
);
3508 set_gdbarch_ptr_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
3509 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
3510 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
3511 set_gdbarch_long_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
3512 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
3513 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
3514 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
3516 set_gdbarch_long_double_bit (gdbarch
, 16 * TARGET_CHAR_BIT
);
3518 set_gdbarch_long_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
3519 set_gdbarch_char_signed (gdbarch
, 0);
3521 set_gdbarch_frame_align (gdbarch
, rs6000_frame_align
);
3522 if (sysv_abi
&& wordsize
== 8)
3524 set_gdbarch_frame_red_zone_size (gdbarch
, 288);
3525 else if (!sysv_abi
&& wordsize
== 4)
3526 /* PowerOpen / AIX 32 bit. The saved area or red zone consists of
3527 19 4 byte GPRS + 18 8 byte FPRs giving a total of 220 bytes.
3528 Problem is, 220 isn't frame (16 byte) aligned. Round it up to
3530 set_gdbarch_frame_red_zone_size (gdbarch
, 224);
3532 set_gdbarch_convert_register_p (gdbarch
, rs6000_convert_register_p
);
3533 set_gdbarch_register_to_value (gdbarch
, rs6000_register_to_value
);
3534 set_gdbarch_value_to_register (gdbarch
, rs6000_value_to_register
);
3536 set_gdbarch_stab_reg_to_regnum (gdbarch
, rs6000_stab_reg_to_regnum
);
3537 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, rs6000_dwarf2_reg_to_regnum
);
3539 if (sysv_abi
&& wordsize
== 4)
3540 set_gdbarch_push_dummy_call (gdbarch
, ppc_sysv_abi_push_dummy_call
);
3541 else if (sysv_abi
&& wordsize
== 8)
3542 set_gdbarch_push_dummy_call (gdbarch
, ppc64_sysv_abi_push_dummy_call
);
3544 set_gdbarch_push_dummy_call (gdbarch
, rs6000_push_dummy_call
);
3546 set_gdbarch_skip_prologue (gdbarch
, rs6000_skip_prologue
);
3547 set_gdbarch_in_function_epilogue_p (gdbarch
, rs6000_in_function_epilogue_p
);
3549 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3550 set_gdbarch_breakpoint_from_pc (gdbarch
, rs6000_breakpoint_from_pc
);
3552 /* Handles single stepping of atomic sequences. */
3553 set_gdbarch_software_single_step (gdbarch
, deal_with_atomic_sequence
);
3555 /* Handle the 64-bit SVR4 minimal-symbol convention of using "FN"
3556 for the descriptor and ".FN" for the entry-point -- a user
3557 specifying "break FN" will unexpectedly end up with a breakpoint
3558 on the descriptor and not the function. This architecture method
3559 transforms any breakpoints on descriptors into breakpoints on the
3560 corresponding entry point. */
3561 if (sysv_abi
&& wordsize
== 8)
3562 set_gdbarch_adjust_breakpoint_address (gdbarch
, ppc64_sysv_abi_adjust_breakpoint_address
);
3564 /* Not sure on this. FIXMEmgo */
3565 set_gdbarch_frame_args_skip (gdbarch
, 8);
3569 /* Handle RS/6000 function pointers (which are really function
3571 set_gdbarch_convert_from_func_ptr_addr (gdbarch
,
3572 rs6000_convert_from_func_ptr_addr
);
3575 /* Helpers for function argument information. */
3576 set_gdbarch_fetch_pointer_argument (gdbarch
, rs6000_fetch_pointer_argument
);
3579 set_gdbarch_in_solib_return_trampoline
3580 (gdbarch
, rs6000_in_solib_return_trampoline
);
3581 set_gdbarch_skip_trampoline_code (gdbarch
, rs6000_skip_trampoline_code
);
3583 /* Hook in the DWARF CFI frame unwinder. */
3584 frame_unwind_append_sniffer (gdbarch
, dwarf2_frame_sniffer
);
3585 dwarf2_frame_set_adjust_regnum (gdbarch
, rs6000_adjust_frame_regnum
);
3587 /* Hook in ABI-specific overrides, if they have been registered. */
3588 gdbarch_init_osabi (info
, gdbarch
);
3592 case GDB_OSABI_LINUX
:
3593 /* FIXME: pgilliam/2005-10-21: Assume all PowerPC 64-bit linux systems
3594 have altivec registers. If not, ptrace will fail the first time it's
3595 called to access one and will not be called again. This wart will
3596 be removed when Daniel Jacobowitz's proposal for autodetecting target
3597 registers is implemented. */
3598 if ((v
->arch
== bfd_arch_powerpc
) && ((v
->mach
)== bfd_mach_ppc64
))
3600 tdep
->ppc_vr0_regnum
= 71;
3601 tdep
->ppc_vrsave_regnum
= 104;
3604 case GDB_OSABI_NETBSD_AOUT
:
3605 case GDB_OSABI_NETBSD_ELF
:
3606 case GDB_OSABI_UNKNOWN
:
3607 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
3608 frame_unwind_append_sniffer (gdbarch
, rs6000_frame_sniffer
);
3609 set_gdbarch_unwind_dummy_id (gdbarch
, rs6000_unwind_dummy_id
);
3610 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
3613 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
3615 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
3616 frame_unwind_append_sniffer (gdbarch
, rs6000_frame_sniffer
);
3617 set_gdbarch_unwind_dummy_id (gdbarch
, rs6000_unwind_dummy_id
);
3618 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
3621 init_sim_regno_table (gdbarch
);
3627 rs6000_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
3629 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3634 /* FIXME: Dump gdbarch_tdep. */
3637 /* Initialization code. */
3639 extern initialize_file_ftype _initialize_rs6000_tdep
; /* -Wmissing-prototypes */
3642 _initialize_rs6000_tdep (void)
3644 gdbarch_register (bfd_arch_rs6000
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
3645 gdbarch_register (bfd_arch_powerpc
, rs6000_gdbarch_init
, rs6000_dump_tdep
);