1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 1986-2021 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
29 #include "arch-utils.h"
32 #include "target-float.h"
34 #include "parser-defs.h"
37 #include "sim-regno.h"
38 #include "gdb/sim-ppc.h"
39 #include "reggroups.h"
40 #include "dwarf2/frame.h"
41 #include "target-descriptions.h"
42 #include "user-regs.h"
43 #include "record-full.h"
46 #include "coff/internal.h" /* for libcoff.h */
47 #include "libcoff.h" /* for xcoff_data */
48 #include "coff/xcoff.h"
53 #include "elf/ppc64.h"
55 #include "solib-svr4.h"
57 #include "ppc-ravenscar-thread.h"
61 #include "trad-frame.h"
62 #include "frame-unwind.h"
63 #include "frame-base.h"
69 #include "features/rs6000/powerpc-32.c"
70 #include "features/rs6000/powerpc-altivec32.c"
71 #include "features/rs6000/powerpc-vsx32.c"
72 #include "features/rs6000/powerpc-403.c"
73 #include "features/rs6000/powerpc-403gc.c"
74 #include "features/rs6000/powerpc-405.c"
75 #include "features/rs6000/powerpc-505.c"
76 #include "features/rs6000/powerpc-601.c"
77 #include "features/rs6000/powerpc-602.c"
78 #include "features/rs6000/powerpc-603.c"
79 #include "features/rs6000/powerpc-604.c"
80 #include "features/rs6000/powerpc-64.c"
81 #include "features/rs6000/powerpc-altivec64.c"
82 #include "features/rs6000/powerpc-vsx64.c"
83 #include "features/rs6000/powerpc-7400.c"
84 #include "features/rs6000/powerpc-750.c"
85 #include "features/rs6000/powerpc-860.c"
86 #include "features/rs6000/powerpc-e500.c"
87 #include "features/rs6000/rs6000.c"
89 /* Determine if regnum is an SPE pseudo-register. */
90 #define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \
91 && (regnum) >= (tdep)->ppc_ev0_regnum \
92 && (regnum) < (tdep)->ppc_ev0_regnum + 32)
94 /* Determine if regnum is a decimal float pseudo-register. */
95 #define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \
96 && (regnum) >= (tdep)->ppc_dl0_regnum \
97 && (regnum) < (tdep)->ppc_dl0_regnum + 16)
99 /* Determine if regnum is a "vX" alias for the raw "vrX" vector
101 #define IS_V_ALIAS_PSEUDOREG(tdep, regnum) (\
102 (tdep)->ppc_v0_alias_regnum >= 0 \
103 && (regnum) >= (tdep)->ppc_v0_alias_regnum \
104 && (regnum) < (tdep)->ppc_v0_alias_regnum + ppc_num_vrs)
106 /* Determine if regnum is a POWER7 VSX register. */
107 #define IS_VSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_vsr0_regnum >= 0 \
108 && (regnum) >= (tdep)->ppc_vsr0_regnum \
109 && (regnum) < (tdep)->ppc_vsr0_regnum + ppc_num_vsrs)
111 /* Determine if regnum is a POWER7 Extended FP register. */
112 #define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \
113 && (regnum) >= (tdep)->ppc_efpr0_regnum \
114 && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_efprs)
116 /* Determine if regnum is a checkpointed decimal float
118 #define IS_CDFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_cdl0_regnum >= 0 \
119 && (regnum) >= (tdep)->ppc_cdl0_regnum \
120 && (regnum) < (tdep)->ppc_cdl0_regnum + 16)
122 /* Determine if regnum is a Checkpointed POWER7 VSX register. */
123 #define IS_CVSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_cvsr0_regnum >= 0 \
124 && (regnum) >= (tdep)->ppc_cvsr0_regnum \
125 && (regnum) < (tdep)->ppc_cvsr0_regnum + ppc_num_vsrs)
127 /* Determine if regnum is a Checkpointed POWER7 Extended FP register. */
128 #define IS_CEFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_cefpr0_regnum >= 0 \
129 && (regnum) >= (tdep)->ppc_cefpr0_regnum \
130 && (regnum) < (tdep)->ppc_cefpr0_regnum + ppc_num_efprs)
132 /* Holds the current set of options to be passed to the disassembler. */
133 static char *powerpc_disassembler_options
;
135 /* The list of available "set powerpc ..." and "show powerpc ..."
137 static struct cmd_list_element
*setpowerpccmdlist
= NULL
;
138 static struct cmd_list_element
*showpowerpccmdlist
= NULL
;
140 static enum auto_boolean powerpc_soft_float_global
= AUTO_BOOLEAN_AUTO
;
142 /* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */
143 static const char *const powerpc_vector_strings
[] =
152 /* A variable that can be configured by the user. */
153 static enum powerpc_vector_abi powerpc_vector_abi_global
= POWERPC_VEC_AUTO
;
154 static const char *powerpc_vector_abi_string
= "auto";
156 /* PowerPC-related per-inferior data. */
158 struct ppc_inferior_data
160 /* This is an optional in case we add more fields to ppc_inferior_data, we
161 don't want it instantiated as soon as we get the ppc_inferior_data for an
163 gdb::optional
<displaced_step_buffers
> disp_step_buf
;
166 static inferior_key
<ppc_inferior_data
> ppc_inferior_data_key
;
168 /* Get the per-inferior PowerPC data for INF. */
170 static ppc_inferior_data
*
171 get_ppc_per_inferior (inferior
*inf
)
173 ppc_inferior_data
*per_inf
= ppc_inferior_data_key
.get (inf
);
175 if (per_inf
== nullptr)
176 per_inf
= ppc_inferior_data_key
.emplace (inf
);
181 /* To be used by skip_prologue. */
183 struct rs6000_framedata
185 int offset
; /* total size of frame --- the distance
186 by which we decrement sp to allocate
188 int saved_gpr
; /* smallest # of saved gpr */
189 unsigned int gpr_mask
; /* Each bit is an individual saved GPR. */
190 int saved_fpr
; /* smallest # of saved fpr */
191 int saved_vr
; /* smallest # of saved vr */
192 int saved_ev
; /* smallest # of saved ev */
193 int alloca_reg
; /* alloca register number (frame ptr) */
194 char frameless
; /* true if frameless functions. */
195 char nosavedpc
; /* true if pc not saved. */
196 char used_bl
; /* true if link register clobbered */
197 int gpr_offset
; /* offset of saved gprs from prev sp */
198 int fpr_offset
; /* offset of saved fprs from prev sp */
199 int vr_offset
; /* offset of saved vrs from prev sp */
200 int ev_offset
; /* offset of saved evs from prev sp */
201 int lr_offset
; /* offset of saved lr */
202 int lr_register
; /* register of saved lr, if trustworthy */
203 int cr_offset
; /* offset of saved cr */
204 int vrsave_offset
; /* offset of saved vrsave register */
208 /* Is REGNO a VSX register? Return 1 if so, 0 otherwise. */
210 vsx_register_p (struct gdbarch
*gdbarch
, int regno
)
212 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
213 if (tdep
->ppc_vsr0_regnum
< 0)
216 return (regno
>= tdep
->ppc_vsr0_upper_regnum
&& regno
217 <= tdep
->ppc_vsr0_upper_regnum
+ 31);
220 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
222 altivec_register_p (struct gdbarch
*gdbarch
, int regno
)
224 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
225 if (tdep
->ppc_vr0_regnum
< 0 || tdep
->ppc_vrsave_regnum
< 0)
228 return (regno
>= tdep
->ppc_vr0_regnum
&& regno
<= tdep
->ppc_vrsave_regnum
);
232 /* Return true if REGNO is an SPE register, false otherwise. */
234 spe_register_p (struct gdbarch
*gdbarch
, int regno
)
236 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
238 /* Is it a reference to EV0 -- EV31, and do we have those? */
239 if (IS_SPE_PSEUDOREG (tdep
, regno
))
242 /* Is it a reference to one of the raw upper GPR halves? */
243 if (tdep
->ppc_ev0_upper_regnum
>= 0
244 && tdep
->ppc_ev0_upper_regnum
<= regno
245 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
248 /* Is it a reference to the 64-bit accumulator, and do we have that? */
249 if (tdep
->ppc_acc_regnum
>= 0
250 && tdep
->ppc_acc_regnum
== regno
)
253 /* Is it a reference to the SPE floating-point status and control register,
254 and do we have that? */
255 if (tdep
->ppc_spefscr_regnum
>= 0
256 && tdep
->ppc_spefscr_regnum
== regno
)
263 /* Return non-zero if the architecture described by GDBARCH has
264 floating-point registers (f0 --- f31 and fpscr). */
266 ppc_floating_point_unit_p (struct gdbarch
*gdbarch
)
268 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
270 return (tdep
->ppc_fp0_regnum
>= 0
271 && tdep
->ppc_fpscr_regnum
>= 0);
274 /* Return non-zero if the architecture described by GDBARCH has
275 Altivec registers (vr0 --- vr31, vrsave and vscr). */
277 ppc_altivec_support_p (struct gdbarch
*gdbarch
)
279 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
281 return (tdep
->ppc_vr0_regnum
>= 0
282 && tdep
->ppc_vrsave_regnum
>= 0);
285 /* Check that TABLE[GDB_REGNO] is not already initialized, and then
288 This is a helper function for init_sim_regno_table, constructing
289 the table mapping GDB register numbers to sim register numbers; we
290 initialize every element in that table to -1 before we start
293 set_sim_regno (int *table
, int gdb_regno
, int sim_regno
)
295 /* Make sure we don't try to assign any given GDB register a sim
296 register number more than once. */
297 gdb_assert (table
[gdb_regno
] == -1);
298 table
[gdb_regno
] = sim_regno
;
302 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
303 numbers to simulator register numbers, based on the values placed
304 in the ARCH->tdep->ppc_foo_regnum members. */
306 init_sim_regno_table (struct gdbarch
*arch
)
308 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
309 int total_regs
= gdbarch_num_regs (arch
);
310 int *sim_regno
= GDBARCH_OBSTACK_CALLOC (arch
, total_regs
, int);
312 static const char *const segment_regs
[] = {
313 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
314 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
317 /* Presume that all registers not explicitly mentioned below are
318 unavailable from the sim. */
319 for (i
= 0; i
< total_regs
; i
++)
322 /* General-purpose registers. */
323 for (i
= 0; i
< ppc_num_gprs
; i
++)
324 set_sim_regno (sim_regno
, tdep
->ppc_gp0_regnum
+ i
, sim_ppc_r0_regnum
+ i
);
326 /* Floating-point registers. */
327 if (tdep
->ppc_fp0_regnum
>= 0)
328 for (i
= 0; i
< ppc_num_fprs
; i
++)
329 set_sim_regno (sim_regno
,
330 tdep
->ppc_fp0_regnum
+ i
,
331 sim_ppc_f0_regnum
+ i
);
332 if (tdep
->ppc_fpscr_regnum
>= 0)
333 set_sim_regno (sim_regno
, tdep
->ppc_fpscr_regnum
, sim_ppc_fpscr_regnum
);
335 set_sim_regno (sim_regno
, gdbarch_pc_regnum (arch
), sim_ppc_pc_regnum
);
336 set_sim_regno (sim_regno
, tdep
->ppc_ps_regnum
, sim_ppc_ps_regnum
);
337 set_sim_regno (sim_regno
, tdep
->ppc_cr_regnum
, sim_ppc_cr_regnum
);
339 /* Segment registers. */
340 for (i
= 0; i
< ppc_num_srs
; i
++)
344 gdb_regno
= user_reg_map_name_to_regnum (arch
, segment_regs
[i
], -1);
346 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_sr0_regnum
+ i
);
349 /* Altivec registers. */
350 if (tdep
->ppc_vr0_regnum
>= 0)
352 for (i
= 0; i
< ppc_num_vrs
; i
++)
353 set_sim_regno (sim_regno
,
354 tdep
->ppc_vr0_regnum
+ i
,
355 sim_ppc_vr0_regnum
+ i
);
357 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
358 we can treat this more like the other cases. */
359 set_sim_regno (sim_regno
,
360 tdep
->ppc_vr0_regnum
+ ppc_num_vrs
,
361 sim_ppc_vscr_regnum
);
363 /* vsave is a special-purpose register, so the code below handles it. */
365 /* SPE APU (E500) registers. */
366 if (tdep
->ppc_ev0_upper_regnum
>= 0)
367 for (i
= 0; i
< ppc_num_gprs
; i
++)
368 set_sim_regno (sim_regno
,
369 tdep
->ppc_ev0_upper_regnum
+ i
,
370 sim_ppc_rh0_regnum
+ i
);
371 if (tdep
->ppc_acc_regnum
>= 0)
372 set_sim_regno (sim_regno
, tdep
->ppc_acc_regnum
, sim_ppc_acc_regnum
);
373 /* spefscr is a special-purpose register, so the code below handles it. */
376 /* Now handle all special-purpose registers. Verify that they
377 haven't mistakenly been assigned numbers by any of the above
379 for (i
= 0; i
< sim_ppc_num_sprs
; i
++)
381 const char *spr_name
= sim_spr_register_name (i
);
384 if (spr_name
!= NULL
)
385 gdb_regno
= user_reg_map_name_to_regnum (arch
, spr_name
, -1);
388 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_spr0_regnum
+ i
);
392 /* Drop the initialized array into place. */
393 tdep
->sim_regno
= sim_regno
;
397 /* Given a GDB register number REG, return the corresponding SIM
400 rs6000_register_sim_regno (struct gdbarch
*gdbarch
, int reg
)
402 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
405 if (tdep
->sim_regno
== NULL
)
406 init_sim_regno_table (gdbarch
);
408 gdb_assert (0 <= reg
&& reg
<= gdbarch_num_cooked_regs (gdbarch
));
409 sim_regno
= tdep
->sim_regno
[reg
];
414 return LEGACY_SIM_REGNO_IGNORE
;
419 /* Register set support functions. */
421 /* REGS + OFFSET contains register REGNUM in a field REGSIZE wide.
422 Write the register to REGCACHE. */
425 ppc_supply_reg (struct regcache
*regcache
, int regnum
,
426 const gdb_byte
*regs
, size_t offset
, int regsize
)
428 if (regnum
!= -1 && offset
!= -1)
432 struct gdbarch
*gdbarch
= regcache
->arch ();
433 int gdb_regsize
= register_size (gdbarch
, regnum
);
434 if (gdb_regsize
< regsize
435 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
436 offset
+= regsize
- gdb_regsize
;
438 regcache
->raw_supply (regnum
, regs
+ offset
);
442 /* Read register REGNUM from REGCACHE and store to REGS + OFFSET
443 in a field REGSIZE wide. Zero pad as necessary. */
446 ppc_collect_reg (const struct regcache
*regcache
, int regnum
,
447 gdb_byte
*regs
, size_t offset
, int regsize
)
449 if (regnum
!= -1 && offset
!= -1)
453 struct gdbarch
*gdbarch
= regcache
->arch ();
454 int gdb_regsize
= register_size (gdbarch
, regnum
);
455 if (gdb_regsize
< regsize
)
457 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
459 memset (regs
+ offset
, 0, regsize
- gdb_regsize
);
460 offset
+= regsize
- gdb_regsize
;
463 memset (regs
+ offset
+ regsize
- gdb_regsize
, 0,
464 regsize
- gdb_regsize
);
467 regcache
->raw_collect (regnum
, regs
+ offset
);
472 ppc_greg_offset (struct gdbarch
*gdbarch
,
473 struct gdbarch_tdep
*tdep
,
474 const struct ppc_reg_offsets
*offsets
,
478 *regsize
= offsets
->gpr_size
;
479 if (regnum
>= tdep
->ppc_gp0_regnum
480 && regnum
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
)
481 return (offsets
->r0_offset
482 + (regnum
- tdep
->ppc_gp0_regnum
) * offsets
->gpr_size
);
484 if (regnum
== gdbarch_pc_regnum (gdbarch
))
485 return offsets
->pc_offset
;
487 if (regnum
== tdep
->ppc_ps_regnum
)
488 return offsets
->ps_offset
;
490 if (regnum
== tdep
->ppc_lr_regnum
)
491 return offsets
->lr_offset
;
493 if (regnum
== tdep
->ppc_ctr_regnum
)
494 return offsets
->ctr_offset
;
496 *regsize
= offsets
->xr_size
;
497 if (regnum
== tdep
->ppc_cr_regnum
)
498 return offsets
->cr_offset
;
500 if (regnum
== tdep
->ppc_xer_regnum
)
501 return offsets
->xer_offset
;
503 if (regnum
== tdep
->ppc_mq_regnum
)
504 return offsets
->mq_offset
;
510 ppc_fpreg_offset (struct gdbarch_tdep
*tdep
,
511 const struct ppc_reg_offsets
*offsets
,
514 if (regnum
>= tdep
->ppc_fp0_regnum
515 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
)
516 return offsets
->f0_offset
+ (regnum
- tdep
->ppc_fp0_regnum
) * 8;
518 if (regnum
== tdep
->ppc_fpscr_regnum
)
519 return offsets
->fpscr_offset
;
524 /* Supply register REGNUM in the general-purpose register set REGSET
525 from the buffer specified by GREGS and LEN to register cache
526 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
529 ppc_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
530 int regnum
, const void *gregs
, size_t len
)
532 struct gdbarch
*gdbarch
= regcache
->arch ();
533 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
534 const struct ppc_reg_offsets
*offsets
535 = (const struct ppc_reg_offsets
*) regset
->regmap
;
542 int gpr_size
= offsets
->gpr_size
;
544 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
545 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
546 i
++, offset
+= gpr_size
)
547 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) gregs
, offset
,
550 ppc_supply_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
551 (const gdb_byte
*) gregs
, offsets
->pc_offset
, gpr_size
);
552 ppc_supply_reg (regcache
, tdep
->ppc_ps_regnum
,
553 (const gdb_byte
*) gregs
, offsets
->ps_offset
, gpr_size
);
554 ppc_supply_reg (regcache
, tdep
->ppc_lr_regnum
,
555 (const gdb_byte
*) gregs
, offsets
->lr_offset
, gpr_size
);
556 ppc_supply_reg (regcache
, tdep
->ppc_ctr_regnum
,
557 (const gdb_byte
*) gregs
, offsets
->ctr_offset
, gpr_size
);
558 ppc_supply_reg (regcache
, tdep
->ppc_cr_regnum
,
559 (const gdb_byte
*) gregs
, offsets
->cr_offset
,
561 ppc_supply_reg (regcache
, tdep
->ppc_xer_regnum
,
562 (const gdb_byte
*) gregs
, offsets
->xer_offset
,
564 ppc_supply_reg (regcache
, tdep
->ppc_mq_regnum
,
565 (const gdb_byte
*) gregs
, offsets
->mq_offset
,
570 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
571 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) gregs
, offset
, regsize
);
574 /* Supply register REGNUM in the floating-point register set REGSET
575 from the buffer specified by FPREGS and LEN to register cache
576 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
579 ppc_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
580 int regnum
, const void *fpregs
, size_t len
)
582 struct gdbarch
*gdbarch
= regcache
->arch ();
583 struct gdbarch_tdep
*tdep
;
584 const struct ppc_reg_offsets
*offsets
;
587 if (!ppc_floating_point_unit_p (gdbarch
))
590 tdep
= gdbarch_tdep (gdbarch
);
591 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
596 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
597 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
599 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) fpregs
, offset
, 8);
601 ppc_supply_reg (regcache
, tdep
->ppc_fpscr_regnum
,
602 (const gdb_byte
*) fpregs
, offsets
->fpscr_offset
,
603 offsets
->fpscr_size
);
607 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
608 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) fpregs
, offset
,
609 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
612 /* Collect register REGNUM in the general-purpose register set
613 REGSET from register cache REGCACHE into the buffer specified by
614 GREGS and LEN. If REGNUM is -1, do this for all registers in
618 ppc_collect_gregset (const struct regset
*regset
,
619 const struct regcache
*regcache
,
620 int regnum
, void *gregs
, size_t len
)
622 struct gdbarch
*gdbarch
= regcache
->arch ();
623 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
624 const struct ppc_reg_offsets
*offsets
625 = (const struct ppc_reg_offsets
*) regset
->regmap
;
632 int gpr_size
= offsets
->gpr_size
;
634 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
635 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
636 i
++, offset
+= gpr_size
)
637 ppc_collect_reg (regcache
, i
, (gdb_byte
*) gregs
, offset
, gpr_size
);
639 ppc_collect_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
640 (gdb_byte
*) gregs
, offsets
->pc_offset
, gpr_size
);
641 ppc_collect_reg (regcache
, tdep
->ppc_ps_regnum
,
642 (gdb_byte
*) gregs
, offsets
->ps_offset
, gpr_size
);
643 ppc_collect_reg (regcache
, tdep
->ppc_lr_regnum
,
644 (gdb_byte
*) gregs
, offsets
->lr_offset
, gpr_size
);
645 ppc_collect_reg (regcache
, tdep
->ppc_ctr_regnum
,
646 (gdb_byte
*) gregs
, offsets
->ctr_offset
, gpr_size
);
647 ppc_collect_reg (regcache
, tdep
->ppc_cr_regnum
,
648 (gdb_byte
*) gregs
, offsets
->cr_offset
,
650 ppc_collect_reg (regcache
, tdep
->ppc_xer_regnum
,
651 (gdb_byte
*) gregs
, offsets
->xer_offset
,
653 ppc_collect_reg (regcache
, tdep
->ppc_mq_regnum
,
654 (gdb_byte
*) gregs
, offsets
->mq_offset
,
659 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
660 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) gregs
, offset
, regsize
);
663 /* Collect register REGNUM in the floating-point register set
664 REGSET from register cache REGCACHE into the buffer specified by
665 FPREGS and LEN. If REGNUM is -1, do this for all registers in
669 ppc_collect_fpregset (const struct regset
*regset
,
670 const struct regcache
*regcache
,
671 int regnum
, void *fpregs
, size_t len
)
673 struct gdbarch
*gdbarch
= regcache
->arch ();
674 struct gdbarch_tdep
*tdep
;
675 const struct ppc_reg_offsets
*offsets
;
678 if (!ppc_floating_point_unit_p (gdbarch
))
681 tdep
= gdbarch_tdep (gdbarch
);
682 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
687 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
688 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
690 ppc_collect_reg (regcache
, i
, (gdb_byte
*) fpregs
, offset
, 8);
692 ppc_collect_reg (regcache
, tdep
->ppc_fpscr_regnum
,
693 (gdb_byte
*) fpregs
, offsets
->fpscr_offset
,
694 offsets
->fpscr_size
);
698 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
699 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) fpregs
, offset
,
700 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
704 insn_changes_sp_or_jumps (unsigned long insn
)
706 int opcode
= (insn
>> 26) & 0x03f;
707 int sd
= (insn
>> 21) & 0x01f;
708 int a
= (insn
>> 16) & 0x01f;
709 int subcode
= (insn
>> 1) & 0x3ff;
711 /* Changes the stack pointer. */
713 /* NOTE: There are many ways to change the value of a given register.
714 The ways below are those used when the register is R1, the SP,
715 in a funtion's epilogue. */
717 if (opcode
== 31 && subcode
== 444 && a
== 1)
718 return 1; /* mr R1,Rn */
719 if (opcode
== 14 && sd
== 1)
720 return 1; /* addi R1,Rn,simm */
721 if (opcode
== 58 && sd
== 1)
722 return 1; /* ld R1,ds(Rn) */
724 /* Transfers control. */
730 if (opcode
== 19 && subcode
== 16)
732 if (opcode
== 19 && subcode
== 528)
733 return 1; /* bcctr */
738 /* Return true if we are in the function's epilogue, i.e. after the
739 instruction that destroyed the function's stack frame.
741 1) scan forward from the point of execution:
742 a) If you find an instruction that modifies the stack pointer
743 or transfers control (except a return), execution is not in
745 b) Stop scanning if you find a return instruction or reach the
746 end of the function or reach the hard limit for the size of
748 2) scan backward from the point of execution:
749 a) If you find an instruction that modifies the stack pointer,
750 execution *is* in an epilogue, return.
751 b) Stop scanning if you reach an instruction that transfers
752 control or the beginning of the function or reach the hard
753 limit for the size of an epilogue. */
756 rs6000_in_function_epilogue_frame_p (struct frame_info
*curfrm
,
757 struct gdbarch
*gdbarch
, CORE_ADDR pc
)
759 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
760 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
761 bfd_byte insn_buf
[PPC_INSN_SIZE
];
762 CORE_ADDR scan_pc
, func_start
, func_end
, epilogue_start
, epilogue_end
;
765 /* Find the search limits based on function boundaries and hard limit. */
767 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
770 epilogue_start
= pc
- PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
771 if (epilogue_start
< func_start
) epilogue_start
= func_start
;
773 epilogue_end
= pc
+ PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
774 if (epilogue_end
> func_end
) epilogue_end
= func_end
;
776 /* Scan forward until next 'blr'. */
778 for (scan_pc
= pc
; scan_pc
< epilogue_end
; scan_pc
+= PPC_INSN_SIZE
)
780 if (!safe_frame_unwind_memory (curfrm
, scan_pc
,
781 {insn_buf
, PPC_INSN_SIZE
}))
783 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
784 if (insn
== 0x4e800020)
786 /* Assume a bctr is a tail call unless it points strictly within
788 if (insn
== 0x4e800420)
790 CORE_ADDR ctr
= get_frame_register_unsigned (curfrm
,
791 tdep
->ppc_ctr_regnum
);
792 if (ctr
> func_start
&& ctr
< func_end
)
797 if (insn_changes_sp_or_jumps (insn
))
801 /* Scan backward until adjustment to stack pointer (R1). */
803 for (scan_pc
= pc
- PPC_INSN_SIZE
;
804 scan_pc
>= epilogue_start
;
805 scan_pc
-= PPC_INSN_SIZE
)
807 if (!safe_frame_unwind_memory (curfrm
, scan_pc
,
808 {insn_buf
, PPC_INSN_SIZE
}))
810 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
811 if (insn_changes_sp_or_jumps (insn
))
818 /* Implement the stack_frame_destroyed_p gdbarch method. */
821 rs6000_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
823 return rs6000_in_function_epilogue_frame_p (get_current_frame (),
827 /* Get the ith function argument for the current function. */
829 rs6000_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
832 return get_frame_register_unsigned (frame
, 3 + argi
);
835 /* Sequence of bytes for breakpoint instruction. */
837 constexpr gdb_byte big_breakpoint
[] = { 0x7d, 0x82, 0x10, 0x08 };
838 constexpr gdb_byte little_breakpoint
[] = { 0x08, 0x10, 0x82, 0x7d };
840 typedef BP_MANIPULATION_ENDIAN (little_breakpoint
, big_breakpoint
)
843 /* Instruction masks for displaced stepping. */
844 #define BRANCH_MASK 0xfc000000
845 #define BP_MASK 0xFC0007FE
846 #define B_INSN 0x48000000
847 #define BC_INSN 0x40000000
848 #define BXL_INSN 0x4c000000
849 #define BP_INSN 0x7C000008
851 /* Instruction masks used during single-stepping of atomic
853 #define LOAD_AND_RESERVE_MASK 0xfc0007fe
854 #define LWARX_INSTRUCTION 0x7c000028
855 #define LDARX_INSTRUCTION 0x7c0000A8
856 #define LBARX_INSTRUCTION 0x7c000068
857 #define LHARX_INSTRUCTION 0x7c0000e8
858 #define LQARX_INSTRUCTION 0x7c000228
859 #define STORE_CONDITIONAL_MASK 0xfc0007ff
860 #define STWCX_INSTRUCTION 0x7c00012d
861 #define STDCX_INSTRUCTION 0x7c0001ad
862 #define STBCX_INSTRUCTION 0x7c00056d
863 #define STHCX_INSTRUCTION 0x7c0005ad
864 #define STQCX_INSTRUCTION 0x7c00016d
866 /* Check if insn is one of the Load And Reserve instructions used for atomic
868 #define IS_LOAD_AND_RESERVE_INSN(insn) ((insn & LOAD_AND_RESERVE_MASK) == LWARX_INSTRUCTION \
869 || (insn & LOAD_AND_RESERVE_MASK) == LDARX_INSTRUCTION \
870 || (insn & LOAD_AND_RESERVE_MASK) == LBARX_INSTRUCTION \
871 || (insn & LOAD_AND_RESERVE_MASK) == LHARX_INSTRUCTION \
872 || (insn & LOAD_AND_RESERVE_MASK) == LQARX_INSTRUCTION)
873 /* Check if insn is one of the Store Conditional instructions used for atomic
875 #define IS_STORE_CONDITIONAL_INSN(insn) ((insn & STORE_CONDITIONAL_MASK) == STWCX_INSTRUCTION \
876 || (insn & STORE_CONDITIONAL_MASK) == STDCX_INSTRUCTION \
877 || (insn & STORE_CONDITIONAL_MASK) == STBCX_INSTRUCTION \
878 || (insn & STORE_CONDITIONAL_MASK) == STHCX_INSTRUCTION \
879 || (insn & STORE_CONDITIONAL_MASK) == STQCX_INSTRUCTION)
881 typedef buf_displaced_step_copy_insn_closure
882 ppc_displaced_step_copy_insn_closure
;
884 /* We can't displaced step atomic sequences. */
886 static displaced_step_copy_insn_closure_up
887 ppc_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
888 CORE_ADDR from
, CORE_ADDR to
,
889 struct regcache
*regs
)
891 size_t len
= gdbarch_max_insn_length (gdbarch
);
892 std::unique_ptr
<ppc_displaced_step_copy_insn_closure
> closure
893 (new ppc_displaced_step_copy_insn_closure (len
));
894 gdb_byte
*buf
= closure
->buf
.data ();
895 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
898 read_memory (from
, buf
, len
);
900 insn
= extract_signed_integer (buf
, PPC_INSN_SIZE
, byte_order
);
902 /* Assume all atomic sequences start with a Load and Reserve instruction. */
903 if (IS_LOAD_AND_RESERVE_INSN (insn
))
905 displaced_debug_printf ("can't displaced step atomic sequence at %s",
906 paddress (gdbarch
, from
));
911 write_memory (to
, buf
, len
);
913 displaced_debug_printf ("copy %s->%s: %s",
914 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
915 displaced_step_dump_bytes (buf
, len
).c_str ());;
917 /* This is a work around for a problem with g++ 4.8. */
918 return displaced_step_copy_insn_closure_up (closure
.release ());
921 /* Fix up the state of registers and memory after having single-stepped
922 a displaced instruction. */
924 ppc_displaced_step_fixup (struct gdbarch
*gdbarch
,
925 struct displaced_step_copy_insn_closure
*closure_
,
926 CORE_ADDR from
, CORE_ADDR to
,
927 struct regcache
*regs
)
929 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
930 /* Our closure is a copy of the instruction. */
931 ppc_displaced_step_copy_insn_closure
*closure
932 = (ppc_displaced_step_copy_insn_closure
*) closure_
;
933 ULONGEST insn
= extract_unsigned_integer (closure
->buf
.data (),
934 PPC_INSN_SIZE
, byte_order
);
936 /* Offset for non PC-relative instructions. */
937 LONGEST offset
= PPC_INSN_SIZE
;
939 opcode
= insn
& BRANCH_MASK
;
941 displaced_debug_printf ("(ppc) fixup (%s, %s)",
942 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
944 /* Handle PC-relative branch instructions. */
945 if (opcode
== B_INSN
|| opcode
== BC_INSN
|| opcode
== BXL_INSN
)
949 /* Read the current PC value after the instruction has been executed
950 in a displaced location. Calculate the offset to be applied to the
951 original PC value before the displaced stepping. */
952 regcache_cooked_read_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
954 offset
= current_pc
- to
;
956 if (opcode
!= BXL_INSN
)
958 /* Check for AA bit indicating whether this is an absolute
959 addressing or PC-relative (1: absolute, 0: relative). */
962 /* PC-relative addressing is being used in the branch. */
963 displaced_debug_printf ("(ppc) branch instruction: %s",
964 paddress (gdbarch
, insn
));
965 displaced_debug_printf ("(ppc) adjusted PC from %s to %s",
966 paddress (gdbarch
, current_pc
),
967 paddress (gdbarch
, from
+ offset
));
969 regcache_cooked_write_unsigned (regs
,
970 gdbarch_pc_regnum (gdbarch
),
976 /* If we're here, it means we have a branch to LR or CTR. If the
977 branch was taken, the offset is probably greater than 4 (the next
978 instruction), so it's safe to assume that an offset of 4 means we
979 did not take the branch. */
980 if (offset
== PPC_INSN_SIZE
)
981 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
982 from
+ PPC_INSN_SIZE
);
985 /* Check for LK bit indicating whether we should set the link
986 register to point to the next instruction
987 (1: Set, 0: Don't set). */
990 /* Link register needs to be set to the next instruction's PC. */
991 regcache_cooked_write_unsigned (regs
,
992 gdbarch_tdep (gdbarch
)->ppc_lr_regnum
,
993 from
+ PPC_INSN_SIZE
);
994 displaced_debug_printf ("(ppc) adjusted LR to %s",
995 paddress (gdbarch
, from
+ PPC_INSN_SIZE
));
999 /* Check for breakpoints in the inferior. If we've found one, place the PC
1000 right at the breakpoint instruction. */
1001 else if ((insn
& BP_MASK
) == BP_INSN
)
1002 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
), from
);
1004 /* Handle any other instructions that do not fit in the categories above. */
1005 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1009 /* Implementation of gdbarch_displaced_step_prepare. */
1011 static displaced_step_prepare_status
1012 ppc_displaced_step_prepare (gdbarch
*arch
, thread_info
*thread
,
1013 CORE_ADDR
&displaced_pc
)
1015 ppc_inferior_data
*per_inferior
= get_ppc_per_inferior (thread
->inf
);
1017 if (!per_inferior
->disp_step_buf
.has_value ())
1019 /* Figure out where the displaced step buffer is. */
1020 CORE_ADDR disp_step_buf_addr
1021 = displaced_step_at_entry_point (thread
->inf
->gdbarch
);
1023 per_inferior
->disp_step_buf
.emplace (disp_step_buf_addr
);
1026 return per_inferior
->disp_step_buf
->prepare (thread
, displaced_pc
);
1029 /* Implementation of gdbarch_displaced_step_finish. */
1031 static displaced_step_finish_status
1032 ppc_displaced_step_finish (gdbarch
*arch
, thread_info
*thread
,
1035 ppc_inferior_data
*per_inferior
= get_ppc_per_inferior (thread
->inf
);
1037 gdb_assert (per_inferior
->disp_step_buf
.has_value ());
1039 return per_inferior
->disp_step_buf
->finish (arch
, thread
, sig
);
1042 /* Implementation of gdbarch_displaced_step_restore_all_in_ptid. */
1045 ppc_displaced_step_restore_all_in_ptid (inferior
*parent_inf
, ptid_t ptid
)
1047 ppc_inferior_data
*per_inferior
= ppc_inferior_data_key
.get (parent_inf
);
1049 if (per_inferior
== nullptr
1050 || !per_inferior
->disp_step_buf
.has_value ())
1053 per_inferior
->disp_step_buf
->restore_in_ptid (ptid
);
1056 /* Always use hardware single-stepping to execute the
1057 displaced instruction. */
1059 ppc_displaced_step_hw_singlestep (struct gdbarch
*gdbarch
)
1064 /* Checks for an atomic sequence of instructions beginning with a
1065 Load And Reserve instruction and ending with a Store Conditional
1066 instruction. If such a sequence is found, attempt to step through it.
1067 A breakpoint is placed at the end of the sequence. */
1068 std::vector
<CORE_ADDR
>
1069 ppc_deal_with_atomic_sequence (struct regcache
*regcache
)
1071 struct gdbarch
*gdbarch
= regcache
->arch ();
1072 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1073 CORE_ADDR pc
= regcache_read_pc (regcache
);
1074 CORE_ADDR breaks
[2] = {CORE_ADDR_MAX
, CORE_ADDR_MAX
};
1076 CORE_ADDR closing_insn
; /* Instruction that closes the atomic sequence. */
1077 int insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1080 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
1081 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
1082 int bc_insn_count
= 0; /* Conditional branch instruction count. */
1084 /* Assume all atomic sequences start with a Load And Reserve instruction. */
1085 if (!IS_LOAD_AND_RESERVE_INSN (insn
))
1088 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
1090 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
1092 loc
+= PPC_INSN_SIZE
;
1093 insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1095 /* Assume that there is at most one conditional branch in the atomic
1096 sequence. If a conditional branch is found, put a breakpoint in
1097 its destination address. */
1098 if ((insn
& BRANCH_MASK
) == BC_INSN
)
1100 int immediate
= ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
1101 int absolute
= insn
& 2;
1103 if (bc_insn_count
>= 1)
1104 return {}; /* More than one conditional branch found, fallback
1105 to the standard single-step code. */
1108 breaks
[1] = immediate
;
1110 breaks
[1] = loc
+ immediate
;
1116 if (IS_STORE_CONDITIONAL_INSN (insn
))
1120 /* Assume that the atomic sequence ends with a Store Conditional
1122 if (!IS_STORE_CONDITIONAL_INSN (insn
))
1126 loc
+= PPC_INSN_SIZE
;
1128 /* Insert a breakpoint right after the end of the atomic sequence. */
1131 /* Check for duplicated breakpoints. Check also for a breakpoint
1132 placed (branch instruction's destination) anywhere in sequence. */
1134 && (breaks
[1] == breaks
[0]
1135 || (breaks
[1] >= pc
&& breaks
[1] <= closing_insn
)))
1136 last_breakpoint
= 0;
1138 std::vector
<CORE_ADDR
> next_pcs
;
1140 for (index
= 0; index
<= last_breakpoint
; index
++)
1141 next_pcs
.push_back (breaks
[index
]);
1147 #define SIGNED_SHORT(x) \
1148 ((sizeof (short) == 2) \
1149 ? ((int)(short)(x)) \
1150 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
1152 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
1154 /* Limit the number of skipped non-prologue instructions, as the examining
1155 of the prologue is expensive. */
1156 static int max_skip_non_prologue_insns
= 10;
1158 /* Return nonzero if the given instruction OP can be part of the prologue
1159 of a function and saves a parameter on the stack. FRAMEP should be
1160 set if one of the previous instructions in the function has set the
1164 store_param_on_stack_p (unsigned long op
, int framep
, int *r0_contains_arg
)
1166 /* Move parameters from argument registers to temporary register. */
1167 if ((op
& 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
1169 /* Rx must be scratch register r0. */
1170 const int rx_regno
= (op
>> 16) & 31;
1171 /* Ry: Only r3 - r10 are used for parameter passing. */
1172 const int ry_regno
= GET_SRC_REG (op
);
1174 if (rx_regno
== 0 && ry_regno
>= 3 && ry_regno
<= 10)
1176 *r0_contains_arg
= 1;
1183 /* Save a General Purpose Register on stack. */
1185 if ((op
& 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
1186 (op
& 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
1188 /* Rx: Only r3 - r10 are used for parameter passing. */
1189 const int rx_regno
= GET_SRC_REG (op
);
1191 return (rx_regno
>= 3 && rx_regno
<= 10);
1194 /* Save a General Purpose Register on stack via the Frame Pointer. */
1197 ((op
& 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
1198 (op
& 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
1199 (op
& 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
1201 /* Rx: Usually, only r3 - r10 are used for parameter passing.
1202 However, the compiler sometimes uses r0 to hold an argument. */
1203 const int rx_regno
= GET_SRC_REG (op
);
1205 return ((rx_regno
>= 3 && rx_regno
<= 10)
1206 || (rx_regno
== 0 && *r0_contains_arg
));
1209 if ((op
& 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
1211 /* Only f2 - f8 are used for parameter passing. */
1212 const int src_regno
= GET_SRC_REG (op
);
1214 return (src_regno
>= 2 && src_regno
<= 8);
1217 if (framep
&& ((op
& 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
1219 /* Only f2 - f8 are used for parameter passing. */
1220 const int src_regno
= GET_SRC_REG (op
);
1222 return (src_regno
>= 2 && src_regno
<= 8);
1225 /* Not an insn that saves a parameter on stack. */
1229 /* Assuming that INSN is a "bl" instruction located at PC, return
1230 nonzero if the destination of the branch is a "blrl" instruction.
1232 This sequence is sometimes found in certain function prologues.
1233 It allows the function to load the LR register with a value that
1234 they can use to access PIC data using PC-relative offsets. */
1237 bl_to_blrl_insn_p (CORE_ADDR pc
, int insn
, enum bfd_endian byte_order
)
1244 absolute
= (int) ((insn
>> 1) & 1);
1245 immediate
= ((insn
& ~3) << 6) >> 6;
1249 dest
= pc
+ immediate
;
1251 dest_insn
= read_memory_integer (dest
, 4, byte_order
);
1252 if ((dest_insn
& 0xfc00ffff) == 0x4c000021) /* blrl */
1258 /* Return true if OP is a stw or std instruction with
1259 register operands RS and RA and any immediate offset.
1261 If WITH_UPDATE is true, also return true if OP is
1262 a stwu or stdu instruction with the same operands.
1264 Return false otherwise.
1267 store_insn_p (unsigned long op
, unsigned long rs
,
1268 unsigned long ra
, bool with_update
)
1273 if (/* std RS, SIMM(RA) */
1274 ((op
& 0xffff0003) == (rs
| ra
| 0xf8000000)) ||
1275 /* stw RS, SIMM(RA) */
1276 ((op
& 0xffff0000) == (rs
| ra
| 0x90000000)))
1281 if (/* stdu RS, SIMM(RA) */
1282 ((op
& 0xffff0003) == (rs
| ra
| 0xf8000001)) ||
1283 /* stwu RS, SIMM(RA) */
1284 ((op
& 0xffff0000) == (rs
| ra
| 0x94000000)))
1291 /* Masks for decoding a branch-and-link (bl) instruction.
1293 BL_MASK and BL_INSTRUCTION are used in combination with each other.
1294 The former is anded with the opcode in question; if the result of
1295 this masking operation is equal to BL_INSTRUCTION, then the opcode in
1296 question is a ``bl'' instruction.
1298 BL_DISPLACEMENT_MASK is anded with the opcode in order to extract
1299 the branch displacement. */
1301 #define BL_MASK 0xfc000001
1302 #define BL_INSTRUCTION 0x48000001
1303 #define BL_DISPLACEMENT_MASK 0x03fffffc
1305 static unsigned long
1306 rs6000_fetch_instruction (struct gdbarch
*gdbarch
, const CORE_ADDR pc
)
1308 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1312 /* Fetch the instruction and convert it to an integer. */
1313 if (target_read_memory (pc
, buf
, 4))
1315 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1320 /* GCC generates several well-known sequences of instructions at the begining
1321 of each function prologue when compiling with -fstack-check. If one of
1322 such sequences starts at START_PC, then return the address of the
1323 instruction immediately past this sequence. Otherwise, return START_PC. */
1326 rs6000_skip_stack_check (struct gdbarch
*gdbarch
, const CORE_ADDR start_pc
)
1328 CORE_ADDR pc
= start_pc
;
1329 unsigned long op
= rs6000_fetch_instruction (gdbarch
, pc
);
1331 /* First possible sequence: A small number of probes.
1332 stw 0, -<some immediate>(1)
1333 [repeat this instruction any (small) number of times]. */
1335 if ((op
& 0xffff0000) == 0x90010000)
1337 while ((op
& 0xffff0000) == 0x90010000)
1340 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1345 /* Second sequence: A probing loop.
1346 addi 12,1,-<some immediate>
1347 lis 0,-<some immediate>
1348 [possibly ori 0,0,<some immediate>]
1352 addi 12,12,-<some immediate>
1355 [possibly one last probe: stw 0,<some immediate>(12)]. */
1359 /* addi 12,1,-<some immediate> */
1360 if ((op
& 0xffff0000) != 0x39810000)
1363 /* lis 0,-<some immediate> */
1365 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1366 if ((op
& 0xffff0000) != 0x3c000000)
1370 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1371 /* [possibly ori 0,0,<some immediate>] */
1372 if ((op
& 0xffff0000) == 0x60000000)
1375 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1378 if (op
!= 0x7c0c0214)
1383 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1384 if (op
!= 0x7c0c0000)
1389 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1390 if ((op
& 0xff9f0001) != 0x41820000)
1393 /* addi 12,12,-<some immediate> */
1395 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1396 if ((op
& 0xffff0000) != 0x398c0000)
1401 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1402 if (op
!= 0x900c0000)
1407 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1408 if ((op
& 0xfc000001) != 0x48000000)
1411 /* [possibly one last probe: stw 0,<some immediate>(12)]. */
1413 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1414 if ((op
& 0xffff0000) == 0x900c0000)
1417 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1420 /* We found a valid stack-check sequence, return the new PC. */
1424 /* Third sequence: No probe; instead, a comparison between the stack size
1425 limit (saved in a run-time global variable) and the current stack
1428 addi 0,1,-<some immediate>
1429 lis 12,__gnat_stack_limit@ha
1430 lwz 12,__gnat_stack_limit@l(12)
1433 or, with a small variant in the case of a bigger stack frame:
1434 addis 0,1,<some immediate>
1435 addic 0,0,-<some immediate>
1436 lis 12,__gnat_stack_limit@ha
1437 lwz 12,__gnat_stack_limit@l(12)
1442 /* addi 0,1,-<some immediate> */
1443 if ((op
& 0xffff0000) != 0x38010000)
1445 /* small stack frame variant not recognized; try the
1446 big stack frame variant: */
1448 /* addis 0,1,<some immediate> */
1449 if ((op
& 0xffff0000) != 0x3c010000)
1452 /* addic 0,0,-<some immediate> */
1454 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1455 if ((op
& 0xffff0000) != 0x30000000)
1459 /* lis 12,<some immediate> */
1461 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1462 if ((op
& 0xffff0000) != 0x3d800000)
1465 /* lwz 12,<some immediate>(12) */
1467 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1468 if ((op
& 0xffff0000) != 0x818c0000)
1473 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1474 if ((op
& 0xfffffffe) != 0x7c406008)
1477 /* We found a valid stack-check sequence, return the new PC. */
1481 /* No stack check code in our prologue, return the start_pc. */
1485 /* return pc value after skipping a function prologue and also return
1486 information about a function frame.
1488 in struct rs6000_framedata fdata:
1489 - frameless is TRUE, if function does not have a frame.
1490 - nosavedpc is TRUE, if function does not save %pc value in its frame.
1491 - offset is the initial size of this stack frame --- the amount by
1492 which we decrement the sp to allocate the frame.
1493 - saved_gpr is the number of the first saved gpr.
1494 - saved_fpr is the number of the first saved fpr.
1495 - saved_vr is the number of the first saved vr.
1496 - saved_ev is the number of the first saved ev.
1497 - alloca_reg is the number of the register used for alloca() handling.
1499 - gpr_offset is the offset of the first saved gpr from the previous frame.
1500 - fpr_offset is the offset of the first saved fpr from the previous frame.
1501 - vr_offset is the offset of the first saved vr from the previous frame.
1502 - ev_offset is the offset of the first saved ev from the previous frame.
1503 - lr_offset is the offset of the saved lr
1504 - cr_offset is the offset of the saved cr
1505 - vrsave_offset is the offset of the saved vrsave register. */
1508 skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
, CORE_ADDR lim_pc
,
1509 struct rs6000_framedata
*fdata
)
1511 CORE_ADDR orig_pc
= pc
;
1512 CORE_ADDR last_prologue_pc
= pc
;
1513 CORE_ADDR li_found_pc
= 0;
1517 long alloca_reg_offset
= 0;
1518 long vr_saved_offset
= 0;
1524 int vrsave_reg
= -1;
1527 int minimal_toc_loaded
= 0;
1528 int prev_insn_was_prologue_insn
= 1;
1529 int num_skip_non_prologue_insns
= 0;
1530 int r0_contains_arg
= 0;
1531 const struct bfd_arch_info
*arch_info
= gdbarch_bfd_arch_info (gdbarch
);
1532 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1533 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1535 memset (fdata
, 0, sizeof (struct rs6000_framedata
));
1536 fdata
->saved_gpr
= -1;
1537 fdata
->saved_fpr
= -1;
1538 fdata
->saved_vr
= -1;
1539 fdata
->saved_ev
= -1;
1540 fdata
->alloca_reg
= -1;
1541 fdata
->frameless
= 1;
1542 fdata
->nosavedpc
= 1;
1543 fdata
->lr_register
= -1;
1545 pc
= rs6000_skip_stack_check (gdbarch
, pc
);
1551 /* Sometimes it isn't clear if an instruction is a prologue
1552 instruction or not. When we encounter one of these ambiguous
1553 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
1554 Otherwise, we'll assume that it really is a prologue instruction. */
1555 if (prev_insn_was_prologue_insn
)
1556 last_prologue_pc
= pc
;
1558 /* Stop scanning if we've hit the limit. */
1562 prev_insn_was_prologue_insn
= 1;
1564 /* Fetch the instruction and convert it to an integer. */
1565 if (target_read_memory (pc
, buf
, 4))
1567 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1569 if ((op
& 0xfc1fffff) == 0x7c0802a6)
1571 /* Since shared library / PIC code, which needs to get its
1572 address at runtime, can appear to save more than one link
1586 remember just the first one, but skip over additional
1589 lr_reg
= (op
& 0x03e00000) >> 21;
1591 r0_contains_arg
= 0;
1594 else if ((op
& 0xfc1fffff) == 0x7c000026)
1596 cr_reg
= (op
& 0x03e00000) >> 21;
1598 r0_contains_arg
= 0;
1602 else if ((op
& 0xfc1f0000) == 0xd8010000)
1603 { /* stfd Rx,NUM(r1) */
1604 reg
= GET_SRC_REG (op
);
1605 if (fdata
->saved_fpr
== -1 || fdata
->saved_fpr
> reg
)
1607 fdata
->saved_fpr
= reg
;
1608 fdata
->fpr_offset
= SIGNED_SHORT (op
) + offset
;
1613 else if (((op
& 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
1614 (((op
& 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1615 (op
& 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1616 (op
& 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
1619 reg
= GET_SRC_REG (op
);
1620 if ((op
& 0xfc1f0000) == 0xbc010000)
1621 fdata
->gpr_mask
|= ~((1U << reg
) - 1);
1623 fdata
->gpr_mask
|= 1U << reg
;
1624 if (fdata
->saved_gpr
== -1 || fdata
->saved_gpr
> reg
)
1626 fdata
->saved_gpr
= reg
;
1627 if ((op
& 0xfc1f0003) == 0xf8010000)
1629 fdata
->gpr_offset
= SIGNED_SHORT (op
) + offset
;
1634 else if ((op
& 0xffff0000) == 0x3c4c0000
1635 || (op
& 0xffff0000) == 0x3c400000
1636 || (op
& 0xffff0000) == 0x38420000)
1638 /* . 0: addis 2,12,.TOC.-0b@ha
1639 . addi 2,2,.TOC.-0b@l
1643 used by ELFv2 global entry points to set up r2. */
1646 else if (op
== 0x60000000)
1649 /* Allow nops in the prologue, but do not consider them to
1650 be part of the prologue unless followed by other prologue
1652 prev_insn_was_prologue_insn
= 0;
1656 else if ((op
& 0xffff0000) == 0x3c000000)
1657 { /* addis 0,0,NUM, used for >= 32k frames */
1658 fdata
->offset
= (op
& 0x0000ffff) << 16;
1659 fdata
->frameless
= 0;
1660 r0_contains_arg
= 0;
1664 else if ((op
& 0xffff0000) == 0x60000000)
1665 { /* ori 0,0,NUM, 2nd half of >= 32k frames */
1666 fdata
->offset
|= (op
& 0x0000ffff);
1667 fdata
->frameless
= 0;
1668 r0_contains_arg
= 0;
1672 else if (lr_reg
>= 0 &&
1673 ((store_insn_p (op
, lr_reg
, 1, true)) ||
1675 (store_insn_p (op
, lr_reg
,
1676 fdata
->alloca_reg
- tdep
->ppc_gp0_regnum
,
1679 if (store_insn_p (op
, lr_reg
, 1, true))
1680 fdata
->lr_offset
= offset
;
1681 else /* LR save through frame pointer. */
1682 fdata
->lr_offset
= alloca_reg_offset
;
1684 fdata
->nosavedpc
= 0;
1685 /* Invalidate lr_reg, but don't set it to -1.
1686 That would mean that it had never been set. */
1688 if ((op
& 0xfc000003) == 0xf8000000 || /* std */
1689 (op
& 0xfc000000) == 0x90000000) /* stw */
1691 /* Does not update r1, so add displacement to lr_offset. */
1692 fdata
->lr_offset
+= SIGNED_SHORT (op
);
1697 else if (cr_reg
>= 0 &&
1698 (store_insn_p (op
, cr_reg
, 1, true)))
1700 fdata
->cr_offset
= offset
;
1701 /* Invalidate cr_reg, but don't set it to -1.
1702 That would mean that it had never been set. */
1704 if ((op
& 0xfc000003) == 0xf8000000 ||
1705 (op
& 0xfc000000) == 0x90000000)
1707 /* Does not update r1, so add displacement to cr_offset. */
1708 fdata
->cr_offset
+= SIGNED_SHORT (op
);
1713 else if ((op
& 0xfe80ffff) == 0x42800005 && lr_reg
!= -1)
1715 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1716 prediction bits. If the LR has already been saved, we can
1720 else if (op
== 0x48000005)
1727 else if (op
== 0x48000004)
1732 else if ((op
& 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1733 in V.4 -mminimal-toc */
1734 (op
& 0xffff0000) == 0x3bde0000)
1735 { /* addi 30,30,foo@l */
1739 else if ((op
& 0xfc000001) == 0x48000001)
1743 fdata
->frameless
= 0;
1745 /* If the return address has already been saved, we can skip
1746 calls to blrl (for PIC). */
1747 if (lr_reg
!= -1 && bl_to_blrl_insn_p (pc
, op
, byte_order
))
1753 /* Don't skip over the subroutine call if it is not within
1754 the first three instructions of the prologue and either
1755 we have no line table information or the line info tells
1756 us that the subroutine call is not part of the line
1757 associated with the prologue. */
1758 if ((pc
- orig_pc
) > 8)
1760 struct symtab_and_line prologue_sal
= find_pc_line (orig_pc
, 0);
1761 struct symtab_and_line this_sal
= find_pc_line (pc
, 0);
1763 if ((prologue_sal
.line
== 0)
1764 || (prologue_sal
.line
!= this_sal
.line
))
1768 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
1770 /* At this point, make sure this is not a trampoline
1771 function (a function that simply calls another functions,
1772 and nothing else). If the next is not a nop, this branch
1773 was part of the function prologue. */
1775 if (op
== 0x4def7b82 || op
== 0) /* crorc 15, 15, 15 */
1776 break; /* Don't skip over
1782 /* update stack pointer */
1783 else if ((op
& 0xfc1f0000) == 0x94010000)
1784 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
1785 fdata
->frameless
= 0;
1786 fdata
->offset
= SIGNED_SHORT (op
);
1787 offset
= fdata
->offset
;
1790 else if ((op
& 0xfc1f07fa) == 0x7c01016a)
1791 { /* stwux rX,r1,rY || stdux rX,r1,rY */
1792 /* No way to figure out what r1 is going to be. */
1793 fdata
->frameless
= 0;
1794 offset
= fdata
->offset
;
1797 else if ((op
& 0xfc1f0003) == 0xf8010001)
1798 { /* stdu rX,NUM(r1) */
1799 fdata
->frameless
= 0;
1800 fdata
->offset
= SIGNED_SHORT (op
& ~3UL);
1801 offset
= fdata
->offset
;
1804 else if ((op
& 0xffff0000) == 0x38210000)
1805 { /* addi r1,r1,SIMM */
1806 fdata
->frameless
= 0;
1807 fdata
->offset
+= SIGNED_SHORT (op
);
1808 offset
= fdata
->offset
;
1811 /* Load up minimal toc pointer. Do not treat an epilogue restore
1812 of r31 as a minimal TOC load. */
1813 else if (((op
>> 22) == 0x20f || /* l r31,... or l r30,... */
1814 (op
>> 22) == 0x3af) /* ld r31,... or ld r30,... */
1816 && !minimal_toc_loaded
)
1818 minimal_toc_loaded
= 1;
1821 /* move parameters from argument registers to local variable
1824 else if ((op
& 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1825 (((op
>> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1826 (((op
>> 21) & 31) <= 10) &&
1827 ((long) ((op
>> 16) & 31)
1828 >= fdata
->saved_gpr
)) /* Rx: local var reg */
1832 /* store parameters in stack */
1834 /* Move parameters from argument registers to temporary register. */
1835 else if (store_param_on_stack_p (op
, framep
, &r0_contains_arg
))
1839 /* Set up frame pointer */
1841 else if (op
== 0x603d0000) /* oril r29, r1, 0x0 */
1843 fdata
->frameless
= 0;
1845 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 29);
1846 alloca_reg_offset
= offset
;
1849 /* Another way to set up the frame pointer. */
1851 else if (op
== 0x603f0000 /* oril r31, r1, 0x0 */
1852 || op
== 0x7c3f0b78)
1854 fdata
->frameless
= 0;
1856 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 31);
1857 alloca_reg_offset
= offset
;
1860 /* Another way to set up the frame pointer. */
1862 else if ((op
& 0xfc1fffff) == 0x38010000)
1863 { /* addi rX, r1, 0x0 */
1864 fdata
->frameless
= 0;
1866 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
1867 + ((op
& ~0x38010000) >> 21));
1868 alloca_reg_offset
= offset
;
1871 /* AltiVec related instructions. */
1872 /* Store the vrsave register (spr 256) in another register for
1873 later manipulation, or load a register into the vrsave
1874 register. 2 instructions are used: mfvrsave and
1875 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1876 and mtspr SPR256, Rn. */
1877 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1878 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1879 else if ((op
& 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1881 vrsave_reg
= GET_SRC_REG (op
);
1884 else if ((op
& 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1888 /* Store the register where vrsave was saved to onto the stack:
1889 rS is the register where vrsave was stored in a previous
1891 /* 100100 sssss 00001 dddddddd dddddddd */
1892 else if ((op
& 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1894 if (vrsave_reg
== GET_SRC_REG (op
))
1896 fdata
->vrsave_offset
= SIGNED_SHORT (op
) + offset
;
1901 /* Compute the new value of vrsave, by modifying the register
1902 where vrsave was saved to. */
1903 else if (((op
& 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1904 || ((op
& 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1908 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1909 in a pair of insns to save the vector registers on the
1911 /* 001110 00000 00000 iiii iiii iiii iiii */
1912 /* 001110 01110 00000 iiii iiii iiii iiii */
1913 else if ((op
& 0xffff0000) == 0x38000000 /* li r0, SIMM */
1914 || (op
& 0xffff0000) == 0x39c00000) /* li r14, SIMM */
1916 if ((op
& 0xffff0000) == 0x38000000)
1917 r0_contains_arg
= 0;
1919 vr_saved_offset
= SIGNED_SHORT (op
);
1921 /* This insn by itself is not part of the prologue, unless
1922 if part of the pair of insns mentioned above. So do not
1923 record this insn as part of the prologue yet. */
1924 prev_insn_was_prologue_insn
= 0;
1926 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1927 /* 011111 sssss 11111 00000 00111001110 */
1928 else if ((op
& 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1930 if (pc
== (li_found_pc
+ 4))
1932 vr_reg
= GET_SRC_REG (op
);
1933 /* If this is the first vector reg to be saved, or if
1934 it has a lower number than others previously seen,
1935 reupdate the frame info. */
1936 if (fdata
->saved_vr
== -1 || fdata
->saved_vr
> vr_reg
)
1938 fdata
->saved_vr
= vr_reg
;
1939 fdata
->vr_offset
= vr_saved_offset
+ offset
;
1941 vr_saved_offset
= -1;
1946 /* End AltiVec related instructions. */
1948 /* Start BookE related instructions. */
1949 /* Store gen register S at (r31+uimm).
1950 Any register less than r13 is volatile, so we don't care. */
1951 /* 000100 sssss 11111 iiiii 01100100001 */
1952 else if (arch_info
->mach
== bfd_mach_ppc_e500
1953 && (op
& 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
1955 if ((op
& 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
1958 ev_reg
= GET_SRC_REG (op
);
1959 imm
= (op
>> 11) & 0x1f;
1960 ev_offset
= imm
* 8;
1961 /* If this is the first vector reg to be saved, or if
1962 it has a lower number than others previously seen,
1963 reupdate the frame info. */
1964 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1966 fdata
->saved_ev
= ev_reg
;
1967 fdata
->ev_offset
= ev_offset
+ offset
;
1972 /* Store gen register rS at (r1+rB). */
1973 /* 000100 sssss 00001 bbbbb 01100100000 */
1974 else if (arch_info
->mach
== bfd_mach_ppc_e500
1975 && (op
& 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1977 if (pc
== (li_found_pc
+ 4))
1979 ev_reg
= GET_SRC_REG (op
);
1980 /* If this is the first vector reg to be saved, or if
1981 it has a lower number than others previously seen,
1982 reupdate the frame info. */
1983 /* We know the contents of rB from the previous instruction. */
1984 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1986 fdata
->saved_ev
= ev_reg
;
1987 fdata
->ev_offset
= vr_saved_offset
+ offset
;
1989 vr_saved_offset
= -1;
1995 /* Store gen register r31 at (rA+uimm). */
1996 /* 000100 11111 aaaaa iiiii 01100100001 */
1997 else if (arch_info
->mach
== bfd_mach_ppc_e500
1998 && (op
& 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
2000 /* Wwe know that the source register is 31 already, but
2001 it can't hurt to compute it. */
2002 ev_reg
= GET_SRC_REG (op
);
2003 ev_offset
= ((op
>> 11) & 0x1f) * 8;
2004 /* If this is the first vector reg to be saved, or if
2005 it has a lower number than others previously seen,
2006 reupdate the frame info. */
2007 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2009 fdata
->saved_ev
= ev_reg
;
2010 fdata
->ev_offset
= ev_offset
+ offset
;
2015 /* Store gen register S at (r31+r0).
2016 Store param on stack when offset from SP bigger than 4 bytes. */
2017 /* 000100 sssss 11111 00000 01100100000 */
2018 else if (arch_info
->mach
== bfd_mach_ppc_e500
2019 && (op
& 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
2021 if (pc
== (li_found_pc
+ 4))
2023 if ((op
& 0x03e00000) >= 0x01a00000)
2025 ev_reg
= GET_SRC_REG (op
);
2026 /* If this is the first vector reg to be saved, or if
2027 it has a lower number than others previously seen,
2028 reupdate the frame info. */
2029 /* We know the contents of r0 from the previous
2031 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2033 fdata
->saved_ev
= ev_reg
;
2034 fdata
->ev_offset
= vr_saved_offset
+ offset
;
2038 vr_saved_offset
= -1;
2043 /* End BookE related instructions. */
2047 /* Not a recognized prologue instruction.
2048 Handle optimizer code motions into the prologue by continuing
2049 the search if we have no valid frame yet or if the return
2050 address is not yet saved in the frame. Also skip instructions
2051 if some of the GPRs expected to be saved are not yet saved. */
2052 if (fdata
->frameless
== 0 && fdata
->nosavedpc
== 0
2053 && fdata
->saved_gpr
!= -1)
2055 unsigned int all_mask
= ~((1U << fdata
->saved_gpr
) - 1);
2057 if ((fdata
->gpr_mask
& all_mask
) == all_mask
)
2061 if (op
== 0x4e800020 /* blr */
2062 || op
== 0x4e800420) /* bctr */
2063 /* Do not scan past epilogue in frameless functions or
2066 if ((op
& 0xf4000000) == 0x40000000) /* bxx */
2067 /* Never skip branches. */
2070 if (num_skip_non_prologue_insns
++ > max_skip_non_prologue_insns
)
2071 /* Do not scan too many insns, scanning insns is expensive with
2075 /* Continue scanning. */
2076 prev_insn_was_prologue_insn
= 0;
2082 /* I have problems with skipping over __main() that I need to address
2083 * sometime. Previously, I used to use misc_function_vector which
2084 * didn't work as well as I wanted to be. -MGO */
2086 /* If the first thing after skipping a prolog is a branch to a function,
2087 this might be a call to an initializer in main(), introduced by gcc2.
2088 We'd like to skip over it as well. Fortunately, xlc does some extra
2089 work before calling a function right after a prologue, thus we can
2090 single out such gcc2 behaviour. */
2093 if ((op
& 0xfc000001) == 0x48000001)
2094 { /* bl foo, an initializer function? */
2095 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
2097 if (op
== 0x4def7b82)
2098 { /* cror 0xf, 0xf, 0xf (nop) */
2100 /* Check and see if we are in main. If so, skip over this
2101 initializer function as well. */
2103 tmp
= find_pc_misc_function (pc
);
2105 && strcmp (misc_function_vector
[tmp
].name
, main_name ()) == 0)
2111 if (pc
== lim_pc
&& lr_reg
>= 0)
2112 fdata
->lr_register
= lr_reg
;
2114 fdata
->offset
= -fdata
->offset
;
2115 return last_prologue_pc
;
2119 rs6000_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2121 struct rs6000_framedata frame
;
2122 CORE_ADDR limit_pc
, func_addr
, func_end_addr
= 0;
2124 /* See if we can determine the end of the prologue via the symbol table.
2125 If so, then return either PC, or the PC after the prologue, whichever
2127 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end_addr
))
2129 CORE_ADDR post_prologue_pc
2130 = skip_prologue_using_sal (gdbarch
, func_addr
);
2131 if (post_prologue_pc
!= 0)
2132 return std::max (pc
, post_prologue_pc
);
2135 /* Can't determine prologue from the symbol table, need to examine
2138 /* Find an upper limit on the function prologue using the debug
2139 information. If the debug information could not be used to provide
2140 that bound, then use an arbitrary large number as the upper bound. */
2141 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
2143 limit_pc
= pc
+ 100; /* Magic. */
2145 /* Do not allow limit_pc to be past the function end, if we know
2146 where that end is... */
2147 if (func_end_addr
&& limit_pc
> func_end_addr
)
2148 limit_pc
= func_end_addr
;
2150 pc
= skip_prologue (gdbarch
, pc
, limit_pc
, &frame
);
2154 /* When compiling for EABI, some versions of GCC emit a call to __eabi
2155 in the prologue of main().
2157 The function below examines the code pointed at by PC and checks to
2158 see if it corresponds to a call to __eabi. If so, it returns the
2159 address of the instruction following that call. Otherwise, it simply
2163 rs6000_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2165 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2169 if (target_read_memory (pc
, buf
, 4))
2171 op
= extract_unsigned_integer (buf
, 4, byte_order
);
2173 if ((op
& BL_MASK
) == BL_INSTRUCTION
)
2175 CORE_ADDR displ
= op
& BL_DISPLACEMENT_MASK
;
2176 CORE_ADDR call_dest
= pc
+ 4 + displ
;
2177 struct bound_minimal_symbol s
= lookup_minimal_symbol_by_pc (call_dest
);
2179 /* We check for ___eabi (three leading underscores) in addition
2180 to __eabi in case the GCC option "-fleading-underscore" was
2181 used to compile the program. */
2182 if (s
.minsym
!= NULL
2183 && s
.minsym
->linkage_name () != NULL
2184 && (strcmp (s
.minsym
->linkage_name (), "__eabi") == 0
2185 || strcmp (s
.minsym
->linkage_name (), "___eabi") == 0))
2191 /* All the ABI's require 16 byte alignment. */
2193 rs6000_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2195 return (addr
& -16);
2198 /* Return whether handle_inferior_event() should proceed through code
2199 starting at PC in function NAME when stepping.
2201 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
2202 handle memory references that are too distant to fit in instructions
2203 generated by the compiler. For example, if 'foo' in the following
2208 is greater than 32767, the linker might replace the lwz with a branch to
2209 somewhere in @FIX1 that does the load in 2 instructions and then branches
2210 back to where execution should continue.
2212 GDB should silently step over @FIX code, just like AIX dbx does.
2213 Unfortunately, the linker uses the "b" instruction for the
2214 branches, meaning that the link register doesn't get set.
2215 Therefore, GDB's usual step_over_function () mechanism won't work.
2217 Instead, use the gdbarch_skip_trampoline_code and
2218 gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past
2222 rs6000_in_solib_return_trampoline (struct gdbarch
*gdbarch
,
2223 CORE_ADDR pc
, const char *name
)
2225 return name
&& startswith (name
, "@FIX");
2228 /* Skip code that the user doesn't want to see when stepping:
2230 1. Indirect function calls use a piece of trampoline code to do context
2231 switching, i.e. to set the new TOC table. Skip such code if we are on
2232 its first instruction (as when we have single-stepped to here).
2234 2. Skip shared library trampoline code (which is different from
2235 indirect function call trampolines).
2237 3. Skip bigtoc fixup code.
2239 Result is desired PC to step until, or NULL if we are not in
2240 code that should be skipped. */
2243 rs6000_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
2245 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2246 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2247 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2248 unsigned int ii
, op
;
2250 CORE_ADDR solib_target_pc
;
2251 struct bound_minimal_symbol msymbol
;
2253 static unsigned trampoline_code
[] =
2255 0x800b0000, /* l r0,0x0(r11) */
2256 0x90410014, /* st r2,0x14(r1) */
2257 0x7c0903a6, /* mtctr r0 */
2258 0x804b0004, /* l r2,0x4(r11) */
2259 0x816b0008, /* l r11,0x8(r11) */
2260 0x4e800420, /* bctr */
2261 0x4e800020, /* br */
2265 /* Check for bigtoc fixup code. */
2266 msymbol
= lookup_minimal_symbol_by_pc (pc
);
2268 && rs6000_in_solib_return_trampoline (gdbarch
, pc
,
2269 msymbol
.minsym
->linkage_name ()))
2271 /* Double-check that the third instruction from PC is relative "b". */
2272 op
= read_memory_integer (pc
+ 8, 4, byte_order
);
2273 if ((op
& 0xfc000003) == 0x48000000)
2275 /* Extract bits 6-29 as a signed 24-bit relative word address and
2276 add it to the containing PC. */
2277 rel
= ((int)(op
<< 6) >> 6);
2278 return pc
+ 8 + rel
;
2282 /* If pc is in a shared library trampoline, return its target. */
2283 solib_target_pc
= find_solib_trampoline_target (frame
, pc
);
2284 if (solib_target_pc
)
2285 return solib_target_pc
;
2287 for (ii
= 0; trampoline_code
[ii
]; ++ii
)
2289 op
= read_memory_integer (pc
+ (ii
* 4), 4, byte_order
);
2290 if (op
!= trampoline_code
[ii
])
2293 ii
= get_frame_register_unsigned (frame
, 11); /* r11 holds destination
2295 pc
= read_memory_unsigned_integer (ii
, tdep
->wordsize
, byte_order
);
2299 /* ISA-specific vector types. */
2301 static struct type
*
2302 rs6000_builtin_type_vec64 (struct gdbarch
*gdbarch
)
2304 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2306 if (!tdep
->ppc_builtin_type_vec64
)
2308 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2310 /* The type we're building is this: */
2312 union __gdb_builtin_type_vec64
2316 int32_t v2_int32
[2];
2317 int16_t v4_int16
[4];
2324 t
= arch_composite_type (gdbarch
,
2325 "__ppc_builtin_type_vec64", TYPE_CODE_UNION
);
2326 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2327 append_composite_type_field (t
, "v2_float",
2328 init_vector_type (bt
->builtin_float
, 2));
2329 append_composite_type_field (t
, "v2_int32",
2330 init_vector_type (bt
->builtin_int32
, 2));
2331 append_composite_type_field (t
, "v4_int16",
2332 init_vector_type (bt
->builtin_int16
, 4));
2333 append_composite_type_field (t
, "v8_int8",
2334 init_vector_type (bt
->builtin_int8
, 8));
2336 t
->set_is_vector (true);
2337 t
->set_name ("ppc_builtin_type_vec64");
2338 tdep
->ppc_builtin_type_vec64
= t
;
2341 return tdep
->ppc_builtin_type_vec64
;
2344 /* Vector 128 type. */
2346 static struct type
*
2347 rs6000_builtin_type_vec128 (struct gdbarch
*gdbarch
)
2349 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2351 if (!tdep
->ppc_builtin_type_vec128
)
2353 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2355 /* The type we're building is this
2357 type = union __ppc_builtin_type_vec128 {
2359 double v2_double[2];
2361 int32_t v4_int32[4];
2362 int16_t v8_int16[8];
2363 int8_t v16_int8[16];
2369 t
= arch_composite_type (gdbarch
,
2370 "__ppc_builtin_type_vec128", TYPE_CODE_UNION
);
2371 append_composite_type_field (t
, "uint128", bt
->builtin_uint128
);
2372 append_composite_type_field (t
, "v2_double",
2373 init_vector_type (bt
->builtin_double
, 2));
2374 append_composite_type_field (t
, "v4_float",
2375 init_vector_type (bt
->builtin_float
, 4));
2376 append_composite_type_field (t
, "v4_int32",
2377 init_vector_type (bt
->builtin_int32
, 4));
2378 append_composite_type_field (t
, "v8_int16",
2379 init_vector_type (bt
->builtin_int16
, 8));
2380 append_composite_type_field (t
, "v16_int8",
2381 init_vector_type (bt
->builtin_int8
, 16));
2383 t
->set_is_vector (true);
2384 t
->set_name ("ppc_builtin_type_vec128");
2385 tdep
->ppc_builtin_type_vec128
= t
;
2388 return tdep
->ppc_builtin_type_vec128
;
2391 /* Return the name of register number REGNO, or the empty string if it
2392 is an anonymous register. */
2395 rs6000_register_name (struct gdbarch
*gdbarch
, int regno
)
2397 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2399 /* The upper half "registers" have names in the XML description,
2400 but we present only the low GPRs and the full 64-bit registers
2402 if (tdep
->ppc_ev0_upper_regnum
>= 0
2403 && tdep
->ppc_ev0_upper_regnum
<= regno
2404 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
2407 /* Hide the upper halves of the vs0~vs31 registers. */
2408 if (tdep
->ppc_vsr0_regnum
>= 0
2409 && tdep
->ppc_vsr0_upper_regnum
<= regno
2410 && regno
< tdep
->ppc_vsr0_upper_regnum
+ ppc_num_gprs
)
2413 /* Hide the upper halves of the cvs0~cvs31 registers. */
2414 if (PPC_CVSR0_UPPER_REGNUM
<= regno
2415 && regno
< PPC_CVSR0_UPPER_REGNUM
+ ppc_num_gprs
)
2418 /* Check if the SPE pseudo registers are available. */
2419 if (IS_SPE_PSEUDOREG (tdep
, regno
))
2421 static const char *const spe_regnames
[] = {
2422 "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7",
2423 "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15",
2424 "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23",
2425 "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31",
2427 return spe_regnames
[regno
- tdep
->ppc_ev0_regnum
];
2430 /* Check if the decimal128 pseudo-registers are available. */
2431 if (IS_DFP_PSEUDOREG (tdep
, regno
))
2433 static const char *const dfp128_regnames
[] = {
2434 "dl0", "dl1", "dl2", "dl3",
2435 "dl4", "dl5", "dl6", "dl7",
2436 "dl8", "dl9", "dl10", "dl11",
2437 "dl12", "dl13", "dl14", "dl15"
2439 return dfp128_regnames
[regno
- tdep
->ppc_dl0_regnum
];
2442 /* Check if this is a vX alias for a raw vrX vector register. */
2443 if (IS_V_ALIAS_PSEUDOREG (tdep
, regno
))
2445 static const char *const vector_alias_regnames
[] = {
2446 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
2447 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
2448 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
2449 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
2451 return vector_alias_regnames
[regno
- tdep
->ppc_v0_alias_regnum
];
2454 /* Check if this is a VSX pseudo-register. */
2455 if (IS_VSX_PSEUDOREG (tdep
, regno
))
2457 static const char *const vsx_regnames
[] = {
2458 "vs0", "vs1", "vs2", "vs3", "vs4", "vs5", "vs6", "vs7",
2459 "vs8", "vs9", "vs10", "vs11", "vs12", "vs13", "vs14",
2460 "vs15", "vs16", "vs17", "vs18", "vs19", "vs20", "vs21",
2461 "vs22", "vs23", "vs24", "vs25", "vs26", "vs27", "vs28",
2462 "vs29", "vs30", "vs31", "vs32", "vs33", "vs34", "vs35",
2463 "vs36", "vs37", "vs38", "vs39", "vs40", "vs41", "vs42",
2464 "vs43", "vs44", "vs45", "vs46", "vs47", "vs48", "vs49",
2465 "vs50", "vs51", "vs52", "vs53", "vs54", "vs55", "vs56",
2466 "vs57", "vs58", "vs59", "vs60", "vs61", "vs62", "vs63"
2468 return vsx_regnames
[regno
- tdep
->ppc_vsr0_regnum
];
2471 /* Check if the this is a Extended FP pseudo-register. */
2472 if (IS_EFP_PSEUDOREG (tdep
, regno
))
2474 static const char *const efpr_regnames
[] = {
2475 "f32", "f33", "f34", "f35", "f36", "f37", "f38",
2476 "f39", "f40", "f41", "f42", "f43", "f44", "f45",
2477 "f46", "f47", "f48", "f49", "f50", "f51",
2478 "f52", "f53", "f54", "f55", "f56", "f57",
2479 "f58", "f59", "f60", "f61", "f62", "f63"
2481 return efpr_regnames
[regno
- tdep
->ppc_efpr0_regnum
];
2484 /* Check if this is a Checkpointed DFP pseudo-register. */
2485 if (IS_CDFP_PSEUDOREG (tdep
, regno
))
2487 static const char *const cdfp128_regnames
[] = {
2488 "cdl0", "cdl1", "cdl2", "cdl3",
2489 "cdl4", "cdl5", "cdl6", "cdl7",
2490 "cdl8", "cdl9", "cdl10", "cdl11",
2491 "cdl12", "cdl13", "cdl14", "cdl15"
2493 return cdfp128_regnames
[regno
- tdep
->ppc_cdl0_regnum
];
2496 /* Check if this is a Checkpointed VSX pseudo-register. */
2497 if (IS_CVSX_PSEUDOREG (tdep
, regno
))
2499 static const char *const cvsx_regnames
[] = {
2500 "cvs0", "cvs1", "cvs2", "cvs3", "cvs4", "cvs5", "cvs6", "cvs7",
2501 "cvs8", "cvs9", "cvs10", "cvs11", "cvs12", "cvs13", "cvs14",
2502 "cvs15", "cvs16", "cvs17", "cvs18", "cvs19", "cvs20", "cvs21",
2503 "cvs22", "cvs23", "cvs24", "cvs25", "cvs26", "cvs27", "cvs28",
2504 "cvs29", "cvs30", "cvs31", "cvs32", "cvs33", "cvs34", "cvs35",
2505 "cvs36", "cvs37", "cvs38", "cvs39", "cvs40", "cvs41", "cvs42",
2506 "cvs43", "cvs44", "cvs45", "cvs46", "cvs47", "cvs48", "cvs49",
2507 "cvs50", "cvs51", "cvs52", "cvs53", "cvs54", "cvs55", "cvs56",
2508 "cvs57", "cvs58", "cvs59", "cvs60", "cvs61", "cvs62", "cvs63"
2510 return cvsx_regnames
[regno
- tdep
->ppc_cvsr0_regnum
];
2513 /* Check if the this is a Checkpointed Extended FP pseudo-register. */
2514 if (IS_CEFP_PSEUDOREG (tdep
, regno
))
2516 static const char *const cefpr_regnames
[] = {
2517 "cf32", "cf33", "cf34", "cf35", "cf36", "cf37", "cf38",
2518 "cf39", "cf40", "cf41", "cf42", "cf43", "cf44", "cf45",
2519 "cf46", "cf47", "cf48", "cf49", "cf50", "cf51",
2520 "cf52", "cf53", "cf54", "cf55", "cf56", "cf57",
2521 "cf58", "cf59", "cf60", "cf61", "cf62", "cf63"
2523 return cefpr_regnames
[regno
- tdep
->ppc_cefpr0_regnum
];
2526 return tdesc_register_name (gdbarch
, regno
);
2529 /* Return the GDB type object for the "standard" data type of data in
2532 static struct type
*
2533 rs6000_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2535 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2537 /* These are the e500 pseudo-registers. */
2538 if (IS_SPE_PSEUDOREG (tdep
, regnum
))
2539 return rs6000_builtin_type_vec64 (gdbarch
);
2540 else if (IS_DFP_PSEUDOREG (tdep
, regnum
)
2541 || IS_CDFP_PSEUDOREG (tdep
, regnum
))
2542 /* PPC decimal128 pseudo-registers. */
2543 return builtin_type (gdbarch
)->builtin_declong
;
2544 else if (IS_V_ALIAS_PSEUDOREG (tdep
, regnum
))
2545 return gdbarch_register_type (gdbarch
,
2546 tdep
->ppc_vr0_regnum
2548 - tdep
->ppc_v0_alias_regnum
));
2549 else if (IS_VSX_PSEUDOREG (tdep
, regnum
)
2550 || IS_CVSX_PSEUDOREG (tdep
, regnum
))
2551 /* POWER7 VSX pseudo-registers. */
2552 return rs6000_builtin_type_vec128 (gdbarch
);
2553 else if (IS_EFP_PSEUDOREG (tdep
, regnum
)
2554 || IS_CEFP_PSEUDOREG (tdep
, regnum
))
2555 /* POWER7 Extended FP pseudo-registers. */
2556 return builtin_type (gdbarch
)->builtin_double
;
2558 internal_error (__FILE__
, __LINE__
,
2559 _("rs6000_pseudo_register_type: "
2560 "called on unexpected register '%s' (%d)"),
2561 gdbarch_register_name (gdbarch
, regnum
), regnum
);
2564 /* Check if REGNUM is a member of REGGROUP. We only need to handle
2565 the vX aliases for the vector registers by always returning false
2566 to avoid duplicated information in "info register vector/all",
2567 since the raw vrX registers will already show in these cases. For
2568 other pseudo-registers we use the default membership function. */
2571 rs6000_pseudo_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2572 struct reggroup
*group
)
2574 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2576 if (IS_V_ALIAS_PSEUDOREG (tdep
, regnum
))
2579 return default_register_reggroup_p (gdbarch
, regnum
, group
);
2582 /* The register format for RS/6000 floating point registers is always
2583 double, we need a conversion if the memory format is float. */
2586 rs6000_convert_register_p (struct gdbarch
*gdbarch
, int regnum
,
2589 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2591 return (tdep
->ppc_fp0_regnum
>= 0
2592 && regnum
>= tdep
->ppc_fp0_regnum
2593 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
2594 && type
->code () == TYPE_CODE_FLT
2595 && TYPE_LENGTH (type
)
2596 != TYPE_LENGTH (builtin_type (gdbarch
)->builtin_double
));
2600 rs6000_register_to_value (struct frame_info
*frame
,
2604 int *optimizedp
, int *unavailablep
)
2606 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2607 gdb_byte from
[PPC_MAX_REGISTER_SIZE
];
2609 gdb_assert (type
->code () == TYPE_CODE_FLT
);
2611 if (!get_frame_register_bytes (frame
, regnum
, 0,
2612 gdb::make_array_view (from
,
2613 register_size (gdbarch
,
2615 optimizedp
, unavailablep
))
2618 target_float_convert (from
, builtin_type (gdbarch
)->builtin_double
,
2620 *optimizedp
= *unavailablep
= 0;
2625 rs6000_value_to_register (struct frame_info
*frame
,
2628 const gdb_byte
*from
)
2630 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2631 gdb_byte to
[PPC_MAX_REGISTER_SIZE
];
2633 gdb_assert (type
->code () == TYPE_CODE_FLT
);
2635 target_float_convert (from
, type
,
2636 to
, builtin_type (gdbarch
)->builtin_double
);
2637 put_frame_register (frame
, regnum
, to
);
2640 /* The type of a function that moves the value of REG between CACHE
2641 or BUF --- in either direction. */
2642 typedef enum register_status (*move_ev_register_func
) (struct regcache
*,
2645 /* Move SPE vector register values between a 64-bit buffer and the two
2646 32-bit raw register halves in a regcache. This function handles
2647 both splitting a 64-bit value into two 32-bit halves, and joining
2648 two halves into a whole 64-bit value, depending on the function
2649 passed as the MOVE argument.
2651 EV_REG must be the number of an SPE evN vector register --- a
2652 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2655 Call MOVE once for each 32-bit half of that register, passing
2656 REGCACHE, the number of the raw register corresponding to that
2657 half, and the address of the appropriate half of BUFFER.
2659 For example, passing 'regcache_raw_read' as the MOVE function will
2660 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2661 'regcache_raw_supply' will supply the contents of BUFFER to the
2662 appropriate pair of raw registers in REGCACHE.
2664 You may need to cast away some 'const' qualifiers when passing
2665 MOVE, since this function can't tell at compile-time which of
2666 REGCACHE or BUFFER is acting as the source of the data. If C had
2667 co-variant type qualifiers, ... */
2669 static enum register_status
2670 e500_move_ev_register (move_ev_register_func move
,
2671 struct regcache
*regcache
, int ev_reg
, void *buffer
)
2673 struct gdbarch
*arch
= regcache
->arch ();
2674 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
2676 gdb_byte
*byte_buffer
= (gdb_byte
*) buffer
;
2677 enum register_status status
;
2679 gdb_assert (IS_SPE_PSEUDOREG (tdep
, ev_reg
));
2681 reg_index
= ev_reg
- tdep
->ppc_ev0_regnum
;
2683 if (gdbarch_byte_order (arch
) == BFD_ENDIAN_BIG
)
2685 status
= move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2687 if (status
== REG_VALID
)
2688 status
= move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
,
2693 status
= move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
, byte_buffer
);
2694 if (status
== REG_VALID
)
2695 status
= move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2702 static enum register_status
2703 do_regcache_raw_write (struct regcache
*regcache
, int regnum
, void *buffer
)
2705 regcache
->raw_write (regnum
, (const gdb_byte
*) buffer
);
2710 static enum register_status
2711 e500_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2712 int ev_reg
, gdb_byte
*buffer
)
2714 struct gdbarch
*arch
= regcache
->arch ();
2715 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
2717 enum register_status status
;
2719 gdb_assert (IS_SPE_PSEUDOREG (tdep
, ev_reg
));
2721 reg_index
= ev_reg
- tdep
->ppc_ev0_regnum
;
2723 if (gdbarch_byte_order (arch
) == BFD_ENDIAN_BIG
)
2725 status
= regcache
->raw_read (tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2727 if (status
== REG_VALID
)
2728 status
= regcache
->raw_read (tdep
->ppc_gp0_regnum
+ reg_index
,
2733 status
= regcache
->raw_read (tdep
->ppc_gp0_regnum
+ reg_index
, buffer
);
2734 if (status
== REG_VALID
)
2735 status
= regcache
->raw_read (tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2744 e500_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2745 int reg_nr
, const gdb_byte
*buffer
)
2747 e500_move_ev_register (do_regcache_raw_write
, regcache
,
2748 reg_nr
, (void *) buffer
);
2751 /* Read method for DFP pseudo-registers. */
2752 static enum register_status
2753 dfp_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2754 int reg_nr
, gdb_byte
*buffer
)
2756 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2758 enum register_status status
;
2760 if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2762 reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2763 fp0
= PPC_F0_REGNUM
;
2767 gdb_assert (IS_CDFP_PSEUDOREG (tdep
, reg_nr
));
2769 reg_index
= reg_nr
- tdep
->ppc_cdl0_regnum
;
2770 fp0
= PPC_CF0_REGNUM
;
2773 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2775 /* Read two FP registers to form a whole dl register. */
2776 status
= regcache
->raw_read (fp0
+ 2 * reg_index
, buffer
);
2777 if (status
== REG_VALID
)
2778 status
= regcache
->raw_read (fp0
+ 2 * reg_index
+ 1,
2783 status
= regcache
->raw_read (fp0
+ 2 * reg_index
+ 1, buffer
);
2784 if (status
== REG_VALID
)
2785 status
= regcache
->raw_read (fp0
+ 2 * reg_index
, buffer
+ 8);
2791 /* Write method for DFP pseudo-registers. */
2793 dfp_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2794 int reg_nr
, const gdb_byte
*buffer
)
2796 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2799 if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2801 reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2802 fp0
= PPC_F0_REGNUM
;
2806 gdb_assert (IS_CDFP_PSEUDOREG (tdep
, reg_nr
));
2808 reg_index
= reg_nr
- tdep
->ppc_cdl0_regnum
;
2809 fp0
= PPC_CF0_REGNUM
;
2812 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2814 /* Write each half of the dl register into a separate
2816 regcache
->raw_write (fp0
+ 2 * reg_index
, buffer
);
2817 regcache
->raw_write (fp0
+ 2 * reg_index
+ 1, buffer
+ 8);
2821 regcache
->raw_write (fp0
+ 2 * reg_index
+ 1, buffer
);
2822 regcache
->raw_write (fp0
+ 2 * reg_index
, buffer
+ 8);
2826 /* Read method for the vX aliases for the raw vrX registers. */
2828 static enum register_status
2829 v_alias_pseudo_register_read (struct gdbarch
*gdbarch
,
2830 readable_regcache
*regcache
, int reg_nr
,
2833 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2834 gdb_assert (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
));
2836 return regcache
->raw_read (tdep
->ppc_vr0_regnum
2837 + (reg_nr
- tdep
->ppc_v0_alias_regnum
),
2841 /* Write method for the vX aliases for the raw vrX registers. */
2844 v_alias_pseudo_register_write (struct gdbarch
*gdbarch
,
2845 struct regcache
*regcache
,
2846 int reg_nr
, const gdb_byte
*buffer
)
2848 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2849 gdb_assert (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
));
2851 regcache
->raw_write (tdep
->ppc_vr0_regnum
2852 + (reg_nr
- tdep
->ppc_v0_alias_regnum
), buffer
);
2855 /* Read method for POWER7 VSX pseudo-registers. */
2856 static enum register_status
2857 vsx_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2858 int reg_nr
, gdb_byte
*buffer
)
2860 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2861 int reg_index
, vr0
, fp0
, vsr0_upper
;
2862 enum register_status status
;
2864 if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2866 reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2867 vr0
= PPC_VR0_REGNUM
;
2868 fp0
= PPC_F0_REGNUM
;
2869 vsr0_upper
= PPC_VSR0_UPPER_REGNUM
;
2873 gdb_assert (IS_CVSX_PSEUDOREG (tdep
, reg_nr
));
2875 reg_index
= reg_nr
- tdep
->ppc_cvsr0_regnum
;
2876 vr0
= PPC_CVR0_REGNUM
;
2877 fp0
= PPC_CF0_REGNUM
;
2878 vsr0_upper
= PPC_CVSR0_UPPER_REGNUM
;
2881 /* Read the portion that overlaps the VMX registers. */
2883 status
= regcache
->raw_read (vr0
+ reg_index
- 32, buffer
);
2885 /* Read the portion that overlaps the FPR registers. */
2886 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2888 status
= regcache
->raw_read (fp0
+ reg_index
, buffer
);
2889 if (status
== REG_VALID
)
2890 status
= regcache
->raw_read (vsr0_upper
+ reg_index
,
2895 status
= regcache
->raw_read (fp0
+ reg_index
, buffer
+ 8);
2896 if (status
== REG_VALID
)
2897 status
= regcache
->raw_read (vsr0_upper
+ reg_index
, buffer
);
2903 /* Write method for POWER7 VSX pseudo-registers. */
2905 vsx_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2906 int reg_nr
, const gdb_byte
*buffer
)
2908 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2909 int reg_index
, vr0
, fp0
, vsr0_upper
;
2911 if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2913 reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2914 vr0
= PPC_VR0_REGNUM
;
2915 fp0
= PPC_F0_REGNUM
;
2916 vsr0_upper
= PPC_VSR0_UPPER_REGNUM
;
2920 gdb_assert (IS_CVSX_PSEUDOREG (tdep
, reg_nr
));
2922 reg_index
= reg_nr
- tdep
->ppc_cvsr0_regnum
;
2923 vr0
= PPC_CVR0_REGNUM
;
2924 fp0
= PPC_CF0_REGNUM
;
2925 vsr0_upper
= PPC_CVSR0_UPPER_REGNUM
;
2928 /* Write the portion that overlaps the VMX registers. */
2930 regcache
->raw_write (vr0
+ reg_index
- 32, buffer
);
2932 /* Write the portion that overlaps the FPR registers. */
2933 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2935 regcache
->raw_write (fp0
+ reg_index
, buffer
);
2936 regcache
->raw_write (vsr0_upper
+ reg_index
, buffer
+ 8);
2940 regcache
->raw_write (fp0
+ reg_index
, buffer
+ 8);
2941 regcache
->raw_write (vsr0_upper
+ reg_index
, buffer
);
2945 /* Read method for POWER7 Extended FP pseudo-registers. */
2946 static enum register_status
2947 efp_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2948 int reg_nr
, gdb_byte
*buffer
)
2950 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2953 if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
2955 reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
2956 vr0
= PPC_VR0_REGNUM
;
2960 gdb_assert (IS_CEFP_PSEUDOREG (tdep
, reg_nr
));
2962 reg_index
= reg_nr
- tdep
->ppc_cefpr0_regnum
;
2963 vr0
= PPC_CVR0_REGNUM
;
2966 int offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 0 : 8;
2968 /* Read the portion that overlaps the VMX register. */
2969 return regcache
->raw_read_part (vr0
+ reg_index
, offset
,
2970 register_size (gdbarch
, reg_nr
),
2974 /* Write method for POWER7 Extended FP pseudo-registers. */
2976 efp_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2977 int reg_nr
, const gdb_byte
*buffer
)
2979 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2981 int offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 0 : 8;
2983 if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
2985 reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
2986 vr0
= PPC_VR0_REGNUM
;
2990 gdb_assert (IS_CEFP_PSEUDOREG (tdep
, reg_nr
));
2992 reg_index
= reg_nr
- tdep
->ppc_cefpr0_regnum
;
2993 vr0
= PPC_CVR0_REGNUM
;
2995 /* The call to raw_write_part fails silently if the initial read
2996 of the read-update-write sequence returns an invalid status,
2997 so we check this manually and throw an error if needed. */
2998 regcache
->raw_update (vr0
+ reg_index
);
2999 if (regcache
->get_register_status (vr0
+ reg_index
) != REG_VALID
)
3000 error (_("Cannot write to the checkpointed EFP register, "
3001 "the corresponding vector register is unavailable."));
3004 /* Write the portion that overlaps the VMX register. */
3005 regcache
->raw_write_part (vr0
+ reg_index
, offset
,
3006 register_size (gdbarch
, reg_nr
), buffer
);
3009 static enum register_status
3010 rs6000_pseudo_register_read (struct gdbarch
*gdbarch
,
3011 readable_regcache
*regcache
,
3012 int reg_nr
, gdb_byte
*buffer
)
3014 struct gdbarch
*regcache_arch
= regcache
->arch ();
3015 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3017 gdb_assert (regcache_arch
== gdbarch
);
3019 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
3020 return e500_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
3021 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
)
3022 || IS_CDFP_PSEUDOREG (tdep
, reg_nr
))
3023 return dfp_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
3024 else if (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
))
3025 return v_alias_pseudo_register_read (gdbarch
, regcache
, reg_nr
,
3027 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
)
3028 || IS_CVSX_PSEUDOREG (tdep
, reg_nr
))
3029 return vsx_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
3030 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
)
3031 || IS_CEFP_PSEUDOREG (tdep
, reg_nr
))
3032 return efp_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
3034 internal_error (__FILE__
, __LINE__
,
3035 _("rs6000_pseudo_register_read: "
3036 "called on unexpected register '%s' (%d)"),
3037 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
3041 rs6000_pseudo_register_write (struct gdbarch
*gdbarch
,
3042 struct regcache
*regcache
,
3043 int reg_nr
, const gdb_byte
*buffer
)
3045 struct gdbarch
*regcache_arch
= regcache
->arch ();
3046 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3048 gdb_assert (regcache_arch
== gdbarch
);
3050 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
3051 e500_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
3052 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
)
3053 || IS_CDFP_PSEUDOREG (tdep
, reg_nr
))
3054 dfp_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
3055 else if (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
))
3056 v_alias_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
3057 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
)
3058 || IS_CVSX_PSEUDOREG (tdep
, reg_nr
))
3059 vsx_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
3060 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
)
3061 || IS_CEFP_PSEUDOREG (tdep
, reg_nr
))
3062 efp_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
3064 internal_error (__FILE__
, __LINE__
,
3065 _("rs6000_pseudo_register_write: "
3066 "called on unexpected register '%s' (%d)"),
3067 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
3070 /* Set the register mask in AX with the registers that form the DFP or
3071 checkpointed DFP pseudo-register REG_NR. */
3074 dfp_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
3075 struct agent_expr
*ax
, int reg_nr
)
3077 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3080 if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
3082 reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
3083 fp0
= PPC_F0_REGNUM
;
3087 gdb_assert (IS_CDFP_PSEUDOREG (tdep
, reg_nr
));
3089 reg_index
= reg_nr
- tdep
->ppc_cdl0_regnum
;
3090 fp0
= PPC_CF0_REGNUM
;
3093 ax_reg_mask (ax
, fp0
+ 2 * reg_index
);
3094 ax_reg_mask (ax
, fp0
+ 2 * reg_index
+ 1);
3097 /* Set the register mask in AX with the raw vector register that
3098 corresponds to its REG_NR alias. */
3101 v_alias_pseudo_register_collect (struct gdbarch
*gdbarch
,
3102 struct agent_expr
*ax
, int reg_nr
)
3104 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3105 gdb_assert (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
));
3107 ax_reg_mask (ax
, tdep
->ppc_vr0_regnum
3108 + (reg_nr
- tdep
->ppc_v0_alias_regnum
));
3111 /* Set the register mask in AX with the registers that form the VSX or
3112 checkpointed VSX pseudo-register REG_NR. */
3115 vsx_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
3116 struct agent_expr
*ax
, int reg_nr
)
3118 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3119 int reg_index
, vr0
, fp0
, vsr0_upper
;
3121 if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
3123 reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
3124 vr0
= PPC_VR0_REGNUM
;
3125 fp0
= PPC_F0_REGNUM
;
3126 vsr0_upper
= PPC_VSR0_UPPER_REGNUM
;
3130 gdb_assert (IS_CVSX_PSEUDOREG (tdep
, reg_nr
));
3132 reg_index
= reg_nr
- tdep
->ppc_cvsr0_regnum
;
3133 vr0
= PPC_CVR0_REGNUM
;
3134 fp0
= PPC_CF0_REGNUM
;
3135 vsr0_upper
= PPC_CVSR0_UPPER_REGNUM
;
3140 ax_reg_mask (ax
, vr0
+ reg_index
- 32);
3144 ax_reg_mask (ax
, fp0
+ reg_index
);
3145 ax_reg_mask (ax
, vsr0_upper
+ reg_index
);
3149 /* Set the register mask in AX with the register that corresponds to
3150 the EFP or checkpointed EFP pseudo-register REG_NR. */
3153 efp_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
3154 struct agent_expr
*ax
, int reg_nr
)
3156 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3159 if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
3161 reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
3162 vr0
= PPC_VR0_REGNUM
;
3166 gdb_assert (IS_CEFP_PSEUDOREG (tdep
, reg_nr
));
3168 reg_index
= reg_nr
- tdep
->ppc_cefpr0_regnum
;
3169 vr0
= PPC_CVR0_REGNUM
;
3172 ax_reg_mask (ax
, vr0
+ reg_index
);
3176 rs6000_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
3177 struct agent_expr
*ax
, int reg_nr
)
3179 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3180 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
3182 int reg_index
= reg_nr
- tdep
->ppc_ev0_regnum
;
3183 ax_reg_mask (ax
, tdep
->ppc_gp0_regnum
+ reg_index
);
3184 ax_reg_mask (ax
, tdep
->ppc_ev0_upper_regnum
+ reg_index
);
3186 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
)
3187 || IS_CDFP_PSEUDOREG (tdep
, reg_nr
))
3189 dfp_ax_pseudo_register_collect (gdbarch
, ax
, reg_nr
);
3191 else if (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
))
3193 v_alias_pseudo_register_collect (gdbarch
, ax
, reg_nr
);
3195 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
)
3196 || IS_CVSX_PSEUDOREG (tdep
, reg_nr
))
3198 vsx_ax_pseudo_register_collect (gdbarch
, ax
, reg_nr
);
3200 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
)
3201 || IS_CEFP_PSEUDOREG (tdep
, reg_nr
))
3203 efp_ax_pseudo_register_collect (gdbarch
, ax
, reg_nr
);
3206 internal_error (__FILE__
, __LINE__
,
3207 _("rs6000_pseudo_register_collect: "
3208 "called on unexpected register '%s' (%d)"),
3209 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
3215 rs6000_gen_return_address (struct gdbarch
*gdbarch
,
3216 struct agent_expr
*ax
, struct axs_value
*value
,
3219 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3220 value
->type
= register_type (gdbarch
, tdep
->ppc_lr_regnum
);
3221 value
->kind
= axs_lvalue_register
;
3222 value
->u
.reg
= tdep
->ppc_lr_regnum
;
3226 /* Convert a DBX STABS register number to a GDB register number. */
3228 rs6000_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
3230 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3232 if (0 <= num
&& num
<= 31)
3233 return tdep
->ppc_gp0_regnum
+ num
;
3234 else if (32 <= num
&& num
<= 63)
3235 /* FIXME: jimb/2004-05-05: What should we do when the debug info
3236 specifies registers the architecture doesn't have? Our
3237 callers don't check the value we return. */
3238 return tdep
->ppc_fp0_regnum
+ (num
- 32);
3239 else if (77 <= num
&& num
<= 108)
3240 return tdep
->ppc_vr0_regnum
+ (num
- 77);
3241 else if (1200 <= num
&& num
< 1200 + 32)
3242 return tdep
->ppc_ev0_upper_regnum
+ (num
- 1200);
3247 return tdep
->ppc_mq_regnum
;
3249 return tdep
->ppc_lr_regnum
;
3251 return tdep
->ppc_ctr_regnum
;
3253 return tdep
->ppc_xer_regnum
;
3255 return tdep
->ppc_vrsave_regnum
;
3257 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
3259 return tdep
->ppc_acc_regnum
;
3261 return tdep
->ppc_spefscr_regnum
;
3268 /* Convert a Dwarf 2 register number to a GDB register number. */
3270 rs6000_dwarf2_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
3272 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3274 if (0 <= num
&& num
<= 31)
3275 return tdep
->ppc_gp0_regnum
+ num
;
3276 else if (32 <= num
&& num
<= 63)
3277 /* FIXME: jimb/2004-05-05: What should we do when the debug info
3278 specifies registers the architecture doesn't have? Our
3279 callers don't check the value we return. */
3280 return tdep
->ppc_fp0_regnum
+ (num
- 32);
3281 else if (1124 <= num
&& num
< 1124 + 32)
3282 return tdep
->ppc_vr0_regnum
+ (num
- 1124);
3283 else if (1200 <= num
&& num
< 1200 + 32)
3284 return tdep
->ppc_ev0_upper_regnum
+ (num
- 1200);
3289 return tdep
->ppc_cr_regnum
;
3291 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
3293 return tdep
->ppc_acc_regnum
;
3295 return tdep
->ppc_mq_regnum
;
3297 return tdep
->ppc_xer_regnum
;
3299 return tdep
->ppc_lr_regnum
;
3301 return tdep
->ppc_ctr_regnum
;
3303 return tdep
->ppc_vrsave_regnum
;
3305 return tdep
->ppc_spefscr_regnum
;
3308 /* Unknown DWARF register number. */
3312 /* Translate a .eh_frame register to DWARF register, or adjust a
3313 .debug_frame register. */
3316 rs6000_adjust_frame_regnum (struct gdbarch
*gdbarch
, int num
, int eh_frame_p
)
3318 /* GCC releases before 3.4 use GCC internal register numbering in
3319 .debug_frame (and .debug_info, et cetera). The numbering is
3320 different from the standard SysV numbering for everything except
3321 for GPRs and FPRs. We can not detect this problem in most cases
3322 - to get accurate debug info for variables living in lr, ctr, v0,
3323 et cetera, use a newer version of GCC. But we must detect
3324 one important case - lr is in column 65 in .debug_frame output,
3327 GCC 3.4, and the "hammer" branch, have a related problem. They
3328 record lr register saves in .debug_frame as 108, but still record
3329 the return column as 65. We fix that up too.
3331 We can do this because 65 is assigned to fpsr, and GCC never
3332 generates debug info referring to it. To add support for
3333 handwritten debug info that restores fpsr, we would need to add a
3334 producer version check to this. */
3343 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
3344 internal register numbering; translate that to the standard DWARF2
3345 register numbering. */
3346 if (0 <= num
&& num
<= 63) /* r0-r31,fp0-fp31 */
3348 else if (68 <= num
&& num
<= 75) /* cr0-cr8 */
3349 return num
- 68 + 86;
3350 else if (77 <= num
&& num
<= 108) /* vr0-vr31 */
3351 return num
- 77 + 1124;
3363 case 109: /* vrsave */
3365 case 110: /* vscr */
3367 case 111: /* spe_acc */
3369 case 112: /* spefscr */
3377 /* Handling the various POWER/PowerPC variants. */
3379 /* Information about a particular processor variant. */
3383 /* Name of this variant. */
3386 /* English description of the variant. */
3387 const char *description
;
3389 /* bfd_arch_info.arch corresponding to variant. */
3390 enum bfd_architecture arch
;
3392 /* bfd_arch_info.mach corresponding to variant. */
3395 /* Target description for this variant. */
3396 struct target_desc
**tdesc
;
3399 static struct ppc_variant variants
[] =
3401 {"powerpc", "PowerPC user-level", bfd_arch_powerpc
,
3402 bfd_mach_ppc
, &tdesc_powerpc_altivec32
},
3403 {"power", "POWER user-level", bfd_arch_rs6000
,
3404 bfd_mach_rs6k
, &tdesc_rs6000
},
3405 {"403", "IBM PowerPC 403", bfd_arch_powerpc
,
3406 bfd_mach_ppc_403
, &tdesc_powerpc_403
},
3407 {"405", "IBM PowerPC 405", bfd_arch_powerpc
,
3408 bfd_mach_ppc_405
, &tdesc_powerpc_405
},
3409 {"601", "Motorola PowerPC 601", bfd_arch_powerpc
,
3410 bfd_mach_ppc_601
, &tdesc_powerpc_601
},
3411 {"602", "Motorola PowerPC 602", bfd_arch_powerpc
,
3412 bfd_mach_ppc_602
, &tdesc_powerpc_602
},
3413 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc
,
3414 bfd_mach_ppc_603
, &tdesc_powerpc_603
},
3415 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc
,
3416 604, &tdesc_powerpc_604
},
3417 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc
,
3418 bfd_mach_ppc_403gc
, &tdesc_powerpc_403gc
},
3419 {"505", "Motorola PowerPC 505", bfd_arch_powerpc
,
3420 bfd_mach_ppc_505
, &tdesc_powerpc_505
},
3421 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc
,
3422 bfd_mach_ppc_860
, &tdesc_powerpc_860
},
3423 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc
,
3424 bfd_mach_ppc_750
, &tdesc_powerpc_750
},
3425 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc
,
3426 bfd_mach_ppc_7400
, &tdesc_powerpc_7400
},
3427 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc
,
3428 bfd_mach_ppc_e500
, &tdesc_powerpc_e500
},
3431 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc
,
3432 bfd_mach_ppc64
, &tdesc_powerpc_altivec64
},
3433 {"620", "Motorola PowerPC 620", bfd_arch_powerpc
,
3434 bfd_mach_ppc_620
, &tdesc_powerpc_64
},
3435 {"630", "Motorola PowerPC 630", bfd_arch_powerpc
,
3436 bfd_mach_ppc_630
, &tdesc_powerpc_64
},
3437 {"a35", "PowerPC A35", bfd_arch_powerpc
,
3438 bfd_mach_ppc_a35
, &tdesc_powerpc_64
},
3439 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc
,
3440 bfd_mach_ppc_rs64ii
, &tdesc_powerpc_64
},
3441 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc
,
3442 bfd_mach_ppc_rs64iii
, &tdesc_powerpc_64
},
3444 /* FIXME: I haven't checked the register sets of the following. */
3445 {"rs1", "IBM POWER RS1", bfd_arch_rs6000
,
3446 bfd_mach_rs6k_rs1
, &tdesc_rs6000
},
3447 {"rsc", "IBM POWER RSC", bfd_arch_rs6000
,
3448 bfd_mach_rs6k_rsc
, &tdesc_rs6000
},
3449 {"rs2", "IBM POWER RS2", bfd_arch_rs6000
,
3450 bfd_mach_rs6k_rs2
, &tdesc_rs6000
},
3452 {0, 0, (enum bfd_architecture
) 0, 0, 0}
3455 /* Return the variant corresponding to architecture ARCH and machine number
3456 MACH. If no such variant exists, return null. */
3458 static const struct ppc_variant
*
3459 find_variant_by_arch (enum bfd_architecture arch
, unsigned long mach
)
3461 const struct ppc_variant
*v
;
3463 for (v
= variants
; v
->name
; v
++)
3464 if (arch
== v
->arch
&& mach
== v
->mach
)
3472 struct rs6000_frame_cache
3475 CORE_ADDR initial_sp
;
3476 trad_frame_saved_reg
*saved_regs
;
3478 /* Set BASE_P to true if this frame cache is properly initialized.
3479 Otherwise set to false because some registers or memory cannot
3482 /* Cache PC for building unavailable frame. */
3486 static struct rs6000_frame_cache
*
3487 rs6000_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3489 struct rs6000_frame_cache
*cache
;
3490 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3491 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3492 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3493 struct rs6000_framedata fdata
;
3494 int wordsize
= tdep
->wordsize
;
3495 CORE_ADDR func
= 0, pc
= 0;
3497 if ((*this_cache
) != NULL
)
3498 return (struct rs6000_frame_cache
*) (*this_cache
);
3499 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
3500 (*this_cache
) = cache
;
3502 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3506 func
= get_frame_func (this_frame
);
3508 pc
= get_frame_pc (this_frame
);
3509 skip_prologue (gdbarch
, func
, pc
, &fdata
);
3511 /* Figure out the parent's stack pointer. */
3513 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
3514 address of the current frame. Things might be easier if the
3515 ->frame pointed to the outer-most address of the frame. In
3516 the mean time, the address of the prev frame is used as the
3517 base address of this frame. */
3518 cache
->base
= get_frame_register_unsigned
3519 (this_frame
, gdbarch_sp_regnum (gdbarch
));
3521 catch (const gdb_exception_error
&ex
)
3523 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
3525 return (struct rs6000_frame_cache
*) (*this_cache
);
3528 /* If the function appears to be frameless, check a couple of likely
3529 indicators that we have simply failed to find the frame setup.
3530 Two common cases of this are missing symbols (i.e.
3531 get_frame_func returns the wrong address or 0), and assembly
3532 stubs which have a fast exit path but set up a frame on the slow
3535 If the LR appears to return to this function, then presume that
3536 we have an ABI compliant frame that we failed to find. */
3537 if (fdata
.frameless
&& fdata
.lr_offset
== 0)
3542 saved_lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
3543 if (func
== 0 && saved_lr
== pc
)
3547 CORE_ADDR saved_func
= get_pc_function_start (saved_lr
);
3548 if (func
== saved_func
)
3554 fdata
.frameless
= 0;
3555 fdata
.lr_offset
= tdep
->lr_frame_offset
;
3559 if (!fdata
.frameless
)
3561 /* Frameless really means stackless. */
3564 if (safe_read_memory_unsigned_integer (cache
->base
, wordsize
,
3565 byte_order
, &backchain
))
3566 cache
->base
= (CORE_ADDR
) backchain
;
3569 cache
->saved_regs
[gdbarch_sp_regnum (gdbarch
)].set_value (cache
->base
);
3571 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
3572 All fpr's from saved_fpr to fp31 are saved. */
3574 if (fdata
.saved_fpr
>= 0)
3577 CORE_ADDR fpr_addr
= cache
->base
+ fdata
.fpr_offset
;
3579 /* If skip_prologue says floating-point registers were saved,
3580 but the current architecture has no floating-point registers,
3581 then that's strange. But we have no indices to even record
3582 the addresses under, so we just ignore it. */
3583 if (ppc_floating_point_unit_p (gdbarch
))
3584 for (i
= fdata
.saved_fpr
; i
< ppc_num_fprs
; i
++)
3586 cache
->saved_regs
[tdep
->ppc_fp0_regnum
+ i
].set_addr (fpr_addr
);
3591 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
3592 All gpr's from saved_gpr to gpr31 are saved (except during the
3595 if (fdata
.saved_gpr
>= 0)
3598 CORE_ADDR gpr_addr
= cache
->base
+ fdata
.gpr_offset
;
3599 for (i
= fdata
.saved_gpr
; i
< ppc_num_gprs
; i
++)
3601 if (fdata
.gpr_mask
& (1U << i
))
3602 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].set_addr (gpr_addr
);
3603 gpr_addr
+= wordsize
;
3607 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
3608 All vr's from saved_vr to vr31 are saved. */
3609 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
3611 if (fdata
.saved_vr
>= 0)
3614 CORE_ADDR vr_addr
= cache
->base
+ fdata
.vr_offset
;
3615 for (i
= fdata
.saved_vr
; i
< 32; i
++)
3617 cache
->saved_regs
[tdep
->ppc_vr0_regnum
+ i
].set_addr (vr_addr
);
3618 vr_addr
+= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
3623 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
3624 All vr's from saved_ev to ev31 are saved. ????? */
3625 if (tdep
->ppc_ev0_regnum
!= -1)
3627 if (fdata
.saved_ev
>= 0)
3630 CORE_ADDR ev_addr
= cache
->base
+ fdata
.ev_offset
;
3631 CORE_ADDR off
= (byte_order
== BFD_ENDIAN_BIG
? 4 : 0);
3633 for (i
= fdata
.saved_ev
; i
< ppc_num_gprs
; i
++)
3635 cache
->saved_regs
[tdep
->ppc_ev0_regnum
+ i
].set_addr (ev_addr
);
3636 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].set_addr (ev_addr
3638 ev_addr
+= register_size (gdbarch
, tdep
->ppc_ev0_regnum
);
3643 /* If != 0, fdata.cr_offset is the offset from the frame that
3645 if (fdata
.cr_offset
!= 0)
3646 cache
->saved_regs
[tdep
->ppc_cr_regnum
].set_addr (cache
->base
3649 /* If != 0, fdata.lr_offset is the offset from the frame that
3651 if (fdata
.lr_offset
!= 0)
3652 cache
->saved_regs
[tdep
->ppc_lr_regnum
].set_addr (cache
->base
3654 else if (fdata
.lr_register
!= -1)
3655 cache
->saved_regs
[tdep
->ppc_lr_regnum
].set_realreg (fdata
.lr_register
);
3656 /* The PC is found in the link register. */
3657 cache
->saved_regs
[gdbarch_pc_regnum (gdbarch
)] =
3658 cache
->saved_regs
[tdep
->ppc_lr_regnum
];
3660 /* If != 0, fdata.vrsave_offset is the offset from the frame that
3661 holds the VRSAVE. */
3662 if (fdata
.vrsave_offset
!= 0)
3663 cache
->saved_regs
[tdep
->ppc_vrsave_regnum
].set_addr (cache
->base
3664 + fdata
.vrsave_offset
);
3666 if (fdata
.alloca_reg
< 0)
3667 /* If no alloca register used, then fi->frame is the value of the
3668 %sp for this frame, and it is good enough. */
3670 = get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
3673 = get_frame_register_unsigned (this_frame
, fdata
.alloca_reg
);
3680 rs6000_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3681 struct frame_id
*this_id
)
3683 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3688 (*this_id
) = frame_id_build_unavailable_stack (info
->pc
);
3692 /* This marks the outermost frame. */
3693 if (info
->base
== 0)
3696 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3699 static struct value
*
3700 rs6000_frame_prev_register (struct frame_info
*this_frame
,
3701 void **this_cache
, int regnum
)
3703 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3705 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3708 static const struct frame_unwind rs6000_frame_unwind
=
3711 default_frame_unwind_stop_reason
,
3712 rs6000_frame_this_id
,
3713 rs6000_frame_prev_register
,
3715 default_frame_sniffer
3718 /* Allocate and initialize a frame cache for an epilogue frame.
3719 SP is restored and prev-PC is stored in LR. */
3721 static struct rs6000_frame_cache
*
3722 rs6000_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3724 struct rs6000_frame_cache
*cache
;
3725 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3726 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3729 return (struct rs6000_frame_cache
*) *this_cache
;
3731 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
3732 (*this_cache
) = cache
;
3733 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3737 /* At this point the stack looks as if we just entered the
3738 function, and the return address is stored in LR. */
3741 sp
= get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
3742 lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
3745 cache
->initial_sp
= sp
;
3747 cache
->saved_regs
[gdbarch_pc_regnum (gdbarch
)].set_value (lr
);
3749 catch (const gdb_exception_error
&ex
)
3751 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
3758 /* Implementation of frame_unwind.this_id, as defined in frame_unwind.h.
3759 Return the frame ID of an epilogue frame. */
3762 rs6000_epilogue_frame_this_id (struct frame_info
*this_frame
,
3763 void **this_cache
, struct frame_id
*this_id
)
3766 struct rs6000_frame_cache
*info
=
3767 rs6000_epilogue_frame_cache (this_frame
, this_cache
);
3769 pc
= get_frame_func (this_frame
);
3770 if (info
->base
== 0)
3771 (*this_id
) = frame_id_build_unavailable_stack (pc
);
3773 (*this_id
) = frame_id_build (info
->base
, pc
);
3776 /* Implementation of frame_unwind.prev_register, as defined in frame_unwind.h.
3777 Return the register value of REGNUM in previous frame. */
3779 static struct value
*
3780 rs6000_epilogue_frame_prev_register (struct frame_info
*this_frame
,
3781 void **this_cache
, int regnum
)
3783 struct rs6000_frame_cache
*info
=
3784 rs6000_epilogue_frame_cache (this_frame
, this_cache
);
3785 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3788 /* Implementation of frame_unwind.sniffer, as defined in frame_unwind.h.
3789 Check whether this an epilogue frame. */
3792 rs6000_epilogue_frame_sniffer (const struct frame_unwind
*self
,
3793 struct frame_info
*this_frame
,
3794 void **this_prologue_cache
)
3796 if (frame_relative_level (this_frame
) == 0)
3797 return rs6000_in_function_epilogue_frame_p (this_frame
,
3798 get_frame_arch (this_frame
),
3799 get_frame_pc (this_frame
));
3804 /* Frame unwinder for epilogue frame. This is required for reverse step-over
3805 a function without debug information. */
3807 static const struct frame_unwind rs6000_epilogue_frame_unwind
=
3810 default_frame_unwind_stop_reason
,
3811 rs6000_epilogue_frame_this_id
, rs6000_epilogue_frame_prev_register
,
3813 rs6000_epilogue_frame_sniffer
3818 rs6000_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
3820 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3822 return info
->initial_sp
;
3825 static const struct frame_base rs6000_frame_base
= {
3826 &rs6000_frame_unwind
,
3827 rs6000_frame_base_address
,
3828 rs6000_frame_base_address
,
3829 rs6000_frame_base_address
3832 static const struct frame_base
*
3833 rs6000_frame_base_sniffer (struct frame_info
*this_frame
)
3835 return &rs6000_frame_base
;
3838 /* DWARF-2 frame support. Used to handle the detection of
3839 clobbered registers during function calls. */
3842 ppc_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
3843 struct dwarf2_frame_state_reg
*reg
,
3844 struct frame_info
*this_frame
)
3846 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3848 /* PPC32 and PPC64 ABI's are the same regarding volatile and
3849 non-volatile registers. We will use the same code for both. */
3851 /* Call-saved GP registers. */
3852 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 14
3853 && regnum
<= tdep
->ppc_gp0_regnum
+ 31)
3854 || (regnum
== tdep
->ppc_gp0_regnum
+ 1))
3855 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3857 /* Call-clobbered GP registers. */
3858 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 3
3859 && regnum
<= tdep
->ppc_gp0_regnum
+ 12)
3860 || (regnum
== tdep
->ppc_gp0_regnum
))
3861 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3863 /* Deal with FP registers, if supported. */
3864 if (tdep
->ppc_fp0_regnum
>= 0)
3866 /* Call-saved FP registers. */
3867 if ((regnum
>= tdep
->ppc_fp0_regnum
+ 14
3868 && regnum
<= tdep
->ppc_fp0_regnum
+ 31))
3869 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3871 /* Call-clobbered FP registers. */
3872 if ((regnum
>= tdep
->ppc_fp0_regnum
3873 && regnum
<= tdep
->ppc_fp0_regnum
+ 13))
3874 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3877 /* Deal with ALTIVEC registers, if supported. */
3878 if (tdep
->ppc_vr0_regnum
> 0 && tdep
->ppc_vrsave_regnum
> 0)
3880 /* Call-saved Altivec registers. */
3881 if ((regnum
>= tdep
->ppc_vr0_regnum
+ 20
3882 && regnum
<= tdep
->ppc_vr0_regnum
+ 31)
3883 || regnum
== tdep
->ppc_vrsave_regnum
)
3884 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3886 /* Call-clobbered Altivec registers. */
3887 if ((regnum
>= tdep
->ppc_vr0_regnum
3888 && regnum
<= tdep
->ppc_vr0_regnum
+ 19))
3889 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3892 /* Handle PC register and Stack Pointer correctly. */
3893 if (regnum
== gdbarch_pc_regnum (gdbarch
))
3894 reg
->how
= DWARF2_FRAME_REG_RA
;
3895 else if (regnum
== gdbarch_sp_regnum (gdbarch
))
3896 reg
->how
= DWARF2_FRAME_REG_CFA
;
3900 /* Return true if a .gnu_attributes section exists in BFD and it
3901 indicates we are using SPE extensions OR if a .PPC.EMB.apuinfo
3902 section exists in BFD and it indicates that SPE extensions are in
3903 use. Check the .gnu.attributes section first, as the binary might be
3904 compiled for SPE, but not actually using SPE instructions. */
3907 bfd_uses_spe_extensions (bfd
*abfd
)
3910 gdb_byte
*contents
= NULL
;
3919 /* Using Tag_GNU_Power_ABI_Vector here is a bit of a hack, as the user
3920 could be using the SPE vector abi without actually using any spe
3921 bits whatsoever. But it's close enough for now. */
3922 int vector_abi
= bfd_elf_get_obj_attr_int (abfd
, OBJ_ATTR_GNU
,
3923 Tag_GNU_Power_ABI_Vector
);
3924 if (vector_abi
== 3)
3928 sect
= bfd_get_section_by_name (abfd
, ".PPC.EMB.apuinfo");
3932 size
= bfd_section_size (sect
);
3933 contents
= (gdb_byte
*) xmalloc (size
);
3934 if (!bfd_get_section_contents (abfd
, sect
, contents
, 0, size
))
3940 /* Parse the .PPC.EMB.apuinfo section. The layout is as follows:
3946 char name[name_len rounded up to 4-byte alignment];
3947 char data[data_len];
3950 Technically, there's only supposed to be one such structure in a
3951 given apuinfo section, but the linker is not always vigilant about
3952 merging apuinfo sections from input files. Just go ahead and parse
3953 them all, exiting early when we discover the binary uses SPE
3956 It's not specified in what endianness the information in this
3957 section is stored. Assume that it's the endianness of the BFD. */
3961 unsigned int name_len
;
3962 unsigned int data_len
;
3965 /* If we can't read the first three fields, we're done. */
3969 name_len
= bfd_get_32 (abfd
, ptr
);
3970 name_len
= (name_len
+ 3) & ~3U; /* Round to 4 bytes. */
3971 data_len
= bfd_get_32 (abfd
, ptr
+ 4);
3972 type
= bfd_get_32 (abfd
, ptr
+ 8);
3975 /* The name must be "APUinfo\0". */
3977 && strcmp ((const char *) ptr
, "APUinfo") != 0)
3981 /* The type must be 2. */
3985 /* The data is stored as a series of uint32. The upper half of
3986 each uint32 indicates the particular APU used and the lower
3987 half indicates the revision of that APU. We just care about
3990 /* Not 4-byte quantities. */
3996 unsigned int apuinfo
= bfd_get_32 (abfd
, ptr
);
3997 unsigned int apu
= apuinfo
>> 16;
4001 /* The SPE APU is 0x100; the SPEFP APU is 0x101. Accept
4003 if (apu
== 0x100 || apu
== 0x101)
4018 /* These are macros for parsing instruction fields (I.1.6.28) */
4020 #define PPC_FIELD(value, from, len) \
4021 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
4022 #define PPC_SEXT(v, bs) \
4023 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
4024 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
4025 - ((CORE_ADDR) 1 << ((bs) - 1)))
4026 #define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
4027 #define PPC_EXTOP(insn) PPC_FIELD (insn, 21, 10)
4028 #define PPC_RT(insn) PPC_FIELD (insn, 6, 5)
4029 #define PPC_RS(insn) PPC_FIELD (insn, 6, 5)
4030 #define PPC_RA(insn) PPC_FIELD (insn, 11, 5)
4031 #define PPC_RB(insn) PPC_FIELD (insn, 16, 5)
4032 #define PPC_NB(insn) PPC_FIELD (insn, 16, 5)
4033 #define PPC_VRT(insn) PPC_FIELD (insn, 6, 5)
4034 #define PPC_FRT(insn) PPC_FIELD (insn, 6, 5)
4035 #define PPC_SPR(insn) (PPC_FIELD (insn, 11, 5) \
4036 | (PPC_FIELD (insn, 16, 5) << 5))
4037 #define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
4038 #define PPC_T(insn) PPC_FIELD (insn, 6, 5)
4039 #define PPC_D(insn) PPC_SEXT (PPC_FIELD (insn, 16, 16), 16)
4040 #define PPC_DS(insn) PPC_SEXT (PPC_FIELD (insn, 16, 14), 14)
4041 #define PPC_DQ(insn) PPC_SEXT (PPC_FIELD (insn, 16, 12), 12)
4042 #define PPC_BIT(insn,n) ((insn & (1 << (31 - (n)))) ? 1 : 0)
4043 #define PPC_OE(insn) PPC_BIT (insn, 21)
4044 #define PPC_RC(insn) PPC_BIT (insn, 31)
4045 #define PPC_Rc(insn) PPC_BIT (insn, 21)
4046 #define PPC_LK(insn) PPC_BIT (insn, 31)
4047 #define PPC_TX(insn) PPC_BIT (insn, 31)
4048 #define PPC_LEV(insn) PPC_FIELD (insn, 20, 7)
4050 #define PPC_XT(insn) ((PPC_TX (insn) << 5) | PPC_T (insn))
4051 #define PPC_XER_NB(xer) (xer & 0x7f)
4053 /* Record Vector-Scalar Registers.
4054 For VSR less than 32, it's represented by an FPR and an VSR-upper register.
4055 Otherwise, it's just a VR register. Record them accordingly. */
4058 ppc_record_vsr (struct regcache
*regcache
, struct gdbarch_tdep
*tdep
, int vsr
)
4060 if (vsr
< 0 || vsr
>= 64)
4065 if (tdep
->ppc_vr0_regnum
>= 0)
4066 record_full_arch_list_add_reg (regcache
, tdep
->ppc_vr0_regnum
+ vsr
- 32);
4070 if (tdep
->ppc_fp0_regnum
>= 0)
4071 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fp0_regnum
+ vsr
);
4072 if (tdep
->ppc_vsr0_upper_regnum
>= 0)
4073 record_full_arch_list_add_reg (regcache
,
4074 tdep
->ppc_vsr0_upper_regnum
+ vsr
);
4080 /* Parse and record instructions primary opcode-4 at ADDR.
4081 Return 0 if successful. */
4084 ppc_process_record_op4 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4085 CORE_ADDR addr
, uint32_t insn
)
4087 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4088 int ext
= PPC_FIELD (insn
, 21, 11);
4089 int vra
= PPC_FIELD (insn
, 11, 5);
4093 case 32: /* Vector Multiply-High-Add Signed Halfword Saturate */
4094 case 33: /* Vector Multiply-High-Round-Add Signed Halfword Saturate */
4095 case 39: /* Vector Multiply-Sum Unsigned Halfword Saturate */
4096 case 41: /* Vector Multiply-Sum Signed Halfword Saturate */
4097 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
4099 case 42: /* Vector Select */
4100 case 43: /* Vector Permute */
4101 case 59: /* Vector Permute Right-indexed */
4102 case 44: /* Vector Shift Left Double by Octet Immediate */
4103 case 45: /* Vector Permute and Exclusive-OR */
4104 case 60: /* Vector Add Extended Unsigned Quadword Modulo */
4105 case 61: /* Vector Add Extended & write Carry Unsigned Quadword */
4106 case 62: /* Vector Subtract Extended Unsigned Quadword Modulo */
4107 case 63: /* Vector Subtract Extended & write Carry Unsigned Quadword */
4108 case 34: /* Vector Multiply-Low-Add Unsigned Halfword Modulo */
4109 case 35: /* Vector Multiply-Sum Unsigned Doubleword Modulo */
4110 case 36: /* Vector Multiply-Sum Unsigned Byte Modulo */
4111 case 37: /* Vector Multiply-Sum Mixed Byte Modulo */
4112 case 38: /* Vector Multiply-Sum Unsigned Halfword Modulo */
4113 case 40: /* Vector Multiply-Sum Signed Halfword Modulo */
4114 case 46: /* Vector Multiply-Add Single-Precision */
4115 case 47: /* Vector Negative Multiply-Subtract Single-Precision */
4116 record_full_arch_list_add_reg (regcache
,
4117 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4120 case 48: /* Multiply-Add High Doubleword */
4121 case 49: /* Multiply-Add High Doubleword Unsigned */
4122 case 51: /* Multiply-Add Low Doubleword */
4123 record_full_arch_list_add_reg (regcache
,
4124 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4128 switch ((ext
& 0x1ff))
4131 if (vra
!= 0 /* Decimal Convert To Signed Quadword */
4132 && vra
!= 2 /* Decimal Convert From Signed Quadword */
4133 && vra
!= 4 /* Decimal Convert To Zoned */
4134 && vra
!= 5 /* Decimal Convert To National */
4135 && vra
!= 6 /* Decimal Convert From Zoned */
4136 && vra
!= 7 /* Decimal Convert From National */
4137 && vra
!= 31) /* Decimal Set Sign */
4140 /* 5.16 Decimal Integer Arithmetic Instructions */
4141 case 1: /* Decimal Add Modulo */
4142 case 65: /* Decimal Subtract Modulo */
4144 case 193: /* Decimal Shift */
4145 case 129: /* Decimal Unsigned Shift */
4146 case 449: /* Decimal Shift and Round */
4148 case 257: /* Decimal Truncate */
4149 case 321: /* Decimal Unsigned Truncate */
4151 /* Bit-21 should be set. */
4152 if (!PPC_BIT (insn
, 21))
4155 record_full_arch_list_add_reg (regcache
,
4156 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4157 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4161 /* Bit-21 is used for RC */
4162 switch (ext
& 0x3ff)
4164 case 6: /* Vector Compare Equal To Unsigned Byte */
4165 case 70: /* Vector Compare Equal To Unsigned Halfword */
4166 case 134: /* Vector Compare Equal To Unsigned Word */
4167 case 199: /* Vector Compare Equal To Unsigned Doubleword */
4168 case 774: /* Vector Compare Greater Than Signed Byte */
4169 case 838: /* Vector Compare Greater Than Signed Halfword */
4170 case 902: /* Vector Compare Greater Than Signed Word */
4171 case 967: /* Vector Compare Greater Than Signed Doubleword */
4172 case 518: /* Vector Compare Greater Than Unsigned Byte */
4173 case 646: /* Vector Compare Greater Than Unsigned Word */
4174 case 582: /* Vector Compare Greater Than Unsigned Halfword */
4175 case 711: /* Vector Compare Greater Than Unsigned Doubleword */
4176 case 966: /* Vector Compare Bounds Single-Precision */
4177 case 198: /* Vector Compare Equal To Single-Precision */
4178 case 454: /* Vector Compare Greater Than or Equal To Single-Precision */
4179 case 710: /* Vector Compare Greater Than Single-Precision */
4180 case 7: /* Vector Compare Not Equal Byte */
4181 case 71: /* Vector Compare Not Equal Halfword */
4182 case 135: /* Vector Compare Not Equal Word */
4183 case 263: /* Vector Compare Not Equal or Zero Byte */
4184 case 327: /* Vector Compare Not Equal or Zero Halfword */
4185 case 391: /* Vector Compare Not Equal or Zero Word */
4187 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4188 record_full_arch_list_add_reg (regcache
,
4189 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4197 case 0: /* Vector Count Leading Zero Least-Significant Bits
4199 case 1: /* Vector Count Trailing Zero Least-Significant Bits
4201 record_full_arch_list_add_reg (regcache
,
4202 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4205 case 6: /* Vector Negate Word */
4206 case 7: /* Vector Negate Doubleword */
4207 case 8: /* Vector Parity Byte Word */
4208 case 9: /* Vector Parity Byte Doubleword */
4209 case 10: /* Vector Parity Byte Quadword */
4210 case 16: /* Vector Extend Sign Byte To Word */
4211 case 17: /* Vector Extend Sign Halfword To Word */
4212 case 24: /* Vector Extend Sign Byte To Doubleword */
4213 case 25: /* Vector Extend Sign Halfword To Doubleword */
4214 case 26: /* Vector Extend Sign Word To Doubleword */
4215 case 28: /* Vector Count Trailing Zeros Byte */
4216 case 29: /* Vector Count Trailing Zeros Halfword */
4217 case 30: /* Vector Count Trailing Zeros Word */
4218 case 31: /* Vector Count Trailing Zeros Doubleword */
4219 record_full_arch_list_add_reg (regcache
,
4220 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4227 case 142: /* Vector Pack Unsigned Halfword Unsigned Saturate */
4228 case 206: /* Vector Pack Unsigned Word Unsigned Saturate */
4229 case 270: /* Vector Pack Signed Halfword Unsigned Saturate */
4230 case 334: /* Vector Pack Signed Word Unsigned Saturate */
4231 case 398: /* Vector Pack Signed Halfword Signed Saturate */
4232 case 462: /* Vector Pack Signed Word Signed Saturate */
4233 case 1230: /* Vector Pack Unsigned Doubleword Unsigned Saturate */
4234 case 1358: /* Vector Pack Signed Doubleword Unsigned Saturate */
4235 case 1486: /* Vector Pack Signed Doubleword Signed Saturate */
4236 case 512: /* Vector Add Unsigned Byte Saturate */
4237 case 576: /* Vector Add Unsigned Halfword Saturate */
4238 case 640: /* Vector Add Unsigned Word Saturate */
4239 case 768: /* Vector Add Signed Byte Saturate */
4240 case 832: /* Vector Add Signed Halfword Saturate */
4241 case 896: /* Vector Add Signed Word Saturate */
4242 case 1536: /* Vector Subtract Unsigned Byte Saturate */
4243 case 1600: /* Vector Subtract Unsigned Halfword Saturate */
4244 case 1664: /* Vector Subtract Unsigned Word Saturate */
4245 case 1792: /* Vector Subtract Signed Byte Saturate */
4246 case 1856: /* Vector Subtract Signed Halfword Saturate */
4247 case 1920: /* Vector Subtract Signed Word Saturate */
4249 case 1544: /* Vector Sum across Quarter Unsigned Byte Saturate */
4250 case 1800: /* Vector Sum across Quarter Signed Byte Saturate */
4251 case 1608: /* Vector Sum across Quarter Signed Halfword Saturate */
4252 case 1672: /* Vector Sum across Half Signed Word Saturate */
4253 case 1928: /* Vector Sum across Signed Word Saturate */
4254 case 970: /* Vector Convert To Signed Fixed-Point Word Saturate */
4255 case 906: /* Vector Convert To Unsigned Fixed-Point Word Saturate */
4256 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
4258 case 12: /* Vector Merge High Byte */
4259 case 14: /* Vector Pack Unsigned Halfword Unsigned Modulo */
4260 case 76: /* Vector Merge High Halfword */
4261 case 78: /* Vector Pack Unsigned Word Unsigned Modulo */
4262 case 140: /* Vector Merge High Word */
4263 case 268: /* Vector Merge Low Byte */
4264 case 332: /* Vector Merge Low Halfword */
4265 case 396: /* Vector Merge Low Word */
4266 case 526: /* Vector Unpack High Signed Byte */
4267 case 590: /* Vector Unpack High Signed Halfword */
4268 case 654: /* Vector Unpack Low Signed Byte */
4269 case 718: /* Vector Unpack Low Signed Halfword */
4270 case 782: /* Vector Pack Pixel */
4271 case 846: /* Vector Unpack High Pixel */
4272 case 974: /* Vector Unpack Low Pixel */
4273 case 1102: /* Vector Pack Unsigned Doubleword Unsigned Modulo */
4274 case 1614: /* Vector Unpack High Signed Word */
4275 case 1676: /* Vector Merge Odd Word */
4276 case 1742: /* Vector Unpack Low Signed Word */
4277 case 1932: /* Vector Merge Even Word */
4278 case 524: /* Vector Splat Byte */
4279 case 588: /* Vector Splat Halfword */
4280 case 652: /* Vector Splat Word */
4281 case 780: /* Vector Splat Immediate Signed Byte */
4282 case 844: /* Vector Splat Immediate Signed Halfword */
4283 case 908: /* Vector Splat Immediate Signed Word */
4284 case 452: /* Vector Shift Left */
4285 case 708: /* Vector Shift Right */
4286 case 1036: /* Vector Shift Left by Octet */
4287 case 1100: /* Vector Shift Right by Octet */
4288 case 0: /* Vector Add Unsigned Byte Modulo */
4289 case 64: /* Vector Add Unsigned Halfword Modulo */
4290 case 128: /* Vector Add Unsigned Word Modulo */
4291 case 192: /* Vector Add Unsigned Doubleword Modulo */
4292 case 256: /* Vector Add Unsigned Quadword Modulo */
4293 case 320: /* Vector Add & write Carry Unsigned Quadword */
4294 case 384: /* Vector Add and Write Carry-Out Unsigned Word */
4295 case 8: /* Vector Multiply Odd Unsigned Byte */
4296 case 72: /* Vector Multiply Odd Unsigned Halfword */
4297 case 136: /* Vector Multiply Odd Unsigned Word */
4298 case 264: /* Vector Multiply Odd Signed Byte */
4299 case 328: /* Vector Multiply Odd Signed Halfword */
4300 case 392: /* Vector Multiply Odd Signed Word */
4301 case 520: /* Vector Multiply Even Unsigned Byte */
4302 case 584: /* Vector Multiply Even Unsigned Halfword */
4303 case 648: /* Vector Multiply Even Unsigned Word */
4304 case 776: /* Vector Multiply Even Signed Byte */
4305 case 840: /* Vector Multiply Even Signed Halfword */
4306 case 904: /* Vector Multiply Even Signed Word */
4307 case 137: /* Vector Multiply Unsigned Word Modulo */
4308 case 1024: /* Vector Subtract Unsigned Byte Modulo */
4309 case 1088: /* Vector Subtract Unsigned Halfword Modulo */
4310 case 1152: /* Vector Subtract Unsigned Word Modulo */
4311 case 1216: /* Vector Subtract Unsigned Doubleword Modulo */
4312 case 1280: /* Vector Subtract Unsigned Quadword Modulo */
4313 case 1344: /* Vector Subtract & write Carry Unsigned Quadword */
4314 case 1408: /* Vector Subtract and Write Carry-Out Unsigned Word */
4315 case 1282: /* Vector Average Signed Byte */
4316 case 1346: /* Vector Average Signed Halfword */
4317 case 1410: /* Vector Average Signed Word */
4318 case 1026: /* Vector Average Unsigned Byte */
4319 case 1090: /* Vector Average Unsigned Halfword */
4320 case 1154: /* Vector Average Unsigned Word */
4321 case 258: /* Vector Maximum Signed Byte */
4322 case 322: /* Vector Maximum Signed Halfword */
4323 case 386: /* Vector Maximum Signed Word */
4324 case 450: /* Vector Maximum Signed Doubleword */
4325 case 2: /* Vector Maximum Unsigned Byte */
4326 case 66: /* Vector Maximum Unsigned Halfword */
4327 case 130: /* Vector Maximum Unsigned Word */
4328 case 194: /* Vector Maximum Unsigned Doubleword */
4329 case 770: /* Vector Minimum Signed Byte */
4330 case 834: /* Vector Minimum Signed Halfword */
4331 case 898: /* Vector Minimum Signed Word */
4332 case 962: /* Vector Minimum Signed Doubleword */
4333 case 514: /* Vector Minimum Unsigned Byte */
4334 case 578: /* Vector Minimum Unsigned Halfword */
4335 case 642: /* Vector Minimum Unsigned Word */
4336 case 706: /* Vector Minimum Unsigned Doubleword */
4337 case 1028: /* Vector Logical AND */
4338 case 1668: /* Vector Logical Equivalent */
4339 case 1092: /* Vector Logical AND with Complement */
4340 case 1412: /* Vector Logical NAND */
4341 case 1348: /* Vector Logical OR with Complement */
4342 case 1156: /* Vector Logical OR */
4343 case 1284: /* Vector Logical NOR */
4344 case 1220: /* Vector Logical XOR */
4345 case 4: /* Vector Rotate Left Byte */
4346 case 132: /* Vector Rotate Left Word VX-form */
4347 case 68: /* Vector Rotate Left Halfword */
4348 case 196: /* Vector Rotate Left Doubleword */
4349 case 260: /* Vector Shift Left Byte */
4350 case 388: /* Vector Shift Left Word */
4351 case 324: /* Vector Shift Left Halfword */
4352 case 1476: /* Vector Shift Left Doubleword */
4353 case 516: /* Vector Shift Right Byte */
4354 case 644: /* Vector Shift Right Word */
4355 case 580: /* Vector Shift Right Halfword */
4356 case 1732: /* Vector Shift Right Doubleword */
4357 case 772: /* Vector Shift Right Algebraic Byte */
4358 case 900: /* Vector Shift Right Algebraic Word */
4359 case 836: /* Vector Shift Right Algebraic Halfword */
4360 case 964: /* Vector Shift Right Algebraic Doubleword */
4361 case 10: /* Vector Add Single-Precision */
4362 case 74: /* Vector Subtract Single-Precision */
4363 case 1034: /* Vector Maximum Single-Precision */
4364 case 1098: /* Vector Minimum Single-Precision */
4365 case 842: /* Vector Convert From Signed Fixed-Point Word */
4366 case 778: /* Vector Convert From Unsigned Fixed-Point Word */
4367 case 714: /* Vector Round to Single-Precision Integer toward -Infinity */
4368 case 522: /* Vector Round to Single-Precision Integer Nearest */
4369 case 650: /* Vector Round to Single-Precision Integer toward +Infinity */
4370 case 586: /* Vector Round to Single-Precision Integer toward Zero */
4371 case 394: /* Vector 2 Raised to the Exponent Estimate Floating-Point */
4372 case 458: /* Vector Log Base 2 Estimate Floating-Point */
4373 case 266: /* Vector Reciprocal Estimate Single-Precision */
4374 case 330: /* Vector Reciprocal Square Root Estimate Single-Precision */
4375 case 1288: /* Vector AES Cipher */
4376 case 1289: /* Vector AES Cipher Last */
4377 case 1352: /* Vector AES Inverse Cipher */
4378 case 1353: /* Vector AES Inverse Cipher Last */
4379 case 1480: /* Vector AES SubBytes */
4380 case 1730: /* Vector SHA-512 Sigma Doubleword */
4381 case 1666: /* Vector SHA-256 Sigma Word */
4382 case 1032: /* Vector Polynomial Multiply-Sum Byte */
4383 case 1160: /* Vector Polynomial Multiply-Sum Word */
4384 case 1096: /* Vector Polynomial Multiply-Sum Halfword */
4385 case 1224: /* Vector Polynomial Multiply-Sum Doubleword */
4386 case 1292: /* Vector Gather Bits by Bytes by Doubleword */
4387 case 1794: /* Vector Count Leading Zeros Byte */
4388 case 1858: /* Vector Count Leading Zeros Halfword */
4389 case 1922: /* Vector Count Leading Zeros Word */
4390 case 1986: /* Vector Count Leading Zeros Doubleword */
4391 case 1795: /* Vector Population Count Byte */
4392 case 1859: /* Vector Population Count Halfword */
4393 case 1923: /* Vector Population Count Word */
4394 case 1987: /* Vector Population Count Doubleword */
4395 case 1356: /* Vector Bit Permute Quadword */
4396 case 1484: /* Vector Bit Permute Doubleword */
4397 case 513: /* Vector Multiply-by-10 Unsigned Quadword */
4398 case 1: /* Vector Multiply-by-10 & write Carry Unsigned
4400 case 577: /* Vector Multiply-by-10 Extended Unsigned Quadword */
4401 case 65: /* Vector Multiply-by-10 Extended & write Carry
4402 Unsigned Quadword */
4403 case 1027: /* Vector Absolute Difference Unsigned Byte */
4404 case 1091: /* Vector Absolute Difference Unsigned Halfword */
4405 case 1155: /* Vector Absolute Difference Unsigned Word */
4406 case 1796: /* Vector Shift Right Variable */
4407 case 1860: /* Vector Shift Left Variable */
4408 case 133: /* Vector Rotate Left Word then Mask Insert */
4409 case 197: /* Vector Rotate Left Doubleword then Mask Insert */
4410 case 389: /* Vector Rotate Left Word then AND with Mask */
4411 case 453: /* Vector Rotate Left Doubleword then AND with Mask */
4412 case 525: /* Vector Extract Unsigned Byte */
4413 case 589: /* Vector Extract Unsigned Halfword */
4414 case 653: /* Vector Extract Unsigned Word */
4415 case 717: /* Vector Extract Doubleword */
4416 case 781: /* Vector Insert Byte */
4417 case 845: /* Vector Insert Halfword */
4418 case 909: /* Vector Insert Word */
4419 case 973: /* Vector Insert Doubleword */
4420 record_full_arch_list_add_reg (regcache
,
4421 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4424 case 1549: /* Vector Extract Unsigned Byte Left-Indexed */
4425 case 1613: /* Vector Extract Unsigned Halfword Left-Indexed */
4426 case 1677: /* Vector Extract Unsigned Word Left-Indexed */
4427 case 1805: /* Vector Extract Unsigned Byte Right-Indexed */
4428 case 1869: /* Vector Extract Unsigned Halfword Right-Indexed */
4429 case 1933: /* Vector Extract Unsigned Word Right-Indexed */
4430 record_full_arch_list_add_reg (regcache
,
4431 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4434 case 1604: /* Move To Vector Status and Control Register */
4435 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
4437 case 1540: /* Move From Vector Status and Control Register */
4438 record_full_arch_list_add_reg (regcache
,
4439 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4441 case 833: /* Decimal Copy Sign */
4442 record_full_arch_list_add_reg (regcache
,
4443 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4444 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4448 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4449 "at %s, 4-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4453 /* Parse and record instructions of primary opcode-19 at ADDR.
4454 Return 0 if successful. */
4457 ppc_process_record_op19 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4458 CORE_ADDR addr
, uint32_t insn
)
4460 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4461 int ext
= PPC_EXTOP (insn
);
4463 switch (ext
& 0x01f)
4465 case 2: /* Add PC Immediate Shifted */
4466 record_full_arch_list_add_reg (regcache
,
4467 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4473 case 0: /* Move Condition Register Field */
4474 case 33: /* Condition Register NOR */
4475 case 129: /* Condition Register AND with Complement */
4476 case 193: /* Condition Register XOR */
4477 case 225: /* Condition Register NAND */
4478 case 257: /* Condition Register AND */
4479 case 289: /* Condition Register Equivalent */
4480 case 417: /* Condition Register OR with Complement */
4481 case 449: /* Condition Register OR */
4482 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4485 case 16: /* Branch Conditional */
4486 case 560: /* Branch Conditional to Branch Target Address Register */
4487 if ((PPC_BO (insn
) & 0x4) == 0)
4488 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
4490 case 528: /* Branch Conditional to Count Register */
4492 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
4495 case 150: /* Instruction Synchronize */
4500 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4501 "at %s, 19-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4505 /* Parse and record instructions of primary opcode-31 at ADDR.
4506 Return 0 if successful. */
4509 ppc_process_record_op31 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4510 CORE_ADDR addr
, uint32_t insn
)
4512 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4513 int ext
= PPC_EXTOP (insn
);
4515 CORE_ADDR at_dcsz
, ea
= 0;
4516 ULONGEST rb
, ra
, xer
;
4519 /* These instructions have OE bit. */
4520 switch (ext
& 0x1ff)
4522 /* These write RT and XER. Update CR if RC is set. */
4523 case 8: /* Subtract from carrying */
4524 case 10: /* Add carrying */
4525 case 136: /* Subtract from extended */
4526 case 138: /* Add extended */
4527 case 200: /* Subtract from zero extended */
4528 case 202: /* Add to zero extended */
4529 case 232: /* Subtract from minus one extended */
4530 case 234: /* Add to minus one extended */
4531 /* CA is always altered, but SO/OV are only altered when OE=1.
4532 In any case, XER is always altered. */
4533 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4535 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4536 record_full_arch_list_add_reg (regcache
,
4537 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4540 /* These write RT. Update CR if RC is set and update XER if OE is set. */
4541 case 40: /* Subtract from */
4542 case 104: /* Negate */
4543 case 233: /* Multiply low doubleword */
4544 case 235: /* Multiply low word */
4546 case 393: /* Divide Doubleword Extended Unsigned */
4547 case 395: /* Divide Word Extended Unsigned */
4548 case 425: /* Divide Doubleword Extended */
4549 case 427: /* Divide Word Extended */
4550 case 457: /* Divide Doubleword Unsigned */
4551 case 459: /* Divide Word Unsigned */
4552 case 489: /* Divide Doubleword */
4553 case 491: /* Divide Word */
4555 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4557 case 9: /* Multiply High Doubleword Unsigned */
4558 case 11: /* Multiply High Word Unsigned */
4559 case 73: /* Multiply High Doubleword */
4560 case 75: /* Multiply High Word */
4562 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4563 record_full_arch_list_add_reg (regcache
,
4564 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4568 if ((ext
& 0x1f) == 15)
4570 /* Integer Select. bit[16:20] is used for BC. */
4571 record_full_arch_list_add_reg (regcache
,
4572 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4576 if ((ext
& 0xff) == 170)
4578 /* Add Extended using alternate carry bits */
4579 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4580 record_full_arch_list_add_reg (regcache
,
4581 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4587 case 78: /* Determine Leftmost Zero Byte */
4589 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4590 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4591 record_full_arch_list_add_reg (regcache
,
4592 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4595 /* These only write RT. */
4596 case 19: /* Move from condition register */
4597 /* Move From One Condition Register Field */
4598 case 74: /* Add and Generate Sixes */
4599 case 74 | 0x200: /* Add and Generate Sixes (bit-21 dont-care) */
4600 case 302: /* Move From Branch History Rolling Buffer */
4601 case 339: /* Move From Special Purpose Register */
4602 case 371: /* Move From Time Base [Phased-Out] */
4603 case 309: /* Load Doubleword Monitored Indexed */
4604 case 128: /* Set Boolean */
4605 case 755: /* Deliver A Random Number */
4606 record_full_arch_list_add_reg (regcache
,
4607 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4610 /* These only write to RA. */
4611 case 51: /* Move From VSR Doubleword */
4612 case 115: /* Move From VSR Word and Zero */
4613 case 122: /* Population count bytes */
4614 case 378: /* Population count words */
4615 case 506: /* Population count doublewords */
4616 case 154: /* Parity Word */
4617 case 186: /* Parity Doubleword */
4618 case 252: /* Bit Permute Doubleword */
4619 case 282: /* Convert Declets To Binary Coded Decimal */
4620 case 314: /* Convert Binary Coded Decimal To Declets */
4621 case 508: /* Compare bytes */
4622 case 307: /* Move From VSR Lower Doubleword */
4623 record_full_arch_list_add_reg (regcache
,
4624 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4627 /* These write CR and optional RA. */
4628 case 792: /* Shift Right Algebraic Word */
4629 case 794: /* Shift Right Algebraic Doubleword */
4630 case 824: /* Shift Right Algebraic Word Immediate */
4631 case 826: /* Shift Right Algebraic Doubleword Immediate (413) */
4632 case 826 | 1: /* Shift Right Algebraic Doubleword Immediate (413) */
4633 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4634 record_full_arch_list_add_reg (regcache
,
4635 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4637 case 0: /* Compare */
4638 case 32: /* Compare logical */
4639 case 144: /* Move To Condition Register Fields */
4640 /* Move To One Condition Register Field */
4641 case 192: /* Compare Ranged Byte */
4642 case 224: /* Compare Equal Byte */
4643 case 576: /* Move XER to CR Extended */
4644 case 902: /* Paste (should always fail due to single-stepping and
4645 the memory location might not be accessible, so
4647 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4650 /* These write to RT. Update RA if 'update indexed.' */
4651 case 53: /* Load Doubleword with Update Indexed */
4652 case 119: /* Load Byte and Zero with Update Indexed */
4653 case 311: /* Load Halfword and Zero with Update Indexed */
4654 case 55: /* Load Word and Zero with Update Indexed */
4655 case 375: /* Load Halfword Algebraic with Update Indexed */
4656 case 373: /* Load Word Algebraic with Update Indexed */
4657 record_full_arch_list_add_reg (regcache
,
4658 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4660 case 21: /* Load Doubleword Indexed */
4661 case 52: /* Load Byte And Reserve Indexed */
4662 case 116: /* Load Halfword And Reserve Indexed */
4663 case 20: /* Load Word And Reserve Indexed */
4664 case 84: /* Load Doubleword And Reserve Indexed */
4665 case 87: /* Load Byte and Zero Indexed */
4666 case 279: /* Load Halfword and Zero Indexed */
4667 case 23: /* Load Word and Zero Indexed */
4668 case 343: /* Load Halfword Algebraic Indexed */
4669 case 341: /* Load Word Algebraic Indexed */
4670 case 790: /* Load Halfword Byte-Reverse Indexed */
4671 case 534: /* Load Word Byte-Reverse Indexed */
4672 case 532: /* Load Doubleword Byte-Reverse Indexed */
4673 case 582: /* Load Word Atomic */
4674 case 614: /* Load Doubleword Atomic */
4675 case 265: /* Modulo Unsigned Doubleword */
4676 case 777: /* Modulo Signed Doubleword */
4677 case 267: /* Modulo Unsigned Word */
4678 case 779: /* Modulo Signed Word */
4679 record_full_arch_list_add_reg (regcache
,
4680 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4683 case 597: /* Load String Word Immediate */
4684 case 533: /* Load String Word Indexed */
4693 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &xer
);
4694 nr
= PPC_XER_NB (xer
);
4699 /* If n=0, the contents of register RT are undefined. */
4703 for (i
= 0; i
< nr
; i
++)
4704 record_full_arch_list_add_reg (regcache
,
4705 tdep
->ppc_gp0_regnum
4706 + ((PPC_RT (insn
) + i
) & 0x1f));
4709 case 276: /* Load Quadword And Reserve Indexed */
4710 tmp
= tdep
->ppc_gp0_regnum
+ (PPC_RT (insn
) & ~1);
4711 record_full_arch_list_add_reg (regcache
, tmp
);
4712 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
4715 /* These write VRT. */
4716 case 6: /* Load Vector for Shift Left Indexed */
4717 case 38: /* Load Vector for Shift Right Indexed */
4718 case 7: /* Load Vector Element Byte Indexed */
4719 case 39: /* Load Vector Element Halfword Indexed */
4720 case 71: /* Load Vector Element Word Indexed */
4721 case 103: /* Load Vector Indexed */
4722 case 359: /* Load Vector Indexed LRU */
4723 record_full_arch_list_add_reg (regcache
,
4724 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4727 /* These write FRT. Update RA if 'update indexed.' */
4728 case 567: /* Load Floating-Point Single with Update Indexed */
4729 case 631: /* Load Floating-Point Double with Update Indexed */
4730 record_full_arch_list_add_reg (regcache
,
4731 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4733 case 535: /* Load Floating-Point Single Indexed */
4734 case 599: /* Load Floating-Point Double Indexed */
4735 case 855: /* Load Floating-Point as Integer Word Algebraic Indexed */
4736 case 887: /* Load Floating-Point as Integer Word and Zero Indexed */
4737 record_full_arch_list_add_reg (regcache
,
4738 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4741 case 791: /* Load Floating-Point Double Pair Indexed */
4742 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
4743 record_full_arch_list_add_reg (regcache
, tmp
);
4744 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
4747 case 179: /* Move To VSR Doubleword */
4748 case 211: /* Move To VSR Word Algebraic */
4749 case 243: /* Move To VSR Word and Zero */
4750 case 588: /* Load VSX Scalar Doubleword Indexed */
4751 case 524: /* Load VSX Scalar Single-Precision Indexed */
4752 case 76: /* Load VSX Scalar as Integer Word Algebraic Indexed */
4753 case 12: /* Load VSX Scalar as Integer Word and Zero Indexed */
4754 case 844: /* Load VSX Vector Doubleword*2 Indexed */
4755 case 332: /* Load VSX Vector Doubleword & Splat Indexed */
4756 case 780: /* Load VSX Vector Word*4 Indexed */
4757 case 268: /* Load VSX Vector Indexed */
4758 case 364: /* Load VSX Vector Word & Splat Indexed */
4759 case 812: /* Load VSX Vector Halfword*8 Indexed */
4760 case 876: /* Load VSX Vector Byte*16 Indexed */
4761 case 269: /* Load VSX Vector with Length */
4762 case 301: /* Load VSX Vector Left-justified with Length */
4763 case 781: /* Load VSX Scalar as Integer Byte & Zero Indexed */
4764 case 813: /* Load VSX Scalar as Integer Halfword & Zero Indexed */
4765 case 403: /* Move To VSR Word & Splat */
4766 case 435: /* Move To VSR Double Doubleword */
4767 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
4770 /* These write RA. Update CR if RC is set. */
4771 case 24: /* Shift Left Word */
4772 case 26: /* Count Leading Zeros Word */
4773 case 27: /* Shift Left Doubleword */
4775 case 58: /* Count Leading Zeros Doubleword */
4776 case 60: /* AND with Complement */
4778 case 284: /* Equivalent */
4780 case 476: /* NAND */
4781 case 412: /* OR with Complement */
4783 case 536: /* Shift Right Word */
4784 case 539: /* Shift Right Doubleword */
4785 case 922: /* Extend Sign Halfword */
4786 case 954: /* Extend Sign Byte */
4787 case 986: /* Extend Sign Word */
4788 case 538: /* Count Trailing Zeros Word */
4789 case 570: /* Count Trailing Zeros Doubleword */
4790 case 890: /* Extend-Sign Word and Shift Left Immediate (445) */
4791 case 890 | 1: /* Extend-Sign Word and Shift Left Immediate (445) */
4793 if (ext
== 444 && tdep
->ppc_ppr_regnum
>= 0
4794 && (PPC_RS (insn
) == PPC_RA (insn
))
4795 && (PPC_RA (insn
) == PPC_RB (insn
))
4798 /* or Rx,Rx,Rx alters PRI in PPR. */
4799 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ppr_regnum
);
4804 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4805 record_full_arch_list_add_reg (regcache
,
4806 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4810 case 181: /* Store Doubleword with Update Indexed */
4811 case 183: /* Store Word with Update Indexed */
4812 case 247: /* Store Byte with Update Indexed */
4813 case 439: /* Store Half Word with Update Indexed */
4814 case 695: /* Store Floating-Point Single with Update Indexed */
4815 case 759: /* Store Floating-Point Double with Update Indexed */
4816 record_full_arch_list_add_reg (regcache
,
4817 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4819 case 135: /* Store Vector Element Byte Indexed */
4820 case 167: /* Store Vector Element Halfword Indexed */
4821 case 199: /* Store Vector Element Word Indexed */
4822 case 231: /* Store Vector Indexed */
4823 case 487: /* Store Vector Indexed LRU */
4824 case 716: /* Store VSX Scalar Doubleword Indexed */
4825 case 140: /* Store VSX Scalar as Integer Word Indexed */
4826 case 652: /* Store VSX Scalar Single-Precision Indexed */
4827 case 972: /* Store VSX Vector Doubleword*2 Indexed */
4828 case 908: /* Store VSX Vector Word*4 Indexed */
4829 case 149: /* Store Doubleword Indexed */
4830 case 151: /* Store Word Indexed */
4831 case 215: /* Store Byte Indexed */
4832 case 407: /* Store Half Word Indexed */
4833 case 694: /* Store Byte Conditional Indexed */
4834 case 726: /* Store Halfword Conditional Indexed */
4835 case 150: /* Store Word Conditional Indexed */
4836 case 214: /* Store Doubleword Conditional Indexed */
4837 case 182: /* Store Quadword Conditional Indexed */
4838 case 662: /* Store Word Byte-Reverse Indexed */
4839 case 918: /* Store Halfword Byte-Reverse Indexed */
4840 case 660: /* Store Doubleword Byte-Reverse Indexed */
4841 case 663: /* Store Floating-Point Single Indexed */
4842 case 727: /* Store Floating-Point Double Indexed */
4843 case 919: /* Store Floating-Point Double Pair Indexed */
4844 case 983: /* Store Floating-Point as Integer Word Indexed */
4845 case 396: /* Store VSX Vector Indexed */
4846 case 940: /* Store VSX Vector Halfword*8 Indexed */
4847 case 1004: /* Store VSX Vector Byte*16 Indexed */
4848 case 909: /* Store VSX Scalar as Integer Byte Indexed */
4849 case 941: /* Store VSX Scalar as Integer Halfword Indexed */
4850 if (ext
== 694 || ext
== 726 || ext
== 150 || ext
== 214 || ext
== 182)
4851 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4854 if (PPC_RA (insn
) != 0)
4855 regcache_raw_read_unsigned (regcache
,
4856 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4857 regcache_raw_read_unsigned (regcache
,
4858 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
4863 case 183: /* Store Word with Update Indexed */
4864 case 199: /* Store Vector Element Word Indexed */
4865 case 140: /* Store VSX Scalar as Integer Word Indexed */
4866 case 652: /* Store VSX Scalar Single-Precision Indexed */
4867 case 151: /* Store Word Indexed */
4868 case 150: /* Store Word Conditional Indexed */
4869 case 662: /* Store Word Byte-Reverse Indexed */
4870 case 663: /* Store Floating-Point Single Indexed */
4871 case 695: /* Store Floating-Point Single with Update Indexed */
4872 case 983: /* Store Floating-Point as Integer Word Indexed */
4875 case 247: /* Store Byte with Update Indexed */
4876 case 135: /* Store Vector Element Byte Indexed */
4877 case 215: /* Store Byte Indexed */
4878 case 694: /* Store Byte Conditional Indexed */
4879 case 909: /* Store VSX Scalar as Integer Byte Indexed */
4882 case 439: /* Store Halfword with Update Indexed */
4883 case 167: /* Store Vector Element Halfword Indexed */
4884 case 407: /* Store Halfword Indexed */
4885 case 726: /* Store Halfword Conditional Indexed */
4886 case 918: /* Store Halfword Byte-Reverse Indexed */
4887 case 941: /* Store VSX Scalar as Integer Halfword Indexed */
4890 case 181: /* Store Doubleword with Update Indexed */
4891 case 716: /* Store VSX Scalar Doubleword Indexed */
4892 case 149: /* Store Doubleword Indexed */
4893 case 214: /* Store Doubleword Conditional Indexed */
4894 case 660: /* Store Doubleword Byte-Reverse Indexed */
4895 case 727: /* Store Floating-Point Double Indexed */
4896 case 759: /* Store Floating-Point Double with Update Indexed */
4899 case 972: /* Store VSX Vector Doubleword*2 Indexed */
4900 case 908: /* Store VSX Vector Word*4 Indexed */
4901 case 182: /* Store Quadword Conditional Indexed */
4902 case 231: /* Store Vector Indexed */
4903 case 487: /* Store Vector Indexed LRU */
4904 case 919: /* Store Floating-Point Double Pair Indexed */
4905 case 396: /* Store VSX Vector Indexed */
4906 case 940: /* Store VSX Vector Halfword*8 Indexed */
4907 case 1004: /* Store VSX Vector Byte*16 Indexed */
4914 /* Align address for Store Vector instructions. */
4917 case 167: /* Store Vector Element Halfword Indexed */
4918 addr
= addr
& ~0x1ULL
;
4921 case 199: /* Store Vector Element Word Indexed */
4922 addr
= addr
& ~0x3ULL
;
4925 case 231: /* Store Vector Indexed */
4926 case 487: /* Store Vector Indexed LRU */
4927 addr
= addr
& ~0xfULL
;
4931 record_full_arch_list_add_mem (addr
, size
);
4934 case 397: /* Store VSX Vector with Length */
4935 case 429: /* Store VSX Vector Left-justified with Length */
4937 if (PPC_RA (insn
) != 0)
4938 regcache_raw_read_unsigned (regcache
,
4939 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4941 regcache_raw_read_unsigned (regcache
,
4942 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
4943 /* Store up to 16 bytes. */
4944 nb
= (rb
& 0xff) > 16 ? 16 : (rb
& 0xff);
4946 record_full_arch_list_add_mem (ea
, nb
);
4949 case 710: /* Store Word Atomic */
4950 case 742: /* Store Doubleword Atomic */
4952 if (PPC_RA (insn
) != 0)
4953 regcache_raw_read_unsigned (regcache
,
4954 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4958 case 710: /* Store Word Atomic */
4961 case 742: /* Store Doubleword Atomic */
4967 record_full_arch_list_add_mem (ea
, size
);
4970 case 725: /* Store String Word Immediate */
4972 if (PPC_RA (insn
) != 0)
4973 regcache_raw_read_unsigned (regcache
,
4974 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4981 record_full_arch_list_add_mem (ea
, nb
);
4985 case 661: /* Store String Word Indexed */
4987 if (PPC_RA (insn
) != 0)
4988 regcache_raw_read_unsigned (regcache
,
4989 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4992 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &xer
);
4993 nb
= PPC_XER_NB (xer
);
4997 regcache_raw_read_unsigned (regcache
,
4998 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
),
5001 record_full_arch_list_add_mem (ea
, nb
);
5006 case 467: /* Move To Special Purpose Register */
5007 switch (PPC_SPR (insn
))
5010 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5013 if (tdep
->ppc_dscr_regnum
>= 0)
5014 record_full_arch_list_add_reg (regcache
, tdep
->ppc_dscr_regnum
);
5017 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
5020 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
5022 case 256: /* VRSAVE */
5023 record_full_arch_list_add_reg (regcache
, tdep
->ppc_vrsave_regnum
);
5026 if (tdep
->ppc_tar_regnum
>= 0)
5027 record_full_arch_list_add_reg (regcache
, tdep
->ppc_tar_regnum
);
5031 if (tdep
->ppc_ppr_regnum
>= 0)
5032 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ppr_regnum
);
5038 case 147: /* Move To Split Little Endian */
5039 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ps_regnum
);
5042 case 512: /* Move to Condition Register from XER */
5043 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5044 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5047 case 4: /* Trap Word */
5048 case 68: /* Trap Doubleword */
5049 case 430: /* Clear BHRB */
5050 case 598: /* Synchronize */
5051 case 62: /* Wait for Interrupt */
5053 case 22: /* Instruction Cache Block Touch */
5054 case 854: /* Enforce In-order Execution of I/O */
5055 case 246: /* Data Cache Block Touch for Store */
5056 case 54: /* Data Cache Block Store */
5057 case 86: /* Data Cache Block Flush */
5058 case 278: /* Data Cache Block Touch */
5059 case 758: /* Data Cache Block Allocate */
5060 case 982: /* Instruction Cache Block Invalidate */
5061 case 774: /* Copy */
5062 case 838: /* CP_Abort */
5065 case 654: /* Transaction Begin */
5066 case 686: /* Transaction End */
5067 case 750: /* Transaction Suspend or Resume */
5068 case 782: /* Transaction Abort Word Conditional */
5069 case 814: /* Transaction Abort Doubleword Conditional */
5070 case 846: /* Transaction Abort Word Conditional Immediate */
5071 case 878: /* Transaction Abort Doubleword Conditional Immediate */
5072 case 910: /* Transaction Abort */
5073 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ps_regnum
);
5075 case 718: /* Transaction Check */
5076 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5079 case 1014: /* Data Cache Block set to Zero */
5080 if (target_auxv_search (current_top_target (), AT_DCACHEBSIZE
, &at_dcsz
) <= 0
5082 at_dcsz
= 128; /* Assume 128-byte cache line size (POWER8) */
5085 if (PPC_RA (insn
) != 0)
5086 regcache_raw_read_unsigned (regcache
,
5087 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
5088 regcache_raw_read_unsigned (regcache
,
5089 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
5090 ea
= (ra
+ rb
) & ~((ULONGEST
) (at_dcsz
- 1));
5091 record_full_arch_list_add_mem (ea
, at_dcsz
);
5096 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5097 "at %s, 31-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5101 /* Parse and record instructions of primary opcode-59 at ADDR.
5102 Return 0 if successful. */
5105 ppc_process_record_op59 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5106 CORE_ADDR addr
, uint32_t insn
)
5108 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5109 int ext
= PPC_EXTOP (insn
);
5113 case 18: /* Floating Divide */
5114 case 20: /* Floating Subtract */
5115 case 21: /* Floating Add */
5116 case 22: /* Floating Square Root */
5117 case 24: /* Floating Reciprocal Estimate */
5118 case 25: /* Floating Multiply */
5119 case 26: /* Floating Reciprocal Square Root Estimate */
5120 case 28: /* Floating Multiply-Subtract */
5121 case 29: /* Floating Multiply-Add */
5122 case 30: /* Floating Negative Multiply-Subtract */
5123 case 31: /* Floating Negative Multiply-Add */
5124 record_full_arch_list_add_reg (regcache
,
5125 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5127 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5128 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5135 case 2: /* DFP Add */
5136 case 3: /* DFP Quantize */
5137 case 34: /* DFP Multiply */
5138 case 35: /* DFP Reround */
5139 case 67: /* DFP Quantize Immediate */
5140 case 99: /* DFP Round To FP Integer With Inexact */
5141 case 227: /* DFP Round To FP Integer Without Inexact */
5142 case 258: /* DFP Convert To DFP Long! */
5143 case 290: /* DFP Convert To Fixed */
5144 case 514: /* DFP Subtract */
5145 case 546: /* DFP Divide */
5146 case 770: /* DFP Round To DFP Short! */
5147 case 802: /* DFP Convert From Fixed */
5148 case 834: /* DFP Encode BCD To DPD */
5150 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5151 record_full_arch_list_add_reg (regcache
,
5152 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5153 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5156 case 130: /* DFP Compare Ordered */
5157 case 162: /* DFP Test Exponent */
5158 case 194: /* DFP Test Data Class */
5159 case 226: /* DFP Test Data Group */
5160 case 642: /* DFP Compare Unordered */
5161 case 674: /* DFP Test Significance */
5162 case 675: /* DFP Test Significance Immediate */
5163 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5164 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5167 case 66: /* DFP Shift Significand Left Immediate */
5168 case 98: /* DFP Shift Significand Right Immediate */
5169 case 322: /* DFP Decode DPD To BCD */
5170 case 354: /* DFP Extract Biased Exponent */
5171 case 866: /* DFP Insert Biased Exponent */
5172 record_full_arch_list_add_reg (regcache
,
5173 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5175 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5178 case 846: /* Floating Convert From Integer Doubleword Single */
5179 case 974: /* Floating Convert From Integer Doubleword Unsigned
5181 record_full_arch_list_add_reg (regcache
,
5182 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5184 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5185 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5190 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5191 "at %s, 59-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5195 /* Parse and record instructions of primary opcode-60 at ADDR.
5196 Return 0 if successful. */
5199 ppc_process_record_op60 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5200 CORE_ADDR addr
, uint32_t insn
)
5202 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5203 int ext
= PPC_EXTOP (insn
);
5207 case 0: /* VSX Scalar Add Single-Precision */
5208 case 32: /* VSX Scalar Add Double-Precision */
5209 case 24: /* VSX Scalar Divide Single-Precision */
5210 case 56: /* VSX Scalar Divide Double-Precision */
5211 case 176: /* VSX Scalar Copy Sign Double-Precision */
5212 case 33: /* VSX Scalar Multiply-Add Double-Precision */
5213 case 41: /* ditto */
5214 case 1: /* VSX Scalar Multiply-Add Single-Precision */
5216 case 160: /* VSX Scalar Maximum Double-Precision */
5217 case 168: /* VSX Scalar Minimum Double-Precision */
5218 case 49: /* VSX Scalar Multiply-Subtract Double-Precision */
5219 case 57: /* ditto */
5220 case 17: /* VSX Scalar Multiply-Subtract Single-Precision */
5221 case 25: /* ditto */
5222 case 48: /* VSX Scalar Multiply Double-Precision */
5223 case 16: /* VSX Scalar Multiply Single-Precision */
5224 case 161: /* VSX Scalar Negative Multiply-Add Double-Precision */
5225 case 169: /* ditto */
5226 case 129: /* VSX Scalar Negative Multiply-Add Single-Precision */
5227 case 137: /* ditto */
5228 case 177: /* VSX Scalar Negative Multiply-Subtract Double-Precision */
5229 case 185: /* ditto */
5230 case 145: /* VSX Scalar Negative Multiply-Subtract Single-Precision */
5231 case 153: /* ditto */
5232 case 40: /* VSX Scalar Subtract Double-Precision */
5233 case 8: /* VSX Scalar Subtract Single-Precision */
5234 case 96: /* VSX Vector Add Double-Precision */
5235 case 64: /* VSX Vector Add Single-Precision */
5236 case 120: /* VSX Vector Divide Double-Precision */
5237 case 88: /* VSX Vector Divide Single-Precision */
5238 case 97: /* VSX Vector Multiply-Add Double-Precision */
5239 case 105: /* ditto */
5240 case 65: /* VSX Vector Multiply-Add Single-Precision */
5241 case 73: /* ditto */
5242 case 224: /* VSX Vector Maximum Double-Precision */
5243 case 192: /* VSX Vector Maximum Single-Precision */
5244 case 232: /* VSX Vector Minimum Double-Precision */
5245 case 200: /* VSX Vector Minimum Single-Precision */
5246 case 113: /* VSX Vector Multiply-Subtract Double-Precision */
5247 case 121: /* ditto */
5248 case 81: /* VSX Vector Multiply-Subtract Single-Precision */
5249 case 89: /* ditto */
5250 case 112: /* VSX Vector Multiply Double-Precision */
5251 case 80: /* VSX Vector Multiply Single-Precision */
5252 case 225: /* VSX Vector Negative Multiply-Add Double-Precision */
5253 case 233: /* ditto */
5254 case 193: /* VSX Vector Negative Multiply-Add Single-Precision */
5255 case 201: /* ditto */
5256 case 241: /* VSX Vector Negative Multiply-Subtract Double-Precision */
5257 case 249: /* ditto */
5258 case 209: /* VSX Vector Negative Multiply-Subtract Single-Precision */
5259 case 217: /* ditto */
5260 case 104: /* VSX Vector Subtract Double-Precision */
5261 case 72: /* VSX Vector Subtract Single-Precision */
5262 case 128: /* VSX Scalar Maximum Type-C Double-Precision */
5263 case 136: /* VSX Scalar Minimum Type-C Double-Precision */
5264 case 144: /* VSX Scalar Maximum Type-J Double-Precision */
5265 case 152: /* VSX Scalar Minimum Type-J Double-Precision */
5266 case 3: /* VSX Scalar Compare Equal Double-Precision */
5267 case 11: /* VSX Scalar Compare Greater Than Double-Precision */
5268 case 19: /* VSX Scalar Compare Greater Than or Equal
5270 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5272 case 240: /* VSX Vector Copy Sign Double-Precision */
5273 case 208: /* VSX Vector Copy Sign Single-Precision */
5274 case 130: /* VSX Logical AND */
5275 case 138: /* VSX Logical AND with Complement */
5276 case 186: /* VSX Logical Equivalence */
5277 case 178: /* VSX Logical NAND */
5278 case 170: /* VSX Logical OR with Complement */
5279 case 162: /* VSX Logical NOR */
5280 case 146: /* VSX Logical OR */
5281 case 154: /* VSX Logical XOR */
5282 case 18: /* VSX Merge High Word */
5283 case 50: /* VSX Merge Low Word */
5284 case 10: /* VSX Permute Doubleword Immediate (DM=0) */
5285 case 10 | 0x20: /* VSX Permute Doubleword Immediate (DM=1) */
5286 case 10 | 0x40: /* VSX Permute Doubleword Immediate (DM=2) */
5287 case 10 | 0x60: /* VSX Permute Doubleword Immediate (DM=3) */
5288 case 2: /* VSX Shift Left Double by Word Immediate (SHW=0) */
5289 case 2 | 0x20: /* VSX Shift Left Double by Word Immediate (SHW=1) */
5290 case 2 | 0x40: /* VSX Shift Left Double by Word Immediate (SHW=2) */
5291 case 2 | 0x60: /* VSX Shift Left Double by Word Immediate (SHW=3) */
5292 case 216: /* VSX Vector Insert Exponent Single-Precision */
5293 case 248: /* VSX Vector Insert Exponent Double-Precision */
5294 case 26: /* VSX Vector Permute */
5295 case 58: /* VSX Vector Permute Right-indexed */
5296 case 213: /* VSX Vector Test Data Class Single-Precision (DC=0) */
5297 case 213 | 0x8: /* VSX Vector Test Data Class Single-Precision (DC=1) */
5298 case 245: /* VSX Vector Test Data Class Double-Precision (DC=0) */
5299 case 245 | 0x8: /* VSX Vector Test Data Class Double-Precision (DC=1) */
5300 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5303 case 61: /* VSX Scalar Test for software Divide Double-Precision */
5304 case 125: /* VSX Vector Test for software Divide Double-Precision */
5305 case 93: /* VSX Vector Test for software Divide Single-Precision */
5306 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5309 case 35: /* VSX Scalar Compare Unordered Double-Precision */
5310 case 43: /* VSX Scalar Compare Ordered Double-Precision */
5311 case 59: /* VSX Scalar Compare Exponents Double-Precision */
5312 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5313 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5317 switch ((ext
>> 2) & 0x7f) /* Mask out Rc-bit. */
5319 case 99: /* VSX Vector Compare Equal To Double-Precision */
5320 case 67: /* VSX Vector Compare Equal To Single-Precision */
5321 case 115: /* VSX Vector Compare Greater Than or
5322 Equal To Double-Precision */
5323 case 83: /* VSX Vector Compare Greater Than or
5324 Equal To Single-Precision */
5325 case 107: /* VSX Vector Compare Greater Than Double-Precision */
5326 case 75: /* VSX Vector Compare Greater Than Single-Precision */
5328 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5329 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5330 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5336 case 265: /* VSX Scalar round Double-Precision to
5337 Single-Precision and Convert to
5338 Single-Precision format */
5339 case 344: /* VSX Scalar truncate Double-Precision to
5340 Integer and Convert to Signed Integer
5341 Doubleword format with Saturate */
5342 case 88: /* VSX Scalar truncate Double-Precision to
5343 Integer and Convert to Signed Integer Word
5344 Format with Saturate */
5345 case 328: /* VSX Scalar truncate Double-Precision integer
5346 and Convert to Unsigned Integer Doubleword
5347 Format with Saturate */
5348 case 72: /* VSX Scalar truncate Double-Precision to
5349 Integer and Convert to Unsigned Integer Word
5350 Format with Saturate */
5351 case 329: /* VSX Scalar Convert Single-Precision to
5352 Double-Precision format */
5353 case 376: /* VSX Scalar Convert Signed Integer
5354 Doubleword to floating-point format and
5355 Round to Double-Precision format */
5356 case 312: /* VSX Scalar Convert Signed Integer
5357 Doubleword to floating-point format and
5358 round to Single-Precision */
5359 case 360: /* VSX Scalar Convert Unsigned Integer
5360 Doubleword to floating-point format and
5361 Round to Double-Precision format */
5362 case 296: /* VSX Scalar Convert Unsigned Integer
5363 Doubleword to floating-point format and
5364 Round to Single-Precision */
5365 case 73: /* VSX Scalar Round to Double-Precision Integer
5366 Using Round to Nearest Away */
5367 case 107: /* VSX Scalar Round to Double-Precision Integer
5368 Exact using Current rounding mode */
5369 case 121: /* VSX Scalar Round to Double-Precision Integer
5370 Using Round toward -Infinity */
5371 case 105: /* VSX Scalar Round to Double-Precision Integer
5372 Using Round toward +Infinity */
5373 case 89: /* VSX Scalar Round to Double-Precision Integer
5374 Using Round toward Zero */
5375 case 90: /* VSX Scalar Reciprocal Estimate Double-Precision */
5376 case 26: /* VSX Scalar Reciprocal Estimate Single-Precision */
5377 case 281: /* VSX Scalar Round to Single-Precision */
5378 case 74: /* VSX Scalar Reciprocal Square Root Estimate
5380 case 10: /* VSX Scalar Reciprocal Square Root Estimate
5382 case 75: /* VSX Scalar Square Root Double-Precision */
5383 case 11: /* VSX Scalar Square Root Single-Precision */
5384 case 393: /* VSX Vector round Double-Precision to
5385 Single-Precision and Convert to
5386 Single-Precision format */
5387 case 472: /* VSX Vector truncate Double-Precision to
5388 Integer and Convert to Signed Integer
5389 Doubleword format with Saturate */
5390 case 216: /* VSX Vector truncate Double-Precision to
5391 Integer and Convert to Signed Integer Word
5392 Format with Saturate */
5393 case 456: /* VSX Vector truncate Double-Precision to
5394 Integer and Convert to Unsigned Integer
5395 Doubleword format with Saturate */
5396 case 200: /* VSX Vector truncate Double-Precision to
5397 Integer and Convert to Unsigned Integer Word
5398 Format with Saturate */
5399 case 457: /* VSX Vector Convert Single-Precision to
5400 Double-Precision format */
5401 case 408: /* VSX Vector truncate Single-Precision to
5402 Integer and Convert to Signed Integer
5403 Doubleword format with Saturate */
5404 case 152: /* VSX Vector truncate Single-Precision to
5405 Integer and Convert to Signed Integer Word
5406 Format with Saturate */
5407 case 392: /* VSX Vector truncate Single-Precision to
5408 Integer and Convert to Unsigned Integer
5409 Doubleword format with Saturate */
5410 case 136: /* VSX Vector truncate Single-Precision to
5411 Integer and Convert to Unsigned Integer Word
5412 Format with Saturate */
5413 case 504: /* VSX Vector Convert and round Signed Integer
5414 Doubleword to Double-Precision format */
5415 case 440: /* VSX Vector Convert and round Signed Integer
5416 Doubleword to Single-Precision format */
5417 case 248: /* VSX Vector Convert Signed Integer Word to
5418 Double-Precision format */
5419 case 184: /* VSX Vector Convert and round Signed Integer
5420 Word to Single-Precision format */
5421 case 488: /* VSX Vector Convert and round Unsigned
5422 Integer Doubleword to Double-Precision format */
5423 case 424: /* VSX Vector Convert and round Unsigned
5424 Integer Doubleword to Single-Precision format */
5425 case 232: /* VSX Vector Convert and round Unsigned
5426 Integer Word to Double-Precision format */
5427 case 168: /* VSX Vector Convert and round Unsigned
5428 Integer Word to Single-Precision format */
5429 case 201: /* VSX Vector Round to Double-Precision
5430 Integer using round to Nearest Away */
5431 case 235: /* VSX Vector Round to Double-Precision
5432 Integer Exact using Current rounding mode */
5433 case 249: /* VSX Vector Round to Double-Precision
5434 Integer using round toward -Infinity */
5435 case 233: /* VSX Vector Round to Double-Precision
5436 Integer using round toward +Infinity */
5437 case 217: /* VSX Vector Round to Double-Precision
5438 Integer using round toward Zero */
5439 case 218: /* VSX Vector Reciprocal Estimate Double-Precision */
5440 case 154: /* VSX Vector Reciprocal Estimate Single-Precision */
5441 case 137: /* VSX Vector Round to Single-Precision Integer
5442 Using Round to Nearest Away */
5443 case 171: /* VSX Vector Round to Single-Precision Integer
5444 Exact Using Current rounding mode */
5445 case 185: /* VSX Vector Round to Single-Precision Integer
5446 Using Round toward -Infinity */
5447 case 169: /* VSX Vector Round to Single-Precision Integer
5448 Using Round toward +Infinity */
5449 case 153: /* VSX Vector Round to Single-Precision Integer
5450 Using round toward Zero */
5451 case 202: /* VSX Vector Reciprocal Square Root Estimate
5453 case 138: /* VSX Vector Reciprocal Square Root Estimate
5455 case 203: /* VSX Vector Square Root Double-Precision */
5456 case 139: /* VSX Vector Square Root Single-Precision */
5457 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5459 case 345: /* VSX Scalar Absolute Value Double-Precision */
5460 case 267: /* VSX Scalar Convert Scalar Single-Precision to
5461 Vector Single-Precision format Non-signalling */
5462 case 331: /* VSX Scalar Convert Single-Precision to
5463 Double-Precision format Non-signalling */
5464 case 361: /* VSX Scalar Negative Absolute Value Double-Precision */
5465 case 377: /* VSX Scalar Negate Double-Precision */
5466 case 473: /* VSX Vector Absolute Value Double-Precision */
5467 case 409: /* VSX Vector Absolute Value Single-Precision */
5468 case 489: /* VSX Vector Negative Absolute Value Double-Precision */
5469 case 425: /* VSX Vector Negative Absolute Value Single-Precision */
5470 case 505: /* VSX Vector Negate Double-Precision */
5471 case 441: /* VSX Vector Negate Single-Precision */
5472 case 164: /* VSX Splat Word */
5473 case 165: /* VSX Vector Extract Unsigned Word */
5474 case 181: /* VSX Vector Insert Word */
5475 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5478 case 298: /* VSX Scalar Test Data Class Single-Precision */
5479 case 362: /* VSX Scalar Test Data Class Double-Precision */
5480 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5482 case 106: /* VSX Scalar Test for software Square Root
5484 case 234: /* VSX Vector Test for software Square Root
5486 case 170: /* VSX Vector Test for software Square Root
5488 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5492 switch (PPC_FIELD (insn
, 11, 5))
5494 case 0: /* VSX Scalar Extract Exponent Double-Precision */
5495 case 1: /* VSX Scalar Extract Significand Double-Precision */
5496 record_full_arch_list_add_reg (regcache
,
5497 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5499 case 16: /* VSX Scalar Convert Half-Precision format to
5500 Double-Precision format */
5501 case 17: /* VSX Scalar round & Convert Double-Precision format
5502 to Half-Precision format */
5503 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5504 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5510 switch (PPC_FIELD (insn
, 11, 5))
5512 case 24: /* VSX Vector Convert Half-Precision format to
5513 Single-Precision format */
5514 case 25: /* VSX Vector round and Convert Single-Precision format
5515 to Half-Precision format */
5516 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5518 case 0: /* VSX Vector Extract Exponent Double-Precision */
5519 case 1: /* VSX Vector Extract Significand Double-Precision */
5520 case 7: /* VSX Vector Byte-Reverse Halfword */
5521 case 8: /* VSX Vector Extract Exponent Single-Precision */
5522 case 9: /* VSX Vector Extract Significand Single-Precision */
5523 case 15: /* VSX Vector Byte-Reverse Word */
5524 case 23: /* VSX Vector Byte-Reverse Doubleword */
5525 case 31: /* VSX Vector Byte-Reverse Quadword */
5526 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5534 case 360: /* VSX Vector Splat Immediate Byte */
5535 if (PPC_FIELD (insn
, 11, 2) == 0)
5537 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5541 case 918: /* VSX Scalar Insert Exponent Double-Precision */
5542 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5546 if (((ext
>> 3) & 0x3) == 3) /* VSX Select */
5548 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5552 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5553 "at %s, 60-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5557 /* Parse and record instructions of primary opcode-61 at ADDR.
5558 Return 0 if successful. */
5561 ppc_process_record_op61 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5562 CORE_ADDR addr
, uint32_t insn
)
5564 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5570 case 0: /* Store Floating-Point Double Pair */
5571 case 2: /* Store VSX Scalar Doubleword */
5572 case 3: /* Store VSX Scalar Single */
5573 if (PPC_RA (insn
) != 0)
5574 regcache_raw_read_unsigned (regcache
,
5575 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5577 ea
+= PPC_DS (insn
) << 2;
5580 case 0: /* Store Floating-Point Double Pair */
5583 case 2: /* Store VSX Scalar Doubleword */
5586 case 3: /* Store VSX Scalar Single */
5592 record_full_arch_list_add_mem (ea
, size
);
5598 case 1: /* Load VSX Vector */
5599 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5601 case 5: /* Store VSX Vector */
5602 if (PPC_RA (insn
) != 0)
5603 regcache_raw_read_unsigned (regcache
,
5604 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5606 ea
+= PPC_DQ (insn
) << 4;
5607 record_full_arch_list_add_mem (ea
, 16);
5611 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5612 "at %s.\n", insn
, paddress (gdbarch
, addr
));
5616 /* Parse and record instructions of primary opcode-63 at ADDR.
5617 Return 0 if successful. */
5620 ppc_process_record_op63 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5621 CORE_ADDR addr
, uint32_t insn
)
5623 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5624 int ext
= PPC_EXTOP (insn
);
5629 case 18: /* Floating Divide */
5630 case 20: /* Floating Subtract */
5631 case 21: /* Floating Add */
5632 case 22: /* Floating Square Root */
5633 case 24: /* Floating Reciprocal Estimate */
5634 case 25: /* Floating Multiply */
5635 case 26: /* Floating Reciprocal Square Root Estimate */
5636 case 28: /* Floating Multiply-Subtract */
5637 case 29: /* Floating Multiply-Add */
5638 case 30: /* Floating Negative Multiply-Subtract */
5639 case 31: /* Floating Negative Multiply-Add */
5640 record_full_arch_list_add_reg (regcache
,
5641 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5643 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5644 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5647 case 23: /* Floating Select */
5648 record_full_arch_list_add_reg (regcache
,
5649 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5651 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5657 case 5: /* VSX Scalar Round to Quad-Precision Integer */
5658 case 37: /* VSX Scalar Round Quad-Precision to Double-Extended
5660 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5661 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5667 case 2: /* DFP Add Quad */
5668 case 3: /* DFP Quantize Quad */
5669 case 34: /* DFP Multiply Quad */
5670 case 35: /* DFP Reround Quad */
5671 case 67: /* DFP Quantize Immediate Quad */
5672 case 99: /* DFP Round To FP Integer With Inexact Quad */
5673 case 227: /* DFP Round To FP Integer Without Inexact Quad */
5674 case 258: /* DFP Convert To DFP Extended Quad */
5675 case 514: /* DFP Subtract Quad */
5676 case 546: /* DFP Divide Quad */
5677 case 770: /* DFP Round To DFP Long Quad */
5678 case 802: /* DFP Convert From Fixed Quad */
5679 case 834: /* DFP Encode BCD To DPD Quad */
5681 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5682 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
5683 record_full_arch_list_add_reg (regcache
, tmp
);
5684 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5685 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5688 case 130: /* DFP Compare Ordered Quad */
5689 case 162: /* DFP Test Exponent Quad */
5690 case 194: /* DFP Test Data Class Quad */
5691 case 226: /* DFP Test Data Group Quad */
5692 case 642: /* DFP Compare Unordered Quad */
5693 case 674: /* DFP Test Significance Quad */
5694 case 675: /* DFP Test Significance Immediate Quad */
5695 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5696 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5699 case 66: /* DFP Shift Significand Left Immediate Quad */
5700 case 98: /* DFP Shift Significand Right Immediate Quad */
5701 case 322: /* DFP Decode DPD To BCD Quad */
5702 case 866: /* DFP Insert Biased Exponent Quad */
5703 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
5704 record_full_arch_list_add_reg (regcache
, tmp
);
5705 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5707 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5710 case 290: /* DFP Convert To Fixed Quad */
5711 record_full_arch_list_add_reg (regcache
,
5712 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5714 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5715 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5718 case 354: /* DFP Extract Biased Exponent Quad */
5719 record_full_arch_list_add_reg (regcache
,
5720 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5722 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5725 case 12: /* Floating Round to Single-Precision */
5726 case 14: /* Floating Convert To Integer Word */
5727 case 15: /* Floating Convert To Integer Word
5728 with round toward Zero */
5729 case 142: /* Floating Convert To Integer Word Unsigned */
5730 case 143: /* Floating Convert To Integer Word Unsigned
5731 with round toward Zero */
5732 case 392: /* Floating Round to Integer Nearest */
5733 case 424: /* Floating Round to Integer Toward Zero */
5734 case 456: /* Floating Round to Integer Plus */
5735 case 488: /* Floating Round to Integer Minus */
5736 case 814: /* Floating Convert To Integer Doubleword */
5737 case 815: /* Floating Convert To Integer Doubleword
5738 with round toward Zero */
5739 case 846: /* Floating Convert From Integer Doubleword */
5740 case 942: /* Floating Convert To Integer Doubleword Unsigned */
5741 case 943: /* Floating Convert To Integer Doubleword Unsigned
5742 with round toward Zero */
5743 case 974: /* Floating Convert From Integer Doubleword Unsigned */
5744 record_full_arch_list_add_reg (regcache
,
5745 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5747 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5748 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5752 switch (PPC_FIELD (insn
, 11, 5))
5754 case 1: /* Move From FPSCR & Clear Enables */
5755 case 20: /* Move From FPSCR Control & set DRN */
5756 case 21: /* Move From FPSCR Control & set DRN Immediate */
5757 case 22: /* Move From FPSCR Control & set RN */
5758 case 23: /* Move From FPSCR Control & set RN Immediate */
5759 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5761 case 0: /* Move From FPSCR */
5762 case 24: /* Move From FPSCR Lightweight */
5763 if (PPC_FIELD (insn
, 11, 5) == 0 && PPC_RC (insn
))
5764 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5765 record_full_arch_list_add_reg (regcache
,
5766 tdep
->ppc_fp0_regnum
5772 case 8: /* Floating Copy Sign */
5773 case 40: /* Floating Negate */
5774 case 72: /* Floating Move Register */
5775 case 136: /* Floating Negative Absolute Value */
5776 case 264: /* Floating Absolute Value */
5777 record_full_arch_list_add_reg (regcache
,
5778 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5780 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5783 case 838: /* Floating Merge Odd Word */
5784 case 966: /* Floating Merge Even Word */
5785 record_full_arch_list_add_reg (regcache
,
5786 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5789 case 38: /* Move To FPSCR Bit 1 */
5790 case 70: /* Move To FPSCR Bit 0 */
5791 case 134: /* Move To FPSCR Field Immediate */
5792 case 711: /* Move To FPSCR Fields */
5794 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5795 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5798 case 0: /* Floating Compare Unordered */
5799 case 32: /* Floating Compare Ordered */
5800 case 64: /* Move to Condition Register from FPSCR */
5801 case 132: /* VSX Scalar Compare Ordered Quad-Precision */
5802 case 164: /* VSX Scalar Compare Exponents Quad-Precision */
5803 case 644: /* VSX Scalar Compare Unordered Quad-Precision */
5804 case 708: /* VSX Scalar Test Data Class Quad-Precision */
5805 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5807 case 128: /* Floating Test for software Divide */
5808 case 160: /* Floating Test for software Square Root */
5809 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5812 case 4: /* VSX Scalar Add Quad-Precision */
5813 case 36: /* VSX Scalar Multiply Quad-Precision */
5814 case 388: /* VSX Scalar Multiply-Add Quad-Precision */
5815 case 420: /* VSX Scalar Multiply-Subtract Quad-Precision */
5816 case 452: /* VSX Scalar Negative Multiply-Add Quad-Precision */
5817 case 484: /* VSX Scalar Negative Multiply-Subtract
5819 case 516: /* VSX Scalar Subtract Quad-Precision */
5820 case 548: /* VSX Scalar Divide Quad-Precision */
5821 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5823 case 100: /* VSX Scalar Copy Sign Quad-Precision */
5824 case 868: /* VSX Scalar Insert Exponent Quad-Precision */
5825 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5829 switch (PPC_FIELD (insn
, 11, 5))
5831 case 27: /* VSX Scalar Square Root Quad-Precision */
5832 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5834 case 0: /* VSX Scalar Absolute Quad-Precision */
5835 case 2: /* VSX Scalar Extract Exponent Quad-Precision */
5836 case 8: /* VSX Scalar Negative Absolute Quad-Precision */
5837 case 16: /* VSX Scalar Negate Quad-Precision */
5838 case 18: /* VSX Scalar Extract Significand Quad-Precision */
5839 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5845 switch (PPC_FIELD (insn
, 11, 5))
5847 case 1: /* VSX Scalar truncate & Convert Quad-Precision format
5848 to Unsigned Word format */
5849 case 2: /* VSX Scalar Convert Unsigned Doubleword format to
5850 Quad-Precision format */
5851 case 9: /* VSX Scalar truncate & Convert Quad-Precision format
5852 to Signed Word format */
5853 case 10: /* VSX Scalar Convert Signed Doubleword format to
5854 Quad-Precision format */
5855 case 17: /* VSX Scalar truncate & Convert Quad-Precision format
5856 to Unsigned Doubleword format */
5857 case 20: /* VSX Scalar round & Convert Quad-Precision format to
5858 Double-Precision format */
5859 case 22: /* VSX Scalar Convert Double-Precision format to
5860 Quad-Precision format */
5861 case 25: /* VSX Scalar truncate & Convert Quad-Precision format
5862 to Signed Doubleword format */
5863 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5864 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5869 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5870 "at %s, 63-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5874 /* Parse the current instruction and record the values of the registers and
5875 memory that will be changed in current instruction to "record_arch_list".
5876 Return -1 if something wrong. */
5879 ppc_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5882 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5883 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5887 insn
= read_memory_unsigned_integer (addr
, 4, byte_order
);
5888 op6
= PPC_OP6 (insn
);
5892 case 2: /* Trap Doubleword Immediate */
5893 case 3: /* Trap Word Immediate */
5898 if (ppc_process_record_op4 (gdbarch
, regcache
, addr
, insn
) != 0)
5902 case 17: /* System call */
5903 if (PPC_LEV (insn
) != 0)
5906 if (tdep
->ppc_syscall_record
!= NULL
)
5908 if (tdep
->ppc_syscall_record (regcache
) != 0)
5913 printf_unfiltered (_("no syscall record support\n"));
5918 case 7: /* Multiply Low Immediate */
5919 record_full_arch_list_add_reg (regcache
,
5920 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5923 case 8: /* Subtract From Immediate Carrying */
5924 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5925 record_full_arch_list_add_reg (regcache
,
5926 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5929 case 10: /* Compare Logical Immediate */
5930 case 11: /* Compare Immediate */
5931 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5934 case 13: /* Add Immediate Carrying and Record */
5935 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5937 case 12: /* Add Immediate Carrying */
5938 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5940 case 14: /* Add Immediate */
5941 case 15: /* Add Immediate Shifted */
5942 record_full_arch_list_add_reg (regcache
,
5943 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5946 case 16: /* Branch Conditional */
5947 if ((PPC_BO (insn
) & 0x4) == 0)
5948 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
5950 case 18: /* Branch */
5952 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
5956 if (ppc_process_record_op19 (gdbarch
, regcache
, addr
, insn
) != 0)
5960 case 20: /* Rotate Left Word Immediate then Mask Insert */
5961 case 21: /* Rotate Left Word Immediate then AND with Mask */
5962 case 23: /* Rotate Left Word then AND with Mask */
5963 case 30: /* Rotate Left Doubleword Immediate then Clear Left */
5964 /* Rotate Left Doubleword Immediate then Clear Right */
5965 /* Rotate Left Doubleword Immediate then Clear */
5966 /* Rotate Left Doubleword then Clear Left */
5967 /* Rotate Left Doubleword then Clear Right */
5968 /* Rotate Left Doubleword Immediate then Mask Insert */
5970 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5971 record_full_arch_list_add_reg (regcache
,
5972 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5975 case 28: /* AND Immediate */
5976 case 29: /* AND Immediate Shifted */
5977 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5979 case 24: /* OR Immediate */
5980 case 25: /* OR Immediate Shifted */
5981 case 26: /* XOR Immediate */
5982 case 27: /* XOR Immediate Shifted */
5983 record_full_arch_list_add_reg (regcache
,
5984 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5988 if (ppc_process_record_op31 (gdbarch
, regcache
, addr
, insn
) != 0)
5992 case 33: /* Load Word and Zero with Update */
5993 case 35: /* Load Byte and Zero with Update */
5994 case 41: /* Load Halfword and Zero with Update */
5995 case 43: /* Load Halfword Algebraic with Update */
5996 record_full_arch_list_add_reg (regcache
,
5997 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5999 case 32: /* Load Word and Zero */
6000 case 34: /* Load Byte and Zero */
6001 case 40: /* Load Halfword and Zero */
6002 case 42: /* Load Halfword Algebraic */
6003 record_full_arch_list_add_reg (regcache
,
6004 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
6007 case 46: /* Load Multiple Word */
6008 for (i
= PPC_RT (insn
); i
< 32; i
++)
6009 record_full_arch_list_add_reg (regcache
, tdep
->ppc_gp0_regnum
+ i
);
6012 case 56: /* Load Quadword */
6013 tmp
= tdep
->ppc_gp0_regnum
+ (PPC_RT (insn
) & ~1);
6014 record_full_arch_list_add_reg (regcache
, tmp
);
6015 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
6018 case 49: /* Load Floating-Point Single with Update */
6019 case 51: /* Load Floating-Point Double with Update */
6020 record_full_arch_list_add_reg (regcache
,
6021 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
6023 case 48: /* Load Floating-Point Single */
6024 case 50: /* Load Floating-Point Double */
6025 record_full_arch_list_add_reg (regcache
,
6026 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
6029 case 47: /* Store Multiple Word */
6033 if (PPC_RA (insn
) != 0)
6034 regcache_raw_read_unsigned (regcache
,
6035 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
6038 iaddr
+= PPC_D (insn
);
6039 record_full_arch_list_add_mem (iaddr
, 4 * (32 - PPC_RS (insn
)));
6043 case 37: /* Store Word with Update */
6044 case 39: /* Store Byte with Update */
6045 case 45: /* Store Halfword with Update */
6046 case 53: /* Store Floating-Point Single with Update */
6047 case 55: /* Store Floating-Point Double with Update */
6048 record_full_arch_list_add_reg (regcache
,
6049 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
6051 case 36: /* Store Word */
6052 case 38: /* Store Byte */
6053 case 44: /* Store Halfword */
6054 case 52: /* Store Floating-Point Single */
6055 case 54: /* Store Floating-Point Double */
6060 if (PPC_RA (insn
) != 0)
6061 regcache_raw_read_unsigned (regcache
,
6062 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
6064 iaddr
+= PPC_D (insn
);
6066 if (op6
== 36 || op6
== 37 || op6
== 52 || op6
== 53)
6068 else if (op6
== 54 || op6
== 55)
6070 else if (op6
== 44 || op6
== 45)
6072 else if (op6
== 38 || op6
== 39)
6077 record_full_arch_list_add_mem (iaddr
, size
);
6084 case 0: /* Load Floating-Point Double Pair */
6085 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_RT (insn
) & ~1);
6086 record_full_arch_list_add_reg (regcache
, tmp
);
6087 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
6089 case 2: /* Load VSX Scalar Doubleword */
6090 case 3: /* Load VSX Scalar Single */
6091 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
6098 case 58: /* Load Doubleword */
6099 /* Load Doubleword with Update */
6100 /* Load Word Algebraic */
6101 if (PPC_FIELD (insn
, 30, 2) > 2)
6104 record_full_arch_list_add_reg (regcache
,
6105 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
6106 if (PPC_BIT (insn
, 31))
6107 record_full_arch_list_add_reg (regcache
,
6108 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
6112 if (ppc_process_record_op59 (gdbarch
, regcache
, addr
, insn
) != 0)
6117 if (ppc_process_record_op60 (gdbarch
, regcache
, addr
, insn
) != 0)
6122 if (ppc_process_record_op61 (gdbarch
, regcache
, addr
, insn
) != 0)
6126 case 62: /* Store Doubleword */
6127 /* Store Doubleword with Update */
6128 /* Store Quadword with Update */
6132 int sub2
= PPC_FIELD (insn
, 30, 2);
6137 if (PPC_RA (insn
) != 0)
6138 regcache_raw_read_unsigned (regcache
,
6139 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
6142 size
= (sub2
== 2) ? 16 : 8;
6144 iaddr
+= PPC_DS (insn
) << 2;
6145 record_full_arch_list_add_mem (iaddr
, size
);
6147 if (op6
== 62 && sub2
== 1)
6148 record_full_arch_list_add_reg (regcache
,
6149 tdep
->ppc_gp0_regnum
+
6156 if (ppc_process_record_op63 (gdbarch
, regcache
, addr
, insn
) != 0)
6162 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
6163 "at %s, %d.\n", insn
, paddress (gdbarch
, addr
), op6
);
6167 if (record_full_arch_list_add_reg (regcache
, PPC_PC_REGNUM
))
6169 if (record_full_arch_list_add_end ())
6174 /* Initialize the current architecture based on INFO. If possible, re-use an
6175 architecture from ARCHES, which is a list of architectures already created
6176 during this debugging session.
6178 Called e.g. at program startup, when reading a core file, and when reading
6181 static struct gdbarch
*
6182 rs6000_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
6184 struct gdbarch
*gdbarch
;
6185 struct gdbarch_tdep
*tdep
;
6186 int wordsize
, from_xcoff_exec
, from_elf_exec
;
6187 enum bfd_architecture arch
;
6190 enum auto_boolean soft_float_flag
= powerpc_soft_float_global
;
6192 enum powerpc_long_double_abi long_double_abi
= POWERPC_LONG_DOUBLE_AUTO
;
6193 enum powerpc_vector_abi vector_abi
= powerpc_vector_abi_global
;
6194 enum powerpc_elf_abi elf_abi
= POWERPC_ELF_AUTO
;
6195 int have_fpu
= 0, have_spe
= 0, have_mq
= 0, have_altivec
= 0;
6196 int have_dfp
= 0, have_vsx
= 0, have_ppr
= 0, have_dscr
= 0;
6197 int have_tar
= 0, have_ebb
= 0, have_pmu
= 0, have_htm_spr
= 0;
6198 int have_htm_core
= 0, have_htm_fpu
= 0, have_htm_altivec
= 0;
6199 int have_htm_vsx
= 0, have_htm_ppr
= 0, have_htm_dscr
= 0;
6200 int have_htm_tar
= 0;
6201 int tdesc_wordsize
= -1;
6202 const struct target_desc
*tdesc
= info
.target_desc
;
6203 tdesc_arch_data_up tdesc_data
;
6204 int num_pseudoregs
= 0;
6207 from_xcoff_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
6208 bfd_get_flavour (info
.abfd
) == bfd_target_xcoff_flavour
;
6210 from_elf_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
6211 bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
;
6213 /* Check word size. If INFO is from a binary file, infer it from
6214 that, else choose a likely default. */
6215 if (from_xcoff_exec
)
6217 if (bfd_xcoff_is_xcoff64 (info
.abfd
))
6222 else if (from_elf_exec
)
6224 if (elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
6229 else if (tdesc_has_registers (tdesc
))
6233 if (info
.bfd_arch_info
!= NULL
&& info
.bfd_arch_info
->bits_per_word
!= 0)
6234 wordsize
= (info
.bfd_arch_info
->bits_per_word
6235 / info
.bfd_arch_info
->bits_per_byte
);
6240 /* Get the architecture and machine from the BFD. */
6241 arch
= info
.bfd_arch_info
->arch
;
6242 mach
= info
.bfd_arch_info
->mach
;
6244 /* For e500 executables, the apuinfo section is of help here. Such
6245 section contains the identifier and revision number of each
6246 Application-specific Processing Unit that is present on the
6247 chip. The content of the section is determined by the assembler
6248 which looks at each instruction and determines which unit (and
6249 which version of it) can execute it. Grovel through the section
6250 looking for relevant e500 APUs. */
6252 if (bfd_uses_spe_extensions (info
.abfd
))
6254 arch
= info
.bfd_arch_info
->arch
;
6255 mach
= bfd_mach_ppc_e500
;
6256 bfd_default_set_arch_mach (&abfd
, arch
, mach
);
6257 info
.bfd_arch_info
= bfd_get_arch_info (&abfd
);
6260 /* Find a default target description which describes our register
6261 layout, if we do not already have one. */
6262 if (! tdesc_has_registers (tdesc
))
6264 const struct ppc_variant
*v
;
6266 /* Choose variant. */
6267 v
= find_variant_by_arch (arch
, mach
);
6274 gdb_assert (tdesc_has_registers (tdesc
));
6276 /* Check any target description for validity. */
6277 if (tdesc_has_registers (tdesc
))
6279 static const char *const gprs
[] = {
6280 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6281 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
6282 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
6283 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
6285 const struct tdesc_feature
*feature
;
6287 static const char *const msr_names
[] = { "msr", "ps" };
6288 static const char *const cr_names
[] = { "cr", "cnd" };
6289 static const char *const ctr_names
[] = { "ctr", "cnt" };
6291 feature
= tdesc_find_feature (tdesc
,
6292 "org.gnu.gdb.power.core");
6293 if (feature
== NULL
)
6296 tdesc_data
= tdesc_data_alloc ();
6299 for (i
= 0; i
< ppc_num_gprs
; i
++)
6300 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6302 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6303 PPC_PC_REGNUM
, "pc");
6304 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6305 PPC_LR_REGNUM
, "lr");
6306 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6307 PPC_XER_REGNUM
, "xer");
6309 /* Allow alternate names for these registers, to accomodate GDB's
6311 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
.get (),
6312 PPC_MSR_REGNUM
, msr_names
);
6313 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
.get (),
6314 PPC_CR_REGNUM
, cr_names
);
6315 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
.get (),
6316 PPC_CTR_REGNUM
, ctr_names
);
6321 have_mq
= tdesc_numbered_register (feature
, tdesc_data
.get (),
6322 PPC_MQ_REGNUM
, "mq");
6324 tdesc_wordsize
= tdesc_register_bitsize (feature
, "pc") / 8;
6326 wordsize
= tdesc_wordsize
;
6328 feature
= tdesc_find_feature (tdesc
,
6329 "org.gnu.gdb.power.fpu");
6330 if (feature
!= NULL
)
6332 static const char *const fprs
[] = {
6333 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
6334 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
6335 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
6336 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
6339 for (i
= 0; i
< ppc_num_fprs
; i
++)
6340 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6341 PPC_F0_REGNUM
+ i
, fprs
[i
]);
6342 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6343 PPC_FPSCR_REGNUM
, "fpscr");
6349 /* The fpscr register was expanded in isa 2.05 to 64 bits
6350 along with the addition of the decimal floating point
6352 if (tdesc_register_bitsize (feature
, "fpscr") > 32)
6358 feature
= tdesc_find_feature (tdesc
,
6359 "org.gnu.gdb.power.altivec");
6360 if (feature
!= NULL
)
6362 static const char *const vector_regs
[] = {
6363 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
6364 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
6365 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
6366 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31"
6370 for (i
= 0; i
< ppc_num_gprs
; i
++)
6371 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6374 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6375 PPC_VSCR_REGNUM
, "vscr");
6376 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6377 PPC_VRSAVE_REGNUM
, "vrsave");
6379 if (have_spe
|| !valid_p
)
6386 /* Check for POWER7 VSX registers support. */
6387 feature
= tdesc_find_feature (tdesc
,
6388 "org.gnu.gdb.power.vsx");
6390 if (feature
!= NULL
)
6392 static const char *const vsx_regs
[] = {
6393 "vs0h", "vs1h", "vs2h", "vs3h", "vs4h", "vs5h",
6394 "vs6h", "vs7h", "vs8h", "vs9h", "vs10h", "vs11h",
6395 "vs12h", "vs13h", "vs14h", "vs15h", "vs16h", "vs17h",
6396 "vs18h", "vs19h", "vs20h", "vs21h", "vs22h", "vs23h",
6397 "vs24h", "vs25h", "vs26h", "vs27h", "vs28h", "vs29h",
6403 for (i
= 0; i
< ppc_num_vshrs
; i
++)
6404 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6405 PPC_VSR0_UPPER_REGNUM
+ i
,
6408 if (!valid_p
|| !have_fpu
|| !have_altivec
)
6416 /* On machines supporting the SPE APU, the general-purpose registers
6417 are 64 bits long. There are SIMD vector instructions to treat them
6418 as pairs of floats, but the rest of the instruction set treats them
6419 as 32-bit registers, and only operates on their lower halves.
6421 In the GDB regcache, we treat their high and low halves as separate
6422 registers. The low halves we present as the general-purpose
6423 registers, and then we have pseudo-registers that stitch together
6424 the upper and lower halves and present them as pseudo-registers.
6426 Thus, the target description is expected to supply the upper
6427 halves separately. */
6429 feature
= tdesc_find_feature (tdesc
,
6430 "org.gnu.gdb.power.spe");
6431 if (feature
!= NULL
)
6433 static const char *const upper_spe
[] = {
6434 "ev0h", "ev1h", "ev2h", "ev3h",
6435 "ev4h", "ev5h", "ev6h", "ev7h",
6436 "ev8h", "ev9h", "ev10h", "ev11h",
6437 "ev12h", "ev13h", "ev14h", "ev15h",
6438 "ev16h", "ev17h", "ev18h", "ev19h",
6439 "ev20h", "ev21h", "ev22h", "ev23h",
6440 "ev24h", "ev25h", "ev26h", "ev27h",
6441 "ev28h", "ev29h", "ev30h", "ev31h"
6445 for (i
= 0; i
< ppc_num_gprs
; i
++)
6446 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6447 PPC_SPE_UPPER_GP0_REGNUM
+ i
,
6449 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6450 PPC_SPE_ACC_REGNUM
, "acc");
6451 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6452 PPC_SPE_FSCR_REGNUM
, "spefscr");
6454 if (have_mq
|| have_fpu
|| !valid_p
)
6461 /* Program Priority Register. */
6462 feature
= tdesc_find_feature (tdesc
,
6463 "org.gnu.gdb.power.ppr");
6464 if (feature
!= NULL
)
6467 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6468 PPC_PPR_REGNUM
, "ppr");
6477 /* Data Stream Control Register. */
6478 feature
= tdesc_find_feature (tdesc
,
6479 "org.gnu.gdb.power.dscr");
6480 if (feature
!= NULL
)
6483 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6484 PPC_DSCR_REGNUM
, "dscr");
6493 /* Target Address Register. */
6494 feature
= tdesc_find_feature (tdesc
,
6495 "org.gnu.gdb.power.tar");
6496 if (feature
!= NULL
)
6499 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6500 PPC_TAR_REGNUM
, "tar");
6509 /* Event-based Branching Registers. */
6510 feature
= tdesc_find_feature (tdesc
,
6511 "org.gnu.gdb.power.ebb");
6512 if (feature
!= NULL
)
6514 static const char *const ebb_regs
[] = {
6515 "bescr", "ebbhr", "ebbrr"
6519 for (i
= 0; i
< ARRAY_SIZE (ebb_regs
); i
++)
6520 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6521 PPC_BESCR_REGNUM
+ i
,
6530 /* Subset of the ISA 2.07 Performance Monitor Registers provided
6532 feature
= tdesc_find_feature (tdesc
,
6533 "org.gnu.gdb.power.linux.pmu");
6534 if (feature
!= NULL
)
6538 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6541 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6544 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6547 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6550 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6561 /* Hardware Transactional Memory Registers. */
6562 feature
= tdesc_find_feature (tdesc
,
6563 "org.gnu.gdb.power.htm.spr");
6564 if (feature
!= NULL
)
6566 static const char *const tm_spr_regs
[] = {
6567 "tfhar", "texasr", "tfiar"
6571 for (i
= 0; i
< ARRAY_SIZE (tm_spr_regs
); i
++)
6572 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6573 PPC_TFHAR_REGNUM
+ i
,
6583 feature
= tdesc_find_feature (tdesc
,
6584 "org.gnu.gdb.power.htm.core");
6585 if (feature
!= NULL
)
6587 static const char *const cgprs
[] = {
6588 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
6589 "cr8", "cr9", "cr10", "cr11", "cr12", "cr13", "cr14",
6590 "cr15", "cr16", "cr17", "cr18", "cr19", "cr20", "cr21",
6591 "cr22", "cr23", "cr24", "cr25", "cr26", "cr27", "cr28",
6592 "cr29", "cr30", "cr31", "ccr", "cxer", "clr", "cctr"
6597 for (i
= 0; i
< ARRAY_SIZE (cgprs
); i
++)
6598 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6609 feature
= tdesc_find_feature (tdesc
,
6610 "org.gnu.gdb.power.htm.fpu");
6611 if (feature
!= NULL
)
6615 static const char *const cfprs
[] = {
6616 "cf0", "cf1", "cf2", "cf3", "cf4", "cf5", "cf6", "cf7",
6617 "cf8", "cf9", "cf10", "cf11", "cf12", "cf13", "cf14", "cf15",
6618 "cf16", "cf17", "cf18", "cf19", "cf20", "cf21", "cf22",
6619 "cf23", "cf24", "cf25", "cf26", "cf27", "cf28", "cf29",
6620 "cf30", "cf31", "cfpscr"
6623 for (i
= 0; i
< ARRAY_SIZE (cfprs
); i
++)
6624 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6635 feature
= tdesc_find_feature (tdesc
,
6636 "org.gnu.gdb.power.htm.altivec");
6637 if (feature
!= NULL
)
6641 static const char *const cvmx
[] = {
6642 "cvr0", "cvr1", "cvr2", "cvr3", "cvr4", "cvr5", "cvr6",
6643 "cvr7", "cvr8", "cvr9", "cvr10", "cvr11", "cvr12", "cvr13",
6644 "cvr14", "cvr15","cvr16", "cvr17", "cvr18", "cvr19", "cvr20",
6645 "cvr21", "cvr22", "cvr23", "cvr24", "cvr25", "cvr26",
6646 "cvr27", "cvr28", "cvr29", "cvr30", "cvr31", "cvscr",
6650 for (i
= 0; i
< ARRAY_SIZE (cvmx
); i
++)
6651 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6652 PPC_CVR0_REGNUM
+ i
,
6657 have_htm_altivec
= 1;
6660 have_htm_altivec
= 0;
6662 feature
= tdesc_find_feature (tdesc
,
6663 "org.gnu.gdb.power.htm.vsx");
6664 if (feature
!= NULL
)
6668 static const char *const cvsx
[] = {
6669 "cvs0h", "cvs1h", "cvs2h", "cvs3h", "cvs4h", "cvs5h",
6670 "cvs6h", "cvs7h", "cvs8h", "cvs9h", "cvs10h", "cvs11h",
6671 "cvs12h", "cvs13h", "cvs14h", "cvs15h", "cvs16h", "cvs17h",
6672 "cvs18h", "cvs19h", "cvs20h", "cvs21h", "cvs22h", "cvs23h",
6673 "cvs24h", "cvs25h", "cvs26h", "cvs27h", "cvs28h", "cvs29h",
6677 for (i
= 0; i
< ARRAY_SIZE (cvsx
); i
++)
6678 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6679 (PPC_CVSR0_UPPER_REGNUM
6683 if (!valid_p
|| !have_htm_fpu
|| !have_htm_altivec
)
6690 feature
= tdesc_find_feature (tdesc
,
6691 "org.gnu.gdb.power.htm.ppr");
6692 if (feature
!= NULL
)
6694 valid_p
= tdesc_numbered_register (feature
, tdesc_data
.get (),
6695 PPC_CPPR_REGNUM
, "cppr");
6704 feature
= tdesc_find_feature (tdesc
,
6705 "org.gnu.gdb.power.htm.dscr");
6706 if (feature
!= NULL
)
6708 valid_p
= tdesc_numbered_register (feature
, tdesc_data
.get (),
6709 PPC_CDSCR_REGNUM
, "cdscr");
6718 feature
= tdesc_find_feature (tdesc
,
6719 "org.gnu.gdb.power.htm.tar");
6720 if (feature
!= NULL
)
6722 valid_p
= tdesc_numbered_register (feature
, tdesc_data
.get (),
6723 PPC_CTAR_REGNUM
, "ctar");
6733 /* If we have a 64-bit binary on a 32-bit target, complain. Also
6734 complain for a 32-bit binary on a 64-bit target; we do not yet
6735 support that. For instance, the 32-bit ABI routines expect
6738 As long as there isn't an explicit target description, we'll
6739 choose one based on the BFD architecture and get a word size
6740 matching the binary (probably powerpc:common or
6741 powerpc:common64). So there is only trouble if a 64-bit target
6742 supplies a 64-bit description while debugging a 32-bit
6744 if (tdesc_wordsize
!= -1 && tdesc_wordsize
!= wordsize
)
6750 switch (elf_elfheader (info
.abfd
)->e_flags
& EF_PPC64_ABI
)
6753 elf_abi
= POWERPC_ELF_V1
;
6756 elf_abi
= POWERPC_ELF_V2
;
6763 if (soft_float_flag
== AUTO_BOOLEAN_AUTO
&& from_elf_exec
)
6765 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6766 Tag_GNU_Power_ABI_FP
) & 3)
6769 soft_float_flag
= AUTO_BOOLEAN_FALSE
;
6772 soft_float_flag
= AUTO_BOOLEAN_TRUE
;
6779 if (long_double_abi
== POWERPC_LONG_DOUBLE_AUTO
&& from_elf_exec
)
6781 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6782 Tag_GNU_Power_ABI_FP
) >> 2)
6785 long_double_abi
= POWERPC_LONG_DOUBLE_IBM128
;
6788 long_double_abi
= POWERPC_LONG_DOUBLE_IEEE128
;
6795 if (vector_abi
== POWERPC_VEC_AUTO
&& from_elf_exec
)
6797 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6798 Tag_GNU_Power_ABI_Vector
))
6801 vector_abi
= POWERPC_VEC_GENERIC
;
6804 vector_abi
= POWERPC_VEC_ALTIVEC
;
6807 vector_abi
= POWERPC_VEC_SPE
;
6815 /* At this point, the only supported ELF-based 64-bit little-endian
6816 operating system is GNU/Linux, and this uses the ELFv2 ABI by
6817 default. All other supported ELF-based operating systems use the
6818 ELFv1 ABI by default. Therefore, if the ABI marker is missing,
6819 e.g. because we run a legacy binary, or have attached to a process
6820 and have not found any associated binary file, set the default
6821 according to this heuristic. */
6822 if (elf_abi
== POWERPC_ELF_AUTO
)
6824 if (wordsize
== 8 && info
.byte_order
== BFD_ENDIAN_LITTLE
)
6825 elf_abi
= POWERPC_ELF_V2
;
6827 elf_abi
= POWERPC_ELF_V1
;
6830 if (soft_float_flag
== AUTO_BOOLEAN_TRUE
)
6832 else if (soft_float_flag
== AUTO_BOOLEAN_FALSE
)
6835 soft_float
= !have_fpu
;
6837 /* If we have a hard float binary or setting but no floating point
6838 registers, downgrade to soft float anyway. We're still somewhat
6839 useful in this scenario. */
6840 if (!soft_float
&& !have_fpu
)
6843 /* Similarly for vector registers. */
6844 if (vector_abi
== POWERPC_VEC_ALTIVEC
&& !have_altivec
)
6845 vector_abi
= POWERPC_VEC_GENERIC
;
6847 if (vector_abi
== POWERPC_VEC_SPE
&& !have_spe
)
6848 vector_abi
= POWERPC_VEC_GENERIC
;
6850 if (vector_abi
== POWERPC_VEC_AUTO
)
6853 vector_abi
= POWERPC_VEC_ALTIVEC
;
6855 vector_abi
= POWERPC_VEC_SPE
;
6857 vector_abi
= POWERPC_VEC_GENERIC
;
6860 /* Do not limit the vector ABI based on available hardware, since we
6861 do not yet know what hardware we'll decide we have. Yuck! FIXME! */
6863 /* Find a candidate among extant architectures. */
6864 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
6866 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
6868 /* Word size in the various PowerPC bfd_arch_info structs isn't
6869 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
6870 separate word size check. */
6871 tdep
= gdbarch_tdep (arches
->gdbarch
);
6872 if (tdep
&& tdep
->elf_abi
!= elf_abi
)
6874 if (tdep
&& tdep
->soft_float
!= soft_float
)
6876 if (tdep
&& tdep
->long_double_abi
!= long_double_abi
)
6878 if (tdep
&& tdep
->vector_abi
!= vector_abi
)
6880 if (tdep
&& tdep
->wordsize
== wordsize
)
6881 return arches
->gdbarch
;
6884 /* None found, create a new architecture from INFO, whose bfd_arch_info
6885 validity depends on the source:
6886 - executable useless
6887 - rs6000_host_arch() good
6889 - "set arch" trust blindly
6890 - GDB startup useless but harmless */
6892 tdep
= XCNEW (struct gdbarch_tdep
);
6893 tdep
->wordsize
= wordsize
;
6894 tdep
->elf_abi
= elf_abi
;
6895 tdep
->soft_float
= soft_float
;
6896 tdep
->long_double_abi
= long_double_abi
;
6897 tdep
->vector_abi
= vector_abi
;
6899 gdbarch
= gdbarch_alloc (&info
, tdep
);
6901 tdep
->ppc_gp0_regnum
= PPC_R0_REGNUM
;
6902 tdep
->ppc_toc_regnum
= PPC_R0_REGNUM
+ 2;
6903 tdep
->ppc_ps_regnum
= PPC_MSR_REGNUM
;
6904 tdep
->ppc_cr_regnum
= PPC_CR_REGNUM
;
6905 tdep
->ppc_lr_regnum
= PPC_LR_REGNUM
;
6906 tdep
->ppc_ctr_regnum
= PPC_CTR_REGNUM
;
6907 tdep
->ppc_xer_regnum
= PPC_XER_REGNUM
;
6908 tdep
->ppc_mq_regnum
= have_mq
? PPC_MQ_REGNUM
: -1;
6910 tdep
->ppc_fp0_regnum
= have_fpu
? PPC_F0_REGNUM
: -1;
6911 tdep
->ppc_fpscr_regnum
= have_fpu
? PPC_FPSCR_REGNUM
: -1;
6912 tdep
->ppc_vsr0_upper_regnum
= have_vsx
? PPC_VSR0_UPPER_REGNUM
: -1;
6913 tdep
->ppc_vr0_regnum
= have_altivec
? PPC_VR0_REGNUM
: -1;
6914 tdep
->ppc_vrsave_regnum
= have_altivec
? PPC_VRSAVE_REGNUM
: -1;
6915 tdep
->ppc_ev0_upper_regnum
= have_spe
? PPC_SPE_UPPER_GP0_REGNUM
: -1;
6916 tdep
->ppc_acc_regnum
= have_spe
? PPC_SPE_ACC_REGNUM
: -1;
6917 tdep
->ppc_spefscr_regnum
= have_spe
? PPC_SPE_FSCR_REGNUM
: -1;
6918 tdep
->ppc_ppr_regnum
= have_ppr
? PPC_PPR_REGNUM
: -1;
6919 tdep
->ppc_dscr_regnum
= have_dscr
? PPC_DSCR_REGNUM
: -1;
6920 tdep
->ppc_tar_regnum
= have_tar
? PPC_TAR_REGNUM
: -1;
6921 tdep
->have_ebb
= have_ebb
;
6923 /* If additional pmu registers are added, care must be taken when
6924 setting new fields in the tdep below, to maintain compatibility
6925 with features that only provide some of the registers. Currently
6926 gdb access to the pmu registers is only supported in linux, and
6927 linux only provides a subset of the pmu registers defined in the
6930 tdep
->ppc_mmcr0_regnum
= have_pmu
? PPC_MMCR0_REGNUM
: -1;
6931 tdep
->ppc_mmcr2_regnum
= have_pmu
? PPC_MMCR2_REGNUM
: -1;
6932 tdep
->ppc_siar_regnum
= have_pmu
? PPC_SIAR_REGNUM
: -1;
6933 tdep
->ppc_sdar_regnum
= have_pmu
? PPC_SDAR_REGNUM
: -1;
6934 tdep
->ppc_sier_regnum
= have_pmu
? PPC_SIER_REGNUM
: -1;
6936 tdep
->have_htm_spr
= have_htm_spr
;
6937 tdep
->have_htm_core
= have_htm_core
;
6938 tdep
->have_htm_fpu
= have_htm_fpu
;
6939 tdep
->have_htm_altivec
= have_htm_altivec
;
6940 tdep
->have_htm_vsx
= have_htm_vsx
;
6941 tdep
->ppc_cppr_regnum
= have_htm_ppr
? PPC_CPPR_REGNUM
: -1;
6942 tdep
->ppc_cdscr_regnum
= have_htm_dscr
? PPC_CDSCR_REGNUM
: -1;
6943 tdep
->ppc_ctar_regnum
= have_htm_tar
? PPC_CTAR_REGNUM
: -1;
6945 set_gdbarch_pc_regnum (gdbarch
, PPC_PC_REGNUM
);
6946 set_gdbarch_sp_regnum (gdbarch
, PPC_R0_REGNUM
+ 1);
6947 set_gdbarch_fp0_regnum (gdbarch
, tdep
->ppc_fp0_regnum
);
6948 set_gdbarch_register_sim_regno (gdbarch
, rs6000_register_sim_regno
);
6950 /* The XML specification for PowerPC sensibly calls the MSR "msr".
6951 GDB traditionally called it "ps", though, so let GDB add an
6953 set_gdbarch_ps_regnum (gdbarch
, tdep
->ppc_ps_regnum
);
6956 set_gdbarch_return_value (gdbarch
, ppc64_sysv_abi_return_value
);
6958 set_gdbarch_return_value (gdbarch
, ppc_sysv_abi_return_value
);
6960 /* Set lr_frame_offset. */
6962 tdep
->lr_frame_offset
= 16;
6964 tdep
->lr_frame_offset
= 4;
6966 if (have_spe
|| have_dfp
|| have_altivec
6967 || have_vsx
|| have_htm_fpu
|| have_htm_vsx
)
6969 set_gdbarch_pseudo_register_read (gdbarch
, rs6000_pseudo_register_read
);
6970 set_gdbarch_pseudo_register_write (gdbarch
,
6971 rs6000_pseudo_register_write
);
6972 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
6973 rs6000_ax_pseudo_register_collect
);
6976 set_gdbarch_gen_return_address (gdbarch
, rs6000_gen_return_address
);
6978 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6980 set_gdbarch_num_regs (gdbarch
, PPC_NUM_REGS
);
6983 num_pseudoregs
+= 32;
6985 num_pseudoregs
+= 16;
6987 num_pseudoregs
+= 32;
6989 /* Include both VSX and Extended FP registers. */
6990 num_pseudoregs
+= 96;
6992 num_pseudoregs
+= 16;
6993 /* Include both checkpointed VSX and EFP registers. */
6995 num_pseudoregs
+= 64 + 32;
6997 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudoregs
);
6999 set_gdbarch_ptr_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
7000 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
7001 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
7002 set_gdbarch_long_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
7003 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
7004 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
7005 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
7006 set_gdbarch_long_double_bit (gdbarch
, 16 * TARGET_CHAR_BIT
);
7007 set_gdbarch_char_signed (gdbarch
, 0);
7009 set_gdbarch_frame_align (gdbarch
, rs6000_frame_align
);
7012 set_gdbarch_frame_red_zone_size (gdbarch
, 288);
7014 set_gdbarch_convert_register_p (gdbarch
, rs6000_convert_register_p
);
7015 set_gdbarch_register_to_value (gdbarch
, rs6000_register_to_value
);
7016 set_gdbarch_value_to_register (gdbarch
, rs6000_value_to_register
);
7018 set_gdbarch_stab_reg_to_regnum (gdbarch
, rs6000_stab_reg_to_regnum
);
7019 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, rs6000_dwarf2_reg_to_regnum
);
7022 set_gdbarch_push_dummy_call (gdbarch
, ppc_sysv_abi_push_dummy_call
);
7023 else if (wordsize
== 8)
7024 set_gdbarch_push_dummy_call (gdbarch
, ppc64_sysv_abi_push_dummy_call
);
7026 set_gdbarch_skip_prologue (gdbarch
, rs6000_skip_prologue
);
7027 set_gdbarch_stack_frame_destroyed_p (gdbarch
, rs6000_stack_frame_destroyed_p
);
7028 set_gdbarch_skip_main_prologue (gdbarch
, rs6000_skip_main_prologue
);
7030 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
7032 set_gdbarch_breakpoint_kind_from_pc (gdbarch
,
7033 rs6000_breakpoint::kind_from_pc
);
7034 set_gdbarch_sw_breakpoint_from_kind (gdbarch
,
7035 rs6000_breakpoint::bp_from_kind
);
7037 /* The value of symbols of type N_SO and N_FUN maybe null when
7039 set_gdbarch_sofun_address_maybe_missing (gdbarch
, 1);
7041 /* Handles single stepping of atomic sequences. */
7042 set_gdbarch_software_single_step (gdbarch
, ppc_deal_with_atomic_sequence
);
7044 /* Not sure on this. FIXMEmgo */
7045 set_gdbarch_frame_args_skip (gdbarch
, 8);
7047 /* Helpers for function argument information. */
7048 set_gdbarch_fetch_pointer_argument (gdbarch
, rs6000_fetch_pointer_argument
);
7051 set_gdbarch_in_solib_return_trampoline
7052 (gdbarch
, rs6000_in_solib_return_trampoline
);
7053 set_gdbarch_skip_trampoline_code (gdbarch
, rs6000_skip_trampoline_code
);
7055 /* Hook in the DWARF CFI frame unwinder. */
7056 dwarf2_append_unwinders (gdbarch
);
7057 dwarf2_frame_set_adjust_regnum (gdbarch
, rs6000_adjust_frame_regnum
);
7059 /* Frame handling. */
7060 dwarf2_frame_set_init_reg (gdbarch
, ppc_dwarf2_frame_init_reg
);
7062 /* Setup displaced stepping. */
7063 set_gdbarch_displaced_step_copy_insn (gdbarch
,
7064 ppc_displaced_step_copy_insn
);
7065 set_gdbarch_displaced_step_hw_singlestep (gdbarch
,
7066 ppc_displaced_step_hw_singlestep
);
7067 set_gdbarch_displaced_step_fixup (gdbarch
, ppc_displaced_step_fixup
);
7068 set_gdbarch_displaced_step_prepare (gdbarch
, ppc_displaced_step_prepare
);
7069 set_gdbarch_displaced_step_finish (gdbarch
, ppc_displaced_step_finish
);
7070 set_gdbarch_displaced_step_restore_all_in_ptid
7071 (gdbarch
, ppc_displaced_step_restore_all_in_ptid
);
7073 set_gdbarch_max_insn_length (gdbarch
, PPC_INSN_SIZE
);
7075 /* Hook in ABI-specific overrides, if they have been registered. */
7076 info
.target_desc
= tdesc
;
7077 info
.tdesc_data
= tdesc_data
.get ();
7078 gdbarch_init_osabi (info
, gdbarch
);
7082 case GDB_OSABI_LINUX
:
7083 case GDB_OSABI_NETBSD
:
7084 case GDB_OSABI_UNKNOWN
:
7085 frame_unwind_append_unwinder (gdbarch
, &rs6000_epilogue_frame_unwind
);
7086 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
7087 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
7090 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
7092 frame_unwind_append_unwinder (gdbarch
, &rs6000_epilogue_frame_unwind
);
7093 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
7094 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
7097 set_tdesc_pseudo_register_type (gdbarch
, rs6000_pseudo_register_type
);
7098 set_tdesc_pseudo_register_reggroup_p (gdbarch
,
7099 rs6000_pseudo_register_reggroup_p
);
7100 tdesc_use_registers (gdbarch
, tdesc
, std::move (tdesc_data
));
7102 /* Override the normal target description method to make the SPE upper
7103 halves anonymous. */
7104 set_gdbarch_register_name (gdbarch
, rs6000_register_name
);
7106 /* Choose register numbers for all supported pseudo-registers. */
7107 tdep
->ppc_ev0_regnum
= -1;
7108 tdep
->ppc_dl0_regnum
= -1;
7109 tdep
->ppc_v0_alias_regnum
= -1;
7110 tdep
->ppc_vsr0_regnum
= -1;
7111 tdep
->ppc_efpr0_regnum
= -1;
7112 tdep
->ppc_cdl0_regnum
= -1;
7113 tdep
->ppc_cvsr0_regnum
= -1;
7114 tdep
->ppc_cefpr0_regnum
= -1;
7116 cur_reg
= gdbarch_num_regs (gdbarch
);
7120 tdep
->ppc_ev0_regnum
= cur_reg
;
7125 tdep
->ppc_dl0_regnum
= cur_reg
;
7130 tdep
->ppc_v0_alias_regnum
= cur_reg
;
7135 tdep
->ppc_vsr0_regnum
= cur_reg
;
7137 tdep
->ppc_efpr0_regnum
= cur_reg
;
7142 tdep
->ppc_cdl0_regnum
= cur_reg
;
7147 tdep
->ppc_cvsr0_regnum
= cur_reg
;
7149 tdep
->ppc_cefpr0_regnum
= cur_reg
;
7153 gdb_assert (gdbarch_num_cooked_regs (gdbarch
) == cur_reg
);
7155 /* Register the ravenscar_arch_ops. */
7156 if (mach
== bfd_mach_ppc_e500
)
7157 register_e500_ravenscar_ops (gdbarch
);
7159 register_ppc_ravenscar_ops (gdbarch
);
7161 set_gdbarch_disassembler_options (gdbarch
, &powerpc_disassembler_options
);
7162 set_gdbarch_valid_disassembler_options (gdbarch
,
7163 disassembler_options_powerpc ());
7169 rs6000_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
7171 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
7176 /* FIXME: Dump gdbarch_tdep. */
7180 powerpc_set_soft_float (const char *args
, int from_tty
,
7181 struct cmd_list_element
*c
)
7183 struct gdbarch_info info
;
7185 /* Update the architecture. */
7186 gdbarch_info_init (&info
);
7187 if (!gdbarch_update_p (info
))
7188 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
7192 powerpc_set_vector_abi (const char *args
, int from_tty
,
7193 struct cmd_list_element
*c
)
7195 struct gdbarch_info info
;
7198 for (vector_abi
= POWERPC_VEC_AUTO
;
7199 vector_abi
!= POWERPC_VEC_LAST
;
7201 if (strcmp (powerpc_vector_abi_string
,
7202 powerpc_vector_strings
[vector_abi
]) == 0)
7204 powerpc_vector_abi_global
= (enum powerpc_vector_abi
) vector_abi
;
7208 if (vector_abi
== POWERPC_VEC_LAST
)
7209 internal_error (__FILE__
, __LINE__
, _("Invalid vector ABI accepted: %s."),
7210 powerpc_vector_abi_string
);
7212 /* Update the architecture. */
7213 gdbarch_info_init (&info
);
7214 if (!gdbarch_update_p (info
))
7215 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
7218 /* Show the current setting of the exact watchpoints flag. */
7221 show_powerpc_exact_watchpoints (struct ui_file
*file
, int from_tty
,
7222 struct cmd_list_element
*c
,
7225 fprintf_filtered (file
, _("Use of exact watchpoints is %s.\n"), value
);
7228 /* Read a PPC instruction from memory. */
7231 read_insn (struct frame_info
*frame
, CORE_ADDR pc
)
7233 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7234 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7236 return read_memory_unsigned_integer (pc
, 4, byte_order
);
7239 /* Return non-zero if the instructions at PC match the series
7240 described in PATTERN, or zero otherwise. PATTERN is an array of
7241 'struct ppc_insn_pattern' objects, terminated by an entry whose
7244 When the match is successful, fill INSNS[i] with what PATTERN[i]
7245 matched. If PATTERN[i] is optional, and the instruction wasn't
7246 present, set INSNS[i] to 0 (which is not a valid PPC instruction).
7247 INSNS should have as many elements as PATTERN, minus the terminator.
7248 Note that, if PATTERN contains optional instructions which aren't
7249 present in memory, then INSNS will have holes, so INSNS[i] isn't
7250 necessarily the i'th instruction in memory. */
7253 ppc_insns_match_pattern (struct frame_info
*frame
, CORE_ADDR pc
,
7254 const struct ppc_insn_pattern
*pattern
,
7255 unsigned int *insns
)
7260 for (i
= 0, insn
= 0; pattern
[i
].mask
; i
++)
7263 insn
= read_insn (frame
, pc
);
7265 if ((insn
& pattern
[i
].mask
) == pattern
[i
].data
)
7271 else if (!pattern
[i
].optional
)
7278 /* Return the 'd' field of the d-form instruction INSN, properly
7282 ppc_insn_d_field (unsigned int insn
)
7284 return ((((CORE_ADDR
) insn
& 0xffff) ^ 0x8000) - 0x8000);
7287 /* Return the 'ds' field of the ds-form instruction INSN, with the two
7288 zero bits concatenated at the right, and properly
7292 ppc_insn_ds_field (unsigned int insn
)
7294 return ((((CORE_ADDR
) insn
& 0xfffc) ^ 0x8000) - 0x8000);
7297 /* Initialization code. */
7299 void _initialize_rs6000_tdep ();
7301 _initialize_rs6000_tdep ()
7303 gdbarch_register (bfd_arch_rs6000
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
7304 gdbarch_register (bfd_arch_powerpc
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
7306 /* Initialize the standard target descriptions. */
7307 initialize_tdesc_powerpc_32 ();
7308 initialize_tdesc_powerpc_altivec32 ();
7309 initialize_tdesc_powerpc_vsx32 ();
7310 initialize_tdesc_powerpc_403 ();
7311 initialize_tdesc_powerpc_403gc ();
7312 initialize_tdesc_powerpc_405 ();
7313 initialize_tdesc_powerpc_505 ();
7314 initialize_tdesc_powerpc_601 ();
7315 initialize_tdesc_powerpc_602 ();
7316 initialize_tdesc_powerpc_603 ();
7317 initialize_tdesc_powerpc_604 ();
7318 initialize_tdesc_powerpc_64 ();
7319 initialize_tdesc_powerpc_altivec64 ();
7320 initialize_tdesc_powerpc_vsx64 ();
7321 initialize_tdesc_powerpc_7400 ();
7322 initialize_tdesc_powerpc_750 ();
7323 initialize_tdesc_powerpc_860 ();
7324 initialize_tdesc_powerpc_e500 ();
7325 initialize_tdesc_rs6000 ();
7327 /* Add root prefix command for all "set powerpc"/"show powerpc"
7329 add_basic_prefix_cmd ("powerpc", no_class
,
7330 _("Various PowerPC-specific commands."),
7331 &setpowerpccmdlist
, "set powerpc ", 0, &setlist
);
7333 add_show_prefix_cmd ("powerpc", no_class
,
7334 _("Various PowerPC-specific commands."),
7335 &showpowerpccmdlist
, "show powerpc ", 0, &showlist
);
7337 /* Add a command to allow the user to force the ABI. */
7338 add_setshow_auto_boolean_cmd ("soft-float", class_support
,
7339 &powerpc_soft_float_global
,
7340 _("Set whether to use a soft-float ABI."),
7341 _("Show whether to use a soft-float ABI."),
7343 powerpc_set_soft_float
, NULL
,
7344 &setpowerpccmdlist
, &showpowerpccmdlist
);
7346 add_setshow_enum_cmd ("vector-abi", class_support
, powerpc_vector_strings
,
7347 &powerpc_vector_abi_string
,
7348 _("Set the vector ABI."),
7349 _("Show the vector ABI."),
7350 NULL
, powerpc_set_vector_abi
, NULL
,
7351 &setpowerpccmdlist
, &showpowerpccmdlist
);
7353 add_setshow_boolean_cmd ("exact-watchpoints", class_support
,
7354 &target_exact_watchpoints
,
7356 Set whether to use just one debug register for watchpoints on scalars."),
7358 Show whether to use just one debug register for watchpoints on scalars."),
7360 If true, GDB will use only one debug register when watching a variable of\n\
7361 scalar type, thus assuming that the variable is accessed through the address\n\
7362 of its first byte."),
7363 NULL
, show_powerpc_exact_watchpoints
,
7364 &setpowerpccmdlist
, &showpowerpccmdlist
);