1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
30 #include "arch-utils.h"
35 #include "parser-defs.h"
38 #include "sim-regno.h"
39 #include "gdb/sim-ppc.h"
40 #include "reggroups.h"
41 #include "dwarf2-frame.h"
42 #include "target-descriptions.h"
43 #include "user-regs.h"
45 #include "libbfd.h" /* for bfd_default_set_arch_mach */
46 #include "coff/internal.h" /* for libcoff.h */
47 #include "libcoff.h" /* for xcoff_data */
48 #include "coff/xcoff.h"
54 #include "solib-svr4.h"
57 #include "gdb_assert.h"
60 #include "trad-frame.h"
61 #include "frame-unwind.h"
62 #include "frame-base.h"
64 #include "features/rs6000/powerpc-32.c"
65 #include "features/rs6000/powerpc-altivec32.c"
66 #include "features/rs6000/powerpc-403.c"
67 #include "features/rs6000/powerpc-403gc.c"
68 #include "features/rs6000/powerpc-505.c"
69 #include "features/rs6000/powerpc-601.c"
70 #include "features/rs6000/powerpc-602.c"
71 #include "features/rs6000/powerpc-603.c"
72 #include "features/rs6000/powerpc-604.c"
73 #include "features/rs6000/powerpc-64.c"
74 #include "features/rs6000/powerpc-altivec64.c"
75 #include "features/rs6000/powerpc-7400.c"
76 #include "features/rs6000/powerpc-750.c"
77 #include "features/rs6000/powerpc-860.c"
78 #include "features/rs6000/powerpc-e500.c"
79 #include "features/rs6000/rs6000.c"
81 /* Determine if regnum is an SPE pseudo-register. */
82 #define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \
83 && (regnum) >= (tdep)->ppc_ev0_regnum \
84 && (regnum) < (tdep)->ppc_ev0_regnum + 32)
86 /* Determine if regnum is a decimal float pseudo-register. */
87 #define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \
88 && (regnum) >= (tdep)->ppc_dl0_regnum \
89 && (regnum) < (tdep)->ppc_dl0_regnum + 16)
91 /* The list of available "set powerpc ..." and "show powerpc ..."
93 static struct cmd_list_element
*setpowerpccmdlist
= NULL
;
94 static struct cmd_list_element
*showpowerpccmdlist
= NULL
;
96 static enum auto_boolean powerpc_soft_float_global
= AUTO_BOOLEAN_AUTO
;
98 /* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */
99 static const char *powerpc_vector_strings
[] =
108 /* A variable that can be configured by the user. */
109 static enum powerpc_vector_abi powerpc_vector_abi_global
= POWERPC_VEC_AUTO
;
110 static const char *powerpc_vector_abi_string
= "auto";
112 /* To be used by skip_prologue. */
114 struct rs6000_framedata
116 int offset
; /* total size of frame --- the distance
117 by which we decrement sp to allocate
119 int saved_gpr
; /* smallest # of saved gpr */
120 int saved_fpr
; /* smallest # of saved fpr */
121 int saved_vr
; /* smallest # of saved vr */
122 int saved_ev
; /* smallest # of saved ev */
123 int alloca_reg
; /* alloca register number (frame ptr) */
124 char frameless
; /* true if frameless functions. */
125 char nosavedpc
; /* true if pc not saved. */
126 int gpr_offset
; /* offset of saved gprs from prev sp */
127 int fpr_offset
; /* offset of saved fprs from prev sp */
128 int vr_offset
; /* offset of saved vrs from prev sp */
129 int ev_offset
; /* offset of saved evs from prev sp */
130 int lr_offset
; /* offset of saved lr */
131 int cr_offset
; /* offset of saved cr */
132 int vrsave_offset
; /* offset of saved vrsave register */
136 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
138 altivec_register_p (struct gdbarch
*gdbarch
, int regno
)
140 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
141 if (tdep
->ppc_vr0_regnum
< 0 || tdep
->ppc_vrsave_regnum
< 0)
144 return (regno
>= tdep
->ppc_vr0_regnum
&& regno
<= tdep
->ppc_vrsave_regnum
);
148 /* Return true if REGNO is an SPE register, false otherwise. */
150 spe_register_p (struct gdbarch
*gdbarch
, int regno
)
152 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
154 /* Is it a reference to EV0 -- EV31, and do we have those? */
155 if (IS_SPE_PSEUDOREG (tdep
, regno
))
158 /* Is it a reference to one of the raw upper GPR halves? */
159 if (tdep
->ppc_ev0_upper_regnum
>= 0
160 && tdep
->ppc_ev0_upper_regnum
<= regno
161 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
164 /* Is it a reference to the 64-bit accumulator, and do we have that? */
165 if (tdep
->ppc_acc_regnum
>= 0
166 && tdep
->ppc_acc_regnum
== regno
)
169 /* Is it a reference to the SPE floating-point status and control register,
170 and do we have that? */
171 if (tdep
->ppc_spefscr_regnum
>= 0
172 && tdep
->ppc_spefscr_regnum
== regno
)
179 /* Return non-zero if the architecture described by GDBARCH has
180 floating-point registers (f0 --- f31 and fpscr). */
182 ppc_floating_point_unit_p (struct gdbarch
*gdbarch
)
184 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
186 return (tdep
->ppc_fp0_regnum
>= 0
187 && tdep
->ppc_fpscr_regnum
>= 0);
190 /* Return non-zero if the architecture described by GDBARCH has
191 Altivec registers (vr0 --- vr31, vrsave and vscr). */
193 ppc_altivec_support_p (struct gdbarch
*gdbarch
)
195 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
197 return (tdep
->ppc_vr0_regnum
>= 0
198 && tdep
->ppc_vrsave_regnum
>= 0);
201 /* Check that TABLE[GDB_REGNO] is not already initialized, and then
204 This is a helper function for init_sim_regno_table, constructing
205 the table mapping GDB register numbers to sim register numbers; we
206 initialize every element in that table to -1 before we start
209 set_sim_regno (int *table
, int gdb_regno
, int sim_regno
)
211 /* Make sure we don't try to assign any given GDB register a sim
212 register number more than once. */
213 gdb_assert (table
[gdb_regno
] == -1);
214 table
[gdb_regno
] = sim_regno
;
218 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
219 numbers to simulator register numbers, based on the values placed
220 in the ARCH->tdep->ppc_foo_regnum members. */
222 init_sim_regno_table (struct gdbarch
*arch
)
224 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
225 int total_regs
= gdbarch_num_regs (arch
);
226 int *sim_regno
= GDBARCH_OBSTACK_CALLOC (arch
, total_regs
, int);
228 static const char *const segment_regs
[] = {
229 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
230 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
233 /* Presume that all registers not explicitly mentioned below are
234 unavailable from the sim. */
235 for (i
= 0; i
< total_regs
; i
++)
238 /* General-purpose registers. */
239 for (i
= 0; i
< ppc_num_gprs
; i
++)
240 set_sim_regno (sim_regno
, tdep
->ppc_gp0_regnum
+ i
, sim_ppc_r0_regnum
+ i
);
242 /* Floating-point registers. */
243 if (tdep
->ppc_fp0_regnum
>= 0)
244 for (i
= 0; i
< ppc_num_fprs
; i
++)
245 set_sim_regno (sim_regno
,
246 tdep
->ppc_fp0_regnum
+ i
,
247 sim_ppc_f0_regnum
+ i
);
248 if (tdep
->ppc_fpscr_regnum
>= 0)
249 set_sim_regno (sim_regno
, tdep
->ppc_fpscr_regnum
, sim_ppc_fpscr_regnum
);
251 set_sim_regno (sim_regno
, gdbarch_pc_regnum (arch
), sim_ppc_pc_regnum
);
252 set_sim_regno (sim_regno
, tdep
->ppc_ps_regnum
, sim_ppc_ps_regnum
);
253 set_sim_regno (sim_regno
, tdep
->ppc_cr_regnum
, sim_ppc_cr_regnum
);
255 /* Segment registers. */
256 for (i
= 0; i
< ppc_num_srs
; i
++)
260 gdb_regno
= user_reg_map_name_to_regnum (arch
, segment_regs
[i
], -1);
262 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_sr0_regnum
+ i
);
265 /* Altivec registers. */
266 if (tdep
->ppc_vr0_regnum
>= 0)
268 for (i
= 0; i
< ppc_num_vrs
; i
++)
269 set_sim_regno (sim_regno
,
270 tdep
->ppc_vr0_regnum
+ i
,
271 sim_ppc_vr0_regnum
+ i
);
273 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
274 we can treat this more like the other cases. */
275 set_sim_regno (sim_regno
,
276 tdep
->ppc_vr0_regnum
+ ppc_num_vrs
,
277 sim_ppc_vscr_regnum
);
279 /* vsave is a special-purpose register, so the code below handles it. */
281 /* SPE APU (E500) registers. */
282 if (tdep
->ppc_ev0_upper_regnum
>= 0)
283 for (i
= 0; i
< ppc_num_gprs
; i
++)
284 set_sim_regno (sim_regno
,
285 tdep
->ppc_ev0_upper_regnum
+ i
,
286 sim_ppc_rh0_regnum
+ i
);
287 if (tdep
->ppc_acc_regnum
>= 0)
288 set_sim_regno (sim_regno
, tdep
->ppc_acc_regnum
, sim_ppc_acc_regnum
);
289 /* spefscr is a special-purpose register, so the code below handles it. */
292 /* Now handle all special-purpose registers. Verify that they
293 haven't mistakenly been assigned numbers by any of the above
295 for (i
= 0; i
< sim_ppc_num_sprs
; i
++)
297 const char *spr_name
= sim_spr_register_name (i
);
300 if (spr_name
!= NULL
)
301 gdb_regno
= user_reg_map_name_to_regnum (arch
, spr_name
, -1);
304 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_spr0_regnum
+ i
);
308 /* Drop the initialized array into place. */
309 tdep
->sim_regno
= sim_regno
;
313 /* Given a GDB register number REG, return the corresponding SIM
316 rs6000_register_sim_regno (struct gdbarch
*gdbarch
, int reg
)
318 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
321 if (tdep
->sim_regno
== NULL
)
322 init_sim_regno_table (gdbarch
);
325 && reg
<= gdbarch_num_regs (gdbarch
)
326 + gdbarch_num_pseudo_regs (gdbarch
));
327 sim_regno
= tdep
->sim_regno
[reg
];
332 return LEGACY_SIM_REGNO_IGNORE
;
337 /* Register set support functions. */
339 /* REGS + OFFSET contains register REGNUM in a field REGSIZE wide.
340 Write the register to REGCACHE. */
343 ppc_supply_reg (struct regcache
*regcache
, int regnum
,
344 const gdb_byte
*regs
, size_t offset
, int regsize
)
346 if (regnum
!= -1 && offset
!= -1)
350 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
351 int gdb_regsize
= register_size (gdbarch
, regnum
);
352 if (gdb_regsize
< regsize
353 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
354 offset
+= regsize
- gdb_regsize
;
356 regcache_raw_supply (regcache
, regnum
, regs
+ offset
);
360 /* Read register REGNUM from REGCACHE and store to REGS + OFFSET
361 in a field REGSIZE wide. Zero pad as necessary. */
364 ppc_collect_reg (const struct regcache
*regcache
, int regnum
,
365 gdb_byte
*regs
, size_t offset
, int regsize
)
367 if (regnum
!= -1 && offset
!= -1)
371 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
372 int gdb_regsize
= register_size (gdbarch
, regnum
);
373 if (gdb_regsize
< regsize
)
375 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
377 memset (regs
+ offset
, 0, regsize
- gdb_regsize
);
378 offset
+= regsize
- gdb_regsize
;
381 memset (regs
+ offset
+ regsize
- gdb_regsize
, 0,
382 regsize
- gdb_regsize
);
385 regcache_raw_collect (regcache
, regnum
, regs
+ offset
);
390 ppc_greg_offset (struct gdbarch
*gdbarch
,
391 struct gdbarch_tdep
*tdep
,
392 const struct ppc_reg_offsets
*offsets
,
396 *regsize
= offsets
->gpr_size
;
397 if (regnum
>= tdep
->ppc_gp0_regnum
398 && regnum
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
)
399 return (offsets
->r0_offset
400 + (regnum
- tdep
->ppc_gp0_regnum
) * offsets
->gpr_size
);
402 if (regnum
== gdbarch_pc_regnum (gdbarch
))
403 return offsets
->pc_offset
;
405 if (regnum
== tdep
->ppc_ps_regnum
)
406 return offsets
->ps_offset
;
408 if (regnum
== tdep
->ppc_lr_regnum
)
409 return offsets
->lr_offset
;
411 if (regnum
== tdep
->ppc_ctr_regnum
)
412 return offsets
->ctr_offset
;
414 *regsize
= offsets
->xr_size
;
415 if (regnum
== tdep
->ppc_cr_regnum
)
416 return offsets
->cr_offset
;
418 if (regnum
== tdep
->ppc_xer_regnum
)
419 return offsets
->xer_offset
;
421 if (regnum
== tdep
->ppc_mq_regnum
)
422 return offsets
->mq_offset
;
428 ppc_fpreg_offset (struct gdbarch_tdep
*tdep
,
429 const struct ppc_reg_offsets
*offsets
,
432 if (regnum
>= tdep
->ppc_fp0_regnum
433 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
)
434 return offsets
->f0_offset
+ (regnum
- tdep
->ppc_fp0_regnum
) * 8;
436 if (regnum
== tdep
->ppc_fpscr_regnum
)
437 return offsets
->fpscr_offset
;
443 ppc_vrreg_offset (struct gdbarch_tdep
*tdep
,
444 const struct ppc_reg_offsets
*offsets
,
447 if (regnum
>= tdep
->ppc_vr0_regnum
448 && regnum
< tdep
->ppc_vr0_regnum
+ ppc_num_vrs
)
449 return offsets
->vr0_offset
+ (regnum
- tdep
->ppc_vr0_regnum
) * 16;
451 if (regnum
== tdep
->ppc_vrsave_regnum
- 1)
452 return offsets
->vscr_offset
;
454 if (regnum
== tdep
->ppc_vrsave_regnum
)
455 return offsets
->vrsave_offset
;
460 /* Supply register REGNUM in the general-purpose register set REGSET
461 from the buffer specified by GREGS and LEN to register cache
462 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
465 ppc_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
466 int regnum
, const void *gregs
, size_t len
)
468 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
469 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
470 const struct ppc_reg_offsets
*offsets
= regset
->descr
;
477 int gpr_size
= offsets
->gpr_size
;
479 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
480 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
481 i
++, offset
+= gpr_size
)
482 ppc_supply_reg (regcache
, i
, gregs
, offset
, gpr_size
);
484 ppc_supply_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
485 gregs
, offsets
->pc_offset
, gpr_size
);
486 ppc_supply_reg (regcache
, tdep
->ppc_ps_regnum
,
487 gregs
, offsets
->ps_offset
, gpr_size
);
488 ppc_supply_reg (regcache
, tdep
->ppc_lr_regnum
,
489 gregs
, offsets
->lr_offset
, gpr_size
);
490 ppc_supply_reg (regcache
, tdep
->ppc_ctr_regnum
,
491 gregs
, offsets
->ctr_offset
, gpr_size
);
492 ppc_supply_reg (regcache
, tdep
->ppc_cr_regnum
,
493 gregs
, offsets
->cr_offset
, offsets
->xr_size
);
494 ppc_supply_reg (regcache
, tdep
->ppc_xer_regnum
,
495 gregs
, offsets
->xer_offset
, offsets
->xr_size
);
496 ppc_supply_reg (regcache
, tdep
->ppc_mq_regnum
,
497 gregs
, offsets
->mq_offset
, offsets
->xr_size
);
501 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
502 ppc_supply_reg (regcache
, regnum
, gregs
, offset
, regsize
);
505 /* Supply register REGNUM in the floating-point register set REGSET
506 from the buffer specified by FPREGS and LEN to register cache
507 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
510 ppc_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
511 int regnum
, const void *fpregs
, size_t len
)
513 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
514 struct gdbarch_tdep
*tdep
;
515 const struct ppc_reg_offsets
*offsets
;
518 if (!ppc_floating_point_unit_p (gdbarch
))
521 tdep
= gdbarch_tdep (gdbarch
);
522 offsets
= regset
->descr
;
527 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
528 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
530 ppc_supply_reg (regcache
, i
, fpregs
, offset
, 8);
532 ppc_supply_reg (regcache
, tdep
->ppc_fpscr_regnum
,
533 fpregs
, offsets
->fpscr_offset
, offsets
->fpscr_size
);
537 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
538 ppc_supply_reg (regcache
, regnum
, fpregs
, offset
,
539 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
542 /* Supply register REGNUM in the Altivec register set REGSET
543 from the buffer specified by VRREGS and LEN to register cache
544 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
547 ppc_supply_vrregset (const struct regset
*regset
, struct regcache
*regcache
,
548 int regnum
, const void *vrregs
, size_t len
)
550 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
551 struct gdbarch_tdep
*tdep
;
552 const struct ppc_reg_offsets
*offsets
;
555 if (!ppc_altivec_support_p (gdbarch
))
558 tdep
= gdbarch_tdep (gdbarch
);
559 offsets
= regset
->descr
;
564 for (i
= tdep
->ppc_vr0_regnum
, offset
= offsets
->vr0_offset
;
565 i
< tdep
->ppc_vr0_regnum
+ ppc_num_vrs
;
567 ppc_supply_reg (regcache
, i
, vrregs
, offset
, 16);
569 ppc_supply_reg (regcache
, (tdep
->ppc_vrsave_regnum
- 1),
570 vrregs
, offsets
->vscr_offset
, 4);
572 ppc_supply_reg (regcache
, tdep
->ppc_vrsave_regnum
,
573 vrregs
, offsets
->vrsave_offset
, 4);
577 offset
= ppc_vrreg_offset (tdep
, offsets
, regnum
);
578 if (regnum
!= tdep
->ppc_vrsave_regnum
579 && regnum
!= tdep
->ppc_vrsave_regnum
- 1)
580 ppc_supply_reg (regcache
, regnum
, vrregs
, offset
, 16);
582 ppc_supply_reg (regcache
, regnum
,
586 /* Collect register REGNUM in the general-purpose register set
587 REGSET from register cache REGCACHE into the buffer specified by
588 GREGS and LEN. If REGNUM is -1, do this for all registers in
592 ppc_collect_gregset (const struct regset
*regset
,
593 const struct regcache
*regcache
,
594 int regnum
, void *gregs
, size_t len
)
596 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
597 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
598 const struct ppc_reg_offsets
*offsets
= regset
->descr
;
605 int gpr_size
= offsets
->gpr_size
;
607 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
608 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
609 i
++, offset
+= gpr_size
)
610 ppc_collect_reg (regcache
, i
, gregs
, offset
, gpr_size
);
612 ppc_collect_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
613 gregs
, offsets
->pc_offset
, gpr_size
);
614 ppc_collect_reg (regcache
, tdep
->ppc_ps_regnum
,
615 gregs
, offsets
->ps_offset
, gpr_size
);
616 ppc_collect_reg (regcache
, tdep
->ppc_lr_regnum
,
617 gregs
, offsets
->lr_offset
, gpr_size
);
618 ppc_collect_reg (regcache
, tdep
->ppc_ctr_regnum
,
619 gregs
, offsets
->ctr_offset
, gpr_size
);
620 ppc_collect_reg (regcache
, tdep
->ppc_cr_regnum
,
621 gregs
, offsets
->cr_offset
, offsets
->xr_size
);
622 ppc_collect_reg (regcache
, tdep
->ppc_xer_regnum
,
623 gregs
, offsets
->xer_offset
, offsets
->xr_size
);
624 ppc_collect_reg (regcache
, tdep
->ppc_mq_regnum
,
625 gregs
, offsets
->mq_offset
, offsets
->xr_size
);
629 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
630 ppc_collect_reg (regcache
, regnum
, gregs
, offset
, regsize
);
633 /* Collect register REGNUM in the floating-point register set
634 REGSET from register cache REGCACHE into the buffer specified by
635 FPREGS and LEN. If REGNUM is -1, do this for all registers in
639 ppc_collect_fpregset (const struct regset
*regset
,
640 const struct regcache
*regcache
,
641 int regnum
, void *fpregs
, size_t len
)
643 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
644 struct gdbarch_tdep
*tdep
;
645 const struct ppc_reg_offsets
*offsets
;
648 if (!ppc_floating_point_unit_p (gdbarch
))
651 tdep
= gdbarch_tdep (gdbarch
);
652 offsets
= regset
->descr
;
657 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
658 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
660 ppc_collect_reg (regcache
, i
, fpregs
, offset
, 8);
662 ppc_collect_reg (regcache
, tdep
->ppc_fpscr_regnum
,
663 fpregs
, offsets
->fpscr_offset
, offsets
->fpscr_size
);
667 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
668 ppc_collect_reg (regcache
, regnum
, fpregs
, offset
,
669 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
672 /* Collect register REGNUM in the Altivec register set
673 REGSET from register cache REGCACHE into the buffer specified by
674 VRREGS and LEN. If REGNUM is -1, do this for all registers in
678 ppc_collect_vrregset (const struct regset
*regset
,
679 const struct regcache
*regcache
,
680 int regnum
, void *vrregs
, size_t len
)
682 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
683 struct gdbarch_tdep
*tdep
;
684 const struct ppc_reg_offsets
*offsets
;
687 if (!ppc_altivec_support_p (gdbarch
))
690 tdep
= gdbarch_tdep (gdbarch
);
691 offsets
= regset
->descr
;
696 for (i
= tdep
->ppc_vr0_regnum
, offset
= offsets
->vr0_offset
;
697 i
< tdep
->ppc_vr0_regnum
+ ppc_num_vrs
;
699 ppc_collect_reg (regcache
, i
, vrregs
, offset
, 16);
701 ppc_collect_reg (regcache
, (tdep
->ppc_vrsave_regnum
- 1),
702 vrregs
, offsets
->vscr_offset
, 4);
704 ppc_collect_reg (regcache
, tdep
->ppc_vrsave_regnum
,
705 vrregs
, offsets
->vrsave_offset
, 4);
709 offset
= ppc_vrreg_offset (tdep
, offsets
, regnum
);
710 if (regnum
!= tdep
->ppc_vrsave_regnum
711 && regnum
!= tdep
->ppc_vrsave_regnum
- 1)
712 ppc_collect_reg (regcache
, regnum
, vrregs
, offset
, 16);
714 ppc_collect_reg (regcache
, regnum
,
720 insn_changes_sp_or_jumps (unsigned long insn
)
722 int opcode
= (insn
>> 26) & 0x03f;
723 int sd
= (insn
>> 21) & 0x01f;
724 int a
= (insn
>> 16) & 0x01f;
725 int subcode
= (insn
>> 1) & 0x3ff;
727 /* Changes the stack pointer. */
729 /* NOTE: There are many ways to change the value of a given register.
730 The ways below are those used when the register is R1, the SP,
731 in a funtion's epilogue. */
733 if (opcode
== 31 && subcode
== 444 && a
== 1)
734 return 1; /* mr R1,Rn */
735 if (opcode
== 14 && sd
== 1)
736 return 1; /* addi R1,Rn,simm */
737 if (opcode
== 58 && sd
== 1)
738 return 1; /* ld R1,ds(Rn) */
740 /* Transfers control. */
746 if (opcode
== 19 && subcode
== 16)
748 if (opcode
== 19 && subcode
== 528)
749 return 1; /* bcctr */
754 /* Return true if we are in the function's epilogue, i.e. after the
755 instruction that destroyed the function's stack frame.
757 1) scan forward from the point of execution:
758 a) If you find an instruction that modifies the stack pointer
759 or transfers control (except a return), execution is not in
761 b) Stop scanning if you find a return instruction or reach the
762 end of the function or reach the hard limit for the size of
764 2) scan backward from the point of execution:
765 a) If you find an instruction that modifies the stack pointer,
766 execution *is* in an epilogue, return.
767 b) Stop scanning if you reach an instruction that transfers
768 control or the beginning of the function or reach the hard
769 limit for the size of an epilogue. */
772 rs6000_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
774 bfd_byte insn_buf
[PPC_INSN_SIZE
];
775 CORE_ADDR scan_pc
, func_start
, func_end
, epilogue_start
, epilogue_end
;
777 struct frame_info
*curfrm
;
779 /* Find the search limits based on function boundaries and hard limit. */
781 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
784 epilogue_start
= pc
- PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
785 if (epilogue_start
< func_start
) epilogue_start
= func_start
;
787 epilogue_end
= pc
+ PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
788 if (epilogue_end
> func_end
) epilogue_end
= func_end
;
790 curfrm
= get_current_frame ();
792 /* Scan forward until next 'blr'. */
794 for (scan_pc
= pc
; scan_pc
< epilogue_end
; scan_pc
+= PPC_INSN_SIZE
)
796 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
798 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
);
799 if (insn
== 0x4e800020)
801 if (insn_changes_sp_or_jumps (insn
))
805 /* Scan backward until adjustment to stack pointer (R1). */
807 for (scan_pc
= pc
- PPC_INSN_SIZE
;
808 scan_pc
>= epilogue_start
;
809 scan_pc
-= PPC_INSN_SIZE
)
811 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
813 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
);
814 if (insn_changes_sp_or_jumps (insn
))
821 /* Get the ith function argument for the current function. */
823 rs6000_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
826 return get_frame_register_unsigned (frame
, 3 + argi
);
829 /* Sequence of bytes for breakpoint instruction. */
831 const static unsigned char *
832 rs6000_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*bp_addr
,
835 static unsigned char big_breakpoint
[] = { 0x7d, 0x82, 0x10, 0x08 };
836 static unsigned char little_breakpoint
[] = { 0x08, 0x10, 0x82, 0x7d };
838 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
839 return big_breakpoint
;
841 return little_breakpoint
;
845 /* Instruction masks used during single-stepping of atomic sequences. */
846 #define LWARX_MASK 0xfc0007fe
847 #define LWARX_INSTRUCTION 0x7c000028
848 #define LDARX_INSTRUCTION 0x7c0000A8
849 #define STWCX_MASK 0xfc0007ff
850 #define STWCX_INSTRUCTION 0x7c00012d
851 #define STDCX_INSTRUCTION 0x7c0001ad
852 #define BC_MASK 0xfc000000
853 #define BC_INSTRUCTION 0x40000000
855 /* Checks for an atomic sequence of instructions beginning with a LWARX/LDARX
856 instruction and ending with a STWCX/STDCX instruction. If such a sequence
857 is found, attempt to step through it. A breakpoint is placed at the end of
861 ppc_deal_with_atomic_sequence (struct frame_info
*frame
)
863 CORE_ADDR pc
= get_frame_pc (frame
);
864 CORE_ADDR breaks
[2] = {-1, -1};
866 CORE_ADDR closing_insn
; /* Instruction that closes the atomic sequence. */
867 int insn
= read_memory_integer (loc
, PPC_INSN_SIZE
);
870 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
871 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
872 int opcode
; /* Branch instruction's OPcode. */
873 int bc_insn_count
= 0; /* Conditional branch instruction count. */
875 /* Assume all atomic sequences start with a lwarx/ldarx instruction. */
876 if ((insn
& LWARX_MASK
) != LWARX_INSTRUCTION
877 && (insn
& LWARX_MASK
) != LDARX_INSTRUCTION
)
880 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
882 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
884 loc
+= PPC_INSN_SIZE
;
885 insn
= read_memory_integer (loc
, PPC_INSN_SIZE
);
887 /* Assume that there is at most one conditional branch in the atomic
888 sequence. If a conditional branch is found, put a breakpoint in
889 its destination address. */
890 if ((insn
& BC_MASK
) == BC_INSTRUCTION
)
892 int immediate
= ((insn
& ~3) << 16) >> 16;
893 int absolute
= ((insn
>> 1) & 1);
895 if (bc_insn_count
>= 1)
896 return 0; /* More than one conditional branch found, fallback
897 to the standard single-step code. */
900 breaks
[1] = immediate
;
902 breaks
[1] = pc
+ immediate
;
908 if ((insn
& STWCX_MASK
) == STWCX_INSTRUCTION
909 || (insn
& STWCX_MASK
) == STDCX_INSTRUCTION
)
913 /* Assume that the atomic sequence ends with a stwcx/stdcx instruction. */
914 if ((insn
& STWCX_MASK
) != STWCX_INSTRUCTION
915 && (insn
& STWCX_MASK
) != STDCX_INSTRUCTION
)
919 loc
+= PPC_INSN_SIZE
;
920 insn
= read_memory_integer (loc
, PPC_INSN_SIZE
);
922 /* Insert a breakpoint right after the end of the atomic sequence. */
925 /* Check for duplicated breakpoints. Check also for a breakpoint
926 placed (branch instruction's destination) at the stwcx/stdcx
927 instruction, this resets the reservation and take us back to the
928 lwarx/ldarx instruction at the beginning of the atomic sequence. */
929 if (last_breakpoint
&& ((breaks
[1] == breaks
[0])
930 || (breaks
[1] == closing_insn
)))
933 /* Effectively inserts the breakpoints. */
934 for (index
= 0; index
<= last_breakpoint
; index
++)
935 insert_single_step_breakpoint (breaks
[index
]);
941 #define SIGNED_SHORT(x) \
942 ((sizeof (short) == 2) \
943 ? ((int)(short)(x)) \
944 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
946 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
948 /* Limit the number of skipped non-prologue instructions, as the examining
949 of the prologue is expensive. */
950 static int max_skip_non_prologue_insns
= 10;
952 /* Return nonzero if the given instruction OP can be part of the prologue
953 of a function and saves a parameter on the stack. FRAMEP should be
954 set if one of the previous instructions in the function has set the
958 store_param_on_stack_p (unsigned long op
, int framep
, int *r0_contains_arg
)
960 /* Move parameters from argument registers to temporary register. */
961 if ((op
& 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
963 /* Rx must be scratch register r0. */
964 const int rx_regno
= (op
>> 16) & 31;
965 /* Ry: Only r3 - r10 are used for parameter passing. */
966 const int ry_regno
= GET_SRC_REG (op
);
968 if (rx_regno
== 0 && ry_regno
>= 3 && ry_regno
<= 10)
970 *r0_contains_arg
= 1;
977 /* Save a General Purpose Register on stack. */
979 if ((op
& 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
980 (op
& 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
982 /* Rx: Only r3 - r10 are used for parameter passing. */
983 const int rx_regno
= GET_SRC_REG (op
);
985 return (rx_regno
>= 3 && rx_regno
<= 10);
988 /* Save a General Purpose Register on stack via the Frame Pointer. */
991 ((op
& 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
992 (op
& 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
993 (op
& 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
995 /* Rx: Usually, only r3 - r10 are used for parameter passing.
996 However, the compiler sometimes uses r0 to hold an argument. */
997 const int rx_regno
= GET_SRC_REG (op
);
999 return ((rx_regno
>= 3 && rx_regno
<= 10)
1000 || (rx_regno
== 0 && *r0_contains_arg
));
1003 if ((op
& 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
1005 /* Only f2 - f8 are used for parameter passing. */
1006 const int src_regno
= GET_SRC_REG (op
);
1008 return (src_regno
>= 2 && src_regno
<= 8);
1011 if (framep
&& ((op
& 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
1013 /* Only f2 - f8 are used for parameter passing. */
1014 const int src_regno
= GET_SRC_REG (op
);
1016 return (src_regno
>= 2 && src_regno
<= 8);
1019 /* Not an insn that saves a parameter on stack. */
1023 /* Assuming that INSN is a "bl" instruction located at PC, return
1024 nonzero if the destination of the branch is a "blrl" instruction.
1026 This sequence is sometimes found in certain function prologues.
1027 It allows the function to load the LR register with a value that
1028 they can use to access PIC data using PC-relative offsets. */
1031 bl_to_blrl_insn_p (CORE_ADDR pc
, int insn
)
1038 absolute
= (int) ((insn
>> 1) & 1);
1039 immediate
= ((insn
& ~3) << 6) >> 6;
1043 dest
= pc
+ immediate
;
1045 dest_insn
= read_memory_integer (dest
, 4);
1046 if ((dest_insn
& 0xfc00ffff) == 0x4c000021) /* blrl */
1052 /* return pc value after skipping a function prologue and also return
1053 information about a function frame.
1055 in struct rs6000_framedata fdata:
1056 - frameless is TRUE, if function does not have a frame.
1057 - nosavedpc is TRUE, if function does not save %pc value in its frame.
1058 - offset is the initial size of this stack frame --- the amount by
1059 which we decrement the sp to allocate the frame.
1060 - saved_gpr is the number of the first saved gpr.
1061 - saved_fpr is the number of the first saved fpr.
1062 - saved_vr is the number of the first saved vr.
1063 - saved_ev is the number of the first saved ev.
1064 - alloca_reg is the number of the register used for alloca() handling.
1066 - gpr_offset is the offset of the first saved gpr from the previous frame.
1067 - fpr_offset is the offset of the first saved fpr from the previous frame.
1068 - vr_offset is the offset of the first saved vr from the previous frame.
1069 - ev_offset is the offset of the first saved ev from the previous frame.
1070 - lr_offset is the offset of the saved lr
1071 - cr_offset is the offset of the saved cr
1072 - vrsave_offset is the offset of the saved vrsave register
1076 skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
, CORE_ADDR lim_pc
,
1077 struct rs6000_framedata
*fdata
)
1079 CORE_ADDR orig_pc
= pc
;
1080 CORE_ADDR last_prologue_pc
= pc
;
1081 CORE_ADDR li_found_pc
= 0;
1085 long vr_saved_offset
= 0;
1091 int vrsave_reg
= -1;
1094 int minimal_toc_loaded
= 0;
1095 int prev_insn_was_prologue_insn
= 1;
1096 int num_skip_non_prologue_insns
= 0;
1097 int r0_contains_arg
= 0;
1098 const struct bfd_arch_info
*arch_info
= gdbarch_bfd_arch_info (gdbarch
);
1099 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1101 memset (fdata
, 0, sizeof (struct rs6000_framedata
));
1102 fdata
->saved_gpr
= -1;
1103 fdata
->saved_fpr
= -1;
1104 fdata
->saved_vr
= -1;
1105 fdata
->saved_ev
= -1;
1106 fdata
->alloca_reg
= -1;
1107 fdata
->frameless
= 1;
1108 fdata
->nosavedpc
= 1;
1112 /* Sometimes it isn't clear if an instruction is a prologue
1113 instruction or not. When we encounter one of these ambiguous
1114 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
1115 Otherwise, we'll assume that it really is a prologue instruction. */
1116 if (prev_insn_was_prologue_insn
)
1117 last_prologue_pc
= pc
;
1119 /* Stop scanning if we've hit the limit. */
1123 prev_insn_was_prologue_insn
= 1;
1125 /* Fetch the instruction and convert it to an integer. */
1126 if (target_read_memory (pc
, buf
, 4))
1128 op
= extract_unsigned_integer (buf
, 4);
1130 if ((op
& 0xfc1fffff) == 0x7c0802a6)
1132 /* Since shared library / PIC code, which needs to get its
1133 address at runtime, can appear to save more than one link
1147 remember just the first one, but skip over additional
1150 lr_reg
= (op
& 0x03e00000);
1152 r0_contains_arg
= 0;
1155 else if ((op
& 0xfc1fffff) == 0x7c000026)
1157 cr_reg
= (op
& 0x03e00000);
1159 r0_contains_arg
= 0;
1163 else if ((op
& 0xfc1f0000) == 0xd8010000)
1164 { /* stfd Rx,NUM(r1) */
1165 reg
= GET_SRC_REG (op
);
1166 if (fdata
->saved_fpr
== -1 || fdata
->saved_fpr
> reg
)
1168 fdata
->saved_fpr
= reg
;
1169 fdata
->fpr_offset
= SIGNED_SHORT (op
) + offset
;
1174 else if (((op
& 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
1175 (((op
& 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1176 (op
& 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1177 (op
& 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
1180 reg
= GET_SRC_REG (op
);
1181 if (fdata
->saved_gpr
== -1 || fdata
->saved_gpr
> reg
)
1183 fdata
->saved_gpr
= reg
;
1184 if ((op
& 0xfc1f0003) == 0xf8010000)
1186 fdata
->gpr_offset
= SIGNED_SHORT (op
) + offset
;
1191 else if ((op
& 0xffff0000) == 0x60000000)
1194 /* Allow nops in the prologue, but do not consider them to
1195 be part of the prologue unless followed by other prologue
1197 prev_insn_was_prologue_insn
= 0;
1201 else if ((op
& 0xffff0000) == 0x3c000000)
1202 { /* addis 0,0,NUM, used
1203 for >= 32k frames */
1204 fdata
->offset
= (op
& 0x0000ffff) << 16;
1205 fdata
->frameless
= 0;
1206 r0_contains_arg
= 0;
1210 else if ((op
& 0xffff0000) == 0x60000000)
1211 { /* ori 0,0,NUM, 2nd ha
1212 lf of >= 32k frames */
1213 fdata
->offset
|= (op
& 0x0000ffff);
1214 fdata
->frameless
= 0;
1215 r0_contains_arg
= 0;
1219 else if (lr_reg
>= 0 &&
1220 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1221 (((op
& 0xffff0000) == (lr_reg
| 0xf8010000)) ||
1222 /* stw Rx, NUM(r1) */
1223 ((op
& 0xffff0000) == (lr_reg
| 0x90010000)) ||
1224 /* stwu Rx, NUM(r1) */
1225 ((op
& 0xffff0000) == (lr_reg
| 0x94010000))))
1226 { /* where Rx == lr */
1227 fdata
->lr_offset
= offset
;
1228 fdata
->nosavedpc
= 0;
1229 /* Invalidate lr_reg, but don't set it to -1.
1230 That would mean that it had never been set. */
1232 if ((op
& 0xfc000003) == 0xf8000000 || /* std */
1233 (op
& 0xfc000000) == 0x90000000) /* stw */
1235 /* Does not update r1, so add displacement to lr_offset. */
1236 fdata
->lr_offset
+= SIGNED_SHORT (op
);
1241 else if (cr_reg
>= 0 &&
1242 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1243 (((op
& 0xffff0000) == (cr_reg
| 0xf8010000)) ||
1244 /* stw Rx, NUM(r1) */
1245 ((op
& 0xffff0000) == (cr_reg
| 0x90010000)) ||
1246 /* stwu Rx, NUM(r1) */
1247 ((op
& 0xffff0000) == (cr_reg
| 0x94010000))))
1248 { /* where Rx == cr */
1249 fdata
->cr_offset
= offset
;
1250 /* Invalidate cr_reg, but don't set it to -1.
1251 That would mean that it had never been set. */
1253 if ((op
& 0xfc000003) == 0xf8000000 ||
1254 (op
& 0xfc000000) == 0x90000000)
1256 /* Does not update r1, so add displacement to cr_offset. */
1257 fdata
->cr_offset
+= SIGNED_SHORT (op
);
1262 else if ((op
& 0xfe80ffff) == 0x42800005 && lr_reg
!= -1)
1264 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1265 prediction bits. If the LR has already been saved, we can
1269 else if (op
== 0x48000005)
1275 else if (op
== 0x48000004)
1280 else if ((op
& 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1281 in V.4 -mminimal-toc */
1282 (op
& 0xffff0000) == 0x3bde0000)
1283 { /* addi 30,30,foo@l */
1287 else if ((op
& 0xfc000001) == 0x48000001)
1291 fdata
->frameless
= 0;
1293 /* If the return address has already been saved, we can skip
1294 calls to blrl (for PIC). */
1295 if (lr_reg
!= -1 && bl_to_blrl_insn_p (pc
, op
))
1298 /* Don't skip over the subroutine call if it is not within
1299 the first three instructions of the prologue and either
1300 we have no line table information or the line info tells
1301 us that the subroutine call is not part of the line
1302 associated with the prologue. */
1303 if ((pc
- orig_pc
) > 8)
1305 struct symtab_and_line prologue_sal
= find_pc_line (orig_pc
, 0);
1306 struct symtab_and_line this_sal
= find_pc_line (pc
, 0);
1308 if ((prologue_sal
.line
== 0) || (prologue_sal
.line
!= this_sal
.line
))
1312 op
= read_memory_integer (pc
+ 4, 4);
1314 /* At this point, make sure this is not a trampoline
1315 function (a function that simply calls another functions,
1316 and nothing else). If the next is not a nop, this branch
1317 was part of the function prologue. */
1319 if (op
== 0x4def7b82 || op
== 0) /* crorc 15, 15, 15 */
1320 break; /* don't skip over
1325 /* update stack pointer */
1326 else if ((op
& 0xfc1f0000) == 0x94010000)
1327 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
1328 fdata
->frameless
= 0;
1329 fdata
->offset
= SIGNED_SHORT (op
);
1330 offset
= fdata
->offset
;
1333 else if ((op
& 0xfc1f016a) == 0x7c01016e)
1334 { /* stwux rX,r1,rY */
1335 /* no way to figure out what r1 is going to be */
1336 fdata
->frameless
= 0;
1337 offset
= fdata
->offset
;
1340 else if ((op
& 0xfc1f0003) == 0xf8010001)
1341 { /* stdu rX,NUM(r1) */
1342 fdata
->frameless
= 0;
1343 fdata
->offset
= SIGNED_SHORT (op
& ~3UL);
1344 offset
= fdata
->offset
;
1347 else if ((op
& 0xfc1f016a) == 0x7c01016a)
1348 { /* stdux rX,r1,rY */
1349 /* no way to figure out what r1 is going to be */
1350 fdata
->frameless
= 0;
1351 offset
= fdata
->offset
;
1354 else if ((op
& 0xffff0000) == 0x38210000)
1355 { /* addi r1,r1,SIMM */
1356 fdata
->frameless
= 0;
1357 fdata
->offset
+= SIGNED_SHORT (op
);
1358 offset
= fdata
->offset
;
1361 /* Load up minimal toc pointer. Do not treat an epilogue restore
1362 of r31 as a minimal TOC load. */
1363 else if (((op
>> 22) == 0x20f || /* l r31,... or l r30,... */
1364 (op
>> 22) == 0x3af) /* ld r31,... or ld r30,... */
1366 && !minimal_toc_loaded
)
1368 minimal_toc_loaded
= 1;
1371 /* move parameters from argument registers to local variable
1374 else if ((op
& 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1375 (((op
>> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1376 (((op
>> 21) & 31) <= 10) &&
1377 ((long) ((op
>> 16) & 31) >= fdata
->saved_gpr
)) /* Rx: local var reg */
1381 /* store parameters in stack */
1383 /* Move parameters from argument registers to temporary register. */
1384 else if (store_param_on_stack_p (op
, framep
, &r0_contains_arg
))
1388 /* Set up frame pointer */
1390 else if (op
== 0x603f0000 /* oril r31, r1, 0x0 */
1391 || op
== 0x7c3f0b78)
1393 fdata
->frameless
= 0;
1395 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 31);
1398 /* Another way to set up the frame pointer. */
1400 else if ((op
& 0xfc1fffff) == 0x38010000)
1401 { /* addi rX, r1, 0x0 */
1402 fdata
->frameless
= 0;
1404 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
1405 + ((op
& ~0x38010000) >> 21));
1408 /* AltiVec related instructions. */
1409 /* Store the vrsave register (spr 256) in another register for
1410 later manipulation, or load a register into the vrsave
1411 register. 2 instructions are used: mfvrsave and
1412 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1413 and mtspr SPR256, Rn. */
1414 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1415 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1416 else if ((op
& 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1418 vrsave_reg
= GET_SRC_REG (op
);
1421 else if ((op
& 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1425 /* Store the register where vrsave was saved to onto the stack:
1426 rS is the register where vrsave was stored in a previous
1428 /* 100100 sssss 00001 dddddddd dddddddd */
1429 else if ((op
& 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1431 if (vrsave_reg
== GET_SRC_REG (op
))
1433 fdata
->vrsave_offset
= SIGNED_SHORT (op
) + offset
;
1438 /* Compute the new value of vrsave, by modifying the register
1439 where vrsave was saved to. */
1440 else if (((op
& 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1441 || ((op
& 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1445 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1446 in a pair of insns to save the vector registers on the
1448 /* 001110 00000 00000 iiii iiii iiii iiii */
1449 /* 001110 01110 00000 iiii iiii iiii iiii */
1450 else if ((op
& 0xffff0000) == 0x38000000 /* li r0, SIMM */
1451 || (op
& 0xffff0000) == 0x39c00000) /* li r14, SIMM */
1453 if ((op
& 0xffff0000) == 0x38000000)
1454 r0_contains_arg
= 0;
1456 vr_saved_offset
= SIGNED_SHORT (op
);
1458 /* This insn by itself is not part of the prologue, unless
1459 if part of the pair of insns mentioned above. So do not
1460 record this insn as part of the prologue yet. */
1461 prev_insn_was_prologue_insn
= 0;
1463 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1464 /* 011111 sssss 11111 00000 00111001110 */
1465 else if ((op
& 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1467 if (pc
== (li_found_pc
+ 4))
1469 vr_reg
= GET_SRC_REG (op
);
1470 /* If this is the first vector reg to be saved, or if
1471 it has a lower number than others previously seen,
1472 reupdate the frame info. */
1473 if (fdata
->saved_vr
== -1 || fdata
->saved_vr
> vr_reg
)
1475 fdata
->saved_vr
= vr_reg
;
1476 fdata
->vr_offset
= vr_saved_offset
+ offset
;
1478 vr_saved_offset
= -1;
1483 /* End AltiVec related instructions. */
1485 /* Start BookE related instructions. */
1486 /* Store gen register S at (r31+uimm).
1487 Any register less than r13 is volatile, so we don't care. */
1488 /* 000100 sssss 11111 iiiii 01100100001 */
1489 else if (arch_info
->mach
== bfd_mach_ppc_e500
1490 && (op
& 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
1492 if ((op
& 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
1495 ev_reg
= GET_SRC_REG (op
);
1496 imm
= (op
>> 11) & 0x1f;
1497 ev_offset
= imm
* 8;
1498 /* If this is the first vector reg to be saved, or if
1499 it has a lower number than others previously seen,
1500 reupdate the frame info. */
1501 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1503 fdata
->saved_ev
= ev_reg
;
1504 fdata
->ev_offset
= ev_offset
+ offset
;
1509 /* Store gen register rS at (r1+rB). */
1510 /* 000100 sssss 00001 bbbbb 01100100000 */
1511 else if (arch_info
->mach
== bfd_mach_ppc_e500
1512 && (op
& 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1514 if (pc
== (li_found_pc
+ 4))
1516 ev_reg
= GET_SRC_REG (op
);
1517 /* If this is the first vector reg to be saved, or if
1518 it has a lower number than others previously seen,
1519 reupdate the frame info. */
1520 /* We know the contents of rB from the previous instruction. */
1521 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1523 fdata
->saved_ev
= ev_reg
;
1524 fdata
->ev_offset
= vr_saved_offset
+ offset
;
1526 vr_saved_offset
= -1;
1532 /* Store gen register r31 at (rA+uimm). */
1533 /* 000100 11111 aaaaa iiiii 01100100001 */
1534 else if (arch_info
->mach
== bfd_mach_ppc_e500
1535 && (op
& 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
1537 /* Wwe know that the source register is 31 already, but
1538 it can't hurt to compute it. */
1539 ev_reg
= GET_SRC_REG (op
);
1540 ev_offset
= ((op
>> 11) & 0x1f) * 8;
1541 /* If this is the first vector reg to be saved, or if
1542 it has a lower number than others previously seen,
1543 reupdate the frame info. */
1544 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1546 fdata
->saved_ev
= ev_reg
;
1547 fdata
->ev_offset
= ev_offset
+ offset
;
1552 /* Store gen register S at (r31+r0).
1553 Store param on stack when offset from SP bigger than 4 bytes. */
1554 /* 000100 sssss 11111 00000 01100100000 */
1555 else if (arch_info
->mach
== bfd_mach_ppc_e500
1556 && (op
& 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
1558 if (pc
== (li_found_pc
+ 4))
1560 if ((op
& 0x03e00000) >= 0x01a00000)
1562 ev_reg
= GET_SRC_REG (op
);
1563 /* If this is the first vector reg to be saved, or if
1564 it has a lower number than others previously seen,
1565 reupdate the frame info. */
1566 /* We know the contents of r0 from the previous
1568 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1570 fdata
->saved_ev
= ev_reg
;
1571 fdata
->ev_offset
= vr_saved_offset
+ offset
;
1575 vr_saved_offset
= -1;
1580 /* End BookE related instructions. */
1584 /* Not a recognized prologue instruction.
1585 Handle optimizer code motions into the prologue by continuing
1586 the search if we have no valid frame yet or if the return
1587 address is not yet saved in the frame. */
1588 if (fdata
->frameless
== 0 && fdata
->nosavedpc
== 0)
1591 if (op
== 0x4e800020 /* blr */
1592 || op
== 0x4e800420) /* bctr */
1593 /* Do not scan past epilogue in frameless functions or
1596 if ((op
& 0xf4000000) == 0x40000000) /* bxx */
1597 /* Never skip branches. */
1600 if (num_skip_non_prologue_insns
++ > max_skip_non_prologue_insns
)
1601 /* Do not scan too many insns, scanning insns is expensive with
1605 /* Continue scanning. */
1606 prev_insn_was_prologue_insn
= 0;
1612 /* I have problems with skipping over __main() that I need to address
1613 * sometime. Previously, I used to use misc_function_vector which
1614 * didn't work as well as I wanted to be. -MGO */
1616 /* If the first thing after skipping a prolog is a branch to a function,
1617 this might be a call to an initializer in main(), introduced by gcc2.
1618 We'd like to skip over it as well. Fortunately, xlc does some extra
1619 work before calling a function right after a prologue, thus we can
1620 single out such gcc2 behaviour. */
1623 if ((op
& 0xfc000001) == 0x48000001)
1624 { /* bl foo, an initializer function? */
1625 op
= read_memory_integer (pc
+ 4, 4);
1627 if (op
== 0x4def7b82)
1628 { /* cror 0xf, 0xf, 0xf (nop) */
1630 /* Check and see if we are in main. If so, skip over this
1631 initializer function as well. */
1633 tmp
= find_pc_misc_function (pc
);
1635 && strcmp (misc_function_vector
[tmp
].name
, main_name ()) == 0)
1641 fdata
->offset
= -fdata
->offset
;
1642 return last_prologue_pc
;
1646 rs6000_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1648 struct rs6000_framedata frame
;
1649 CORE_ADDR limit_pc
, func_addr
;
1651 /* See if we can determine the end of the prologue via the symbol table.
1652 If so, then return either PC, or the PC after the prologue, whichever
1654 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
1656 CORE_ADDR post_prologue_pc
= skip_prologue_using_sal (func_addr
);
1657 if (post_prologue_pc
!= 0)
1658 return max (pc
, post_prologue_pc
);
1661 /* Can't determine prologue from the symbol table, need to examine
1664 /* Find an upper limit on the function prologue using the debug
1665 information. If the debug information could not be used to provide
1666 that bound, then use an arbitrary large number as the upper bound. */
1667 limit_pc
= skip_prologue_using_sal (pc
);
1669 limit_pc
= pc
+ 100; /* Magic. */
1671 pc
= skip_prologue (gdbarch
, pc
, limit_pc
, &frame
);
1676 /* All the ABI's require 16 byte alignment. */
1678 rs6000_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1680 return (addr
& -16);
1683 /* Return whether handle_inferior_event() should proceed through code
1684 starting at PC in function NAME when stepping.
1686 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
1687 handle memory references that are too distant to fit in instructions
1688 generated by the compiler. For example, if 'foo' in the following
1693 is greater than 32767, the linker might replace the lwz with a branch to
1694 somewhere in @FIX1 that does the load in 2 instructions and then branches
1695 back to where execution should continue.
1697 GDB should silently step over @FIX code, just like AIX dbx does.
1698 Unfortunately, the linker uses the "b" instruction for the
1699 branches, meaning that the link register doesn't get set.
1700 Therefore, GDB's usual step_over_function () mechanism won't work.
1702 Instead, use the gdbarch_skip_trampoline_code and
1703 gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past
1707 rs6000_in_solib_return_trampoline (CORE_ADDR pc
, char *name
)
1709 return name
&& !strncmp (name
, "@FIX", 4);
1712 /* Skip code that the user doesn't want to see when stepping:
1714 1. Indirect function calls use a piece of trampoline code to do context
1715 switching, i.e. to set the new TOC table. Skip such code if we are on
1716 its first instruction (as when we have single-stepped to here).
1718 2. Skip shared library trampoline code (which is different from
1719 indirect function call trampolines).
1721 3. Skip bigtoc fixup code.
1723 Result is desired PC to step until, or NULL if we are not in
1724 code that should be skipped. */
1727 rs6000_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
1729 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (frame
));
1730 unsigned int ii
, op
;
1732 CORE_ADDR solib_target_pc
;
1733 struct minimal_symbol
*msymbol
;
1735 static unsigned trampoline_code
[] =
1737 0x800b0000, /* l r0,0x0(r11) */
1738 0x90410014, /* st r2,0x14(r1) */
1739 0x7c0903a6, /* mtctr r0 */
1740 0x804b0004, /* l r2,0x4(r11) */
1741 0x816b0008, /* l r11,0x8(r11) */
1742 0x4e800420, /* bctr */
1743 0x4e800020, /* br */
1747 /* Check for bigtoc fixup code. */
1748 msymbol
= lookup_minimal_symbol_by_pc (pc
);
1750 && rs6000_in_solib_return_trampoline (pc
, SYMBOL_LINKAGE_NAME (msymbol
)))
1752 /* Double-check that the third instruction from PC is relative "b". */
1753 op
= read_memory_integer (pc
+ 8, 4);
1754 if ((op
& 0xfc000003) == 0x48000000)
1756 /* Extract bits 6-29 as a signed 24-bit relative word address and
1757 add it to the containing PC. */
1758 rel
= ((int)(op
<< 6) >> 6);
1759 return pc
+ 8 + rel
;
1763 /* If pc is in a shared library trampoline, return its target. */
1764 solib_target_pc
= find_solib_trampoline_target (frame
, pc
);
1765 if (solib_target_pc
)
1766 return solib_target_pc
;
1768 for (ii
= 0; trampoline_code
[ii
]; ++ii
)
1770 op
= read_memory_integer (pc
+ (ii
* 4), 4);
1771 if (op
!= trampoline_code
[ii
])
1774 ii
= get_frame_register_unsigned (frame
, 11); /* r11 holds destination addr */
1775 pc
= read_memory_unsigned_integer (ii
, tdep
->wordsize
); /* (r11) value */
1779 /* ISA-specific vector types. */
1781 static struct type
*
1782 rs6000_builtin_type_vec64 (struct gdbarch
*gdbarch
)
1784 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1786 if (!tdep
->ppc_builtin_type_vec64
)
1788 /* The type we're building is this: */
1790 union __gdb_builtin_type_vec64
1794 int32_t v2_int32
[2];
1795 int16_t v4_int16
[4];
1802 t
= init_composite_type ("__ppc_builtin_type_vec64", TYPE_CODE_UNION
);
1803 append_composite_type_field (t
, "uint64", builtin_type_int64
);
1804 append_composite_type_field (t
, "v2_float",
1805 init_vector_type (builtin_type_float
, 2));
1806 append_composite_type_field (t
, "v2_int32",
1807 init_vector_type (builtin_type_int32
, 2));
1808 append_composite_type_field (t
, "v4_int16",
1809 init_vector_type (builtin_type_int16
, 4));
1810 append_composite_type_field (t
, "v8_int8",
1811 init_vector_type (builtin_type_int8
, 8));
1813 TYPE_FLAGS (t
) |= TYPE_FLAG_VECTOR
;
1814 TYPE_NAME (t
) = "ppc_builtin_type_vec64";
1815 tdep
->ppc_builtin_type_vec64
= t
;
1818 return tdep
->ppc_builtin_type_vec64
;
1821 /* Return the name of register number REGNO, or the empty string if it
1822 is an anonymous register. */
1825 rs6000_register_name (struct gdbarch
*gdbarch
, int regno
)
1827 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1829 /* The upper half "registers" have names in the XML description,
1830 but we present only the low GPRs and the full 64-bit registers
1832 if (tdep
->ppc_ev0_upper_regnum
>= 0
1833 && tdep
->ppc_ev0_upper_regnum
<= regno
1834 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
1837 /* Check if the SPE pseudo registers are available. */
1838 if (IS_SPE_PSEUDOREG (tdep
, regno
))
1840 static const char *const spe_regnames
[] = {
1841 "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7",
1842 "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15",
1843 "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23",
1844 "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31",
1846 return spe_regnames
[regno
- tdep
->ppc_ev0_regnum
];
1849 /* Check if the decimal128 pseudo-registers are available. */
1850 if (IS_DFP_PSEUDOREG (tdep
, regno
))
1852 static const char *const dfp128_regnames
[] = {
1853 "dl0", "dl1", "dl2", "dl3",
1854 "dl4", "dl5", "dl6", "dl7",
1855 "dl8", "dl9", "dl10", "dl11",
1856 "dl12", "dl13", "dl14", "dl15"
1858 return dfp128_regnames
[regno
- tdep
->ppc_dl0_regnum
];
1861 return tdesc_register_name (gdbarch
, regno
);
1864 /* Return the GDB type object for the "standard" data type of data in
1867 static struct type
*
1868 rs6000_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
1870 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1872 /* These are the only pseudo-registers we support. */
1873 gdb_assert (IS_SPE_PSEUDOREG (tdep
, regnum
)
1874 || IS_DFP_PSEUDOREG (tdep
, regnum
));
1876 /* These are the e500 pseudo-registers. */
1877 if (IS_SPE_PSEUDOREG (tdep
, regnum
))
1878 return rs6000_builtin_type_vec64 (gdbarch
);
1880 /* Could only be the ppc decimal128 pseudo-registers. */
1881 return builtin_type (gdbarch
)->builtin_declong
;
1884 /* Is REGNUM a member of REGGROUP? */
1886 rs6000_pseudo_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
1887 struct reggroup
*group
)
1889 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1891 /* These are the only pseudo-registers we support. */
1892 gdb_assert (IS_SPE_PSEUDOREG (tdep
, regnum
)
1893 || IS_DFP_PSEUDOREG (tdep
, regnum
));
1895 /* These are the e500 pseudo-registers. */
1896 if (IS_SPE_PSEUDOREG (tdep
, regnum
))
1897 return group
== all_reggroup
|| group
== vector_reggroup
;
1899 /* Could only be the ppc decimal128 pseudo-registers. */
1900 return group
== all_reggroup
|| group
== float_reggroup
;
1903 /* The register format for RS/6000 floating point registers is always
1904 double, we need a conversion if the memory format is float. */
1907 rs6000_convert_register_p (struct gdbarch
*gdbarch
, int regnum
,
1910 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1912 return (tdep
->ppc_fp0_regnum
>= 0
1913 && regnum
>= tdep
->ppc_fp0_regnum
1914 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
1915 && TYPE_CODE (type
) == TYPE_CODE_FLT
1916 && TYPE_LENGTH (type
) != TYPE_LENGTH (builtin_type_double
));
1920 rs6000_register_to_value (struct frame_info
*frame
,
1925 gdb_byte from
[MAX_REGISTER_SIZE
];
1927 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
1929 get_frame_register (frame
, regnum
, from
);
1930 convert_typed_floating (from
, builtin_type_double
, to
, type
);
1934 rs6000_value_to_register (struct frame_info
*frame
,
1937 const gdb_byte
*from
)
1939 gdb_byte to
[MAX_REGISTER_SIZE
];
1941 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
1943 convert_typed_floating (from
, type
, to
, builtin_type_double
);
1944 put_frame_register (frame
, regnum
, to
);
1947 /* Move SPE vector register values between a 64-bit buffer and the two
1948 32-bit raw register halves in a regcache. This function handles
1949 both splitting a 64-bit value into two 32-bit halves, and joining
1950 two halves into a whole 64-bit value, depending on the function
1951 passed as the MOVE argument.
1953 EV_REG must be the number of an SPE evN vector register --- a
1954 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
1957 Call MOVE once for each 32-bit half of that register, passing
1958 REGCACHE, the number of the raw register corresponding to that
1959 half, and the address of the appropriate half of BUFFER.
1961 For example, passing 'regcache_raw_read' as the MOVE function will
1962 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
1963 'regcache_raw_supply' will supply the contents of BUFFER to the
1964 appropriate pair of raw registers in REGCACHE.
1966 You may need to cast away some 'const' qualifiers when passing
1967 MOVE, since this function can't tell at compile-time which of
1968 REGCACHE or BUFFER is acting as the source of the data. If C had
1969 co-variant type qualifiers, ... */
1971 e500_move_ev_register (void (*move
) (struct regcache
*regcache
,
1972 int regnum
, gdb_byte
*buf
),
1973 struct regcache
*regcache
, int ev_reg
,
1976 struct gdbarch
*arch
= get_regcache_arch (regcache
);
1977 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
1979 gdb_byte
*byte_buffer
= buffer
;
1981 gdb_assert (IS_SPE_PSEUDOREG (tdep
, ev_reg
));
1983 reg_index
= ev_reg
- tdep
->ppc_ev0_regnum
;
1985 if (gdbarch_byte_order (arch
) == BFD_ENDIAN_BIG
)
1987 move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
, byte_buffer
);
1988 move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
, byte_buffer
+ 4);
1992 move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
, byte_buffer
);
1993 move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
, byte_buffer
+ 4);
1998 e500_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1999 int reg_nr
, gdb_byte
*buffer
)
2001 e500_move_ev_register (regcache_raw_read
, regcache
, reg_nr
, buffer
);
2005 e500_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2006 int reg_nr
, const gdb_byte
*buffer
)
2008 e500_move_ev_register ((void (*) (struct regcache
*, int, gdb_byte
*))
2010 regcache
, reg_nr
, (gdb_byte
*) buffer
);
2013 /* Read method for PPC pseudo-registers. Currently this is handling the
2014 16 decimal128 registers that map into 16 pairs of FP registers. */
2016 ppc_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2017 int reg_nr
, gdb_byte
*buffer
)
2019 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2020 int reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2022 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2024 /* Read two FP registers to form a whole dl register. */
2025 regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2026 2 * reg_index
, buffer
);
2027 regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2028 2 * reg_index
+ 1, buffer
+ 8);
2032 regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2033 2 * reg_index
+ 1, buffer
+ 8);
2034 regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2035 2 * reg_index
, buffer
);
2039 /* Write method for PPC pseudo-registers. Currently this is handling the
2040 16 decimal128 registers that map into 16 pairs of FP registers. */
2042 ppc_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2043 int reg_nr
, const gdb_byte
*buffer
)
2045 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2046 int reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2048 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2050 /* Write each half of the dl register into a separate
2052 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2053 2 * reg_index
, buffer
);
2054 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2055 2 * reg_index
+ 1, buffer
+ 8);
2059 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2060 2 * reg_index
+ 1, buffer
+ 8);
2061 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2062 2 * reg_index
, buffer
);
2067 rs6000_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2068 int reg_nr
, gdb_byte
*buffer
)
2070 struct gdbarch
*regcache_arch
= get_regcache_arch (regcache
);
2071 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2073 gdb_assert (regcache_arch
== gdbarch
);
2075 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2076 e500_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2077 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2078 ppc_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2080 internal_error (__FILE__
, __LINE__
,
2081 _("rs6000_pseudo_register_read: "
2082 "called on unexpected register '%s' (%d)"),
2083 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2087 rs6000_pseudo_register_write (struct gdbarch
*gdbarch
,
2088 struct regcache
*regcache
,
2089 int reg_nr
, const gdb_byte
*buffer
)
2091 struct gdbarch
*regcache_arch
= get_regcache_arch (regcache
);
2092 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2094 gdb_assert (regcache_arch
== gdbarch
);
2096 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2097 e500_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2098 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2099 ppc_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2101 internal_error (__FILE__
, __LINE__
,
2102 _("rs6000_pseudo_register_write: "
2103 "called on unexpected register '%s' (%d)"),
2104 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2107 /* Convert a DBX STABS register number to a GDB register number. */
2109 rs6000_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
2111 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2113 if (0 <= num
&& num
<= 31)
2114 return tdep
->ppc_gp0_regnum
+ num
;
2115 else if (32 <= num
&& num
<= 63)
2116 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2117 specifies registers the architecture doesn't have? Our
2118 callers don't check the value we return. */
2119 return tdep
->ppc_fp0_regnum
+ (num
- 32);
2120 else if (77 <= num
&& num
<= 108)
2121 return tdep
->ppc_vr0_regnum
+ (num
- 77);
2122 else if (1200 <= num
&& num
< 1200 + 32)
2123 return tdep
->ppc_ev0_regnum
+ (num
- 1200);
2128 return tdep
->ppc_mq_regnum
;
2130 return tdep
->ppc_lr_regnum
;
2132 return tdep
->ppc_ctr_regnum
;
2134 return tdep
->ppc_xer_regnum
;
2136 return tdep
->ppc_vrsave_regnum
;
2138 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
2140 return tdep
->ppc_acc_regnum
;
2142 return tdep
->ppc_spefscr_regnum
;
2149 /* Convert a Dwarf 2 register number to a GDB register number. */
2151 rs6000_dwarf2_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
2153 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2155 if (0 <= num
&& num
<= 31)
2156 return tdep
->ppc_gp0_regnum
+ num
;
2157 else if (32 <= num
&& num
<= 63)
2158 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2159 specifies registers the architecture doesn't have? Our
2160 callers don't check the value we return. */
2161 return tdep
->ppc_fp0_regnum
+ (num
- 32);
2162 else if (1124 <= num
&& num
< 1124 + 32)
2163 return tdep
->ppc_vr0_regnum
+ (num
- 1124);
2164 else if (1200 <= num
&& num
< 1200 + 32)
2165 return tdep
->ppc_ev0_regnum
+ (num
- 1200);
2170 return tdep
->ppc_cr_regnum
;
2172 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
2174 return tdep
->ppc_acc_regnum
;
2176 return tdep
->ppc_mq_regnum
;
2178 return tdep
->ppc_xer_regnum
;
2180 return tdep
->ppc_lr_regnum
;
2182 return tdep
->ppc_ctr_regnum
;
2184 return tdep
->ppc_vrsave_regnum
;
2186 return tdep
->ppc_spefscr_regnum
;
2192 /* Translate a .eh_frame register to DWARF register, or adjust a
2193 .debug_frame register. */
2196 rs6000_adjust_frame_regnum (struct gdbarch
*gdbarch
, int num
, int eh_frame_p
)
2198 /* GCC releases before 3.4 use GCC internal register numbering in
2199 .debug_frame (and .debug_info, et cetera). The numbering is
2200 different from the standard SysV numbering for everything except
2201 for GPRs and FPRs. We can not detect this problem in most cases
2202 - to get accurate debug info for variables living in lr, ctr, v0,
2203 et cetera, use a newer version of GCC. But we must detect
2204 one important case - lr is in column 65 in .debug_frame output,
2207 GCC 3.4, and the "hammer" branch, have a related problem. They
2208 record lr register saves in .debug_frame as 108, but still record
2209 the return column as 65. We fix that up too.
2211 We can do this because 65 is assigned to fpsr, and GCC never
2212 generates debug info referring to it. To add support for
2213 handwritten debug info that restores fpsr, we would need to add a
2214 producer version check to this. */
2223 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
2224 internal register numbering; translate that to the standard DWARF2
2225 register numbering. */
2226 if (0 <= num
&& num
<= 63) /* r0-r31,fp0-fp31 */
2228 else if (68 <= num
&& num
<= 75) /* cr0-cr8 */
2229 return num
- 68 + 86;
2230 else if (77 <= num
&& num
<= 108) /* vr0-vr31 */
2231 return num
- 77 + 1124;
2243 case 109: /* vrsave */
2245 case 110: /* vscr */
2247 case 111: /* spe_acc */
2249 case 112: /* spefscr */
2257 /* Handling the various POWER/PowerPC variants. */
2259 /* Information about a particular processor variant. */
2263 /* Name of this variant. */
2266 /* English description of the variant. */
2269 /* bfd_arch_info.arch corresponding to variant. */
2270 enum bfd_architecture arch
;
2272 /* bfd_arch_info.mach corresponding to variant. */
2275 /* Target description for this variant. */
2276 struct target_desc
**tdesc
;
2279 static struct variant variants
[] =
2281 {"powerpc", "PowerPC user-level", bfd_arch_powerpc
,
2282 bfd_mach_ppc
, &tdesc_powerpc_altivec32
},
2283 {"power", "POWER user-level", bfd_arch_rs6000
,
2284 bfd_mach_rs6k
, &tdesc_rs6000
},
2285 {"403", "IBM PowerPC 403", bfd_arch_powerpc
,
2286 bfd_mach_ppc_403
, &tdesc_powerpc_403
},
2287 {"601", "Motorola PowerPC 601", bfd_arch_powerpc
,
2288 bfd_mach_ppc_601
, &tdesc_powerpc_601
},
2289 {"602", "Motorola PowerPC 602", bfd_arch_powerpc
,
2290 bfd_mach_ppc_602
, &tdesc_powerpc_602
},
2291 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc
,
2292 bfd_mach_ppc_603
, &tdesc_powerpc_603
},
2293 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc
,
2294 604, &tdesc_powerpc_604
},
2295 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc
,
2296 bfd_mach_ppc_403gc
, &tdesc_powerpc_403gc
},
2297 {"505", "Motorola PowerPC 505", bfd_arch_powerpc
,
2298 bfd_mach_ppc_505
, &tdesc_powerpc_505
},
2299 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc
,
2300 bfd_mach_ppc_860
, &tdesc_powerpc_860
},
2301 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc
,
2302 bfd_mach_ppc_750
, &tdesc_powerpc_750
},
2303 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc
,
2304 bfd_mach_ppc_7400
, &tdesc_powerpc_7400
},
2305 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc
,
2306 bfd_mach_ppc_e500
, &tdesc_powerpc_e500
},
2309 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc
,
2310 bfd_mach_ppc64
, &tdesc_powerpc_altivec64
},
2311 {"620", "Motorola PowerPC 620", bfd_arch_powerpc
,
2312 bfd_mach_ppc_620
, &tdesc_powerpc_64
},
2313 {"630", "Motorola PowerPC 630", bfd_arch_powerpc
,
2314 bfd_mach_ppc_630
, &tdesc_powerpc_64
},
2315 {"a35", "PowerPC A35", bfd_arch_powerpc
,
2316 bfd_mach_ppc_a35
, &tdesc_powerpc_64
},
2317 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc
,
2318 bfd_mach_ppc_rs64ii
, &tdesc_powerpc_64
},
2319 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc
,
2320 bfd_mach_ppc_rs64iii
, &tdesc_powerpc_64
},
2322 /* FIXME: I haven't checked the register sets of the following. */
2323 {"rs1", "IBM POWER RS1", bfd_arch_rs6000
,
2324 bfd_mach_rs6k_rs1
, &tdesc_rs6000
},
2325 {"rsc", "IBM POWER RSC", bfd_arch_rs6000
,
2326 bfd_mach_rs6k_rsc
, &tdesc_rs6000
},
2327 {"rs2", "IBM POWER RS2", bfd_arch_rs6000
,
2328 bfd_mach_rs6k_rs2
, &tdesc_rs6000
},
2333 /* Return the variant corresponding to architecture ARCH and machine number
2334 MACH. If no such variant exists, return null. */
2336 static const struct variant
*
2337 find_variant_by_arch (enum bfd_architecture arch
, unsigned long mach
)
2339 const struct variant
*v
;
2341 for (v
= variants
; v
->name
; v
++)
2342 if (arch
== v
->arch
&& mach
== v
->mach
)
2349 gdb_print_insn_powerpc (bfd_vma memaddr
, disassemble_info
*info
)
2351 if (!info
->disassembler_options
)
2352 info
->disassembler_options
= "any";
2354 if (info
->endian
== BFD_ENDIAN_BIG
)
2355 return print_insn_big_powerpc (memaddr
, info
);
2357 return print_insn_little_powerpc (memaddr
, info
);
2361 rs6000_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2363 return frame_unwind_register_unsigned (next_frame
,
2364 gdbarch_pc_regnum (gdbarch
));
2367 static struct frame_id
2368 rs6000_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2370 return frame_id_build (get_frame_register_unsigned
2371 (this_frame
, gdbarch_sp_regnum (gdbarch
)),
2372 get_frame_pc (this_frame
));
2375 struct rs6000_frame_cache
2378 CORE_ADDR initial_sp
;
2379 struct trad_frame_saved_reg
*saved_regs
;
2382 static struct rs6000_frame_cache
*
2383 rs6000_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2385 struct rs6000_frame_cache
*cache
;
2386 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2387 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2388 struct rs6000_framedata fdata
;
2389 int wordsize
= tdep
->wordsize
;
2392 if ((*this_cache
) != NULL
)
2393 return (*this_cache
);
2394 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
2395 (*this_cache
) = cache
;
2396 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2398 func
= get_frame_func (this_frame
);
2399 pc
= get_frame_pc (this_frame
);
2400 skip_prologue (gdbarch
, func
, pc
, &fdata
);
2402 /* Figure out the parent's stack pointer. */
2404 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
2405 address of the current frame. Things might be easier if the
2406 ->frame pointed to the outer-most address of the frame. In
2407 the mean time, the address of the prev frame is used as the
2408 base address of this frame. */
2409 cache
->base
= get_frame_register_unsigned
2410 (this_frame
, gdbarch_sp_regnum (gdbarch
));
2412 /* If the function appears to be frameless, check a couple of likely
2413 indicators that we have simply failed to find the frame setup.
2414 Two common cases of this are missing symbols (i.e.
2415 frame_func_unwind returns the wrong address or 0), and assembly
2416 stubs which have a fast exit path but set up a frame on the slow
2419 If the LR appears to return to this function, then presume that
2420 we have an ABI compliant frame that we failed to find. */
2421 if (fdata
.frameless
&& fdata
.lr_offset
== 0)
2426 saved_lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
2427 if (func
== 0 && saved_lr
== pc
)
2431 CORE_ADDR saved_func
= get_pc_function_start (saved_lr
);
2432 if (func
== saved_func
)
2438 fdata
.frameless
= 0;
2439 fdata
.lr_offset
= tdep
->lr_frame_offset
;
2443 if (!fdata
.frameless
)
2444 /* Frameless really means stackless. */
2445 cache
->base
= read_memory_unsigned_integer (cache
->base
, wordsize
);
2447 trad_frame_set_value (cache
->saved_regs
,
2448 gdbarch_sp_regnum (gdbarch
), cache
->base
);
2450 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
2451 All fpr's from saved_fpr to fp31 are saved. */
2453 if (fdata
.saved_fpr
>= 0)
2456 CORE_ADDR fpr_addr
= cache
->base
+ fdata
.fpr_offset
;
2458 /* If skip_prologue says floating-point registers were saved,
2459 but the current architecture has no floating-point registers,
2460 then that's strange. But we have no indices to even record
2461 the addresses under, so we just ignore it. */
2462 if (ppc_floating_point_unit_p (gdbarch
))
2463 for (i
= fdata
.saved_fpr
; i
< ppc_num_fprs
; i
++)
2465 cache
->saved_regs
[tdep
->ppc_fp0_regnum
+ i
].addr
= fpr_addr
;
2470 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
2471 All gpr's from saved_gpr to gpr31 are saved. */
2473 if (fdata
.saved_gpr
>= 0)
2476 CORE_ADDR gpr_addr
= cache
->base
+ fdata
.gpr_offset
;
2477 for (i
= fdata
.saved_gpr
; i
< ppc_num_gprs
; i
++)
2479 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= gpr_addr
;
2480 gpr_addr
+= wordsize
;
2484 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
2485 All vr's from saved_vr to vr31 are saved. */
2486 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
2488 if (fdata
.saved_vr
>= 0)
2491 CORE_ADDR vr_addr
= cache
->base
+ fdata
.vr_offset
;
2492 for (i
= fdata
.saved_vr
; i
< 32; i
++)
2494 cache
->saved_regs
[tdep
->ppc_vr0_regnum
+ i
].addr
= vr_addr
;
2495 vr_addr
+= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
2500 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
2501 All vr's from saved_ev to ev31 are saved. ????? */
2502 if (tdep
->ppc_ev0_regnum
!= -1)
2504 if (fdata
.saved_ev
>= 0)
2507 CORE_ADDR ev_addr
= cache
->base
+ fdata
.ev_offset
;
2508 for (i
= fdata
.saved_ev
; i
< ppc_num_gprs
; i
++)
2510 cache
->saved_regs
[tdep
->ppc_ev0_regnum
+ i
].addr
= ev_addr
;
2511 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= ev_addr
+ 4;
2512 ev_addr
+= register_size (gdbarch
, tdep
->ppc_ev0_regnum
);
2517 /* If != 0, fdata.cr_offset is the offset from the frame that
2519 if (fdata
.cr_offset
!= 0)
2520 cache
->saved_regs
[tdep
->ppc_cr_regnum
].addr
= cache
->base
+ fdata
.cr_offset
;
2522 /* If != 0, fdata.lr_offset is the offset from the frame that
2524 if (fdata
.lr_offset
!= 0)
2525 cache
->saved_regs
[tdep
->ppc_lr_regnum
].addr
= cache
->base
+ fdata
.lr_offset
;
2526 /* The PC is found in the link register. */
2527 cache
->saved_regs
[gdbarch_pc_regnum (gdbarch
)] =
2528 cache
->saved_regs
[tdep
->ppc_lr_regnum
];
2530 /* If != 0, fdata.vrsave_offset is the offset from the frame that
2531 holds the VRSAVE. */
2532 if (fdata
.vrsave_offset
!= 0)
2533 cache
->saved_regs
[tdep
->ppc_vrsave_regnum
].addr
= cache
->base
+ fdata
.vrsave_offset
;
2535 if (fdata
.alloca_reg
< 0)
2536 /* If no alloca register used, then fi->frame is the value of the
2537 %sp for this frame, and it is good enough. */
2539 = get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
2542 = get_frame_register_unsigned (this_frame
, fdata
.alloca_reg
);
2548 rs6000_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2549 struct frame_id
*this_id
)
2551 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
2553 /* This marks the outermost frame. */
2554 if (info
->base
== 0)
2557 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2560 static struct value
*
2561 rs6000_frame_prev_register (struct frame_info
*this_frame
,
2562 void **this_cache
, int regnum
)
2564 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
2566 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2569 static const struct frame_unwind rs6000_frame_unwind
=
2572 rs6000_frame_this_id
,
2573 rs6000_frame_prev_register
,
2575 default_frame_sniffer
2580 rs6000_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2582 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
2584 return info
->initial_sp
;
2587 static const struct frame_base rs6000_frame_base
= {
2588 &rs6000_frame_unwind
,
2589 rs6000_frame_base_address
,
2590 rs6000_frame_base_address
,
2591 rs6000_frame_base_address
2594 static const struct frame_base
*
2595 rs6000_frame_base_sniffer (struct frame_info
*this_frame
)
2597 return &rs6000_frame_base
;
2600 /* DWARF-2 frame support. Used to handle the detection of
2601 clobbered registers during function calls. */
2604 ppc_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
2605 struct dwarf2_frame_state_reg
*reg
,
2606 struct frame_info
*this_frame
)
2608 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2610 /* PPC32 and PPC64 ABI's are the same regarding volatile and
2611 non-volatile registers. We will use the same code for both. */
2613 /* Call-saved GP registers. */
2614 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 14
2615 && regnum
<= tdep
->ppc_gp0_regnum
+ 31)
2616 || (regnum
== tdep
->ppc_gp0_regnum
+ 1))
2617 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
2619 /* Call-clobbered GP registers. */
2620 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 3
2621 && regnum
<= tdep
->ppc_gp0_regnum
+ 12)
2622 || (regnum
== tdep
->ppc_gp0_regnum
))
2623 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
2625 /* Deal with FP registers, if supported. */
2626 if (tdep
->ppc_fp0_regnum
>= 0)
2628 /* Call-saved FP registers. */
2629 if ((regnum
>= tdep
->ppc_fp0_regnum
+ 14
2630 && regnum
<= tdep
->ppc_fp0_regnum
+ 31))
2631 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
2633 /* Call-clobbered FP registers. */
2634 if ((regnum
>= tdep
->ppc_fp0_regnum
2635 && regnum
<= tdep
->ppc_fp0_regnum
+ 13))
2636 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
2639 /* Deal with ALTIVEC registers, if supported. */
2640 if (tdep
->ppc_vr0_regnum
> 0 && tdep
->ppc_vrsave_regnum
> 0)
2642 /* Call-saved Altivec registers. */
2643 if ((regnum
>= tdep
->ppc_vr0_regnum
+ 20
2644 && regnum
<= tdep
->ppc_vr0_regnum
+ 31)
2645 || regnum
== tdep
->ppc_vrsave_regnum
)
2646 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
2648 /* Call-clobbered Altivec registers. */
2649 if ((regnum
>= tdep
->ppc_vr0_regnum
2650 && regnum
<= tdep
->ppc_vr0_regnum
+ 19))
2651 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
2654 /* Handle PC register and Stack Pointer correctly. */
2655 if (regnum
== gdbarch_pc_regnum (gdbarch
))
2656 reg
->how
= DWARF2_FRAME_REG_RA
;
2657 else if (regnum
== gdbarch_sp_regnum (gdbarch
))
2658 reg
->how
= DWARF2_FRAME_REG_CFA
;
2662 /* Initialize the current architecture based on INFO. If possible, re-use an
2663 architecture from ARCHES, which is a list of architectures already created
2664 during this debugging session.
2666 Called e.g. at program startup, when reading a core file, and when reading
2669 static struct gdbarch
*
2670 rs6000_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2672 struct gdbarch
*gdbarch
;
2673 struct gdbarch_tdep
*tdep
;
2674 int wordsize
, from_xcoff_exec
, from_elf_exec
;
2675 enum bfd_architecture arch
;
2679 enum auto_boolean soft_float_flag
= powerpc_soft_float_global
;
2681 enum powerpc_vector_abi vector_abi
= powerpc_vector_abi_global
;
2682 int have_fpu
= 1, have_spe
= 0, have_mq
= 0, have_altivec
= 0, have_dfp
= 0;
2683 int tdesc_wordsize
= -1;
2684 const struct target_desc
*tdesc
= info
.target_desc
;
2685 struct tdesc_arch_data
*tdesc_data
= NULL
;
2686 int num_pseudoregs
= 0;
2688 from_xcoff_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
2689 bfd_get_flavour (info
.abfd
) == bfd_target_xcoff_flavour
;
2691 from_elf_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
2692 bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
;
2694 /* Check word size. If INFO is from a binary file, infer it from
2695 that, else choose a likely default. */
2696 if (from_xcoff_exec
)
2698 if (bfd_xcoff_is_xcoff64 (info
.abfd
))
2703 else if (from_elf_exec
)
2705 if (elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
2710 else if (tdesc_has_registers (tdesc
))
2714 if (info
.bfd_arch_info
!= NULL
&& info
.bfd_arch_info
->bits_per_word
!= 0)
2715 wordsize
= info
.bfd_arch_info
->bits_per_word
/
2716 info
.bfd_arch_info
->bits_per_byte
;
2721 /* Get the architecture and machine from the BFD. */
2722 arch
= info
.bfd_arch_info
->arch
;
2723 mach
= info
.bfd_arch_info
->mach
;
2725 /* For e500 executables, the apuinfo section is of help here. Such
2726 section contains the identifier and revision number of each
2727 Application-specific Processing Unit that is present on the
2728 chip. The content of the section is determined by the assembler
2729 which looks at each instruction and determines which unit (and
2730 which version of it) can execute it. In our case we just look for
2731 the existance of the section. */
2735 sect
= bfd_get_section_by_name (info
.abfd
, ".PPC.EMB.apuinfo");
2738 arch
= info
.bfd_arch_info
->arch
;
2739 mach
= bfd_mach_ppc_e500
;
2740 bfd_default_set_arch_mach (&abfd
, arch
, mach
);
2741 info
.bfd_arch_info
= bfd_get_arch_info (&abfd
);
2745 /* Find a default target description which describes our register
2746 layout, if we do not already have one. */
2747 if (! tdesc_has_registers (tdesc
))
2749 const struct variant
*v
;
2751 /* Choose variant. */
2752 v
= find_variant_by_arch (arch
, mach
);
2759 gdb_assert (tdesc_has_registers (tdesc
));
2761 /* Check any target description for validity. */
2762 if (tdesc_has_registers (tdesc
))
2764 static const char *const gprs
[] = {
2765 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2766 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
2767 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
2768 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
2770 static const char *const segment_regs
[] = {
2771 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
2772 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
2774 const struct tdesc_feature
*feature
;
2776 static const char *const msr_names
[] = { "msr", "ps" };
2777 static const char *const cr_names
[] = { "cr", "cnd" };
2778 static const char *const ctr_names
[] = { "ctr", "cnt" };
2780 feature
= tdesc_find_feature (tdesc
,
2781 "org.gnu.gdb.power.core");
2782 if (feature
== NULL
)
2785 tdesc_data
= tdesc_data_alloc ();
2788 for (i
= 0; i
< ppc_num_gprs
; i
++)
2789 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
, gprs
[i
]);
2790 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_PC_REGNUM
,
2792 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_LR_REGNUM
,
2794 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_XER_REGNUM
,
2797 /* Allow alternate names for these registers, to accomodate GDB's
2799 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
2800 PPC_MSR_REGNUM
, msr_names
);
2801 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
2802 PPC_CR_REGNUM
, cr_names
);
2803 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
2804 PPC_CTR_REGNUM
, ctr_names
);
2808 tdesc_data_cleanup (tdesc_data
);
2812 have_mq
= tdesc_numbered_register (feature
, tdesc_data
, PPC_MQ_REGNUM
,
2815 tdesc_wordsize
= tdesc_register_size (feature
, "pc") / 8;
2817 wordsize
= tdesc_wordsize
;
2819 feature
= tdesc_find_feature (tdesc
,
2820 "org.gnu.gdb.power.fpu");
2821 if (feature
!= NULL
)
2823 static const char *const fprs
[] = {
2824 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
2825 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
2826 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
2827 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
2830 for (i
= 0; i
< ppc_num_fprs
; i
++)
2831 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
2832 PPC_F0_REGNUM
+ i
, fprs
[i
]);
2833 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
2834 PPC_FPSCR_REGNUM
, "fpscr");
2838 tdesc_data_cleanup (tdesc_data
);
2846 /* The DFP pseudo-registers will be available when there are floating
2848 have_dfp
= have_fpu
;
2850 feature
= tdesc_find_feature (tdesc
,
2851 "org.gnu.gdb.power.altivec");
2852 if (feature
!= NULL
)
2854 static const char *const vector_regs
[] = {
2855 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
2856 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
2857 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
2858 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31"
2862 for (i
= 0; i
< ppc_num_gprs
; i
++)
2863 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
2866 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
2867 PPC_VSCR_REGNUM
, "vscr");
2868 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
2869 PPC_VRSAVE_REGNUM
, "vrsave");
2871 if (have_spe
|| !valid_p
)
2873 tdesc_data_cleanup (tdesc_data
);
2881 /* On machines supporting the SPE APU, the general-purpose registers
2882 are 64 bits long. There are SIMD vector instructions to treat them
2883 as pairs of floats, but the rest of the instruction set treats them
2884 as 32-bit registers, and only operates on their lower halves.
2886 In the GDB regcache, we treat their high and low halves as separate
2887 registers. The low halves we present as the general-purpose
2888 registers, and then we have pseudo-registers that stitch together
2889 the upper and lower halves and present them as pseudo-registers.
2891 Thus, the target description is expected to supply the upper
2892 halves separately. */
2894 feature
= tdesc_find_feature (tdesc
,
2895 "org.gnu.gdb.power.spe");
2896 if (feature
!= NULL
)
2898 static const char *const upper_spe
[] = {
2899 "ev0h", "ev1h", "ev2h", "ev3h",
2900 "ev4h", "ev5h", "ev6h", "ev7h",
2901 "ev8h", "ev9h", "ev10h", "ev11h",
2902 "ev12h", "ev13h", "ev14h", "ev15h",
2903 "ev16h", "ev17h", "ev18h", "ev19h",
2904 "ev20h", "ev21h", "ev22h", "ev23h",
2905 "ev24h", "ev25h", "ev26h", "ev27h",
2906 "ev28h", "ev29h", "ev30h", "ev31h"
2910 for (i
= 0; i
< ppc_num_gprs
; i
++)
2911 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
2912 PPC_SPE_UPPER_GP0_REGNUM
+ i
,
2914 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
2915 PPC_SPE_ACC_REGNUM
, "acc");
2916 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
2917 PPC_SPE_FSCR_REGNUM
, "spefscr");
2919 if (have_mq
|| have_fpu
|| !valid_p
)
2921 tdesc_data_cleanup (tdesc_data
);
2930 /* If we have a 64-bit binary on a 32-bit target, complain. Also
2931 complain for a 32-bit binary on a 64-bit target; we do not yet
2932 support that. For instance, the 32-bit ABI routines expect
2935 As long as there isn't an explicit target description, we'll
2936 choose one based on the BFD architecture and get a word size
2937 matching the binary (probably powerpc:common or
2938 powerpc:common64). So there is only trouble if a 64-bit target
2939 supplies a 64-bit description while debugging a 32-bit
2941 if (tdesc_wordsize
!= -1 && tdesc_wordsize
!= wordsize
)
2943 tdesc_data_cleanup (tdesc_data
);
2948 if (soft_float_flag
== AUTO_BOOLEAN_AUTO
&& from_elf_exec
)
2950 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
2951 Tag_GNU_Power_ABI_FP
))
2954 soft_float_flag
= AUTO_BOOLEAN_FALSE
;
2957 soft_float_flag
= AUTO_BOOLEAN_TRUE
;
2964 if (vector_abi
== POWERPC_VEC_AUTO
&& from_elf_exec
)
2966 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
2967 Tag_GNU_Power_ABI_Vector
))
2970 vector_abi
= POWERPC_VEC_GENERIC
;
2973 vector_abi
= POWERPC_VEC_ALTIVEC
;
2976 vector_abi
= POWERPC_VEC_SPE
;
2984 if (soft_float_flag
== AUTO_BOOLEAN_TRUE
)
2986 else if (soft_float_flag
== AUTO_BOOLEAN_FALSE
)
2989 soft_float
= !have_fpu
;
2991 /* If we have a hard float binary or setting but no floating point
2992 registers, downgrade to soft float anyway. We're still somewhat
2993 useful in this scenario. */
2994 if (!soft_float
&& !have_fpu
)
2997 /* Similarly for vector registers. */
2998 if (vector_abi
== POWERPC_VEC_ALTIVEC
&& !have_altivec
)
2999 vector_abi
= POWERPC_VEC_GENERIC
;
3001 if (vector_abi
== POWERPC_VEC_SPE
&& !have_spe
)
3002 vector_abi
= POWERPC_VEC_GENERIC
;
3004 if (vector_abi
== POWERPC_VEC_AUTO
)
3007 vector_abi
= POWERPC_VEC_ALTIVEC
;
3009 vector_abi
= POWERPC_VEC_SPE
;
3011 vector_abi
= POWERPC_VEC_GENERIC
;
3014 /* Do not limit the vector ABI based on available hardware, since we
3015 do not yet know what hardware we'll decide we have. Yuck! FIXME! */
3017 /* Find a candidate among extant architectures. */
3018 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
3020 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
3022 /* Word size in the various PowerPC bfd_arch_info structs isn't
3023 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
3024 separate word size check. */
3025 tdep
= gdbarch_tdep (arches
->gdbarch
);
3026 if (tdep
&& tdep
->soft_float
!= soft_float
)
3028 if (tdep
&& tdep
->vector_abi
!= vector_abi
)
3030 if (tdep
&& tdep
->wordsize
== wordsize
)
3032 if (tdesc_data
!= NULL
)
3033 tdesc_data_cleanup (tdesc_data
);
3034 return arches
->gdbarch
;
3038 /* None found, create a new architecture from INFO, whose bfd_arch_info
3039 validity depends on the source:
3040 - executable useless
3041 - rs6000_host_arch() good
3043 - "set arch" trust blindly
3044 - GDB startup useless but harmless */
3046 tdep
= XCALLOC (1, struct gdbarch_tdep
);
3047 tdep
->wordsize
= wordsize
;
3048 tdep
->soft_float
= soft_float
;
3049 tdep
->vector_abi
= vector_abi
;
3051 gdbarch
= gdbarch_alloc (&info
, tdep
);
3053 tdep
->ppc_gp0_regnum
= PPC_R0_REGNUM
;
3054 tdep
->ppc_toc_regnum
= PPC_R0_REGNUM
+ 2;
3055 tdep
->ppc_ps_regnum
= PPC_MSR_REGNUM
;
3056 tdep
->ppc_cr_regnum
= PPC_CR_REGNUM
;
3057 tdep
->ppc_lr_regnum
= PPC_LR_REGNUM
;
3058 tdep
->ppc_ctr_regnum
= PPC_CTR_REGNUM
;
3059 tdep
->ppc_xer_regnum
= PPC_XER_REGNUM
;
3060 tdep
->ppc_mq_regnum
= have_mq
? PPC_MQ_REGNUM
: -1;
3062 tdep
->ppc_fp0_regnum
= have_fpu
? PPC_F0_REGNUM
: -1;
3063 tdep
->ppc_fpscr_regnum
= have_fpu
? PPC_FPSCR_REGNUM
: -1;
3064 tdep
->ppc_vr0_regnum
= have_altivec
? PPC_VR0_REGNUM
: -1;
3065 tdep
->ppc_vrsave_regnum
= have_altivec
? PPC_VRSAVE_REGNUM
: -1;
3066 tdep
->ppc_ev0_upper_regnum
= have_spe
? PPC_SPE_UPPER_GP0_REGNUM
: -1;
3067 tdep
->ppc_acc_regnum
= have_spe
? PPC_SPE_ACC_REGNUM
: -1;
3068 tdep
->ppc_spefscr_regnum
= have_spe
? PPC_SPE_FSCR_REGNUM
: -1;
3070 set_gdbarch_pc_regnum (gdbarch
, PPC_PC_REGNUM
);
3071 set_gdbarch_sp_regnum (gdbarch
, PPC_R0_REGNUM
+ 1);
3072 set_gdbarch_deprecated_fp_regnum (gdbarch
, PPC_R0_REGNUM
+ 1);
3073 set_gdbarch_fp0_regnum (gdbarch
, tdep
->ppc_fp0_regnum
);
3074 set_gdbarch_register_sim_regno (gdbarch
, rs6000_register_sim_regno
);
3076 /* The XML specification for PowerPC sensibly calls the MSR "msr".
3077 GDB traditionally called it "ps", though, so let GDB add an
3079 set_gdbarch_ps_regnum (gdbarch
, tdep
->ppc_ps_regnum
);
3082 set_gdbarch_return_value (gdbarch
, ppc64_sysv_abi_return_value
);
3084 set_gdbarch_return_value (gdbarch
, ppc_sysv_abi_return_value
);
3086 /* Set lr_frame_offset. */
3088 tdep
->lr_frame_offset
= 16;
3090 tdep
->lr_frame_offset
= 4;
3092 if (have_spe
|| have_dfp
)
3094 set_gdbarch_pseudo_register_read (gdbarch
, rs6000_pseudo_register_read
);
3095 set_gdbarch_pseudo_register_write (gdbarch
, rs6000_pseudo_register_write
);
3098 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
3100 /* Select instruction printer. */
3101 if (arch
== bfd_arch_rs6000
)
3102 set_gdbarch_print_insn (gdbarch
, print_insn_rs6000
);
3104 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_powerpc
);
3106 set_gdbarch_num_regs (gdbarch
, PPC_NUM_REGS
);
3109 num_pseudoregs
+= 32;
3111 num_pseudoregs
+= 16;
3113 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudoregs
);
3115 set_gdbarch_ptr_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
3116 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
3117 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
3118 set_gdbarch_long_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
3119 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
3120 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
3121 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
3122 set_gdbarch_long_double_bit (gdbarch
, 16 * TARGET_CHAR_BIT
);
3123 set_gdbarch_char_signed (gdbarch
, 0);
3125 set_gdbarch_frame_align (gdbarch
, rs6000_frame_align
);
3128 set_gdbarch_frame_red_zone_size (gdbarch
, 288);
3130 set_gdbarch_convert_register_p (gdbarch
, rs6000_convert_register_p
);
3131 set_gdbarch_register_to_value (gdbarch
, rs6000_register_to_value
);
3132 set_gdbarch_value_to_register (gdbarch
, rs6000_value_to_register
);
3134 set_gdbarch_stab_reg_to_regnum (gdbarch
, rs6000_stab_reg_to_regnum
);
3135 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, rs6000_dwarf2_reg_to_regnum
);
3138 set_gdbarch_push_dummy_call (gdbarch
, ppc_sysv_abi_push_dummy_call
);
3139 else if (wordsize
== 8)
3140 set_gdbarch_push_dummy_call (gdbarch
, ppc64_sysv_abi_push_dummy_call
);
3142 set_gdbarch_skip_prologue (gdbarch
, rs6000_skip_prologue
);
3143 set_gdbarch_in_function_epilogue_p (gdbarch
, rs6000_in_function_epilogue_p
);
3145 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3146 set_gdbarch_breakpoint_from_pc (gdbarch
, rs6000_breakpoint_from_pc
);
3148 /* The value of symbols of type N_SO and N_FUN maybe null when
3150 set_gdbarch_sofun_address_maybe_missing (gdbarch
, 1);
3152 /* Handles single stepping of atomic sequences. */
3153 set_gdbarch_software_single_step (gdbarch
, ppc_deal_with_atomic_sequence
);
3155 /* Not sure on this. FIXMEmgo */
3156 set_gdbarch_frame_args_skip (gdbarch
, 8);
3158 /* Helpers for function argument information. */
3159 set_gdbarch_fetch_pointer_argument (gdbarch
, rs6000_fetch_pointer_argument
);
3162 set_gdbarch_in_solib_return_trampoline
3163 (gdbarch
, rs6000_in_solib_return_trampoline
);
3164 set_gdbarch_skip_trampoline_code (gdbarch
, rs6000_skip_trampoline_code
);
3166 /* Hook in the DWARF CFI frame unwinder. */
3167 dwarf2_append_unwinders (gdbarch
);
3168 dwarf2_frame_set_adjust_regnum (gdbarch
, rs6000_adjust_frame_regnum
);
3170 /* Frame handling. */
3171 dwarf2_frame_set_init_reg (gdbarch
, ppc_dwarf2_frame_init_reg
);
3173 /* Hook in ABI-specific overrides, if they have been registered. */
3174 info
.target_desc
= tdesc
;
3175 info
.tdep_info
= (void *) tdesc_data
;
3176 gdbarch_init_osabi (info
, gdbarch
);
3180 case GDB_OSABI_LINUX
:
3181 case GDB_OSABI_NETBSD_AOUT
:
3182 case GDB_OSABI_NETBSD_ELF
:
3183 case GDB_OSABI_UNKNOWN
:
3184 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
3185 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
3186 set_gdbarch_dummy_id (gdbarch
, rs6000_dummy_id
);
3187 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
3190 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
3192 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
3193 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
3194 set_gdbarch_dummy_id (gdbarch
, rs6000_dummy_id
);
3195 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
3198 set_tdesc_pseudo_register_type (gdbarch
, rs6000_pseudo_register_type
);
3199 set_tdesc_pseudo_register_reggroup_p (gdbarch
,
3200 rs6000_pseudo_register_reggroup_p
);
3201 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
3203 /* Override the normal target description method to make the SPE upper
3204 halves anonymous. */
3205 set_gdbarch_register_name (gdbarch
, rs6000_register_name
);
3207 /* Recording the numbering of pseudo registers. */
3208 tdep
->ppc_ev0_regnum
= have_spe
? gdbarch_num_regs (gdbarch
) : -1;
3210 /* Set the register number for _Decimal128 pseudo-registers. */
3211 tdep
->ppc_dl0_regnum
= have_dfp
? gdbarch_num_regs (gdbarch
) : -1;
3213 if (have_dfp
&& have_spe
)
3214 /* Put the _Decimal128 pseudo-registers after the SPE registers. */
3215 tdep
->ppc_dl0_regnum
+= 32;
3221 rs6000_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
3223 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3228 /* FIXME: Dump gdbarch_tdep. */
3231 /* PowerPC-specific commands. */
3234 set_powerpc_command (char *args
, int from_tty
)
3236 printf_unfiltered (_("\
3237 \"set powerpc\" must be followed by an appropriate subcommand.\n"));
3238 help_list (setpowerpccmdlist
, "set powerpc ", all_commands
, gdb_stdout
);
3242 show_powerpc_command (char *args
, int from_tty
)
3244 cmd_show_list (showpowerpccmdlist
, from_tty
, "");
3248 powerpc_set_soft_float (char *args
, int from_tty
,
3249 struct cmd_list_element
*c
)
3251 struct gdbarch_info info
;
3253 /* Update the architecture. */
3254 gdbarch_info_init (&info
);
3255 if (!gdbarch_update_p (info
))
3256 internal_error (__FILE__
, __LINE__
, "could not update architecture");
3260 powerpc_set_vector_abi (char *args
, int from_tty
,
3261 struct cmd_list_element
*c
)
3263 struct gdbarch_info info
;
3264 enum powerpc_vector_abi vector_abi
;
3266 for (vector_abi
= POWERPC_VEC_AUTO
;
3267 vector_abi
!= POWERPC_VEC_LAST
;
3269 if (strcmp (powerpc_vector_abi_string
,
3270 powerpc_vector_strings
[vector_abi
]) == 0)
3272 powerpc_vector_abi_global
= vector_abi
;
3276 if (vector_abi
== POWERPC_VEC_LAST
)
3277 internal_error (__FILE__
, __LINE__
, _("Invalid vector ABI accepted: %s."),
3278 powerpc_vector_abi_string
);
3280 /* Update the architecture. */
3281 gdbarch_info_init (&info
);
3282 if (!gdbarch_update_p (info
))
3283 internal_error (__FILE__
, __LINE__
, "could not update architecture");
3286 /* Initialization code. */
3288 extern initialize_file_ftype _initialize_rs6000_tdep
; /* -Wmissing-prototypes */
3291 _initialize_rs6000_tdep (void)
3293 gdbarch_register (bfd_arch_rs6000
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
3294 gdbarch_register (bfd_arch_powerpc
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
3296 /* Initialize the standard target descriptions. */
3297 initialize_tdesc_powerpc_32 ();
3298 initialize_tdesc_powerpc_altivec32 ();
3299 initialize_tdesc_powerpc_403 ();
3300 initialize_tdesc_powerpc_403gc ();
3301 initialize_tdesc_powerpc_505 ();
3302 initialize_tdesc_powerpc_601 ();
3303 initialize_tdesc_powerpc_602 ();
3304 initialize_tdesc_powerpc_603 ();
3305 initialize_tdesc_powerpc_604 ();
3306 initialize_tdesc_powerpc_64 ();
3307 initialize_tdesc_powerpc_altivec64 ();
3308 initialize_tdesc_powerpc_7400 ();
3309 initialize_tdesc_powerpc_750 ();
3310 initialize_tdesc_powerpc_860 ();
3311 initialize_tdesc_powerpc_e500 ();
3312 initialize_tdesc_rs6000 ();
3314 /* Add root prefix command for all "set powerpc"/"show powerpc"
3316 add_prefix_cmd ("powerpc", no_class
, set_powerpc_command
,
3317 _("Various PowerPC-specific commands."),
3318 &setpowerpccmdlist
, "set powerpc ", 0, &setlist
);
3320 add_prefix_cmd ("powerpc", no_class
, show_powerpc_command
,
3321 _("Various PowerPC-specific commands."),
3322 &showpowerpccmdlist
, "show powerpc ", 0, &showlist
);
3324 /* Add a command to allow the user to force the ABI. */
3325 add_setshow_auto_boolean_cmd ("soft-float", class_support
,
3326 &powerpc_soft_float_global
,
3327 _("Set whether to use a soft-float ABI."),
3328 _("Show whether to use a soft-float ABI."),
3330 powerpc_set_soft_float
, NULL
,
3331 &setpowerpccmdlist
, &showpowerpccmdlist
);
3333 add_setshow_enum_cmd ("vector-abi", class_support
, powerpc_vector_strings
,
3334 &powerpc_vector_abi_string
,
3335 _("Set the vector ABI."),
3336 _("Show the vector ABI."),
3337 NULL
, powerpc_set_vector_abi
, NULL
,
3338 &setpowerpccmdlist
, &showpowerpccmdlist
);