1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
32 #include "arch-utils.h"
37 #include "parser-defs.h"
40 #include "libbfd.h" /* for bfd_default_set_arch_mach */
41 #include "coff/internal.h" /* for libcoff.h */
42 #include "libcoff.h" /* for xcoff_data */
43 #include "coff/xcoff.h"
48 #include "solib-svr4.h"
51 #include "gdb_assert.h"
54 #include "trad-frame.h"
55 #include "frame-unwind.h"
56 #include "frame-base.h"
58 /* If the kernel has to deliver a signal, it pushes a sigcontext
59 structure on the stack and then calls the signal handler, passing
60 the address of the sigcontext in an argument register. Usually
61 the signal handler doesn't save this register, so we have to
62 access the sigcontext structure via an offset from the signal handler
64 The following constants were determined by experimentation on AIX 3.2. */
65 #define SIG_FRAME_PC_OFFSET 96
66 #define SIG_FRAME_LR_OFFSET 108
67 #define SIG_FRAME_FP_OFFSET 284
69 /* To be used by skip_prologue. */
71 struct rs6000_framedata
73 int offset
; /* total size of frame --- the distance
74 by which we decrement sp to allocate
76 int saved_gpr
; /* smallest # of saved gpr */
77 int saved_fpr
; /* smallest # of saved fpr */
78 int saved_vr
; /* smallest # of saved vr */
79 int saved_ev
; /* smallest # of saved ev */
80 int alloca_reg
; /* alloca register number (frame ptr) */
81 char frameless
; /* true if frameless functions. */
82 char nosavedpc
; /* true if pc not saved. */
83 int gpr_offset
; /* offset of saved gprs from prev sp */
84 int fpr_offset
; /* offset of saved fprs from prev sp */
85 int vr_offset
; /* offset of saved vrs from prev sp */
86 int ev_offset
; /* offset of saved evs from prev sp */
87 int lr_offset
; /* offset of saved lr */
88 int cr_offset
; /* offset of saved cr */
89 int vrsave_offset
; /* offset of saved vrsave register */
92 /* Description of a single register. */
96 char *name
; /* name of register */
97 unsigned char sz32
; /* size on 32-bit arch, 0 if nonextant */
98 unsigned char sz64
; /* size on 64-bit arch, 0 if nonextant */
99 unsigned char fpr
; /* whether register is floating-point */
100 unsigned char pseudo
; /* whether register is pseudo */
103 /* Breakpoint shadows for the single step instructions will be kept here. */
105 static struct sstep_breaks
107 /* Address, or 0 if this is not in use. */
109 /* Shadow contents. */
114 /* Hook for determining the TOC address when calling functions in the
115 inferior under AIX. The initialization code in rs6000-nat.c sets
116 this hook to point to find_toc_address. */
118 CORE_ADDR (*rs6000_find_toc_address_hook
) (CORE_ADDR
) = NULL
;
120 /* Hook to set the current architecture when starting a child process.
121 rs6000-nat.c sets this. */
123 void (*rs6000_set_host_arch_hook
) (int) = NULL
;
125 /* Static function prototypes */
127 static CORE_ADDR
branch_dest (int opcode
, int instr
, CORE_ADDR pc
,
129 static CORE_ADDR
skip_prologue (CORE_ADDR
, CORE_ADDR
,
130 struct rs6000_framedata
*);
132 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
134 altivec_register_p (int regno
)
136 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
137 if (tdep
->ppc_vr0_regnum
< 0 || tdep
->ppc_vrsave_regnum
< 0)
140 return (regno
>= tdep
->ppc_vr0_regnum
&& regno
<= tdep
->ppc_vrsave_regnum
);
144 /* Return true if REGNO is an SPE register, false otherwise. */
146 spe_register_p (int regno
)
148 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
150 /* Is it a reference to EV0 -- EV31, and do we have those? */
151 if (tdep
->ppc_ev0_regnum
>= 0
152 && tdep
->ppc_ev31_regnum
>= 0
153 && tdep
->ppc_ev0_regnum
<= regno
&& regno
<= tdep
->ppc_ev31_regnum
)
156 /* Is it a reference to the 64-bit accumulator, and do we have that? */
157 if (tdep
->ppc_acc_regnum
>= 0
158 && tdep
->ppc_acc_regnum
== regno
)
161 /* Is it a reference to the SPE floating-point status and control register,
162 and do we have that? */
163 if (tdep
->ppc_spefscr_regnum
>= 0
164 && tdep
->ppc_spefscr_regnum
== regno
)
171 /* Return non-zero if the architecture described by GDBARCH has
172 floating-point registers (f0 --- f31 and fpscr). */
174 ppc_floating_point_unit_p (struct gdbarch
*gdbarch
)
176 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
178 return (tdep
->ppc_fp0_regnum
>= 0
179 && tdep
->ppc_fpscr_regnum
>= 0);
183 /* Register set support functions. */
186 ppc_supply_reg (struct regcache
*regcache
, int regnum
,
187 const char *regs
, size_t offset
)
189 if (regnum
!= -1 && offset
!= -1)
190 regcache_raw_supply (regcache
, regnum
, regs
+ offset
);
194 ppc_collect_reg (const struct regcache
*regcache
, int regnum
,
195 char *regs
, size_t offset
)
197 if (regnum
!= -1 && offset
!= -1)
198 regcache_raw_collect (regcache
, regnum
, regs
+ offset
);
201 /* Supply register REGNUM in the general-purpose register set REGSET
202 from the buffer specified by GREGS and LEN to register cache
203 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
206 ppc_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
207 int regnum
, const void *gregs
, size_t len
)
209 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
210 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
211 const struct ppc_reg_offsets
*offsets
= regset
->descr
;
215 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
216 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
219 if (regnum
== -1 || regnum
== i
)
220 ppc_supply_reg (regcache
, i
, gregs
, offset
);
223 if (regnum
== -1 || regnum
== PC_REGNUM
)
224 ppc_supply_reg (regcache
, PC_REGNUM
, gregs
, offsets
->pc_offset
);
225 if (regnum
== -1 || regnum
== tdep
->ppc_ps_regnum
)
226 ppc_supply_reg (regcache
, tdep
->ppc_ps_regnum
,
227 gregs
, offsets
->ps_offset
);
228 if (regnum
== -1 || regnum
== tdep
->ppc_cr_regnum
)
229 ppc_supply_reg (regcache
, tdep
->ppc_cr_regnum
,
230 gregs
, offsets
->cr_offset
);
231 if (regnum
== -1 || regnum
== tdep
->ppc_lr_regnum
)
232 ppc_supply_reg (regcache
, tdep
->ppc_lr_regnum
,
233 gregs
, offsets
->lr_offset
);
234 if (regnum
== -1 || regnum
== tdep
->ppc_ctr_regnum
)
235 ppc_supply_reg (regcache
, tdep
->ppc_ctr_regnum
,
236 gregs
, offsets
->ctr_offset
);
237 if (regnum
== -1 || regnum
== tdep
->ppc_xer_regnum
)
238 ppc_supply_reg (regcache
, tdep
->ppc_xer_regnum
,
239 gregs
, offsets
->cr_offset
);
240 if (regnum
== -1 || regnum
== tdep
->ppc_mq_regnum
)
241 ppc_supply_reg (regcache
, tdep
->ppc_mq_regnum
, gregs
, offsets
->mq_offset
);
244 /* Supply register REGNUM in the floating-point register set REGSET
245 from the buffer specified by FPREGS and LEN to register cache
246 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
249 ppc_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
250 int regnum
, const void *fpregs
, size_t len
)
252 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
253 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
254 const struct ppc_reg_offsets
*offsets
= regset
->descr
;
258 gdb_assert (ppc_floating_point_unit_p (gdbarch
));
260 offset
= offsets
->f0_offset
;
261 for (i
= tdep
->ppc_fp0_regnum
;
262 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
265 if (regnum
== -1 || regnum
== i
)
266 ppc_supply_reg (regcache
, i
, fpregs
, offset
);
269 if (regnum
== -1 || regnum
== tdep
->ppc_fpscr_regnum
)
270 ppc_supply_reg (regcache
, tdep
->ppc_fpscr_regnum
,
271 fpregs
, offsets
->fpscr_offset
);
274 /* Collect register REGNUM in the general-purpose register set
275 REGSET. from register cache REGCACHE into the buffer specified by
276 GREGS and LEN. If REGNUM is -1, do this for all registers in
280 ppc_collect_gregset (const struct regset
*regset
,
281 const struct regcache
*regcache
,
282 int regnum
, void *gregs
, size_t len
)
284 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
285 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
286 const struct ppc_reg_offsets
*offsets
= regset
->descr
;
290 offset
= offsets
->r0_offset
;
291 for (i
= tdep
->ppc_gp0_regnum
;
292 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
295 if (regnum
== -1 || regnum
== i
)
296 ppc_collect_reg (regcache
, i
, gregs
, offset
);
299 if (regnum
== -1 || regnum
== PC_REGNUM
)
300 ppc_collect_reg (regcache
, PC_REGNUM
, gregs
, offsets
->pc_offset
);
301 if (regnum
== -1 || regnum
== tdep
->ppc_ps_regnum
)
302 ppc_collect_reg (regcache
, tdep
->ppc_ps_regnum
,
303 gregs
, offsets
->ps_offset
);
304 if (regnum
== -1 || regnum
== tdep
->ppc_cr_regnum
)
305 ppc_collect_reg (regcache
, tdep
->ppc_cr_regnum
,
306 gregs
, offsets
->cr_offset
);
307 if (regnum
== -1 || regnum
== tdep
->ppc_lr_regnum
)
308 ppc_collect_reg (regcache
, tdep
->ppc_lr_regnum
,
309 gregs
, offsets
->lr_offset
);
310 if (regnum
== -1 || regnum
== tdep
->ppc_ctr_regnum
)
311 ppc_collect_reg (regcache
, tdep
->ppc_ctr_regnum
,
312 gregs
, offsets
->ctr_offset
);
313 if (regnum
== -1 || regnum
== tdep
->ppc_xer_regnum
)
314 ppc_collect_reg (regcache
, tdep
->ppc_xer_regnum
,
315 gregs
, offsets
->xer_offset
);
316 if (regnum
== -1 || regnum
== tdep
->ppc_mq_regnum
)
317 ppc_collect_reg (regcache
, tdep
->ppc_mq_regnum
,
318 gregs
, offsets
->mq_offset
);
321 /* Collect register REGNUM in the floating-point register set
322 REGSET. from register cache REGCACHE into the buffer specified by
323 FPREGS and LEN. If REGNUM is -1, do this for all registers in
327 ppc_collect_fpregset (const struct regset
*regset
,
328 const struct regcache
*regcache
,
329 int regnum
, void *fpregs
, size_t len
)
331 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
332 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
333 const struct ppc_reg_offsets
*offsets
= regset
->descr
;
337 gdb_assert (ppc_floating_point_unit_p (gdbarch
));
339 offset
= offsets
->f0_offset
;
340 for (i
= tdep
->ppc_fp0_regnum
;
341 i
<= tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
344 if (regnum
== -1 || regnum
== i
)
345 ppc_collect_reg (regcache
, regnum
, fpregs
, offset
);
348 if (regnum
== -1 || regnum
== tdep
->ppc_fpscr_regnum
)
349 ppc_collect_reg (regcache
, tdep
->ppc_fpscr_regnum
,
350 fpregs
, offsets
->fpscr_offset
);
354 /* Read a LEN-byte address from debugged memory address MEMADDR. */
357 read_memory_addr (CORE_ADDR memaddr
, int len
)
359 return read_memory_unsigned_integer (memaddr
, len
);
363 rs6000_skip_prologue (CORE_ADDR pc
)
365 struct rs6000_framedata frame
;
366 pc
= skip_prologue (pc
, 0, &frame
);
371 /* Fill in fi->saved_regs */
373 struct frame_extra_info
375 /* Functions calling alloca() change the value of the stack
376 pointer. We need to use initial stack pointer (which is saved in
377 r31 by gcc) in such cases. If a compiler emits traceback table,
378 then we should use the alloca register specified in traceback
380 CORE_ADDR initial_sp
; /* initial stack pointer. */
383 /* Get the ith function argument for the current function. */
385 rs6000_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
389 get_frame_register (frame
, 3 + argi
, &addr
);
393 /* Calculate the destination of a branch/jump. Return -1 if not a branch. */
396 branch_dest (int opcode
, int instr
, CORE_ADDR pc
, CORE_ADDR safety
)
403 absolute
= (int) ((instr
>> 1) & 1);
408 immediate
= ((instr
& ~3) << 6) >> 6; /* br unconditional */
412 dest
= pc
+ immediate
;
416 immediate
= ((instr
& ~3) << 16) >> 16; /* br conditional */
420 dest
= pc
+ immediate
;
424 ext_op
= (instr
>> 1) & 0x3ff;
426 if (ext_op
== 16) /* br conditional register */
428 dest
= read_register (gdbarch_tdep (current_gdbarch
)->ppc_lr_regnum
) & ~3;
430 /* If we are about to return from a signal handler, dest is
431 something like 0x3c90. The current frame is a signal handler
432 caller frame, upon completion of the sigreturn system call
433 execution will return to the saved PC in the frame. */
434 if (dest
< TEXT_SEGMENT_BASE
)
436 struct frame_info
*fi
;
438 fi
= get_current_frame ();
440 dest
= read_memory_addr (get_frame_base (fi
) + SIG_FRAME_PC_OFFSET
,
441 gdbarch_tdep (current_gdbarch
)->wordsize
);
445 else if (ext_op
== 528) /* br cond to count reg */
447 dest
= read_register (gdbarch_tdep (current_gdbarch
)->ppc_ctr_regnum
) & ~3;
449 /* If we are about to execute a system call, dest is something
450 like 0x22fc or 0x3b00. Upon completion the system call
451 will return to the address in the link register. */
452 if (dest
< TEXT_SEGMENT_BASE
)
453 dest
= read_register (gdbarch_tdep (current_gdbarch
)->ppc_lr_regnum
) & ~3;
462 return (dest
< TEXT_SEGMENT_BASE
) ? safety
: dest
;
466 /* Sequence of bytes for breakpoint instruction. */
468 const static unsigned char *
469 rs6000_breakpoint_from_pc (CORE_ADDR
*bp_addr
, int *bp_size
)
471 static unsigned char big_breakpoint
[] = { 0x7d, 0x82, 0x10, 0x08 };
472 static unsigned char little_breakpoint
[] = { 0x08, 0x10, 0x82, 0x7d };
474 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
475 return big_breakpoint
;
477 return little_breakpoint
;
481 /* AIX does not support PT_STEP. Simulate it. */
484 rs6000_software_single_step (enum target_signal signal
,
485 int insert_breakpoints_p
)
489 const char *breakp
= rs6000_breakpoint_from_pc (&dummy
, &breakp_sz
);
495 if (insert_breakpoints_p
)
500 insn
= read_memory_integer (loc
, 4);
502 breaks
[0] = loc
+ breakp_sz
;
504 breaks
[1] = branch_dest (opcode
, insn
, loc
, breaks
[0]);
506 /* Don't put two breakpoints on the same address. */
507 if (breaks
[1] == breaks
[0])
510 stepBreaks
[1].address
= 0;
512 for (ii
= 0; ii
< 2; ++ii
)
515 /* ignore invalid breakpoint. */
516 if (breaks
[ii
] == -1)
518 target_insert_breakpoint (breaks
[ii
], stepBreaks
[ii
].data
);
519 stepBreaks
[ii
].address
= breaks
[ii
];
526 /* remove step breakpoints. */
527 for (ii
= 0; ii
< 2; ++ii
)
528 if (stepBreaks
[ii
].address
!= 0)
529 target_remove_breakpoint (stepBreaks
[ii
].address
,
530 stepBreaks
[ii
].data
);
532 errno
= 0; /* FIXME, don't ignore errors! */
533 /* What errors? {read,write}_memory call error(). */
537 /* return pc value after skipping a function prologue and also return
538 information about a function frame.
540 in struct rs6000_framedata fdata:
541 - frameless is TRUE, if function does not have a frame.
542 - nosavedpc is TRUE, if function does not save %pc value in its frame.
543 - offset is the initial size of this stack frame --- the amount by
544 which we decrement the sp to allocate the frame.
545 - saved_gpr is the number of the first saved gpr.
546 - saved_fpr is the number of the first saved fpr.
547 - saved_vr is the number of the first saved vr.
548 - saved_ev is the number of the first saved ev.
549 - alloca_reg is the number of the register used for alloca() handling.
551 - gpr_offset is the offset of the first saved gpr from the previous frame.
552 - fpr_offset is the offset of the first saved fpr from the previous frame.
553 - vr_offset is the offset of the first saved vr from the previous frame.
554 - ev_offset is the offset of the first saved ev from the previous frame.
555 - lr_offset is the offset of the saved lr
556 - cr_offset is the offset of the saved cr
557 - vrsave_offset is the offset of the saved vrsave register
560 #define SIGNED_SHORT(x) \
561 ((sizeof (short) == 2) \
562 ? ((int)(short)(x)) \
563 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
565 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
567 /* Limit the number of skipped non-prologue instructions, as the examining
568 of the prologue is expensive. */
569 static int max_skip_non_prologue_insns
= 10;
571 /* Given PC representing the starting address of a function, and
572 LIM_PC which is the (sloppy) limit to which to scan when looking
573 for a prologue, attempt to further refine this limit by using
574 the line data in the symbol table. If successful, a better guess
575 on where the prologue ends is returned, otherwise the previous
576 value of lim_pc is returned. */
578 /* FIXME: cagney/2004-02-14: This function and logic have largely been
579 superseded by skip_prologue_using_sal. */
582 refine_prologue_limit (CORE_ADDR pc
, CORE_ADDR lim_pc
)
584 struct symtab_and_line prologue_sal
;
586 prologue_sal
= find_pc_line (pc
, 0);
587 if (prologue_sal
.line
!= 0)
590 CORE_ADDR addr
= prologue_sal
.end
;
592 /* Handle the case in which compiler's optimizer/scheduler
593 has moved instructions into the prologue. We scan ahead
594 in the function looking for address ranges whose corresponding
595 line number is less than or equal to the first one that we
596 found for the function. (It can be less than when the
597 scheduler puts a body instruction before the first prologue
599 for (i
= 2 * max_skip_non_prologue_insns
;
600 i
> 0 && (lim_pc
== 0 || addr
< lim_pc
);
603 struct symtab_and_line sal
;
605 sal
= find_pc_line (addr
, 0);
608 if (sal
.line
<= prologue_sal
.line
609 && sal
.symtab
== prologue_sal
.symtab
)
616 if (lim_pc
== 0 || prologue_sal
.end
< lim_pc
)
617 lim_pc
= prologue_sal
.end
;
622 /* Return nonzero if the given instruction OP can be part of the prologue
623 of a function and saves a parameter on the stack. FRAMEP should be
624 set if one of the previous instructions in the function has set the
628 store_param_on_stack_p (unsigned long op
, int framep
, int *r0_contains_arg
)
630 /* Move parameters from argument registers to temporary register. */
631 if ((op
& 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
633 /* Rx must be scratch register r0. */
634 const int rx_regno
= (op
>> 16) & 31;
635 /* Ry: Only r3 - r10 are used for parameter passing. */
636 const int ry_regno
= GET_SRC_REG (op
);
638 if (rx_regno
== 0 && ry_regno
>= 3 && ry_regno
<= 10)
640 *r0_contains_arg
= 1;
647 /* Save a General Purpose Register on stack. */
649 if ((op
& 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
650 (op
& 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
652 /* Rx: Only r3 - r10 are used for parameter passing. */
653 const int rx_regno
= GET_SRC_REG (op
);
655 return (rx_regno
>= 3 && rx_regno
<= 10);
658 /* Save a General Purpose Register on stack via the Frame Pointer. */
661 ((op
& 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
662 (op
& 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
663 (op
& 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
665 /* Rx: Usually, only r3 - r10 are used for parameter passing.
666 However, the compiler sometimes uses r0 to hold an argument. */
667 const int rx_regno
= GET_SRC_REG (op
);
669 return ((rx_regno
>= 3 && rx_regno
<= 10)
670 || (rx_regno
== 0 && *r0_contains_arg
));
673 if ((op
& 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
675 /* Only f2 - f8 are used for parameter passing. */
676 const int src_regno
= GET_SRC_REG (op
);
678 return (src_regno
>= 2 && src_regno
<= 8);
681 if (framep
&& ((op
& 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
683 /* Only f2 - f8 are used for parameter passing. */
684 const int src_regno
= GET_SRC_REG (op
);
686 return (src_regno
>= 2 && src_regno
<= 8);
689 /* Not an insn that saves a parameter on stack. */
694 skip_prologue (CORE_ADDR pc
, CORE_ADDR lim_pc
, struct rs6000_framedata
*fdata
)
696 CORE_ADDR orig_pc
= pc
;
697 CORE_ADDR last_prologue_pc
= pc
;
698 CORE_ADDR li_found_pc
= 0;
702 long vr_saved_offset
= 0;
711 int minimal_toc_loaded
= 0;
712 int prev_insn_was_prologue_insn
= 1;
713 int num_skip_non_prologue_insns
= 0;
714 int r0_contains_arg
= 0;
715 const struct bfd_arch_info
*arch_info
= gdbarch_bfd_arch_info (current_gdbarch
);
716 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
718 /* Attempt to find the end of the prologue when no limit is specified.
719 Note that refine_prologue_limit() has been written so that it may
720 be used to "refine" the limits of non-zero PC values too, but this
721 is only safe if we 1) trust the line information provided by the
722 compiler and 2) iterate enough to actually find the end of the
725 It may become a good idea at some point (for both performance and
726 accuracy) to unconditionally call refine_prologue_limit(). But,
727 until we can make a clear determination that this is beneficial,
728 we'll play it safe and only use it to obtain a limit when none
729 has been specified. */
731 lim_pc
= refine_prologue_limit (pc
, lim_pc
);
733 memset (fdata
, 0, sizeof (struct rs6000_framedata
));
734 fdata
->saved_gpr
= -1;
735 fdata
->saved_fpr
= -1;
736 fdata
->saved_vr
= -1;
737 fdata
->saved_ev
= -1;
738 fdata
->alloca_reg
= -1;
739 fdata
->frameless
= 1;
740 fdata
->nosavedpc
= 1;
744 /* Sometimes it isn't clear if an instruction is a prologue
745 instruction or not. When we encounter one of these ambiguous
746 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
747 Otherwise, we'll assume that it really is a prologue instruction. */
748 if (prev_insn_was_prologue_insn
)
749 last_prologue_pc
= pc
;
751 /* Stop scanning if we've hit the limit. */
752 if (lim_pc
!= 0 && pc
>= lim_pc
)
755 prev_insn_was_prologue_insn
= 1;
757 /* Fetch the instruction and convert it to an integer. */
758 if (target_read_memory (pc
, buf
, 4))
760 op
= extract_signed_integer (buf
, 4);
762 if ((op
& 0xfc1fffff) == 0x7c0802a6)
764 /* Since shared library / PIC code, which needs to get its
765 address at runtime, can appear to save more than one link
779 remember just the first one, but skip over additional
782 lr_reg
= (op
& 0x03e00000);
787 else if ((op
& 0xfc1fffff) == 0x7c000026)
789 cr_reg
= (op
& 0x03e00000);
795 else if ((op
& 0xfc1f0000) == 0xd8010000)
796 { /* stfd Rx,NUM(r1) */
797 reg
= GET_SRC_REG (op
);
798 if (fdata
->saved_fpr
== -1 || fdata
->saved_fpr
> reg
)
800 fdata
->saved_fpr
= reg
;
801 fdata
->fpr_offset
= SIGNED_SHORT (op
) + offset
;
806 else if (((op
& 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
807 (((op
& 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
808 (op
& 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
809 (op
& 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
812 reg
= GET_SRC_REG (op
);
813 if (fdata
->saved_gpr
== -1 || fdata
->saved_gpr
> reg
)
815 fdata
->saved_gpr
= reg
;
816 if ((op
& 0xfc1f0003) == 0xf8010000)
818 fdata
->gpr_offset
= SIGNED_SHORT (op
) + offset
;
823 else if ((op
& 0xffff0000) == 0x60000000)
826 /* Allow nops in the prologue, but do not consider them to
827 be part of the prologue unless followed by other prologue
829 prev_insn_was_prologue_insn
= 0;
833 else if ((op
& 0xffff0000) == 0x3c000000)
834 { /* addis 0,0,NUM, used
836 fdata
->offset
= (op
& 0x0000ffff) << 16;
837 fdata
->frameless
= 0;
842 else if ((op
& 0xffff0000) == 0x60000000)
843 { /* ori 0,0,NUM, 2nd ha
844 lf of >= 32k frames */
845 fdata
->offset
|= (op
& 0x0000ffff);
846 fdata
->frameless
= 0;
851 else if (lr_reg
!= -1 &&
852 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
853 (((op
& 0xffff0000) == (lr_reg
| 0xf8010000)) ||
854 /* stw Rx, NUM(r1) */
855 ((op
& 0xffff0000) == (lr_reg
| 0x90010000)) ||
856 /* stwu Rx, NUM(r1) */
857 ((op
& 0xffff0000) == (lr_reg
| 0x94010000))))
858 { /* where Rx == lr */
859 fdata
->lr_offset
= offset
;
860 fdata
->nosavedpc
= 0;
862 if ((op
& 0xfc000003) == 0xf8000000 || /* std */
863 (op
& 0xfc000000) == 0x90000000) /* stw */
865 /* Does not update r1, so add displacement to lr_offset. */
866 fdata
->lr_offset
+= SIGNED_SHORT (op
);
871 else if (cr_reg
!= -1 &&
872 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
873 (((op
& 0xffff0000) == (cr_reg
| 0xf8010000)) ||
874 /* stw Rx, NUM(r1) */
875 ((op
& 0xffff0000) == (cr_reg
| 0x90010000)) ||
876 /* stwu Rx, NUM(r1) */
877 ((op
& 0xffff0000) == (cr_reg
| 0x94010000))))
878 { /* where Rx == cr */
879 fdata
->cr_offset
= offset
;
881 if ((op
& 0xfc000003) == 0xf8000000 ||
882 (op
& 0xfc000000) == 0x90000000)
884 /* Does not update r1, so add displacement to cr_offset. */
885 fdata
->cr_offset
+= SIGNED_SHORT (op
);
890 else if (op
== 0x48000005)
896 else if (op
== 0x48000004)
901 else if ((op
& 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
902 in V.4 -mminimal-toc */
903 (op
& 0xffff0000) == 0x3bde0000)
904 { /* addi 30,30,foo@l */
908 else if ((op
& 0xfc000001) == 0x48000001)
912 fdata
->frameless
= 0;
913 /* Don't skip over the subroutine call if it is not within
914 the first three instructions of the prologue. */
915 if ((pc
- orig_pc
) > 8)
918 op
= read_memory_integer (pc
+ 4, 4);
920 /* At this point, make sure this is not a trampoline
921 function (a function that simply calls another functions,
922 and nothing else). If the next is not a nop, this branch
923 was part of the function prologue. */
925 if (op
== 0x4def7b82 || op
== 0) /* crorc 15, 15, 15 */
926 break; /* don't skip over
931 /* update stack pointer */
932 else if ((op
& 0xfc1f0000) == 0x94010000)
933 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
934 fdata
->frameless
= 0;
935 fdata
->offset
= SIGNED_SHORT (op
);
936 offset
= fdata
->offset
;
939 else if ((op
& 0xfc1f016a) == 0x7c01016e)
940 { /* stwux rX,r1,rY */
941 /* no way to figure out what r1 is going to be */
942 fdata
->frameless
= 0;
943 offset
= fdata
->offset
;
946 else if ((op
& 0xfc1f0003) == 0xf8010001)
947 { /* stdu rX,NUM(r1) */
948 fdata
->frameless
= 0;
949 fdata
->offset
= SIGNED_SHORT (op
& ~3UL);
950 offset
= fdata
->offset
;
953 else if ((op
& 0xfc1f016a) == 0x7c01016a)
954 { /* stdux rX,r1,rY */
955 /* no way to figure out what r1 is going to be */
956 fdata
->frameless
= 0;
957 offset
= fdata
->offset
;
960 /* Load up minimal toc pointer */
961 else if (((op
>> 22) == 0x20f || /* l r31,... or l r30,... */
962 (op
>> 22) == 0x3af) /* ld r31,... or ld r30,... */
963 && !minimal_toc_loaded
)
965 minimal_toc_loaded
= 1;
968 /* move parameters from argument registers to local variable
971 else if ((op
& 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
972 (((op
>> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
973 (((op
>> 21) & 31) <= 10) &&
974 ((long) ((op
>> 16) & 31) >= fdata
->saved_gpr
)) /* Rx: local var reg */
978 /* store parameters in stack */
980 /* Move parameters from argument registers to temporary register. */
981 else if (store_param_on_stack_p (op
, framep
, &r0_contains_arg
))
985 /* Set up frame pointer */
987 else if (op
== 0x603f0000 /* oril r31, r1, 0x0 */
990 fdata
->frameless
= 0;
992 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 31);
995 /* Another way to set up the frame pointer. */
997 else if ((op
& 0xfc1fffff) == 0x38010000)
998 { /* addi rX, r1, 0x0 */
999 fdata
->frameless
= 0;
1001 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
1002 + ((op
& ~0x38010000) >> 21));
1005 /* AltiVec related instructions. */
1006 /* Store the vrsave register (spr 256) in another register for
1007 later manipulation, or load a register into the vrsave
1008 register. 2 instructions are used: mfvrsave and
1009 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1010 and mtspr SPR256, Rn. */
1011 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1012 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1013 else if ((op
& 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1015 vrsave_reg
= GET_SRC_REG (op
);
1018 else if ((op
& 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1022 /* Store the register where vrsave was saved to onto the stack:
1023 rS is the register where vrsave was stored in a previous
1025 /* 100100 sssss 00001 dddddddd dddddddd */
1026 else if ((op
& 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1028 if (vrsave_reg
== GET_SRC_REG (op
))
1030 fdata
->vrsave_offset
= SIGNED_SHORT (op
) + offset
;
1035 /* Compute the new value of vrsave, by modifying the register
1036 where vrsave was saved to. */
1037 else if (((op
& 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1038 || ((op
& 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1042 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1043 in a pair of insns to save the vector registers on the
1045 /* 001110 00000 00000 iiii iiii iiii iiii */
1046 /* 001110 01110 00000 iiii iiii iiii iiii */
1047 else if ((op
& 0xffff0000) == 0x38000000 /* li r0, SIMM */
1048 || (op
& 0xffff0000) == 0x39c00000) /* li r14, SIMM */
1050 if ((op
& 0xffff0000) == 0x38000000)
1051 r0_contains_arg
= 0;
1053 vr_saved_offset
= SIGNED_SHORT (op
);
1055 /* This insn by itself is not part of the prologue, unless
1056 if part of the pair of insns mentioned above. So do not
1057 record this insn as part of the prologue yet. */
1058 prev_insn_was_prologue_insn
= 0;
1060 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1061 /* 011111 sssss 11111 00000 00111001110 */
1062 else if ((op
& 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1064 if (pc
== (li_found_pc
+ 4))
1066 vr_reg
= GET_SRC_REG (op
);
1067 /* If this is the first vector reg to be saved, or if
1068 it has a lower number than others previously seen,
1069 reupdate the frame info. */
1070 if (fdata
->saved_vr
== -1 || fdata
->saved_vr
> vr_reg
)
1072 fdata
->saved_vr
= vr_reg
;
1073 fdata
->vr_offset
= vr_saved_offset
+ offset
;
1075 vr_saved_offset
= -1;
1080 /* End AltiVec related instructions. */
1082 /* Start BookE related instructions. */
1083 /* Store gen register S at (r31+uimm).
1084 Any register less than r13 is volatile, so we don't care. */
1085 /* 000100 sssss 11111 iiiii 01100100001 */
1086 else if (arch_info
->mach
== bfd_mach_ppc_e500
1087 && (op
& 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
1089 if ((op
& 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
1092 ev_reg
= GET_SRC_REG (op
);
1093 imm
= (op
>> 11) & 0x1f;
1094 ev_offset
= imm
* 8;
1095 /* If this is the first vector reg to be saved, or if
1096 it has a lower number than others previously seen,
1097 reupdate the frame info. */
1098 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1100 fdata
->saved_ev
= ev_reg
;
1101 fdata
->ev_offset
= ev_offset
+ offset
;
1106 /* Store gen register rS at (r1+rB). */
1107 /* 000100 sssss 00001 bbbbb 01100100000 */
1108 else if (arch_info
->mach
== bfd_mach_ppc_e500
1109 && (op
& 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1111 if (pc
== (li_found_pc
+ 4))
1113 ev_reg
= GET_SRC_REG (op
);
1114 /* If this is the first vector reg to be saved, or if
1115 it has a lower number than others previously seen,
1116 reupdate the frame info. */
1117 /* We know the contents of rB from the previous instruction. */
1118 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1120 fdata
->saved_ev
= ev_reg
;
1121 fdata
->ev_offset
= vr_saved_offset
+ offset
;
1123 vr_saved_offset
= -1;
1129 /* Store gen register r31 at (rA+uimm). */
1130 /* 000100 11111 aaaaa iiiii 01100100001 */
1131 else if (arch_info
->mach
== bfd_mach_ppc_e500
1132 && (op
& 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
1134 /* Wwe know that the source register is 31 already, but
1135 it can't hurt to compute it. */
1136 ev_reg
= GET_SRC_REG (op
);
1137 ev_offset
= ((op
>> 11) & 0x1f) * 8;
1138 /* If this is the first vector reg to be saved, or if
1139 it has a lower number than others previously seen,
1140 reupdate the frame info. */
1141 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1143 fdata
->saved_ev
= ev_reg
;
1144 fdata
->ev_offset
= ev_offset
+ offset
;
1149 /* Store gen register S at (r31+r0).
1150 Store param on stack when offset from SP bigger than 4 bytes. */
1151 /* 000100 sssss 11111 00000 01100100000 */
1152 else if (arch_info
->mach
== bfd_mach_ppc_e500
1153 && (op
& 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
1155 if (pc
== (li_found_pc
+ 4))
1157 if ((op
& 0x03e00000) >= 0x01a00000)
1159 ev_reg
= GET_SRC_REG (op
);
1160 /* If this is the first vector reg to be saved, or if
1161 it has a lower number than others previously seen,
1162 reupdate the frame info. */
1163 /* We know the contents of r0 from the previous
1165 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1167 fdata
->saved_ev
= ev_reg
;
1168 fdata
->ev_offset
= vr_saved_offset
+ offset
;
1172 vr_saved_offset
= -1;
1177 /* End BookE related instructions. */
1181 /* Not a recognized prologue instruction.
1182 Handle optimizer code motions into the prologue by continuing
1183 the search if we have no valid frame yet or if the return
1184 address is not yet saved in the frame. */
1185 if (fdata
->frameless
== 0
1186 && (lr_reg
== -1 || fdata
->nosavedpc
== 0))
1189 if (op
== 0x4e800020 /* blr */
1190 || op
== 0x4e800420) /* bctr */
1191 /* Do not scan past epilogue in frameless functions or
1194 if ((op
& 0xf4000000) == 0x40000000) /* bxx */
1195 /* Never skip branches. */
1198 if (num_skip_non_prologue_insns
++ > max_skip_non_prologue_insns
)
1199 /* Do not scan too many insns, scanning insns is expensive with
1203 /* Continue scanning. */
1204 prev_insn_was_prologue_insn
= 0;
1210 /* I have problems with skipping over __main() that I need to address
1211 * sometime. Previously, I used to use misc_function_vector which
1212 * didn't work as well as I wanted to be. -MGO */
1214 /* If the first thing after skipping a prolog is a branch to a function,
1215 this might be a call to an initializer in main(), introduced by gcc2.
1216 We'd like to skip over it as well. Fortunately, xlc does some extra
1217 work before calling a function right after a prologue, thus we can
1218 single out such gcc2 behaviour. */
1221 if ((op
& 0xfc000001) == 0x48000001)
1222 { /* bl foo, an initializer function? */
1223 op
= read_memory_integer (pc
+ 4, 4);
1225 if (op
== 0x4def7b82)
1226 { /* cror 0xf, 0xf, 0xf (nop) */
1228 /* Check and see if we are in main. If so, skip over this
1229 initializer function as well. */
1231 tmp
= find_pc_misc_function (pc
);
1233 && strcmp (misc_function_vector
[tmp
].name
, main_name ()) == 0)
1239 fdata
->offset
= -fdata
->offset
;
1240 return last_prologue_pc
;
1244 /*************************************************************************
1245 Support for creating pushing a dummy frame into the stack, and popping
1247 *************************************************************************/
1250 /* All the ABI's require 16 byte alignment. */
1252 rs6000_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1254 return (addr
& -16);
1257 /* Pass the arguments in either registers, or in the stack. In RS/6000,
1258 the first eight words of the argument list (that might be less than
1259 eight parameters if some parameters occupy more than one word) are
1260 passed in r3..r10 registers. float and double parameters are
1261 passed in fpr's, in addition to that. Rest of the parameters if any
1262 are passed in user stack. There might be cases in which half of the
1263 parameter is copied into registers, the other half is pushed into
1266 Stack must be aligned on 64-bit boundaries when synthesizing
1269 If the function is returning a structure, then the return address is passed
1270 in r3, then the first 7 words of the parameters can be passed in registers,
1271 starting from r4. */
1274 rs6000_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
1275 struct regcache
*regcache
, CORE_ADDR bp_addr
,
1276 int nargs
, struct value
**args
, CORE_ADDR sp
,
1277 int struct_return
, CORE_ADDR struct_addr
)
1279 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1282 int argno
; /* current argument number */
1283 int argbytes
; /* current argument byte */
1284 char tmp_buffer
[50];
1285 int f_argno
= 0; /* current floating point argno */
1286 int wordsize
= gdbarch_tdep (current_gdbarch
)->wordsize
;
1288 struct value
*arg
= 0;
1293 /* The calling convention this function implements assumes the
1294 processor has floating-point registers. We shouldn't be using it
1295 on PPC variants that lack them. */
1296 gdb_assert (ppc_floating_point_unit_p (current_gdbarch
));
1298 /* The first eight words of ther arguments are passed in registers.
1299 Copy them appropriately. */
1302 /* If the function is returning a `struct', then the first word
1303 (which will be passed in r3) is used for struct return address.
1304 In that case we should advance one word and start from r4
1305 register to copy parameters. */
1308 regcache_raw_write_unsigned (regcache
, tdep
->ppc_gp0_regnum
+ 3,
1314 effectively indirect call... gcc does...
1316 return_val example( float, int);
1319 float in fp0, int in r3
1320 offset of stack on overflow 8/16
1321 for varargs, must go by type.
1323 float in r3&r4, int in r5
1324 offset of stack on overflow different
1326 return in r3 or f0. If no float, must study how gcc emulates floats;
1327 pay attention to arg promotion.
1328 User may have to cast\args to handle promotion correctly
1329 since gdb won't know if prototype supplied or not.
1332 for (argno
= 0, argbytes
= 0; argno
< nargs
&& ii
< 8; ++ii
)
1334 int reg_size
= DEPRECATED_REGISTER_RAW_SIZE (ii
+ 3);
1337 type
= check_typedef (VALUE_TYPE (arg
));
1338 len
= TYPE_LENGTH (type
);
1340 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1343 /* Floating point arguments are passed in fpr's, as well as gpr's.
1344 There are 13 fpr's reserved for passing parameters. At this point
1345 there is no way we would run out of them. */
1348 printf_unfiltered ("Fatal Error: a floating point parameter "
1349 "#%d with a size > 8 is found!\n", argno
);
1351 memcpy (&deprecated_registers
[DEPRECATED_REGISTER_BYTE
1352 (tdep
->ppc_fp0_regnum
+ 1 + f_argno
)],
1353 VALUE_CONTENTS (arg
),
1361 /* Argument takes more than one register. */
1362 while (argbytes
< len
)
1364 memset (&deprecated_registers
[DEPRECATED_REGISTER_BYTE (ii
+ 3)], 0,
1366 memcpy (&deprecated_registers
[DEPRECATED_REGISTER_BYTE (ii
+ 3)],
1367 ((char *) VALUE_CONTENTS (arg
)) + argbytes
,
1368 (len
- argbytes
) > reg_size
1369 ? reg_size
: len
- argbytes
);
1370 ++ii
, argbytes
+= reg_size
;
1373 goto ran_out_of_registers_for_arguments
;
1380 /* Argument can fit in one register. No problem. */
1381 int adj
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? reg_size
- len
: 0;
1382 memset (&deprecated_registers
[DEPRECATED_REGISTER_BYTE (ii
+ 3)], 0, reg_size
);
1383 memcpy ((char *)&deprecated_registers
[DEPRECATED_REGISTER_BYTE (ii
+ 3)] + adj
,
1384 VALUE_CONTENTS (arg
), len
);
1389 ran_out_of_registers_for_arguments
:
1391 saved_sp
= read_sp ();
1393 /* Location for 8 parameters are always reserved. */
1396 /* Another six words for back chain, TOC register, link register, etc. */
1399 /* Stack pointer must be quadword aligned. */
1402 /* If there are more arguments, allocate space for them in
1403 the stack, then push them starting from the ninth one. */
1405 if ((argno
< nargs
) || argbytes
)
1411 space
+= ((len
- argbytes
+ 3) & -4);
1417 for (; jj
< nargs
; ++jj
)
1419 struct value
*val
= args
[jj
];
1420 space
+= ((TYPE_LENGTH (VALUE_TYPE (val
))) + 3) & -4;
1423 /* Add location required for the rest of the parameters. */
1424 space
= (space
+ 15) & -16;
1427 /* This is another instance we need to be concerned about
1428 securing our stack space. If we write anything underneath %sp
1429 (r1), we might conflict with the kernel who thinks he is free
1430 to use this area. So, update %sp first before doing anything
1433 regcache_raw_write_signed (regcache
, SP_REGNUM
, sp
);
1435 /* If the last argument copied into the registers didn't fit there
1436 completely, push the rest of it into stack. */
1440 write_memory (sp
+ 24 + (ii
* 4),
1441 ((char *) VALUE_CONTENTS (arg
)) + argbytes
,
1444 ii
+= ((len
- argbytes
+ 3) & -4) / 4;
1447 /* Push the rest of the arguments into stack. */
1448 for (; argno
< nargs
; ++argno
)
1452 type
= check_typedef (VALUE_TYPE (arg
));
1453 len
= TYPE_LENGTH (type
);
1456 /* Float types should be passed in fpr's, as well as in the
1458 if (TYPE_CODE (type
) == TYPE_CODE_FLT
&& f_argno
< 13)
1462 printf_unfiltered ("Fatal Error: a floating point parameter"
1463 " #%d with a size > 8 is found!\n", argno
);
1465 memcpy (&(deprecated_registers
1466 [DEPRECATED_REGISTER_BYTE
1467 (tdep
->ppc_fp0_regnum
+ 1 + f_argno
)]),
1468 VALUE_CONTENTS (arg
),
1473 write_memory (sp
+ 24 + (ii
* 4),
1474 (char *) VALUE_CONTENTS (arg
),
1476 ii
+= ((len
+ 3) & -4) / 4;
1480 /* Set the stack pointer. According to the ABI, the SP is meant to
1481 be set _before_ the corresponding stack space is used. On AIX,
1482 this even applies when the target has been completely stopped!
1483 Not doing this can lead to conflicts with the kernel which thinks
1484 that it still has control over this not-yet-allocated stack
1486 regcache_raw_write_signed (regcache
, SP_REGNUM
, sp
);
1488 /* Set back chain properly. */
1489 store_unsigned_integer (tmp_buffer
, 4, saved_sp
);
1490 write_memory (sp
, tmp_buffer
, 4);
1492 /* Point the inferior function call's return address at the dummy's
1494 regcache_raw_write_signed (regcache
, tdep
->ppc_lr_regnum
, bp_addr
);
1496 /* Set the TOC register, get the value from the objfile reader
1497 which, in turn, gets it from the VMAP table. */
1498 if (rs6000_find_toc_address_hook
!= NULL
)
1500 CORE_ADDR tocvalue
= (*rs6000_find_toc_address_hook
) (func_addr
);
1501 regcache_raw_write_signed (regcache
, tdep
->ppc_toc_regnum
, tocvalue
);
1504 target_store_registers (-1);
1508 /* PowerOpen always puts structures in memory. Vectors, which were
1509 added later, do get returned in a register though. */
1512 rs6000_use_struct_convention (int gcc_p
, struct type
*value_type
)
1514 if ((TYPE_LENGTH (value_type
) == 16 || TYPE_LENGTH (value_type
) == 8)
1515 && TYPE_VECTOR (value_type
))
1521 rs6000_extract_return_value (struct type
*valtype
, char *regbuf
, char *valbuf
)
1524 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1526 /* The calling convention this function implements assumes the
1527 processor has floating-point registers. We shouldn't be using it
1528 on PPC variants that lack them. */
1529 gdb_assert (ppc_floating_point_unit_p (current_gdbarch
));
1531 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
)
1534 /* floats and doubles are returned in fpr1. fpr's have a size of 8 bytes.
1535 We need to truncate the return value into float size (4 byte) if
1538 convert_typed_floating (®buf
[DEPRECATED_REGISTER_BYTE
1539 (tdep
->ppc_fp0_regnum
+ 1)],
1540 builtin_type_double
,
1544 else if (TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
1545 && TYPE_LENGTH (valtype
) == 16
1546 && TYPE_VECTOR (valtype
))
1548 memcpy (valbuf
, regbuf
+ DEPRECATED_REGISTER_BYTE (tdep
->ppc_vr0_regnum
+ 2),
1549 TYPE_LENGTH (valtype
));
1553 /* return value is copied starting from r3. */
1554 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
1555 && TYPE_LENGTH (valtype
) < DEPRECATED_REGISTER_RAW_SIZE (3))
1556 offset
= DEPRECATED_REGISTER_RAW_SIZE (3) - TYPE_LENGTH (valtype
);
1559 regbuf
+ DEPRECATED_REGISTER_BYTE (3) + offset
,
1560 TYPE_LENGTH (valtype
));
1564 /* Return whether handle_inferior_event() should proceed through code
1565 starting at PC in function NAME when stepping.
1567 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
1568 handle memory references that are too distant to fit in instructions
1569 generated by the compiler. For example, if 'foo' in the following
1574 is greater than 32767, the linker might replace the lwz with a branch to
1575 somewhere in @FIX1 that does the load in 2 instructions and then branches
1576 back to where execution should continue.
1578 GDB should silently step over @FIX code, just like AIX dbx does.
1579 Unfortunately, the linker uses the "b" instruction for the branches,
1580 meaning that the link register doesn't get set. Therefore, GDB's usual
1581 step_over_function() mechanism won't work.
1583 Instead, use the IN_SOLIB_RETURN_TRAMPOLINE and SKIP_TRAMPOLINE_CODE hooks
1584 in handle_inferior_event() to skip past @FIX code. */
1587 rs6000_in_solib_return_trampoline (CORE_ADDR pc
, char *name
)
1589 return name
&& !strncmp (name
, "@FIX", 4);
1592 /* Skip code that the user doesn't want to see when stepping:
1594 1. Indirect function calls use a piece of trampoline code to do context
1595 switching, i.e. to set the new TOC table. Skip such code if we are on
1596 its first instruction (as when we have single-stepped to here).
1598 2. Skip shared library trampoline code (which is different from
1599 indirect function call trampolines).
1601 3. Skip bigtoc fixup code.
1603 Result is desired PC to step until, or NULL if we are not in
1604 code that should be skipped. */
1607 rs6000_skip_trampoline_code (CORE_ADDR pc
)
1609 unsigned int ii
, op
;
1611 CORE_ADDR solib_target_pc
;
1612 struct minimal_symbol
*msymbol
;
1614 static unsigned trampoline_code
[] =
1616 0x800b0000, /* l r0,0x0(r11) */
1617 0x90410014, /* st r2,0x14(r1) */
1618 0x7c0903a6, /* mtctr r0 */
1619 0x804b0004, /* l r2,0x4(r11) */
1620 0x816b0008, /* l r11,0x8(r11) */
1621 0x4e800420, /* bctr */
1622 0x4e800020, /* br */
1626 /* Check for bigtoc fixup code. */
1627 msymbol
= lookup_minimal_symbol_by_pc (pc
);
1628 if (msymbol
&& rs6000_in_solib_return_trampoline (pc
, DEPRECATED_SYMBOL_NAME (msymbol
)))
1630 /* Double-check that the third instruction from PC is relative "b". */
1631 op
= read_memory_integer (pc
+ 8, 4);
1632 if ((op
& 0xfc000003) == 0x48000000)
1634 /* Extract bits 6-29 as a signed 24-bit relative word address and
1635 add it to the containing PC. */
1636 rel
= ((int)(op
<< 6) >> 6);
1637 return pc
+ 8 + rel
;
1641 /* If pc is in a shared library trampoline, return its target. */
1642 solib_target_pc
= find_solib_trampoline_target (pc
);
1643 if (solib_target_pc
)
1644 return solib_target_pc
;
1646 for (ii
= 0; trampoline_code
[ii
]; ++ii
)
1648 op
= read_memory_integer (pc
+ (ii
* 4), 4);
1649 if (op
!= trampoline_code
[ii
])
1652 ii
= read_register (11); /* r11 holds destination addr */
1653 pc
= read_memory_addr (ii
, gdbarch_tdep (current_gdbarch
)->wordsize
); /* (r11) value */
1657 /* Return the size of register REG when words are WORDSIZE bytes long. If REG
1658 isn't available with that word size, return 0. */
1661 regsize (const struct reg
*reg
, int wordsize
)
1663 return wordsize
== 8 ? reg
->sz64
: reg
->sz32
;
1666 /* Return the name of register number N, or null if no such register exists
1667 in the current architecture. */
1670 rs6000_register_name (int n
)
1672 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1673 const struct reg
*reg
= tdep
->regs
+ n
;
1675 if (!regsize (reg
, tdep
->wordsize
))
1680 /* Return the GDB type object for the "standard" data type
1681 of data in register N. */
1683 static struct type
*
1684 rs6000_register_type (struct gdbarch
*gdbarch
, int n
)
1686 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1687 const struct reg
*reg
= tdep
->regs
+ n
;
1690 return builtin_type_double
;
1693 int size
= regsize (reg
, tdep
->wordsize
);
1697 return builtin_type_int0
;
1699 return builtin_type_uint32
;
1701 if (tdep
->ppc_ev0_regnum
<= n
&& n
<= tdep
->ppc_ev31_regnum
)
1702 return builtin_type_vec64
;
1704 return builtin_type_uint64
;
1707 return builtin_type_vec128
;
1710 internal_error (__FILE__
, __LINE__
, "Register %d size %d unknown",
1716 /* The register format for RS/6000 floating point registers is always
1717 double, we need a conversion if the memory format is float. */
1720 rs6000_convert_register_p (int regnum
, struct type
*type
)
1722 const struct reg
*reg
= gdbarch_tdep (current_gdbarch
)->regs
+ regnum
;
1725 && TYPE_CODE (type
) == TYPE_CODE_FLT
1726 && TYPE_LENGTH (type
) != TYPE_LENGTH (builtin_type_double
));
1730 rs6000_register_to_value (struct frame_info
*frame
,
1735 const struct reg
*reg
= gdbarch_tdep (current_gdbarch
)->regs
+ regnum
;
1736 char from
[MAX_REGISTER_SIZE
];
1738 gdb_assert (reg
->fpr
);
1739 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
1741 get_frame_register (frame
, regnum
, from
);
1742 convert_typed_floating (from
, builtin_type_double
, to
, type
);
1746 rs6000_value_to_register (struct frame_info
*frame
,
1751 const struct reg
*reg
= gdbarch_tdep (current_gdbarch
)->regs
+ regnum
;
1752 char to
[MAX_REGISTER_SIZE
];
1754 gdb_assert (reg
->fpr
);
1755 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
1757 convert_typed_floating (from
, type
, to
, builtin_type_double
);
1758 put_frame_register (frame
, regnum
, to
);
1762 e500_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1763 int reg_nr
, void *buffer
)
1767 char temp_buffer
[MAX_REGISTER_SIZE
];
1768 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1770 if (reg_nr
>= tdep
->ppc_gp0_regnum
1771 && reg_nr
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
)
1773 base_regnum
= reg_nr
- tdep
->ppc_gp0_regnum
+ tdep
->ppc_ev0_regnum
;
1775 /* Build the value in the provided buffer. */
1776 /* Read the raw register of which this one is the lower portion. */
1777 regcache_raw_read (regcache
, base_regnum
, temp_buffer
);
1778 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1780 memcpy ((char *) buffer
, temp_buffer
+ offset
, 4);
1785 e500_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1786 int reg_nr
, const void *buffer
)
1790 char temp_buffer
[MAX_REGISTER_SIZE
];
1791 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1793 if (reg_nr
>= tdep
->ppc_gp0_regnum
1794 && reg_nr
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
)
1796 base_regnum
= reg_nr
- tdep
->ppc_gp0_regnum
+ tdep
->ppc_ev0_regnum
;
1797 /* reg_nr is 32 bit here, and base_regnum is 64 bits. */
1798 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1801 /* Let's read the value of the base register into a temporary
1802 buffer, so that overwriting the last four bytes with the new
1803 value of the pseudo will leave the upper 4 bytes unchanged. */
1804 regcache_raw_read (regcache
, base_regnum
, temp_buffer
);
1806 /* Write as an 8 byte quantity. */
1807 memcpy (temp_buffer
+ offset
, (char *) buffer
, 4);
1808 regcache_raw_write (regcache
, base_regnum
, temp_buffer
);
1812 /* Convert a DBX STABS register number to a GDB register number. */
1814 rs6000_stab_reg_to_regnum (int num
)
1816 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1818 if (0 <= num
&& num
<= 31)
1819 return tdep
->ppc_gp0_regnum
+ num
;
1820 else if (32 <= num
&& num
<= 63)
1821 /* FIXME: jimb/2004-05-05: What should we do when the debug info
1822 specifies registers the architecture doesn't have? Our
1823 callers don't check the value we return. */
1824 return tdep
->ppc_fp0_regnum
+ (num
- 32);
1825 else if (77 <= num
&& num
<= 108)
1826 return tdep
->ppc_vr0_regnum
+ (num
- 77);
1827 else if (1200 <= num
&& num
< 1200 + 32)
1828 return tdep
->ppc_ev0_regnum
+ (num
- 1200);
1833 return tdep
->ppc_mq_regnum
;
1835 return tdep
->ppc_lr_regnum
;
1837 return tdep
->ppc_ctr_regnum
;
1839 return tdep
->ppc_xer_regnum
;
1841 return tdep
->ppc_vrsave_regnum
;
1843 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
1845 return tdep
->ppc_acc_regnum
;
1847 return tdep
->ppc_spefscr_regnum
;
1854 /* Convert a Dwarf 2 register number to a GDB register number. */
1856 rs6000_dwarf2_reg_to_regnum (int num
)
1858 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1860 if (0 <= num
&& num
<= 31)
1861 return tdep
->ppc_gp0_regnum
+ num
;
1862 else if (32 <= num
&& num
<= 63)
1863 /* FIXME: jimb/2004-05-05: What should we do when the debug info
1864 specifies registers the architecture doesn't have? Our
1865 callers don't check the value we return. */
1866 return tdep
->ppc_fp0_regnum
+ (num
- 32);
1867 else if (1124 <= num
&& num
< 1124 + 32)
1868 return tdep
->ppc_vr0_regnum
+ (num
- 1124);
1869 else if (1200 <= num
&& num
< 1200 + 32)
1870 return tdep
->ppc_ev0_regnum
+ (num
- 1200);
1875 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
1877 return tdep
->ppc_acc_regnum
;
1879 return tdep
->ppc_mq_regnum
;
1881 return tdep
->ppc_xer_regnum
;
1883 return tdep
->ppc_lr_regnum
;
1885 return tdep
->ppc_ctr_regnum
;
1887 return tdep
->ppc_vrsave_regnum
;
1889 return tdep
->ppc_spefscr_regnum
;
1897 rs6000_store_return_value (struct type
*type
,
1898 struct regcache
*regcache
,
1901 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1902 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1905 /* The calling convention this function implements assumes the
1906 processor has floating-point registers. We shouldn't be using it
1907 on PPC variants that lack them. */
1908 gdb_assert (ppc_floating_point_unit_p (gdbarch
));
1910 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1911 /* Floating point values are returned starting from FPR1 and up.
1912 Say a double_double_double type could be returned in
1913 FPR1/FPR2/FPR3 triple. */
1914 regnum
= tdep
->ppc_fp0_regnum
+ 1;
1915 else if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
1917 if (TYPE_LENGTH (type
) == 16
1918 && TYPE_VECTOR (type
))
1919 regnum
= tdep
->ppc_vr0_regnum
+ 2;
1924 /* Everything else is returned in GPR3 and up. */
1925 regnum
= tdep
->ppc_gp0_regnum
+ 3;
1928 size_t bytes_written
= 0;
1930 while (bytes_written
< TYPE_LENGTH (type
))
1932 /* How much of this value can we write to this register? */
1933 size_t bytes_to_write
= min (TYPE_LENGTH (type
) - bytes_written
,
1934 register_size (gdbarch
, regnum
));
1935 regcache_cooked_write_part (regcache
, regnum
,
1937 (char *) valbuf
+ bytes_written
);
1939 bytes_written
+= bytes_to_write
;
1945 /* Extract from an array REGBUF containing the (raw) register state
1946 the address in which a function should return its structure value,
1947 as a CORE_ADDR (or an expression that can be used as one). */
1950 rs6000_extract_struct_value_address (struct regcache
*regcache
)
1952 /* FIXME: cagney/2002-09-26: PR gdb/724: When making an inferior
1953 function call GDB knows the address of the struct return value
1954 and hence, should not need to call this function. Unfortunately,
1955 the current call_function_by_hand() code only saves the most
1956 recent struct address leading to occasional calls. The code
1957 should instead maintain a stack of such addresses (in the dummy
1959 /* NOTE: cagney/2002-09-26: Return 0 which indicates that we've
1960 really got no idea where the return value is being stored. While
1961 r3, on function entry, contained the address it will have since
1962 been reused (scratch) and hence wouldn't be valid */
1966 /* Hook called when a new child process is started. */
1969 rs6000_create_inferior (int pid
)
1971 if (rs6000_set_host_arch_hook
)
1972 rs6000_set_host_arch_hook (pid
);
1975 /* Support for CONVERT_FROM_FUNC_PTR_ADDR (ARCH, ADDR, TARG).
1977 Usually a function pointer's representation is simply the address
1978 of the function. On the RS/6000 however, a function pointer is
1979 represented by a pointer to a TOC entry. This TOC entry contains
1980 three words, the first word is the address of the function, the
1981 second word is the TOC pointer (r2), and the third word is the
1982 static chain value. Throughout GDB it is currently assumed that a
1983 function pointer contains the address of the function, which is not
1984 easy to fix. In addition, the conversion of a function address to
1985 a function pointer would require allocation of a TOC entry in the
1986 inferior's memory space, with all its drawbacks. To be able to
1987 call C++ virtual methods in the inferior (which are called via
1988 function pointers), find_function_addr uses this function to get the
1989 function address from a function pointer. */
1991 /* Return real function address if ADDR (a function pointer) is in the data
1992 space and is therefore a special function pointer. */
1995 rs6000_convert_from_func_ptr_addr (struct gdbarch
*gdbarch
,
1997 struct target_ops
*targ
)
1999 struct obj_section
*s
;
2001 s
= find_pc_section (addr
);
2002 if (s
&& s
->the_bfd_section
->flags
& SEC_CODE
)
2005 /* ADDR is in the data space, so it's a special function pointer. */
2006 return read_memory_addr (addr
, gdbarch_tdep (current_gdbarch
)->wordsize
);
2010 /* Handling the various POWER/PowerPC variants. */
2013 /* The arrays here called registers_MUMBLE hold information about available
2016 For each family of PPC variants, I've tried to isolate out the
2017 common registers and put them up front, so that as long as you get
2018 the general family right, GDB will correctly identify the registers
2019 common to that family. The common register sets are:
2021 For the 60x family: hid0 hid1 iabr dabr pir
2023 For the 505 and 860 family: eie eid nri
2025 For the 403 and 403GC: icdbdr esr dear evpr cdbcr tsr tcr pit tbhi
2026 tblo srr2 srr3 dbsr dbcr iac1 iac2 dac1 dac2 dccr iccr pbl1
2029 Most of these register groups aren't anything formal. I arrived at
2030 them by looking at the registers that occurred in more than one
2033 Note: kevinb/2002-04-30: Support for the fpscr register was added
2034 during April, 2002. Slot 70 is being used for PowerPC and slot 71
2035 for Power. For PowerPC, slot 70 was unused and was already in the
2036 PPC_UISA_SPRS which is ideally where fpscr should go. For Power,
2037 slot 70 was being used for "mq", so the next available slot (71)
2038 was chosen. It would have been nice to be able to make the
2039 register numbers the same across processor cores, but this wasn't
2040 possible without either 1) renumbering some registers for some
2041 processors or 2) assigning fpscr to a really high slot that's
2042 larger than any current register number. Doing (1) is bad because
2043 existing stubs would break. Doing (2) is undesirable because it
2044 would introduce a really large gap between fpscr and the rest of
2045 the registers for most processors. */
2047 /* Convenience macros for populating register arrays. */
2049 /* Within another macro, convert S to a string. */
2053 /* Return a struct reg defining register NAME that's 32 bits on 32-bit systems
2054 and 64 bits on 64-bit systems. */
2055 #define R(name) { STR(name), 4, 8, 0, 0 }
2057 /* Return a struct reg defining register NAME that's 32 bits on all
2059 #define R4(name) { STR(name), 4, 4, 0, 0 }
2061 /* Return a struct reg defining register NAME that's 64 bits on all
2063 #define R8(name) { STR(name), 8, 8, 0, 0 }
2065 /* Return a struct reg defining register NAME that's 128 bits on all
2067 #define R16(name) { STR(name), 16, 16, 0, 0 }
2069 /* Return a struct reg defining floating-point register NAME. */
2070 #define F(name) { STR(name), 8, 8, 1, 0 }
2072 /* Return a struct reg defining a pseudo register NAME. */
2073 #define P(name) { STR(name), 4, 8, 0, 1}
2075 /* Return a struct reg defining register NAME that's 32 bits on 32-bit
2076 systems and that doesn't exist on 64-bit systems. */
2077 #define R32(name) { STR(name), 4, 0, 0, 0 }
2079 /* Return a struct reg defining register NAME that's 64 bits on 64-bit
2080 systems and that doesn't exist on 32-bit systems. */
2081 #define R64(name) { STR(name), 0, 8, 0, 0 }
2083 /* Return a struct reg placeholder for a register that doesn't exist. */
2084 #define R0 { 0, 0, 0, 0, 0 }
2086 /* UISA registers common across all architectures, including POWER. */
2088 #define COMMON_UISA_REGS \
2089 /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \
2090 /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \
2091 /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \
2092 /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \
2093 /* 32 */ F(f0), F(f1), F(f2), F(f3), F(f4), F(f5), F(f6), F(f7), \
2094 /* 40 */ F(f8), F(f9), F(f10),F(f11),F(f12),F(f13),F(f14),F(f15), \
2095 /* 48 */ F(f16),F(f17),F(f18),F(f19),F(f20),F(f21),F(f22),F(f23), \
2096 /* 56 */ F(f24),F(f25),F(f26),F(f27),F(f28),F(f29),F(f30),F(f31), \
2097 /* 64 */ R(pc), R(ps)
2099 #define COMMON_UISA_NOFP_REGS \
2100 /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \
2101 /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \
2102 /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \
2103 /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \
2104 /* 32 */ R0, R0, R0, R0, R0, R0, R0, R0, \
2105 /* 40 */ R0, R0, R0, R0, R0, R0, R0, R0, \
2106 /* 48 */ R0, R0, R0, R0, R0, R0, R0, R0, \
2107 /* 56 */ R0, R0, R0, R0, R0, R0, R0, R0, \
2108 /* 64 */ R(pc), R(ps)
2110 /* UISA-level SPRs for PowerPC. */
2111 #define PPC_UISA_SPRS \
2112 /* 66 */ R4(cr), R(lr), R(ctr), R4(xer), R4(fpscr)
2114 /* UISA-level SPRs for PowerPC without floating point support. */
2115 #define PPC_UISA_NOFP_SPRS \
2116 /* 66 */ R4(cr), R(lr), R(ctr), R4(xer), R0
2118 /* Segment registers, for PowerPC. */
2119 #define PPC_SEGMENT_REGS \
2120 /* 71 */ R32(sr0), R32(sr1), R32(sr2), R32(sr3), \
2121 /* 75 */ R32(sr4), R32(sr5), R32(sr6), R32(sr7), \
2122 /* 79 */ R32(sr8), R32(sr9), R32(sr10), R32(sr11), \
2123 /* 83 */ R32(sr12), R32(sr13), R32(sr14), R32(sr15)
2125 /* OEA SPRs for PowerPC. */
2126 #define PPC_OEA_SPRS \
2128 /* 88 */ R(ibat0u), R(ibat0l), R(ibat1u), R(ibat1l), \
2129 /* 92 */ R(ibat2u), R(ibat2l), R(ibat3u), R(ibat3l), \
2130 /* 96 */ R(dbat0u), R(dbat0l), R(dbat1u), R(dbat1l), \
2131 /* 100 */ R(dbat2u), R(dbat2l), R(dbat3u), R(dbat3l), \
2132 /* 104 */ R(sdr1), R64(asr), R(dar), R4(dsisr), \
2133 /* 108 */ R(sprg0), R(sprg1), R(sprg2), R(sprg3), \
2134 /* 112 */ R(srr0), R(srr1), R(tbl), R(tbu), \
2135 /* 116 */ R4(dec), R(dabr), R4(ear)
2137 /* AltiVec registers. */
2138 #define PPC_ALTIVEC_REGS \
2139 /*119*/R16(vr0), R16(vr1), R16(vr2), R16(vr3), R16(vr4), R16(vr5), R16(vr6), R16(vr7), \
2140 /*127*/R16(vr8), R16(vr9), R16(vr10),R16(vr11),R16(vr12),R16(vr13),R16(vr14),R16(vr15), \
2141 /*135*/R16(vr16),R16(vr17),R16(vr18),R16(vr19),R16(vr20),R16(vr21),R16(vr22),R16(vr23), \
2142 /*143*/R16(vr24),R16(vr25),R16(vr26),R16(vr27),R16(vr28),R16(vr29),R16(vr30),R16(vr31), \
2143 /*151*/R4(vscr), R4(vrsave)
2145 /* Vectors of hi-lo general purpose registers. */
2146 #define PPC_EV_REGS \
2147 /* 0*/R8(ev0), R8(ev1), R8(ev2), R8(ev3), R8(ev4), R8(ev5), R8(ev6), R8(ev7), \
2148 /* 8*/R8(ev8), R8(ev9), R8(ev10),R8(ev11),R8(ev12),R8(ev13),R8(ev14),R8(ev15), \
2149 /*16*/R8(ev16),R8(ev17),R8(ev18),R8(ev19),R8(ev20),R8(ev21),R8(ev22),R8(ev23), \
2150 /*24*/R8(ev24),R8(ev25),R8(ev26),R8(ev27),R8(ev28),R8(ev29),R8(ev30),R8(ev31)
2152 /* Lower half of the EV registers. */
2153 #define PPC_GPRS_PSEUDO_REGS \
2154 /* 0 */ P(r0), P(r1), P(r2), P(r3), P(r4), P(r5), P(r6), P(r7), \
2155 /* 8 */ P(r8), P(r9), P(r10),P(r11),P(r12),P(r13),P(r14),P(r15), \
2156 /* 16 */ P(r16),P(r17),P(r18),P(r19),P(r20),P(r21),P(r22),P(r23), \
2157 /* 24 */ P(r24),P(r25),P(r26),P(r27),P(r28),P(r29),P(r30),P(r31)
2159 /* IBM POWER (pre-PowerPC) architecture, user-level view. We only cover
2160 user-level SPR's. */
2161 static const struct reg registers_power
[] =
2164 /* 66 */ R4(cnd
), R(lr
), R(cnt
), R4(xer
), R4(mq
),
2168 /* PowerPC UISA - a PPC processor as viewed by user-level code. A UISA-only
2169 view of the PowerPC. */
2170 static const struct reg registers_powerpc
[] =
2177 /* PowerPC UISA - a PPC processor as viewed by user-level
2178 code, but without floating point registers. */
2179 static const struct reg registers_powerpc_nofp
[] =
2181 COMMON_UISA_NOFP_REGS
,
2185 /* IBM PowerPC 403. */
2186 static const struct reg registers_403
[] =
2192 /* 119 */ R(icdbdr
), R(esr
), R(dear
), R(evpr
),
2193 /* 123 */ R(cdbcr
), R(tsr
), R(tcr
), R(pit
),
2194 /* 127 */ R(tbhi
), R(tblo
), R(srr2
), R(srr3
),
2195 /* 131 */ R(dbsr
), R(dbcr
), R(iac1
), R(iac2
),
2196 /* 135 */ R(dac1
), R(dac2
), R(dccr
), R(iccr
),
2197 /* 139 */ R(pbl1
), R(pbu1
), R(pbl2
), R(pbu2
)
2200 /* IBM PowerPC 403GC. */
2201 static const struct reg registers_403GC
[] =
2207 /* 119 */ R(icdbdr
), R(esr
), R(dear
), R(evpr
),
2208 /* 123 */ R(cdbcr
), R(tsr
), R(tcr
), R(pit
),
2209 /* 127 */ R(tbhi
), R(tblo
), R(srr2
), R(srr3
),
2210 /* 131 */ R(dbsr
), R(dbcr
), R(iac1
), R(iac2
),
2211 /* 135 */ R(dac1
), R(dac2
), R(dccr
), R(iccr
),
2212 /* 139 */ R(pbl1
), R(pbu1
), R(pbl2
), R(pbu2
),
2213 /* 143 */ R(zpr
), R(pid
), R(sgr
), R(dcwr
),
2214 /* 147 */ R(tbhu
), R(tblu
)
2217 /* Motorola PowerPC 505. */
2218 static const struct reg registers_505
[] =
2224 /* 119 */ R(eie
), R(eid
), R(nri
)
2227 /* Motorola PowerPC 860 or 850. */
2228 static const struct reg registers_860
[] =
2234 /* 119 */ R(eie
), R(eid
), R(nri
), R(cmpa
),
2235 /* 123 */ R(cmpb
), R(cmpc
), R(cmpd
), R(icr
),
2236 /* 127 */ R(der
), R(counta
), R(countb
), R(cmpe
),
2237 /* 131 */ R(cmpf
), R(cmpg
), R(cmph
), R(lctrl1
),
2238 /* 135 */ R(lctrl2
), R(ictrl
), R(bar
), R(ic_cst
),
2239 /* 139 */ R(ic_adr
), R(ic_dat
), R(dc_cst
), R(dc_adr
),
2240 /* 143 */ R(dc_dat
), R(dpdr
), R(dpir
), R(immr
),
2241 /* 147 */ R(mi_ctr
), R(mi_ap
), R(mi_epn
), R(mi_twc
),
2242 /* 151 */ R(mi_rpn
), R(md_ctr
), R(m_casid
), R(md_ap
),
2243 /* 155 */ R(md_epn
), R(md_twb
), R(md_twc
), R(md_rpn
),
2244 /* 159 */ R(m_tw
), R(mi_dbcam
), R(mi_dbram0
), R(mi_dbram1
),
2245 /* 163 */ R(md_dbcam
), R(md_dbram0
), R(md_dbram1
)
2248 /* Motorola PowerPC 601. Note that the 601 has different register numbers
2249 for reading and writing RTCU and RTCL. However, how one reads and writes a
2250 register is the stub's problem. */
2251 static const struct reg registers_601
[] =
2257 /* 119 */ R(hid0
), R(hid1
), R(iabr
), R(dabr
),
2258 /* 123 */ R(pir
), R(mq
), R(rtcu
), R(rtcl
)
2261 /* Motorola PowerPC 602. */
2262 static const struct reg registers_602
[] =
2268 /* 119 */ R(hid0
), R(hid1
), R(iabr
), R0
,
2269 /* 123 */ R0
, R(tcr
), R(ibr
), R(esassr
),
2270 /* 127 */ R(sebr
), R(ser
), R(sp
), R(lt
)
2273 /* Motorola/IBM PowerPC 603 or 603e. */
2274 static const struct reg registers_603
[] =
2280 /* 119 */ R(hid0
), R(hid1
), R(iabr
), R0
,
2281 /* 123 */ R0
, R(dmiss
), R(dcmp
), R(hash1
),
2282 /* 127 */ R(hash2
), R(imiss
), R(icmp
), R(rpa
)
2285 /* Motorola PowerPC 604 or 604e. */
2286 static const struct reg registers_604
[] =
2292 /* 119 */ R(hid0
), R(hid1
), R(iabr
), R(dabr
),
2293 /* 123 */ R(pir
), R(mmcr0
), R(pmc1
), R(pmc2
),
2294 /* 127 */ R(sia
), R(sda
)
2297 /* Motorola/IBM PowerPC 750 or 740. */
2298 static const struct reg registers_750
[] =
2304 /* 119 */ R(hid0
), R(hid1
), R(iabr
), R(dabr
),
2305 /* 123 */ R0
, R(ummcr0
), R(upmc1
), R(upmc2
),
2306 /* 127 */ R(usia
), R(ummcr1
), R(upmc3
), R(upmc4
),
2307 /* 131 */ R(mmcr0
), R(pmc1
), R(pmc2
), R(sia
),
2308 /* 135 */ R(mmcr1
), R(pmc3
), R(pmc4
), R(l2cr
),
2309 /* 139 */ R(ictc
), R(thrm1
), R(thrm2
), R(thrm3
)
2313 /* Motorola PowerPC 7400. */
2314 static const struct reg registers_7400
[] =
2316 /* gpr0-gpr31, fpr0-fpr31 */
2318 /* cr, lr, ctr, xer, fpscr */
2323 /* vr0-vr31, vrsave, vscr */
2325 /* FIXME? Add more registers? */
2328 /* Motorola e500. */
2329 static const struct reg registers_e500
[] =
2332 /* cr, lr, ctr, xer, "" */
2336 R8(acc
), R(spefscr
),
2337 /* NOTE: Add new registers here the end of the raw register
2338 list and just before the first pseudo register. */
2340 PPC_GPRS_PSEUDO_REGS
2343 /* Information about a particular processor variant. */
2347 /* Name of this variant. */
2350 /* English description of the variant. */
2353 /* bfd_arch_info.arch corresponding to variant. */
2354 enum bfd_architecture arch
;
2356 /* bfd_arch_info.mach corresponding to variant. */
2359 /* Number of real registers. */
2362 /* Number of pseudo registers. */
2365 /* Number of total registers (the sum of nregs and npregs). */
2368 /* Table of register names; registers[R] is the name of the register
2370 const struct reg
*regs
;
2373 #define tot_num_registers(list) (sizeof (list) / sizeof((list)[0]))
2376 num_registers (const struct reg
*reg_list
, int num_tot_regs
)
2381 for (i
= 0; i
< num_tot_regs
; i
++)
2382 if (!reg_list
[i
].pseudo
)
2389 num_pseudo_registers (const struct reg
*reg_list
, int num_tot_regs
)
2394 for (i
= 0; i
< num_tot_regs
; i
++)
2395 if (reg_list
[i
].pseudo
)
2401 /* Information in this table comes from the following web sites:
2402 IBM: http://www.chips.ibm.com:80/products/embedded/
2403 Motorola: http://www.mot.com/SPS/PowerPC/
2405 I'm sure I've got some of the variant descriptions not quite right.
2406 Please report any inaccuracies you find to GDB's maintainer.
2408 If you add entries to this table, please be sure to allow the new
2409 value as an argument to the --with-cpu flag, in configure.in. */
2411 static struct variant variants
[] =
2414 {"powerpc", "PowerPC user-level", bfd_arch_powerpc
,
2415 bfd_mach_ppc
, -1, -1, tot_num_registers (registers_powerpc
),
2417 {"power", "POWER user-level", bfd_arch_rs6000
,
2418 bfd_mach_rs6k
, -1, -1, tot_num_registers (registers_power
),
2420 {"403", "IBM PowerPC 403", bfd_arch_powerpc
,
2421 bfd_mach_ppc_403
, -1, -1, tot_num_registers (registers_403
),
2423 {"601", "Motorola PowerPC 601", bfd_arch_powerpc
,
2424 bfd_mach_ppc_601
, -1, -1, tot_num_registers (registers_601
),
2426 {"602", "Motorola PowerPC 602", bfd_arch_powerpc
,
2427 bfd_mach_ppc_602
, -1, -1, tot_num_registers (registers_602
),
2429 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc
,
2430 bfd_mach_ppc_603
, -1, -1, tot_num_registers (registers_603
),
2432 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc
,
2433 604, -1, -1, tot_num_registers (registers_604
),
2435 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc
,
2436 bfd_mach_ppc_403gc
, -1, -1, tot_num_registers (registers_403GC
),
2438 {"505", "Motorola PowerPC 505", bfd_arch_powerpc
,
2439 bfd_mach_ppc_505
, -1, -1, tot_num_registers (registers_505
),
2441 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc
,
2442 bfd_mach_ppc_860
, -1, -1, tot_num_registers (registers_860
),
2444 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc
,
2445 bfd_mach_ppc_750
, -1, -1, tot_num_registers (registers_750
),
2447 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc
,
2448 bfd_mach_ppc_7400
, -1, -1, tot_num_registers (registers_7400
),
2450 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc
,
2451 bfd_mach_ppc_e500
, -1, -1, tot_num_registers (registers_e500
),
2455 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc
,
2456 bfd_mach_ppc64
, -1, -1, tot_num_registers (registers_powerpc
),
2458 {"620", "Motorola PowerPC 620", bfd_arch_powerpc
,
2459 bfd_mach_ppc_620
, -1, -1, tot_num_registers (registers_powerpc
),
2461 {"630", "Motorola PowerPC 630", bfd_arch_powerpc
,
2462 bfd_mach_ppc_630
, -1, -1, tot_num_registers (registers_powerpc
),
2464 {"a35", "PowerPC A35", bfd_arch_powerpc
,
2465 bfd_mach_ppc_a35
, -1, -1, tot_num_registers (registers_powerpc
),
2467 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc
,
2468 bfd_mach_ppc_rs64ii
, -1, -1, tot_num_registers (registers_powerpc
),
2470 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc
,
2471 bfd_mach_ppc_rs64iii
, -1, -1, tot_num_registers (registers_powerpc
),
2474 /* FIXME: I haven't checked the register sets of the following. */
2475 {"rs1", "IBM POWER RS1", bfd_arch_rs6000
,
2476 bfd_mach_rs6k_rs1
, -1, -1, tot_num_registers (registers_power
),
2478 {"rsc", "IBM POWER RSC", bfd_arch_rs6000
,
2479 bfd_mach_rs6k_rsc
, -1, -1, tot_num_registers (registers_power
),
2481 {"rs2", "IBM POWER RS2", bfd_arch_rs6000
,
2482 bfd_mach_rs6k_rs2
, -1, -1, tot_num_registers (registers_power
),
2485 {0, 0, 0, 0, 0, 0, 0, 0}
2488 /* Initialize the number of registers and pseudo registers in each variant. */
2491 init_variants (void)
2495 for (v
= variants
; v
->name
; v
++)
2498 v
->nregs
= num_registers (v
->regs
, v
->num_tot_regs
);
2499 if (v
->npregs
== -1)
2500 v
->npregs
= num_pseudo_registers (v
->regs
, v
->num_tot_regs
);
2504 /* Return the variant corresponding to architecture ARCH and machine number
2505 MACH. If no such variant exists, return null. */
2507 static const struct variant
*
2508 find_variant_by_arch (enum bfd_architecture arch
, unsigned long mach
)
2510 const struct variant
*v
;
2512 for (v
= variants
; v
->name
; v
++)
2513 if (arch
== v
->arch
&& mach
== v
->mach
)
2520 gdb_print_insn_powerpc (bfd_vma memaddr
, disassemble_info
*info
)
2522 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2523 return print_insn_big_powerpc (memaddr
, info
);
2525 return print_insn_little_powerpc (memaddr
, info
);
2529 rs6000_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2531 return frame_unwind_register_unsigned (next_frame
, PC_REGNUM
);
2534 static struct frame_id
2535 rs6000_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2537 return frame_id_build (frame_unwind_register_unsigned (next_frame
,
2539 frame_pc_unwind (next_frame
));
2542 struct rs6000_frame_cache
2545 CORE_ADDR initial_sp
;
2546 struct trad_frame_saved_reg
*saved_regs
;
2549 static struct rs6000_frame_cache
*
2550 rs6000_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2552 struct rs6000_frame_cache
*cache
;
2553 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
2554 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2555 struct rs6000_framedata fdata
;
2556 int wordsize
= tdep
->wordsize
;
2558 if ((*this_cache
) != NULL
)
2559 return (*this_cache
);
2560 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
2561 (*this_cache
) = cache
;
2562 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
2564 skip_prologue (frame_func_unwind (next_frame
), frame_pc_unwind (next_frame
),
2567 /* If there were any saved registers, figure out parent's stack
2569 /* The following is true only if the frame doesn't have a call to
2572 if (fdata
.saved_fpr
== 0
2573 && fdata
.saved_gpr
== 0
2574 && fdata
.saved_vr
== 0
2575 && fdata
.saved_ev
== 0
2576 && fdata
.lr_offset
== 0
2577 && fdata
.cr_offset
== 0
2578 && fdata
.vr_offset
== 0
2579 && fdata
.ev_offset
== 0)
2580 cache
->base
= frame_unwind_register_unsigned (next_frame
, SP_REGNUM
);
2583 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
2584 address of the current frame. Things might be easier if the
2585 ->frame pointed to the outer-most address of the frame. In
2586 the mean time, the address of the prev frame is used as the
2587 base address of this frame. */
2588 cache
->base
= frame_unwind_register_unsigned (next_frame
, SP_REGNUM
);
2589 if (!fdata
.frameless
)
2590 /* Frameless really means stackless. */
2591 cache
->base
= read_memory_addr (cache
->base
, wordsize
);
2593 trad_frame_set_value (cache
->saved_regs
, SP_REGNUM
, cache
->base
);
2595 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
2596 All fpr's from saved_fpr to fp31 are saved. */
2598 if (fdata
.saved_fpr
>= 0)
2601 CORE_ADDR fpr_addr
= cache
->base
+ fdata
.fpr_offset
;
2603 /* If skip_prologue says floating-point registers were saved,
2604 but the current architecture has no floating-point registers,
2605 then that's strange. But we have no indices to even record
2606 the addresses under, so we just ignore it. */
2607 if (ppc_floating_point_unit_p (gdbarch
))
2608 for (i
= fdata
.saved_fpr
; i
< ppc_num_fprs
; i
++)
2610 cache
->saved_regs
[tdep
->ppc_fp0_regnum
+ i
].addr
= fpr_addr
;
2615 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
2616 All gpr's from saved_gpr to gpr31 are saved. */
2618 if (fdata
.saved_gpr
>= 0)
2621 CORE_ADDR gpr_addr
= cache
->base
+ fdata
.gpr_offset
;
2622 for (i
= fdata
.saved_gpr
; i
< ppc_num_gprs
; i
++)
2624 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= gpr_addr
;
2625 gpr_addr
+= wordsize
;
2629 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
2630 All vr's from saved_vr to vr31 are saved. */
2631 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
2633 if (fdata
.saved_vr
>= 0)
2636 CORE_ADDR vr_addr
= cache
->base
+ fdata
.vr_offset
;
2637 for (i
= fdata
.saved_vr
; i
< 32; i
++)
2639 cache
->saved_regs
[tdep
->ppc_vr0_regnum
+ i
].addr
= vr_addr
;
2640 vr_addr
+= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
2645 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
2646 All vr's from saved_ev to ev31 are saved. ????? */
2647 if (tdep
->ppc_ev0_regnum
!= -1 && tdep
->ppc_ev31_regnum
!= -1)
2649 if (fdata
.saved_ev
>= 0)
2652 CORE_ADDR ev_addr
= cache
->base
+ fdata
.ev_offset
;
2653 for (i
= fdata
.saved_ev
; i
< ppc_num_gprs
; i
++)
2655 cache
->saved_regs
[tdep
->ppc_ev0_regnum
+ i
].addr
= ev_addr
;
2656 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= ev_addr
+ 4;
2657 ev_addr
+= register_size (gdbarch
, tdep
->ppc_ev0_regnum
);
2662 /* If != 0, fdata.cr_offset is the offset from the frame that
2664 if (fdata
.cr_offset
!= 0)
2665 cache
->saved_regs
[tdep
->ppc_cr_regnum
].addr
= cache
->base
+ fdata
.cr_offset
;
2667 /* If != 0, fdata.lr_offset is the offset from the frame that
2669 if (fdata
.lr_offset
!= 0)
2670 cache
->saved_regs
[tdep
->ppc_lr_regnum
].addr
= cache
->base
+ fdata
.lr_offset
;
2671 /* The PC is found in the link register. */
2672 cache
->saved_regs
[PC_REGNUM
] = cache
->saved_regs
[tdep
->ppc_lr_regnum
];
2674 /* If != 0, fdata.vrsave_offset is the offset from the frame that
2675 holds the VRSAVE. */
2676 if (fdata
.vrsave_offset
!= 0)
2677 cache
->saved_regs
[tdep
->ppc_vrsave_regnum
].addr
= cache
->base
+ fdata
.vrsave_offset
;
2679 if (fdata
.alloca_reg
< 0)
2680 /* If no alloca register used, then fi->frame is the value of the
2681 %sp for this frame, and it is good enough. */
2682 cache
->initial_sp
= frame_unwind_register_unsigned (next_frame
, SP_REGNUM
);
2684 cache
->initial_sp
= frame_unwind_register_unsigned (next_frame
,
2691 rs6000_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2692 struct frame_id
*this_id
)
2694 struct rs6000_frame_cache
*info
= rs6000_frame_cache (next_frame
,
2696 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
2700 rs6000_frame_prev_register (struct frame_info
*next_frame
,
2702 int regnum
, int *optimizedp
,
2703 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2704 int *realnump
, void *valuep
)
2706 struct rs6000_frame_cache
*info
= rs6000_frame_cache (next_frame
,
2708 trad_frame_prev_register (next_frame
, info
->saved_regs
, regnum
,
2709 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
2712 static const struct frame_unwind rs6000_frame_unwind
=
2715 rs6000_frame_this_id
,
2716 rs6000_frame_prev_register
2719 static const struct frame_unwind
*
2720 rs6000_frame_sniffer (struct frame_info
*next_frame
)
2722 return &rs6000_frame_unwind
;
2728 rs6000_frame_base_address (struct frame_info
*next_frame
,
2731 struct rs6000_frame_cache
*info
= rs6000_frame_cache (next_frame
,
2733 return info
->initial_sp
;
2736 static const struct frame_base rs6000_frame_base
= {
2737 &rs6000_frame_unwind
,
2738 rs6000_frame_base_address
,
2739 rs6000_frame_base_address
,
2740 rs6000_frame_base_address
2743 static const struct frame_base
*
2744 rs6000_frame_base_sniffer (struct frame_info
*next_frame
)
2746 return &rs6000_frame_base
;
2749 /* Initialize the current architecture based on INFO. If possible, re-use an
2750 architecture from ARCHES, which is a list of architectures already created
2751 during this debugging session.
2753 Called e.g. at program startup, when reading a core file, and when reading
2756 static struct gdbarch
*
2757 rs6000_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2759 struct gdbarch
*gdbarch
;
2760 struct gdbarch_tdep
*tdep
;
2761 int wordsize
, from_xcoff_exec
, from_elf_exec
, power
, i
, off
;
2763 const struct variant
*v
;
2764 enum bfd_architecture arch
;
2770 from_xcoff_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
2771 bfd_get_flavour (info
.abfd
) == bfd_target_xcoff_flavour
;
2773 from_elf_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
2774 bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
;
2776 sysv_abi
= info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
;
2778 /* Check word size. If INFO is from a binary file, infer it from
2779 that, else choose a likely default. */
2780 if (from_xcoff_exec
)
2782 if (bfd_xcoff_is_xcoff64 (info
.abfd
))
2787 else if (from_elf_exec
)
2789 if (elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
2796 if (info
.bfd_arch_info
!= NULL
&& info
.bfd_arch_info
->bits_per_word
!= 0)
2797 wordsize
= info
.bfd_arch_info
->bits_per_word
/
2798 info
.bfd_arch_info
->bits_per_byte
;
2803 /* Find a candidate among extant architectures. */
2804 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2806 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
2808 /* Word size in the various PowerPC bfd_arch_info structs isn't
2809 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
2810 separate word size check. */
2811 tdep
= gdbarch_tdep (arches
->gdbarch
);
2812 if (tdep
&& tdep
->wordsize
== wordsize
)
2813 return arches
->gdbarch
;
2816 /* None found, create a new architecture from INFO, whose bfd_arch_info
2817 validity depends on the source:
2818 - executable useless
2819 - rs6000_host_arch() good
2821 - "set arch" trust blindly
2822 - GDB startup useless but harmless */
2824 if (!from_xcoff_exec
)
2826 arch
= info
.bfd_arch_info
->arch
;
2827 mach
= info
.bfd_arch_info
->mach
;
2831 arch
= bfd_arch_powerpc
;
2832 bfd_default_set_arch_mach (&abfd
, arch
, 0);
2833 info
.bfd_arch_info
= bfd_get_arch_info (&abfd
);
2834 mach
= info
.bfd_arch_info
->mach
;
2836 tdep
= xmalloc (sizeof (struct gdbarch_tdep
));
2837 tdep
->wordsize
= wordsize
;
2839 /* For e500 executables, the apuinfo section is of help here. Such
2840 section contains the identifier and revision number of each
2841 Application-specific Processing Unit that is present on the
2842 chip. The content of the section is determined by the assembler
2843 which looks at each instruction and determines which unit (and
2844 which version of it) can execute it. In our case we just look for
2845 the existance of the section. */
2849 sect
= bfd_get_section_by_name (info
.abfd
, ".PPC.EMB.apuinfo");
2852 arch
= info
.bfd_arch_info
->arch
;
2853 mach
= bfd_mach_ppc_e500
;
2854 bfd_default_set_arch_mach (&abfd
, arch
, mach
);
2855 info
.bfd_arch_info
= bfd_get_arch_info (&abfd
);
2859 gdbarch
= gdbarch_alloc (&info
, tdep
);
2860 power
= arch
== bfd_arch_rs6000
;
2862 /* Initialize the number of real and pseudo registers in each variant. */
2865 /* Choose variant. */
2866 v
= find_variant_by_arch (arch
, mach
);
2870 tdep
->regs
= v
->regs
;
2872 tdep
->ppc_gp0_regnum
= 0;
2873 tdep
->ppc_toc_regnum
= 2;
2874 tdep
->ppc_ps_regnum
= 65;
2875 tdep
->ppc_cr_regnum
= 66;
2876 tdep
->ppc_lr_regnum
= 67;
2877 tdep
->ppc_ctr_regnum
= 68;
2878 tdep
->ppc_xer_regnum
= 69;
2879 if (v
->mach
== bfd_mach_ppc_601
)
2880 tdep
->ppc_mq_regnum
= 124;
2882 tdep
->ppc_mq_regnum
= 70;
2884 tdep
->ppc_mq_regnum
= -1;
2885 tdep
->ppc_fp0_regnum
= 32;
2886 tdep
->ppc_fpscr_regnum
= power
? 71 : 70;
2887 tdep
->ppc_vr0_regnum
= -1;
2888 tdep
->ppc_vrsave_regnum
= -1;
2889 tdep
->ppc_ev0_regnum
= -1;
2890 tdep
->ppc_ev31_regnum
= -1;
2891 tdep
->ppc_acc_regnum
= -1;
2892 tdep
->ppc_spefscr_regnum
= -1;
2894 set_gdbarch_pc_regnum (gdbarch
, 64);
2895 set_gdbarch_sp_regnum (gdbarch
, 1);
2896 set_gdbarch_deprecated_fp_regnum (gdbarch
, 1);
2897 if (sysv_abi
&& wordsize
== 8)
2898 set_gdbarch_return_value (gdbarch
, ppc64_sysv_abi_return_value
);
2899 else if (sysv_abi
&& wordsize
== 4)
2900 set_gdbarch_return_value (gdbarch
, ppc_sysv_abi_return_value
);
2903 set_gdbarch_deprecated_extract_return_value (gdbarch
, rs6000_extract_return_value
);
2904 set_gdbarch_store_return_value (gdbarch
, rs6000_store_return_value
);
2907 /* Set lr_frame_offset. */
2909 tdep
->lr_frame_offset
= 16;
2911 tdep
->lr_frame_offset
= 4;
2913 tdep
->lr_frame_offset
= 8;
2915 if (v
->arch
== bfd_arch_powerpc
)
2919 tdep
->ppc_vr0_regnum
= 71;
2920 tdep
->ppc_vrsave_regnum
= 104;
2922 case bfd_mach_ppc_7400
:
2923 tdep
->ppc_vr0_regnum
= 119;
2924 tdep
->ppc_vrsave_regnum
= 152;
2926 case bfd_mach_ppc_e500
:
2927 tdep
->ppc_gp0_regnum
= 41;
2928 tdep
->ppc_toc_regnum
= -1;
2929 tdep
->ppc_ps_regnum
= 1;
2930 tdep
->ppc_cr_regnum
= 2;
2931 tdep
->ppc_lr_regnum
= 3;
2932 tdep
->ppc_ctr_regnum
= 4;
2933 tdep
->ppc_xer_regnum
= 5;
2934 tdep
->ppc_ev0_regnum
= 7;
2935 tdep
->ppc_ev31_regnum
= 38;
2936 tdep
->ppc_fp0_regnum
= -1;
2937 tdep
->ppc_fpscr_regnum
= -1;
2938 tdep
->ppc_acc_regnum
= 39;
2939 tdep
->ppc_spefscr_regnum
= 40;
2940 set_gdbarch_pc_regnum (gdbarch
, 0);
2941 set_gdbarch_sp_regnum (gdbarch
, tdep
->ppc_gp0_regnum
+ 1);
2942 set_gdbarch_deprecated_fp_regnum (gdbarch
, tdep
->ppc_gp0_regnum
+ 1);
2943 set_gdbarch_pseudo_register_read (gdbarch
, e500_pseudo_register_read
);
2944 set_gdbarch_pseudo_register_write (gdbarch
, e500_pseudo_register_write
);
2948 /* Sanity check on registers. */
2949 gdb_assert (strcmp (tdep
->regs
[tdep
->ppc_gp0_regnum
].name
, "r0") == 0);
2951 /* Select instruction printer. */
2953 set_gdbarch_print_insn (gdbarch
, print_insn_rs6000
);
2955 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_powerpc
);
2957 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
2959 set_gdbarch_num_regs (gdbarch
, v
->nregs
);
2960 set_gdbarch_num_pseudo_regs (gdbarch
, v
->npregs
);
2961 set_gdbarch_register_name (gdbarch
, rs6000_register_name
);
2962 set_gdbarch_register_type (gdbarch
, rs6000_register_type
);
2964 set_gdbarch_ptr_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
2965 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
2966 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2967 set_gdbarch_long_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
2968 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2969 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2970 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2972 set_gdbarch_long_double_bit (gdbarch
, 16 * TARGET_CHAR_BIT
);
2974 set_gdbarch_long_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2975 set_gdbarch_char_signed (gdbarch
, 0);
2977 set_gdbarch_frame_align (gdbarch
, rs6000_frame_align
);
2978 if (sysv_abi
&& wordsize
== 8)
2980 set_gdbarch_frame_red_zone_size (gdbarch
, 288);
2981 else if (!sysv_abi
&& wordsize
== 4)
2982 /* PowerOpen / AIX 32 bit. The saved area or red zone consists of
2983 19 4 byte GPRS + 18 8 byte FPRs giving a total of 220 bytes.
2984 Problem is, 220 isn't frame (16 byte) aligned. Round it up to
2986 set_gdbarch_frame_red_zone_size (gdbarch
, 224);
2988 set_gdbarch_convert_register_p (gdbarch
, rs6000_convert_register_p
);
2989 set_gdbarch_register_to_value (gdbarch
, rs6000_register_to_value
);
2990 set_gdbarch_value_to_register (gdbarch
, rs6000_value_to_register
);
2992 set_gdbarch_stab_reg_to_regnum (gdbarch
, rs6000_stab_reg_to_regnum
);
2993 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, rs6000_dwarf2_reg_to_regnum
);
2994 /* Note: kevinb/2002-04-12: I'm not convinced that rs6000_push_arguments()
2995 is correct for the SysV ABI when the wordsize is 8, but I'm also
2996 fairly certain that ppc_sysv_abi_push_arguments() will give even
2997 worse results since it only works for 32-bit code. So, for the moment,
2998 we're better off calling rs6000_push_arguments() since it works for
2999 64-bit code. At some point in the future, this matter needs to be
3001 if (sysv_abi
&& wordsize
== 4)
3002 set_gdbarch_push_dummy_call (gdbarch
, ppc_sysv_abi_push_dummy_call
);
3003 else if (sysv_abi
&& wordsize
== 8)
3004 set_gdbarch_push_dummy_call (gdbarch
, ppc64_sysv_abi_push_dummy_call
);
3006 set_gdbarch_push_dummy_call (gdbarch
, rs6000_push_dummy_call
);
3008 set_gdbarch_deprecated_extract_struct_value_address (gdbarch
, rs6000_extract_struct_value_address
);
3010 set_gdbarch_skip_prologue (gdbarch
, rs6000_skip_prologue
);
3011 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3012 set_gdbarch_breakpoint_from_pc (gdbarch
, rs6000_breakpoint_from_pc
);
3014 /* Handle the 64-bit SVR4 minimal-symbol convention of using "FN"
3015 for the descriptor and ".FN" for the entry-point -- a user
3016 specifying "break FN" will unexpectedly end up with a breakpoint
3017 on the descriptor and not the function. This architecture method
3018 transforms any breakpoints on descriptors into breakpoints on the
3019 corresponding entry point. */
3020 if (sysv_abi
&& wordsize
== 8)
3021 set_gdbarch_adjust_breakpoint_address (gdbarch
, ppc64_sysv_abi_adjust_breakpoint_address
);
3023 /* Not sure on this. FIXMEmgo */
3024 set_gdbarch_frame_args_skip (gdbarch
, 8);
3027 set_gdbarch_use_struct_convention (gdbarch
,
3028 rs6000_use_struct_convention
);
3032 /* Handle RS/6000 function pointers (which are really function
3034 set_gdbarch_convert_from_func_ptr_addr (gdbarch
,
3035 rs6000_convert_from_func_ptr_addr
);
3038 /* Helpers for function argument information. */
3039 set_gdbarch_fetch_pointer_argument (gdbarch
, rs6000_fetch_pointer_argument
);
3041 /* Hook in ABI-specific overrides, if they have been registered. */
3042 gdbarch_init_osabi (info
, gdbarch
);
3046 case GDB_OSABI_NETBSD_AOUT
:
3047 case GDB_OSABI_NETBSD_ELF
:
3048 case GDB_OSABI_UNKNOWN
:
3049 case GDB_OSABI_LINUX
:
3050 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
3051 frame_unwind_append_sniffer (gdbarch
, rs6000_frame_sniffer
);
3052 set_gdbarch_unwind_dummy_id (gdbarch
, rs6000_unwind_dummy_id
);
3053 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
3056 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
3058 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
3059 frame_unwind_append_sniffer (gdbarch
, rs6000_frame_sniffer
);
3060 set_gdbarch_unwind_dummy_id (gdbarch
, rs6000_unwind_dummy_id
);
3061 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
3064 if (from_xcoff_exec
)
3066 /* NOTE: jimix/2003-06-09: This test should really check for
3067 GDB_OSABI_AIX when that is defined and becomes
3068 available. (Actually, once things are properly split apart,
3069 the test goes away.) */
3070 /* RS6000/AIX does not support PT_STEP. Has to be simulated. */
3071 set_gdbarch_software_single_step (gdbarch
, rs6000_software_single_step
);
3078 rs6000_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
3080 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3085 /* FIXME: Dump gdbarch_tdep. */
3088 static struct cmd_list_element
*info_powerpc_cmdlist
= NULL
;
3091 rs6000_info_powerpc_command (char *args
, int from_tty
)
3093 help_list (info_powerpc_cmdlist
, "info powerpc ", class_info
, gdb_stdout
);
3096 /* Initialization code. */
3098 extern initialize_file_ftype _initialize_rs6000_tdep
; /* -Wmissing-prototypes */
3101 _initialize_rs6000_tdep (void)
3103 gdbarch_register (bfd_arch_rs6000
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
3104 gdbarch_register (bfd_arch_powerpc
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
3106 /* Add root prefix command for "info powerpc" commands */
3107 add_prefix_cmd ("powerpc", class_info
, rs6000_info_powerpc_command
,
3108 "Various POWERPC info specific commands.",
3109 &info_powerpc_cmdlist
, "info powerpc ", 0, &infolist
);