1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
30 #include "arch-utils.h"
35 #include "parser-defs.h"
38 #include "sim-regno.h"
39 #include "gdb/sim-ppc.h"
40 #include "reggroups.h"
41 #include "dwarf2-frame.h"
42 #include "target-descriptions.h"
43 #include "user-regs.h"
45 #include "libbfd.h" /* for bfd_default_set_arch_mach */
46 #include "coff/internal.h" /* for libcoff.h */
47 #include "libcoff.h" /* for xcoff_data */
48 #include "coff/xcoff.h"
54 #include "solib-svr4.h"
57 #include "gdb_assert.h"
60 #include "trad-frame.h"
61 #include "frame-unwind.h"
62 #include "frame-base.h"
64 #include "rs6000-tdep.h"
66 #include "features/rs6000/powerpc-32.c"
67 #include "features/rs6000/powerpc-403.c"
68 #include "features/rs6000/powerpc-403gc.c"
69 #include "features/rs6000/powerpc-505.c"
70 #include "features/rs6000/powerpc-601.c"
71 #include "features/rs6000/powerpc-602.c"
72 #include "features/rs6000/powerpc-603.c"
73 #include "features/rs6000/powerpc-604.c"
74 #include "features/rs6000/powerpc-64.c"
75 #include "features/rs6000/powerpc-7400.c"
76 #include "features/rs6000/powerpc-750.c"
77 #include "features/rs6000/powerpc-860.c"
78 #include "features/rs6000/powerpc-e500.c"
79 #include "features/rs6000/rs6000.c"
81 /* The list of available "set powerpc ..." and "show powerpc ..."
83 static struct cmd_list_element
*setpowerpccmdlist
= NULL
;
84 static struct cmd_list_element
*showpowerpccmdlist
= NULL
;
86 static enum auto_boolean powerpc_soft_float_global
= AUTO_BOOLEAN_AUTO
;
88 /* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */
89 static const char *powerpc_vector_strings
[] =
98 /* A variable that can be configured by the user. */
99 static enum powerpc_vector_abi powerpc_vector_abi_global
= POWERPC_VEC_AUTO
;
100 static const char *powerpc_vector_abi_string
= "auto";
102 /* If the kernel has to deliver a signal, it pushes a sigcontext
103 structure on the stack and then calls the signal handler, passing
104 the address of the sigcontext in an argument register. Usually
105 the signal handler doesn't save this register, so we have to
106 access the sigcontext structure via an offset from the signal handler
108 The following constants were determined by experimentation on AIX 3.2. */
109 #define SIG_FRAME_PC_OFFSET 96
110 #define SIG_FRAME_LR_OFFSET 108
111 #define SIG_FRAME_FP_OFFSET 284
113 /* To be used by skip_prologue. */
115 struct rs6000_framedata
117 int offset
; /* total size of frame --- the distance
118 by which we decrement sp to allocate
120 int saved_gpr
; /* smallest # of saved gpr */
121 int saved_fpr
; /* smallest # of saved fpr */
122 int saved_vr
; /* smallest # of saved vr */
123 int saved_ev
; /* smallest # of saved ev */
124 int alloca_reg
; /* alloca register number (frame ptr) */
125 char frameless
; /* true if frameless functions. */
126 char nosavedpc
; /* true if pc not saved. */
127 int gpr_offset
; /* offset of saved gprs from prev sp */
128 int fpr_offset
; /* offset of saved fprs from prev sp */
129 int vr_offset
; /* offset of saved vrs from prev sp */
130 int ev_offset
; /* offset of saved evs from prev sp */
131 int lr_offset
; /* offset of saved lr */
132 int cr_offset
; /* offset of saved cr */
133 int vrsave_offset
; /* offset of saved vrsave register */
136 /* Description of a single register. */
140 char *name
; /* name of register */
141 unsigned char sz32
; /* size on 32-bit arch, 0 if nonexistent */
142 unsigned char sz64
; /* size on 64-bit arch, 0 if nonexistent */
143 unsigned char fpr
; /* whether register is floating-point */
144 unsigned char pseudo
; /* whether register is pseudo */
145 int spr_num
; /* PowerPC SPR number, or -1 if not an SPR.
146 This is an ISA SPR number, not a GDB
150 /* Hook for determining the TOC address when calling functions in the
151 inferior under AIX. The initialization code in rs6000-nat.c sets
152 this hook to point to find_toc_address. */
154 CORE_ADDR (*rs6000_find_toc_address_hook
) (CORE_ADDR
) = NULL
;
156 /* Static function prototypes */
158 static CORE_ADDR
branch_dest (struct frame_info
*frame
, int opcode
,
159 int instr
, CORE_ADDR pc
, CORE_ADDR safety
);
160 static CORE_ADDR
skip_prologue (struct gdbarch
*, CORE_ADDR
, CORE_ADDR
,
161 struct rs6000_framedata
*);
163 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
165 altivec_register_p (struct gdbarch
*gdbarch
, int regno
)
167 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
168 if (tdep
->ppc_vr0_regnum
< 0 || tdep
->ppc_vrsave_regnum
< 0)
171 return (regno
>= tdep
->ppc_vr0_regnum
&& regno
<= tdep
->ppc_vrsave_regnum
);
175 /* Return true if REGNO is an SPE register, false otherwise. */
177 spe_register_p (struct gdbarch
*gdbarch
, int regno
)
179 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
181 /* Is it a reference to EV0 -- EV31, and do we have those? */
182 if (tdep
->ppc_ev0_regnum
>= 0
183 && tdep
->ppc_ev31_regnum
>= 0
184 && tdep
->ppc_ev0_regnum
<= regno
&& regno
<= tdep
->ppc_ev31_regnum
)
187 /* Is it a reference to one of the raw upper GPR halves? */
188 if (tdep
->ppc_ev0_upper_regnum
>= 0
189 && tdep
->ppc_ev0_upper_regnum
<= regno
190 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
193 /* Is it a reference to the 64-bit accumulator, and do we have that? */
194 if (tdep
->ppc_acc_regnum
>= 0
195 && tdep
->ppc_acc_regnum
== regno
)
198 /* Is it a reference to the SPE floating-point status and control register,
199 and do we have that? */
200 if (tdep
->ppc_spefscr_regnum
>= 0
201 && tdep
->ppc_spefscr_regnum
== regno
)
208 /* Return non-zero if the architecture described by GDBARCH has
209 floating-point registers (f0 --- f31 and fpscr). */
211 ppc_floating_point_unit_p (struct gdbarch
*gdbarch
)
213 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
215 return (tdep
->ppc_fp0_regnum
>= 0
216 && tdep
->ppc_fpscr_regnum
>= 0);
219 /* Return non-zero if the architecture described by GDBARCH has
220 Altivec registers (vr0 --- vr31, vrsave and vscr). */
222 ppc_altivec_support_p (struct gdbarch
*gdbarch
)
224 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
226 return (tdep
->ppc_vr0_regnum
>= 0
227 && tdep
->ppc_vrsave_regnum
>= 0);
230 /* Check that TABLE[GDB_REGNO] is not already initialized, and then
233 This is a helper function for init_sim_regno_table, constructing
234 the table mapping GDB register numbers to sim register numbers; we
235 initialize every element in that table to -1 before we start
238 set_sim_regno (int *table
, int gdb_regno
, int sim_regno
)
240 /* Make sure we don't try to assign any given GDB register a sim
241 register number more than once. */
242 gdb_assert (table
[gdb_regno
] == -1);
243 table
[gdb_regno
] = sim_regno
;
247 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
248 numbers to simulator register numbers, based on the values placed
249 in the ARCH->tdep->ppc_foo_regnum members. */
251 init_sim_regno_table (struct gdbarch
*arch
)
253 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
254 int total_regs
= gdbarch_num_regs (arch
);
255 int *sim_regno
= GDBARCH_OBSTACK_CALLOC (arch
, total_regs
, int);
257 static const char *const segment_regs
[] = {
258 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
259 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
262 /* Presume that all registers not explicitly mentioned below are
263 unavailable from the sim. */
264 for (i
= 0; i
< total_regs
; i
++)
267 /* General-purpose registers. */
268 for (i
= 0; i
< ppc_num_gprs
; i
++)
269 set_sim_regno (sim_regno
, tdep
->ppc_gp0_regnum
+ i
, sim_ppc_r0_regnum
+ i
);
271 /* Floating-point registers. */
272 if (tdep
->ppc_fp0_regnum
>= 0)
273 for (i
= 0; i
< ppc_num_fprs
; i
++)
274 set_sim_regno (sim_regno
,
275 tdep
->ppc_fp0_regnum
+ i
,
276 sim_ppc_f0_regnum
+ i
);
277 if (tdep
->ppc_fpscr_regnum
>= 0)
278 set_sim_regno (sim_regno
, tdep
->ppc_fpscr_regnum
, sim_ppc_fpscr_regnum
);
280 set_sim_regno (sim_regno
, gdbarch_pc_regnum (arch
), sim_ppc_pc_regnum
);
281 set_sim_regno (sim_regno
, tdep
->ppc_ps_regnum
, sim_ppc_ps_regnum
);
282 set_sim_regno (sim_regno
, tdep
->ppc_cr_regnum
, sim_ppc_cr_regnum
);
284 /* Segment registers. */
285 for (i
= 0; i
< ppc_num_srs
; i
++)
289 gdb_regno
= user_reg_map_name_to_regnum (arch
, segment_regs
[i
], -1);
291 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_sr0_regnum
+ i
);
294 /* Altivec registers. */
295 if (tdep
->ppc_vr0_regnum
>= 0)
297 for (i
= 0; i
< ppc_num_vrs
; i
++)
298 set_sim_regno (sim_regno
,
299 tdep
->ppc_vr0_regnum
+ i
,
300 sim_ppc_vr0_regnum
+ i
);
302 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
303 we can treat this more like the other cases. */
304 set_sim_regno (sim_regno
,
305 tdep
->ppc_vr0_regnum
+ ppc_num_vrs
,
306 sim_ppc_vscr_regnum
);
308 /* vsave is a special-purpose register, so the code below handles it. */
310 /* SPE APU (E500) registers. */
311 if (tdep
->ppc_ev0_upper_regnum
>= 0)
312 for (i
= 0; i
< ppc_num_gprs
; i
++)
313 set_sim_regno (sim_regno
,
314 tdep
->ppc_ev0_upper_regnum
+ i
,
315 sim_ppc_rh0_regnum
+ i
);
316 if (tdep
->ppc_acc_regnum
>= 0)
317 set_sim_regno (sim_regno
, tdep
->ppc_acc_regnum
, sim_ppc_acc_regnum
);
318 /* spefscr is a special-purpose register, so the code below handles it. */
321 /* Now handle all special-purpose registers. Verify that they
322 haven't mistakenly been assigned numbers by any of the above
324 for (i
= 0; i
< sim_ppc_num_sprs
; i
++)
326 const char *spr_name
= sim_spr_register_name (i
);
329 if (spr_name
!= NULL
)
330 gdb_regno
= user_reg_map_name_to_regnum (arch
, spr_name
, -1);
333 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_spr0_regnum
+ i
);
337 /* Drop the initialized array into place. */
338 tdep
->sim_regno
= sim_regno
;
342 /* Given a GDB register number REG, return the corresponding SIM
345 rs6000_register_sim_regno (struct gdbarch
*gdbarch
, int reg
)
347 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
350 if (tdep
->sim_regno
== NULL
)
351 init_sim_regno_table (gdbarch
);
354 && reg
<= gdbarch_num_regs (gdbarch
)
355 + gdbarch_num_pseudo_regs (gdbarch
));
356 sim_regno
= tdep
->sim_regno
[reg
];
361 return LEGACY_SIM_REGNO_IGNORE
;
366 /* Register set support functions. */
368 /* REGS + OFFSET contains register REGNUM in a field REGSIZE wide.
369 Write the register to REGCACHE. */
372 ppc_supply_reg (struct regcache
*regcache
, int regnum
,
373 const gdb_byte
*regs
, size_t offset
, int regsize
)
375 if (regnum
!= -1 && offset
!= -1)
379 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
380 int gdb_regsize
= register_size (gdbarch
, regnum
);
381 if (gdb_regsize
< regsize
382 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
383 offset
+= regsize
- gdb_regsize
;
385 regcache_raw_supply (regcache
, regnum
, regs
+ offset
);
389 /* Read register REGNUM from REGCACHE and store to REGS + OFFSET
390 in a field REGSIZE wide. Zero pad as necessary. */
393 ppc_collect_reg (const struct regcache
*regcache
, int regnum
,
394 gdb_byte
*regs
, size_t offset
, int regsize
)
396 if (regnum
!= -1 && offset
!= -1)
400 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
401 int gdb_regsize
= register_size (gdbarch
, regnum
);
402 if (gdb_regsize
< regsize
)
404 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
406 memset (regs
+ offset
, 0, regsize
- gdb_regsize
);
407 offset
+= regsize
- gdb_regsize
;
410 memset (regs
+ offset
+ regsize
- gdb_regsize
, 0,
411 regsize
- gdb_regsize
);
414 regcache_raw_collect (regcache
, regnum
, regs
+ offset
);
419 ppc_greg_offset (struct gdbarch
*gdbarch
,
420 struct gdbarch_tdep
*tdep
,
421 const struct ppc_reg_offsets
*offsets
,
425 *regsize
= offsets
->gpr_size
;
426 if (regnum
>= tdep
->ppc_gp0_regnum
427 && regnum
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
)
428 return (offsets
->r0_offset
429 + (regnum
- tdep
->ppc_gp0_regnum
) * offsets
->gpr_size
);
431 if (regnum
== gdbarch_pc_regnum (gdbarch
))
432 return offsets
->pc_offset
;
434 if (regnum
== tdep
->ppc_ps_regnum
)
435 return offsets
->ps_offset
;
437 if (regnum
== tdep
->ppc_lr_regnum
)
438 return offsets
->lr_offset
;
440 if (regnum
== tdep
->ppc_ctr_regnum
)
441 return offsets
->ctr_offset
;
443 *regsize
= offsets
->xr_size
;
444 if (regnum
== tdep
->ppc_cr_regnum
)
445 return offsets
->cr_offset
;
447 if (regnum
== tdep
->ppc_xer_regnum
)
448 return offsets
->xer_offset
;
450 if (regnum
== tdep
->ppc_mq_regnum
)
451 return offsets
->mq_offset
;
457 ppc_fpreg_offset (struct gdbarch_tdep
*tdep
,
458 const struct ppc_reg_offsets
*offsets
,
461 if (regnum
>= tdep
->ppc_fp0_regnum
462 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
)
463 return offsets
->f0_offset
+ (regnum
- tdep
->ppc_fp0_regnum
) * 8;
465 if (regnum
== tdep
->ppc_fpscr_regnum
)
466 return offsets
->fpscr_offset
;
472 ppc_vrreg_offset (struct gdbarch_tdep
*tdep
,
473 const struct ppc_reg_offsets
*offsets
,
476 if (regnum
>= tdep
->ppc_vr0_regnum
477 && regnum
< tdep
->ppc_vr0_regnum
+ ppc_num_vrs
)
478 return offsets
->vr0_offset
+ (regnum
- tdep
->ppc_vr0_regnum
) * 16;
480 if (regnum
== tdep
->ppc_vrsave_regnum
- 1)
481 return offsets
->vscr_offset
;
483 if (regnum
== tdep
->ppc_vrsave_regnum
)
484 return offsets
->vrsave_offset
;
489 /* Supply register REGNUM in the general-purpose register set REGSET
490 from the buffer specified by GREGS and LEN to register cache
491 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
494 ppc_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
495 int regnum
, const void *gregs
, size_t len
)
497 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
498 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
499 const struct ppc_reg_offsets
*offsets
= regset
->descr
;
506 int gpr_size
= offsets
->gpr_size
;
508 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
509 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
510 i
++, offset
+= gpr_size
)
511 ppc_supply_reg (regcache
, i
, gregs
, offset
, gpr_size
);
513 ppc_supply_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
514 gregs
, offsets
->pc_offset
, gpr_size
);
515 ppc_supply_reg (regcache
, tdep
->ppc_ps_regnum
,
516 gregs
, offsets
->ps_offset
, gpr_size
);
517 ppc_supply_reg (regcache
, tdep
->ppc_lr_regnum
,
518 gregs
, offsets
->lr_offset
, gpr_size
);
519 ppc_supply_reg (regcache
, tdep
->ppc_ctr_regnum
,
520 gregs
, offsets
->ctr_offset
, gpr_size
);
521 ppc_supply_reg (regcache
, tdep
->ppc_cr_regnum
,
522 gregs
, offsets
->cr_offset
, offsets
->xr_size
);
523 ppc_supply_reg (regcache
, tdep
->ppc_xer_regnum
,
524 gregs
, offsets
->xer_offset
, offsets
->xr_size
);
525 ppc_supply_reg (regcache
, tdep
->ppc_mq_regnum
,
526 gregs
, offsets
->mq_offset
, offsets
->xr_size
);
530 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
531 ppc_supply_reg (regcache
, regnum
, gregs
, offset
, regsize
);
534 /* Supply register REGNUM in the floating-point register set REGSET
535 from the buffer specified by FPREGS and LEN to register cache
536 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
539 ppc_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
540 int regnum
, const void *fpregs
, size_t len
)
542 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
543 struct gdbarch_tdep
*tdep
;
544 const struct ppc_reg_offsets
*offsets
;
547 if (!ppc_floating_point_unit_p (gdbarch
))
550 tdep
= gdbarch_tdep (gdbarch
);
551 offsets
= regset
->descr
;
556 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
557 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
559 ppc_supply_reg (regcache
, i
, fpregs
, offset
, 8);
561 ppc_supply_reg (regcache
, tdep
->ppc_fpscr_regnum
,
562 fpregs
, offsets
->fpscr_offset
, offsets
->fpscr_size
);
566 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
567 ppc_supply_reg (regcache
, regnum
, fpregs
, offset
,
568 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
571 /* Supply register REGNUM in the Altivec register set REGSET
572 from the buffer specified by VRREGS and LEN to register cache
573 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
576 ppc_supply_vrregset (const struct regset
*regset
, struct regcache
*regcache
,
577 int regnum
, const void *vrregs
, size_t len
)
579 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
580 struct gdbarch_tdep
*tdep
;
581 const struct ppc_reg_offsets
*offsets
;
584 if (!ppc_altivec_support_p (gdbarch
))
587 tdep
= gdbarch_tdep (gdbarch
);
588 offsets
= regset
->descr
;
593 for (i
= tdep
->ppc_vr0_regnum
, offset
= offsets
->vr0_offset
;
594 i
< tdep
->ppc_vr0_regnum
+ ppc_num_vrs
;
596 ppc_supply_reg (regcache
, i
, vrregs
, offset
, 16);
598 ppc_supply_reg (regcache
, (tdep
->ppc_vrsave_regnum
- 1),
599 vrregs
, offsets
->vscr_offset
, 4);
601 ppc_supply_reg (regcache
, tdep
->ppc_vrsave_regnum
,
602 vrregs
, offsets
->vrsave_offset
, 4);
606 offset
= ppc_vrreg_offset (tdep
, offsets
, regnum
);
607 if (regnum
!= tdep
->ppc_vrsave_regnum
608 && regnum
!= tdep
->ppc_vrsave_regnum
- 1)
609 ppc_supply_reg (regcache
, regnum
, vrregs
, offset
, 16);
611 ppc_supply_reg (regcache
, regnum
,
615 /* Collect register REGNUM in the general-purpose register set
616 REGSET from register cache REGCACHE into the buffer specified by
617 GREGS and LEN. If REGNUM is -1, do this for all registers in
621 ppc_collect_gregset (const struct regset
*regset
,
622 const struct regcache
*regcache
,
623 int regnum
, void *gregs
, size_t len
)
625 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
626 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
627 const struct ppc_reg_offsets
*offsets
= regset
->descr
;
634 int gpr_size
= offsets
->gpr_size
;
636 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
637 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
638 i
++, offset
+= gpr_size
)
639 ppc_collect_reg (regcache
, i
, gregs
, offset
, gpr_size
);
641 ppc_collect_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
642 gregs
, offsets
->pc_offset
, gpr_size
);
643 ppc_collect_reg (regcache
, tdep
->ppc_ps_regnum
,
644 gregs
, offsets
->ps_offset
, gpr_size
);
645 ppc_collect_reg (regcache
, tdep
->ppc_lr_regnum
,
646 gregs
, offsets
->lr_offset
, gpr_size
);
647 ppc_collect_reg (regcache
, tdep
->ppc_ctr_regnum
,
648 gregs
, offsets
->ctr_offset
, gpr_size
);
649 ppc_collect_reg (regcache
, tdep
->ppc_cr_regnum
,
650 gregs
, offsets
->cr_offset
, offsets
->xr_size
);
651 ppc_collect_reg (regcache
, tdep
->ppc_xer_regnum
,
652 gregs
, offsets
->xer_offset
, offsets
->xr_size
);
653 ppc_collect_reg (regcache
, tdep
->ppc_mq_regnum
,
654 gregs
, offsets
->mq_offset
, offsets
->xr_size
);
658 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
659 ppc_collect_reg (regcache
, regnum
, gregs
, offset
, regsize
);
662 /* Collect register REGNUM in the floating-point register set
663 REGSET from register cache REGCACHE into the buffer specified by
664 FPREGS and LEN. If REGNUM is -1, do this for all registers in
668 ppc_collect_fpregset (const struct regset
*regset
,
669 const struct regcache
*regcache
,
670 int regnum
, void *fpregs
, size_t len
)
672 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
673 struct gdbarch_tdep
*tdep
;
674 const struct ppc_reg_offsets
*offsets
;
677 if (!ppc_floating_point_unit_p (gdbarch
))
680 tdep
= gdbarch_tdep (gdbarch
);
681 offsets
= regset
->descr
;
686 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
687 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
689 ppc_collect_reg (regcache
, i
, fpregs
, offset
, 8);
691 ppc_collect_reg (regcache
, tdep
->ppc_fpscr_regnum
,
692 fpregs
, offsets
->fpscr_offset
, offsets
->fpscr_size
);
696 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
697 ppc_collect_reg (regcache
, regnum
, fpregs
, offset
,
698 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
701 /* Collect register REGNUM in the Altivec register set
702 REGSET from register cache REGCACHE into the buffer specified by
703 VRREGS and LEN. If REGNUM is -1, do this for all registers in
707 ppc_collect_vrregset (const struct regset
*regset
,
708 const struct regcache
*regcache
,
709 int regnum
, void *vrregs
, size_t len
)
711 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
712 struct gdbarch_tdep
*tdep
;
713 const struct ppc_reg_offsets
*offsets
;
716 if (!ppc_altivec_support_p (gdbarch
))
719 tdep
= gdbarch_tdep (gdbarch
);
720 offsets
= regset
->descr
;
725 for (i
= tdep
->ppc_vr0_regnum
, offset
= offsets
->vr0_offset
;
726 i
< tdep
->ppc_vr0_regnum
+ ppc_num_vrs
;
728 ppc_collect_reg (regcache
, i
, vrregs
, offset
, 16);
730 ppc_collect_reg (regcache
, (tdep
->ppc_vrsave_regnum
- 1),
731 vrregs
, offsets
->vscr_offset
, 4);
733 ppc_collect_reg (regcache
, tdep
->ppc_vrsave_regnum
,
734 vrregs
, offsets
->vrsave_offset
, 4);
738 offset
= ppc_vrreg_offset (tdep
, offsets
, regnum
);
739 if (regnum
!= tdep
->ppc_vrsave_regnum
740 && regnum
!= tdep
->ppc_vrsave_regnum
- 1)
741 ppc_collect_reg (regcache
, regnum
, vrregs
, offset
, 16);
743 ppc_collect_reg (regcache
, regnum
,
748 /* Read a LEN-byte address from debugged memory address MEMADDR. */
751 read_memory_addr (CORE_ADDR memaddr
, int len
)
753 return read_memory_unsigned_integer (memaddr
, len
);
757 rs6000_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
759 struct rs6000_framedata frame
;
760 CORE_ADDR limit_pc
, func_addr
;
762 /* See if we can determine the end of the prologue via the symbol table.
763 If so, then return either PC, or the PC after the prologue, whichever
765 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
767 CORE_ADDR post_prologue_pc
= skip_prologue_using_sal (func_addr
);
768 if (post_prologue_pc
!= 0)
769 return max (pc
, post_prologue_pc
);
772 /* Can't determine prologue from the symbol table, need to examine
775 /* Find an upper limit on the function prologue using the debug
776 information. If the debug information could not be used to provide
777 that bound, then use an arbitrary large number as the upper bound. */
778 limit_pc
= skip_prologue_using_sal (pc
);
780 limit_pc
= pc
+ 100; /* Magic. */
782 pc
= skip_prologue (gdbarch
, pc
, limit_pc
, &frame
);
787 insn_changes_sp_or_jumps (unsigned long insn
)
789 int opcode
= (insn
>> 26) & 0x03f;
790 int sd
= (insn
>> 21) & 0x01f;
791 int a
= (insn
>> 16) & 0x01f;
792 int subcode
= (insn
>> 1) & 0x3ff;
794 /* Changes the stack pointer. */
796 /* NOTE: There are many ways to change the value of a given register.
797 The ways below are those used when the register is R1, the SP,
798 in a funtion's epilogue. */
800 if (opcode
== 31 && subcode
== 444 && a
== 1)
801 return 1; /* mr R1,Rn */
802 if (opcode
== 14 && sd
== 1)
803 return 1; /* addi R1,Rn,simm */
804 if (opcode
== 58 && sd
== 1)
805 return 1; /* ld R1,ds(Rn) */
807 /* Transfers control. */
813 if (opcode
== 19 && subcode
== 16)
815 if (opcode
== 19 && subcode
== 528)
816 return 1; /* bcctr */
821 /* Return true if we are in the function's epilogue, i.e. after the
822 instruction that destroyed the function's stack frame.
824 1) scan forward from the point of execution:
825 a) If you find an instruction that modifies the stack pointer
826 or transfers control (except a return), execution is not in
828 b) Stop scanning if you find a return instruction or reach the
829 end of the function or reach the hard limit for the size of
831 2) scan backward from the point of execution:
832 a) If you find an instruction that modifies the stack pointer,
833 execution *is* in an epilogue, return.
834 b) Stop scanning if you reach an instruction that transfers
835 control or the beginning of the function or reach the hard
836 limit for the size of an epilogue. */
839 rs6000_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
841 bfd_byte insn_buf
[PPC_INSN_SIZE
];
842 CORE_ADDR scan_pc
, func_start
, func_end
, epilogue_start
, epilogue_end
;
844 struct frame_info
*curfrm
;
846 /* Find the search limits based on function boundaries and hard limit. */
848 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
851 epilogue_start
= pc
- PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
852 if (epilogue_start
< func_start
) epilogue_start
= func_start
;
854 epilogue_end
= pc
+ PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
855 if (epilogue_end
> func_end
) epilogue_end
= func_end
;
857 curfrm
= get_current_frame ();
859 /* Scan forward until next 'blr'. */
861 for (scan_pc
= pc
; scan_pc
< epilogue_end
; scan_pc
+= PPC_INSN_SIZE
)
863 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
865 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
);
866 if (insn
== 0x4e800020)
868 if (insn_changes_sp_or_jumps (insn
))
872 /* Scan backward until adjustment to stack pointer (R1). */
874 for (scan_pc
= pc
- PPC_INSN_SIZE
;
875 scan_pc
>= epilogue_start
;
876 scan_pc
-= PPC_INSN_SIZE
)
878 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
880 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
);
881 if (insn_changes_sp_or_jumps (insn
))
888 /* Get the ith function argument for the current function. */
890 rs6000_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
893 return get_frame_register_unsigned (frame
, 3 + argi
);
896 /* Calculate the destination of a branch/jump. Return -1 if not a branch. */
899 branch_dest (struct frame_info
*frame
, int opcode
, int instr
,
900 CORE_ADDR pc
, CORE_ADDR safety
)
902 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (frame
));
908 absolute
= (int) ((instr
>> 1) & 1);
913 immediate
= ((instr
& ~3) << 6) >> 6; /* br unconditional */
917 dest
= pc
+ immediate
;
921 immediate
= ((instr
& ~3) << 16) >> 16; /* br conditional */
925 dest
= pc
+ immediate
;
929 ext_op
= (instr
>> 1) & 0x3ff;
931 if (ext_op
== 16) /* br conditional register */
933 dest
= get_frame_register_unsigned (frame
, tdep
->ppc_lr_regnum
) & ~3;
935 /* If we are about to return from a signal handler, dest is
936 something like 0x3c90. The current frame is a signal handler
937 caller frame, upon completion of the sigreturn system call
938 execution will return to the saved PC in the frame. */
939 if (dest
< tdep
->text_segment_base
)
940 dest
= read_memory_addr (get_frame_base (frame
) + SIG_FRAME_PC_OFFSET
,
944 else if (ext_op
== 528) /* br cond to count reg */
946 dest
= get_frame_register_unsigned (frame
, tdep
->ppc_ctr_regnum
) & ~3;
948 /* If we are about to execute a system call, dest is something
949 like 0x22fc or 0x3b00. Upon completion the system call
950 will return to the address in the link register. */
951 if (dest
< tdep
->text_segment_base
)
952 dest
= get_frame_register_unsigned (frame
, tdep
->ppc_lr_regnum
) & ~3;
961 return (dest
< tdep
->text_segment_base
) ? safety
: dest
;
965 /* Sequence of bytes for breakpoint instruction. */
967 const static unsigned char *
968 rs6000_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*bp_addr
,
971 static unsigned char big_breakpoint
[] = { 0x7d, 0x82, 0x10, 0x08 };
972 static unsigned char little_breakpoint
[] = { 0x08, 0x10, 0x82, 0x7d };
974 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
975 return big_breakpoint
;
977 return little_breakpoint
;
981 /* Instruction masks used during single-stepping of atomic sequences. */
982 #define LWARX_MASK 0xfc0007fe
983 #define LWARX_INSTRUCTION 0x7c000028
984 #define LDARX_INSTRUCTION 0x7c0000A8
985 #define STWCX_MASK 0xfc0007ff
986 #define STWCX_INSTRUCTION 0x7c00012d
987 #define STDCX_INSTRUCTION 0x7c0001ad
988 #define BC_MASK 0xfc000000
989 #define BC_INSTRUCTION 0x40000000
991 /* Checks for an atomic sequence of instructions beginning with a LWARX/LDARX
992 instruction and ending with a STWCX/STDCX instruction. If such a sequence
993 is found, attempt to step through it. A breakpoint is placed at the end of
997 deal_with_atomic_sequence (struct frame_info
*frame
)
999 CORE_ADDR pc
= get_frame_pc (frame
);
1000 CORE_ADDR breaks
[2] = {-1, -1};
1002 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
1003 CORE_ADDR closing_insn
; /* Instruction that closes the atomic sequence. */
1004 int insn
= read_memory_integer (loc
, PPC_INSN_SIZE
);
1007 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
1008 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
1009 int opcode
; /* Branch instruction's OPcode. */
1010 int bc_insn_count
= 0; /* Conditional branch instruction count. */
1012 /* Assume all atomic sequences start with a lwarx/ldarx instruction. */
1013 if ((insn
& LWARX_MASK
) != LWARX_INSTRUCTION
1014 && (insn
& LWARX_MASK
) != LDARX_INSTRUCTION
)
1017 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
1019 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
1021 loc
+= PPC_INSN_SIZE
;
1022 insn
= read_memory_integer (loc
, PPC_INSN_SIZE
);
1024 /* Assume that there is at most one conditional branch in the atomic
1025 sequence. If a conditional branch is found, put a breakpoint in
1026 its destination address. */
1027 if ((insn
& BC_MASK
) == BC_INSTRUCTION
)
1029 if (bc_insn_count
>= 1)
1030 return 0; /* More than one conditional branch found, fallback
1031 to the standard single-step code. */
1033 opcode
= insn
>> 26;
1034 branch_bp
= branch_dest (frame
, opcode
, insn
, pc
, breaks
[0]);
1036 if (branch_bp
!= -1)
1038 breaks
[1] = branch_bp
;
1044 if ((insn
& STWCX_MASK
) == STWCX_INSTRUCTION
1045 || (insn
& STWCX_MASK
) == STDCX_INSTRUCTION
)
1049 /* Assume that the atomic sequence ends with a stwcx/stdcx instruction. */
1050 if ((insn
& STWCX_MASK
) != STWCX_INSTRUCTION
1051 && (insn
& STWCX_MASK
) != STDCX_INSTRUCTION
)
1055 loc
+= PPC_INSN_SIZE
;
1056 insn
= read_memory_integer (loc
, PPC_INSN_SIZE
);
1058 /* Insert a breakpoint right after the end of the atomic sequence. */
1061 /* Check for duplicated breakpoints. Check also for a breakpoint
1062 placed (branch instruction's destination) at the stwcx/stdcx
1063 instruction, this resets the reservation and take us back to the
1064 lwarx/ldarx instruction at the beginning of the atomic sequence. */
1065 if (last_breakpoint
&& ((breaks
[1] == breaks
[0])
1066 || (breaks
[1] == closing_insn
)))
1067 last_breakpoint
= 0;
1069 /* Effectively inserts the breakpoints. */
1070 for (index
= 0; index
<= last_breakpoint
; index
++)
1071 insert_single_step_breakpoint (breaks
[index
]);
1076 /* AIX does not support PT_STEP. Simulate it. */
1079 rs6000_software_single_step (struct frame_info
*frame
)
1083 const gdb_byte
*breakp
1084 = rs6000_breakpoint_from_pc (get_frame_arch (frame
), &dummy
, &breakp_sz
);
1087 CORE_ADDR breaks
[2];
1090 loc
= get_frame_pc (frame
);
1092 insn
= read_memory_integer (loc
, 4);
1094 if (deal_with_atomic_sequence (frame
))
1097 breaks
[0] = loc
+ breakp_sz
;
1098 opcode
= insn
>> 26;
1099 breaks
[1] = branch_dest (frame
, opcode
, insn
, loc
, breaks
[0]);
1101 /* Don't put two breakpoints on the same address. */
1102 if (breaks
[1] == breaks
[0])
1105 for (ii
= 0; ii
< 2; ++ii
)
1107 /* ignore invalid breakpoint. */
1108 if (breaks
[ii
] == -1)
1110 insert_single_step_breakpoint (breaks
[ii
]);
1113 errno
= 0; /* FIXME, don't ignore errors! */
1114 /* What errors? {read,write}_memory call error(). */
1119 #define SIGNED_SHORT(x) \
1120 ((sizeof (short) == 2) \
1121 ? ((int)(short)(x)) \
1122 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
1124 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
1126 /* Limit the number of skipped non-prologue instructions, as the examining
1127 of the prologue is expensive. */
1128 static int max_skip_non_prologue_insns
= 10;
1130 /* Return nonzero if the given instruction OP can be part of the prologue
1131 of a function and saves a parameter on the stack. FRAMEP should be
1132 set if one of the previous instructions in the function has set the
1136 store_param_on_stack_p (unsigned long op
, int framep
, int *r0_contains_arg
)
1138 /* Move parameters from argument registers to temporary register. */
1139 if ((op
& 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
1141 /* Rx must be scratch register r0. */
1142 const int rx_regno
= (op
>> 16) & 31;
1143 /* Ry: Only r3 - r10 are used for parameter passing. */
1144 const int ry_regno
= GET_SRC_REG (op
);
1146 if (rx_regno
== 0 && ry_regno
>= 3 && ry_regno
<= 10)
1148 *r0_contains_arg
= 1;
1155 /* Save a General Purpose Register on stack. */
1157 if ((op
& 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
1158 (op
& 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
1160 /* Rx: Only r3 - r10 are used for parameter passing. */
1161 const int rx_regno
= GET_SRC_REG (op
);
1163 return (rx_regno
>= 3 && rx_regno
<= 10);
1166 /* Save a General Purpose Register on stack via the Frame Pointer. */
1169 ((op
& 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
1170 (op
& 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
1171 (op
& 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
1173 /* Rx: Usually, only r3 - r10 are used for parameter passing.
1174 However, the compiler sometimes uses r0 to hold an argument. */
1175 const int rx_regno
= GET_SRC_REG (op
);
1177 return ((rx_regno
>= 3 && rx_regno
<= 10)
1178 || (rx_regno
== 0 && *r0_contains_arg
));
1181 if ((op
& 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
1183 /* Only f2 - f8 are used for parameter passing. */
1184 const int src_regno
= GET_SRC_REG (op
);
1186 return (src_regno
>= 2 && src_regno
<= 8);
1189 if (framep
&& ((op
& 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
1191 /* Only f2 - f8 are used for parameter passing. */
1192 const int src_regno
= GET_SRC_REG (op
);
1194 return (src_regno
>= 2 && src_regno
<= 8);
1197 /* Not an insn that saves a parameter on stack. */
1201 /* Assuming that INSN is a "bl" instruction located at PC, return
1202 nonzero if the destination of the branch is a "blrl" instruction.
1204 This sequence is sometimes found in certain function prologues.
1205 It allows the function to load the LR register with a value that
1206 they can use to access PIC data using PC-relative offsets. */
1209 bl_to_blrl_insn_p (CORE_ADDR pc
, int insn
)
1216 absolute
= (int) ((insn
>> 1) & 1);
1217 immediate
= ((insn
& ~3) << 6) >> 6;
1221 dest
= pc
+ immediate
;
1223 dest_insn
= read_memory_integer (dest
, 4);
1224 if ((dest_insn
& 0xfc00ffff) == 0x4c000021) /* blrl */
1230 /* return pc value after skipping a function prologue and also return
1231 information about a function frame.
1233 in struct rs6000_framedata fdata:
1234 - frameless is TRUE, if function does not have a frame.
1235 - nosavedpc is TRUE, if function does not save %pc value in its frame.
1236 - offset is the initial size of this stack frame --- the amount by
1237 which we decrement the sp to allocate the frame.
1238 - saved_gpr is the number of the first saved gpr.
1239 - saved_fpr is the number of the first saved fpr.
1240 - saved_vr is the number of the first saved vr.
1241 - saved_ev is the number of the first saved ev.
1242 - alloca_reg is the number of the register used for alloca() handling.
1244 - gpr_offset is the offset of the first saved gpr from the previous frame.
1245 - fpr_offset is the offset of the first saved fpr from the previous frame.
1246 - vr_offset is the offset of the first saved vr from the previous frame.
1247 - ev_offset is the offset of the first saved ev from the previous frame.
1248 - lr_offset is the offset of the saved lr
1249 - cr_offset is the offset of the saved cr
1250 - vrsave_offset is the offset of the saved vrsave register
1254 skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
, CORE_ADDR lim_pc
,
1255 struct rs6000_framedata
*fdata
)
1257 CORE_ADDR orig_pc
= pc
;
1258 CORE_ADDR last_prologue_pc
= pc
;
1259 CORE_ADDR li_found_pc
= 0;
1263 long vr_saved_offset
= 0;
1269 int vrsave_reg
= -1;
1272 int minimal_toc_loaded
= 0;
1273 int prev_insn_was_prologue_insn
= 1;
1274 int num_skip_non_prologue_insns
= 0;
1275 int r0_contains_arg
= 0;
1276 const struct bfd_arch_info
*arch_info
= gdbarch_bfd_arch_info (gdbarch
);
1277 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1279 memset (fdata
, 0, sizeof (struct rs6000_framedata
));
1280 fdata
->saved_gpr
= -1;
1281 fdata
->saved_fpr
= -1;
1282 fdata
->saved_vr
= -1;
1283 fdata
->saved_ev
= -1;
1284 fdata
->alloca_reg
= -1;
1285 fdata
->frameless
= 1;
1286 fdata
->nosavedpc
= 1;
1290 /* Sometimes it isn't clear if an instruction is a prologue
1291 instruction or not. When we encounter one of these ambiguous
1292 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
1293 Otherwise, we'll assume that it really is a prologue instruction. */
1294 if (prev_insn_was_prologue_insn
)
1295 last_prologue_pc
= pc
;
1297 /* Stop scanning if we've hit the limit. */
1301 prev_insn_was_prologue_insn
= 1;
1303 /* Fetch the instruction and convert it to an integer. */
1304 if (target_read_memory (pc
, buf
, 4))
1306 op
= extract_unsigned_integer (buf
, 4);
1308 if ((op
& 0xfc1fffff) == 0x7c0802a6)
1310 /* Since shared library / PIC code, which needs to get its
1311 address at runtime, can appear to save more than one link
1325 remember just the first one, but skip over additional
1328 lr_reg
= (op
& 0x03e00000);
1330 r0_contains_arg
= 0;
1333 else if ((op
& 0xfc1fffff) == 0x7c000026)
1335 cr_reg
= (op
& 0x03e00000);
1337 r0_contains_arg
= 0;
1341 else if ((op
& 0xfc1f0000) == 0xd8010000)
1342 { /* stfd Rx,NUM(r1) */
1343 reg
= GET_SRC_REG (op
);
1344 if (fdata
->saved_fpr
== -1 || fdata
->saved_fpr
> reg
)
1346 fdata
->saved_fpr
= reg
;
1347 fdata
->fpr_offset
= SIGNED_SHORT (op
) + offset
;
1352 else if (((op
& 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
1353 (((op
& 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1354 (op
& 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1355 (op
& 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
1358 reg
= GET_SRC_REG (op
);
1359 if (fdata
->saved_gpr
== -1 || fdata
->saved_gpr
> reg
)
1361 fdata
->saved_gpr
= reg
;
1362 if ((op
& 0xfc1f0003) == 0xf8010000)
1364 fdata
->gpr_offset
= SIGNED_SHORT (op
) + offset
;
1369 else if ((op
& 0xffff0000) == 0x60000000)
1372 /* Allow nops in the prologue, but do not consider them to
1373 be part of the prologue unless followed by other prologue
1375 prev_insn_was_prologue_insn
= 0;
1379 else if ((op
& 0xffff0000) == 0x3c000000)
1380 { /* addis 0,0,NUM, used
1381 for >= 32k frames */
1382 fdata
->offset
= (op
& 0x0000ffff) << 16;
1383 fdata
->frameless
= 0;
1384 r0_contains_arg
= 0;
1388 else if ((op
& 0xffff0000) == 0x60000000)
1389 { /* ori 0,0,NUM, 2nd ha
1390 lf of >= 32k frames */
1391 fdata
->offset
|= (op
& 0x0000ffff);
1392 fdata
->frameless
= 0;
1393 r0_contains_arg
= 0;
1397 else if (lr_reg
>= 0 &&
1398 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1399 (((op
& 0xffff0000) == (lr_reg
| 0xf8010000)) ||
1400 /* stw Rx, NUM(r1) */
1401 ((op
& 0xffff0000) == (lr_reg
| 0x90010000)) ||
1402 /* stwu Rx, NUM(r1) */
1403 ((op
& 0xffff0000) == (lr_reg
| 0x94010000))))
1404 { /* where Rx == lr */
1405 fdata
->lr_offset
= offset
;
1406 fdata
->nosavedpc
= 0;
1407 /* Invalidate lr_reg, but don't set it to -1.
1408 That would mean that it had never been set. */
1410 if ((op
& 0xfc000003) == 0xf8000000 || /* std */
1411 (op
& 0xfc000000) == 0x90000000) /* stw */
1413 /* Does not update r1, so add displacement to lr_offset. */
1414 fdata
->lr_offset
+= SIGNED_SHORT (op
);
1419 else if (cr_reg
>= 0 &&
1420 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1421 (((op
& 0xffff0000) == (cr_reg
| 0xf8010000)) ||
1422 /* stw Rx, NUM(r1) */
1423 ((op
& 0xffff0000) == (cr_reg
| 0x90010000)) ||
1424 /* stwu Rx, NUM(r1) */
1425 ((op
& 0xffff0000) == (cr_reg
| 0x94010000))))
1426 { /* where Rx == cr */
1427 fdata
->cr_offset
= offset
;
1428 /* Invalidate cr_reg, but don't set it to -1.
1429 That would mean that it had never been set. */
1431 if ((op
& 0xfc000003) == 0xf8000000 ||
1432 (op
& 0xfc000000) == 0x90000000)
1434 /* Does not update r1, so add displacement to cr_offset. */
1435 fdata
->cr_offset
+= SIGNED_SHORT (op
);
1440 else if ((op
& 0xfe80ffff) == 0x42800005 && lr_reg
!= -1)
1442 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1443 prediction bits. If the LR has already been saved, we can
1447 else if (op
== 0x48000005)
1453 else if (op
== 0x48000004)
1458 else if ((op
& 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1459 in V.4 -mminimal-toc */
1460 (op
& 0xffff0000) == 0x3bde0000)
1461 { /* addi 30,30,foo@l */
1465 else if ((op
& 0xfc000001) == 0x48000001)
1469 fdata
->frameless
= 0;
1471 /* If the return address has already been saved, we can skip
1472 calls to blrl (for PIC). */
1473 if (lr_reg
!= -1 && bl_to_blrl_insn_p (pc
, op
))
1476 /* Don't skip over the subroutine call if it is not within
1477 the first three instructions of the prologue and either
1478 we have no line table information or the line info tells
1479 us that the subroutine call is not part of the line
1480 associated with the prologue. */
1481 if ((pc
- orig_pc
) > 8)
1483 struct symtab_and_line prologue_sal
= find_pc_line (orig_pc
, 0);
1484 struct symtab_and_line this_sal
= find_pc_line (pc
, 0);
1486 if ((prologue_sal
.line
== 0) || (prologue_sal
.line
!= this_sal
.line
))
1490 op
= read_memory_integer (pc
+ 4, 4);
1492 /* At this point, make sure this is not a trampoline
1493 function (a function that simply calls another functions,
1494 and nothing else). If the next is not a nop, this branch
1495 was part of the function prologue. */
1497 if (op
== 0x4def7b82 || op
== 0) /* crorc 15, 15, 15 */
1498 break; /* don't skip over
1503 /* update stack pointer */
1504 else if ((op
& 0xfc1f0000) == 0x94010000)
1505 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
1506 fdata
->frameless
= 0;
1507 fdata
->offset
= SIGNED_SHORT (op
);
1508 offset
= fdata
->offset
;
1511 else if ((op
& 0xfc1f016a) == 0x7c01016e)
1512 { /* stwux rX,r1,rY */
1513 /* no way to figure out what r1 is going to be */
1514 fdata
->frameless
= 0;
1515 offset
= fdata
->offset
;
1518 else if ((op
& 0xfc1f0003) == 0xf8010001)
1519 { /* stdu rX,NUM(r1) */
1520 fdata
->frameless
= 0;
1521 fdata
->offset
= SIGNED_SHORT (op
& ~3UL);
1522 offset
= fdata
->offset
;
1525 else if ((op
& 0xfc1f016a) == 0x7c01016a)
1526 { /* stdux rX,r1,rY */
1527 /* no way to figure out what r1 is going to be */
1528 fdata
->frameless
= 0;
1529 offset
= fdata
->offset
;
1532 else if ((op
& 0xffff0000) == 0x38210000)
1533 { /* addi r1,r1,SIMM */
1534 fdata
->frameless
= 0;
1535 fdata
->offset
+= SIGNED_SHORT (op
);
1536 offset
= fdata
->offset
;
1539 /* Load up minimal toc pointer. Do not treat an epilogue restore
1540 of r31 as a minimal TOC load. */
1541 else if (((op
>> 22) == 0x20f || /* l r31,... or l r30,... */
1542 (op
>> 22) == 0x3af) /* ld r31,... or ld r30,... */
1544 && !minimal_toc_loaded
)
1546 minimal_toc_loaded
= 1;
1549 /* move parameters from argument registers to local variable
1552 else if ((op
& 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1553 (((op
>> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1554 (((op
>> 21) & 31) <= 10) &&
1555 ((long) ((op
>> 16) & 31) >= fdata
->saved_gpr
)) /* Rx: local var reg */
1559 /* store parameters in stack */
1561 /* Move parameters from argument registers to temporary register. */
1562 else if (store_param_on_stack_p (op
, framep
, &r0_contains_arg
))
1566 /* Set up frame pointer */
1568 else if (op
== 0x603f0000 /* oril r31, r1, 0x0 */
1569 || op
== 0x7c3f0b78)
1571 fdata
->frameless
= 0;
1573 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 31);
1576 /* Another way to set up the frame pointer. */
1578 else if ((op
& 0xfc1fffff) == 0x38010000)
1579 { /* addi rX, r1, 0x0 */
1580 fdata
->frameless
= 0;
1582 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
1583 + ((op
& ~0x38010000) >> 21));
1586 /* AltiVec related instructions. */
1587 /* Store the vrsave register (spr 256) in another register for
1588 later manipulation, or load a register into the vrsave
1589 register. 2 instructions are used: mfvrsave and
1590 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1591 and mtspr SPR256, Rn. */
1592 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1593 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1594 else if ((op
& 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1596 vrsave_reg
= GET_SRC_REG (op
);
1599 else if ((op
& 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1603 /* Store the register where vrsave was saved to onto the stack:
1604 rS is the register where vrsave was stored in a previous
1606 /* 100100 sssss 00001 dddddddd dddddddd */
1607 else if ((op
& 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1609 if (vrsave_reg
== GET_SRC_REG (op
))
1611 fdata
->vrsave_offset
= SIGNED_SHORT (op
) + offset
;
1616 /* Compute the new value of vrsave, by modifying the register
1617 where vrsave was saved to. */
1618 else if (((op
& 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1619 || ((op
& 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1623 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1624 in a pair of insns to save the vector registers on the
1626 /* 001110 00000 00000 iiii iiii iiii iiii */
1627 /* 001110 01110 00000 iiii iiii iiii iiii */
1628 else if ((op
& 0xffff0000) == 0x38000000 /* li r0, SIMM */
1629 || (op
& 0xffff0000) == 0x39c00000) /* li r14, SIMM */
1631 if ((op
& 0xffff0000) == 0x38000000)
1632 r0_contains_arg
= 0;
1634 vr_saved_offset
= SIGNED_SHORT (op
);
1636 /* This insn by itself is not part of the prologue, unless
1637 if part of the pair of insns mentioned above. So do not
1638 record this insn as part of the prologue yet. */
1639 prev_insn_was_prologue_insn
= 0;
1641 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1642 /* 011111 sssss 11111 00000 00111001110 */
1643 else if ((op
& 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1645 if (pc
== (li_found_pc
+ 4))
1647 vr_reg
= GET_SRC_REG (op
);
1648 /* If this is the first vector reg to be saved, or if
1649 it has a lower number than others previously seen,
1650 reupdate the frame info. */
1651 if (fdata
->saved_vr
== -1 || fdata
->saved_vr
> vr_reg
)
1653 fdata
->saved_vr
= vr_reg
;
1654 fdata
->vr_offset
= vr_saved_offset
+ offset
;
1656 vr_saved_offset
= -1;
1661 /* End AltiVec related instructions. */
1663 /* Start BookE related instructions. */
1664 /* Store gen register S at (r31+uimm).
1665 Any register less than r13 is volatile, so we don't care. */
1666 /* 000100 sssss 11111 iiiii 01100100001 */
1667 else if (arch_info
->mach
== bfd_mach_ppc_e500
1668 && (op
& 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
1670 if ((op
& 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
1673 ev_reg
= GET_SRC_REG (op
);
1674 imm
= (op
>> 11) & 0x1f;
1675 ev_offset
= imm
* 8;
1676 /* If this is the first vector reg to be saved, or if
1677 it has a lower number than others previously seen,
1678 reupdate the frame info. */
1679 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1681 fdata
->saved_ev
= ev_reg
;
1682 fdata
->ev_offset
= ev_offset
+ offset
;
1687 /* Store gen register rS at (r1+rB). */
1688 /* 000100 sssss 00001 bbbbb 01100100000 */
1689 else if (arch_info
->mach
== bfd_mach_ppc_e500
1690 && (op
& 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1692 if (pc
== (li_found_pc
+ 4))
1694 ev_reg
= GET_SRC_REG (op
);
1695 /* If this is the first vector reg to be saved, or if
1696 it has a lower number than others previously seen,
1697 reupdate the frame info. */
1698 /* We know the contents of rB from the previous instruction. */
1699 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1701 fdata
->saved_ev
= ev_reg
;
1702 fdata
->ev_offset
= vr_saved_offset
+ offset
;
1704 vr_saved_offset
= -1;
1710 /* Store gen register r31 at (rA+uimm). */
1711 /* 000100 11111 aaaaa iiiii 01100100001 */
1712 else if (arch_info
->mach
== bfd_mach_ppc_e500
1713 && (op
& 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
1715 /* Wwe know that the source register is 31 already, but
1716 it can't hurt to compute it. */
1717 ev_reg
= GET_SRC_REG (op
);
1718 ev_offset
= ((op
>> 11) & 0x1f) * 8;
1719 /* If this is the first vector reg to be saved, or if
1720 it has a lower number than others previously seen,
1721 reupdate the frame info. */
1722 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1724 fdata
->saved_ev
= ev_reg
;
1725 fdata
->ev_offset
= ev_offset
+ offset
;
1730 /* Store gen register S at (r31+r0).
1731 Store param on stack when offset from SP bigger than 4 bytes. */
1732 /* 000100 sssss 11111 00000 01100100000 */
1733 else if (arch_info
->mach
== bfd_mach_ppc_e500
1734 && (op
& 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
1736 if (pc
== (li_found_pc
+ 4))
1738 if ((op
& 0x03e00000) >= 0x01a00000)
1740 ev_reg
= GET_SRC_REG (op
);
1741 /* If this is the first vector reg to be saved, or if
1742 it has a lower number than others previously seen,
1743 reupdate the frame info. */
1744 /* We know the contents of r0 from the previous
1746 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1748 fdata
->saved_ev
= ev_reg
;
1749 fdata
->ev_offset
= vr_saved_offset
+ offset
;
1753 vr_saved_offset
= -1;
1758 /* End BookE related instructions. */
1762 /* Not a recognized prologue instruction.
1763 Handle optimizer code motions into the prologue by continuing
1764 the search if we have no valid frame yet or if the return
1765 address is not yet saved in the frame. */
1766 if (fdata
->frameless
== 0 && fdata
->nosavedpc
== 0)
1769 if (op
== 0x4e800020 /* blr */
1770 || op
== 0x4e800420) /* bctr */
1771 /* Do not scan past epilogue in frameless functions or
1774 if ((op
& 0xf4000000) == 0x40000000) /* bxx */
1775 /* Never skip branches. */
1778 if (num_skip_non_prologue_insns
++ > max_skip_non_prologue_insns
)
1779 /* Do not scan too many insns, scanning insns is expensive with
1783 /* Continue scanning. */
1784 prev_insn_was_prologue_insn
= 0;
1790 /* I have problems with skipping over __main() that I need to address
1791 * sometime. Previously, I used to use misc_function_vector which
1792 * didn't work as well as I wanted to be. -MGO */
1794 /* If the first thing after skipping a prolog is a branch to a function,
1795 this might be a call to an initializer in main(), introduced by gcc2.
1796 We'd like to skip over it as well. Fortunately, xlc does some extra
1797 work before calling a function right after a prologue, thus we can
1798 single out such gcc2 behaviour. */
1801 if ((op
& 0xfc000001) == 0x48000001)
1802 { /* bl foo, an initializer function? */
1803 op
= read_memory_integer (pc
+ 4, 4);
1805 if (op
== 0x4def7b82)
1806 { /* cror 0xf, 0xf, 0xf (nop) */
1808 /* Check and see if we are in main. If so, skip over this
1809 initializer function as well. */
1811 tmp
= find_pc_misc_function (pc
);
1813 && strcmp (misc_function_vector
[tmp
].name
, main_name ()) == 0)
1819 fdata
->offset
= -fdata
->offset
;
1820 return last_prologue_pc
;
1824 /*************************************************************************
1825 Support for creating pushing a dummy frame into the stack, and popping
1827 *************************************************************************/
1830 /* All the ABI's require 16 byte alignment. */
1832 rs6000_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1834 return (addr
& -16);
1837 /* Pass the arguments in either registers, or in the stack. In RS/6000,
1838 the first eight words of the argument list (that might be less than
1839 eight parameters if some parameters occupy more than one word) are
1840 passed in r3..r10 registers. float and double parameters are
1841 passed in fpr's, in addition to that. Rest of the parameters if any
1842 are passed in user stack. There might be cases in which half of the
1843 parameter is copied into registers, the other half is pushed into
1846 Stack must be aligned on 64-bit boundaries when synthesizing
1849 If the function is returning a structure, then the return address is passed
1850 in r3, then the first 7 words of the parameters can be passed in registers,
1851 starting from r4. */
1854 rs6000_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1855 struct regcache
*regcache
, CORE_ADDR bp_addr
,
1856 int nargs
, struct value
**args
, CORE_ADDR sp
,
1857 int struct_return
, CORE_ADDR struct_addr
)
1859 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1862 int argno
; /* current argument number */
1863 int argbytes
; /* current argument byte */
1864 gdb_byte tmp_buffer
[50];
1865 int f_argno
= 0; /* current floating point argno */
1866 int wordsize
= gdbarch_tdep (gdbarch
)->wordsize
;
1867 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
1869 struct value
*arg
= 0;
1874 /* The calling convention this function implements assumes the
1875 processor has floating-point registers. We shouldn't be using it
1876 on PPC variants that lack them. */
1877 gdb_assert (ppc_floating_point_unit_p (gdbarch
));
1879 /* The first eight words of ther arguments are passed in registers.
1880 Copy them appropriately. */
1883 /* If the function is returning a `struct', then the first word
1884 (which will be passed in r3) is used for struct return address.
1885 In that case we should advance one word and start from r4
1886 register to copy parameters. */
1889 regcache_raw_write_unsigned (regcache
, tdep
->ppc_gp0_regnum
+ 3,
1895 effectively indirect call... gcc does...
1897 return_val example( float, int);
1900 float in fp0, int in r3
1901 offset of stack on overflow 8/16
1902 for varargs, must go by type.
1904 float in r3&r4, int in r5
1905 offset of stack on overflow different
1907 return in r3 or f0. If no float, must study how gcc emulates floats;
1908 pay attention to arg promotion.
1909 User may have to cast\args to handle promotion correctly
1910 since gdb won't know if prototype supplied or not.
1913 for (argno
= 0, argbytes
= 0; argno
< nargs
&& ii
< 8; ++ii
)
1915 int reg_size
= register_size (gdbarch
, ii
+ 3);
1918 type
= check_typedef (value_type (arg
));
1919 len
= TYPE_LENGTH (type
);
1921 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1924 /* Floating point arguments are passed in fpr's, as well as gpr's.
1925 There are 13 fpr's reserved for passing parameters. At this point
1926 there is no way we would run out of them. */
1928 gdb_assert (len
<= 8);
1930 regcache_cooked_write (regcache
,
1931 tdep
->ppc_fp0_regnum
+ 1 + f_argno
,
1932 value_contents (arg
));
1939 /* Argument takes more than one register. */
1940 while (argbytes
< len
)
1942 gdb_byte word
[MAX_REGISTER_SIZE
];
1943 memset (word
, 0, reg_size
);
1945 ((char *) value_contents (arg
)) + argbytes
,
1946 (len
- argbytes
) > reg_size
1947 ? reg_size
: len
- argbytes
);
1948 regcache_cooked_write (regcache
,
1949 tdep
->ppc_gp0_regnum
+ 3 + ii
,
1951 ++ii
, argbytes
+= reg_size
;
1954 goto ran_out_of_registers_for_arguments
;
1961 /* Argument can fit in one register. No problem. */
1962 int adj
= gdbarch_byte_order (gdbarch
)
1963 == BFD_ENDIAN_BIG
? reg_size
- len
: 0;
1964 gdb_byte word
[MAX_REGISTER_SIZE
];
1966 memset (word
, 0, reg_size
);
1967 memcpy (word
, value_contents (arg
), len
);
1968 regcache_cooked_write (regcache
, tdep
->ppc_gp0_regnum
+ 3 +ii
, word
);
1973 ran_out_of_registers_for_arguments
:
1975 regcache_cooked_read_unsigned (regcache
,
1976 gdbarch_sp_regnum (gdbarch
),
1979 /* Location for 8 parameters are always reserved. */
1982 /* Another six words for back chain, TOC register, link register, etc. */
1985 /* Stack pointer must be quadword aligned. */
1988 /* If there are more arguments, allocate space for them in
1989 the stack, then push them starting from the ninth one. */
1991 if ((argno
< nargs
) || argbytes
)
1997 space
+= ((len
- argbytes
+ 3) & -4);
2003 for (; jj
< nargs
; ++jj
)
2005 struct value
*val
= args
[jj
];
2006 space
+= ((TYPE_LENGTH (value_type (val
))) + 3) & -4;
2009 /* Add location required for the rest of the parameters. */
2010 space
= (space
+ 15) & -16;
2013 /* This is another instance we need to be concerned about
2014 securing our stack space. If we write anything underneath %sp
2015 (r1), we might conflict with the kernel who thinks he is free
2016 to use this area. So, update %sp first before doing anything
2019 regcache_raw_write_signed (regcache
,
2020 gdbarch_sp_regnum (gdbarch
), sp
);
2022 /* If the last argument copied into the registers didn't fit there
2023 completely, push the rest of it into stack. */
2027 write_memory (sp
+ 24 + (ii
* 4),
2028 value_contents (arg
) + argbytes
,
2031 ii
+= ((len
- argbytes
+ 3) & -4) / 4;
2034 /* Push the rest of the arguments into stack. */
2035 for (; argno
< nargs
; ++argno
)
2039 type
= check_typedef (value_type (arg
));
2040 len
= TYPE_LENGTH (type
);
2043 /* Float types should be passed in fpr's, as well as in the
2045 if (TYPE_CODE (type
) == TYPE_CODE_FLT
&& f_argno
< 13)
2048 gdb_assert (len
<= 8);
2050 regcache_cooked_write (regcache
,
2051 tdep
->ppc_fp0_regnum
+ 1 + f_argno
,
2052 value_contents (arg
));
2056 write_memory (sp
+ 24 + (ii
* 4), value_contents (arg
), len
);
2057 ii
+= ((len
+ 3) & -4) / 4;
2061 /* Set the stack pointer. According to the ABI, the SP is meant to
2062 be set _before_ the corresponding stack space is used. On AIX,
2063 this even applies when the target has been completely stopped!
2064 Not doing this can lead to conflicts with the kernel which thinks
2065 that it still has control over this not-yet-allocated stack
2067 regcache_raw_write_signed (regcache
, gdbarch_sp_regnum (gdbarch
), sp
);
2069 /* Set back chain properly. */
2070 store_unsigned_integer (tmp_buffer
, wordsize
, saved_sp
);
2071 write_memory (sp
, tmp_buffer
, wordsize
);
2073 /* Point the inferior function call's return address at the dummy's
2075 regcache_raw_write_signed (regcache
, tdep
->ppc_lr_regnum
, bp_addr
);
2077 /* Set the TOC register, get the value from the objfile reader
2078 which, in turn, gets it from the VMAP table. */
2079 if (rs6000_find_toc_address_hook
!= NULL
)
2081 CORE_ADDR tocvalue
= (*rs6000_find_toc_address_hook
) (func_addr
);
2082 regcache_raw_write_signed (regcache
, tdep
->ppc_toc_regnum
, tocvalue
);
2085 target_store_registers (regcache
, -1);
2089 static enum return_value_convention
2090 rs6000_return_value (struct gdbarch
*gdbarch
, struct type
*valtype
,
2091 struct regcache
*regcache
, gdb_byte
*readbuf
,
2092 const gdb_byte
*writebuf
)
2094 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2097 /* The calling convention this function implements assumes the
2098 processor has floating-point registers. We shouldn't be using it
2099 on PowerPC variants that lack them. */
2100 gdb_assert (ppc_floating_point_unit_p (gdbarch
));
2102 /* AltiVec extension: Functions that declare a vector data type as a
2103 return value place that return value in VR2. */
2104 if (TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (valtype
)
2105 && TYPE_LENGTH (valtype
) == 16)
2108 regcache_cooked_read (regcache
, tdep
->ppc_vr0_regnum
+ 2, readbuf
);
2110 regcache_cooked_write (regcache
, tdep
->ppc_vr0_regnum
+ 2, writebuf
);
2112 return RETURN_VALUE_REGISTER_CONVENTION
;
2115 /* If the called subprogram returns an aggregate, there exists an
2116 implicit first argument, whose value is the address of a caller-
2117 allocated buffer into which the callee is assumed to store its
2118 return value. All explicit parameters are appropriately
2120 if (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
2121 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
2122 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
2123 return RETURN_VALUE_STRUCT_CONVENTION
;
2125 /* Scalar floating-point values are returned in FPR1 for float or
2126 double, and in FPR1:FPR2 for quadword precision. Fortran
2127 complex*8 and complex*16 are returned in FPR1:FPR2, and
2128 complex*32 is returned in FPR1:FPR4. */
2129 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
2130 && (TYPE_LENGTH (valtype
) == 4 || TYPE_LENGTH (valtype
) == 8))
2132 struct type
*regtype
= register_type (gdbarch
, tdep
->ppc_fp0_regnum
);
2135 /* FIXME: kettenis/2007-01-01: Add support for quadword
2136 precision and complex. */
2140 regcache_cooked_read (regcache
, tdep
->ppc_fp0_regnum
+ 1, regval
);
2141 convert_typed_floating (regval
, regtype
, readbuf
, valtype
);
2145 convert_typed_floating (writebuf
, valtype
, regval
, regtype
);
2146 regcache_cooked_write (regcache
, tdep
->ppc_fp0_regnum
+ 1, regval
);
2149 return RETURN_VALUE_REGISTER_CONVENTION
;
2152 /* Values of the types int, long, short, pointer, and char (length
2153 is less than or equal to four bytes), as well as bit values of
2154 lengths less than or equal to 32 bits, must be returned right
2155 justified in GPR3 with signed values sign extended and unsigned
2156 values zero extended, as necessary. */
2157 if (TYPE_LENGTH (valtype
) <= tdep
->wordsize
)
2163 /* For reading we don't have to worry about sign extension. */
2164 regcache_cooked_read_unsigned (regcache
, tdep
->ppc_gp0_regnum
+ 3,
2166 store_unsigned_integer (readbuf
, TYPE_LENGTH (valtype
), regval
);
2170 /* For writing, use unpack_long since that should handle any
2171 required sign extension. */
2172 regcache_cooked_write_unsigned (regcache
, tdep
->ppc_gp0_regnum
+ 3,
2173 unpack_long (valtype
, writebuf
));
2176 return RETURN_VALUE_REGISTER_CONVENTION
;
2179 /* Eight-byte non-floating-point scalar values must be returned in
2182 if (TYPE_LENGTH (valtype
) == 8)
2184 gdb_assert (TYPE_CODE (valtype
) != TYPE_CODE_FLT
);
2185 gdb_assert (tdep
->wordsize
== 4);
2191 regcache_cooked_read (regcache
, tdep
->ppc_gp0_regnum
+ 3, regval
);
2192 regcache_cooked_read (regcache
, tdep
->ppc_gp0_regnum
+ 4,
2194 memcpy (readbuf
, regval
, 8);
2198 regcache_cooked_write (regcache
, tdep
->ppc_gp0_regnum
+ 3, writebuf
);
2199 regcache_cooked_write (regcache
, tdep
->ppc_gp0_regnum
+ 4,
2203 return RETURN_VALUE_REGISTER_CONVENTION
;
2206 return RETURN_VALUE_STRUCT_CONVENTION
;
2209 /* Return whether handle_inferior_event() should proceed through code
2210 starting at PC in function NAME when stepping.
2212 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
2213 handle memory references that are too distant to fit in instructions
2214 generated by the compiler. For example, if 'foo' in the following
2219 is greater than 32767, the linker might replace the lwz with a branch to
2220 somewhere in @FIX1 that does the load in 2 instructions and then branches
2221 back to where execution should continue.
2223 GDB should silently step over @FIX code, just like AIX dbx does.
2224 Unfortunately, the linker uses the "b" instruction for the
2225 branches, meaning that the link register doesn't get set.
2226 Therefore, GDB's usual step_over_function () mechanism won't work.
2228 Instead, use the gdbarch_skip_trampoline_code and
2229 gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past
2233 rs6000_in_solib_return_trampoline (CORE_ADDR pc
, char *name
)
2235 return name
&& !strncmp (name
, "@FIX", 4);
2238 /* Skip code that the user doesn't want to see when stepping:
2240 1. Indirect function calls use a piece of trampoline code to do context
2241 switching, i.e. to set the new TOC table. Skip such code if we are on
2242 its first instruction (as when we have single-stepped to here).
2244 2. Skip shared library trampoline code (which is different from
2245 indirect function call trampolines).
2247 3. Skip bigtoc fixup code.
2249 Result is desired PC to step until, or NULL if we are not in
2250 code that should be skipped. */
2253 rs6000_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
2255 unsigned int ii
, op
;
2257 CORE_ADDR solib_target_pc
;
2258 struct minimal_symbol
*msymbol
;
2260 static unsigned trampoline_code
[] =
2262 0x800b0000, /* l r0,0x0(r11) */
2263 0x90410014, /* st r2,0x14(r1) */
2264 0x7c0903a6, /* mtctr r0 */
2265 0x804b0004, /* l r2,0x4(r11) */
2266 0x816b0008, /* l r11,0x8(r11) */
2267 0x4e800420, /* bctr */
2268 0x4e800020, /* br */
2272 /* Check for bigtoc fixup code. */
2273 msymbol
= lookup_minimal_symbol_by_pc (pc
);
2275 && rs6000_in_solib_return_trampoline (pc
,
2276 DEPRECATED_SYMBOL_NAME (msymbol
)))
2278 /* Double-check that the third instruction from PC is relative "b". */
2279 op
= read_memory_integer (pc
+ 8, 4);
2280 if ((op
& 0xfc000003) == 0x48000000)
2282 /* Extract bits 6-29 as a signed 24-bit relative word address and
2283 add it to the containing PC. */
2284 rel
= ((int)(op
<< 6) >> 6);
2285 return pc
+ 8 + rel
;
2289 /* If pc is in a shared library trampoline, return its target. */
2290 solib_target_pc
= find_solib_trampoline_target (frame
, pc
);
2291 if (solib_target_pc
)
2292 return solib_target_pc
;
2294 for (ii
= 0; trampoline_code
[ii
]; ++ii
)
2296 op
= read_memory_integer (pc
+ (ii
* 4), 4);
2297 if (op
!= trampoline_code
[ii
])
2300 ii
= get_frame_register_unsigned (frame
, 11); /* r11 holds destination addr */
2301 pc
= read_memory_addr (ii
,
2302 gdbarch_tdep (get_frame_arch (frame
))->wordsize
); /* (r11) value */
2306 /* ISA-specific vector types. */
2308 static struct type
*
2309 rs6000_builtin_type_vec64 (struct gdbarch
*gdbarch
)
2311 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2313 if (!tdep
->ppc_builtin_type_vec64
)
2315 /* The type we're building is this: */
2317 union __gdb_builtin_type_vec64
2321 int32_t v2_int32
[2];
2322 int16_t v4_int16
[4];
2329 t
= init_composite_type ("__ppc_builtin_type_vec64", TYPE_CODE_UNION
);
2330 append_composite_type_field (t
, "uint64", builtin_type_int64
);
2331 append_composite_type_field (t
, "v2_float",
2332 init_vector_type (builtin_type_float
, 2));
2333 append_composite_type_field (t
, "v2_int32",
2334 init_vector_type (builtin_type_int32
, 2));
2335 append_composite_type_field (t
, "v4_int16",
2336 init_vector_type (builtin_type_int16
, 4));
2337 append_composite_type_field (t
, "v8_int8",
2338 init_vector_type (builtin_type_int8
, 8));
2340 TYPE_FLAGS (t
) |= TYPE_FLAG_VECTOR
;
2341 TYPE_NAME (t
) = "ppc_builtin_type_vec64";
2342 tdep
->ppc_builtin_type_vec64
= t
;
2345 return tdep
->ppc_builtin_type_vec64
;
2348 /* Return the size of register REG when words are WORDSIZE bytes long. If REG
2349 isn't available with that word size, return 0. */
2352 regsize (const struct reg
*reg
, int wordsize
)
2354 return wordsize
== 8 ? reg
->sz64
: reg
->sz32
;
2357 /* Return the name of register number REGNO, or the empty string if it
2358 is an anonymous register. */
2361 rs6000_register_name (struct gdbarch
*gdbarch
, int regno
)
2363 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2365 /* The upper half "registers" have names in the XML description,
2366 but we present only the low GPRs and the full 64-bit registers
2368 if (tdep
->ppc_ev0_upper_regnum
>= 0
2369 && tdep
->ppc_ev0_upper_regnum
<= regno
2370 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
2373 /* Check if the SPE pseudo registers are available. */
2374 if (tdep
->ppc_ev0_regnum
>= 0
2375 && tdep
->ppc_ev0_regnum
<= regno
2376 && regno
< tdep
->ppc_ev0_regnum
+ ppc_num_gprs
)
2378 static const char *const spe_regnames
[] = {
2379 "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7",
2380 "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15",
2381 "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23",
2382 "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31",
2384 return spe_regnames
[regno
- tdep
->ppc_ev0_regnum
];
2387 return tdesc_register_name (gdbarch
, regno
);
2390 /* Return the GDB type object for the "standard" data type of data in
2393 static struct type
*
2394 rs6000_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2396 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2398 /* These are the only pseudo-registers we support. */
2399 gdb_assert (tdep
->ppc_ev0_regnum
>= 0
2400 && regnum
>= tdep
->ppc_ev0_regnum
2401 && regnum
< tdep
->ppc_ev0_regnum
+ 32);
2403 return rs6000_builtin_type_vec64 (gdbarch
);
2406 /* Is REGNUM a member of REGGROUP? */
2408 rs6000_pseudo_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2409 struct reggroup
*group
)
2411 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2413 /* These are the only pseudo-registers we support. */
2414 gdb_assert (tdep
->ppc_ev0_regnum
>= 0
2415 && regnum
>= tdep
->ppc_ev0_regnum
2416 && regnum
< tdep
->ppc_ev0_regnum
+ 32);
2418 if (group
== all_reggroup
|| group
== vector_reggroup
)
2424 /* The register format for RS/6000 floating point registers is always
2425 double, we need a conversion if the memory format is float. */
2428 rs6000_convert_register_p (struct gdbarch
*gdbarch
, int regnum
,
2431 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2433 return (tdep
->ppc_fp0_regnum
>= 0
2434 && regnum
>= tdep
->ppc_fp0_regnum
2435 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
2436 && TYPE_CODE (type
) == TYPE_CODE_FLT
2437 && TYPE_LENGTH (type
) != TYPE_LENGTH (builtin_type_double
));
2441 rs6000_register_to_value (struct frame_info
*frame
,
2446 gdb_byte from
[MAX_REGISTER_SIZE
];
2448 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
2450 get_frame_register (frame
, regnum
, from
);
2451 convert_typed_floating (from
, builtin_type_double
, to
, type
);
2455 rs6000_value_to_register (struct frame_info
*frame
,
2458 const gdb_byte
*from
)
2460 gdb_byte to
[MAX_REGISTER_SIZE
];
2462 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
2464 convert_typed_floating (from
, type
, to
, builtin_type_double
);
2465 put_frame_register (frame
, regnum
, to
);
2468 /* Move SPE vector register values between a 64-bit buffer and the two
2469 32-bit raw register halves in a regcache. This function handles
2470 both splitting a 64-bit value into two 32-bit halves, and joining
2471 two halves into a whole 64-bit value, depending on the function
2472 passed as the MOVE argument.
2474 EV_REG must be the number of an SPE evN vector register --- a
2475 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2478 Call MOVE once for each 32-bit half of that register, passing
2479 REGCACHE, the number of the raw register corresponding to that
2480 half, and the address of the appropriate half of BUFFER.
2482 For example, passing 'regcache_raw_read' as the MOVE function will
2483 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2484 'regcache_raw_supply' will supply the contents of BUFFER to the
2485 appropriate pair of raw registers in REGCACHE.
2487 You may need to cast away some 'const' qualifiers when passing
2488 MOVE, since this function can't tell at compile-time which of
2489 REGCACHE or BUFFER is acting as the source of the data. If C had
2490 co-variant type qualifiers, ... */
2492 e500_move_ev_register (void (*move
) (struct regcache
*regcache
,
2493 int regnum
, gdb_byte
*buf
),
2494 struct regcache
*regcache
, int ev_reg
,
2497 struct gdbarch
*arch
= get_regcache_arch (regcache
);
2498 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
2500 gdb_byte
*byte_buffer
= buffer
;
2502 gdb_assert (tdep
->ppc_ev0_regnum
<= ev_reg
2503 && ev_reg
< tdep
->ppc_ev0_regnum
+ ppc_num_gprs
);
2505 reg_index
= ev_reg
- tdep
->ppc_ev0_regnum
;
2507 if (gdbarch_byte_order (arch
) == BFD_ENDIAN_BIG
)
2509 move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
, byte_buffer
);
2510 move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
, byte_buffer
+ 4);
2514 move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
, byte_buffer
);
2515 move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
, byte_buffer
+ 4);
2520 e500_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2521 int reg_nr
, gdb_byte
*buffer
)
2523 struct gdbarch
*regcache_arch
= get_regcache_arch (regcache
);
2524 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2526 gdb_assert (regcache_arch
== gdbarch
);
2528 if (tdep
->ppc_ev0_regnum
<= reg_nr
2529 && reg_nr
< tdep
->ppc_ev0_regnum
+ ppc_num_gprs
)
2530 e500_move_ev_register (regcache_raw_read
, regcache
, reg_nr
, buffer
);
2532 internal_error (__FILE__
, __LINE__
,
2533 _("e500_pseudo_register_read: "
2534 "called on unexpected register '%s' (%d)"),
2535 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2539 e500_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2540 int reg_nr
, const gdb_byte
*buffer
)
2542 struct gdbarch
*regcache_arch
= get_regcache_arch (regcache
);
2543 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2545 gdb_assert (regcache_arch
== gdbarch
);
2547 if (tdep
->ppc_ev0_regnum
<= reg_nr
2548 && reg_nr
< tdep
->ppc_ev0_regnum
+ ppc_num_gprs
)
2549 e500_move_ev_register ((void (*) (struct regcache
*, int, gdb_byte
*))
2551 regcache
, reg_nr
, (gdb_byte
*) buffer
);
2553 internal_error (__FILE__
, __LINE__
,
2554 _("e500_pseudo_register_read: "
2555 "called on unexpected register '%s' (%d)"),
2556 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2559 /* Convert a DBX STABS register number to a GDB register number. */
2561 rs6000_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
2563 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2565 if (0 <= num
&& num
<= 31)
2566 return tdep
->ppc_gp0_regnum
+ num
;
2567 else if (32 <= num
&& num
<= 63)
2568 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2569 specifies registers the architecture doesn't have? Our
2570 callers don't check the value we return. */
2571 return tdep
->ppc_fp0_regnum
+ (num
- 32);
2572 else if (77 <= num
&& num
<= 108)
2573 return tdep
->ppc_vr0_regnum
+ (num
- 77);
2574 else if (1200 <= num
&& num
< 1200 + 32)
2575 return tdep
->ppc_ev0_regnum
+ (num
- 1200);
2580 return tdep
->ppc_mq_regnum
;
2582 return tdep
->ppc_lr_regnum
;
2584 return tdep
->ppc_ctr_regnum
;
2586 return tdep
->ppc_xer_regnum
;
2588 return tdep
->ppc_vrsave_regnum
;
2590 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
2592 return tdep
->ppc_acc_regnum
;
2594 return tdep
->ppc_spefscr_regnum
;
2601 /* Convert a Dwarf 2 register number to a GDB register number. */
2603 rs6000_dwarf2_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
2605 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2607 if (0 <= num
&& num
<= 31)
2608 return tdep
->ppc_gp0_regnum
+ num
;
2609 else if (32 <= num
&& num
<= 63)
2610 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2611 specifies registers the architecture doesn't have? Our
2612 callers don't check the value we return. */
2613 return tdep
->ppc_fp0_regnum
+ (num
- 32);
2614 else if (1124 <= num
&& num
< 1124 + 32)
2615 return tdep
->ppc_vr0_regnum
+ (num
- 1124);
2616 else if (1200 <= num
&& num
< 1200 + 32)
2617 return tdep
->ppc_ev0_regnum
+ (num
- 1200);
2622 return tdep
->ppc_cr_regnum
;
2624 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
2626 return tdep
->ppc_acc_regnum
;
2628 return tdep
->ppc_mq_regnum
;
2630 return tdep
->ppc_xer_regnum
;
2632 return tdep
->ppc_lr_regnum
;
2634 return tdep
->ppc_ctr_regnum
;
2636 return tdep
->ppc_vrsave_regnum
;
2638 return tdep
->ppc_spefscr_regnum
;
2644 /* Translate a .eh_frame register to DWARF register, or adjust a
2645 .debug_frame register. */
2648 rs6000_adjust_frame_regnum (struct gdbarch
*gdbarch
, int num
, int eh_frame_p
)
2650 /* GCC releases before 3.4 use GCC internal register numbering in
2651 .debug_frame (and .debug_info, et cetera). The numbering is
2652 different from the standard SysV numbering for everything except
2653 for GPRs and FPRs. We can not detect this problem in most cases
2654 - to get accurate debug info for variables living in lr, ctr, v0,
2655 et cetera, use a newer version of GCC. But we must detect
2656 one important case - lr is in column 65 in .debug_frame output,
2659 GCC 3.4, and the "hammer" branch, have a related problem. They
2660 record lr register saves in .debug_frame as 108, but still record
2661 the return column as 65. We fix that up too.
2663 We can do this because 65 is assigned to fpsr, and GCC never
2664 generates debug info referring to it. To add support for
2665 handwritten debug info that restores fpsr, we would need to add a
2666 producer version check to this. */
2675 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
2676 internal register numbering; translate that to the standard DWARF2
2677 register numbering. */
2678 if (0 <= num
&& num
<= 63) /* r0-r31,fp0-fp31 */
2680 else if (68 <= num
&& num
<= 75) /* cr0-cr8 */
2681 return num
- 68 + 86;
2682 else if (77 <= num
&& num
<= 108) /* vr0-vr31 */
2683 return num
- 77 + 1124;
2695 case 109: /* vrsave */
2697 case 110: /* vscr */
2699 case 111: /* spe_acc */
2701 case 112: /* spefscr */
2708 /* Support for CONVERT_FROM_FUNC_PTR_ADDR (ARCH, ADDR, TARG).
2710 Usually a function pointer's representation is simply the address
2711 of the function. On the RS/6000 however, a function pointer is
2712 represented by a pointer to an OPD entry. This OPD entry contains
2713 three words, the first word is the address of the function, the
2714 second word is the TOC pointer (r2), and the third word is the
2715 static chain value. Throughout GDB it is currently assumed that a
2716 function pointer contains the address of the function, which is not
2717 easy to fix. In addition, the conversion of a function address to
2718 a function pointer would require allocation of an OPD entry in the
2719 inferior's memory space, with all its drawbacks. To be able to
2720 call C++ virtual methods in the inferior (which are called via
2721 function pointers), find_function_addr uses this function to get the
2722 function address from a function pointer. */
2724 /* Return real function address if ADDR (a function pointer) is in the data
2725 space and is therefore a special function pointer. */
2728 rs6000_convert_from_func_ptr_addr (struct gdbarch
*gdbarch
,
2730 struct target_ops
*targ
)
2732 struct obj_section
*s
;
2734 s
= find_pc_section (addr
);
2735 if (s
&& s
->the_bfd_section
->flags
& SEC_CODE
)
2738 /* ADDR is in the data space, so it's a special function pointer. */
2739 return read_memory_addr (addr
, gdbarch_tdep (gdbarch
)->wordsize
);
2743 /* Handling the various POWER/PowerPC variants. */
2745 /* Information about a particular processor variant. */
2749 /* Name of this variant. */
2752 /* English description of the variant. */
2755 /* bfd_arch_info.arch corresponding to variant. */
2756 enum bfd_architecture arch
;
2758 /* bfd_arch_info.mach corresponding to variant. */
2761 /* Target description for this variant. */
2762 struct target_desc
**tdesc
;
2765 static struct variant variants
[] =
2767 {"powerpc", "PowerPC user-level", bfd_arch_powerpc
,
2768 bfd_mach_ppc
, &tdesc_powerpc_32
},
2769 {"power", "POWER user-level", bfd_arch_rs6000
,
2770 bfd_mach_rs6k
, &tdesc_rs6000
},
2771 {"403", "IBM PowerPC 403", bfd_arch_powerpc
,
2772 bfd_mach_ppc_403
, &tdesc_powerpc_403
},
2773 {"601", "Motorola PowerPC 601", bfd_arch_powerpc
,
2774 bfd_mach_ppc_601
, &tdesc_powerpc_601
},
2775 {"602", "Motorola PowerPC 602", bfd_arch_powerpc
,
2776 bfd_mach_ppc_602
, &tdesc_powerpc_602
},
2777 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc
,
2778 bfd_mach_ppc_603
, &tdesc_powerpc_603
},
2779 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc
,
2780 604, &tdesc_powerpc_604
},
2781 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc
,
2782 bfd_mach_ppc_403gc
, &tdesc_powerpc_403gc
},
2783 {"505", "Motorola PowerPC 505", bfd_arch_powerpc
,
2784 bfd_mach_ppc_505
, &tdesc_powerpc_505
},
2785 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc
,
2786 bfd_mach_ppc_860
, &tdesc_powerpc_860
},
2787 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc
,
2788 bfd_mach_ppc_750
, &tdesc_powerpc_750
},
2789 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc
,
2790 bfd_mach_ppc_7400
, &tdesc_powerpc_7400
},
2791 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc
,
2792 bfd_mach_ppc_e500
, &tdesc_powerpc_e500
},
2795 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc
,
2796 bfd_mach_ppc64
, &tdesc_powerpc_64
},
2797 {"620", "Motorola PowerPC 620", bfd_arch_powerpc
,
2798 bfd_mach_ppc_620
, &tdesc_powerpc_64
},
2799 {"630", "Motorola PowerPC 630", bfd_arch_powerpc
,
2800 bfd_mach_ppc_630
, &tdesc_powerpc_64
},
2801 {"a35", "PowerPC A35", bfd_arch_powerpc
,
2802 bfd_mach_ppc_a35
, &tdesc_powerpc_64
},
2803 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc
,
2804 bfd_mach_ppc_rs64ii
, &tdesc_powerpc_64
},
2805 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc
,
2806 bfd_mach_ppc_rs64iii
, &tdesc_powerpc_64
},
2808 /* FIXME: I haven't checked the register sets of the following. */
2809 {"rs1", "IBM POWER RS1", bfd_arch_rs6000
,
2810 bfd_mach_rs6k_rs1
, &tdesc_rs6000
},
2811 {"rsc", "IBM POWER RSC", bfd_arch_rs6000
,
2812 bfd_mach_rs6k_rsc
, &tdesc_rs6000
},
2813 {"rs2", "IBM POWER RS2", bfd_arch_rs6000
,
2814 bfd_mach_rs6k_rs2
, &tdesc_rs6000
},
2819 /* Return the variant corresponding to architecture ARCH and machine number
2820 MACH. If no such variant exists, return null. */
2822 static const struct variant
*
2823 find_variant_by_arch (enum bfd_architecture arch
, unsigned long mach
)
2825 const struct variant
*v
;
2827 for (v
= variants
; v
->name
; v
++)
2828 if (arch
== v
->arch
&& mach
== v
->mach
)
2835 gdb_print_insn_powerpc (bfd_vma memaddr
, disassemble_info
*info
)
2837 if (!info
->disassembler_options
)
2838 info
->disassembler_options
= "any";
2840 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
2841 return print_insn_big_powerpc (memaddr
, info
);
2843 return print_insn_little_powerpc (memaddr
, info
);
2847 rs6000_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2849 return frame_unwind_register_unsigned (next_frame
,
2850 gdbarch_pc_regnum (gdbarch
));
2853 static struct frame_id
2854 rs6000_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2856 return frame_id_build (frame_unwind_register_unsigned
2857 (next_frame
, gdbarch_sp_regnum (gdbarch
)),
2858 frame_pc_unwind (next_frame
));
2861 struct rs6000_frame_cache
2864 CORE_ADDR initial_sp
;
2865 struct trad_frame_saved_reg
*saved_regs
;
2868 static struct rs6000_frame_cache
*
2869 rs6000_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2871 struct rs6000_frame_cache
*cache
;
2872 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
2873 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2874 struct rs6000_framedata fdata
;
2875 int wordsize
= tdep
->wordsize
;
2878 if ((*this_cache
) != NULL
)
2879 return (*this_cache
);
2880 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
2881 (*this_cache
) = cache
;
2882 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
2884 func
= frame_func_unwind (next_frame
, NORMAL_FRAME
);
2885 pc
= frame_pc_unwind (next_frame
);
2886 skip_prologue (gdbarch
, func
, pc
, &fdata
);
2888 /* Figure out the parent's stack pointer. */
2890 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
2891 address of the current frame. Things might be easier if the
2892 ->frame pointed to the outer-most address of the frame. In
2893 the mean time, the address of the prev frame is used as the
2894 base address of this frame. */
2895 cache
->base
= frame_unwind_register_unsigned
2896 (next_frame
, gdbarch_sp_regnum (gdbarch
));
2898 /* If the function appears to be frameless, check a couple of likely
2899 indicators that we have simply failed to find the frame setup.
2900 Two common cases of this are missing symbols (i.e.
2901 frame_func_unwind returns the wrong address or 0), and assembly
2902 stubs which have a fast exit path but set up a frame on the slow
2905 If the LR appears to return to this function, then presume that
2906 we have an ABI compliant frame that we failed to find. */
2907 if (fdata
.frameless
&& fdata
.lr_offset
== 0)
2912 saved_lr
= frame_unwind_register_unsigned (next_frame
,
2913 tdep
->ppc_lr_regnum
);
2914 if (func
== 0 && saved_lr
== pc
)
2918 CORE_ADDR saved_func
= get_pc_function_start (saved_lr
);
2919 if (func
== saved_func
)
2925 fdata
.frameless
= 0;
2926 fdata
.lr_offset
= tdep
->lr_frame_offset
;
2930 if (!fdata
.frameless
)
2931 /* Frameless really means stackless. */
2932 cache
->base
= read_memory_addr (cache
->base
, wordsize
);
2934 trad_frame_set_value (cache
->saved_regs
,
2935 gdbarch_sp_regnum (gdbarch
), cache
->base
);
2937 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
2938 All fpr's from saved_fpr to fp31 are saved. */
2940 if (fdata
.saved_fpr
>= 0)
2943 CORE_ADDR fpr_addr
= cache
->base
+ fdata
.fpr_offset
;
2945 /* If skip_prologue says floating-point registers were saved,
2946 but the current architecture has no floating-point registers,
2947 then that's strange. But we have no indices to even record
2948 the addresses under, so we just ignore it. */
2949 if (ppc_floating_point_unit_p (gdbarch
))
2950 for (i
= fdata
.saved_fpr
; i
< ppc_num_fprs
; i
++)
2952 cache
->saved_regs
[tdep
->ppc_fp0_regnum
+ i
].addr
= fpr_addr
;
2957 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
2958 All gpr's from saved_gpr to gpr31 are saved. */
2960 if (fdata
.saved_gpr
>= 0)
2963 CORE_ADDR gpr_addr
= cache
->base
+ fdata
.gpr_offset
;
2964 for (i
= fdata
.saved_gpr
; i
< ppc_num_gprs
; i
++)
2966 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= gpr_addr
;
2967 gpr_addr
+= wordsize
;
2971 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
2972 All vr's from saved_vr to vr31 are saved. */
2973 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
2975 if (fdata
.saved_vr
>= 0)
2978 CORE_ADDR vr_addr
= cache
->base
+ fdata
.vr_offset
;
2979 for (i
= fdata
.saved_vr
; i
< 32; i
++)
2981 cache
->saved_regs
[tdep
->ppc_vr0_regnum
+ i
].addr
= vr_addr
;
2982 vr_addr
+= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
2987 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
2988 All vr's from saved_ev to ev31 are saved. ????? */
2989 if (tdep
->ppc_ev0_regnum
!= -1 && tdep
->ppc_ev31_regnum
!= -1)
2991 if (fdata
.saved_ev
>= 0)
2994 CORE_ADDR ev_addr
= cache
->base
+ fdata
.ev_offset
;
2995 for (i
= fdata
.saved_ev
; i
< ppc_num_gprs
; i
++)
2997 cache
->saved_regs
[tdep
->ppc_ev0_regnum
+ i
].addr
= ev_addr
;
2998 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= ev_addr
+ 4;
2999 ev_addr
+= register_size (gdbarch
, tdep
->ppc_ev0_regnum
);
3004 /* If != 0, fdata.cr_offset is the offset from the frame that
3006 if (fdata
.cr_offset
!= 0)
3007 cache
->saved_regs
[tdep
->ppc_cr_regnum
].addr
= cache
->base
+ fdata
.cr_offset
;
3009 /* If != 0, fdata.lr_offset is the offset from the frame that
3011 if (fdata
.lr_offset
!= 0)
3012 cache
->saved_regs
[tdep
->ppc_lr_regnum
].addr
= cache
->base
+ fdata
.lr_offset
;
3013 /* The PC is found in the link register. */
3014 cache
->saved_regs
[gdbarch_pc_regnum (gdbarch
)] =
3015 cache
->saved_regs
[tdep
->ppc_lr_regnum
];
3017 /* If != 0, fdata.vrsave_offset is the offset from the frame that
3018 holds the VRSAVE. */
3019 if (fdata
.vrsave_offset
!= 0)
3020 cache
->saved_regs
[tdep
->ppc_vrsave_regnum
].addr
= cache
->base
+ fdata
.vrsave_offset
;
3022 if (fdata
.alloca_reg
< 0)
3023 /* If no alloca register used, then fi->frame is the value of the
3024 %sp for this frame, and it is good enough. */
3025 cache
->initial_sp
= frame_unwind_register_unsigned
3026 (next_frame
, gdbarch_sp_regnum (gdbarch
));
3028 cache
->initial_sp
= frame_unwind_register_unsigned (next_frame
,
3035 rs6000_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
3036 struct frame_id
*this_id
)
3038 struct rs6000_frame_cache
*info
= rs6000_frame_cache (next_frame
,
3040 (*this_id
) = frame_id_build (info
->base
,
3041 frame_func_unwind (next_frame
, NORMAL_FRAME
));
3045 rs6000_frame_prev_register (struct frame_info
*next_frame
,
3047 int regnum
, int *optimizedp
,
3048 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
3049 int *realnump
, gdb_byte
*valuep
)
3051 struct rs6000_frame_cache
*info
= rs6000_frame_cache (next_frame
,
3053 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
3054 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
3057 static const struct frame_unwind rs6000_frame_unwind
=
3060 rs6000_frame_this_id
,
3061 rs6000_frame_prev_register
3064 static const struct frame_unwind
*
3065 rs6000_frame_sniffer (struct frame_info
*next_frame
)
3067 return &rs6000_frame_unwind
;
3073 rs6000_frame_base_address (struct frame_info
*next_frame
,
3076 struct rs6000_frame_cache
*info
= rs6000_frame_cache (next_frame
,
3078 return info
->initial_sp
;
3081 static const struct frame_base rs6000_frame_base
= {
3082 &rs6000_frame_unwind
,
3083 rs6000_frame_base_address
,
3084 rs6000_frame_base_address
,
3085 rs6000_frame_base_address
3088 static const struct frame_base
*
3089 rs6000_frame_base_sniffer (struct frame_info
*next_frame
)
3091 return &rs6000_frame_base
;
3094 /* DWARF-2 frame support. Used to handle the detection of
3095 clobbered registers during function calls. */
3098 ppc_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
3099 struct dwarf2_frame_state_reg
*reg
,
3100 struct frame_info
*next_frame
)
3102 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3104 /* PPC32 and PPC64 ABI's are the same regarding volatile and
3105 non-volatile registers. We will use the same code for both. */
3107 /* Call-saved GP registers. */
3108 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 14
3109 && regnum
<= tdep
->ppc_gp0_regnum
+ 31)
3110 || (regnum
== tdep
->ppc_gp0_regnum
+ 1))
3111 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3113 /* Call-clobbered GP registers. */
3114 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 3
3115 && regnum
<= tdep
->ppc_gp0_regnum
+ 12)
3116 || (regnum
== tdep
->ppc_gp0_regnum
))
3117 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3119 /* Deal with FP registers, if supported. */
3120 if (tdep
->ppc_fp0_regnum
>= 0)
3122 /* Call-saved FP registers. */
3123 if ((regnum
>= tdep
->ppc_fp0_regnum
+ 14
3124 && regnum
<= tdep
->ppc_fp0_regnum
+ 31))
3125 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3127 /* Call-clobbered FP registers. */
3128 if ((regnum
>= tdep
->ppc_fp0_regnum
3129 && regnum
<= tdep
->ppc_fp0_regnum
+ 13))
3130 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3133 /* Deal with ALTIVEC registers, if supported. */
3134 if (tdep
->ppc_vr0_regnum
> 0 && tdep
->ppc_vrsave_regnum
> 0)
3136 /* Call-saved Altivec registers. */
3137 if ((regnum
>= tdep
->ppc_vr0_regnum
+ 20
3138 && regnum
<= tdep
->ppc_vr0_regnum
+ 31)
3139 || regnum
== tdep
->ppc_vrsave_regnum
)
3140 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3142 /* Call-clobbered Altivec registers. */
3143 if ((regnum
>= tdep
->ppc_vr0_regnum
3144 && regnum
<= tdep
->ppc_vr0_regnum
+ 19))
3145 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3148 /* Handle PC register and Stack Pointer correctly. */
3149 if (regnum
== gdbarch_pc_regnum (gdbarch
))
3150 reg
->how
= DWARF2_FRAME_REG_RA
;
3151 else if (regnum
== gdbarch_sp_regnum (gdbarch
))
3152 reg
->how
= DWARF2_FRAME_REG_CFA
;
3156 /* Initialize the current architecture based on INFO. If possible, re-use an
3157 architecture from ARCHES, which is a list of architectures already created
3158 during this debugging session.
3160 Called e.g. at program startup, when reading a core file, and when reading
3163 static struct gdbarch
*
3164 rs6000_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
3166 struct gdbarch
*gdbarch
;
3167 struct gdbarch_tdep
*tdep
;
3168 int wordsize
, from_xcoff_exec
, from_elf_exec
;
3169 enum bfd_architecture arch
;
3174 enum auto_boolean soft_float_flag
= powerpc_soft_float_global
;
3176 enum powerpc_vector_abi vector_abi
= powerpc_vector_abi_global
;
3177 int have_fpu
= 1, have_spe
= 0, have_mq
= 0, have_altivec
= 0;
3178 int tdesc_wordsize
= -1;
3179 const struct target_desc
*tdesc
= info
.target_desc
;
3180 struct tdesc_arch_data
*tdesc_data
= NULL
;
3183 from_xcoff_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
3184 bfd_get_flavour (info
.abfd
) == bfd_target_xcoff_flavour
;
3186 from_elf_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
3187 bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
;
3189 sysv_abi
= info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
;
3191 /* Check word size. If INFO is from a binary file, infer it from
3192 that, else choose a likely default. */
3193 if (from_xcoff_exec
)
3195 if (bfd_xcoff_is_xcoff64 (info
.abfd
))
3200 else if (from_elf_exec
)
3202 if (elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
3207 else if (tdesc_has_registers (tdesc
))
3211 if (info
.bfd_arch_info
!= NULL
&& info
.bfd_arch_info
->bits_per_word
!= 0)
3212 wordsize
= info
.bfd_arch_info
->bits_per_word
/
3213 info
.bfd_arch_info
->bits_per_byte
;
3218 if (!from_xcoff_exec
)
3220 arch
= info
.bfd_arch_info
->arch
;
3221 mach
= info
.bfd_arch_info
->mach
;
3225 arch
= bfd_arch_powerpc
;
3226 bfd_default_set_arch_mach (&abfd
, arch
, 0);
3227 info
.bfd_arch_info
= bfd_get_arch_info (&abfd
);
3228 mach
= info
.bfd_arch_info
->mach
;
3231 /* For e500 executables, the apuinfo section is of help here. Such
3232 section contains the identifier and revision number of each
3233 Application-specific Processing Unit that is present on the
3234 chip. The content of the section is determined by the assembler
3235 which looks at each instruction and determines which unit (and
3236 which version of it) can execute it. In our case we just look for
3237 the existance of the section. */
3241 sect
= bfd_get_section_by_name (info
.abfd
, ".PPC.EMB.apuinfo");
3244 arch
= info
.bfd_arch_info
->arch
;
3245 mach
= bfd_mach_ppc_e500
;
3246 bfd_default_set_arch_mach (&abfd
, arch
, mach
);
3247 info
.bfd_arch_info
= bfd_get_arch_info (&abfd
);
3251 /* Find a default target description which describes our register
3252 layout, if we do not already have one. */
3253 if (! tdesc_has_registers (tdesc
))
3255 const struct variant
*v
;
3257 /* Choose variant. */
3258 v
= find_variant_by_arch (arch
, mach
);
3265 gdb_assert (tdesc_has_registers (tdesc
));
3267 /* Check any target description for validity. */
3268 if (tdesc_has_registers (tdesc
))
3270 static const char *const gprs
[] = {
3271 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
3272 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
3273 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
3274 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
3276 static const char *const segment_regs
[] = {
3277 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
3278 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
3280 const struct tdesc_feature
*feature
;
3282 static const char *const msr_names
[] = { "msr", "ps" };
3283 static const char *const cr_names
[] = { "cr", "cnd" };
3284 static const char *const ctr_names
[] = { "ctr", "cnt" };
3286 feature
= tdesc_find_feature (tdesc
,
3287 "org.gnu.gdb.power.core");
3288 if (feature
== NULL
)
3291 tdesc_data
= tdesc_data_alloc ();
3294 for (i
= 0; i
< ppc_num_gprs
; i
++)
3295 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
, gprs
[i
]);
3296 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_PC_REGNUM
,
3298 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_LR_REGNUM
,
3300 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_XER_REGNUM
,
3303 /* Allow alternate names for these registers, to accomodate GDB's
3305 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
3306 PPC_MSR_REGNUM
, msr_names
);
3307 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
3308 PPC_CR_REGNUM
, cr_names
);
3309 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
3310 PPC_CTR_REGNUM
, ctr_names
);
3314 tdesc_data_cleanup (tdesc_data
);
3318 have_mq
= tdesc_numbered_register (feature
, tdesc_data
, PPC_MQ_REGNUM
,
3321 tdesc_wordsize
= tdesc_register_size (feature
, "pc") / 8;
3323 wordsize
= tdesc_wordsize
;
3325 feature
= tdesc_find_feature (tdesc
,
3326 "org.gnu.gdb.power.fpu");
3327 if (feature
!= NULL
)
3329 static const char *const fprs
[] = {
3330 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
3331 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
3332 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
3333 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
3336 for (i
= 0; i
< ppc_num_fprs
; i
++)
3337 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
3338 PPC_F0_REGNUM
+ i
, fprs
[i
]);
3339 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
3340 PPC_FPSCR_REGNUM
, "fpscr");
3344 tdesc_data_cleanup (tdesc_data
);
3352 feature
= tdesc_find_feature (tdesc
,
3353 "org.gnu.gdb.power.altivec");
3354 if (feature
!= NULL
)
3356 static const char *const vector_regs
[] = {
3357 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
3358 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
3359 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
3360 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31"
3364 for (i
= 0; i
< ppc_num_gprs
; i
++)
3365 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
3368 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
3369 PPC_VSCR_REGNUM
, "vscr");
3370 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
3371 PPC_VRSAVE_REGNUM
, "vrsave");
3373 if (have_spe
|| !valid_p
)
3375 tdesc_data_cleanup (tdesc_data
);
3383 /* On machines supporting the SPE APU, the general-purpose registers
3384 are 64 bits long. There are SIMD vector instructions to treat them
3385 as pairs of floats, but the rest of the instruction set treats them
3386 as 32-bit registers, and only operates on their lower halves.
3388 In the GDB regcache, we treat their high and low halves as separate
3389 registers. The low halves we present as the general-purpose
3390 registers, and then we have pseudo-registers that stitch together
3391 the upper and lower halves and present them as pseudo-registers.
3393 Thus, the target description is expected to supply the upper
3394 halves separately. */
3396 feature
= tdesc_find_feature (tdesc
,
3397 "org.gnu.gdb.power.spe");
3398 if (feature
!= NULL
)
3400 static const char *const upper_spe
[] = {
3401 "ev0h", "ev1h", "ev2h", "ev3h",
3402 "ev4h", "ev5h", "ev6h", "ev7h",
3403 "ev8h", "ev9h", "ev10h", "ev11h",
3404 "ev12h", "ev13h", "ev14h", "ev15h",
3405 "ev16h", "ev17h", "ev18h", "ev19h",
3406 "ev20h", "ev21h", "ev22h", "ev23h",
3407 "ev24h", "ev25h", "ev26h", "ev27h",
3408 "ev28h", "ev29h", "ev30h", "ev31h"
3412 for (i
= 0; i
< ppc_num_gprs
; i
++)
3413 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
3414 PPC_SPE_UPPER_GP0_REGNUM
+ i
,
3416 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
3417 PPC_SPE_ACC_REGNUM
, "acc");
3418 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
3419 PPC_SPE_FSCR_REGNUM
, "spefscr");
3421 if (have_mq
|| have_fpu
|| !valid_p
)
3423 tdesc_data_cleanup (tdesc_data
);
3432 /* If we have a 64-bit binary on a 32-bit target, complain. Also
3433 complain for a 32-bit binary on a 64-bit target; we do not yet
3434 support that. For instance, the 32-bit ABI routines expect
3437 As long as there isn't an explicit target description, we'll
3438 choose one based on the BFD architecture and get a word size
3439 matching the binary (probably powerpc:common or
3440 powerpc:common64). So there is only trouble if a 64-bit target
3441 supplies a 64-bit description while debugging a 32-bit
3443 if (tdesc_wordsize
!= -1 && tdesc_wordsize
!= wordsize
)
3445 tdesc_data_cleanup (tdesc_data
);
3450 if (soft_float_flag
== AUTO_BOOLEAN_AUTO
&& from_elf_exec
)
3452 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
3453 Tag_GNU_Power_ABI_FP
))
3456 soft_float_flag
= AUTO_BOOLEAN_FALSE
;
3459 soft_float_flag
= AUTO_BOOLEAN_TRUE
;
3466 if (vector_abi
== POWERPC_VEC_AUTO
&& from_elf_exec
)
3468 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
3469 Tag_GNU_Power_ABI_Vector
))
3472 vector_abi
= POWERPC_VEC_GENERIC
;
3475 vector_abi
= POWERPC_VEC_ALTIVEC
;
3478 vector_abi
= POWERPC_VEC_SPE
;
3486 if (soft_float_flag
== AUTO_BOOLEAN_TRUE
)
3488 else if (soft_float_flag
== AUTO_BOOLEAN_FALSE
)
3491 soft_float
= !have_fpu
;
3493 /* If we have a hard float binary or setting but no floating point
3494 registers, downgrade to soft float anyway. We're still somewhat
3495 useful in this scenario. */
3496 if (!soft_float
&& !have_fpu
)
3499 /* Similarly for vector registers. */
3500 if (vector_abi
== POWERPC_VEC_ALTIVEC
&& !have_altivec
)
3501 vector_abi
= POWERPC_VEC_GENERIC
;
3503 if (vector_abi
== POWERPC_VEC_SPE
&& !have_spe
)
3504 vector_abi
= POWERPC_VEC_GENERIC
;
3506 if (vector_abi
== POWERPC_VEC_AUTO
)
3509 vector_abi
= POWERPC_VEC_ALTIVEC
;
3511 vector_abi
= POWERPC_VEC_SPE
;
3513 vector_abi
= POWERPC_VEC_GENERIC
;
3516 /* Do not limit the vector ABI based on available hardware, since we
3517 do not yet know what hardware we'll decide we have. Yuck! FIXME! */
3519 /* Find a candidate among extant architectures. */
3520 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
3522 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
3524 /* Word size in the various PowerPC bfd_arch_info structs isn't
3525 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
3526 separate word size check. */
3527 tdep
= gdbarch_tdep (arches
->gdbarch
);
3528 if (tdep
&& tdep
->soft_float
!= soft_float
)
3530 if (tdep
&& tdep
->vector_abi
!= vector_abi
)
3532 if (tdep
&& tdep
->wordsize
== wordsize
)
3534 if (tdesc_data
!= NULL
)
3535 tdesc_data_cleanup (tdesc_data
);
3536 return arches
->gdbarch
;
3540 /* None found, create a new architecture from INFO, whose bfd_arch_info
3541 validity depends on the source:
3542 - executable useless
3543 - rs6000_host_arch() good
3545 - "set arch" trust blindly
3546 - GDB startup useless but harmless */
3548 tdep
= XCALLOC (1, struct gdbarch_tdep
);
3549 tdep
->wordsize
= wordsize
;
3550 tdep
->soft_float
= soft_float
;
3551 tdep
->vector_abi
= vector_abi
;
3553 gdbarch
= gdbarch_alloc (&info
, tdep
);
3555 tdep
->ppc_gp0_regnum
= PPC_R0_REGNUM
;
3556 tdep
->ppc_toc_regnum
= PPC_R0_REGNUM
+ 2;
3557 tdep
->ppc_ps_regnum
= PPC_MSR_REGNUM
;
3558 tdep
->ppc_cr_regnum
= PPC_CR_REGNUM
;
3559 tdep
->ppc_lr_regnum
= PPC_LR_REGNUM
;
3560 tdep
->ppc_ctr_regnum
= PPC_CTR_REGNUM
;
3561 tdep
->ppc_xer_regnum
= PPC_XER_REGNUM
;
3562 tdep
->ppc_mq_regnum
= have_mq
? PPC_MQ_REGNUM
: -1;
3564 tdep
->ppc_fp0_regnum
= have_fpu
? PPC_F0_REGNUM
: -1;
3565 tdep
->ppc_fpscr_regnum
= have_fpu
? PPC_FPSCR_REGNUM
: -1;
3566 tdep
->ppc_vr0_regnum
= have_altivec
? PPC_VR0_REGNUM
: -1;
3567 tdep
->ppc_vrsave_regnum
= have_altivec
? PPC_VRSAVE_REGNUM
: -1;
3568 tdep
->ppc_ev0_upper_regnum
= have_spe
? PPC_SPE_UPPER_GP0_REGNUM
: -1;
3569 tdep
->ppc_acc_regnum
= have_spe
? PPC_SPE_ACC_REGNUM
: -1;
3570 tdep
->ppc_spefscr_regnum
= have_spe
? PPC_SPE_FSCR_REGNUM
: -1;
3572 set_gdbarch_pc_regnum (gdbarch
, PPC_PC_REGNUM
);
3573 set_gdbarch_sp_regnum (gdbarch
, PPC_R0_REGNUM
+ 1);
3574 set_gdbarch_deprecated_fp_regnum (gdbarch
, PPC_R0_REGNUM
+ 1);
3575 set_gdbarch_fp0_regnum (gdbarch
, tdep
->ppc_fp0_regnum
);
3576 set_gdbarch_register_sim_regno (gdbarch
, rs6000_register_sim_regno
);
3578 /* The XML specification for PowerPC sensibly calls the MSR "msr".
3579 GDB traditionally called it "ps", though, so let GDB add an
3581 set_gdbarch_ps_regnum (gdbarch
, tdep
->ppc_ps_regnum
);
3583 if (sysv_abi
&& wordsize
== 8)
3584 set_gdbarch_return_value (gdbarch
, ppc64_sysv_abi_return_value
);
3585 else if (sysv_abi
&& wordsize
== 4)
3586 set_gdbarch_return_value (gdbarch
, ppc_sysv_abi_return_value
);
3588 set_gdbarch_return_value (gdbarch
, rs6000_return_value
);
3590 /* Set lr_frame_offset. */
3592 tdep
->lr_frame_offset
= 16;
3594 tdep
->lr_frame_offset
= 4;
3596 tdep
->lr_frame_offset
= 8;
3600 set_gdbarch_pseudo_register_read (gdbarch
, e500_pseudo_register_read
);
3601 set_gdbarch_pseudo_register_write (gdbarch
, e500_pseudo_register_write
);
3604 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
3606 /* Select instruction printer. */
3607 if (arch
== bfd_arch_rs6000
)
3608 set_gdbarch_print_insn (gdbarch
, print_insn_rs6000
);
3610 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_powerpc
);
3612 set_gdbarch_num_regs (gdbarch
, PPC_NUM_REGS
+ num_sprs
);
3613 set_gdbarch_num_pseudo_regs (gdbarch
, have_spe
? 32 : 0);
3615 set_gdbarch_ptr_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
3616 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
3617 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
3618 set_gdbarch_long_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
3619 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
3620 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
3621 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
3623 set_gdbarch_long_double_bit (gdbarch
, 16 * TARGET_CHAR_BIT
);
3625 set_gdbarch_long_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
3626 set_gdbarch_char_signed (gdbarch
, 0);
3628 set_gdbarch_frame_align (gdbarch
, rs6000_frame_align
);
3629 if (sysv_abi
&& wordsize
== 8)
3631 set_gdbarch_frame_red_zone_size (gdbarch
, 288);
3632 else if (!sysv_abi
&& wordsize
== 4)
3633 /* PowerOpen / AIX 32 bit. The saved area or red zone consists of
3634 19 4 byte GPRS + 18 8 byte FPRs giving a total of 220 bytes.
3635 Problem is, 220 isn't frame (16 byte) aligned. Round it up to
3637 set_gdbarch_frame_red_zone_size (gdbarch
, 224);
3639 set_gdbarch_convert_register_p (gdbarch
, rs6000_convert_register_p
);
3640 set_gdbarch_register_to_value (gdbarch
, rs6000_register_to_value
);
3641 set_gdbarch_value_to_register (gdbarch
, rs6000_value_to_register
);
3643 set_gdbarch_stab_reg_to_regnum (gdbarch
, rs6000_stab_reg_to_regnum
);
3644 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, rs6000_dwarf2_reg_to_regnum
);
3646 if (sysv_abi
&& wordsize
== 4)
3647 set_gdbarch_push_dummy_call (gdbarch
, ppc_sysv_abi_push_dummy_call
);
3648 else if (sysv_abi
&& wordsize
== 8)
3649 set_gdbarch_push_dummy_call (gdbarch
, ppc64_sysv_abi_push_dummy_call
);
3651 set_gdbarch_push_dummy_call (gdbarch
, rs6000_push_dummy_call
);
3653 set_gdbarch_skip_prologue (gdbarch
, rs6000_skip_prologue
);
3654 set_gdbarch_in_function_epilogue_p (gdbarch
, rs6000_in_function_epilogue_p
);
3656 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3657 set_gdbarch_breakpoint_from_pc (gdbarch
, rs6000_breakpoint_from_pc
);
3659 /* The value of symbols of type N_SO and N_FUN maybe null when
3661 set_gdbarch_sofun_address_maybe_missing (gdbarch
, 1);
3663 /* Handles single stepping of atomic sequences. */
3664 set_gdbarch_software_single_step (gdbarch
, deal_with_atomic_sequence
);
3666 /* Handle the 64-bit SVR4 minimal-symbol convention of using "FN"
3667 for the descriptor and ".FN" for the entry-point -- a user
3668 specifying "break FN" will unexpectedly end up with a breakpoint
3669 on the descriptor and not the function. This architecture method
3670 transforms any breakpoints on descriptors into breakpoints on the
3671 corresponding entry point. */
3672 if (sysv_abi
&& wordsize
== 8)
3673 set_gdbarch_adjust_breakpoint_address (gdbarch
, ppc64_sysv_abi_adjust_breakpoint_address
);
3675 /* Not sure on this. FIXMEmgo */
3676 set_gdbarch_frame_args_skip (gdbarch
, 8);
3680 /* Handle RS/6000 function pointers (which are really function
3682 set_gdbarch_convert_from_func_ptr_addr (gdbarch
,
3683 rs6000_convert_from_func_ptr_addr
);
3686 /* Helpers for function argument information. */
3687 set_gdbarch_fetch_pointer_argument (gdbarch
, rs6000_fetch_pointer_argument
);
3690 set_gdbarch_in_solib_return_trampoline
3691 (gdbarch
, rs6000_in_solib_return_trampoline
);
3692 set_gdbarch_skip_trampoline_code (gdbarch
, rs6000_skip_trampoline_code
);
3694 /* Hook in the DWARF CFI frame unwinder. */
3695 frame_unwind_append_sniffer (gdbarch
, dwarf2_frame_sniffer
);
3696 dwarf2_frame_set_adjust_regnum (gdbarch
, rs6000_adjust_frame_regnum
);
3698 /* Frame handling. */
3699 dwarf2_frame_set_init_reg (gdbarch
, ppc_dwarf2_frame_init_reg
);
3701 /* Hook in ABI-specific overrides, if they have been registered. */
3702 gdbarch_init_osabi (info
, gdbarch
);
3706 case GDB_OSABI_LINUX
:
3707 case GDB_OSABI_NETBSD_AOUT
:
3708 case GDB_OSABI_NETBSD_ELF
:
3709 case GDB_OSABI_UNKNOWN
:
3710 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
3711 frame_unwind_append_sniffer (gdbarch
, rs6000_frame_sniffer
);
3712 set_gdbarch_unwind_dummy_id (gdbarch
, rs6000_unwind_dummy_id
);
3713 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
3716 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
3718 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
3719 frame_unwind_append_sniffer (gdbarch
, rs6000_frame_sniffer
);
3720 set_gdbarch_unwind_dummy_id (gdbarch
, rs6000_unwind_dummy_id
);
3721 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
3724 set_tdesc_pseudo_register_type (gdbarch
, rs6000_pseudo_register_type
);
3725 set_tdesc_pseudo_register_reggroup_p (gdbarch
,
3726 rs6000_pseudo_register_reggroup_p
);
3727 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
3729 /* Override the normal target description method to make the SPE upper
3730 halves anonymous. */
3731 set_gdbarch_register_name (gdbarch
, rs6000_register_name
);
3733 /* Recording the numbering of pseudo registers. */
3734 tdep
->ppc_ev0_regnum
= have_spe
? gdbarch_num_regs (gdbarch
) : -1;
3735 tdep
->ppc_ev31_regnum
= have_spe
? tdep
->ppc_ev0_regnum
+ 31 : -1;
3741 rs6000_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
3743 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3748 /* FIXME: Dump gdbarch_tdep. */
3751 /* PowerPC-specific commands. */
3754 set_powerpc_command (char *args
, int from_tty
)
3756 printf_unfiltered (_("\
3757 \"set powerpc\" must be followed by an appropriate subcommand.\n"));
3758 help_list (setpowerpccmdlist
, "set powerpc ", all_commands
, gdb_stdout
);
3762 show_powerpc_command (char *args
, int from_tty
)
3764 cmd_show_list (showpowerpccmdlist
, from_tty
, "");
3768 powerpc_set_soft_float (char *args
, int from_tty
,
3769 struct cmd_list_element
*c
)
3771 struct gdbarch_info info
;
3773 /* Update the architecture. */
3774 gdbarch_info_init (&info
);
3775 if (!gdbarch_update_p (info
))
3776 internal_error (__FILE__
, __LINE__
, "could not update architecture");
3780 powerpc_set_vector_abi (char *args
, int from_tty
,
3781 struct cmd_list_element
*c
)
3783 struct gdbarch_info info
;
3784 enum powerpc_vector_abi vector_abi
;
3786 for (vector_abi
= POWERPC_VEC_AUTO
;
3787 vector_abi
!= POWERPC_VEC_LAST
;
3789 if (strcmp (powerpc_vector_abi_string
,
3790 powerpc_vector_strings
[vector_abi
]) == 0)
3792 powerpc_vector_abi_global
= vector_abi
;
3796 if (vector_abi
== POWERPC_VEC_LAST
)
3797 internal_error (__FILE__
, __LINE__
, _("Invalid vector ABI accepted: %s."),
3798 powerpc_vector_abi_string
);
3800 /* Update the architecture. */
3801 gdbarch_info_init (&info
);
3802 if (!gdbarch_update_p (info
))
3803 internal_error (__FILE__
, __LINE__
, "could not update architecture");
3806 /* Initialization code. */
3808 extern initialize_file_ftype _initialize_rs6000_tdep
; /* -Wmissing-prototypes */
3811 _initialize_rs6000_tdep (void)
3813 gdbarch_register (bfd_arch_rs6000
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
3814 gdbarch_register (bfd_arch_powerpc
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
3816 /* Initialize the standard target descriptions. */
3817 initialize_tdesc_powerpc_32 ();
3818 initialize_tdesc_powerpc_403 ();
3819 initialize_tdesc_powerpc_403gc ();
3820 initialize_tdesc_powerpc_505 ();
3821 initialize_tdesc_powerpc_601 ();
3822 initialize_tdesc_powerpc_602 ();
3823 initialize_tdesc_powerpc_603 ();
3824 initialize_tdesc_powerpc_604 ();
3825 initialize_tdesc_powerpc_64 ();
3826 initialize_tdesc_powerpc_7400 ();
3827 initialize_tdesc_powerpc_750 ();
3828 initialize_tdesc_powerpc_860 ();
3829 initialize_tdesc_powerpc_e500 ();
3830 initialize_tdesc_rs6000 ();
3832 /* Add root prefix command for all "set powerpc"/"show powerpc"
3834 add_prefix_cmd ("powerpc", no_class
, set_powerpc_command
,
3835 _("Various PowerPC-specific commands."),
3836 &setpowerpccmdlist
, "set powerpc ", 0, &setlist
);
3838 add_prefix_cmd ("powerpc", no_class
, show_powerpc_command
,
3839 _("Various PowerPC-specific commands."),
3840 &showpowerpccmdlist
, "show powerpc ", 0, &showlist
);
3842 /* Add a command to allow the user to force the ABI. */
3843 add_setshow_auto_boolean_cmd ("soft-float", class_support
,
3844 &powerpc_soft_float_global
,
3845 _("Set whether to use a soft-float ABI."),
3846 _("Show whether to use a soft-float ABI."),
3848 powerpc_set_soft_float
, NULL
,
3849 &setpowerpccmdlist
, &showpowerpccmdlist
);
3851 add_setshow_enum_cmd ("vector-abi", class_support
, powerpc_vector_strings
,
3852 &powerpc_vector_abi_string
,
3853 _("Set the vector ABI."),
3854 _("Show the vector ABI."),
3855 NULL
, powerpc_set_vector_abi
, NULL
,
3856 &setpowerpccmdlist
, &showpowerpccmdlist
);