1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
30 #include "arch-utils.h"
35 #include "parser-defs.h"
38 #include "sim-regno.h"
39 #include "gdb/sim-ppc.h"
40 #include "reggroups.h"
41 #include "dwarf2-frame.h"
42 #include "target-descriptions.h"
43 #include "user-regs.h"
45 #include "libbfd.h" /* for bfd_default_set_arch_mach */
46 #include "coff/internal.h" /* for libcoff.h */
47 #include "libcoff.h" /* for xcoff_data */
48 #include "coff/xcoff.h"
54 #include "solib-svr4.h"
57 #include "gdb_assert.h"
60 #include "trad-frame.h"
61 #include "frame-unwind.h"
62 #include "frame-base.h"
64 #include "features/rs6000/powerpc-32.c"
65 #include "features/rs6000/powerpc-altivec32.c"
66 #include "features/rs6000/powerpc-vsx32.c"
67 #include "features/rs6000/powerpc-403.c"
68 #include "features/rs6000/powerpc-403gc.c"
69 #include "features/rs6000/powerpc-405.c"
70 #include "features/rs6000/powerpc-505.c"
71 #include "features/rs6000/powerpc-601.c"
72 #include "features/rs6000/powerpc-602.c"
73 #include "features/rs6000/powerpc-603.c"
74 #include "features/rs6000/powerpc-604.c"
75 #include "features/rs6000/powerpc-64.c"
76 #include "features/rs6000/powerpc-altivec64.c"
77 #include "features/rs6000/powerpc-vsx64.c"
78 #include "features/rs6000/powerpc-7400.c"
79 #include "features/rs6000/powerpc-750.c"
80 #include "features/rs6000/powerpc-860.c"
81 #include "features/rs6000/powerpc-e500.c"
82 #include "features/rs6000/rs6000.c"
84 /* Determine if regnum is an SPE pseudo-register. */
85 #define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \
86 && (regnum) >= (tdep)->ppc_ev0_regnum \
87 && (regnum) < (tdep)->ppc_ev0_regnum + 32)
89 /* Determine if regnum is a decimal float pseudo-register. */
90 #define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \
91 && (regnum) >= (tdep)->ppc_dl0_regnum \
92 && (regnum) < (tdep)->ppc_dl0_regnum + 16)
94 /* Determine if regnum is a POWER7 VSX register. */
95 #define IS_VSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_vsr0_regnum >= 0 \
96 && (regnum) >= (tdep)->ppc_vsr0_regnum \
97 && (regnum) < (tdep)->ppc_vsr0_regnum + ppc_num_vsrs)
99 /* Determine if regnum is a POWER7 Extended FP register. */
100 #define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \
101 && (regnum) >= (tdep)->ppc_efpr0_regnum \
102 && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_fprs)
104 /* The list of available "set powerpc ..." and "show powerpc ..."
106 static struct cmd_list_element
*setpowerpccmdlist
= NULL
;
107 static struct cmd_list_element
*showpowerpccmdlist
= NULL
;
109 static enum auto_boolean powerpc_soft_float_global
= AUTO_BOOLEAN_AUTO
;
111 /* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */
112 static const char *powerpc_vector_strings
[] =
121 /* A variable that can be configured by the user. */
122 static enum powerpc_vector_abi powerpc_vector_abi_global
= POWERPC_VEC_AUTO
;
123 static const char *powerpc_vector_abi_string
= "auto";
125 /* To be used by skip_prologue. */
127 struct rs6000_framedata
129 int offset
; /* total size of frame --- the distance
130 by which we decrement sp to allocate
132 int saved_gpr
; /* smallest # of saved gpr */
133 unsigned int gpr_mask
; /* Each bit is an individual saved GPR. */
134 int saved_fpr
; /* smallest # of saved fpr */
135 int saved_vr
; /* smallest # of saved vr */
136 int saved_ev
; /* smallest # of saved ev */
137 int alloca_reg
; /* alloca register number (frame ptr) */
138 char frameless
; /* true if frameless functions. */
139 char nosavedpc
; /* true if pc not saved. */
140 char used_bl
; /* true if link register clobbered */
141 int gpr_offset
; /* offset of saved gprs from prev sp */
142 int fpr_offset
; /* offset of saved fprs from prev sp */
143 int vr_offset
; /* offset of saved vrs from prev sp */
144 int ev_offset
; /* offset of saved evs from prev sp */
145 int lr_offset
; /* offset of saved lr */
146 int lr_register
; /* register of saved lr, if trustworthy */
147 int cr_offset
; /* offset of saved cr */
148 int vrsave_offset
; /* offset of saved vrsave register */
152 /* Is REGNO a VSX register? Return 1 if so, 0 otherwise. */
154 vsx_register_p (struct gdbarch
*gdbarch
, int regno
)
156 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
157 if (tdep
->ppc_vsr0_regnum
< 0)
160 return (regno
>= tdep
->ppc_vsr0_upper_regnum
&& regno
161 <= tdep
->ppc_vsr0_upper_regnum
+ 31);
164 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
166 altivec_register_p (struct gdbarch
*gdbarch
, int regno
)
168 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
169 if (tdep
->ppc_vr0_regnum
< 0 || tdep
->ppc_vrsave_regnum
< 0)
172 return (regno
>= tdep
->ppc_vr0_regnum
&& regno
<= tdep
->ppc_vrsave_regnum
);
176 /* Return true if REGNO is an SPE register, false otherwise. */
178 spe_register_p (struct gdbarch
*gdbarch
, int regno
)
180 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
182 /* Is it a reference to EV0 -- EV31, and do we have those? */
183 if (IS_SPE_PSEUDOREG (tdep
, regno
))
186 /* Is it a reference to one of the raw upper GPR halves? */
187 if (tdep
->ppc_ev0_upper_regnum
>= 0
188 && tdep
->ppc_ev0_upper_regnum
<= regno
189 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
192 /* Is it a reference to the 64-bit accumulator, and do we have that? */
193 if (tdep
->ppc_acc_regnum
>= 0
194 && tdep
->ppc_acc_regnum
== regno
)
197 /* Is it a reference to the SPE floating-point status and control register,
198 and do we have that? */
199 if (tdep
->ppc_spefscr_regnum
>= 0
200 && tdep
->ppc_spefscr_regnum
== regno
)
207 /* Return non-zero if the architecture described by GDBARCH has
208 floating-point registers (f0 --- f31 and fpscr). */
210 ppc_floating_point_unit_p (struct gdbarch
*gdbarch
)
212 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
214 return (tdep
->ppc_fp0_regnum
>= 0
215 && tdep
->ppc_fpscr_regnum
>= 0);
218 /* Return non-zero if the architecture described by GDBARCH has
219 VSX registers (vsr0 --- vsr63). */
221 ppc_vsx_support_p (struct gdbarch
*gdbarch
)
223 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
225 return tdep
->ppc_vsr0_regnum
>= 0;
228 /* Return non-zero if the architecture described by GDBARCH has
229 Altivec registers (vr0 --- vr31, vrsave and vscr). */
231 ppc_altivec_support_p (struct gdbarch
*gdbarch
)
233 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
235 return (tdep
->ppc_vr0_regnum
>= 0
236 && tdep
->ppc_vrsave_regnum
>= 0);
239 /* Check that TABLE[GDB_REGNO] is not already initialized, and then
242 This is a helper function for init_sim_regno_table, constructing
243 the table mapping GDB register numbers to sim register numbers; we
244 initialize every element in that table to -1 before we start
247 set_sim_regno (int *table
, int gdb_regno
, int sim_regno
)
249 /* Make sure we don't try to assign any given GDB register a sim
250 register number more than once. */
251 gdb_assert (table
[gdb_regno
] == -1);
252 table
[gdb_regno
] = sim_regno
;
256 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
257 numbers to simulator register numbers, based on the values placed
258 in the ARCH->tdep->ppc_foo_regnum members. */
260 init_sim_regno_table (struct gdbarch
*arch
)
262 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
263 int total_regs
= gdbarch_num_regs (arch
);
264 int *sim_regno
= GDBARCH_OBSTACK_CALLOC (arch
, total_regs
, int);
266 static const char *const segment_regs
[] = {
267 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
268 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
271 /* Presume that all registers not explicitly mentioned below are
272 unavailable from the sim. */
273 for (i
= 0; i
< total_regs
; i
++)
276 /* General-purpose registers. */
277 for (i
= 0; i
< ppc_num_gprs
; i
++)
278 set_sim_regno (sim_regno
, tdep
->ppc_gp0_regnum
+ i
, sim_ppc_r0_regnum
+ i
);
280 /* Floating-point registers. */
281 if (tdep
->ppc_fp0_regnum
>= 0)
282 for (i
= 0; i
< ppc_num_fprs
; i
++)
283 set_sim_regno (sim_regno
,
284 tdep
->ppc_fp0_regnum
+ i
,
285 sim_ppc_f0_regnum
+ i
);
286 if (tdep
->ppc_fpscr_regnum
>= 0)
287 set_sim_regno (sim_regno
, tdep
->ppc_fpscr_regnum
, sim_ppc_fpscr_regnum
);
289 set_sim_regno (sim_regno
, gdbarch_pc_regnum (arch
), sim_ppc_pc_regnum
);
290 set_sim_regno (sim_regno
, tdep
->ppc_ps_regnum
, sim_ppc_ps_regnum
);
291 set_sim_regno (sim_regno
, tdep
->ppc_cr_regnum
, sim_ppc_cr_regnum
);
293 /* Segment registers. */
294 for (i
= 0; i
< ppc_num_srs
; i
++)
298 gdb_regno
= user_reg_map_name_to_regnum (arch
, segment_regs
[i
], -1);
300 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_sr0_regnum
+ i
);
303 /* Altivec registers. */
304 if (tdep
->ppc_vr0_regnum
>= 0)
306 for (i
= 0; i
< ppc_num_vrs
; i
++)
307 set_sim_regno (sim_regno
,
308 tdep
->ppc_vr0_regnum
+ i
,
309 sim_ppc_vr0_regnum
+ i
);
311 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
312 we can treat this more like the other cases. */
313 set_sim_regno (sim_regno
,
314 tdep
->ppc_vr0_regnum
+ ppc_num_vrs
,
315 sim_ppc_vscr_regnum
);
317 /* vsave is a special-purpose register, so the code below handles it. */
319 /* SPE APU (E500) registers. */
320 if (tdep
->ppc_ev0_upper_regnum
>= 0)
321 for (i
= 0; i
< ppc_num_gprs
; i
++)
322 set_sim_regno (sim_regno
,
323 tdep
->ppc_ev0_upper_regnum
+ i
,
324 sim_ppc_rh0_regnum
+ i
);
325 if (tdep
->ppc_acc_regnum
>= 0)
326 set_sim_regno (sim_regno
, tdep
->ppc_acc_regnum
, sim_ppc_acc_regnum
);
327 /* spefscr is a special-purpose register, so the code below handles it. */
330 /* Now handle all special-purpose registers. Verify that they
331 haven't mistakenly been assigned numbers by any of the above
333 for (i
= 0; i
< sim_ppc_num_sprs
; i
++)
335 const char *spr_name
= sim_spr_register_name (i
);
338 if (spr_name
!= NULL
)
339 gdb_regno
= user_reg_map_name_to_regnum (arch
, spr_name
, -1);
342 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_spr0_regnum
+ i
);
346 /* Drop the initialized array into place. */
347 tdep
->sim_regno
= sim_regno
;
351 /* Given a GDB register number REG, return the corresponding SIM
354 rs6000_register_sim_regno (struct gdbarch
*gdbarch
, int reg
)
356 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
359 if (tdep
->sim_regno
== NULL
)
360 init_sim_regno_table (gdbarch
);
363 && reg
<= gdbarch_num_regs (gdbarch
)
364 + gdbarch_num_pseudo_regs (gdbarch
));
365 sim_regno
= tdep
->sim_regno
[reg
];
370 return LEGACY_SIM_REGNO_IGNORE
;
375 /* Register set support functions. */
377 /* REGS + OFFSET contains register REGNUM in a field REGSIZE wide.
378 Write the register to REGCACHE. */
381 ppc_supply_reg (struct regcache
*regcache
, int regnum
,
382 const gdb_byte
*regs
, size_t offset
, int regsize
)
384 if (regnum
!= -1 && offset
!= -1)
388 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
389 int gdb_regsize
= register_size (gdbarch
, regnum
);
390 if (gdb_regsize
< regsize
391 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
392 offset
+= regsize
- gdb_regsize
;
394 regcache_raw_supply (regcache
, regnum
, regs
+ offset
);
398 /* Read register REGNUM from REGCACHE and store to REGS + OFFSET
399 in a field REGSIZE wide. Zero pad as necessary. */
402 ppc_collect_reg (const struct regcache
*regcache
, int regnum
,
403 gdb_byte
*regs
, size_t offset
, int regsize
)
405 if (regnum
!= -1 && offset
!= -1)
409 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
410 int gdb_regsize
= register_size (gdbarch
, regnum
);
411 if (gdb_regsize
< regsize
)
413 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
415 memset (regs
+ offset
, 0, regsize
- gdb_regsize
);
416 offset
+= regsize
- gdb_regsize
;
419 memset (regs
+ offset
+ regsize
- gdb_regsize
, 0,
420 regsize
- gdb_regsize
);
423 regcache_raw_collect (regcache
, regnum
, regs
+ offset
);
428 ppc_greg_offset (struct gdbarch
*gdbarch
,
429 struct gdbarch_tdep
*tdep
,
430 const struct ppc_reg_offsets
*offsets
,
434 *regsize
= offsets
->gpr_size
;
435 if (regnum
>= tdep
->ppc_gp0_regnum
436 && regnum
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
)
437 return (offsets
->r0_offset
438 + (regnum
- tdep
->ppc_gp0_regnum
) * offsets
->gpr_size
);
440 if (regnum
== gdbarch_pc_regnum (gdbarch
))
441 return offsets
->pc_offset
;
443 if (regnum
== tdep
->ppc_ps_regnum
)
444 return offsets
->ps_offset
;
446 if (regnum
== tdep
->ppc_lr_regnum
)
447 return offsets
->lr_offset
;
449 if (regnum
== tdep
->ppc_ctr_regnum
)
450 return offsets
->ctr_offset
;
452 *regsize
= offsets
->xr_size
;
453 if (regnum
== tdep
->ppc_cr_regnum
)
454 return offsets
->cr_offset
;
456 if (regnum
== tdep
->ppc_xer_regnum
)
457 return offsets
->xer_offset
;
459 if (regnum
== tdep
->ppc_mq_regnum
)
460 return offsets
->mq_offset
;
466 ppc_fpreg_offset (struct gdbarch_tdep
*tdep
,
467 const struct ppc_reg_offsets
*offsets
,
470 if (regnum
>= tdep
->ppc_fp0_regnum
471 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
)
472 return offsets
->f0_offset
+ (regnum
- tdep
->ppc_fp0_regnum
) * 8;
474 if (regnum
== tdep
->ppc_fpscr_regnum
)
475 return offsets
->fpscr_offset
;
481 ppc_vrreg_offset (struct gdbarch_tdep
*tdep
,
482 const struct ppc_reg_offsets
*offsets
,
485 if (regnum
>= tdep
->ppc_vr0_regnum
486 && regnum
< tdep
->ppc_vr0_regnum
+ ppc_num_vrs
)
487 return offsets
->vr0_offset
+ (regnum
- tdep
->ppc_vr0_regnum
) * 16;
489 if (regnum
== tdep
->ppc_vrsave_regnum
- 1)
490 return offsets
->vscr_offset
;
492 if (regnum
== tdep
->ppc_vrsave_regnum
)
493 return offsets
->vrsave_offset
;
498 /* Supply register REGNUM in the general-purpose register set REGSET
499 from the buffer specified by GREGS and LEN to register cache
500 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
503 ppc_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
504 int regnum
, const void *gregs
, size_t len
)
506 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
507 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
508 const struct ppc_reg_offsets
*offsets
= regset
->descr
;
515 int gpr_size
= offsets
->gpr_size
;
517 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
518 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
519 i
++, offset
+= gpr_size
)
520 ppc_supply_reg (regcache
, i
, gregs
, offset
, gpr_size
);
522 ppc_supply_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
523 gregs
, offsets
->pc_offset
, gpr_size
);
524 ppc_supply_reg (regcache
, tdep
->ppc_ps_regnum
,
525 gregs
, offsets
->ps_offset
, gpr_size
);
526 ppc_supply_reg (regcache
, tdep
->ppc_lr_regnum
,
527 gregs
, offsets
->lr_offset
, gpr_size
);
528 ppc_supply_reg (regcache
, tdep
->ppc_ctr_regnum
,
529 gregs
, offsets
->ctr_offset
, gpr_size
);
530 ppc_supply_reg (regcache
, tdep
->ppc_cr_regnum
,
531 gregs
, offsets
->cr_offset
, offsets
->xr_size
);
532 ppc_supply_reg (regcache
, tdep
->ppc_xer_regnum
,
533 gregs
, offsets
->xer_offset
, offsets
->xr_size
);
534 ppc_supply_reg (regcache
, tdep
->ppc_mq_regnum
,
535 gregs
, offsets
->mq_offset
, offsets
->xr_size
);
539 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
540 ppc_supply_reg (regcache
, regnum
, gregs
, offset
, regsize
);
543 /* Supply register REGNUM in the floating-point register set REGSET
544 from the buffer specified by FPREGS and LEN to register cache
545 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
548 ppc_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
549 int regnum
, const void *fpregs
, size_t len
)
551 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
552 struct gdbarch_tdep
*tdep
;
553 const struct ppc_reg_offsets
*offsets
;
556 if (!ppc_floating_point_unit_p (gdbarch
))
559 tdep
= gdbarch_tdep (gdbarch
);
560 offsets
= regset
->descr
;
565 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
566 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
568 ppc_supply_reg (regcache
, i
, fpregs
, offset
, 8);
570 ppc_supply_reg (regcache
, tdep
->ppc_fpscr_regnum
,
571 fpregs
, offsets
->fpscr_offset
, offsets
->fpscr_size
);
575 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
576 ppc_supply_reg (regcache
, regnum
, fpregs
, offset
,
577 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
580 /* Supply register REGNUM in the VSX register set REGSET
581 from the buffer specified by VSXREGS and LEN to register cache
582 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
585 ppc_supply_vsxregset (const struct regset
*regset
, struct regcache
*regcache
,
586 int regnum
, const void *vsxregs
, size_t len
)
588 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
589 struct gdbarch_tdep
*tdep
;
591 if (!ppc_vsx_support_p (gdbarch
))
594 tdep
= gdbarch_tdep (gdbarch
);
600 for (i
= tdep
->ppc_vsr0_upper_regnum
;
601 i
< tdep
->ppc_vsr0_upper_regnum
+ 32;
603 ppc_supply_reg (regcache
, i
, vsxregs
, 0, 8);
608 ppc_supply_reg (regcache
, regnum
, vsxregs
, 0, 8);
611 /* Supply register REGNUM in the Altivec register set REGSET
612 from the buffer specified by VRREGS and LEN to register cache
613 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
616 ppc_supply_vrregset (const struct regset
*regset
, struct regcache
*regcache
,
617 int regnum
, const void *vrregs
, size_t len
)
619 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
620 struct gdbarch_tdep
*tdep
;
621 const struct ppc_reg_offsets
*offsets
;
624 if (!ppc_altivec_support_p (gdbarch
))
627 tdep
= gdbarch_tdep (gdbarch
);
628 offsets
= regset
->descr
;
633 for (i
= tdep
->ppc_vr0_regnum
, offset
= offsets
->vr0_offset
;
634 i
< tdep
->ppc_vr0_regnum
+ ppc_num_vrs
;
636 ppc_supply_reg (regcache
, i
, vrregs
, offset
, 16);
638 ppc_supply_reg (regcache
, (tdep
->ppc_vrsave_regnum
- 1),
639 vrregs
, offsets
->vscr_offset
, 4);
641 ppc_supply_reg (regcache
, tdep
->ppc_vrsave_regnum
,
642 vrregs
, offsets
->vrsave_offset
, 4);
646 offset
= ppc_vrreg_offset (tdep
, offsets
, regnum
);
647 if (regnum
!= tdep
->ppc_vrsave_regnum
648 && regnum
!= tdep
->ppc_vrsave_regnum
- 1)
649 ppc_supply_reg (regcache
, regnum
, vrregs
, offset
, 16);
651 ppc_supply_reg (regcache
, regnum
,
655 /* Collect register REGNUM in the general-purpose register set
656 REGSET from register cache REGCACHE into the buffer specified by
657 GREGS and LEN. If REGNUM is -1, do this for all registers in
661 ppc_collect_gregset (const struct regset
*regset
,
662 const struct regcache
*regcache
,
663 int regnum
, void *gregs
, size_t len
)
665 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
666 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
667 const struct ppc_reg_offsets
*offsets
= regset
->descr
;
674 int gpr_size
= offsets
->gpr_size
;
676 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
677 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
678 i
++, offset
+= gpr_size
)
679 ppc_collect_reg (regcache
, i
, gregs
, offset
, gpr_size
);
681 ppc_collect_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
682 gregs
, offsets
->pc_offset
, gpr_size
);
683 ppc_collect_reg (regcache
, tdep
->ppc_ps_regnum
,
684 gregs
, offsets
->ps_offset
, gpr_size
);
685 ppc_collect_reg (regcache
, tdep
->ppc_lr_regnum
,
686 gregs
, offsets
->lr_offset
, gpr_size
);
687 ppc_collect_reg (regcache
, tdep
->ppc_ctr_regnum
,
688 gregs
, offsets
->ctr_offset
, gpr_size
);
689 ppc_collect_reg (regcache
, tdep
->ppc_cr_regnum
,
690 gregs
, offsets
->cr_offset
, offsets
->xr_size
);
691 ppc_collect_reg (regcache
, tdep
->ppc_xer_regnum
,
692 gregs
, offsets
->xer_offset
, offsets
->xr_size
);
693 ppc_collect_reg (regcache
, tdep
->ppc_mq_regnum
,
694 gregs
, offsets
->mq_offset
, offsets
->xr_size
);
698 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
699 ppc_collect_reg (regcache
, regnum
, gregs
, offset
, regsize
);
702 /* Collect register REGNUM in the floating-point register set
703 REGSET from register cache REGCACHE into the buffer specified by
704 FPREGS and LEN. If REGNUM is -1, do this for all registers in
708 ppc_collect_fpregset (const struct regset
*regset
,
709 const struct regcache
*regcache
,
710 int regnum
, void *fpregs
, size_t len
)
712 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
713 struct gdbarch_tdep
*tdep
;
714 const struct ppc_reg_offsets
*offsets
;
717 if (!ppc_floating_point_unit_p (gdbarch
))
720 tdep
= gdbarch_tdep (gdbarch
);
721 offsets
= regset
->descr
;
726 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
727 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
729 ppc_collect_reg (regcache
, i
, fpregs
, offset
, 8);
731 ppc_collect_reg (regcache
, tdep
->ppc_fpscr_regnum
,
732 fpregs
, offsets
->fpscr_offset
, offsets
->fpscr_size
);
736 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
737 ppc_collect_reg (regcache
, regnum
, fpregs
, offset
,
738 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
741 /* Collect register REGNUM in the VSX register set
742 REGSET from register cache REGCACHE into the buffer specified by
743 VSXREGS and LEN. If REGNUM is -1, do this for all registers in
747 ppc_collect_vsxregset (const struct regset
*regset
,
748 const struct regcache
*regcache
,
749 int regnum
, void *vsxregs
, size_t len
)
751 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
752 struct gdbarch_tdep
*tdep
;
754 if (!ppc_vsx_support_p (gdbarch
))
757 tdep
= gdbarch_tdep (gdbarch
);
763 for (i
= tdep
->ppc_vsr0_upper_regnum
;
764 i
< tdep
->ppc_vsr0_upper_regnum
+ 32;
766 ppc_collect_reg (regcache
, i
, vsxregs
, 0, 8);
771 ppc_collect_reg (regcache
, regnum
, vsxregs
, 0, 8);
775 /* Collect register REGNUM in the Altivec register set
776 REGSET from register cache REGCACHE into the buffer specified by
777 VRREGS and LEN. If REGNUM is -1, do this for all registers in
781 ppc_collect_vrregset (const struct regset
*regset
,
782 const struct regcache
*regcache
,
783 int regnum
, void *vrregs
, size_t len
)
785 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
786 struct gdbarch_tdep
*tdep
;
787 const struct ppc_reg_offsets
*offsets
;
790 if (!ppc_altivec_support_p (gdbarch
))
793 tdep
= gdbarch_tdep (gdbarch
);
794 offsets
= regset
->descr
;
799 for (i
= tdep
->ppc_vr0_regnum
, offset
= offsets
->vr0_offset
;
800 i
< tdep
->ppc_vr0_regnum
+ ppc_num_vrs
;
802 ppc_collect_reg (regcache
, i
, vrregs
, offset
, 16);
804 ppc_collect_reg (regcache
, (tdep
->ppc_vrsave_regnum
- 1),
805 vrregs
, offsets
->vscr_offset
, 4);
807 ppc_collect_reg (regcache
, tdep
->ppc_vrsave_regnum
,
808 vrregs
, offsets
->vrsave_offset
, 4);
812 offset
= ppc_vrreg_offset (tdep
, offsets
, regnum
);
813 if (regnum
!= tdep
->ppc_vrsave_regnum
814 && regnum
!= tdep
->ppc_vrsave_regnum
- 1)
815 ppc_collect_reg (regcache
, regnum
, vrregs
, offset
, 16);
817 ppc_collect_reg (regcache
, regnum
,
823 insn_changes_sp_or_jumps (unsigned long insn
)
825 int opcode
= (insn
>> 26) & 0x03f;
826 int sd
= (insn
>> 21) & 0x01f;
827 int a
= (insn
>> 16) & 0x01f;
828 int subcode
= (insn
>> 1) & 0x3ff;
830 /* Changes the stack pointer. */
832 /* NOTE: There are many ways to change the value of a given register.
833 The ways below are those used when the register is R1, the SP,
834 in a funtion's epilogue. */
836 if (opcode
== 31 && subcode
== 444 && a
== 1)
837 return 1; /* mr R1,Rn */
838 if (opcode
== 14 && sd
== 1)
839 return 1; /* addi R1,Rn,simm */
840 if (opcode
== 58 && sd
== 1)
841 return 1; /* ld R1,ds(Rn) */
843 /* Transfers control. */
849 if (opcode
== 19 && subcode
== 16)
851 if (opcode
== 19 && subcode
== 528)
852 return 1; /* bcctr */
857 /* Return true if we are in the function's epilogue, i.e. after the
858 instruction that destroyed the function's stack frame.
860 1) scan forward from the point of execution:
861 a) If you find an instruction that modifies the stack pointer
862 or transfers control (except a return), execution is not in
864 b) Stop scanning if you find a return instruction or reach the
865 end of the function or reach the hard limit for the size of
867 2) scan backward from the point of execution:
868 a) If you find an instruction that modifies the stack pointer,
869 execution *is* in an epilogue, return.
870 b) Stop scanning if you reach an instruction that transfers
871 control or the beginning of the function or reach the hard
872 limit for the size of an epilogue. */
875 rs6000_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
877 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
878 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
879 bfd_byte insn_buf
[PPC_INSN_SIZE
];
880 CORE_ADDR scan_pc
, func_start
, func_end
, epilogue_start
, epilogue_end
;
882 struct frame_info
*curfrm
;
884 /* Find the search limits based on function boundaries and hard limit. */
886 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
889 epilogue_start
= pc
- PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
890 if (epilogue_start
< func_start
) epilogue_start
= func_start
;
892 epilogue_end
= pc
+ PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
893 if (epilogue_end
> func_end
) epilogue_end
= func_end
;
895 curfrm
= get_current_frame ();
897 /* Scan forward until next 'blr'. */
899 for (scan_pc
= pc
; scan_pc
< epilogue_end
; scan_pc
+= PPC_INSN_SIZE
)
901 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
903 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
904 if (insn
== 0x4e800020)
906 /* Assume a bctr is a tail call unless it points strictly within
908 if (insn
== 0x4e800420)
910 CORE_ADDR ctr
= get_frame_register_unsigned (curfrm
,
911 tdep
->ppc_ctr_regnum
);
912 if (ctr
> func_start
&& ctr
< func_end
)
917 if (insn_changes_sp_or_jumps (insn
))
921 /* Scan backward until adjustment to stack pointer (R1). */
923 for (scan_pc
= pc
- PPC_INSN_SIZE
;
924 scan_pc
>= epilogue_start
;
925 scan_pc
-= PPC_INSN_SIZE
)
927 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
929 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
930 if (insn_changes_sp_or_jumps (insn
))
937 /* Get the ith function argument for the current function. */
939 rs6000_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
942 return get_frame_register_unsigned (frame
, 3 + argi
);
945 /* Sequence of bytes for breakpoint instruction. */
947 const static unsigned char *
948 rs6000_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*bp_addr
,
951 static unsigned char big_breakpoint
[] = { 0x7d, 0x82, 0x10, 0x08 };
952 static unsigned char little_breakpoint
[] = { 0x08, 0x10, 0x82, 0x7d };
954 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
955 return big_breakpoint
;
957 return little_breakpoint
;
960 /* Instruction masks for displaced stepping. */
961 #define BRANCH_MASK 0xfc000000
962 #define BP_MASK 0xFC0007FE
963 #define B_INSN 0x48000000
964 #define BC_INSN 0x40000000
965 #define BXL_INSN 0x4c000000
966 #define BP_INSN 0x7C000008
968 /* Fix up the state of registers and memory after having single-stepped
969 a displaced instruction. */
971 ppc_displaced_step_fixup (struct gdbarch
*gdbarch
,
972 struct displaced_step_closure
*closure
,
973 CORE_ADDR from
, CORE_ADDR to
,
974 struct regcache
*regs
)
976 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
977 /* Since we use simple_displaced_step_copy_insn, our closure is a
978 copy of the instruction. */
979 ULONGEST insn
= extract_unsigned_integer ((gdb_byte
*) closure
,
980 PPC_INSN_SIZE
, byte_order
);
982 /* Offset for non PC-relative instructions. */
983 LONGEST offset
= PPC_INSN_SIZE
;
985 opcode
= insn
& BRANCH_MASK
;
988 fprintf_unfiltered (gdb_stdlog
,
989 "displaced: (ppc) fixup (%s, %s)\n",
990 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
993 /* Handle PC-relative branch instructions. */
994 if (opcode
== B_INSN
|| opcode
== BC_INSN
|| opcode
== BXL_INSN
)
998 /* Read the current PC value after the instruction has been executed
999 in a displaced location. Calculate the offset to be applied to the
1000 original PC value before the displaced stepping. */
1001 regcache_cooked_read_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1003 offset
= current_pc
- to
;
1005 if (opcode
!= BXL_INSN
)
1007 /* Check for AA bit indicating whether this is an absolute
1008 addressing or PC-relative (1: absolute, 0: relative). */
1011 /* PC-relative addressing is being used in the branch. */
1012 if (debug_displaced
)
1015 "displaced: (ppc) branch instruction: %s\n"
1016 "displaced: (ppc) adjusted PC from %s to %s\n",
1017 paddress (gdbarch
, insn
), paddress (gdbarch
, current_pc
),
1018 paddress (gdbarch
, from
+ offset
));
1020 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1026 /* If we're here, it means we have a branch to LR or CTR. If the
1027 branch was taken, the offset is probably greater than 4 (the next
1028 instruction), so it's safe to assume that an offset of 4 means we
1029 did not take the branch. */
1030 if (offset
== PPC_INSN_SIZE
)
1031 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1032 from
+ PPC_INSN_SIZE
);
1035 /* Check for LK bit indicating whether we should set the link
1036 register to point to the next instruction
1037 (1: Set, 0: Don't set). */
1040 /* Link register needs to be set to the next instruction's PC. */
1041 regcache_cooked_write_unsigned (regs
,
1042 gdbarch_tdep (gdbarch
)->ppc_lr_regnum
,
1043 from
+ PPC_INSN_SIZE
);
1044 if (debug_displaced
)
1045 fprintf_unfiltered (gdb_stdlog
,
1046 "displaced: (ppc) adjusted LR to %s\n",
1047 paddress (gdbarch
, from
+ PPC_INSN_SIZE
));
1051 /* Check for breakpoints in the inferior. If we've found one, place the PC
1052 right at the breakpoint instruction. */
1053 else if ((insn
& BP_MASK
) == BP_INSN
)
1054 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
), from
);
1056 /* Handle any other instructions that do not fit in the categories above. */
1057 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1061 /* Instruction masks used during single-stepping of atomic sequences. */
1062 #define LWARX_MASK 0xfc0007fe
1063 #define LWARX_INSTRUCTION 0x7c000028
1064 #define LDARX_INSTRUCTION 0x7c0000A8
1065 #define STWCX_MASK 0xfc0007ff
1066 #define STWCX_INSTRUCTION 0x7c00012d
1067 #define STDCX_INSTRUCTION 0x7c0001ad
1069 /* Checks for an atomic sequence of instructions beginning with a LWARX/LDARX
1070 instruction and ending with a STWCX/STDCX instruction. If such a sequence
1071 is found, attempt to step through it. A breakpoint is placed at the end of
1075 ppc_deal_with_atomic_sequence (struct frame_info
*frame
)
1077 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1078 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1079 CORE_ADDR pc
= get_frame_pc (frame
);
1080 CORE_ADDR breaks
[2] = {-1, -1};
1082 CORE_ADDR closing_insn
; /* Instruction that closes the atomic sequence. */
1083 int insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1086 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
1087 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
1088 int opcode
; /* Branch instruction's OPcode. */
1089 int bc_insn_count
= 0; /* Conditional branch instruction count. */
1091 /* Assume all atomic sequences start with a lwarx/ldarx instruction. */
1092 if ((insn
& LWARX_MASK
) != LWARX_INSTRUCTION
1093 && (insn
& LWARX_MASK
) != LDARX_INSTRUCTION
)
1096 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
1098 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
1100 loc
+= PPC_INSN_SIZE
;
1101 insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1103 /* Assume that there is at most one conditional branch in the atomic
1104 sequence. If a conditional branch is found, put a breakpoint in
1105 its destination address. */
1106 if ((insn
& BRANCH_MASK
) == BC_INSN
)
1108 int immediate
= ((insn
& ~3) << 16) >> 16;
1109 int absolute
= ((insn
>> 1) & 1);
1111 if (bc_insn_count
>= 1)
1112 return 0; /* More than one conditional branch found, fallback
1113 to the standard single-step code. */
1116 breaks
[1] = immediate
;
1118 breaks
[1] = pc
+ immediate
;
1124 if ((insn
& STWCX_MASK
) == STWCX_INSTRUCTION
1125 || (insn
& STWCX_MASK
) == STDCX_INSTRUCTION
)
1129 /* Assume that the atomic sequence ends with a stwcx/stdcx instruction. */
1130 if ((insn
& STWCX_MASK
) != STWCX_INSTRUCTION
1131 && (insn
& STWCX_MASK
) != STDCX_INSTRUCTION
)
1135 loc
+= PPC_INSN_SIZE
;
1136 insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1138 /* Insert a breakpoint right after the end of the atomic sequence. */
1141 /* Check for duplicated breakpoints. Check also for a breakpoint
1142 placed (branch instruction's destination) at the stwcx/stdcx
1143 instruction, this resets the reservation and take us back to the
1144 lwarx/ldarx instruction at the beginning of the atomic sequence. */
1145 if (last_breakpoint
&& ((breaks
[1] == breaks
[0])
1146 || (breaks
[1] == closing_insn
)))
1147 last_breakpoint
= 0;
1149 /* Effectively inserts the breakpoints. */
1150 for (index
= 0; index
<= last_breakpoint
; index
++)
1151 insert_single_step_breakpoint (gdbarch
, breaks
[index
]);
1157 #define SIGNED_SHORT(x) \
1158 ((sizeof (short) == 2) \
1159 ? ((int)(short)(x)) \
1160 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
1162 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
1164 /* Limit the number of skipped non-prologue instructions, as the examining
1165 of the prologue is expensive. */
1166 static int max_skip_non_prologue_insns
= 10;
1168 /* Return nonzero if the given instruction OP can be part of the prologue
1169 of a function and saves a parameter on the stack. FRAMEP should be
1170 set if one of the previous instructions in the function has set the
1174 store_param_on_stack_p (unsigned long op
, int framep
, int *r0_contains_arg
)
1176 /* Move parameters from argument registers to temporary register. */
1177 if ((op
& 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
1179 /* Rx must be scratch register r0. */
1180 const int rx_regno
= (op
>> 16) & 31;
1181 /* Ry: Only r3 - r10 are used for parameter passing. */
1182 const int ry_regno
= GET_SRC_REG (op
);
1184 if (rx_regno
== 0 && ry_regno
>= 3 && ry_regno
<= 10)
1186 *r0_contains_arg
= 1;
1193 /* Save a General Purpose Register on stack. */
1195 if ((op
& 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
1196 (op
& 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
1198 /* Rx: Only r3 - r10 are used for parameter passing. */
1199 const int rx_regno
= GET_SRC_REG (op
);
1201 return (rx_regno
>= 3 && rx_regno
<= 10);
1204 /* Save a General Purpose Register on stack via the Frame Pointer. */
1207 ((op
& 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
1208 (op
& 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
1209 (op
& 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
1211 /* Rx: Usually, only r3 - r10 are used for parameter passing.
1212 However, the compiler sometimes uses r0 to hold an argument. */
1213 const int rx_regno
= GET_SRC_REG (op
);
1215 return ((rx_regno
>= 3 && rx_regno
<= 10)
1216 || (rx_regno
== 0 && *r0_contains_arg
));
1219 if ((op
& 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
1221 /* Only f2 - f8 are used for parameter passing. */
1222 const int src_regno
= GET_SRC_REG (op
);
1224 return (src_regno
>= 2 && src_regno
<= 8);
1227 if (framep
&& ((op
& 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
1229 /* Only f2 - f8 are used for parameter passing. */
1230 const int src_regno
= GET_SRC_REG (op
);
1232 return (src_regno
>= 2 && src_regno
<= 8);
1235 /* Not an insn that saves a parameter on stack. */
1239 /* Assuming that INSN is a "bl" instruction located at PC, return
1240 nonzero if the destination of the branch is a "blrl" instruction.
1242 This sequence is sometimes found in certain function prologues.
1243 It allows the function to load the LR register with a value that
1244 they can use to access PIC data using PC-relative offsets. */
1247 bl_to_blrl_insn_p (CORE_ADDR pc
, int insn
, enum bfd_endian byte_order
)
1254 absolute
= (int) ((insn
>> 1) & 1);
1255 immediate
= ((insn
& ~3) << 6) >> 6;
1259 dest
= pc
+ immediate
;
1261 dest_insn
= read_memory_integer (dest
, 4, byte_order
);
1262 if ((dest_insn
& 0xfc00ffff) == 0x4c000021) /* blrl */
1268 /* Masks for decoding a branch-and-link (bl) instruction.
1270 BL_MASK and BL_INSTRUCTION are used in combination with each other.
1271 The former is anded with the opcode in question; if the result of
1272 this masking operation is equal to BL_INSTRUCTION, then the opcode in
1273 question is a ``bl'' instruction.
1275 BL_DISPLACMENT_MASK is anded with the opcode in order to extract
1276 the branch displacement. */
1278 #define BL_MASK 0xfc000001
1279 #define BL_INSTRUCTION 0x48000001
1280 #define BL_DISPLACEMENT_MASK 0x03fffffc
1282 static unsigned long
1283 rs6000_fetch_instruction (struct gdbarch
*gdbarch
, const CORE_ADDR pc
)
1285 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1289 /* Fetch the instruction and convert it to an integer. */
1290 if (target_read_memory (pc
, buf
, 4))
1292 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1297 /* GCC generates several well-known sequences of instructions at the begining
1298 of each function prologue when compiling with -fstack-check. If one of
1299 such sequences starts at START_PC, then return the address of the
1300 instruction immediately past this sequence. Otherwise, return START_PC. */
1303 rs6000_skip_stack_check (struct gdbarch
*gdbarch
, const CORE_ADDR start_pc
)
1305 CORE_ADDR pc
= start_pc
;
1306 unsigned long op
= rs6000_fetch_instruction (gdbarch
, pc
);
1308 /* First possible sequence: A small number of probes.
1309 stw 0, -<some immediate>(1)
1310 [repeat this instruction any (small) number of times]
1313 if ((op
& 0xffff0000) == 0x90010000)
1315 while ((op
& 0xffff0000) == 0x90010000)
1318 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1323 /* Second sequence: A probing loop.
1324 addi 12,1,-<some immediate>
1325 lis 0,-<some immediate>
1326 [possibly ori 0,0,<some immediate>]
1330 addi 12,12,-<some immediate>
1333 [possibly one last probe: stw 0,<some immediate>(12)]
1338 /* addi 12,1,-<some immediate> */
1339 if ((op
& 0xffff0000) != 0x39810000)
1342 /* lis 0,-<some immediate> */
1344 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1345 if ((op
& 0xffff0000) != 0x3c000000)
1349 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1350 /* [possibly ori 0,0,<some immediate>] */
1351 if ((op
& 0xffff0000) == 0x60000000)
1354 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1357 if (op
!= 0x7c0c0214)
1362 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1363 if (op
!= 0x7c0c0000)
1368 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1369 if ((op
& 0xff9f0001) != 0x41820000)
1372 /* addi 12,12,-<some immediate> */
1374 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1375 if ((op
& 0xffff0000) != 0x398c0000)
1380 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1381 if (op
!= 0x900c0000)
1386 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1387 if ((op
& 0xfc000001) != 0x48000000)
1390 /* [possibly one last probe: stw 0,<some immediate>(12)] */
1392 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1393 if ((op
& 0xffff0000) == 0x900c0000)
1396 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1399 /* We found a valid stack-check sequence, return the new PC. */
1403 /* Third sequence: No probe; instead, a comparizon between the stack size
1404 limit (saved in a run-time global variable) and the current stack
1407 addi 0,1,-<some immediate>
1408 lis 12,__gnat_stack_limit@ha
1409 lwz 12,__gnat_stack_limit@l(12)
1412 or, with a small variant in the case of a bigger stack frame:
1413 addis 0,1,<some immediate>
1414 addic 0,0,-<some immediate>
1415 lis 12,__gnat_stack_limit@ha
1416 lwz 12,__gnat_stack_limit@l(12)
1421 /* addi 0,1,-<some immediate> */
1422 if ((op
& 0xffff0000) != 0x38010000)
1424 /* small stack frame variant not recognized; try the
1425 big stack frame variant: */
1427 /* addis 0,1,<some immediate> */
1428 if ((op
& 0xffff0000) != 0x3c010000)
1431 /* addic 0,0,-<some immediate> */
1433 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1434 if ((op
& 0xffff0000) != 0x30000000)
1438 /* lis 12,<some immediate> */
1440 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1441 if ((op
& 0xffff0000) != 0x3d800000)
1444 /* lwz 12,<some immediate>(12) */
1446 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1447 if ((op
& 0xffff0000) != 0x818c0000)
1452 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1453 if ((op
& 0xfffffffe) != 0x7c406008)
1456 /* We found a valid stack-check sequence, return the new PC. */
1460 /* No stack check code in our prologue, return the start_pc. */
1464 /* return pc value after skipping a function prologue and also return
1465 information about a function frame.
1467 in struct rs6000_framedata fdata:
1468 - frameless is TRUE, if function does not have a frame.
1469 - nosavedpc is TRUE, if function does not save %pc value in its frame.
1470 - offset is the initial size of this stack frame --- the amount by
1471 which we decrement the sp to allocate the frame.
1472 - saved_gpr is the number of the first saved gpr.
1473 - saved_fpr is the number of the first saved fpr.
1474 - saved_vr is the number of the first saved vr.
1475 - saved_ev is the number of the first saved ev.
1476 - alloca_reg is the number of the register used for alloca() handling.
1478 - gpr_offset is the offset of the first saved gpr from the previous frame.
1479 - fpr_offset is the offset of the first saved fpr from the previous frame.
1480 - vr_offset is the offset of the first saved vr from the previous frame.
1481 - ev_offset is the offset of the first saved ev from the previous frame.
1482 - lr_offset is the offset of the saved lr
1483 - cr_offset is the offset of the saved cr
1484 - vrsave_offset is the offset of the saved vrsave register
1488 skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
, CORE_ADDR lim_pc
,
1489 struct rs6000_framedata
*fdata
)
1491 CORE_ADDR orig_pc
= pc
;
1492 CORE_ADDR last_prologue_pc
= pc
;
1493 CORE_ADDR li_found_pc
= 0;
1497 long vr_saved_offset
= 0;
1503 int vrsave_reg
= -1;
1506 int minimal_toc_loaded
= 0;
1507 int prev_insn_was_prologue_insn
= 1;
1508 int num_skip_non_prologue_insns
= 0;
1509 int r0_contains_arg
= 0;
1510 const struct bfd_arch_info
*arch_info
= gdbarch_bfd_arch_info (gdbarch
);
1511 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1512 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1514 memset (fdata
, 0, sizeof (struct rs6000_framedata
));
1515 fdata
->saved_gpr
= -1;
1516 fdata
->saved_fpr
= -1;
1517 fdata
->saved_vr
= -1;
1518 fdata
->saved_ev
= -1;
1519 fdata
->alloca_reg
= -1;
1520 fdata
->frameless
= 1;
1521 fdata
->nosavedpc
= 1;
1522 fdata
->lr_register
= -1;
1524 pc
= rs6000_skip_stack_check (gdbarch
, pc
);
1530 /* Sometimes it isn't clear if an instruction is a prologue
1531 instruction or not. When we encounter one of these ambiguous
1532 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
1533 Otherwise, we'll assume that it really is a prologue instruction. */
1534 if (prev_insn_was_prologue_insn
)
1535 last_prologue_pc
= pc
;
1537 /* Stop scanning if we've hit the limit. */
1541 prev_insn_was_prologue_insn
= 1;
1543 /* Fetch the instruction and convert it to an integer. */
1544 if (target_read_memory (pc
, buf
, 4))
1546 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1548 if ((op
& 0xfc1fffff) == 0x7c0802a6)
1550 /* Since shared library / PIC code, which needs to get its
1551 address at runtime, can appear to save more than one link
1565 remember just the first one, but skip over additional
1568 lr_reg
= (op
& 0x03e00000) >> 21;
1570 r0_contains_arg
= 0;
1573 else if ((op
& 0xfc1fffff) == 0x7c000026)
1575 cr_reg
= (op
& 0x03e00000);
1577 r0_contains_arg
= 0;
1581 else if ((op
& 0xfc1f0000) == 0xd8010000)
1582 { /* stfd Rx,NUM(r1) */
1583 reg
= GET_SRC_REG (op
);
1584 if (fdata
->saved_fpr
== -1 || fdata
->saved_fpr
> reg
)
1586 fdata
->saved_fpr
= reg
;
1587 fdata
->fpr_offset
= SIGNED_SHORT (op
) + offset
;
1592 else if (((op
& 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
1593 (((op
& 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1594 (op
& 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1595 (op
& 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
1598 reg
= GET_SRC_REG (op
);
1599 if ((op
& 0xfc1f0000) == 0xbc010000)
1600 fdata
->gpr_mask
|= ~((1U << reg
) - 1);
1602 fdata
->gpr_mask
|= 1U << reg
;
1603 if (fdata
->saved_gpr
== -1 || fdata
->saved_gpr
> reg
)
1605 fdata
->saved_gpr
= reg
;
1606 if ((op
& 0xfc1f0003) == 0xf8010000)
1608 fdata
->gpr_offset
= SIGNED_SHORT (op
) + offset
;
1613 else if ((op
& 0xffff0000) == 0x60000000)
1616 /* Allow nops in the prologue, but do not consider them to
1617 be part of the prologue unless followed by other prologue
1619 prev_insn_was_prologue_insn
= 0;
1623 else if ((op
& 0xffff0000) == 0x3c000000)
1624 { /* addis 0,0,NUM, used
1625 for >= 32k frames */
1626 fdata
->offset
= (op
& 0x0000ffff) << 16;
1627 fdata
->frameless
= 0;
1628 r0_contains_arg
= 0;
1632 else if ((op
& 0xffff0000) == 0x60000000)
1633 { /* ori 0,0,NUM, 2nd ha
1634 lf of >= 32k frames */
1635 fdata
->offset
|= (op
& 0x0000ffff);
1636 fdata
->frameless
= 0;
1637 r0_contains_arg
= 0;
1641 else if (lr_reg
>= 0 &&
1642 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1643 (((op
& 0xffff0000) == (lr_reg
| 0xf8010000)) ||
1644 /* stw Rx, NUM(r1) */
1645 ((op
& 0xffff0000) == (lr_reg
| 0x90010000)) ||
1646 /* stwu Rx, NUM(r1) */
1647 ((op
& 0xffff0000) == (lr_reg
| 0x94010000))))
1648 { /* where Rx == lr */
1649 fdata
->lr_offset
= offset
;
1650 fdata
->nosavedpc
= 0;
1651 /* Invalidate lr_reg, but don't set it to -1.
1652 That would mean that it had never been set. */
1654 if ((op
& 0xfc000003) == 0xf8000000 || /* std */
1655 (op
& 0xfc000000) == 0x90000000) /* stw */
1657 /* Does not update r1, so add displacement to lr_offset. */
1658 fdata
->lr_offset
+= SIGNED_SHORT (op
);
1663 else if (cr_reg
>= 0 &&
1664 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1665 (((op
& 0xffff0000) == (cr_reg
| 0xf8010000)) ||
1666 /* stw Rx, NUM(r1) */
1667 ((op
& 0xffff0000) == (cr_reg
| 0x90010000)) ||
1668 /* stwu Rx, NUM(r1) */
1669 ((op
& 0xffff0000) == (cr_reg
| 0x94010000))))
1670 { /* where Rx == cr */
1671 fdata
->cr_offset
= offset
;
1672 /* Invalidate cr_reg, but don't set it to -1.
1673 That would mean that it had never been set. */
1675 if ((op
& 0xfc000003) == 0xf8000000 ||
1676 (op
& 0xfc000000) == 0x90000000)
1678 /* Does not update r1, so add displacement to cr_offset. */
1679 fdata
->cr_offset
+= SIGNED_SHORT (op
);
1684 else if ((op
& 0xfe80ffff) == 0x42800005 && lr_reg
!= -1)
1686 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1687 prediction bits. If the LR has already been saved, we can
1691 else if (op
== 0x48000005)
1698 else if (op
== 0x48000004)
1703 else if ((op
& 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1704 in V.4 -mminimal-toc */
1705 (op
& 0xffff0000) == 0x3bde0000)
1706 { /* addi 30,30,foo@l */
1710 else if ((op
& 0xfc000001) == 0x48000001)
1714 fdata
->frameless
= 0;
1716 /* If the return address has already been saved, we can skip
1717 calls to blrl (for PIC). */
1718 if (lr_reg
!= -1 && bl_to_blrl_insn_p (pc
, op
, byte_order
))
1724 /* Don't skip over the subroutine call if it is not within
1725 the first three instructions of the prologue and either
1726 we have no line table information or the line info tells
1727 us that the subroutine call is not part of the line
1728 associated with the prologue. */
1729 if ((pc
- orig_pc
) > 8)
1731 struct symtab_and_line prologue_sal
= find_pc_line (orig_pc
, 0);
1732 struct symtab_and_line this_sal
= find_pc_line (pc
, 0);
1734 if ((prologue_sal
.line
== 0) || (prologue_sal
.line
!= this_sal
.line
))
1738 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
1740 /* At this point, make sure this is not a trampoline
1741 function (a function that simply calls another functions,
1742 and nothing else). If the next is not a nop, this branch
1743 was part of the function prologue. */
1745 if (op
== 0x4def7b82 || op
== 0) /* crorc 15, 15, 15 */
1746 break; /* don't skip over
1752 /* update stack pointer */
1753 else if ((op
& 0xfc1f0000) == 0x94010000)
1754 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
1755 fdata
->frameless
= 0;
1756 fdata
->offset
= SIGNED_SHORT (op
);
1757 offset
= fdata
->offset
;
1760 else if ((op
& 0xfc1f016a) == 0x7c01016e)
1761 { /* stwux rX,r1,rY */
1762 /* no way to figure out what r1 is going to be */
1763 fdata
->frameless
= 0;
1764 offset
= fdata
->offset
;
1767 else if ((op
& 0xfc1f0003) == 0xf8010001)
1768 { /* stdu rX,NUM(r1) */
1769 fdata
->frameless
= 0;
1770 fdata
->offset
= SIGNED_SHORT (op
& ~3UL);
1771 offset
= fdata
->offset
;
1774 else if ((op
& 0xfc1f016a) == 0x7c01016a)
1775 { /* stdux rX,r1,rY */
1776 /* no way to figure out what r1 is going to be */
1777 fdata
->frameless
= 0;
1778 offset
= fdata
->offset
;
1781 else if ((op
& 0xffff0000) == 0x38210000)
1782 { /* addi r1,r1,SIMM */
1783 fdata
->frameless
= 0;
1784 fdata
->offset
+= SIGNED_SHORT (op
);
1785 offset
= fdata
->offset
;
1788 /* Load up minimal toc pointer. Do not treat an epilogue restore
1789 of r31 as a minimal TOC load. */
1790 else if (((op
>> 22) == 0x20f || /* l r31,... or l r30,... */
1791 (op
>> 22) == 0x3af) /* ld r31,... or ld r30,... */
1793 && !minimal_toc_loaded
)
1795 minimal_toc_loaded
= 1;
1798 /* move parameters from argument registers to local variable
1801 else if ((op
& 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1802 (((op
>> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1803 (((op
>> 21) & 31) <= 10) &&
1804 ((long) ((op
>> 16) & 31) >= fdata
->saved_gpr
)) /* Rx: local var reg */
1808 /* store parameters in stack */
1810 /* Move parameters from argument registers to temporary register. */
1811 else if (store_param_on_stack_p (op
, framep
, &r0_contains_arg
))
1815 /* Set up frame pointer */
1817 else if (op
== 0x603f0000 /* oril r31, r1, 0x0 */
1818 || op
== 0x7c3f0b78)
1820 fdata
->frameless
= 0;
1822 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 31);
1825 /* Another way to set up the frame pointer. */
1827 else if ((op
& 0xfc1fffff) == 0x38010000)
1828 { /* addi rX, r1, 0x0 */
1829 fdata
->frameless
= 0;
1831 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
1832 + ((op
& ~0x38010000) >> 21));
1835 /* AltiVec related instructions. */
1836 /* Store the vrsave register (spr 256) in another register for
1837 later manipulation, or load a register into the vrsave
1838 register. 2 instructions are used: mfvrsave and
1839 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1840 and mtspr SPR256, Rn. */
1841 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1842 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1843 else if ((op
& 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1845 vrsave_reg
= GET_SRC_REG (op
);
1848 else if ((op
& 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1852 /* Store the register where vrsave was saved to onto the stack:
1853 rS is the register where vrsave was stored in a previous
1855 /* 100100 sssss 00001 dddddddd dddddddd */
1856 else if ((op
& 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1858 if (vrsave_reg
== GET_SRC_REG (op
))
1860 fdata
->vrsave_offset
= SIGNED_SHORT (op
) + offset
;
1865 /* Compute the new value of vrsave, by modifying the register
1866 where vrsave was saved to. */
1867 else if (((op
& 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1868 || ((op
& 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1872 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1873 in a pair of insns to save the vector registers on the
1875 /* 001110 00000 00000 iiii iiii iiii iiii */
1876 /* 001110 01110 00000 iiii iiii iiii iiii */
1877 else if ((op
& 0xffff0000) == 0x38000000 /* li r0, SIMM */
1878 || (op
& 0xffff0000) == 0x39c00000) /* li r14, SIMM */
1880 if ((op
& 0xffff0000) == 0x38000000)
1881 r0_contains_arg
= 0;
1883 vr_saved_offset
= SIGNED_SHORT (op
);
1885 /* This insn by itself is not part of the prologue, unless
1886 if part of the pair of insns mentioned above. So do not
1887 record this insn as part of the prologue yet. */
1888 prev_insn_was_prologue_insn
= 0;
1890 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1891 /* 011111 sssss 11111 00000 00111001110 */
1892 else if ((op
& 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1894 if (pc
== (li_found_pc
+ 4))
1896 vr_reg
= GET_SRC_REG (op
);
1897 /* If this is the first vector reg to be saved, or if
1898 it has a lower number than others previously seen,
1899 reupdate the frame info. */
1900 if (fdata
->saved_vr
== -1 || fdata
->saved_vr
> vr_reg
)
1902 fdata
->saved_vr
= vr_reg
;
1903 fdata
->vr_offset
= vr_saved_offset
+ offset
;
1905 vr_saved_offset
= -1;
1910 /* End AltiVec related instructions. */
1912 /* Start BookE related instructions. */
1913 /* Store gen register S at (r31+uimm).
1914 Any register less than r13 is volatile, so we don't care. */
1915 /* 000100 sssss 11111 iiiii 01100100001 */
1916 else if (arch_info
->mach
== bfd_mach_ppc_e500
1917 && (op
& 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
1919 if ((op
& 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
1922 ev_reg
= GET_SRC_REG (op
);
1923 imm
= (op
>> 11) & 0x1f;
1924 ev_offset
= imm
* 8;
1925 /* If this is the first vector reg to be saved, or if
1926 it has a lower number than others previously seen,
1927 reupdate the frame info. */
1928 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1930 fdata
->saved_ev
= ev_reg
;
1931 fdata
->ev_offset
= ev_offset
+ offset
;
1936 /* Store gen register rS at (r1+rB). */
1937 /* 000100 sssss 00001 bbbbb 01100100000 */
1938 else if (arch_info
->mach
== bfd_mach_ppc_e500
1939 && (op
& 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1941 if (pc
== (li_found_pc
+ 4))
1943 ev_reg
= GET_SRC_REG (op
);
1944 /* If this is the first vector reg to be saved, or if
1945 it has a lower number than others previously seen,
1946 reupdate the frame info. */
1947 /* We know the contents of rB from the previous instruction. */
1948 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1950 fdata
->saved_ev
= ev_reg
;
1951 fdata
->ev_offset
= vr_saved_offset
+ offset
;
1953 vr_saved_offset
= -1;
1959 /* Store gen register r31 at (rA+uimm). */
1960 /* 000100 11111 aaaaa iiiii 01100100001 */
1961 else if (arch_info
->mach
== bfd_mach_ppc_e500
1962 && (op
& 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
1964 /* Wwe know that the source register is 31 already, but
1965 it can't hurt to compute it. */
1966 ev_reg
= GET_SRC_REG (op
);
1967 ev_offset
= ((op
>> 11) & 0x1f) * 8;
1968 /* If this is the first vector reg to be saved, or if
1969 it has a lower number than others previously seen,
1970 reupdate the frame info. */
1971 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1973 fdata
->saved_ev
= ev_reg
;
1974 fdata
->ev_offset
= ev_offset
+ offset
;
1979 /* Store gen register S at (r31+r0).
1980 Store param on stack when offset from SP bigger than 4 bytes. */
1981 /* 000100 sssss 11111 00000 01100100000 */
1982 else if (arch_info
->mach
== bfd_mach_ppc_e500
1983 && (op
& 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
1985 if (pc
== (li_found_pc
+ 4))
1987 if ((op
& 0x03e00000) >= 0x01a00000)
1989 ev_reg
= GET_SRC_REG (op
);
1990 /* If this is the first vector reg to be saved, or if
1991 it has a lower number than others previously seen,
1992 reupdate the frame info. */
1993 /* We know the contents of r0 from the previous
1995 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1997 fdata
->saved_ev
= ev_reg
;
1998 fdata
->ev_offset
= vr_saved_offset
+ offset
;
2002 vr_saved_offset
= -1;
2007 /* End BookE related instructions. */
2011 unsigned int all_mask
= ~((1U << fdata
->saved_gpr
) - 1);
2013 /* Not a recognized prologue instruction.
2014 Handle optimizer code motions into the prologue by continuing
2015 the search if we have no valid frame yet or if the return
2016 address is not yet saved in the frame. Also skip instructions
2017 if some of the GPRs expected to be saved are not yet saved. */
2018 if (fdata
->frameless
== 0 && fdata
->nosavedpc
== 0
2019 && (fdata
->gpr_mask
& all_mask
) == all_mask
)
2022 if (op
== 0x4e800020 /* blr */
2023 || op
== 0x4e800420) /* bctr */
2024 /* Do not scan past epilogue in frameless functions or
2027 if ((op
& 0xf4000000) == 0x40000000) /* bxx */
2028 /* Never skip branches. */
2031 if (num_skip_non_prologue_insns
++ > max_skip_non_prologue_insns
)
2032 /* Do not scan too many insns, scanning insns is expensive with
2036 /* Continue scanning. */
2037 prev_insn_was_prologue_insn
= 0;
2043 /* I have problems with skipping over __main() that I need to address
2044 * sometime. Previously, I used to use misc_function_vector which
2045 * didn't work as well as I wanted to be. -MGO */
2047 /* If the first thing after skipping a prolog is a branch to a function,
2048 this might be a call to an initializer in main(), introduced by gcc2.
2049 We'd like to skip over it as well. Fortunately, xlc does some extra
2050 work before calling a function right after a prologue, thus we can
2051 single out such gcc2 behaviour. */
2054 if ((op
& 0xfc000001) == 0x48000001)
2055 { /* bl foo, an initializer function? */
2056 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
2058 if (op
== 0x4def7b82)
2059 { /* cror 0xf, 0xf, 0xf (nop) */
2061 /* Check and see if we are in main. If so, skip over this
2062 initializer function as well. */
2064 tmp
= find_pc_misc_function (pc
);
2066 && strcmp (misc_function_vector
[tmp
].name
, main_name ()) == 0)
2072 if (pc
== lim_pc
&& lr_reg
>= 0)
2073 fdata
->lr_register
= lr_reg
;
2075 fdata
->offset
= -fdata
->offset
;
2076 return last_prologue_pc
;
2080 rs6000_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2082 struct rs6000_framedata frame
;
2083 CORE_ADDR limit_pc
, func_addr
;
2085 /* See if we can determine the end of the prologue via the symbol table.
2086 If so, then return either PC, or the PC after the prologue, whichever
2088 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
2090 CORE_ADDR post_prologue_pc
2091 = skip_prologue_using_sal (gdbarch
, func_addr
);
2092 if (post_prologue_pc
!= 0)
2093 return max (pc
, post_prologue_pc
);
2096 /* Can't determine prologue from the symbol table, need to examine
2099 /* Find an upper limit on the function prologue using the debug
2100 information. If the debug information could not be used to provide
2101 that bound, then use an arbitrary large number as the upper bound. */
2102 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
2104 limit_pc
= pc
+ 100; /* Magic. */
2106 pc
= skip_prologue (gdbarch
, pc
, limit_pc
, &frame
);
2110 /* When compiling for EABI, some versions of GCC emit a call to __eabi
2111 in the prologue of main().
2113 The function below examines the code pointed at by PC and checks to
2114 see if it corresponds to a call to __eabi. If so, it returns the
2115 address of the instruction following that call. Otherwise, it simply
2119 rs6000_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2121 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2125 if (target_read_memory (pc
, buf
, 4))
2127 op
= extract_unsigned_integer (buf
, 4, byte_order
);
2129 if ((op
& BL_MASK
) == BL_INSTRUCTION
)
2131 CORE_ADDR displ
= op
& BL_DISPLACEMENT_MASK
;
2132 CORE_ADDR call_dest
= pc
+ 4 + displ
;
2133 struct minimal_symbol
*s
= lookup_minimal_symbol_by_pc (call_dest
);
2135 /* We check for ___eabi (three leading underscores) in addition
2136 to __eabi in case the GCC option "-fleading-underscore" was
2137 used to compile the program. */
2139 && SYMBOL_LINKAGE_NAME (s
) != NULL
2140 && (strcmp (SYMBOL_LINKAGE_NAME (s
), "__eabi") == 0
2141 || strcmp (SYMBOL_LINKAGE_NAME (s
), "___eabi") == 0))
2147 /* All the ABI's require 16 byte alignment. */
2149 rs6000_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2151 return (addr
& -16);
2154 /* Return whether handle_inferior_event() should proceed through code
2155 starting at PC in function NAME when stepping.
2157 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
2158 handle memory references that are too distant to fit in instructions
2159 generated by the compiler. For example, if 'foo' in the following
2164 is greater than 32767, the linker might replace the lwz with a branch to
2165 somewhere in @FIX1 that does the load in 2 instructions and then branches
2166 back to where execution should continue.
2168 GDB should silently step over @FIX code, just like AIX dbx does.
2169 Unfortunately, the linker uses the "b" instruction for the
2170 branches, meaning that the link register doesn't get set.
2171 Therefore, GDB's usual step_over_function () mechanism won't work.
2173 Instead, use the gdbarch_skip_trampoline_code and
2174 gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past
2178 rs6000_in_solib_return_trampoline (struct gdbarch
*gdbarch
,
2179 CORE_ADDR pc
, char *name
)
2181 return name
&& !strncmp (name
, "@FIX", 4);
2184 /* Skip code that the user doesn't want to see when stepping:
2186 1. Indirect function calls use a piece of trampoline code to do context
2187 switching, i.e. to set the new TOC table. Skip such code if we are on
2188 its first instruction (as when we have single-stepped to here).
2190 2. Skip shared library trampoline code (which is different from
2191 indirect function call trampolines).
2193 3. Skip bigtoc fixup code.
2195 Result is desired PC to step until, or NULL if we are not in
2196 code that should be skipped. */
2199 rs6000_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
2201 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2202 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2203 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2204 unsigned int ii
, op
;
2206 CORE_ADDR solib_target_pc
;
2207 struct minimal_symbol
*msymbol
;
2209 static unsigned trampoline_code
[] =
2211 0x800b0000, /* l r0,0x0(r11) */
2212 0x90410014, /* st r2,0x14(r1) */
2213 0x7c0903a6, /* mtctr r0 */
2214 0x804b0004, /* l r2,0x4(r11) */
2215 0x816b0008, /* l r11,0x8(r11) */
2216 0x4e800420, /* bctr */
2217 0x4e800020, /* br */
2221 /* Check for bigtoc fixup code. */
2222 msymbol
= lookup_minimal_symbol_by_pc (pc
);
2224 && rs6000_in_solib_return_trampoline (gdbarch
, pc
,
2225 SYMBOL_LINKAGE_NAME (msymbol
)))
2227 /* Double-check that the third instruction from PC is relative "b". */
2228 op
= read_memory_integer (pc
+ 8, 4, byte_order
);
2229 if ((op
& 0xfc000003) == 0x48000000)
2231 /* Extract bits 6-29 as a signed 24-bit relative word address and
2232 add it to the containing PC. */
2233 rel
= ((int)(op
<< 6) >> 6);
2234 return pc
+ 8 + rel
;
2238 /* If pc is in a shared library trampoline, return its target. */
2239 solib_target_pc
= find_solib_trampoline_target (frame
, pc
);
2240 if (solib_target_pc
)
2241 return solib_target_pc
;
2243 for (ii
= 0; trampoline_code
[ii
]; ++ii
)
2245 op
= read_memory_integer (pc
+ (ii
* 4), 4, byte_order
);
2246 if (op
!= trampoline_code
[ii
])
2249 ii
= get_frame_register_unsigned (frame
, 11); /* r11 holds destination addr */
2250 pc
= read_memory_unsigned_integer (ii
, tdep
->wordsize
, byte_order
);
2254 /* ISA-specific vector types. */
2256 static struct type
*
2257 rs6000_builtin_type_vec64 (struct gdbarch
*gdbarch
)
2259 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2261 if (!tdep
->ppc_builtin_type_vec64
)
2263 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2265 /* The type we're building is this: */
2267 union __gdb_builtin_type_vec64
2271 int32_t v2_int32
[2];
2272 int16_t v4_int16
[4];
2279 t
= arch_composite_type (gdbarch
,
2280 "__ppc_builtin_type_vec64", TYPE_CODE_UNION
);
2281 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2282 append_composite_type_field (t
, "v2_float",
2283 init_vector_type (bt
->builtin_float
, 2));
2284 append_composite_type_field (t
, "v2_int32",
2285 init_vector_type (bt
->builtin_int32
, 2));
2286 append_composite_type_field (t
, "v4_int16",
2287 init_vector_type (bt
->builtin_int16
, 4));
2288 append_composite_type_field (t
, "v8_int8",
2289 init_vector_type (bt
->builtin_int8
, 8));
2291 TYPE_VECTOR (t
) = 1;
2292 TYPE_NAME (t
) = "ppc_builtin_type_vec64";
2293 tdep
->ppc_builtin_type_vec64
= t
;
2296 return tdep
->ppc_builtin_type_vec64
;
2299 /* Vector 128 type. */
2301 static struct type
*
2302 rs6000_builtin_type_vec128 (struct gdbarch
*gdbarch
)
2304 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2306 if (!tdep
->ppc_builtin_type_vec128
)
2308 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2310 /* The type we're building is this
2312 type = union __ppc_builtin_type_vec128 {
2314 double v2_double[2];
2316 int32_t v4_int32[4];
2317 int16_t v8_int16[8];
2318 int8_t v16_int8[16];
2324 t
= arch_composite_type (gdbarch
,
2325 "__ppc_builtin_type_vec128", TYPE_CODE_UNION
);
2326 append_composite_type_field (t
, "uint128", bt
->builtin_uint128
);
2327 append_composite_type_field (t
, "v2_double",
2328 init_vector_type (bt
->builtin_double
, 2));
2329 append_composite_type_field (t
, "v4_float",
2330 init_vector_type (bt
->builtin_float
, 4));
2331 append_composite_type_field (t
, "v4_int32",
2332 init_vector_type (bt
->builtin_int32
, 4));
2333 append_composite_type_field (t
, "v8_int16",
2334 init_vector_type (bt
->builtin_int16
, 8));
2335 append_composite_type_field (t
, "v16_int8",
2336 init_vector_type (bt
->builtin_int8
, 16));
2338 TYPE_VECTOR (t
) = 1;
2339 TYPE_NAME (t
) = "ppc_builtin_type_vec128";
2340 tdep
->ppc_builtin_type_vec128
= t
;
2343 return tdep
->ppc_builtin_type_vec128
;
2346 /* Return the name of register number REGNO, or the empty string if it
2347 is an anonymous register. */
2350 rs6000_register_name (struct gdbarch
*gdbarch
, int regno
)
2352 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2354 /* The upper half "registers" have names in the XML description,
2355 but we present only the low GPRs and the full 64-bit registers
2357 if (tdep
->ppc_ev0_upper_regnum
>= 0
2358 && tdep
->ppc_ev0_upper_regnum
<= regno
2359 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
2362 /* Hide the upper halves of the vs0~vs31 registers. */
2363 if (tdep
->ppc_vsr0_regnum
>= 0
2364 && tdep
->ppc_vsr0_upper_regnum
<= regno
2365 && regno
< tdep
->ppc_vsr0_upper_regnum
+ ppc_num_gprs
)
2368 /* Check if the SPE pseudo registers are available. */
2369 if (IS_SPE_PSEUDOREG (tdep
, regno
))
2371 static const char *const spe_regnames
[] = {
2372 "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7",
2373 "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15",
2374 "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23",
2375 "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31",
2377 return spe_regnames
[regno
- tdep
->ppc_ev0_regnum
];
2380 /* Check if the decimal128 pseudo-registers are available. */
2381 if (IS_DFP_PSEUDOREG (tdep
, regno
))
2383 static const char *const dfp128_regnames
[] = {
2384 "dl0", "dl1", "dl2", "dl3",
2385 "dl4", "dl5", "dl6", "dl7",
2386 "dl8", "dl9", "dl10", "dl11",
2387 "dl12", "dl13", "dl14", "dl15"
2389 return dfp128_regnames
[regno
- tdep
->ppc_dl0_regnum
];
2392 /* Check if this is a VSX pseudo-register. */
2393 if (IS_VSX_PSEUDOREG (tdep
, regno
))
2395 static const char *const vsx_regnames
[] = {
2396 "vs0", "vs1", "vs2", "vs3", "vs4", "vs5", "vs6", "vs7",
2397 "vs8", "vs9", "vs10", "vs11", "vs12", "vs13", "vs14",
2398 "vs15", "vs16", "vs17", "vs18", "vs19", "vs20", "vs21",
2399 "vs22", "vs23", "vs24", "vs25", "vs26", "vs27", "vs28",
2400 "vs29", "vs30", "vs31", "vs32", "vs33", "vs34", "vs35",
2401 "vs36", "vs37", "vs38", "vs39", "vs40", "vs41", "vs42",
2402 "vs43", "vs44", "vs45", "vs46", "vs47", "vs48", "vs49",
2403 "vs50", "vs51", "vs52", "vs53", "vs54", "vs55", "vs56",
2404 "vs57", "vs58", "vs59", "vs60", "vs61", "vs62", "vs63"
2406 return vsx_regnames
[regno
- tdep
->ppc_vsr0_regnum
];
2409 /* Check if the this is a Extended FP pseudo-register. */
2410 if (IS_EFP_PSEUDOREG (tdep
, regno
))
2412 static const char *const efpr_regnames
[] = {
2413 "f32", "f33", "f34", "f35", "f36", "f37", "f38",
2414 "f39", "f40", "f41", "f42", "f43", "f44", "f45",
2415 "f46", "f47", "f48", "f49", "f50", "f51",
2416 "f52", "f53", "f54", "f55", "f56", "f57",
2417 "f58", "f59", "f60", "f61", "f62", "f63"
2419 return efpr_regnames
[regno
- tdep
->ppc_efpr0_regnum
];
2422 return tdesc_register_name (gdbarch
, regno
);
2425 /* Return the GDB type object for the "standard" data type of data in
2428 static struct type
*
2429 rs6000_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2431 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2433 /* These are the only pseudo-registers we support. */
2434 gdb_assert (IS_SPE_PSEUDOREG (tdep
, regnum
)
2435 || IS_DFP_PSEUDOREG (tdep
, regnum
)
2436 || IS_VSX_PSEUDOREG (tdep
, regnum
)
2437 || IS_EFP_PSEUDOREG (tdep
, regnum
));
2439 /* These are the e500 pseudo-registers. */
2440 if (IS_SPE_PSEUDOREG (tdep
, regnum
))
2441 return rs6000_builtin_type_vec64 (gdbarch
);
2442 else if (IS_DFP_PSEUDOREG (tdep
, regnum
))
2443 /* PPC decimal128 pseudo-registers. */
2444 return builtin_type (gdbarch
)->builtin_declong
;
2445 else if (IS_VSX_PSEUDOREG (tdep
, regnum
))
2446 /* POWER7 VSX pseudo-registers. */
2447 return rs6000_builtin_type_vec128 (gdbarch
);
2449 /* POWER7 Extended FP pseudo-registers. */
2450 return builtin_type (gdbarch
)->builtin_double
;
2453 /* Is REGNUM a member of REGGROUP? */
2455 rs6000_pseudo_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2456 struct reggroup
*group
)
2458 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2460 /* These are the only pseudo-registers we support. */
2461 gdb_assert (IS_SPE_PSEUDOREG (tdep
, regnum
)
2462 || IS_DFP_PSEUDOREG (tdep
, regnum
)
2463 || IS_VSX_PSEUDOREG (tdep
, regnum
)
2464 || IS_EFP_PSEUDOREG (tdep
, regnum
));
2466 /* These are the e500 pseudo-registers or the POWER7 VSX registers. */
2467 if (IS_SPE_PSEUDOREG (tdep
, regnum
) || IS_VSX_PSEUDOREG (tdep
, regnum
))
2468 return group
== all_reggroup
|| group
== vector_reggroup
;
2470 /* PPC decimal128 or Extended FP pseudo-registers. */
2471 return group
== all_reggroup
|| group
== float_reggroup
;
2474 /* The register format for RS/6000 floating point registers is always
2475 double, we need a conversion if the memory format is float. */
2478 rs6000_convert_register_p (struct gdbarch
*gdbarch
, int regnum
,
2481 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2483 return (tdep
->ppc_fp0_regnum
>= 0
2484 && regnum
>= tdep
->ppc_fp0_regnum
2485 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
2486 && TYPE_CODE (type
) == TYPE_CODE_FLT
2487 && TYPE_LENGTH (type
)
2488 != TYPE_LENGTH (builtin_type (gdbarch
)->builtin_double
));
2492 rs6000_register_to_value (struct frame_info
*frame
,
2497 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2498 gdb_byte from
[MAX_REGISTER_SIZE
];
2500 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
2502 get_frame_register (frame
, regnum
, from
);
2503 convert_typed_floating (from
, builtin_type (gdbarch
)->builtin_double
,
2508 rs6000_value_to_register (struct frame_info
*frame
,
2511 const gdb_byte
*from
)
2513 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2514 gdb_byte to
[MAX_REGISTER_SIZE
];
2516 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
2518 convert_typed_floating (from
, type
,
2519 to
, builtin_type (gdbarch
)->builtin_double
);
2520 put_frame_register (frame
, regnum
, to
);
2523 /* Move SPE vector register values between a 64-bit buffer and the two
2524 32-bit raw register halves in a regcache. This function handles
2525 both splitting a 64-bit value into two 32-bit halves, and joining
2526 two halves into a whole 64-bit value, depending on the function
2527 passed as the MOVE argument.
2529 EV_REG must be the number of an SPE evN vector register --- a
2530 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2533 Call MOVE once for each 32-bit half of that register, passing
2534 REGCACHE, the number of the raw register corresponding to that
2535 half, and the address of the appropriate half of BUFFER.
2537 For example, passing 'regcache_raw_read' as the MOVE function will
2538 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2539 'regcache_raw_supply' will supply the contents of BUFFER to the
2540 appropriate pair of raw registers in REGCACHE.
2542 You may need to cast away some 'const' qualifiers when passing
2543 MOVE, since this function can't tell at compile-time which of
2544 REGCACHE or BUFFER is acting as the source of the data. If C had
2545 co-variant type qualifiers, ... */
2547 e500_move_ev_register (void (*move
) (struct regcache
*regcache
,
2548 int regnum
, gdb_byte
*buf
),
2549 struct regcache
*regcache
, int ev_reg
,
2552 struct gdbarch
*arch
= get_regcache_arch (regcache
);
2553 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
2555 gdb_byte
*byte_buffer
= buffer
;
2557 gdb_assert (IS_SPE_PSEUDOREG (tdep
, ev_reg
));
2559 reg_index
= ev_reg
- tdep
->ppc_ev0_regnum
;
2561 if (gdbarch_byte_order (arch
) == BFD_ENDIAN_BIG
)
2563 move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
, byte_buffer
);
2564 move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
, byte_buffer
+ 4);
2568 move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
, byte_buffer
);
2569 move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
, byte_buffer
+ 4);
2574 e500_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2575 int reg_nr
, gdb_byte
*buffer
)
2577 e500_move_ev_register (regcache_raw_read
, regcache
, reg_nr
, buffer
);
2581 e500_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2582 int reg_nr
, const gdb_byte
*buffer
)
2584 e500_move_ev_register ((void (*) (struct regcache
*, int, gdb_byte
*))
2586 regcache
, reg_nr
, (gdb_byte
*) buffer
);
2589 /* Read method for DFP pseudo-registers. */
2591 dfp_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2592 int reg_nr
, gdb_byte
*buffer
)
2594 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2595 int reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2597 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2599 /* Read two FP registers to form a whole dl register. */
2600 regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2601 2 * reg_index
, buffer
);
2602 regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2603 2 * reg_index
+ 1, buffer
+ 8);
2607 regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2608 2 * reg_index
+ 1, buffer
+ 8);
2609 regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2610 2 * reg_index
, buffer
);
2614 /* Write method for DFP pseudo-registers. */
2616 dfp_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2617 int reg_nr
, const gdb_byte
*buffer
)
2619 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2620 int reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2622 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2624 /* Write each half of the dl register into a separate
2626 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2627 2 * reg_index
, buffer
);
2628 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2629 2 * reg_index
+ 1, buffer
+ 8);
2633 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2634 2 * reg_index
+ 1, buffer
+ 8);
2635 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2636 2 * reg_index
, buffer
);
2640 /* Read method for POWER7 VSX pseudo-registers. */
2642 vsx_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2643 int reg_nr
, gdb_byte
*buffer
)
2645 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2646 int reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2648 /* Read the portion that overlaps the VMX registers. */
2650 regcache_raw_read (regcache
, tdep
->ppc_vr0_regnum
+
2651 reg_index
- 32, buffer
);
2653 /* Read the portion that overlaps the FPR registers. */
2654 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2656 regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2658 regcache_raw_read (regcache
, tdep
->ppc_vsr0_upper_regnum
+
2659 reg_index
, buffer
+ 8);
2663 regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2664 reg_index
, buffer
+ 8);
2665 regcache_raw_read (regcache
, tdep
->ppc_vsr0_upper_regnum
+
2670 /* Write method for POWER7 VSX pseudo-registers. */
2672 vsx_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2673 int reg_nr
, const gdb_byte
*buffer
)
2675 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2676 int reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2678 /* Write the portion that overlaps the VMX registers. */
2680 regcache_raw_write (regcache
, tdep
->ppc_vr0_regnum
+
2681 reg_index
- 32, buffer
);
2683 /* Write the portion that overlaps the FPR registers. */
2684 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2686 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2688 regcache_raw_write (regcache
, tdep
->ppc_vsr0_upper_regnum
+
2689 reg_index
, buffer
+ 8);
2693 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2694 reg_index
, buffer
+ 8);
2695 regcache_raw_write (regcache
, tdep
->ppc_vsr0_upper_regnum
+
2700 /* Read method for POWER7 Extended FP pseudo-registers. */
2702 efpr_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2703 int reg_nr
, gdb_byte
*buffer
)
2705 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2706 int reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
2708 /* Read the portion that overlaps the VMX registers. */
2709 regcache_raw_read (regcache
, tdep
->ppc_vr0_regnum
+
2713 /* Write method for POWER7 Extended FP pseudo-registers. */
2715 efpr_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2716 int reg_nr
, const gdb_byte
*buffer
)
2718 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2719 int reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
2721 /* Write the portion that overlaps the VMX registers. */
2722 regcache_raw_write (regcache
, tdep
->ppc_vr0_regnum
+
2727 rs6000_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2728 int reg_nr
, gdb_byte
*buffer
)
2730 struct gdbarch
*regcache_arch
= get_regcache_arch (regcache
);
2731 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2733 gdb_assert (regcache_arch
== gdbarch
);
2735 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2736 e500_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2737 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2738 dfp_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2739 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2740 vsx_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2741 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
2742 efpr_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2744 internal_error (__FILE__
, __LINE__
,
2745 _("rs6000_pseudo_register_read: "
2746 "called on unexpected register '%s' (%d)"),
2747 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2751 rs6000_pseudo_register_write (struct gdbarch
*gdbarch
,
2752 struct regcache
*regcache
,
2753 int reg_nr
, const gdb_byte
*buffer
)
2755 struct gdbarch
*regcache_arch
= get_regcache_arch (regcache
);
2756 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2758 gdb_assert (regcache_arch
== gdbarch
);
2760 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2761 e500_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2762 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2763 dfp_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2764 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2765 vsx_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2766 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
2767 efpr_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2769 internal_error (__FILE__
, __LINE__
,
2770 _("rs6000_pseudo_register_write: "
2771 "called on unexpected register '%s' (%d)"),
2772 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2775 /* Convert a DBX STABS register number to a GDB register number. */
2777 rs6000_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
2779 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2781 if (0 <= num
&& num
<= 31)
2782 return tdep
->ppc_gp0_regnum
+ num
;
2783 else if (32 <= num
&& num
<= 63)
2784 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2785 specifies registers the architecture doesn't have? Our
2786 callers don't check the value we return. */
2787 return tdep
->ppc_fp0_regnum
+ (num
- 32);
2788 else if (77 <= num
&& num
<= 108)
2789 return tdep
->ppc_vr0_regnum
+ (num
- 77);
2790 else if (1200 <= num
&& num
< 1200 + 32)
2791 return tdep
->ppc_ev0_regnum
+ (num
- 1200);
2796 return tdep
->ppc_mq_regnum
;
2798 return tdep
->ppc_lr_regnum
;
2800 return tdep
->ppc_ctr_regnum
;
2802 return tdep
->ppc_xer_regnum
;
2804 return tdep
->ppc_vrsave_regnum
;
2806 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
2808 return tdep
->ppc_acc_regnum
;
2810 return tdep
->ppc_spefscr_regnum
;
2817 /* Convert a Dwarf 2 register number to a GDB register number. */
2819 rs6000_dwarf2_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
2821 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2823 if (0 <= num
&& num
<= 31)
2824 return tdep
->ppc_gp0_regnum
+ num
;
2825 else if (32 <= num
&& num
<= 63)
2826 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2827 specifies registers the architecture doesn't have? Our
2828 callers don't check the value we return. */
2829 return tdep
->ppc_fp0_regnum
+ (num
- 32);
2830 else if (1124 <= num
&& num
< 1124 + 32)
2831 return tdep
->ppc_vr0_regnum
+ (num
- 1124);
2832 else if (1200 <= num
&& num
< 1200 + 32)
2833 return tdep
->ppc_ev0_regnum
+ (num
- 1200);
2838 return tdep
->ppc_cr_regnum
;
2840 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
2842 return tdep
->ppc_acc_regnum
;
2844 return tdep
->ppc_mq_regnum
;
2846 return tdep
->ppc_xer_regnum
;
2848 return tdep
->ppc_lr_regnum
;
2850 return tdep
->ppc_ctr_regnum
;
2852 return tdep
->ppc_vrsave_regnum
;
2854 return tdep
->ppc_spefscr_regnum
;
2860 /* Translate a .eh_frame register to DWARF register, or adjust a
2861 .debug_frame register. */
2864 rs6000_adjust_frame_regnum (struct gdbarch
*gdbarch
, int num
, int eh_frame_p
)
2866 /* GCC releases before 3.4 use GCC internal register numbering in
2867 .debug_frame (and .debug_info, et cetera). The numbering is
2868 different from the standard SysV numbering for everything except
2869 for GPRs and FPRs. We can not detect this problem in most cases
2870 - to get accurate debug info for variables living in lr, ctr, v0,
2871 et cetera, use a newer version of GCC. But we must detect
2872 one important case - lr is in column 65 in .debug_frame output,
2875 GCC 3.4, and the "hammer" branch, have a related problem. They
2876 record lr register saves in .debug_frame as 108, but still record
2877 the return column as 65. We fix that up too.
2879 We can do this because 65 is assigned to fpsr, and GCC never
2880 generates debug info referring to it. To add support for
2881 handwritten debug info that restores fpsr, we would need to add a
2882 producer version check to this. */
2891 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
2892 internal register numbering; translate that to the standard DWARF2
2893 register numbering. */
2894 if (0 <= num
&& num
<= 63) /* r0-r31,fp0-fp31 */
2896 else if (68 <= num
&& num
<= 75) /* cr0-cr8 */
2897 return num
- 68 + 86;
2898 else if (77 <= num
&& num
<= 108) /* vr0-vr31 */
2899 return num
- 77 + 1124;
2911 case 109: /* vrsave */
2913 case 110: /* vscr */
2915 case 111: /* spe_acc */
2917 case 112: /* spefscr */
2925 /* Handling the various POWER/PowerPC variants. */
2927 /* Information about a particular processor variant. */
2931 /* Name of this variant. */
2934 /* English description of the variant. */
2937 /* bfd_arch_info.arch corresponding to variant. */
2938 enum bfd_architecture arch
;
2940 /* bfd_arch_info.mach corresponding to variant. */
2943 /* Target description for this variant. */
2944 struct target_desc
**tdesc
;
2947 static struct variant variants
[] =
2949 {"powerpc", "PowerPC user-level", bfd_arch_powerpc
,
2950 bfd_mach_ppc
, &tdesc_powerpc_altivec32
},
2951 {"power", "POWER user-level", bfd_arch_rs6000
,
2952 bfd_mach_rs6k
, &tdesc_rs6000
},
2953 {"403", "IBM PowerPC 403", bfd_arch_powerpc
,
2954 bfd_mach_ppc_403
, &tdesc_powerpc_403
},
2955 {"405", "IBM PowerPC 405", bfd_arch_powerpc
,
2956 bfd_mach_ppc_405
, &tdesc_powerpc_405
},
2957 {"601", "Motorola PowerPC 601", bfd_arch_powerpc
,
2958 bfd_mach_ppc_601
, &tdesc_powerpc_601
},
2959 {"602", "Motorola PowerPC 602", bfd_arch_powerpc
,
2960 bfd_mach_ppc_602
, &tdesc_powerpc_602
},
2961 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc
,
2962 bfd_mach_ppc_603
, &tdesc_powerpc_603
},
2963 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc
,
2964 604, &tdesc_powerpc_604
},
2965 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc
,
2966 bfd_mach_ppc_403gc
, &tdesc_powerpc_403gc
},
2967 {"505", "Motorola PowerPC 505", bfd_arch_powerpc
,
2968 bfd_mach_ppc_505
, &tdesc_powerpc_505
},
2969 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc
,
2970 bfd_mach_ppc_860
, &tdesc_powerpc_860
},
2971 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc
,
2972 bfd_mach_ppc_750
, &tdesc_powerpc_750
},
2973 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc
,
2974 bfd_mach_ppc_7400
, &tdesc_powerpc_7400
},
2975 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc
,
2976 bfd_mach_ppc_e500
, &tdesc_powerpc_e500
},
2979 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc
,
2980 bfd_mach_ppc64
, &tdesc_powerpc_altivec64
},
2981 {"620", "Motorola PowerPC 620", bfd_arch_powerpc
,
2982 bfd_mach_ppc_620
, &tdesc_powerpc_64
},
2983 {"630", "Motorola PowerPC 630", bfd_arch_powerpc
,
2984 bfd_mach_ppc_630
, &tdesc_powerpc_64
},
2985 {"a35", "PowerPC A35", bfd_arch_powerpc
,
2986 bfd_mach_ppc_a35
, &tdesc_powerpc_64
},
2987 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc
,
2988 bfd_mach_ppc_rs64ii
, &tdesc_powerpc_64
},
2989 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc
,
2990 bfd_mach_ppc_rs64iii
, &tdesc_powerpc_64
},
2992 /* FIXME: I haven't checked the register sets of the following. */
2993 {"rs1", "IBM POWER RS1", bfd_arch_rs6000
,
2994 bfd_mach_rs6k_rs1
, &tdesc_rs6000
},
2995 {"rsc", "IBM POWER RSC", bfd_arch_rs6000
,
2996 bfd_mach_rs6k_rsc
, &tdesc_rs6000
},
2997 {"rs2", "IBM POWER RS2", bfd_arch_rs6000
,
2998 bfd_mach_rs6k_rs2
, &tdesc_rs6000
},
3003 /* Return the variant corresponding to architecture ARCH and machine number
3004 MACH. If no such variant exists, return null. */
3006 static const struct variant
*
3007 find_variant_by_arch (enum bfd_architecture arch
, unsigned long mach
)
3009 const struct variant
*v
;
3011 for (v
= variants
; v
->name
; v
++)
3012 if (arch
== v
->arch
&& mach
== v
->mach
)
3019 gdb_print_insn_powerpc (bfd_vma memaddr
, disassemble_info
*info
)
3021 if (!info
->disassembler_options
)
3022 info
->disassembler_options
= "any";
3024 if (info
->endian
== BFD_ENDIAN_BIG
)
3025 return print_insn_big_powerpc (memaddr
, info
);
3027 return print_insn_little_powerpc (memaddr
, info
);
3031 rs6000_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
3033 return frame_unwind_register_unsigned (next_frame
,
3034 gdbarch_pc_regnum (gdbarch
));
3037 static struct frame_id
3038 rs6000_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3040 return frame_id_build (get_frame_register_unsigned
3041 (this_frame
, gdbarch_sp_regnum (gdbarch
)),
3042 get_frame_pc (this_frame
));
3045 struct rs6000_frame_cache
3048 CORE_ADDR initial_sp
;
3049 struct trad_frame_saved_reg
*saved_regs
;
3052 static struct rs6000_frame_cache
*
3053 rs6000_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3055 struct rs6000_frame_cache
*cache
;
3056 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3057 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3058 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3059 struct rs6000_framedata fdata
;
3060 int wordsize
= tdep
->wordsize
;
3063 if ((*this_cache
) != NULL
)
3064 return (*this_cache
);
3065 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
3066 (*this_cache
) = cache
;
3067 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3069 func
= get_frame_func (this_frame
);
3070 pc
= get_frame_pc (this_frame
);
3071 skip_prologue (gdbarch
, func
, pc
, &fdata
);
3073 /* Figure out the parent's stack pointer. */
3075 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
3076 address of the current frame. Things might be easier if the
3077 ->frame pointed to the outer-most address of the frame. In
3078 the mean time, the address of the prev frame is used as the
3079 base address of this frame. */
3080 cache
->base
= get_frame_register_unsigned
3081 (this_frame
, gdbarch_sp_regnum (gdbarch
));
3083 /* If the function appears to be frameless, check a couple of likely
3084 indicators that we have simply failed to find the frame setup.
3085 Two common cases of this are missing symbols (i.e.
3086 get_frame_func returns the wrong address or 0), and assembly
3087 stubs which have a fast exit path but set up a frame on the slow
3090 If the LR appears to return to this function, then presume that
3091 we have an ABI compliant frame that we failed to find. */
3092 if (fdata
.frameless
&& fdata
.lr_offset
== 0)
3097 saved_lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
3098 if (func
== 0 && saved_lr
== pc
)
3102 CORE_ADDR saved_func
= get_pc_function_start (saved_lr
);
3103 if (func
== saved_func
)
3109 fdata
.frameless
= 0;
3110 fdata
.lr_offset
= tdep
->lr_frame_offset
;
3114 if (!fdata
.frameless
)
3115 /* Frameless really means stackless. */
3117 = read_memory_unsigned_integer (cache
->base
, wordsize
, byte_order
);
3119 trad_frame_set_value (cache
->saved_regs
,
3120 gdbarch_sp_regnum (gdbarch
), cache
->base
);
3122 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
3123 All fpr's from saved_fpr to fp31 are saved. */
3125 if (fdata
.saved_fpr
>= 0)
3128 CORE_ADDR fpr_addr
= cache
->base
+ fdata
.fpr_offset
;
3130 /* If skip_prologue says floating-point registers were saved,
3131 but the current architecture has no floating-point registers,
3132 then that's strange. But we have no indices to even record
3133 the addresses under, so we just ignore it. */
3134 if (ppc_floating_point_unit_p (gdbarch
))
3135 for (i
= fdata
.saved_fpr
; i
< ppc_num_fprs
; i
++)
3137 cache
->saved_regs
[tdep
->ppc_fp0_regnum
+ i
].addr
= fpr_addr
;
3142 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
3143 All gpr's from saved_gpr to gpr31 are saved (except during the
3146 if (fdata
.saved_gpr
>= 0)
3149 CORE_ADDR gpr_addr
= cache
->base
+ fdata
.gpr_offset
;
3150 for (i
= fdata
.saved_gpr
; i
< ppc_num_gprs
; i
++)
3152 if (fdata
.gpr_mask
& (1U << i
))
3153 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= gpr_addr
;
3154 gpr_addr
+= wordsize
;
3158 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
3159 All vr's from saved_vr to vr31 are saved. */
3160 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
3162 if (fdata
.saved_vr
>= 0)
3165 CORE_ADDR vr_addr
= cache
->base
+ fdata
.vr_offset
;
3166 for (i
= fdata
.saved_vr
; i
< 32; i
++)
3168 cache
->saved_regs
[tdep
->ppc_vr0_regnum
+ i
].addr
= vr_addr
;
3169 vr_addr
+= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
3174 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
3175 All vr's from saved_ev to ev31 are saved. ????? */
3176 if (tdep
->ppc_ev0_regnum
!= -1)
3178 if (fdata
.saved_ev
>= 0)
3181 CORE_ADDR ev_addr
= cache
->base
+ fdata
.ev_offset
;
3182 for (i
= fdata
.saved_ev
; i
< ppc_num_gprs
; i
++)
3184 cache
->saved_regs
[tdep
->ppc_ev0_regnum
+ i
].addr
= ev_addr
;
3185 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= ev_addr
+ 4;
3186 ev_addr
+= register_size (gdbarch
, tdep
->ppc_ev0_regnum
);
3191 /* If != 0, fdata.cr_offset is the offset from the frame that
3193 if (fdata
.cr_offset
!= 0)
3194 cache
->saved_regs
[tdep
->ppc_cr_regnum
].addr
= cache
->base
+ fdata
.cr_offset
;
3196 /* If != 0, fdata.lr_offset is the offset from the frame that
3198 if (fdata
.lr_offset
!= 0)
3199 cache
->saved_regs
[tdep
->ppc_lr_regnum
].addr
= cache
->base
+ fdata
.lr_offset
;
3200 else if (fdata
.lr_register
!= -1)
3201 cache
->saved_regs
[tdep
->ppc_lr_regnum
].realreg
= fdata
.lr_register
;
3202 /* The PC is found in the link register. */
3203 cache
->saved_regs
[gdbarch_pc_regnum (gdbarch
)] =
3204 cache
->saved_regs
[tdep
->ppc_lr_regnum
];
3206 /* If != 0, fdata.vrsave_offset is the offset from the frame that
3207 holds the VRSAVE. */
3208 if (fdata
.vrsave_offset
!= 0)
3209 cache
->saved_regs
[tdep
->ppc_vrsave_regnum
].addr
= cache
->base
+ fdata
.vrsave_offset
;
3211 if (fdata
.alloca_reg
< 0)
3212 /* If no alloca register used, then fi->frame is the value of the
3213 %sp for this frame, and it is good enough. */
3215 = get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
3218 = get_frame_register_unsigned (this_frame
, fdata
.alloca_reg
);
3224 rs6000_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3225 struct frame_id
*this_id
)
3227 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3229 /* This marks the outermost frame. */
3230 if (info
->base
== 0)
3233 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3236 static struct value
*
3237 rs6000_frame_prev_register (struct frame_info
*this_frame
,
3238 void **this_cache
, int regnum
)
3240 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3242 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3245 static const struct frame_unwind rs6000_frame_unwind
=
3248 rs6000_frame_this_id
,
3249 rs6000_frame_prev_register
,
3251 default_frame_sniffer
3256 rs6000_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
3258 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3260 return info
->initial_sp
;
3263 static const struct frame_base rs6000_frame_base
= {
3264 &rs6000_frame_unwind
,
3265 rs6000_frame_base_address
,
3266 rs6000_frame_base_address
,
3267 rs6000_frame_base_address
3270 static const struct frame_base
*
3271 rs6000_frame_base_sniffer (struct frame_info
*this_frame
)
3273 return &rs6000_frame_base
;
3276 /* DWARF-2 frame support. Used to handle the detection of
3277 clobbered registers during function calls. */
3280 ppc_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
3281 struct dwarf2_frame_state_reg
*reg
,
3282 struct frame_info
*this_frame
)
3284 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3286 /* PPC32 and PPC64 ABI's are the same regarding volatile and
3287 non-volatile registers. We will use the same code for both. */
3289 /* Call-saved GP registers. */
3290 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 14
3291 && regnum
<= tdep
->ppc_gp0_regnum
+ 31)
3292 || (regnum
== tdep
->ppc_gp0_regnum
+ 1))
3293 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3295 /* Call-clobbered GP registers. */
3296 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 3
3297 && regnum
<= tdep
->ppc_gp0_regnum
+ 12)
3298 || (regnum
== tdep
->ppc_gp0_regnum
))
3299 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3301 /* Deal with FP registers, if supported. */
3302 if (tdep
->ppc_fp0_regnum
>= 0)
3304 /* Call-saved FP registers. */
3305 if ((regnum
>= tdep
->ppc_fp0_regnum
+ 14
3306 && regnum
<= tdep
->ppc_fp0_regnum
+ 31))
3307 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3309 /* Call-clobbered FP registers. */
3310 if ((regnum
>= tdep
->ppc_fp0_regnum
3311 && regnum
<= tdep
->ppc_fp0_regnum
+ 13))
3312 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3315 /* Deal with ALTIVEC registers, if supported. */
3316 if (tdep
->ppc_vr0_regnum
> 0 && tdep
->ppc_vrsave_regnum
> 0)
3318 /* Call-saved Altivec registers. */
3319 if ((regnum
>= tdep
->ppc_vr0_regnum
+ 20
3320 && regnum
<= tdep
->ppc_vr0_regnum
+ 31)
3321 || regnum
== tdep
->ppc_vrsave_regnum
)
3322 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3324 /* Call-clobbered Altivec registers. */
3325 if ((regnum
>= tdep
->ppc_vr0_regnum
3326 && regnum
<= tdep
->ppc_vr0_regnum
+ 19))
3327 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3330 /* Handle PC register and Stack Pointer correctly. */
3331 if (regnum
== gdbarch_pc_regnum (gdbarch
))
3332 reg
->how
= DWARF2_FRAME_REG_RA
;
3333 else if (regnum
== gdbarch_sp_regnum (gdbarch
))
3334 reg
->how
= DWARF2_FRAME_REG_CFA
;
3338 /* Initialize the current architecture based on INFO. If possible, re-use an
3339 architecture from ARCHES, which is a list of architectures already created
3340 during this debugging session.
3342 Called e.g. at program startup, when reading a core file, and when reading
3345 static struct gdbarch
*
3346 rs6000_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
3348 struct gdbarch
*gdbarch
;
3349 struct gdbarch_tdep
*tdep
;
3350 int wordsize
, from_xcoff_exec
, from_elf_exec
;
3351 enum bfd_architecture arch
;
3355 enum auto_boolean soft_float_flag
= powerpc_soft_float_global
;
3357 enum powerpc_vector_abi vector_abi
= powerpc_vector_abi_global
;
3358 int have_fpu
= 1, have_spe
= 0, have_mq
= 0, have_altivec
= 0, have_dfp
= 0,
3360 int tdesc_wordsize
= -1;
3361 const struct target_desc
*tdesc
= info
.target_desc
;
3362 struct tdesc_arch_data
*tdesc_data
= NULL
;
3363 int num_pseudoregs
= 0;
3366 /* INFO may refer to a binary that is not of the PowerPC architecture,
3367 e.g. when debugging a stand-alone SPE executable on a Cell/B.E. system.
3368 In this case, we must not attempt to infer properties of the (PowerPC
3369 side) of the target system from properties of that executable. Trust
3370 the target description instead. */
3372 && bfd_get_arch (info
.abfd
) != bfd_arch_powerpc
3373 && bfd_get_arch (info
.abfd
) != bfd_arch_rs6000
)
3376 from_xcoff_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
3377 bfd_get_flavour (info
.abfd
) == bfd_target_xcoff_flavour
;
3379 from_elf_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
3380 bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
;
3382 /* Check word size. If INFO is from a binary file, infer it from
3383 that, else choose a likely default. */
3384 if (from_xcoff_exec
)
3386 if (bfd_xcoff_is_xcoff64 (info
.abfd
))
3391 else if (from_elf_exec
)
3393 if (elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
3398 else if (tdesc_has_registers (tdesc
))
3402 if (info
.bfd_arch_info
!= NULL
&& info
.bfd_arch_info
->bits_per_word
!= 0)
3403 wordsize
= info
.bfd_arch_info
->bits_per_word
/
3404 info
.bfd_arch_info
->bits_per_byte
;
3409 /* Get the architecture and machine from the BFD. */
3410 arch
= info
.bfd_arch_info
->arch
;
3411 mach
= info
.bfd_arch_info
->mach
;
3413 /* For e500 executables, the apuinfo section is of help here. Such
3414 section contains the identifier and revision number of each
3415 Application-specific Processing Unit that is present on the
3416 chip. The content of the section is determined by the assembler
3417 which looks at each instruction and determines which unit (and
3418 which version of it) can execute it. In our case we just look for
3419 the existance of the section. */
3423 sect
= bfd_get_section_by_name (info
.abfd
, ".PPC.EMB.apuinfo");
3426 arch
= info
.bfd_arch_info
->arch
;
3427 mach
= bfd_mach_ppc_e500
;
3428 bfd_default_set_arch_mach (&abfd
, arch
, mach
);
3429 info
.bfd_arch_info
= bfd_get_arch_info (&abfd
);
3433 /* Find a default target description which describes our register
3434 layout, if we do not already have one. */
3435 if (! tdesc_has_registers (tdesc
))
3437 const struct variant
*v
;
3439 /* Choose variant. */
3440 v
= find_variant_by_arch (arch
, mach
);
3447 gdb_assert (tdesc_has_registers (tdesc
));
3449 /* Check any target description for validity. */
3450 if (tdesc_has_registers (tdesc
))
3452 static const char *const gprs
[] = {
3453 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
3454 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
3455 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
3456 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
3458 static const char *const segment_regs
[] = {
3459 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
3460 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
3462 const struct tdesc_feature
*feature
;
3464 static const char *const msr_names
[] = { "msr", "ps" };
3465 static const char *const cr_names
[] = { "cr", "cnd" };
3466 static const char *const ctr_names
[] = { "ctr", "cnt" };
3468 feature
= tdesc_find_feature (tdesc
,
3469 "org.gnu.gdb.power.core");
3470 if (feature
== NULL
)
3473 tdesc_data
= tdesc_data_alloc ();
3476 for (i
= 0; i
< ppc_num_gprs
; i
++)
3477 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
, gprs
[i
]);
3478 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_PC_REGNUM
,
3480 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_LR_REGNUM
,
3482 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_XER_REGNUM
,
3485 /* Allow alternate names for these registers, to accomodate GDB's
3487 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
3488 PPC_MSR_REGNUM
, msr_names
);
3489 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
3490 PPC_CR_REGNUM
, cr_names
);
3491 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
3492 PPC_CTR_REGNUM
, ctr_names
);
3496 tdesc_data_cleanup (tdesc_data
);
3500 have_mq
= tdesc_numbered_register (feature
, tdesc_data
, PPC_MQ_REGNUM
,
3503 tdesc_wordsize
= tdesc_register_size (feature
, "pc") / 8;
3505 wordsize
= tdesc_wordsize
;
3507 feature
= tdesc_find_feature (tdesc
,
3508 "org.gnu.gdb.power.fpu");
3509 if (feature
!= NULL
)
3511 static const char *const fprs
[] = {
3512 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
3513 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
3514 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
3515 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
3518 for (i
= 0; i
< ppc_num_fprs
; i
++)
3519 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
3520 PPC_F0_REGNUM
+ i
, fprs
[i
]);
3521 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
3522 PPC_FPSCR_REGNUM
, "fpscr");
3526 tdesc_data_cleanup (tdesc_data
);
3534 /* The DFP pseudo-registers will be available when there are floating
3536 have_dfp
= have_fpu
;
3538 feature
= tdesc_find_feature (tdesc
,
3539 "org.gnu.gdb.power.altivec");
3540 if (feature
!= NULL
)
3542 static const char *const vector_regs
[] = {
3543 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
3544 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
3545 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
3546 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31"
3550 for (i
= 0; i
< ppc_num_gprs
; i
++)
3551 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
3554 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
3555 PPC_VSCR_REGNUM
, "vscr");
3556 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
3557 PPC_VRSAVE_REGNUM
, "vrsave");
3559 if (have_spe
|| !valid_p
)
3561 tdesc_data_cleanup (tdesc_data
);
3569 /* Check for POWER7 VSX registers support. */
3570 feature
= tdesc_find_feature (tdesc
,
3571 "org.gnu.gdb.power.vsx");
3573 if (feature
!= NULL
)
3575 static const char *const vsx_regs
[] = {
3576 "vs0h", "vs1h", "vs2h", "vs3h", "vs4h", "vs5h",
3577 "vs6h", "vs7h", "vs8h", "vs9h", "vs10h", "vs11h",
3578 "vs12h", "vs13h", "vs14h", "vs15h", "vs16h", "vs17h",
3579 "vs18h", "vs19h", "vs20h", "vs21h", "vs22h", "vs23h",
3580 "vs24h", "vs25h", "vs26h", "vs27h", "vs28h", "vs29h",
3586 for (i
= 0; i
< ppc_num_vshrs
; i
++)
3587 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
3588 PPC_VSR0_UPPER_REGNUM
+ i
,
3592 tdesc_data_cleanup (tdesc_data
);
3601 /* On machines supporting the SPE APU, the general-purpose registers
3602 are 64 bits long. There are SIMD vector instructions to treat them
3603 as pairs of floats, but the rest of the instruction set treats them
3604 as 32-bit registers, and only operates on their lower halves.
3606 In the GDB regcache, we treat their high and low halves as separate
3607 registers. The low halves we present as the general-purpose
3608 registers, and then we have pseudo-registers that stitch together
3609 the upper and lower halves and present them as pseudo-registers.
3611 Thus, the target description is expected to supply the upper
3612 halves separately. */
3614 feature
= tdesc_find_feature (tdesc
,
3615 "org.gnu.gdb.power.spe");
3616 if (feature
!= NULL
)
3618 static const char *const upper_spe
[] = {
3619 "ev0h", "ev1h", "ev2h", "ev3h",
3620 "ev4h", "ev5h", "ev6h", "ev7h",
3621 "ev8h", "ev9h", "ev10h", "ev11h",
3622 "ev12h", "ev13h", "ev14h", "ev15h",
3623 "ev16h", "ev17h", "ev18h", "ev19h",
3624 "ev20h", "ev21h", "ev22h", "ev23h",
3625 "ev24h", "ev25h", "ev26h", "ev27h",
3626 "ev28h", "ev29h", "ev30h", "ev31h"
3630 for (i
= 0; i
< ppc_num_gprs
; i
++)
3631 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
3632 PPC_SPE_UPPER_GP0_REGNUM
+ i
,
3634 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
3635 PPC_SPE_ACC_REGNUM
, "acc");
3636 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
3637 PPC_SPE_FSCR_REGNUM
, "spefscr");
3639 if (have_mq
|| have_fpu
|| !valid_p
)
3641 tdesc_data_cleanup (tdesc_data
);
3650 /* If we have a 64-bit binary on a 32-bit target, complain. Also
3651 complain for a 32-bit binary on a 64-bit target; we do not yet
3652 support that. For instance, the 32-bit ABI routines expect
3655 As long as there isn't an explicit target description, we'll
3656 choose one based on the BFD architecture and get a word size
3657 matching the binary (probably powerpc:common or
3658 powerpc:common64). So there is only trouble if a 64-bit target
3659 supplies a 64-bit description while debugging a 32-bit
3661 if (tdesc_wordsize
!= -1 && tdesc_wordsize
!= wordsize
)
3663 tdesc_data_cleanup (tdesc_data
);
3668 if (soft_float_flag
== AUTO_BOOLEAN_AUTO
&& from_elf_exec
)
3670 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
3671 Tag_GNU_Power_ABI_FP
))
3674 soft_float_flag
= AUTO_BOOLEAN_FALSE
;
3677 soft_float_flag
= AUTO_BOOLEAN_TRUE
;
3684 if (vector_abi
== POWERPC_VEC_AUTO
&& from_elf_exec
)
3686 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
3687 Tag_GNU_Power_ABI_Vector
))
3690 vector_abi
= POWERPC_VEC_GENERIC
;
3693 vector_abi
= POWERPC_VEC_ALTIVEC
;
3696 vector_abi
= POWERPC_VEC_SPE
;
3704 if (soft_float_flag
== AUTO_BOOLEAN_TRUE
)
3706 else if (soft_float_flag
== AUTO_BOOLEAN_FALSE
)
3709 soft_float
= !have_fpu
;
3711 /* If we have a hard float binary or setting but no floating point
3712 registers, downgrade to soft float anyway. We're still somewhat
3713 useful in this scenario. */
3714 if (!soft_float
&& !have_fpu
)
3717 /* Similarly for vector registers. */
3718 if (vector_abi
== POWERPC_VEC_ALTIVEC
&& !have_altivec
)
3719 vector_abi
= POWERPC_VEC_GENERIC
;
3721 if (vector_abi
== POWERPC_VEC_SPE
&& !have_spe
)
3722 vector_abi
= POWERPC_VEC_GENERIC
;
3724 if (vector_abi
== POWERPC_VEC_AUTO
)
3727 vector_abi
= POWERPC_VEC_ALTIVEC
;
3729 vector_abi
= POWERPC_VEC_SPE
;
3731 vector_abi
= POWERPC_VEC_GENERIC
;
3734 /* Do not limit the vector ABI based on available hardware, since we
3735 do not yet know what hardware we'll decide we have. Yuck! FIXME! */
3737 /* Find a candidate among extant architectures. */
3738 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
3740 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
3742 /* Word size in the various PowerPC bfd_arch_info structs isn't
3743 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
3744 separate word size check. */
3745 tdep
= gdbarch_tdep (arches
->gdbarch
);
3746 if (tdep
&& tdep
->soft_float
!= soft_float
)
3748 if (tdep
&& tdep
->vector_abi
!= vector_abi
)
3750 if (tdep
&& tdep
->wordsize
== wordsize
)
3752 if (tdesc_data
!= NULL
)
3753 tdesc_data_cleanup (tdesc_data
);
3754 return arches
->gdbarch
;
3758 /* None found, create a new architecture from INFO, whose bfd_arch_info
3759 validity depends on the source:
3760 - executable useless
3761 - rs6000_host_arch() good
3763 - "set arch" trust blindly
3764 - GDB startup useless but harmless */
3766 tdep
= XCALLOC (1, struct gdbarch_tdep
);
3767 tdep
->wordsize
= wordsize
;
3768 tdep
->soft_float
= soft_float
;
3769 tdep
->vector_abi
= vector_abi
;
3771 gdbarch
= gdbarch_alloc (&info
, tdep
);
3773 tdep
->ppc_gp0_regnum
= PPC_R0_REGNUM
;
3774 tdep
->ppc_toc_regnum
= PPC_R0_REGNUM
+ 2;
3775 tdep
->ppc_ps_regnum
= PPC_MSR_REGNUM
;
3776 tdep
->ppc_cr_regnum
= PPC_CR_REGNUM
;
3777 tdep
->ppc_lr_regnum
= PPC_LR_REGNUM
;
3778 tdep
->ppc_ctr_regnum
= PPC_CTR_REGNUM
;
3779 tdep
->ppc_xer_regnum
= PPC_XER_REGNUM
;
3780 tdep
->ppc_mq_regnum
= have_mq
? PPC_MQ_REGNUM
: -1;
3782 tdep
->ppc_fp0_regnum
= have_fpu
? PPC_F0_REGNUM
: -1;
3783 tdep
->ppc_fpscr_regnum
= have_fpu
? PPC_FPSCR_REGNUM
: -1;
3784 tdep
->ppc_vsr0_upper_regnum
= have_vsx
? PPC_VSR0_UPPER_REGNUM
: -1;
3785 tdep
->ppc_vr0_regnum
= have_altivec
? PPC_VR0_REGNUM
: -1;
3786 tdep
->ppc_vrsave_regnum
= have_altivec
? PPC_VRSAVE_REGNUM
: -1;
3787 tdep
->ppc_ev0_upper_regnum
= have_spe
? PPC_SPE_UPPER_GP0_REGNUM
: -1;
3788 tdep
->ppc_acc_regnum
= have_spe
? PPC_SPE_ACC_REGNUM
: -1;
3789 tdep
->ppc_spefscr_regnum
= have_spe
? PPC_SPE_FSCR_REGNUM
: -1;
3791 set_gdbarch_pc_regnum (gdbarch
, PPC_PC_REGNUM
);
3792 set_gdbarch_sp_regnum (gdbarch
, PPC_R0_REGNUM
+ 1);
3793 set_gdbarch_deprecated_fp_regnum (gdbarch
, PPC_R0_REGNUM
+ 1);
3794 set_gdbarch_fp0_regnum (gdbarch
, tdep
->ppc_fp0_regnum
);
3795 set_gdbarch_register_sim_regno (gdbarch
, rs6000_register_sim_regno
);
3797 /* The XML specification for PowerPC sensibly calls the MSR "msr".
3798 GDB traditionally called it "ps", though, so let GDB add an
3800 set_gdbarch_ps_regnum (gdbarch
, tdep
->ppc_ps_regnum
);
3803 set_gdbarch_return_value (gdbarch
, ppc64_sysv_abi_return_value
);
3805 set_gdbarch_return_value (gdbarch
, ppc_sysv_abi_return_value
);
3807 /* Set lr_frame_offset. */
3809 tdep
->lr_frame_offset
= 16;
3811 tdep
->lr_frame_offset
= 4;
3813 if (have_spe
|| have_dfp
|| have_vsx
)
3815 set_gdbarch_pseudo_register_read (gdbarch
, rs6000_pseudo_register_read
);
3816 set_gdbarch_pseudo_register_write (gdbarch
, rs6000_pseudo_register_write
);
3819 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
3821 /* Select instruction printer. */
3822 if (arch
== bfd_arch_rs6000
)
3823 set_gdbarch_print_insn (gdbarch
, print_insn_rs6000
);
3825 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_powerpc
);
3827 set_gdbarch_num_regs (gdbarch
, PPC_NUM_REGS
);
3830 num_pseudoregs
+= 32;
3832 num_pseudoregs
+= 16;
3834 /* Include both VSX and Extended FP registers. */
3835 num_pseudoregs
+= 96;
3837 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudoregs
);
3839 set_gdbarch_ptr_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
3840 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
3841 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
3842 set_gdbarch_long_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
3843 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
3844 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
3845 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
3846 set_gdbarch_long_double_bit (gdbarch
, 16 * TARGET_CHAR_BIT
);
3847 set_gdbarch_char_signed (gdbarch
, 0);
3849 set_gdbarch_frame_align (gdbarch
, rs6000_frame_align
);
3852 set_gdbarch_frame_red_zone_size (gdbarch
, 288);
3854 set_gdbarch_convert_register_p (gdbarch
, rs6000_convert_register_p
);
3855 set_gdbarch_register_to_value (gdbarch
, rs6000_register_to_value
);
3856 set_gdbarch_value_to_register (gdbarch
, rs6000_value_to_register
);
3858 set_gdbarch_stab_reg_to_regnum (gdbarch
, rs6000_stab_reg_to_regnum
);
3859 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, rs6000_dwarf2_reg_to_regnum
);
3862 set_gdbarch_push_dummy_call (gdbarch
, ppc_sysv_abi_push_dummy_call
);
3863 else if (wordsize
== 8)
3864 set_gdbarch_push_dummy_call (gdbarch
, ppc64_sysv_abi_push_dummy_call
);
3866 set_gdbarch_skip_prologue (gdbarch
, rs6000_skip_prologue
);
3867 set_gdbarch_in_function_epilogue_p (gdbarch
, rs6000_in_function_epilogue_p
);
3868 set_gdbarch_skip_main_prologue (gdbarch
, rs6000_skip_main_prologue
);
3870 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3871 set_gdbarch_breakpoint_from_pc (gdbarch
, rs6000_breakpoint_from_pc
);
3873 /* The value of symbols of type N_SO and N_FUN maybe null when
3875 set_gdbarch_sofun_address_maybe_missing (gdbarch
, 1);
3877 /* Handles single stepping of atomic sequences. */
3878 set_gdbarch_software_single_step (gdbarch
, ppc_deal_with_atomic_sequence
);
3880 /* Not sure on this. FIXMEmgo */
3881 set_gdbarch_frame_args_skip (gdbarch
, 8);
3883 /* Helpers for function argument information. */
3884 set_gdbarch_fetch_pointer_argument (gdbarch
, rs6000_fetch_pointer_argument
);
3887 set_gdbarch_in_solib_return_trampoline
3888 (gdbarch
, rs6000_in_solib_return_trampoline
);
3889 set_gdbarch_skip_trampoline_code (gdbarch
, rs6000_skip_trampoline_code
);
3891 /* Hook in the DWARF CFI frame unwinder. */
3892 dwarf2_append_unwinders (gdbarch
);
3893 dwarf2_frame_set_adjust_regnum (gdbarch
, rs6000_adjust_frame_regnum
);
3895 /* Frame handling. */
3896 dwarf2_frame_set_init_reg (gdbarch
, ppc_dwarf2_frame_init_reg
);
3898 /* Setup displaced stepping. */
3899 set_gdbarch_displaced_step_copy_insn (gdbarch
,
3900 simple_displaced_step_copy_insn
);
3901 set_gdbarch_displaced_step_fixup (gdbarch
, ppc_displaced_step_fixup
);
3902 set_gdbarch_displaced_step_free_closure (gdbarch
,
3903 simple_displaced_step_free_closure
);
3904 set_gdbarch_displaced_step_location (gdbarch
,
3905 displaced_step_at_entry_point
);
3907 set_gdbarch_max_insn_length (gdbarch
, PPC_INSN_SIZE
);
3909 /* Hook in ABI-specific overrides, if they have been registered. */
3910 info
.target_desc
= tdesc
;
3911 info
.tdep_info
= (void *) tdesc_data
;
3912 gdbarch_init_osabi (info
, gdbarch
);
3916 case GDB_OSABI_LINUX
:
3917 case GDB_OSABI_NETBSD_AOUT
:
3918 case GDB_OSABI_NETBSD_ELF
:
3919 case GDB_OSABI_UNKNOWN
:
3920 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
3921 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
3922 set_gdbarch_dummy_id (gdbarch
, rs6000_dummy_id
);
3923 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
3926 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
3928 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
3929 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
3930 set_gdbarch_dummy_id (gdbarch
, rs6000_dummy_id
);
3931 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
3934 set_tdesc_pseudo_register_type (gdbarch
, rs6000_pseudo_register_type
);
3935 set_tdesc_pseudo_register_reggroup_p (gdbarch
,
3936 rs6000_pseudo_register_reggroup_p
);
3937 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
3939 /* Override the normal target description method to make the SPE upper
3940 halves anonymous. */
3941 set_gdbarch_register_name (gdbarch
, rs6000_register_name
);
3943 /* Choose register numbers for all supported pseudo-registers. */
3944 tdep
->ppc_ev0_regnum
= -1;
3945 tdep
->ppc_dl0_regnum
= -1;
3946 tdep
->ppc_vsr0_regnum
= -1;
3947 tdep
->ppc_efpr0_regnum
= -1;
3949 cur_reg
= gdbarch_num_regs (gdbarch
);
3953 tdep
->ppc_ev0_regnum
= cur_reg
;
3958 tdep
->ppc_dl0_regnum
= cur_reg
;
3963 tdep
->ppc_vsr0_regnum
= cur_reg
;
3965 tdep
->ppc_efpr0_regnum
= cur_reg
;
3969 gdb_assert (gdbarch_num_regs (gdbarch
)
3970 + gdbarch_num_pseudo_regs (gdbarch
) == cur_reg
);
3976 rs6000_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
3978 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3983 /* FIXME: Dump gdbarch_tdep. */
3986 /* PowerPC-specific commands. */
3989 set_powerpc_command (char *args
, int from_tty
)
3991 printf_unfiltered (_("\
3992 \"set powerpc\" must be followed by an appropriate subcommand.\n"));
3993 help_list (setpowerpccmdlist
, "set powerpc ", all_commands
, gdb_stdout
);
3997 show_powerpc_command (char *args
, int from_tty
)
3999 cmd_show_list (showpowerpccmdlist
, from_tty
, "");
4003 powerpc_set_soft_float (char *args
, int from_tty
,
4004 struct cmd_list_element
*c
)
4006 struct gdbarch_info info
;
4008 /* Update the architecture. */
4009 gdbarch_info_init (&info
);
4010 if (!gdbarch_update_p (info
))
4011 internal_error (__FILE__
, __LINE__
, "could not update architecture");
4015 powerpc_set_vector_abi (char *args
, int from_tty
,
4016 struct cmd_list_element
*c
)
4018 struct gdbarch_info info
;
4019 enum powerpc_vector_abi vector_abi
;
4021 for (vector_abi
= POWERPC_VEC_AUTO
;
4022 vector_abi
!= POWERPC_VEC_LAST
;
4024 if (strcmp (powerpc_vector_abi_string
,
4025 powerpc_vector_strings
[vector_abi
]) == 0)
4027 powerpc_vector_abi_global
= vector_abi
;
4031 if (vector_abi
== POWERPC_VEC_LAST
)
4032 internal_error (__FILE__
, __LINE__
, _("Invalid vector ABI accepted: %s."),
4033 powerpc_vector_abi_string
);
4035 /* Update the architecture. */
4036 gdbarch_info_init (&info
);
4037 if (!gdbarch_update_p (info
))
4038 internal_error (__FILE__
, __LINE__
, "could not update architecture");
4041 /* Initialization code. */
4043 extern initialize_file_ftype _initialize_rs6000_tdep
; /* -Wmissing-prototypes */
4046 _initialize_rs6000_tdep (void)
4048 gdbarch_register (bfd_arch_rs6000
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
4049 gdbarch_register (bfd_arch_powerpc
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
4051 /* Initialize the standard target descriptions. */
4052 initialize_tdesc_powerpc_32 ();
4053 initialize_tdesc_powerpc_altivec32 ();
4054 initialize_tdesc_powerpc_vsx32 ();
4055 initialize_tdesc_powerpc_403 ();
4056 initialize_tdesc_powerpc_403gc ();
4057 initialize_tdesc_powerpc_405 ();
4058 initialize_tdesc_powerpc_505 ();
4059 initialize_tdesc_powerpc_601 ();
4060 initialize_tdesc_powerpc_602 ();
4061 initialize_tdesc_powerpc_603 ();
4062 initialize_tdesc_powerpc_604 ();
4063 initialize_tdesc_powerpc_64 ();
4064 initialize_tdesc_powerpc_altivec64 ();
4065 initialize_tdesc_powerpc_vsx64 ();
4066 initialize_tdesc_powerpc_7400 ();
4067 initialize_tdesc_powerpc_750 ();
4068 initialize_tdesc_powerpc_860 ();
4069 initialize_tdesc_powerpc_e500 ();
4070 initialize_tdesc_rs6000 ();
4072 /* Add root prefix command for all "set powerpc"/"show powerpc"
4074 add_prefix_cmd ("powerpc", no_class
, set_powerpc_command
,
4075 _("Various PowerPC-specific commands."),
4076 &setpowerpccmdlist
, "set powerpc ", 0, &setlist
);
4078 add_prefix_cmd ("powerpc", no_class
, show_powerpc_command
,
4079 _("Various PowerPC-specific commands."),
4080 &showpowerpccmdlist
, "show powerpc ", 0, &showlist
);
4082 /* Add a command to allow the user to force the ABI. */
4083 add_setshow_auto_boolean_cmd ("soft-float", class_support
,
4084 &powerpc_soft_float_global
,
4085 _("Set whether to use a soft-float ABI."),
4086 _("Show whether to use a soft-float ABI."),
4088 powerpc_set_soft_float
, NULL
,
4089 &setpowerpccmdlist
, &showpowerpccmdlist
);
4091 add_setshow_enum_cmd ("vector-abi", class_support
, powerpc_vector_strings
,
4092 &powerpc_vector_abi_string
,
4093 _("Set the vector ABI."),
4094 _("Show the vector ABI."),
4095 NULL
, powerpc_set_vector_abi
, NULL
,
4096 &setpowerpccmdlist
, &showpowerpccmdlist
);