1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 1986-2020 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
29 #include "arch-utils.h"
32 #include "target-float.h"
34 #include "parser-defs.h"
37 #include "sim-regno.h"
38 #include "gdb/sim-ppc.h"
39 #include "reggroups.h"
40 #include "dwarf2/frame.h"
41 #include "target-descriptions.h"
42 #include "user-regs.h"
43 #include "record-full.h"
46 #include "coff/internal.h" /* for libcoff.h */
47 #include "libcoff.h" /* for xcoff_data */
48 #include "coff/xcoff.h"
53 #include "elf/ppc64.h"
55 #include "solib-svr4.h"
57 #include "ppc-ravenscar-thread.h"
61 #include "trad-frame.h"
62 #include "frame-unwind.h"
63 #include "frame-base.h"
69 #include "features/rs6000/powerpc-32.c"
70 #include "features/rs6000/powerpc-altivec32.c"
71 #include "features/rs6000/powerpc-vsx32.c"
72 #include "features/rs6000/powerpc-403.c"
73 #include "features/rs6000/powerpc-403gc.c"
74 #include "features/rs6000/powerpc-405.c"
75 #include "features/rs6000/powerpc-505.c"
76 #include "features/rs6000/powerpc-601.c"
77 #include "features/rs6000/powerpc-602.c"
78 #include "features/rs6000/powerpc-603.c"
79 #include "features/rs6000/powerpc-604.c"
80 #include "features/rs6000/powerpc-64.c"
81 #include "features/rs6000/powerpc-altivec64.c"
82 #include "features/rs6000/powerpc-vsx64.c"
83 #include "features/rs6000/powerpc-7400.c"
84 #include "features/rs6000/powerpc-750.c"
85 #include "features/rs6000/powerpc-860.c"
86 #include "features/rs6000/powerpc-e500.c"
87 #include "features/rs6000/rs6000.c"
89 /* Determine if regnum is an SPE pseudo-register. */
90 #define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \
91 && (regnum) >= (tdep)->ppc_ev0_regnum \
92 && (regnum) < (tdep)->ppc_ev0_regnum + 32)
94 /* Determine if regnum is a decimal float pseudo-register. */
95 #define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \
96 && (regnum) >= (tdep)->ppc_dl0_regnum \
97 && (regnum) < (tdep)->ppc_dl0_regnum + 16)
99 /* Determine if regnum is a "vX" alias for the raw "vrX" vector
101 #define IS_V_ALIAS_PSEUDOREG(tdep, regnum) (\
102 (tdep)->ppc_v0_alias_regnum >= 0 \
103 && (regnum) >= (tdep)->ppc_v0_alias_regnum \
104 && (regnum) < (tdep)->ppc_v0_alias_regnum + ppc_num_vrs)
106 /* Determine if regnum is a POWER7 VSX register. */
107 #define IS_VSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_vsr0_regnum >= 0 \
108 && (regnum) >= (tdep)->ppc_vsr0_regnum \
109 && (regnum) < (tdep)->ppc_vsr0_regnum + ppc_num_vsrs)
111 /* Determine if regnum is a POWER7 Extended FP register. */
112 #define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \
113 && (regnum) >= (tdep)->ppc_efpr0_regnum \
114 && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_efprs)
116 /* Determine if regnum is a checkpointed decimal float
118 #define IS_CDFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_cdl0_regnum >= 0 \
119 && (regnum) >= (tdep)->ppc_cdl0_regnum \
120 && (regnum) < (tdep)->ppc_cdl0_regnum + 16)
122 /* Determine if regnum is a Checkpointed POWER7 VSX register. */
123 #define IS_CVSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_cvsr0_regnum >= 0 \
124 && (regnum) >= (tdep)->ppc_cvsr0_regnum \
125 && (regnum) < (tdep)->ppc_cvsr0_regnum + ppc_num_vsrs)
127 /* Determine if regnum is a Checkpointed POWER7 Extended FP register. */
128 #define IS_CEFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_cefpr0_regnum >= 0 \
129 && (regnum) >= (tdep)->ppc_cefpr0_regnum \
130 && (regnum) < (tdep)->ppc_cefpr0_regnum + ppc_num_efprs)
132 /* Holds the current set of options to be passed to the disassembler. */
133 static char *powerpc_disassembler_options
;
135 /* The list of available "set powerpc ..." and "show powerpc ..."
137 static struct cmd_list_element
*setpowerpccmdlist
= NULL
;
138 static struct cmd_list_element
*showpowerpccmdlist
= NULL
;
140 static enum auto_boolean powerpc_soft_float_global
= AUTO_BOOLEAN_AUTO
;
142 /* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */
143 static const char *const powerpc_vector_strings
[] =
152 /* A variable that can be configured by the user. */
153 static enum powerpc_vector_abi powerpc_vector_abi_global
= POWERPC_VEC_AUTO
;
154 static const char *powerpc_vector_abi_string
= "auto";
156 /* To be used by skip_prologue. */
158 struct rs6000_framedata
160 int offset
; /* total size of frame --- the distance
161 by which we decrement sp to allocate
163 int saved_gpr
; /* smallest # of saved gpr */
164 unsigned int gpr_mask
; /* Each bit is an individual saved GPR. */
165 int saved_fpr
; /* smallest # of saved fpr */
166 int saved_vr
; /* smallest # of saved vr */
167 int saved_ev
; /* smallest # of saved ev */
168 int alloca_reg
; /* alloca register number (frame ptr) */
169 char frameless
; /* true if frameless functions. */
170 char nosavedpc
; /* true if pc not saved. */
171 char used_bl
; /* true if link register clobbered */
172 int gpr_offset
; /* offset of saved gprs from prev sp */
173 int fpr_offset
; /* offset of saved fprs from prev sp */
174 int vr_offset
; /* offset of saved vrs from prev sp */
175 int ev_offset
; /* offset of saved evs from prev sp */
176 int lr_offset
; /* offset of saved lr */
177 int lr_register
; /* register of saved lr, if trustworthy */
178 int cr_offset
; /* offset of saved cr */
179 int vrsave_offset
; /* offset of saved vrsave register */
183 /* Is REGNO a VSX register? Return 1 if so, 0 otherwise. */
185 vsx_register_p (struct gdbarch
*gdbarch
, int regno
)
187 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
188 if (tdep
->ppc_vsr0_regnum
< 0)
191 return (regno
>= tdep
->ppc_vsr0_upper_regnum
&& regno
192 <= tdep
->ppc_vsr0_upper_regnum
+ 31);
195 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
197 altivec_register_p (struct gdbarch
*gdbarch
, int regno
)
199 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
200 if (tdep
->ppc_vr0_regnum
< 0 || tdep
->ppc_vrsave_regnum
< 0)
203 return (regno
>= tdep
->ppc_vr0_regnum
&& regno
<= tdep
->ppc_vrsave_regnum
);
207 /* Return true if REGNO is an SPE register, false otherwise. */
209 spe_register_p (struct gdbarch
*gdbarch
, int regno
)
211 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
213 /* Is it a reference to EV0 -- EV31, and do we have those? */
214 if (IS_SPE_PSEUDOREG (tdep
, regno
))
217 /* Is it a reference to one of the raw upper GPR halves? */
218 if (tdep
->ppc_ev0_upper_regnum
>= 0
219 && tdep
->ppc_ev0_upper_regnum
<= regno
220 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
223 /* Is it a reference to the 64-bit accumulator, and do we have that? */
224 if (tdep
->ppc_acc_regnum
>= 0
225 && tdep
->ppc_acc_regnum
== regno
)
228 /* Is it a reference to the SPE floating-point status and control register,
229 and do we have that? */
230 if (tdep
->ppc_spefscr_regnum
>= 0
231 && tdep
->ppc_spefscr_regnum
== regno
)
238 /* Return non-zero if the architecture described by GDBARCH has
239 floating-point registers (f0 --- f31 and fpscr). */
241 ppc_floating_point_unit_p (struct gdbarch
*gdbarch
)
243 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
245 return (tdep
->ppc_fp0_regnum
>= 0
246 && tdep
->ppc_fpscr_regnum
>= 0);
249 /* Return non-zero if the architecture described by GDBARCH has
250 Altivec registers (vr0 --- vr31, vrsave and vscr). */
252 ppc_altivec_support_p (struct gdbarch
*gdbarch
)
254 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
256 return (tdep
->ppc_vr0_regnum
>= 0
257 && tdep
->ppc_vrsave_regnum
>= 0);
260 /* Check that TABLE[GDB_REGNO] is not already initialized, and then
263 This is a helper function for init_sim_regno_table, constructing
264 the table mapping GDB register numbers to sim register numbers; we
265 initialize every element in that table to -1 before we start
268 set_sim_regno (int *table
, int gdb_regno
, int sim_regno
)
270 /* Make sure we don't try to assign any given GDB register a sim
271 register number more than once. */
272 gdb_assert (table
[gdb_regno
] == -1);
273 table
[gdb_regno
] = sim_regno
;
277 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
278 numbers to simulator register numbers, based on the values placed
279 in the ARCH->tdep->ppc_foo_regnum members. */
281 init_sim_regno_table (struct gdbarch
*arch
)
283 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
284 int total_regs
= gdbarch_num_regs (arch
);
285 int *sim_regno
= GDBARCH_OBSTACK_CALLOC (arch
, total_regs
, int);
287 static const char *const segment_regs
[] = {
288 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
289 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
292 /* Presume that all registers not explicitly mentioned below are
293 unavailable from the sim. */
294 for (i
= 0; i
< total_regs
; i
++)
297 /* General-purpose registers. */
298 for (i
= 0; i
< ppc_num_gprs
; i
++)
299 set_sim_regno (sim_regno
, tdep
->ppc_gp0_regnum
+ i
, sim_ppc_r0_regnum
+ i
);
301 /* Floating-point registers. */
302 if (tdep
->ppc_fp0_regnum
>= 0)
303 for (i
= 0; i
< ppc_num_fprs
; i
++)
304 set_sim_regno (sim_regno
,
305 tdep
->ppc_fp0_regnum
+ i
,
306 sim_ppc_f0_regnum
+ i
);
307 if (tdep
->ppc_fpscr_regnum
>= 0)
308 set_sim_regno (sim_regno
, tdep
->ppc_fpscr_regnum
, sim_ppc_fpscr_regnum
);
310 set_sim_regno (sim_regno
, gdbarch_pc_regnum (arch
), sim_ppc_pc_regnum
);
311 set_sim_regno (sim_regno
, tdep
->ppc_ps_regnum
, sim_ppc_ps_regnum
);
312 set_sim_regno (sim_regno
, tdep
->ppc_cr_regnum
, sim_ppc_cr_regnum
);
314 /* Segment registers. */
315 for (i
= 0; i
< ppc_num_srs
; i
++)
319 gdb_regno
= user_reg_map_name_to_regnum (arch
, segment_regs
[i
], -1);
321 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_sr0_regnum
+ i
);
324 /* Altivec registers. */
325 if (tdep
->ppc_vr0_regnum
>= 0)
327 for (i
= 0; i
< ppc_num_vrs
; i
++)
328 set_sim_regno (sim_regno
,
329 tdep
->ppc_vr0_regnum
+ i
,
330 sim_ppc_vr0_regnum
+ i
);
332 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
333 we can treat this more like the other cases. */
334 set_sim_regno (sim_regno
,
335 tdep
->ppc_vr0_regnum
+ ppc_num_vrs
,
336 sim_ppc_vscr_regnum
);
338 /* vsave is a special-purpose register, so the code below handles it. */
340 /* SPE APU (E500) registers. */
341 if (tdep
->ppc_ev0_upper_regnum
>= 0)
342 for (i
= 0; i
< ppc_num_gprs
; i
++)
343 set_sim_regno (sim_regno
,
344 tdep
->ppc_ev0_upper_regnum
+ i
,
345 sim_ppc_rh0_regnum
+ i
);
346 if (tdep
->ppc_acc_regnum
>= 0)
347 set_sim_regno (sim_regno
, tdep
->ppc_acc_regnum
, sim_ppc_acc_regnum
);
348 /* spefscr is a special-purpose register, so the code below handles it. */
351 /* Now handle all special-purpose registers. Verify that they
352 haven't mistakenly been assigned numbers by any of the above
354 for (i
= 0; i
< sim_ppc_num_sprs
; i
++)
356 const char *spr_name
= sim_spr_register_name (i
);
359 if (spr_name
!= NULL
)
360 gdb_regno
= user_reg_map_name_to_regnum (arch
, spr_name
, -1);
363 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_spr0_regnum
+ i
);
367 /* Drop the initialized array into place. */
368 tdep
->sim_regno
= sim_regno
;
372 /* Given a GDB register number REG, return the corresponding SIM
375 rs6000_register_sim_regno (struct gdbarch
*gdbarch
, int reg
)
377 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
380 if (tdep
->sim_regno
== NULL
)
381 init_sim_regno_table (gdbarch
);
383 gdb_assert (0 <= reg
&& reg
<= gdbarch_num_cooked_regs (gdbarch
));
384 sim_regno
= tdep
->sim_regno
[reg
];
389 return LEGACY_SIM_REGNO_IGNORE
;
394 /* Register set support functions. */
396 /* REGS + OFFSET contains register REGNUM in a field REGSIZE wide.
397 Write the register to REGCACHE. */
400 ppc_supply_reg (struct regcache
*regcache
, int regnum
,
401 const gdb_byte
*regs
, size_t offset
, int regsize
)
403 if (regnum
!= -1 && offset
!= -1)
407 struct gdbarch
*gdbarch
= regcache
->arch ();
408 int gdb_regsize
= register_size (gdbarch
, regnum
);
409 if (gdb_regsize
< regsize
410 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
411 offset
+= regsize
- gdb_regsize
;
413 regcache
->raw_supply (regnum
, regs
+ offset
);
417 /* Read register REGNUM from REGCACHE and store to REGS + OFFSET
418 in a field REGSIZE wide. Zero pad as necessary. */
421 ppc_collect_reg (const struct regcache
*regcache
, int regnum
,
422 gdb_byte
*regs
, size_t offset
, int regsize
)
424 if (regnum
!= -1 && offset
!= -1)
428 struct gdbarch
*gdbarch
= regcache
->arch ();
429 int gdb_regsize
= register_size (gdbarch
, regnum
);
430 if (gdb_regsize
< regsize
)
432 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
434 memset (regs
+ offset
, 0, regsize
- gdb_regsize
);
435 offset
+= regsize
- gdb_regsize
;
438 memset (regs
+ offset
+ regsize
- gdb_regsize
, 0,
439 regsize
- gdb_regsize
);
442 regcache
->raw_collect (regnum
, regs
+ offset
);
447 ppc_greg_offset (struct gdbarch
*gdbarch
,
448 struct gdbarch_tdep
*tdep
,
449 const struct ppc_reg_offsets
*offsets
,
453 *regsize
= offsets
->gpr_size
;
454 if (regnum
>= tdep
->ppc_gp0_regnum
455 && regnum
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
)
456 return (offsets
->r0_offset
457 + (regnum
- tdep
->ppc_gp0_regnum
) * offsets
->gpr_size
);
459 if (regnum
== gdbarch_pc_regnum (gdbarch
))
460 return offsets
->pc_offset
;
462 if (regnum
== tdep
->ppc_ps_regnum
)
463 return offsets
->ps_offset
;
465 if (regnum
== tdep
->ppc_lr_regnum
)
466 return offsets
->lr_offset
;
468 if (regnum
== tdep
->ppc_ctr_regnum
)
469 return offsets
->ctr_offset
;
471 *regsize
= offsets
->xr_size
;
472 if (regnum
== tdep
->ppc_cr_regnum
)
473 return offsets
->cr_offset
;
475 if (regnum
== tdep
->ppc_xer_regnum
)
476 return offsets
->xer_offset
;
478 if (regnum
== tdep
->ppc_mq_regnum
)
479 return offsets
->mq_offset
;
485 ppc_fpreg_offset (struct gdbarch_tdep
*tdep
,
486 const struct ppc_reg_offsets
*offsets
,
489 if (regnum
>= tdep
->ppc_fp0_regnum
490 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
)
491 return offsets
->f0_offset
+ (regnum
- tdep
->ppc_fp0_regnum
) * 8;
493 if (regnum
== tdep
->ppc_fpscr_regnum
)
494 return offsets
->fpscr_offset
;
499 /* Supply register REGNUM in the general-purpose register set REGSET
500 from the buffer specified by GREGS and LEN to register cache
501 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
504 ppc_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
505 int regnum
, const void *gregs
, size_t len
)
507 struct gdbarch
*gdbarch
= regcache
->arch ();
508 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
509 const struct ppc_reg_offsets
*offsets
510 = (const struct ppc_reg_offsets
*) regset
->regmap
;
517 int gpr_size
= offsets
->gpr_size
;
519 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
520 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
521 i
++, offset
+= gpr_size
)
522 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) gregs
, offset
,
525 ppc_supply_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
526 (const gdb_byte
*) gregs
, offsets
->pc_offset
, gpr_size
);
527 ppc_supply_reg (regcache
, tdep
->ppc_ps_regnum
,
528 (const gdb_byte
*) gregs
, offsets
->ps_offset
, gpr_size
);
529 ppc_supply_reg (regcache
, tdep
->ppc_lr_regnum
,
530 (const gdb_byte
*) gregs
, offsets
->lr_offset
, gpr_size
);
531 ppc_supply_reg (regcache
, tdep
->ppc_ctr_regnum
,
532 (const gdb_byte
*) gregs
, offsets
->ctr_offset
, gpr_size
);
533 ppc_supply_reg (regcache
, tdep
->ppc_cr_regnum
,
534 (const gdb_byte
*) gregs
, offsets
->cr_offset
,
536 ppc_supply_reg (regcache
, tdep
->ppc_xer_regnum
,
537 (const gdb_byte
*) gregs
, offsets
->xer_offset
,
539 ppc_supply_reg (regcache
, tdep
->ppc_mq_regnum
,
540 (const gdb_byte
*) gregs
, offsets
->mq_offset
,
545 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
546 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) gregs
, offset
, regsize
);
549 /* Supply register REGNUM in the floating-point register set REGSET
550 from the buffer specified by FPREGS and LEN to register cache
551 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
554 ppc_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
555 int regnum
, const void *fpregs
, size_t len
)
557 struct gdbarch
*gdbarch
= regcache
->arch ();
558 struct gdbarch_tdep
*tdep
;
559 const struct ppc_reg_offsets
*offsets
;
562 if (!ppc_floating_point_unit_p (gdbarch
))
565 tdep
= gdbarch_tdep (gdbarch
);
566 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
571 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
572 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
574 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) fpregs
, offset
, 8);
576 ppc_supply_reg (regcache
, tdep
->ppc_fpscr_regnum
,
577 (const gdb_byte
*) fpregs
, offsets
->fpscr_offset
,
578 offsets
->fpscr_size
);
582 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
583 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) fpregs
, offset
,
584 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
587 /* Collect register REGNUM in the general-purpose register set
588 REGSET from register cache REGCACHE into the buffer specified by
589 GREGS and LEN. If REGNUM is -1, do this for all registers in
593 ppc_collect_gregset (const struct regset
*regset
,
594 const struct regcache
*regcache
,
595 int regnum
, void *gregs
, size_t len
)
597 struct gdbarch
*gdbarch
= regcache
->arch ();
598 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
599 const struct ppc_reg_offsets
*offsets
600 = (const struct ppc_reg_offsets
*) regset
->regmap
;
607 int gpr_size
= offsets
->gpr_size
;
609 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
610 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
611 i
++, offset
+= gpr_size
)
612 ppc_collect_reg (regcache
, i
, (gdb_byte
*) gregs
, offset
, gpr_size
);
614 ppc_collect_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
615 (gdb_byte
*) gregs
, offsets
->pc_offset
, gpr_size
);
616 ppc_collect_reg (regcache
, tdep
->ppc_ps_regnum
,
617 (gdb_byte
*) gregs
, offsets
->ps_offset
, gpr_size
);
618 ppc_collect_reg (regcache
, tdep
->ppc_lr_regnum
,
619 (gdb_byte
*) gregs
, offsets
->lr_offset
, gpr_size
);
620 ppc_collect_reg (regcache
, tdep
->ppc_ctr_regnum
,
621 (gdb_byte
*) gregs
, offsets
->ctr_offset
, gpr_size
);
622 ppc_collect_reg (regcache
, tdep
->ppc_cr_regnum
,
623 (gdb_byte
*) gregs
, offsets
->cr_offset
,
625 ppc_collect_reg (regcache
, tdep
->ppc_xer_regnum
,
626 (gdb_byte
*) gregs
, offsets
->xer_offset
,
628 ppc_collect_reg (regcache
, tdep
->ppc_mq_regnum
,
629 (gdb_byte
*) gregs
, offsets
->mq_offset
,
634 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
635 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) gregs
, offset
, regsize
);
638 /* Collect register REGNUM in the floating-point register set
639 REGSET from register cache REGCACHE into the buffer specified by
640 FPREGS and LEN. If REGNUM is -1, do this for all registers in
644 ppc_collect_fpregset (const struct regset
*regset
,
645 const struct regcache
*regcache
,
646 int regnum
, void *fpregs
, size_t len
)
648 struct gdbarch
*gdbarch
= regcache
->arch ();
649 struct gdbarch_tdep
*tdep
;
650 const struct ppc_reg_offsets
*offsets
;
653 if (!ppc_floating_point_unit_p (gdbarch
))
656 tdep
= gdbarch_tdep (gdbarch
);
657 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
662 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
663 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
665 ppc_collect_reg (regcache
, i
, (gdb_byte
*) fpregs
, offset
, 8);
667 ppc_collect_reg (regcache
, tdep
->ppc_fpscr_regnum
,
668 (gdb_byte
*) fpregs
, offsets
->fpscr_offset
,
669 offsets
->fpscr_size
);
673 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
674 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) fpregs
, offset
,
675 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
679 insn_changes_sp_or_jumps (unsigned long insn
)
681 int opcode
= (insn
>> 26) & 0x03f;
682 int sd
= (insn
>> 21) & 0x01f;
683 int a
= (insn
>> 16) & 0x01f;
684 int subcode
= (insn
>> 1) & 0x3ff;
686 /* Changes the stack pointer. */
688 /* NOTE: There are many ways to change the value of a given register.
689 The ways below are those used when the register is R1, the SP,
690 in a funtion's epilogue. */
692 if (opcode
== 31 && subcode
== 444 && a
== 1)
693 return 1; /* mr R1,Rn */
694 if (opcode
== 14 && sd
== 1)
695 return 1; /* addi R1,Rn,simm */
696 if (opcode
== 58 && sd
== 1)
697 return 1; /* ld R1,ds(Rn) */
699 /* Transfers control. */
705 if (opcode
== 19 && subcode
== 16)
707 if (opcode
== 19 && subcode
== 528)
708 return 1; /* bcctr */
713 /* Return true if we are in the function's epilogue, i.e. after the
714 instruction that destroyed the function's stack frame.
716 1) scan forward from the point of execution:
717 a) If you find an instruction that modifies the stack pointer
718 or transfers control (except a return), execution is not in
720 b) Stop scanning if you find a return instruction or reach the
721 end of the function or reach the hard limit for the size of
723 2) scan backward from the point of execution:
724 a) If you find an instruction that modifies the stack pointer,
725 execution *is* in an epilogue, return.
726 b) Stop scanning if you reach an instruction that transfers
727 control or the beginning of the function or reach the hard
728 limit for the size of an epilogue. */
731 rs6000_in_function_epilogue_frame_p (struct frame_info
*curfrm
,
732 struct gdbarch
*gdbarch
, CORE_ADDR pc
)
734 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
735 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
736 bfd_byte insn_buf
[PPC_INSN_SIZE
];
737 CORE_ADDR scan_pc
, func_start
, func_end
, epilogue_start
, epilogue_end
;
740 /* Find the search limits based on function boundaries and hard limit. */
742 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
745 epilogue_start
= pc
- PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
746 if (epilogue_start
< func_start
) epilogue_start
= func_start
;
748 epilogue_end
= pc
+ PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
749 if (epilogue_end
> func_end
) epilogue_end
= func_end
;
751 /* Scan forward until next 'blr'. */
753 for (scan_pc
= pc
; scan_pc
< epilogue_end
; scan_pc
+= PPC_INSN_SIZE
)
755 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
757 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
758 if (insn
== 0x4e800020)
760 /* Assume a bctr is a tail call unless it points strictly within
762 if (insn
== 0x4e800420)
764 CORE_ADDR ctr
= get_frame_register_unsigned (curfrm
,
765 tdep
->ppc_ctr_regnum
);
766 if (ctr
> func_start
&& ctr
< func_end
)
771 if (insn_changes_sp_or_jumps (insn
))
775 /* Scan backward until adjustment to stack pointer (R1). */
777 for (scan_pc
= pc
- PPC_INSN_SIZE
;
778 scan_pc
>= epilogue_start
;
779 scan_pc
-= PPC_INSN_SIZE
)
781 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
783 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
784 if (insn_changes_sp_or_jumps (insn
))
791 /* Implement the stack_frame_destroyed_p gdbarch method. */
794 rs6000_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
796 return rs6000_in_function_epilogue_frame_p (get_current_frame (),
800 /* Get the ith function argument for the current function. */
802 rs6000_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
805 return get_frame_register_unsigned (frame
, 3 + argi
);
808 /* Sequence of bytes for breakpoint instruction. */
810 constexpr gdb_byte big_breakpoint
[] = { 0x7d, 0x82, 0x10, 0x08 };
811 constexpr gdb_byte little_breakpoint
[] = { 0x08, 0x10, 0x82, 0x7d };
813 typedef BP_MANIPULATION_ENDIAN (little_breakpoint
, big_breakpoint
)
816 /* Instruction masks for displaced stepping. */
817 #define BRANCH_MASK 0xfc000000
818 #define BP_MASK 0xFC0007FE
819 #define B_INSN 0x48000000
820 #define BC_INSN 0x40000000
821 #define BXL_INSN 0x4c000000
822 #define BP_INSN 0x7C000008
824 /* Instruction masks used during single-stepping of atomic
826 #define LOAD_AND_RESERVE_MASK 0xfc0007fe
827 #define LWARX_INSTRUCTION 0x7c000028
828 #define LDARX_INSTRUCTION 0x7c0000A8
829 #define LBARX_INSTRUCTION 0x7c000068
830 #define LHARX_INSTRUCTION 0x7c0000e8
831 #define LQARX_INSTRUCTION 0x7c000228
832 #define STORE_CONDITIONAL_MASK 0xfc0007ff
833 #define STWCX_INSTRUCTION 0x7c00012d
834 #define STDCX_INSTRUCTION 0x7c0001ad
835 #define STBCX_INSTRUCTION 0x7c00056d
836 #define STHCX_INSTRUCTION 0x7c0005ad
837 #define STQCX_INSTRUCTION 0x7c00016d
839 /* Check if insn is one of the Load And Reserve instructions used for atomic
841 #define IS_LOAD_AND_RESERVE_INSN(insn) ((insn & LOAD_AND_RESERVE_MASK) == LWARX_INSTRUCTION \
842 || (insn & LOAD_AND_RESERVE_MASK) == LDARX_INSTRUCTION \
843 || (insn & LOAD_AND_RESERVE_MASK) == LBARX_INSTRUCTION \
844 || (insn & LOAD_AND_RESERVE_MASK) == LHARX_INSTRUCTION \
845 || (insn & LOAD_AND_RESERVE_MASK) == LQARX_INSTRUCTION)
846 /* Check if insn is one of the Store Conditional instructions used for atomic
848 #define IS_STORE_CONDITIONAL_INSN(insn) ((insn & STORE_CONDITIONAL_MASK) == STWCX_INSTRUCTION \
849 || (insn & STORE_CONDITIONAL_MASK) == STDCX_INSTRUCTION \
850 || (insn & STORE_CONDITIONAL_MASK) == STBCX_INSTRUCTION \
851 || (insn & STORE_CONDITIONAL_MASK) == STHCX_INSTRUCTION \
852 || (insn & STORE_CONDITIONAL_MASK) == STQCX_INSTRUCTION)
854 typedef buf_displaced_step_closure ppc_displaced_step_closure
;
856 /* We can't displaced step atomic sequences. */
858 static displaced_step_closure_up
859 ppc_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
860 CORE_ADDR from
, CORE_ADDR to
,
861 struct regcache
*regs
)
863 size_t len
= gdbarch_max_insn_length (gdbarch
);
864 std::unique_ptr
<ppc_displaced_step_closure
> closure
865 (new ppc_displaced_step_closure (len
));
866 gdb_byte
*buf
= closure
->buf
.data ();
867 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
870 read_memory (from
, buf
, len
);
872 insn
= extract_signed_integer (buf
, PPC_INSN_SIZE
, byte_order
);
874 /* Assume all atomic sequences start with a Load and Reserve instruction. */
875 if (IS_LOAD_AND_RESERVE_INSN (insn
))
877 displaced_debug_printf ("can't displaced step atomic sequence at %s",
878 paddress (gdbarch
, from
));
883 write_memory (to
, buf
, len
);
885 displaced_debug_printf ("copy %s->%s: %s",
886 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
887 displaced_step_dump_bytes (buf
, len
).c_str ());;
889 /* This is a work around for a problem with g++ 4.8. */
890 return displaced_step_closure_up (closure
.release ());
893 /* Fix up the state of registers and memory after having single-stepped
894 a displaced instruction. */
896 ppc_displaced_step_fixup (struct gdbarch
*gdbarch
,
897 struct displaced_step_closure
*closure_
,
898 CORE_ADDR from
, CORE_ADDR to
,
899 struct regcache
*regs
)
901 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
902 /* Our closure is a copy of the instruction. */
903 ppc_displaced_step_closure
*closure
= (ppc_displaced_step_closure
*) closure_
;
904 ULONGEST insn
= extract_unsigned_integer (closure
->buf
.data (),
905 PPC_INSN_SIZE
, byte_order
);
907 /* Offset for non PC-relative instructions. */
908 LONGEST offset
= PPC_INSN_SIZE
;
910 opcode
= insn
& BRANCH_MASK
;
912 displaced_debug_printf ("(ppc) fixup (%s, %s)",
913 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
915 /* Handle PC-relative branch instructions. */
916 if (opcode
== B_INSN
|| opcode
== BC_INSN
|| opcode
== BXL_INSN
)
920 /* Read the current PC value after the instruction has been executed
921 in a displaced location. Calculate the offset to be applied to the
922 original PC value before the displaced stepping. */
923 regcache_cooked_read_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
925 offset
= current_pc
- to
;
927 if (opcode
!= BXL_INSN
)
929 /* Check for AA bit indicating whether this is an absolute
930 addressing or PC-relative (1: absolute, 0: relative). */
933 /* PC-relative addressing is being used in the branch. */
934 displaced_debug_printf ("(ppc) branch instruction: %s",
935 paddress (gdbarch
, insn
));
936 displaced_debug_printf ("(ppc) adjusted PC from %s to %s",
937 paddress (gdbarch
, current_pc
),
938 paddress (gdbarch
, from
+ offset
));
940 regcache_cooked_write_unsigned (regs
,
941 gdbarch_pc_regnum (gdbarch
),
947 /* If we're here, it means we have a branch to LR or CTR. If the
948 branch was taken, the offset is probably greater than 4 (the next
949 instruction), so it's safe to assume that an offset of 4 means we
950 did not take the branch. */
951 if (offset
== PPC_INSN_SIZE
)
952 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
953 from
+ PPC_INSN_SIZE
);
956 /* Check for LK bit indicating whether we should set the link
957 register to point to the next instruction
958 (1: Set, 0: Don't set). */
961 /* Link register needs to be set to the next instruction's PC. */
962 regcache_cooked_write_unsigned (regs
,
963 gdbarch_tdep (gdbarch
)->ppc_lr_regnum
,
964 from
+ PPC_INSN_SIZE
);
965 displaced_debug_printf ("(ppc) adjusted LR to %s",
966 paddress (gdbarch
, from
+ PPC_INSN_SIZE
));
970 /* Check for breakpoints in the inferior. If we've found one, place the PC
971 right at the breakpoint instruction. */
972 else if ((insn
& BP_MASK
) == BP_INSN
)
973 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
), from
);
975 /* Handle any other instructions that do not fit in the categories above. */
976 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
980 /* Always use hardware single-stepping to execute the
981 displaced instruction. */
983 ppc_displaced_step_hw_singlestep (struct gdbarch
*gdbarch
)
988 /* Checks for an atomic sequence of instructions beginning with a
989 Load And Reserve instruction and ending with a Store Conditional
990 instruction. If such a sequence is found, attempt to step through it.
991 A breakpoint is placed at the end of the sequence. */
992 std::vector
<CORE_ADDR
>
993 ppc_deal_with_atomic_sequence (struct regcache
*regcache
)
995 struct gdbarch
*gdbarch
= regcache
->arch ();
996 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
997 CORE_ADDR pc
= regcache_read_pc (regcache
);
998 CORE_ADDR breaks
[2] = {CORE_ADDR_MAX
, CORE_ADDR_MAX
};
1000 CORE_ADDR closing_insn
; /* Instruction that closes the atomic sequence. */
1001 int insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1004 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
1005 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
1006 int bc_insn_count
= 0; /* Conditional branch instruction count. */
1008 /* Assume all atomic sequences start with a Load And Reserve instruction. */
1009 if (!IS_LOAD_AND_RESERVE_INSN (insn
))
1012 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
1014 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
1016 loc
+= PPC_INSN_SIZE
;
1017 insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1019 /* Assume that there is at most one conditional branch in the atomic
1020 sequence. If a conditional branch is found, put a breakpoint in
1021 its destination address. */
1022 if ((insn
& BRANCH_MASK
) == BC_INSN
)
1024 int immediate
= ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
1025 int absolute
= insn
& 2;
1027 if (bc_insn_count
>= 1)
1028 return {}; /* More than one conditional branch found, fallback
1029 to the standard single-step code. */
1032 breaks
[1] = immediate
;
1034 breaks
[1] = loc
+ immediate
;
1040 if (IS_STORE_CONDITIONAL_INSN (insn
))
1044 /* Assume that the atomic sequence ends with a Store Conditional
1046 if (!IS_STORE_CONDITIONAL_INSN (insn
))
1050 loc
+= PPC_INSN_SIZE
;
1052 /* Insert a breakpoint right after the end of the atomic sequence. */
1055 /* Check for duplicated breakpoints. Check also for a breakpoint
1056 placed (branch instruction's destination) anywhere in sequence. */
1058 && (breaks
[1] == breaks
[0]
1059 || (breaks
[1] >= pc
&& breaks
[1] <= closing_insn
)))
1060 last_breakpoint
= 0;
1062 std::vector
<CORE_ADDR
> next_pcs
;
1064 for (index
= 0; index
<= last_breakpoint
; index
++)
1065 next_pcs
.push_back (breaks
[index
]);
1071 #define SIGNED_SHORT(x) \
1072 ((sizeof (short) == 2) \
1073 ? ((int)(short)(x)) \
1074 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
1076 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
1078 /* Limit the number of skipped non-prologue instructions, as the examining
1079 of the prologue is expensive. */
1080 static int max_skip_non_prologue_insns
= 10;
1082 /* Return nonzero if the given instruction OP can be part of the prologue
1083 of a function and saves a parameter on the stack. FRAMEP should be
1084 set if one of the previous instructions in the function has set the
1088 store_param_on_stack_p (unsigned long op
, int framep
, int *r0_contains_arg
)
1090 /* Move parameters from argument registers to temporary register. */
1091 if ((op
& 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
1093 /* Rx must be scratch register r0. */
1094 const int rx_regno
= (op
>> 16) & 31;
1095 /* Ry: Only r3 - r10 are used for parameter passing. */
1096 const int ry_regno
= GET_SRC_REG (op
);
1098 if (rx_regno
== 0 && ry_regno
>= 3 && ry_regno
<= 10)
1100 *r0_contains_arg
= 1;
1107 /* Save a General Purpose Register on stack. */
1109 if ((op
& 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
1110 (op
& 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
1112 /* Rx: Only r3 - r10 are used for parameter passing. */
1113 const int rx_regno
= GET_SRC_REG (op
);
1115 return (rx_regno
>= 3 && rx_regno
<= 10);
1118 /* Save a General Purpose Register on stack via the Frame Pointer. */
1121 ((op
& 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
1122 (op
& 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
1123 (op
& 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
1125 /* Rx: Usually, only r3 - r10 are used for parameter passing.
1126 However, the compiler sometimes uses r0 to hold an argument. */
1127 const int rx_regno
= GET_SRC_REG (op
);
1129 return ((rx_regno
>= 3 && rx_regno
<= 10)
1130 || (rx_regno
== 0 && *r0_contains_arg
));
1133 if ((op
& 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
1135 /* Only f2 - f8 are used for parameter passing. */
1136 const int src_regno
= GET_SRC_REG (op
);
1138 return (src_regno
>= 2 && src_regno
<= 8);
1141 if (framep
&& ((op
& 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
1143 /* Only f2 - f8 are used for parameter passing. */
1144 const int src_regno
= GET_SRC_REG (op
);
1146 return (src_regno
>= 2 && src_regno
<= 8);
1149 /* Not an insn that saves a parameter on stack. */
1153 /* Assuming that INSN is a "bl" instruction located at PC, return
1154 nonzero if the destination of the branch is a "blrl" instruction.
1156 This sequence is sometimes found in certain function prologues.
1157 It allows the function to load the LR register with a value that
1158 they can use to access PIC data using PC-relative offsets. */
1161 bl_to_blrl_insn_p (CORE_ADDR pc
, int insn
, enum bfd_endian byte_order
)
1168 absolute
= (int) ((insn
>> 1) & 1);
1169 immediate
= ((insn
& ~3) << 6) >> 6;
1173 dest
= pc
+ immediate
;
1175 dest_insn
= read_memory_integer (dest
, 4, byte_order
);
1176 if ((dest_insn
& 0xfc00ffff) == 0x4c000021) /* blrl */
1182 /* Return true if OP is a stw or std instruction with
1183 register operands RS and RA and any immediate offset.
1185 If WITH_UPDATE is true, also return true if OP is
1186 a stwu or stdu instruction with the same operands.
1188 Return false otherwise.
1191 store_insn_p (unsigned long op
, unsigned long rs
,
1192 unsigned long ra
, bool with_update
)
1197 if (/* std RS, SIMM(RA) */
1198 ((op
& 0xffff0003) == (rs
| ra
| 0xf8000000)) ||
1199 /* stw RS, SIMM(RA) */
1200 ((op
& 0xffff0000) == (rs
| ra
| 0x90000000)))
1205 if (/* stdu RS, SIMM(RA) */
1206 ((op
& 0xffff0003) == (rs
| ra
| 0xf8000001)) ||
1207 /* stwu RS, SIMM(RA) */
1208 ((op
& 0xffff0000) == (rs
| ra
| 0x94000000)))
1215 /* Masks for decoding a branch-and-link (bl) instruction.
1217 BL_MASK and BL_INSTRUCTION are used in combination with each other.
1218 The former is anded with the opcode in question; if the result of
1219 this masking operation is equal to BL_INSTRUCTION, then the opcode in
1220 question is a ``bl'' instruction.
1222 BL_DISPLACEMENT_MASK is anded with the opcode in order to extract
1223 the branch displacement. */
1225 #define BL_MASK 0xfc000001
1226 #define BL_INSTRUCTION 0x48000001
1227 #define BL_DISPLACEMENT_MASK 0x03fffffc
1229 static unsigned long
1230 rs6000_fetch_instruction (struct gdbarch
*gdbarch
, const CORE_ADDR pc
)
1232 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1236 /* Fetch the instruction and convert it to an integer. */
1237 if (target_read_memory (pc
, buf
, 4))
1239 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1244 /* GCC generates several well-known sequences of instructions at the begining
1245 of each function prologue when compiling with -fstack-check. If one of
1246 such sequences starts at START_PC, then return the address of the
1247 instruction immediately past this sequence. Otherwise, return START_PC. */
1250 rs6000_skip_stack_check (struct gdbarch
*gdbarch
, const CORE_ADDR start_pc
)
1252 CORE_ADDR pc
= start_pc
;
1253 unsigned long op
= rs6000_fetch_instruction (gdbarch
, pc
);
1255 /* First possible sequence: A small number of probes.
1256 stw 0, -<some immediate>(1)
1257 [repeat this instruction any (small) number of times]. */
1259 if ((op
& 0xffff0000) == 0x90010000)
1261 while ((op
& 0xffff0000) == 0x90010000)
1264 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1269 /* Second sequence: A probing loop.
1270 addi 12,1,-<some immediate>
1271 lis 0,-<some immediate>
1272 [possibly ori 0,0,<some immediate>]
1276 addi 12,12,-<some immediate>
1279 [possibly one last probe: stw 0,<some immediate>(12)]. */
1283 /* addi 12,1,-<some immediate> */
1284 if ((op
& 0xffff0000) != 0x39810000)
1287 /* lis 0,-<some immediate> */
1289 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1290 if ((op
& 0xffff0000) != 0x3c000000)
1294 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1295 /* [possibly ori 0,0,<some immediate>] */
1296 if ((op
& 0xffff0000) == 0x60000000)
1299 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1302 if (op
!= 0x7c0c0214)
1307 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1308 if (op
!= 0x7c0c0000)
1313 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1314 if ((op
& 0xff9f0001) != 0x41820000)
1317 /* addi 12,12,-<some immediate> */
1319 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1320 if ((op
& 0xffff0000) != 0x398c0000)
1325 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1326 if (op
!= 0x900c0000)
1331 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1332 if ((op
& 0xfc000001) != 0x48000000)
1335 /* [possibly one last probe: stw 0,<some immediate>(12)]. */
1337 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1338 if ((op
& 0xffff0000) == 0x900c0000)
1341 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1344 /* We found a valid stack-check sequence, return the new PC. */
1348 /* Third sequence: No probe; instead, a comparison between the stack size
1349 limit (saved in a run-time global variable) and the current stack
1352 addi 0,1,-<some immediate>
1353 lis 12,__gnat_stack_limit@ha
1354 lwz 12,__gnat_stack_limit@l(12)
1357 or, with a small variant in the case of a bigger stack frame:
1358 addis 0,1,<some immediate>
1359 addic 0,0,-<some immediate>
1360 lis 12,__gnat_stack_limit@ha
1361 lwz 12,__gnat_stack_limit@l(12)
1366 /* addi 0,1,-<some immediate> */
1367 if ((op
& 0xffff0000) != 0x38010000)
1369 /* small stack frame variant not recognized; try the
1370 big stack frame variant: */
1372 /* addis 0,1,<some immediate> */
1373 if ((op
& 0xffff0000) != 0x3c010000)
1376 /* addic 0,0,-<some immediate> */
1378 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1379 if ((op
& 0xffff0000) != 0x30000000)
1383 /* lis 12,<some immediate> */
1385 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1386 if ((op
& 0xffff0000) != 0x3d800000)
1389 /* lwz 12,<some immediate>(12) */
1391 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1392 if ((op
& 0xffff0000) != 0x818c0000)
1397 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1398 if ((op
& 0xfffffffe) != 0x7c406008)
1401 /* We found a valid stack-check sequence, return the new PC. */
1405 /* No stack check code in our prologue, return the start_pc. */
1409 /* return pc value after skipping a function prologue and also return
1410 information about a function frame.
1412 in struct rs6000_framedata fdata:
1413 - frameless is TRUE, if function does not have a frame.
1414 - nosavedpc is TRUE, if function does not save %pc value in its frame.
1415 - offset is the initial size of this stack frame --- the amount by
1416 which we decrement the sp to allocate the frame.
1417 - saved_gpr is the number of the first saved gpr.
1418 - saved_fpr is the number of the first saved fpr.
1419 - saved_vr is the number of the first saved vr.
1420 - saved_ev is the number of the first saved ev.
1421 - alloca_reg is the number of the register used for alloca() handling.
1423 - gpr_offset is the offset of the first saved gpr from the previous frame.
1424 - fpr_offset is the offset of the first saved fpr from the previous frame.
1425 - vr_offset is the offset of the first saved vr from the previous frame.
1426 - ev_offset is the offset of the first saved ev from the previous frame.
1427 - lr_offset is the offset of the saved lr
1428 - cr_offset is the offset of the saved cr
1429 - vrsave_offset is the offset of the saved vrsave register. */
1432 skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
, CORE_ADDR lim_pc
,
1433 struct rs6000_framedata
*fdata
)
1435 CORE_ADDR orig_pc
= pc
;
1436 CORE_ADDR last_prologue_pc
= pc
;
1437 CORE_ADDR li_found_pc
= 0;
1441 long alloca_reg_offset
= 0;
1442 long vr_saved_offset
= 0;
1448 int vrsave_reg
= -1;
1451 int minimal_toc_loaded
= 0;
1452 int prev_insn_was_prologue_insn
= 1;
1453 int num_skip_non_prologue_insns
= 0;
1454 int r0_contains_arg
= 0;
1455 const struct bfd_arch_info
*arch_info
= gdbarch_bfd_arch_info (gdbarch
);
1456 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1457 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1459 memset (fdata
, 0, sizeof (struct rs6000_framedata
));
1460 fdata
->saved_gpr
= -1;
1461 fdata
->saved_fpr
= -1;
1462 fdata
->saved_vr
= -1;
1463 fdata
->saved_ev
= -1;
1464 fdata
->alloca_reg
= -1;
1465 fdata
->frameless
= 1;
1466 fdata
->nosavedpc
= 1;
1467 fdata
->lr_register
= -1;
1469 pc
= rs6000_skip_stack_check (gdbarch
, pc
);
1475 /* Sometimes it isn't clear if an instruction is a prologue
1476 instruction or not. When we encounter one of these ambiguous
1477 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
1478 Otherwise, we'll assume that it really is a prologue instruction. */
1479 if (prev_insn_was_prologue_insn
)
1480 last_prologue_pc
= pc
;
1482 /* Stop scanning if we've hit the limit. */
1486 prev_insn_was_prologue_insn
= 1;
1488 /* Fetch the instruction and convert it to an integer. */
1489 if (target_read_memory (pc
, buf
, 4))
1491 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1493 if ((op
& 0xfc1fffff) == 0x7c0802a6)
1495 /* Since shared library / PIC code, which needs to get its
1496 address at runtime, can appear to save more than one link
1510 remember just the first one, but skip over additional
1513 lr_reg
= (op
& 0x03e00000) >> 21;
1515 r0_contains_arg
= 0;
1518 else if ((op
& 0xfc1fffff) == 0x7c000026)
1520 cr_reg
= (op
& 0x03e00000) >> 21;
1522 r0_contains_arg
= 0;
1526 else if ((op
& 0xfc1f0000) == 0xd8010000)
1527 { /* stfd Rx,NUM(r1) */
1528 reg
= GET_SRC_REG (op
);
1529 if (fdata
->saved_fpr
== -1 || fdata
->saved_fpr
> reg
)
1531 fdata
->saved_fpr
= reg
;
1532 fdata
->fpr_offset
= SIGNED_SHORT (op
) + offset
;
1537 else if (((op
& 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
1538 (((op
& 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1539 (op
& 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1540 (op
& 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
1543 reg
= GET_SRC_REG (op
);
1544 if ((op
& 0xfc1f0000) == 0xbc010000)
1545 fdata
->gpr_mask
|= ~((1U << reg
) - 1);
1547 fdata
->gpr_mask
|= 1U << reg
;
1548 if (fdata
->saved_gpr
== -1 || fdata
->saved_gpr
> reg
)
1550 fdata
->saved_gpr
= reg
;
1551 if ((op
& 0xfc1f0003) == 0xf8010000)
1553 fdata
->gpr_offset
= SIGNED_SHORT (op
) + offset
;
1558 else if ((op
& 0xffff0000) == 0x3c4c0000
1559 || (op
& 0xffff0000) == 0x3c400000
1560 || (op
& 0xffff0000) == 0x38420000)
1562 /* . 0: addis 2,12,.TOC.-0b@ha
1563 . addi 2,2,.TOC.-0b@l
1567 used by ELFv2 global entry points to set up r2. */
1570 else if (op
== 0x60000000)
1573 /* Allow nops in the prologue, but do not consider them to
1574 be part of the prologue unless followed by other prologue
1576 prev_insn_was_prologue_insn
= 0;
1580 else if ((op
& 0xffff0000) == 0x3c000000)
1581 { /* addis 0,0,NUM, used for >= 32k frames */
1582 fdata
->offset
= (op
& 0x0000ffff) << 16;
1583 fdata
->frameless
= 0;
1584 r0_contains_arg
= 0;
1588 else if ((op
& 0xffff0000) == 0x60000000)
1589 { /* ori 0,0,NUM, 2nd half of >= 32k frames */
1590 fdata
->offset
|= (op
& 0x0000ffff);
1591 fdata
->frameless
= 0;
1592 r0_contains_arg
= 0;
1596 else if (lr_reg
>= 0 &&
1597 ((store_insn_p (op
, lr_reg
, 1, true)) ||
1599 (store_insn_p (op
, lr_reg
,
1600 fdata
->alloca_reg
- tdep
->ppc_gp0_regnum
,
1603 if (store_insn_p (op
, lr_reg
, 1, true))
1604 fdata
->lr_offset
= offset
;
1605 else /* LR save through frame pointer. */
1606 fdata
->lr_offset
= alloca_reg_offset
;
1608 fdata
->nosavedpc
= 0;
1609 /* Invalidate lr_reg, but don't set it to -1.
1610 That would mean that it had never been set. */
1612 if ((op
& 0xfc000003) == 0xf8000000 || /* std */
1613 (op
& 0xfc000000) == 0x90000000) /* stw */
1615 /* Does not update r1, so add displacement to lr_offset. */
1616 fdata
->lr_offset
+= SIGNED_SHORT (op
);
1621 else if (cr_reg
>= 0 &&
1622 (store_insn_p (op
, cr_reg
, 1, true)))
1624 fdata
->cr_offset
= offset
;
1625 /* Invalidate cr_reg, but don't set it to -1.
1626 That would mean that it had never been set. */
1628 if ((op
& 0xfc000003) == 0xf8000000 ||
1629 (op
& 0xfc000000) == 0x90000000)
1631 /* Does not update r1, so add displacement to cr_offset. */
1632 fdata
->cr_offset
+= SIGNED_SHORT (op
);
1637 else if ((op
& 0xfe80ffff) == 0x42800005 && lr_reg
!= -1)
1639 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1640 prediction bits. If the LR has already been saved, we can
1644 else if (op
== 0x48000005)
1651 else if (op
== 0x48000004)
1656 else if ((op
& 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1657 in V.4 -mminimal-toc */
1658 (op
& 0xffff0000) == 0x3bde0000)
1659 { /* addi 30,30,foo@l */
1663 else if ((op
& 0xfc000001) == 0x48000001)
1667 fdata
->frameless
= 0;
1669 /* If the return address has already been saved, we can skip
1670 calls to blrl (for PIC). */
1671 if (lr_reg
!= -1 && bl_to_blrl_insn_p (pc
, op
, byte_order
))
1677 /* Don't skip over the subroutine call if it is not within
1678 the first three instructions of the prologue and either
1679 we have no line table information or the line info tells
1680 us that the subroutine call is not part of the line
1681 associated with the prologue. */
1682 if ((pc
- orig_pc
) > 8)
1684 struct symtab_and_line prologue_sal
= find_pc_line (orig_pc
, 0);
1685 struct symtab_and_line this_sal
= find_pc_line (pc
, 0);
1687 if ((prologue_sal
.line
== 0)
1688 || (prologue_sal
.line
!= this_sal
.line
))
1692 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
1694 /* At this point, make sure this is not a trampoline
1695 function (a function that simply calls another functions,
1696 and nothing else). If the next is not a nop, this branch
1697 was part of the function prologue. */
1699 if (op
== 0x4def7b82 || op
== 0) /* crorc 15, 15, 15 */
1700 break; /* Don't skip over
1706 /* update stack pointer */
1707 else if ((op
& 0xfc1f0000) == 0x94010000)
1708 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
1709 fdata
->frameless
= 0;
1710 fdata
->offset
= SIGNED_SHORT (op
);
1711 offset
= fdata
->offset
;
1714 else if ((op
& 0xfc1f07fa) == 0x7c01016a)
1715 { /* stwux rX,r1,rY || stdux rX,r1,rY */
1716 /* No way to figure out what r1 is going to be. */
1717 fdata
->frameless
= 0;
1718 offset
= fdata
->offset
;
1721 else if ((op
& 0xfc1f0003) == 0xf8010001)
1722 { /* stdu rX,NUM(r1) */
1723 fdata
->frameless
= 0;
1724 fdata
->offset
= SIGNED_SHORT (op
& ~3UL);
1725 offset
= fdata
->offset
;
1728 else if ((op
& 0xffff0000) == 0x38210000)
1729 { /* addi r1,r1,SIMM */
1730 fdata
->frameless
= 0;
1731 fdata
->offset
+= SIGNED_SHORT (op
);
1732 offset
= fdata
->offset
;
1735 /* Load up minimal toc pointer. Do not treat an epilogue restore
1736 of r31 as a minimal TOC load. */
1737 else if (((op
>> 22) == 0x20f || /* l r31,... or l r30,... */
1738 (op
>> 22) == 0x3af) /* ld r31,... or ld r30,... */
1740 && !minimal_toc_loaded
)
1742 minimal_toc_loaded
= 1;
1745 /* move parameters from argument registers to local variable
1748 else if ((op
& 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1749 (((op
>> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1750 (((op
>> 21) & 31) <= 10) &&
1751 ((long) ((op
>> 16) & 31)
1752 >= fdata
->saved_gpr
)) /* Rx: local var reg */
1756 /* store parameters in stack */
1758 /* Move parameters from argument registers to temporary register. */
1759 else if (store_param_on_stack_p (op
, framep
, &r0_contains_arg
))
1763 /* Set up frame pointer */
1765 else if (op
== 0x603d0000) /* oril r29, r1, 0x0 */
1767 fdata
->frameless
= 0;
1769 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 29);
1770 alloca_reg_offset
= offset
;
1773 /* Another way to set up the frame pointer. */
1775 else if (op
== 0x603f0000 /* oril r31, r1, 0x0 */
1776 || op
== 0x7c3f0b78)
1778 fdata
->frameless
= 0;
1780 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 31);
1781 alloca_reg_offset
= offset
;
1784 /* Another way to set up the frame pointer. */
1786 else if ((op
& 0xfc1fffff) == 0x38010000)
1787 { /* addi rX, r1, 0x0 */
1788 fdata
->frameless
= 0;
1790 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
1791 + ((op
& ~0x38010000) >> 21));
1792 alloca_reg_offset
= offset
;
1795 /* AltiVec related instructions. */
1796 /* Store the vrsave register (spr 256) in another register for
1797 later manipulation, or load a register into the vrsave
1798 register. 2 instructions are used: mfvrsave and
1799 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1800 and mtspr SPR256, Rn. */
1801 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1802 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1803 else if ((op
& 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1805 vrsave_reg
= GET_SRC_REG (op
);
1808 else if ((op
& 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1812 /* Store the register where vrsave was saved to onto the stack:
1813 rS is the register where vrsave was stored in a previous
1815 /* 100100 sssss 00001 dddddddd dddddddd */
1816 else if ((op
& 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1818 if (vrsave_reg
== GET_SRC_REG (op
))
1820 fdata
->vrsave_offset
= SIGNED_SHORT (op
) + offset
;
1825 /* Compute the new value of vrsave, by modifying the register
1826 where vrsave was saved to. */
1827 else if (((op
& 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1828 || ((op
& 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1832 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1833 in a pair of insns to save the vector registers on the
1835 /* 001110 00000 00000 iiii iiii iiii iiii */
1836 /* 001110 01110 00000 iiii iiii iiii iiii */
1837 else if ((op
& 0xffff0000) == 0x38000000 /* li r0, SIMM */
1838 || (op
& 0xffff0000) == 0x39c00000) /* li r14, SIMM */
1840 if ((op
& 0xffff0000) == 0x38000000)
1841 r0_contains_arg
= 0;
1843 vr_saved_offset
= SIGNED_SHORT (op
);
1845 /* This insn by itself is not part of the prologue, unless
1846 if part of the pair of insns mentioned above. So do not
1847 record this insn as part of the prologue yet. */
1848 prev_insn_was_prologue_insn
= 0;
1850 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1851 /* 011111 sssss 11111 00000 00111001110 */
1852 else if ((op
& 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1854 if (pc
== (li_found_pc
+ 4))
1856 vr_reg
= GET_SRC_REG (op
);
1857 /* If this is the first vector reg to be saved, or if
1858 it has a lower number than others previously seen,
1859 reupdate the frame info. */
1860 if (fdata
->saved_vr
== -1 || fdata
->saved_vr
> vr_reg
)
1862 fdata
->saved_vr
= vr_reg
;
1863 fdata
->vr_offset
= vr_saved_offset
+ offset
;
1865 vr_saved_offset
= -1;
1870 /* End AltiVec related instructions. */
1872 /* Start BookE related instructions. */
1873 /* Store gen register S at (r31+uimm).
1874 Any register less than r13 is volatile, so we don't care. */
1875 /* 000100 sssss 11111 iiiii 01100100001 */
1876 else if (arch_info
->mach
== bfd_mach_ppc_e500
1877 && (op
& 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
1879 if ((op
& 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
1882 ev_reg
= GET_SRC_REG (op
);
1883 imm
= (op
>> 11) & 0x1f;
1884 ev_offset
= imm
* 8;
1885 /* If this is the first vector reg to be saved, or if
1886 it has a lower number than others previously seen,
1887 reupdate the frame info. */
1888 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1890 fdata
->saved_ev
= ev_reg
;
1891 fdata
->ev_offset
= ev_offset
+ offset
;
1896 /* Store gen register rS at (r1+rB). */
1897 /* 000100 sssss 00001 bbbbb 01100100000 */
1898 else if (arch_info
->mach
== bfd_mach_ppc_e500
1899 && (op
& 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1901 if (pc
== (li_found_pc
+ 4))
1903 ev_reg
= GET_SRC_REG (op
);
1904 /* If this is the first vector reg to be saved, or if
1905 it has a lower number than others previously seen,
1906 reupdate the frame info. */
1907 /* We know the contents of rB from the previous instruction. */
1908 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1910 fdata
->saved_ev
= ev_reg
;
1911 fdata
->ev_offset
= vr_saved_offset
+ offset
;
1913 vr_saved_offset
= -1;
1919 /* Store gen register r31 at (rA+uimm). */
1920 /* 000100 11111 aaaaa iiiii 01100100001 */
1921 else if (arch_info
->mach
== bfd_mach_ppc_e500
1922 && (op
& 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
1924 /* Wwe know that the source register is 31 already, but
1925 it can't hurt to compute it. */
1926 ev_reg
= GET_SRC_REG (op
);
1927 ev_offset
= ((op
>> 11) & 0x1f) * 8;
1928 /* If this is the first vector reg to be saved, or if
1929 it has a lower number than others previously seen,
1930 reupdate the frame info. */
1931 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1933 fdata
->saved_ev
= ev_reg
;
1934 fdata
->ev_offset
= ev_offset
+ offset
;
1939 /* Store gen register S at (r31+r0).
1940 Store param on stack when offset from SP bigger than 4 bytes. */
1941 /* 000100 sssss 11111 00000 01100100000 */
1942 else if (arch_info
->mach
== bfd_mach_ppc_e500
1943 && (op
& 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
1945 if (pc
== (li_found_pc
+ 4))
1947 if ((op
& 0x03e00000) >= 0x01a00000)
1949 ev_reg
= GET_SRC_REG (op
);
1950 /* If this is the first vector reg to be saved, or if
1951 it has a lower number than others previously seen,
1952 reupdate the frame info. */
1953 /* We know the contents of r0 from the previous
1955 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1957 fdata
->saved_ev
= ev_reg
;
1958 fdata
->ev_offset
= vr_saved_offset
+ offset
;
1962 vr_saved_offset
= -1;
1967 /* End BookE related instructions. */
1971 /* Not a recognized prologue instruction.
1972 Handle optimizer code motions into the prologue by continuing
1973 the search if we have no valid frame yet or if the return
1974 address is not yet saved in the frame. Also skip instructions
1975 if some of the GPRs expected to be saved are not yet saved. */
1976 if (fdata
->frameless
== 0 && fdata
->nosavedpc
== 0
1977 && fdata
->saved_gpr
!= -1)
1979 unsigned int all_mask
= ~((1U << fdata
->saved_gpr
) - 1);
1981 if ((fdata
->gpr_mask
& all_mask
) == all_mask
)
1985 if (op
== 0x4e800020 /* blr */
1986 || op
== 0x4e800420) /* bctr */
1987 /* Do not scan past epilogue in frameless functions or
1990 if ((op
& 0xf4000000) == 0x40000000) /* bxx */
1991 /* Never skip branches. */
1994 if (num_skip_non_prologue_insns
++ > max_skip_non_prologue_insns
)
1995 /* Do not scan too many insns, scanning insns is expensive with
1999 /* Continue scanning. */
2000 prev_insn_was_prologue_insn
= 0;
2006 /* I have problems with skipping over __main() that I need to address
2007 * sometime. Previously, I used to use misc_function_vector which
2008 * didn't work as well as I wanted to be. -MGO */
2010 /* If the first thing after skipping a prolog is a branch to a function,
2011 this might be a call to an initializer in main(), introduced by gcc2.
2012 We'd like to skip over it as well. Fortunately, xlc does some extra
2013 work before calling a function right after a prologue, thus we can
2014 single out such gcc2 behaviour. */
2017 if ((op
& 0xfc000001) == 0x48000001)
2018 { /* bl foo, an initializer function? */
2019 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
2021 if (op
== 0x4def7b82)
2022 { /* cror 0xf, 0xf, 0xf (nop) */
2024 /* Check and see if we are in main. If so, skip over this
2025 initializer function as well. */
2027 tmp
= find_pc_misc_function (pc
);
2029 && strcmp (misc_function_vector
[tmp
].name
, main_name ()) == 0)
2035 if (pc
== lim_pc
&& lr_reg
>= 0)
2036 fdata
->lr_register
= lr_reg
;
2038 fdata
->offset
= -fdata
->offset
;
2039 return last_prologue_pc
;
2043 rs6000_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2045 struct rs6000_framedata frame
;
2046 CORE_ADDR limit_pc
, func_addr
, func_end_addr
= 0;
2048 /* See if we can determine the end of the prologue via the symbol table.
2049 If so, then return either PC, or the PC after the prologue, whichever
2051 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end_addr
))
2053 CORE_ADDR post_prologue_pc
2054 = skip_prologue_using_sal (gdbarch
, func_addr
);
2055 if (post_prologue_pc
!= 0)
2056 return std::max (pc
, post_prologue_pc
);
2059 /* Can't determine prologue from the symbol table, need to examine
2062 /* Find an upper limit on the function prologue using the debug
2063 information. If the debug information could not be used to provide
2064 that bound, then use an arbitrary large number as the upper bound. */
2065 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
2067 limit_pc
= pc
+ 100; /* Magic. */
2069 /* Do not allow limit_pc to be past the function end, if we know
2070 where that end is... */
2071 if (func_end_addr
&& limit_pc
> func_end_addr
)
2072 limit_pc
= func_end_addr
;
2074 pc
= skip_prologue (gdbarch
, pc
, limit_pc
, &frame
);
2078 /* When compiling for EABI, some versions of GCC emit a call to __eabi
2079 in the prologue of main().
2081 The function below examines the code pointed at by PC and checks to
2082 see if it corresponds to a call to __eabi. If so, it returns the
2083 address of the instruction following that call. Otherwise, it simply
2087 rs6000_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2089 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2093 if (target_read_memory (pc
, buf
, 4))
2095 op
= extract_unsigned_integer (buf
, 4, byte_order
);
2097 if ((op
& BL_MASK
) == BL_INSTRUCTION
)
2099 CORE_ADDR displ
= op
& BL_DISPLACEMENT_MASK
;
2100 CORE_ADDR call_dest
= pc
+ 4 + displ
;
2101 struct bound_minimal_symbol s
= lookup_minimal_symbol_by_pc (call_dest
);
2103 /* We check for ___eabi (three leading underscores) in addition
2104 to __eabi in case the GCC option "-fleading-underscore" was
2105 used to compile the program. */
2106 if (s
.minsym
!= NULL
2107 && s
.minsym
->linkage_name () != NULL
2108 && (strcmp (s
.minsym
->linkage_name (), "__eabi") == 0
2109 || strcmp (s
.minsym
->linkage_name (), "___eabi") == 0))
2115 /* All the ABI's require 16 byte alignment. */
2117 rs6000_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2119 return (addr
& -16);
2122 /* Return whether handle_inferior_event() should proceed through code
2123 starting at PC in function NAME when stepping.
2125 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
2126 handle memory references that are too distant to fit in instructions
2127 generated by the compiler. For example, if 'foo' in the following
2132 is greater than 32767, the linker might replace the lwz with a branch to
2133 somewhere in @FIX1 that does the load in 2 instructions and then branches
2134 back to where execution should continue.
2136 GDB should silently step over @FIX code, just like AIX dbx does.
2137 Unfortunately, the linker uses the "b" instruction for the
2138 branches, meaning that the link register doesn't get set.
2139 Therefore, GDB's usual step_over_function () mechanism won't work.
2141 Instead, use the gdbarch_skip_trampoline_code and
2142 gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past
2146 rs6000_in_solib_return_trampoline (struct gdbarch
*gdbarch
,
2147 CORE_ADDR pc
, const char *name
)
2149 return name
&& startswith (name
, "@FIX");
2152 /* Skip code that the user doesn't want to see when stepping:
2154 1. Indirect function calls use a piece of trampoline code to do context
2155 switching, i.e. to set the new TOC table. Skip such code if we are on
2156 its first instruction (as when we have single-stepped to here).
2158 2. Skip shared library trampoline code (which is different from
2159 indirect function call trampolines).
2161 3. Skip bigtoc fixup code.
2163 Result is desired PC to step until, or NULL if we are not in
2164 code that should be skipped. */
2167 rs6000_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
2169 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2170 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2171 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2172 unsigned int ii
, op
;
2174 CORE_ADDR solib_target_pc
;
2175 struct bound_minimal_symbol msymbol
;
2177 static unsigned trampoline_code
[] =
2179 0x800b0000, /* l r0,0x0(r11) */
2180 0x90410014, /* st r2,0x14(r1) */
2181 0x7c0903a6, /* mtctr r0 */
2182 0x804b0004, /* l r2,0x4(r11) */
2183 0x816b0008, /* l r11,0x8(r11) */
2184 0x4e800420, /* bctr */
2185 0x4e800020, /* br */
2189 /* Check for bigtoc fixup code. */
2190 msymbol
= lookup_minimal_symbol_by_pc (pc
);
2192 && rs6000_in_solib_return_trampoline (gdbarch
, pc
,
2193 msymbol
.minsym
->linkage_name ()))
2195 /* Double-check that the third instruction from PC is relative "b". */
2196 op
= read_memory_integer (pc
+ 8, 4, byte_order
);
2197 if ((op
& 0xfc000003) == 0x48000000)
2199 /* Extract bits 6-29 as a signed 24-bit relative word address and
2200 add it to the containing PC. */
2201 rel
= ((int)(op
<< 6) >> 6);
2202 return pc
+ 8 + rel
;
2206 /* If pc is in a shared library trampoline, return its target. */
2207 solib_target_pc
= find_solib_trampoline_target (frame
, pc
);
2208 if (solib_target_pc
)
2209 return solib_target_pc
;
2211 for (ii
= 0; trampoline_code
[ii
]; ++ii
)
2213 op
= read_memory_integer (pc
+ (ii
* 4), 4, byte_order
);
2214 if (op
!= trampoline_code
[ii
])
2217 ii
= get_frame_register_unsigned (frame
, 11); /* r11 holds destination
2219 pc
= read_memory_unsigned_integer (ii
, tdep
->wordsize
, byte_order
);
2223 /* ISA-specific vector types. */
2225 static struct type
*
2226 rs6000_builtin_type_vec64 (struct gdbarch
*gdbarch
)
2228 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2230 if (!tdep
->ppc_builtin_type_vec64
)
2232 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2234 /* The type we're building is this: */
2236 union __gdb_builtin_type_vec64
2240 int32_t v2_int32
[2];
2241 int16_t v4_int16
[4];
2248 t
= arch_composite_type (gdbarch
,
2249 "__ppc_builtin_type_vec64", TYPE_CODE_UNION
);
2250 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2251 append_composite_type_field (t
, "v2_float",
2252 init_vector_type (bt
->builtin_float
, 2));
2253 append_composite_type_field (t
, "v2_int32",
2254 init_vector_type (bt
->builtin_int32
, 2));
2255 append_composite_type_field (t
, "v4_int16",
2256 init_vector_type (bt
->builtin_int16
, 4));
2257 append_composite_type_field (t
, "v8_int8",
2258 init_vector_type (bt
->builtin_int8
, 8));
2260 t
->set_is_vector (true);
2261 t
->set_name ("ppc_builtin_type_vec64");
2262 tdep
->ppc_builtin_type_vec64
= t
;
2265 return tdep
->ppc_builtin_type_vec64
;
2268 /* Vector 128 type. */
2270 static struct type
*
2271 rs6000_builtin_type_vec128 (struct gdbarch
*gdbarch
)
2273 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2275 if (!tdep
->ppc_builtin_type_vec128
)
2277 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2279 /* The type we're building is this
2281 type = union __ppc_builtin_type_vec128 {
2283 double v2_double[2];
2285 int32_t v4_int32[4];
2286 int16_t v8_int16[8];
2287 int8_t v16_int8[16];
2293 t
= arch_composite_type (gdbarch
,
2294 "__ppc_builtin_type_vec128", TYPE_CODE_UNION
);
2295 append_composite_type_field (t
, "uint128", bt
->builtin_uint128
);
2296 append_composite_type_field (t
, "v2_double",
2297 init_vector_type (bt
->builtin_double
, 2));
2298 append_composite_type_field (t
, "v4_float",
2299 init_vector_type (bt
->builtin_float
, 4));
2300 append_composite_type_field (t
, "v4_int32",
2301 init_vector_type (bt
->builtin_int32
, 4));
2302 append_composite_type_field (t
, "v8_int16",
2303 init_vector_type (bt
->builtin_int16
, 8));
2304 append_composite_type_field (t
, "v16_int8",
2305 init_vector_type (bt
->builtin_int8
, 16));
2307 t
->set_is_vector (true);
2308 t
->set_name ("ppc_builtin_type_vec128");
2309 tdep
->ppc_builtin_type_vec128
= t
;
2312 return tdep
->ppc_builtin_type_vec128
;
2315 /* Return the name of register number REGNO, or the empty string if it
2316 is an anonymous register. */
2319 rs6000_register_name (struct gdbarch
*gdbarch
, int regno
)
2321 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2323 /* The upper half "registers" have names in the XML description,
2324 but we present only the low GPRs and the full 64-bit registers
2326 if (tdep
->ppc_ev0_upper_regnum
>= 0
2327 && tdep
->ppc_ev0_upper_regnum
<= regno
2328 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
2331 /* Hide the upper halves of the vs0~vs31 registers. */
2332 if (tdep
->ppc_vsr0_regnum
>= 0
2333 && tdep
->ppc_vsr0_upper_regnum
<= regno
2334 && regno
< tdep
->ppc_vsr0_upper_regnum
+ ppc_num_gprs
)
2337 /* Hide the upper halves of the cvs0~cvs31 registers. */
2338 if (PPC_CVSR0_UPPER_REGNUM
<= regno
2339 && regno
< PPC_CVSR0_UPPER_REGNUM
+ ppc_num_gprs
)
2342 /* Check if the SPE pseudo registers are available. */
2343 if (IS_SPE_PSEUDOREG (tdep
, regno
))
2345 static const char *const spe_regnames
[] = {
2346 "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7",
2347 "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15",
2348 "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23",
2349 "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31",
2351 return spe_regnames
[regno
- tdep
->ppc_ev0_regnum
];
2354 /* Check if the decimal128 pseudo-registers are available. */
2355 if (IS_DFP_PSEUDOREG (tdep
, regno
))
2357 static const char *const dfp128_regnames
[] = {
2358 "dl0", "dl1", "dl2", "dl3",
2359 "dl4", "dl5", "dl6", "dl7",
2360 "dl8", "dl9", "dl10", "dl11",
2361 "dl12", "dl13", "dl14", "dl15"
2363 return dfp128_regnames
[regno
- tdep
->ppc_dl0_regnum
];
2366 /* Check if this is a vX alias for a raw vrX vector register. */
2367 if (IS_V_ALIAS_PSEUDOREG (tdep
, regno
))
2369 static const char *const vector_alias_regnames
[] = {
2370 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
2371 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
2372 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
2373 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
2375 return vector_alias_regnames
[regno
- tdep
->ppc_v0_alias_regnum
];
2378 /* Check if this is a VSX pseudo-register. */
2379 if (IS_VSX_PSEUDOREG (tdep
, regno
))
2381 static const char *const vsx_regnames
[] = {
2382 "vs0", "vs1", "vs2", "vs3", "vs4", "vs5", "vs6", "vs7",
2383 "vs8", "vs9", "vs10", "vs11", "vs12", "vs13", "vs14",
2384 "vs15", "vs16", "vs17", "vs18", "vs19", "vs20", "vs21",
2385 "vs22", "vs23", "vs24", "vs25", "vs26", "vs27", "vs28",
2386 "vs29", "vs30", "vs31", "vs32", "vs33", "vs34", "vs35",
2387 "vs36", "vs37", "vs38", "vs39", "vs40", "vs41", "vs42",
2388 "vs43", "vs44", "vs45", "vs46", "vs47", "vs48", "vs49",
2389 "vs50", "vs51", "vs52", "vs53", "vs54", "vs55", "vs56",
2390 "vs57", "vs58", "vs59", "vs60", "vs61", "vs62", "vs63"
2392 return vsx_regnames
[regno
- tdep
->ppc_vsr0_regnum
];
2395 /* Check if the this is a Extended FP pseudo-register. */
2396 if (IS_EFP_PSEUDOREG (tdep
, regno
))
2398 static const char *const efpr_regnames
[] = {
2399 "f32", "f33", "f34", "f35", "f36", "f37", "f38",
2400 "f39", "f40", "f41", "f42", "f43", "f44", "f45",
2401 "f46", "f47", "f48", "f49", "f50", "f51",
2402 "f52", "f53", "f54", "f55", "f56", "f57",
2403 "f58", "f59", "f60", "f61", "f62", "f63"
2405 return efpr_regnames
[regno
- tdep
->ppc_efpr0_regnum
];
2408 /* Check if this is a Checkpointed DFP pseudo-register. */
2409 if (IS_CDFP_PSEUDOREG (tdep
, regno
))
2411 static const char *const cdfp128_regnames
[] = {
2412 "cdl0", "cdl1", "cdl2", "cdl3",
2413 "cdl4", "cdl5", "cdl6", "cdl7",
2414 "cdl8", "cdl9", "cdl10", "cdl11",
2415 "cdl12", "cdl13", "cdl14", "cdl15"
2417 return cdfp128_regnames
[regno
- tdep
->ppc_cdl0_regnum
];
2420 /* Check if this is a Checkpointed VSX pseudo-register. */
2421 if (IS_CVSX_PSEUDOREG (tdep
, regno
))
2423 static const char *const cvsx_regnames
[] = {
2424 "cvs0", "cvs1", "cvs2", "cvs3", "cvs4", "cvs5", "cvs6", "cvs7",
2425 "cvs8", "cvs9", "cvs10", "cvs11", "cvs12", "cvs13", "cvs14",
2426 "cvs15", "cvs16", "cvs17", "cvs18", "cvs19", "cvs20", "cvs21",
2427 "cvs22", "cvs23", "cvs24", "cvs25", "cvs26", "cvs27", "cvs28",
2428 "cvs29", "cvs30", "cvs31", "cvs32", "cvs33", "cvs34", "cvs35",
2429 "cvs36", "cvs37", "cvs38", "cvs39", "cvs40", "cvs41", "cvs42",
2430 "cvs43", "cvs44", "cvs45", "cvs46", "cvs47", "cvs48", "cvs49",
2431 "cvs50", "cvs51", "cvs52", "cvs53", "cvs54", "cvs55", "cvs56",
2432 "cvs57", "cvs58", "cvs59", "cvs60", "cvs61", "cvs62", "cvs63"
2434 return cvsx_regnames
[regno
- tdep
->ppc_cvsr0_regnum
];
2437 /* Check if the this is a Checkpointed Extended FP pseudo-register. */
2438 if (IS_CEFP_PSEUDOREG (tdep
, regno
))
2440 static const char *const cefpr_regnames
[] = {
2441 "cf32", "cf33", "cf34", "cf35", "cf36", "cf37", "cf38",
2442 "cf39", "cf40", "cf41", "cf42", "cf43", "cf44", "cf45",
2443 "cf46", "cf47", "cf48", "cf49", "cf50", "cf51",
2444 "cf52", "cf53", "cf54", "cf55", "cf56", "cf57",
2445 "cf58", "cf59", "cf60", "cf61", "cf62", "cf63"
2447 return cefpr_regnames
[regno
- tdep
->ppc_cefpr0_regnum
];
2450 return tdesc_register_name (gdbarch
, regno
);
2453 /* Return the GDB type object for the "standard" data type of data in
2456 static struct type
*
2457 rs6000_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2459 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2461 /* These are the e500 pseudo-registers. */
2462 if (IS_SPE_PSEUDOREG (tdep
, regnum
))
2463 return rs6000_builtin_type_vec64 (gdbarch
);
2464 else if (IS_DFP_PSEUDOREG (tdep
, regnum
)
2465 || IS_CDFP_PSEUDOREG (tdep
, regnum
))
2466 /* PPC decimal128 pseudo-registers. */
2467 return builtin_type (gdbarch
)->builtin_declong
;
2468 else if (IS_V_ALIAS_PSEUDOREG (tdep
, regnum
))
2469 return gdbarch_register_type (gdbarch
,
2470 tdep
->ppc_vr0_regnum
2472 - tdep
->ppc_v0_alias_regnum
));
2473 else if (IS_VSX_PSEUDOREG (tdep
, regnum
)
2474 || IS_CVSX_PSEUDOREG (tdep
, regnum
))
2475 /* POWER7 VSX pseudo-registers. */
2476 return rs6000_builtin_type_vec128 (gdbarch
);
2477 else if (IS_EFP_PSEUDOREG (tdep
, regnum
)
2478 || IS_CEFP_PSEUDOREG (tdep
, regnum
))
2479 /* POWER7 Extended FP pseudo-registers. */
2480 return builtin_type (gdbarch
)->builtin_double
;
2482 internal_error (__FILE__
, __LINE__
,
2483 _("rs6000_pseudo_register_type: "
2484 "called on unexpected register '%s' (%d)"),
2485 gdbarch_register_name (gdbarch
, regnum
), regnum
);
2488 /* Check if REGNUM is a member of REGGROUP. We only need to handle
2489 the vX aliases for the vector registers by always returning false
2490 to avoid duplicated information in "info register vector/all",
2491 since the raw vrX registers will already show in these cases. For
2492 other pseudo-registers we use the default membership function. */
2495 rs6000_pseudo_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2496 struct reggroup
*group
)
2498 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2500 if (IS_V_ALIAS_PSEUDOREG (tdep
, regnum
))
2503 return default_register_reggroup_p (gdbarch
, regnum
, group
);
2506 /* The register format for RS/6000 floating point registers is always
2507 double, we need a conversion if the memory format is float. */
2510 rs6000_convert_register_p (struct gdbarch
*gdbarch
, int regnum
,
2513 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2515 return (tdep
->ppc_fp0_regnum
>= 0
2516 && regnum
>= tdep
->ppc_fp0_regnum
2517 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
2518 && type
->code () == TYPE_CODE_FLT
2519 && TYPE_LENGTH (type
)
2520 != TYPE_LENGTH (builtin_type (gdbarch
)->builtin_double
));
2524 rs6000_register_to_value (struct frame_info
*frame
,
2528 int *optimizedp
, int *unavailablep
)
2530 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2531 gdb_byte from
[PPC_MAX_REGISTER_SIZE
];
2533 gdb_assert (type
->code () == TYPE_CODE_FLT
);
2535 if (!get_frame_register_bytes (frame
, regnum
, 0,
2536 register_size (gdbarch
, regnum
),
2537 from
, optimizedp
, unavailablep
))
2540 target_float_convert (from
, builtin_type (gdbarch
)->builtin_double
,
2542 *optimizedp
= *unavailablep
= 0;
2547 rs6000_value_to_register (struct frame_info
*frame
,
2550 const gdb_byte
*from
)
2552 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2553 gdb_byte to
[PPC_MAX_REGISTER_SIZE
];
2555 gdb_assert (type
->code () == TYPE_CODE_FLT
);
2557 target_float_convert (from
, type
,
2558 to
, builtin_type (gdbarch
)->builtin_double
);
2559 put_frame_register (frame
, regnum
, to
);
2562 /* The type of a function that moves the value of REG between CACHE
2563 or BUF --- in either direction. */
2564 typedef enum register_status (*move_ev_register_func
) (struct regcache
*,
2567 /* Move SPE vector register values between a 64-bit buffer and the two
2568 32-bit raw register halves in a regcache. This function handles
2569 both splitting a 64-bit value into two 32-bit halves, and joining
2570 two halves into a whole 64-bit value, depending on the function
2571 passed as the MOVE argument.
2573 EV_REG must be the number of an SPE evN vector register --- a
2574 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2577 Call MOVE once for each 32-bit half of that register, passing
2578 REGCACHE, the number of the raw register corresponding to that
2579 half, and the address of the appropriate half of BUFFER.
2581 For example, passing 'regcache_raw_read' as the MOVE function will
2582 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2583 'regcache_raw_supply' will supply the contents of BUFFER to the
2584 appropriate pair of raw registers in REGCACHE.
2586 You may need to cast away some 'const' qualifiers when passing
2587 MOVE, since this function can't tell at compile-time which of
2588 REGCACHE or BUFFER is acting as the source of the data. If C had
2589 co-variant type qualifiers, ... */
2591 static enum register_status
2592 e500_move_ev_register (move_ev_register_func move
,
2593 struct regcache
*regcache
, int ev_reg
, void *buffer
)
2595 struct gdbarch
*arch
= regcache
->arch ();
2596 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
2598 gdb_byte
*byte_buffer
= (gdb_byte
*) buffer
;
2599 enum register_status status
;
2601 gdb_assert (IS_SPE_PSEUDOREG (tdep
, ev_reg
));
2603 reg_index
= ev_reg
- tdep
->ppc_ev0_regnum
;
2605 if (gdbarch_byte_order (arch
) == BFD_ENDIAN_BIG
)
2607 status
= move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2609 if (status
== REG_VALID
)
2610 status
= move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
,
2615 status
= move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
, byte_buffer
);
2616 if (status
== REG_VALID
)
2617 status
= move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2624 static enum register_status
2625 do_regcache_raw_write (struct regcache
*regcache
, int regnum
, void *buffer
)
2627 regcache
->raw_write (regnum
, (const gdb_byte
*) buffer
);
2632 static enum register_status
2633 e500_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2634 int ev_reg
, gdb_byte
*buffer
)
2636 struct gdbarch
*arch
= regcache
->arch ();
2637 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
2639 enum register_status status
;
2641 gdb_assert (IS_SPE_PSEUDOREG (tdep
, ev_reg
));
2643 reg_index
= ev_reg
- tdep
->ppc_ev0_regnum
;
2645 if (gdbarch_byte_order (arch
) == BFD_ENDIAN_BIG
)
2647 status
= regcache
->raw_read (tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2649 if (status
== REG_VALID
)
2650 status
= regcache
->raw_read (tdep
->ppc_gp0_regnum
+ reg_index
,
2655 status
= regcache
->raw_read (tdep
->ppc_gp0_regnum
+ reg_index
, buffer
);
2656 if (status
== REG_VALID
)
2657 status
= regcache
->raw_read (tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2666 e500_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2667 int reg_nr
, const gdb_byte
*buffer
)
2669 e500_move_ev_register (do_regcache_raw_write
, regcache
,
2670 reg_nr
, (void *) buffer
);
2673 /* Read method for DFP pseudo-registers. */
2674 static enum register_status
2675 dfp_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2676 int reg_nr
, gdb_byte
*buffer
)
2678 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2680 enum register_status status
;
2682 if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2684 reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2685 fp0
= PPC_F0_REGNUM
;
2689 gdb_assert (IS_CDFP_PSEUDOREG (tdep
, reg_nr
));
2691 reg_index
= reg_nr
- tdep
->ppc_cdl0_regnum
;
2692 fp0
= PPC_CF0_REGNUM
;
2695 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2697 /* Read two FP registers to form a whole dl register. */
2698 status
= regcache
->raw_read (fp0
+ 2 * reg_index
, buffer
);
2699 if (status
== REG_VALID
)
2700 status
= regcache
->raw_read (fp0
+ 2 * reg_index
+ 1,
2705 status
= regcache
->raw_read (fp0
+ 2 * reg_index
+ 1, buffer
);
2706 if (status
== REG_VALID
)
2707 status
= regcache
->raw_read (fp0
+ 2 * reg_index
, buffer
+ 8);
2713 /* Write method for DFP pseudo-registers. */
2715 dfp_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2716 int reg_nr
, const gdb_byte
*buffer
)
2718 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2721 if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2723 reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2724 fp0
= PPC_F0_REGNUM
;
2728 gdb_assert (IS_CDFP_PSEUDOREG (tdep
, reg_nr
));
2730 reg_index
= reg_nr
- tdep
->ppc_cdl0_regnum
;
2731 fp0
= PPC_CF0_REGNUM
;
2734 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2736 /* Write each half of the dl register into a separate
2738 regcache
->raw_write (fp0
+ 2 * reg_index
, buffer
);
2739 regcache
->raw_write (fp0
+ 2 * reg_index
+ 1, buffer
+ 8);
2743 regcache
->raw_write (fp0
+ 2 * reg_index
+ 1, buffer
);
2744 regcache
->raw_write (fp0
+ 2 * reg_index
, buffer
+ 8);
2748 /* Read method for the vX aliases for the raw vrX registers. */
2750 static enum register_status
2751 v_alias_pseudo_register_read (struct gdbarch
*gdbarch
,
2752 readable_regcache
*regcache
, int reg_nr
,
2755 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2756 gdb_assert (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
));
2758 return regcache
->raw_read (tdep
->ppc_vr0_regnum
2759 + (reg_nr
- tdep
->ppc_v0_alias_regnum
),
2763 /* Write method for the vX aliases for the raw vrX registers. */
2766 v_alias_pseudo_register_write (struct gdbarch
*gdbarch
,
2767 struct regcache
*regcache
,
2768 int reg_nr
, const gdb_byte
*buffer
)
2770 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2771 gdb_assert (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
));
2773 regcache
->raw_write (tdep
->ppc_vr0_regnum
2774 + (reg_nr
- tdep
->ppc_v0_alias_regnum
), buffer
);
2777 /* Read method for POWER7 VSX pseudo-registers. */
2778 static enum register_status
2779 vsx_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2780 int reg_nr
, gdb_byte
*buffer
)
2782 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2783 int reg_index
, vr0
, fp0
, vsr0_upper
;
2784 enum register_status status
;
2786 if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2788 reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2789 vr0
= PPC_VR0_REGNUM
;
2790 fp0
= PPC_F0_REGNUM
;
2791 vsr0_upper
= PPC_VSR0_UPPER_REGNUM
;
2795 gdb_assert (IS_CVSX_PSEUDOREG (tdep
, reg_nr
));
2797 reg_index
= reg_nr
- tdep
->ppc_cvsr0_regnum
;
2798 vr0
= PPC_CVR0_REGNUM
;
2799 fp0
= PPC_CF0_REGNUM
;
2800 vsr0_upper
= PPC_CVSR0_UPPER_REGNUM
;
2803 /* Read the portion that overlaps the VMX registers. */
2805 status
= regcache
->raw_read (vr0
+ reg_index
- 32, buffer
);
2807 /* Read the portion that overlaps the FPR registers. */
2808 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2810 status
= regcache
->raw_read (fp0
+ reg_index
, buffer
);
2811 if (status
== REG_VALID
)
2812 status
= regcache
->raw_read (vsr0_upper
+ reg_index
,
2817 status
= regcache
->raw_read (fp0
+ reg_index
, buffer
+ 8);
2818 if (status
== REG_VALID
)
2819 status
= regcache
->raw_read (vsr0_upper
+ reg_index
, buffer
);
2825 /* Write method for POWER7 VSX pseudo-registers. */
2827 vsx_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2828 int reg_nr
, const gdb_byte
*buffer
)
2830 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2831 int reg_index
, vr0
, fp0
, vsr0_upper
;
2833 if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2835 reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2836 vr0
= PPC_VR0_REGNUM
;
2837 fp0
= PPC_F0_REGNUM
;
2838 vsr0_upper
= PPC_VSR0_UPPER_REGNUM
;
2842 gdb_assert (IS_CVSX_PSEUDOREG (tdep
, reg_nr
));
2844 reg_index
= reg_nr
- tdep
->ppc_cvsr0_regnum
;
2845 vr0
= PPC_CVR0_REGNUM
;
2846 fp0
= PPC_CF0_REGNUM
;
2847 vsr0_upper
= PPC_CVSR0_UPPER_REGNUM
;
2850 /* Write the portion that overlaps the VMX registers. */
2852 regcache
->raw_write (vr0
+ reg_index
- 32, buffer
);
2854 /* Write the portion that overlaps the FPR registers. */
2855 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2857 regcache
->raw_write (fp0
+ reg_index
, buffer
);
2858 regcache
->raw_write (vsr0_upper
+ reg_index
, buffer
+ 8);
2862 regcache
->raw_write (fp0
+ reg_index
, buffer
+ 8);
2863 regcache
->raw_write (vsr0_upper
+ reg_index
, buffer
);
2867 /* Read method for POWER7 Extended FP pseudo-registers. */
2868 static enum register_status
2869 efp_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2870 int reg_nr
, gdb_byte
*buffer
)
2872 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2875 if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
2877 reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
2878 vr0
= PPC_VR0_REGNUM
;
2882 gdb_assert (IS_CEFP_PSEUDOREG (tdep
, reg_nr
));
2884 reg_index
= reg_nr
- tdep
->ppc_cefpr0_regnum
;
2885 vr0
= PPC_CVR0_REGNUM
;
2888 int offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 0 : 8;
2890 /* Read the portion that overlaps the VMX register. */
2891 return regcache
->raw_read_part (vr0
+ reg_index
, offset
,
2892 register_size (gdbarch
, reg_nr
),
2896 /* Write method for POWER7 Extended FP pseudo-registers. */
2898 efp_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2899 int reg_nr
, const gdb_byte
*buffer
)
2901 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2903 int offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 0 : 8;
2905 if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
2907 reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
2908 vr0
= PPC_VR0_REGNUM
;
2912 gdb_assert (IS_CEFP_PSEUDOREG (tdep
, reg_nr
));
2914 reg_index
= reg_nr
- tdep
->ppc_cefpr0_regnum
;
2915 vr0
= PPC_CVR0_REGNUM
;
2917 /* The call to raw_write_part fails silently if the initial read
2918 of the read-update-write sequence returns an invalid status,
2919 so we check this manually and throw an error if needed. */
2920 regcache
->raw_update (vr0
+ reg_index
);
2921 if (regcache
->get_register_status (vr0
+ reg_index
) != REG_VALID
)
2922 error (_("Cannot write to the checkpointed EFP register, "
2923 "the corresponding vector register is unavailable."));
2926 /* Write the portion that overlaps the VMX register. */
2927 regcache
->raw_write_part (vr0
+ reg_index
, offset
,
2928 register_size (gdbarch
, reg_nr
), buffer
);
2931 static enum register_status
2932 rs6000_pseudo_register_read (struct gdbarch
*gdbarch
,
2933 readable_regcache
*regcache
,
2934 int reg_nr
, gdb_byte
*buffer
)
2936 struct gdbarch
*regcache_arch
= regcache
->arch ();
2937 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2939 gdb_assert (regcache_arch
== gdbarch
);
2941 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2942 return e500_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2943 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
)
2944 || IS_CDFP_PSEUDOREG (tdep
, reg_nr
))
2945 return dfp_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2946 else if (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
))
2947 return v_alias_pseudo_register_read (gdbarch
, regcache
, reg_nr
,
2949 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
)
2950 || IS_CVSX_PSEUDOREG (tdep
, reg_nr
))
2951 return vsx_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2952 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
)
2953 || IS_CEFP_PSEUDOREG (tdep
, reg_nr
))
2954 return efp_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2956 internal_error (__FILE__
, __LINE__
,
2957 _("rs6000_pseudo_register_read: "
2958 "called on unexpected register '%s' (%d)"),
2959 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2963 rs6000_pseudo_register_write (struct gdbarch
*gdbarch
,
2964 struct regcache
*regcache
,
2965 int reg_nr
, const gdb_byte
*buffer
)
2967 struct gdbarch
*regcache_arch
= regcache
->arch ();
2968 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2970 gdb_assert (regcache_arch
== gdbarch
);
2972 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2973 e500_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2974 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
)
2975 || IS_CDFP_PSEUDOREG (tdep
, reg_nr
))
2976 dfp_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2977 else if (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
))
2978 v_alias_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2979 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
)
2980 || IS_CVSX_PSEUDOREG (tdep
, reg_nr
))
2981 vsx_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2982 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
)
2983 || IS_CEFP_PSEUDOREG (tdep
, reg_nr
))
2984 efp_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2986 internal_error (__FILE__
, __LINE__
,
2987 _("rs6000_pseudo_register_write: "
2988 "called on unexpected register '%s' (%d)"),
2989 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2992 /* Set the register mask in AX with the registers that form the DFP or
2993 checkpointed DFP pseudo-register REG_NR. */
2996 dfp_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
2997 struct agent_expr
*ax
, int reg_nr
)
2999 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3002 if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
3004 reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
3005 fp0
= PPC_F0_REGNUM
;
3009 gdb_assert (IS_CDFP_PSEUDOREG (tdep
, reg_nr
));
3011 reg_index
= reg_nr
- tdep
->ppc_cdl0_regnum
;
3012 fp0
= PPC_CF0_REGNUM
;
3015 ax_reg_mask (ax
, fp0
+ 2 * reg_index
);
3016 ax_reg_mask (ax
, fp0
+ 2 * reg_index
+ 1);
3019 /* Set the register mask in AX with the raw vector register that
3020 corresponds to its REG_NR alias. */
3023 v_alias_pseudo_register_collect (struct gdbarch
*gdbarch
,
3024 struct agent_expr
*ax
, int reg_nr
)
3026 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3027 gdb_assert (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
));
3029 ax_reg_mask (ax
, tdep
->ppc_vr0_regnum
3030 + (reg_nr
- tdep
->ppc_v0_alias_regnum
));
3033 /* Set the register mask in AX with the registers that form the VSX or
3034 checkpointed VSX pseudo-register REG_NR. */
3037 vsx_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
3038 struct agent_expr
*ax
, int reg_nr
)
3040 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3041 int reg_index
, vr0
, fp0
, vsr0_upper
;
3043 if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
3045 reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
3046 vr0
= PPC_VR0_REGNUM
;
3047 fp0
= PPC_F0_REGNUM
;
3048 vsr0_upper
= PPC_VSR0_UPPER_REGNUM
;
3052 gdb_assert (IS_CVSX_PSEUDOREG (tdep
, reg_nr
));
3054 reg_index
= reg_nr
- tdep
->ppc_cvsr0_regnum
;
3055 vr0
= PPC_CVR0_REGNUM
;
3056 fp0
= PPC_CF0_REGNUM
;
3057 vsr0_upper
= PPC_CVSR0_UPPER_REGNUM
;
3062 ax_reg_mask (ax
, vr0
+ reg_index
- 32);
3066 ax_reg_mask (ax
, fp0
+ reg_index
);
3067 ax_reg_mask (ax
, vsr0_upper
+ reg_index
);
3071 /* Set the register mask in AX with the register that corresponds to
3072 the EFP or checkpointed EFP pseudo-register REG_NR. */
3075 efp_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
3076 struct agent_expr
*ax
, int reg_nr
)
3078 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3081 if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
3083 reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
3084 vr0
= PPC_VR0_REGNUM
;
3088 gdb_assert (IS_CEFP_PSEUDOREG (tdep
, reg_nr
));
3090 reg_index
= reg_nr
- tdep
->ppc_cefpr0_regnum
;
3091 vr0
= PPC_CVR0_REGNUM
;
3094 ax_reg_mask (ax
, vr0
+ reg_index
);
3098 rs6000_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
3099 struct agent_expr
*ax
, int reg_nr
)
3101 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3102 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
3104 int reg_index
= reg_nr
- tdep
->ppc_ev0_regnum
;
3105 ax_reg_mask (ax
, tdep
->ppc_gp0_regnum
+ reg_index
);
3106 ax_reg_mask (ax
, tdep
->ppc_ev0_upper_regnum
+ reg_index
);
3108 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
)
3109 || IS_CDFP_PSEUDOREG (tdep
, reg_nr
))
3111 dfp_ax_pseudo_register_collect (gdbarch
, ax
, reg_nr
);
3113 else if (IS_V_ALIAS_PSEUDOREG (tdep
, reg_nr
))
3115 v_alias_pseudo_register_collect (gdbarch
, ax
, reg_nr
);
3117 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
)
3118 || IS_CVSX_PSEUDOREG (tdep
, reg_nr
))
3120 vsx_ax_pseudo_register_collect (gdbarch
, ax
, reg_nr
);
3122 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
)
3123 || IS_CEFP_PSEUDOREG (tdep
, reg_nr
))
3125 efp_ax_pseudo_register_collect (gdbarch
, ax
, reg_nr
);
3128 internal_error (__FILE__
, __LINE__
,
3129 _("rs6000_pseudo_register_collect: "
3130 "called on unexpected register '%s' (%d)"),
3131 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
3137 rs6000_gen_return_address (struct gdbarch
*gdbarch
,
3138 struct agent_expr
*ax
, struct axs_value
*value
,
3141 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3142 value
->type
= register_type (gdbarch
, tdep
->ppc_lr_regnum
);
3143 value
->kind
= axs_lvalue_register
;
3144 value
->u
.reg
= tdep
->ppc_lr_regnum
;
3148 /* Convert a DBX STABS register number to a GDB register number. */
3150 rs6000_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
3152 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3154 if (0 <= num
&& num
<= 31)
3155 return tdep
->ppc_gp0_regnum
+ num
;
3156 else if (32 <= num
&& num
<= 63)
3157 /* FIXME: jimb/2004-05-05: What should we do when the debug info
3158 specifies registers the architecture doesn't have? Our
3159 callers don't check the value we return. */
3160 return tdep
->ppc_fp0_regnum
+ (num
- 32);
3161 else if (77 <= num
&& num
<= 108)
3162 return tdep
->ppc_vr0_regnum
+ (num
- 77);
3163 else if (1200 <= num
&& num
< 1200 + 32)
3164 return tdep
->ppc_ev0_upper_regnum
+ (num
- 1200);
3169 return tdep
->ppc_mq_regnum
;
3171 return tdep
->ppc_lr_regnum
;
3173 return tdep
->ppc_ctr_regnum
;
3175 return tdep
->ppc_xer_regnum
;
3177 return tdep
->ppc_vrsave_regnum
;
3179 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
3181 return tdep
->ppc_acc_regnum
;
3183 return tdep
->ppc_spefscr_regnum
;
3190 /* Convert a Dwarf 2 register number to a GDB register number. */
3192 rs6000_dwarf2_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
3194 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3196 if (0 <= num
&& num
<= 31)
3197 return tdep
->ppc_gp0_regnum
+ num
;
3198 else if (32 <= num
&& num
<= 63)
3199 /* FIXME: jimb/2004-05-05: What should we do when the debug info
3200 specifies registers the architecture doesn't have? Our
3201 callers don't check the value we return. */
3202 return tdep
->ppc_fp0_regnum
+ (num
- 32);
3203 else if (1124 <= num
&& num
< 1124 + 32)
3204 return tdep
->ppc_vr0_regnum
+ (num
- 1124);
3205 else if (1200 <= num
&& num
< 1200 + 32)
3206 return tdep
->ppc_ev0_upper_regnum
+ (num
- 1200);
3211 return tdep
->ppc_cr_regnum
;
3213 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
3215 return tdep
->ppc_acc_regnum
;
3217 return tdep
->ppc_mq_regnum
;
3219 return tdep
->ppc_xer_regnum
;
3221 return tdep
->ppc_lr_regnum
;
3223 return tdep
->ppc_ctr_regnum
;
3225 return tdep
->ppc_vrsave_regnum
;
3227 return tdep
->ppc_spefscr_regnum
;
3230 /* Unknown DWARF register number. */
3234 /* Translate a .eh_frame register to DWARF register, or adjust a
3235 .debug_frame register. */
3238 rs6000_adjust_frame_regnum (struct gdbarch
*gdbarch
, int num
, int eh_frame_p
)
3240 /* GCC releases before 3.4 use GCC internal register numbering in
3241 .debug_frame (and .debug_info, et cetera). The numbering is
3242 different from the standard SysV numbering for everything except
3243 for GPRs and FPRs. We can not detect this problem in most cases
3244 - to get accurate debug info for variables living in lr, ctr, v0,
3245 et cetera, use a newer version of GCC. But we must detect
3246 one important case - lr is in column 65 in .debug_frame output,
3249 GCC 3.4, and the "hammer" branch, have a related problem. They
3250 record lr register saves in .debug_frame as 108, but still record
3251 the return column as 65. We fix that up too.
3253 We can do this because 65 is assigned to fpsr, and GCC never
3254 generates debug info referring to it. To add support for
3255 handwritten debug info that restores fpsr, we would need to add a
3256 producer version check to this. */
3265 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
3266 internal register numbering; translate that to the standard DWARF2
3267 register numbering. */
3268 if (0 <= num
&& num
<= 63) /* r0-r31,fp0-fp31 */
3270 else if (68 <= num
&& num
<= 75) /* cr0-cr8 */
3271 return num
- 68 + 86;
3272 else if (77 <= num
&& num
<= 108) /* vr0-vr31 */
3273 return num
- 77 + 1124;
3285 case 109: /* vrsave */
3287 case 110: /* vscr */
3289 case 111: /* spe_acc */
3291 case 112: /* spefscr */
3299 /* Handling the various POWER/PowerPC variants. */
3301 /* Information about a particular processor variant. */
3305 /* Name of this variant. */
3308 /* English description of the variant. */
3309 const char *description
;
3311 /* bfd_arch_info.arch corresponding to variant. */
3312 enum bfd_architecture arch
;
3314 /* bfd_arch_info.mach corresponding to variant. */
3317 /* Target description for this variant. */
3318 struct target_desc
**tdesc
;
3321 static struct ppc_variant variants
[] =
3323 {"powerpc", "PowerPC user-level", bfd_arch_powerpc
,
3324 bfd_mach_ppc
, &tdesc_powerpc_altivec32
},
3325 {"power", "POWER user-level", bfd_arch_rs6000
,
3326 bfd_mach_rs6k
, &tdesc_rs6000
},
3327 {"403", "IBM PowerPC 403", bfd_arch_powerpc
,
3328 bfd_mach_ppc_403
, &tdesc_powerpc_403
},
3329 {"405", "IBM PowerPC 405", bfd_arch_powerpc
,
3330 bfd_mach_ppc_405
, &tdesc_powerpc_405
},
3331 {"601", "Motorola PowerPC 601", bfd_arch_powerpc
,
3332 bfd_mach_ppc_601
, &tdesc_powerpc_601
},
3333 {"602", "Motorola PowerPC 602", bfd_arch_powerpc
,
3334 bfd_mach_ppc_602
, &tdesc_powerpc_602
},
3335 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc
,
3336 bfd_mach_ppc_603
, &tdesc_powerpc_603
},
3337 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc
,
3338 604, &tdesc_powerpc_604
},
3339 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc
,
3340 bfd_mach_ppc_403gc
, &tdesc_powerpc_403gc
},
3341 {"505", "Motorola PowerPC 505", bfd_arch_powerpc
,
3342 bfd_mach_ppc_505
, &tdesc_powerpc_505
},
3343 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc
,
3344 bfd_mach_ppc_860
, &tdesc_powerpc_860
},
3345 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc
,
3346 bfd_mach_ppc_750
, &tdesc_powerpc_750
},
3347 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc
,
3348 bfd_mach_ppc_7400
, &tdesc_powerpc_7400
},
3349 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc
,
3350 bfd_mach_ppc_e500
, &tdesc_powerpc_e500
},
3353 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc
,
3354 bfd_mach_ppc64
, &tdesc_powerpc_altivec64
},
3355 {"620", "Motorola PowerPC 620", bfd_arch_powerpc
,
3356 bfd_mach_ppc_620
, &tdesc_powerpc_64
},
3357 {"630", "Motorola PowerPC 630", bfd_arch_powerpc
,
3358 bfd_mach_ppc_630
, &tdesc_powerpc_64
},
3359 {"a35", "PowerPC A35", bfd_arch_powerpc
,
3360 bfd_mach_ppc_a35
, &tdesc_powerpc_64
},
3361 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc
,
3362 bfd_mach_ppc_rs64ii
, &tdesc_powerpc_64
},
3363 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc
,
3364 bfd_mach_ppc_rs64iii
, &tdesc_powerpc_64
},
3366 /* FIXME: I haven't checked the register sets of the following. */
3367 {"rs1", "IBM POWER RS1", bfd_arch_rs6000
,
3368 bfd_mach_rs6k_rs1
, &tdesc_rs6000
},
3369 {"rsc", "IBM POWER RSC", bfd_arch_rs6000
,
3370 bfd_mach_rs6k_rsc
, &tdesc_rs6000
},
3371 {"rs2", "IBM POWER RS2", bfd_arch_rs6000
,
3372 bfd_mach_rs6k_rs2
, &tdesc_rs6000
},
3374 {0, 0, (enum bfd_architecture
) 0, 0, 0}
3377 /* Return the variant corresponding to architecture ARCH and machine number
3378 MACH. If no such variant exists, return null. */
3380 static const struct ppc_variant
*
3381 find_variant_by_arch (enum bfd_architecture arch
, unsigned long mach
)
3383 const struct ppc_variant
*v
;
3385 for (v
= variants
; v
->name
; v
++)
3386 if (arch
== v
->arch
&& mach
== v
->mach
)
3394 struct rs6000_frame_cache
3397 CORE_ADDR initial_sp
;
3398 struct trad_frame_saved_reg
*saved_regs
;
3400 /* Set BASE_P to true if this frame cache is properly initialized.
3401 Otherwise set to false because some registers or memory cannot
3404 /* Cache PC for building unavailable frame. */
3408 static struct rs6000_frame_cache
*
3409 rs6000_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3411 struct rs6000_frame_cache
*cache
;
3412 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3413 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3414 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3415 struct rs6000_framedata fdata
;
3416 int wordsize
= tdep
->wordsize
;
3417 CORE_ADDR func
= 0, pc
= 0;
3419 if ((*this_cache
) != NULL
)
3420 return (struct rs6000_frame_cache
*) (*this_cache
);
3421 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
3422 (*this_cache
) = cache
;
3424 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3428 func
= get_frame_func (this_frame
);
3430 pc
= get_frame_pc (this_frame
);
3431 skip_prologue (gdbarch
, func
, pc
, &fdata
);
3433 /* Figure out the parent's stack pointer. */
3435 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
3436 address of the current frame. Things might be easier if the
3437 ->frame pointed to the outer-most address of the frame. In
3438 the mean time, the address of the prev frame is used as the
3439 base address of this frame. */
3440 cache
->base
= get_frame_register_unsigned
3441 (this_frame
, gdbarch_sp_regnum (gdbarch
));
3443 catch (const gdb_exception_error
&ex
)
3445 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
3447 return (struct rs6000_frame_cache
*) (*this_cache
);
3450 /* If the function appears to be frameless, check a couple of likely
3451 indicators that we have simply failed to find the frame setup.
3452 Two common cases of this are missing symbols (i.e.
3453 get_frame_func returns the wrong address or 0), and assembly
3454 stubs which have a fast exit path but set up a frame on the slow
3457 If the LR appears to return to this function, then presume that
3458 we have an ABI compliant frame that we failed to find. */
3459 if (fdata
.frameless
&& fdata
.lr_offset
== 0)
3464 saved_lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
3465 if (func
== 0 && saved_lr
== pc
)
3469 CORE_ADDR saved_func
= get_pc_function_start (saved_lr
);
3470 if (func
== saved_func
)
3476 fdata
.frameless
= 0;
3477 fdata
.lr_offset
= tdep
->lr_frame_offset
;
3481 if (!fdata
.frameless
)
3483 /* Frameless really means stackless. */
3486 if (safe_read_memory_unsigned_integer (cache
->base
, wordsize
,
3487 byte_order
, &backchain
))
3488 cache
->base
= (CORE_ADDR
) backchain
;
3491 trad_frame_set_value (cache
->saved_regs
,
3492 gdbarch_sp_regnum (gdbarch
), cache
->base
);
3494 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
3495 All fpr's from saved_fpr to fp31 are saved. */
3497 if (fdata
.saved_fpr
>= 0)
3500 CORE_ADDR fpr_addr
= cache
->base
+ fdata
.fpr_offset
;
3502 /* If skip_prologue says floating-point registers were saved,
3503 but the current architecture has no floating-point registers,
3504 then that's strange. But we have no indices to even record
3505 the addresses under, so we just ignore it. */
3506 if (ppc_floating_point_unit_p (gdbarch
))
3507 for (i
= fdata
.saved_fpr
; i
< ppc_num_fprs
; i
++)
3509 cache
->saved_regs
[tdep
->ppc_fp0_regnum
+ i
].addr
= fpr_addr
;
3514 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
3515 All gpr's from saved_gpr to gpr31 are saved (except during the
3518 if (fdata
.saved_gpr
>= 0)
3521 CORE_ADDR gpr_addr
= cache
->base
+ fdata
.gpr_offset
;
3522 for (i
= fdata
.saved_gpr
; i
< ppc_num_gprs
; i
++)
3524 if (fdata
.gpr_mask
& (1U << i
))
3525 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= gpr_addr
;
3526 gpr_addr
+= wordsize
;
3530 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
3531 All vr's from saved_vr to vr31 are saved. */
3532 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
3534 if (fdata
.saved_vr
>= 0)
3537 CORE_ADDR vr_addr
= cache
->base
+ fdata
.vr_offset
;
3538 for (i
= fdata
.saved_vr
; i
< 32; i
++)
3540 cache
->saved_regs
[tdep
->ppc_vr0_regnum
+ i
].addr
= vr_addr
;
3541 vr_addr
+= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
3546 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
3547 All vr's from saved_ev to ev31 are saved. ????? */
3548 if (tdep
->ppc_ev0_regnum
!= -1)
3550 if (fdata
.saved_ev
>= 0)
3553 CORE_ADDR ev_addr
= cache
->base
+ fdata
.ev_offset
;
3554 CORE_ADDR off
= (byte_order
== BFD_ENDIAN_BIG
? 4 : 0);
3556 for (i
= fdata
.saved_ev
; i
< ppc_num_gprs
; i
++)
3558 cache
->saved_regs
[tdep
->ppc_ev0_regnum
+ i
].addr
= ev_addr
;
3559 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= ev_addr
+ off
;
3560 ev_addr
+= register_size (gdbarch
, tdep
->ppc_ev0_regnum
);
3565 /* If != 0, fdata.cr_offset is the offset from the frame that
3567 if (fdata
.cr_offset
!= 0)
3568 cache
->saved_regs
[tdep
->ppc_cr_regnum
].addr
3569 = cache
->base
+ fdata
.cr_offset
;
3571 /* If != 0, fdata.lr_offset is the offset from the frame that
3573 if (fdata
.lr_offset
!= 0)
3574 cache
->saved_regs
[tdep
->ppc_lr_regnum
].addr
3575 = cache
->base
+ fdata
.lr_offset
;
3576 else if (fdata
.lr_register
!= -1)
3577 cache
->saved_regs
[tdep
->ppc_lr_regnum
].realreg
= fdata
.lr_register
;
3578 /* The PC is found in the link register. */
3579 cache
->saved_regs
[gdbarch_pc_regnum (gdbarch
)] =
3580 cache
->saved_regs
[tdep
->ppc_lr_regnum
];
3582 /* If != 0, fdata.vrsave_offset is the offset from the frame that
3583 holds the VRSAVE. */
3584 if (fdata
.vrsave_offset
!= 0)
3585 cache
->saved_regs
[tdep
->ppc_vrsave_regnum
].addr
3586 = cache
->base
+ fdata
.vrsave_offset
;
3588 if (fdata
.alloca_reg
< 0)
3589 /* If no alloca register used, then fi->frame is the value of the
3590 %sp for this frame, and it is good enough. */
3592 = get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
3595 = get_frame_register_unsigned (this_frame
, fdata
.alloca_reg
);
3602 rs6000_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3603 struct frame_id
*this_id
)
3605 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3610 (*this_id
) = frame_id_build_unavailable_stack (info
->pc
);
3614 /* This marks the outermost frame. */
3615 if (info
->base
== 0)
3618 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3621 static struct value
*
3622 rs6000_frame_prev_register (struct frame_info
*this_frame
,
3623 void **this_cache
, int regnum
)
3625 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3627 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3630 static const struct frame_unwind rs6000_frame_unwind
=
3633 default_frame_unwind_stop_reason
,
3634 rs6000_frame_this_id
,
3635 rs6000_frame_prev_register
,
3637 default_frame_sniffer
3640 /* Allocate and initialize a frame cache for an epilogue frame.
3641 SP is restored and prev-PC is stored in LR. */
3643 static struct rs6000_frame_cache
*
3644 rs6000_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3646 struct rs6000_frame_cache
*cache
;
3647 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3648 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3651 return (struct rs6000_frame_cache
*) *this_cache
;
3653 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
3654 (*this_cache
) = cache
;
3655 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3659 /* At this point the stack looks as if we just entered the
3660 function, and the return address is stored in LR. */
3663 sp
= get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
3664 lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
3667 cache
->initial_sp
= sp
;
3669 trad_frame_set_value (cache
->saved_regs
,
3670 gdbarch_pc_regnum (gdbarch
), lr
);
3672 catch (const gdb_exception_error
&ex
)
3674 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
3681 /* Implementation of frame_unwind.this_id, as defined in frame_unwind.h.
3682 Return the frame ID of an epilogue frame. */
3685 rs6000_epilogue_frame_this_id (struct frame_info
*this_frame
,
3686 void **this_cache
, struct frame_id
*this_id
)
3689 struct rs6000_frame_cache
*info
=
3690 rs6000_epilogue_frame_cache (this_frame
, this_cache
);
3692 pc
= get_frame_func (this_frame
);
3693 if (info
->base
== 0)
3694 (*this_id
) = frame_id_build_unavailable_stack (pc
);
3696 (*this_id
) = frame_id_build (info
->base
, pc
);
3699 /* Implementation of frame_unwind.prev_register, as defined in frame_unwind.h.
3700 Return the register value of REGNUM in previous frame. */
3702 static struct value
*
3703 rs6000_epilogue_frame_prev_register (struct frame_info
*this_frame
,
3704 void **this_cache
, int regnum
)
3706 struct rs6000_frame_cache
*info
=
3707 rs6000_epilogue_frame_cache (this_frame
, this_cache
);
3708 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3711 /* Implementation of frame_unwind.sniffer, as defined in frame_unwind.h.
3712 Check whether this an epilogue frame. */
3715 rs6000_epilogue_frame_sniffer (const struct frame_unwind
*self
,
3716 struct frame_info
*this_frame
,
3717 void **this_prologue_cache
)
3719 if (frame_relative_level (this_frame
) == 0)
3720 return rs6000_in_function_epilogue_frame_p (this_frame
,
3721 get_frame_arch (this_frame
),
3722 get_frame_pc (this_frame
));
3727 /* Frame unwinder for epilogue frame. This is required for reverse step-over
3728 a function without debug information. */
3730 static const struct frame_unwind rs6000_epilogue_frame_unwind
=
3733 default_frame_unwind_stop_reason
,
3734 rs6000_epilogue_frame_this_id
, rs6000_epilogue_frame_prev_register
,
3736 rs6000_epilogue_frame_sniffer
3741 rs6000_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
3743 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3745 return info
->initial_sp
;
3748 static const struct frame_base rs6000_frame_base
= {
3749 &rs6000_frame_unwind
,
3750 rs6000_frame_base_address
,
3751 rs6000_frame_base_address
,
3752 rs6000_frame_base_address
3755 static const struct frame_base
*
3756 rs6000_frame_base_sniffer (struct frame_info
*this_frame
)
3758 return &rs6000_frame_base
;
3761 /* DWARF-2 frame support. Used to handle the detection of
3762 clobbered registers during function calls. */
3765 ppc_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
3766 struct dwarf2_frame_state_reg
*reg
,
3767 struct frame_info
*this_frame
)
3769 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3771 /* PPC32 and PPC64 ABI's are the same regarding volatile and
3772 non-volatile registers. We will use the same code for both. */
3774 /* Call-saved GP registers. */
3775 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 14
3776 && regnum
<= tdep
->ppc_gp0_regnum
+ 31)
3777 || (regnum
== tdep
->ppc_gp0_regnum
+ 1))
3778 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3780 /* Call-clobbered GP registers. */
3781 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 3
3782 && regnum
<= tdep
->ppc_gp0_regnum
+ 12)
3783 || (regnum
== tdep
->ppc_gp0_regnum
))
3784 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3786 /* Deal with FP registers, if supported. */
3787 if (tdep
->ppc_fp0_regnum
>= 0)
3789 /* Call-saved FP registers. */
3790 if ((regnum
>= tdep
->ppc_fp0_regnum
+ 14
3791 && regnum
<= tdep
->ppc_fp0_regnum
+ 31))
3792 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3794 /* Call-clobbered FP registers. */
3795 if ((regnum
>= tdep
->ppc_fp0_regnum
3796 && regnum
<= tdep
->ppc_fp0_regnum
+ 13))
3797 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3800 /* Deal with ALTIVEC registers, if supported. */
3801 if (tdep
->ppc_vr0_regnum
> 0 && tdep
->ppc_vrsave_regnum
> 0)
3803 /* Call-saved Altivec registers. */
3804 if ((regnum
>= tdep
->ppc_vr0_regnum
+ 20
3805 && regnum
<= tdep
->ppc_vr0_regnum
+ 31)
3806 || regnum
== tdep
->ppc_vrsave_regnum
)
3807 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3809 /* Call-clobbered Altivec registers. */
3810 if ((regnum
>= tdep
->ppc_vr0_regnum
3811 && regnum
<= tdep
->ppc_vr0_regnum
+ 19))
3812 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3815 /* Handle PC register and Stack Pointer correctly. */
3816 if (regnum
== gdbarch_pc_regnum (gdbarch
))
3817 reg
->how
= DWARF2_FRAME_REG_RA
;
3818 else if (regnum
== gdbarch_sp_regnum (gdbarch
))
3819 reg
->how
= DWARF2_FRAME_REG_CFA
;
3823 /* Return true if a .gnu_attributes section exists in BFD and it
3824 indicates we are using SPE extensions OR if a .PPC.EMB.apuinfo
3825 section exists in BFD and it indicates that SPE extensions are in
3826 use. Check the .gnu.attributes section first, as the binary might be
3827 compiled for SPE, but not actually using SPE instructions. */
3830 bfd_uses_spe_extensions (bfd
*abfd
)
3833 gdb_byte
*contents
= NULL
;
3842 /* Using Tag_GNU_Power_ABI_Vector here is a bit of a hack, as the user
3843 could be using the SPE vector abi without actually using any spe
3844 bits whatsoever. But it's close enough for now. */
3845 int vector_abi
= bfd_elf_get_obj_attr_int (abfd
, OBJ_ATTR_GNU
,
3846 Tag_GNU_Power_ABI_Vector
);
3847 if (vector_abi
== 3)
3851 sect
= bfd_get_section_by_name (abfd
, ".PPC.EMB.apuinfo");
3855 size
= bfd_section_size (sect
);
3856 contents
= (gdb_byte
*) xmalloc (size
);
3857 if (!bfd_get_section_contents (abfd
, sect
, contents
, 0, size
))
3863 /* Parse the .PPC.EMB.apuinfo section. The layout is as follows:
3869 char name[name_len rounded up to 4-byte alignment];
3870 char data[data_len];
3873 Technically, there's only supposed to be one such structure in a
3874 given apuinfo section, but the linker is not always vigilant about
3875 merging apuinfo sections from input files. Just go ahead and parse
3876 them all, exiting early when we discover the binary uses SPE
3879 It's not specified in what endianness the information in this
3880 section is stored. Assume that it's the endianness of the BFD. */
3884 unsigned int name_len
;
3885 unsigned int data_len
;
3888 /* If we can't read the first three fields, we're done. */
3892 name_len
= bfd_get_32 (abfd
, ptr
);
3893 name_len
= (name_len
+ 3) & ~3U; /* Round to 4 bytes. */
3894 data_len
= bfd_get_32 (abfd
, ptr
+ 4);
3895 type
= bfd_get_32 (abfd
, ptr
+ 8);
3898 /* The name must be "APUinfo\0". */
3900 && strcmp ((const char *) ptr
, "APUinfo") != 0)
3904 /* The type must be 2. */
3908 /* The data is stored as a series of uint32. The upper half of
3909 each uint32 indicates the particular APU used and the lower
3910 half indicates the revision of that APU. We just care about
3913 /* Not 4-byte quantities. */
3919 unsigned int apuinfo
= bfd_get_32 (abfd
, ptr
);
3920 unsigned int apu
= apuinfo
>> 16;
3924 /* The SPE APU is 0x100; the SPEFP APU is 0x101. Accept
3926 if (apu
== 0x100 || apu
== 0x101)
3941 /* These are macros for parsing instruction fields (I.1.6.28) */
3943 #define PPC_FIELD(value, from, len) \
3944 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
3945 #define PPC_SEXT(v, bs) \
3946 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
3947 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
3948 - ((CORE_ADDR) 1 << ((bs) - 1)))
3949 #define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
3950 #define PPC_EXTOP(insn) PPC_FIELD (insn, 21, 10)
3951 #define PPC_RT(insn) PPC_FIELD (insn, 6, 5)
3952 #define PPC_RS(insn) PPC_FIELD (insn, 6, 5)
3953 #define PPC_RA(insn) PPC_FIELD (insn, 11, 5)
3954 #define PPC_RB(insn) PPC_FIELD (insn, 16, 5)
3955 #define PPC_NB(insn) PPC_FIELD (insn, 16, 5)
3956 #define PPC_VRT(insn) PPC_FIELD (insn, 6, 5)
3957 #define PPC_FRT(insn) PPC_FIELD (insn, 6, 5)
3958 #define PPC_SPR(insn) (PPC_FIELD (insn, 11, 5) \
3959 | (PPC_FIELD (insn, 16, 5) << 5))
3960 #define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
3961 #define PPC_T(insn) PPC_FIELD (insn, 6, 5)
3962 #define PPC_D(insn) PPC_SEXT (PPC_FIELD (insn, 16, 16), 16)
3963 #define PPC_DS(insn) PPC_SEXT (PPC_FIELD (insn, 16, 14), 14)
3964 #define PPC_DQ(insn) PPC_SEXT (PPC_FIELD (insn, 16, 12), 12)
3965 #define PPC_BIT(insn,n) ((insn & (1 << (31 - (n)))) ? 1 : 0)
3966 #define PPC_OE(insn) PPC_BIT (insn, 21)
3967 #define PPC_RC(insn) PPC_BIT (insn, 31)
3968 #define PPC_Rc(insn) PPC_BIT (insn, 21)
3969 #define PPC_LK(insn) PPC_BIT (insn, 31)
3970 #define PPC_TX(insn) PPC_BIT (insn, 31)
3971 #define PPC_LEV(insn) PPC_FIELD (insn, 20, 7)
3973 #define PPC_XT(insn) ((PPC_TX (insn) << 5) | PPC_T (insn))
3974 #define PPC_XER_NB(xer) (xer & 0x7f)
3976 /* Record Vector-Scalar Registers.
3977 For VSR less than 32, it's represented by an FPR and an VSR-upper register.
3978 Otherwise, it's just a VR register. Record them accordingly. */
3981 ppc_record_vsr (struct regcache
*regcache
, struct gdbarch_tdep
*tdep
, int vsr
)
3983 if (vsr
< 0 || vsr
>= 64)
3988 if (tdep
->ppc_vr0_regnum
>= 0)
3989 record_full_arch_list_add_reg (regcache
, tdep
->ppc_vr0_regnum
+ vsr
- 32);
3993 if (tdep
->ppc_fp0_regnum
>= 0)
3994 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fp0_regnum
+ vsr
);
3995 if (tdep
->ppc_vsr0_upper_regnum
>= 0)
3996 record_full_arch_list_add_reg (regcache
,
3997 tdep
->ppc_vsr0_upper_regnum
+ vsr
);
4003 /* Parse and record instructions primary opcode-4 at ADDR.
4004 Return 0 if successful. */
4007 ppc_process_record_op4 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4008 CORE_ADDR addr
, uint32_t insn
)
4010 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4011 int ext
= PPC_FIELD (insn
, 21, 11);
4012 int vra
= PPC_FIELD (insn
, 11, 5);
4016 case 32: /* Vector Multiply-High-Add Signed Halfword Saturate */
4017 case 33: /* Vector Multiply-High-Round-Add Signed Halfword Saturate */
4018 case 39: /* Vector Multiply-Sum Unsigned Halfword Saturate */
4019 case 41: /* Vector Multiply-Sum Signed Halfword Saturate */
4020 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
4022 case 42: /* Vector Select */
4023 case 43: /* Vector Permute */
4024 case 59: /* Vector Permute Right-indexed */
4025 case 44: /* Vector Shift Left Double by Octet Immediate */
4026 case 45: /* Vector Permute and Exclusive-OR */
4027 case 60: /* Vector Add Extended Unsigned Quadword Modulo */
4028 case 61: /* Vector Add Extended & write Carry Unsigned Quadword */
4029 case 62: /* Vector Subtract Extended Unsigned Quadword Modulo */
4030 case 63: /* Vector Subtract Extended & write Carry Unsigned Quadword */
4031 case 34: /* Vector Multiply-Low-Add Unsigned Halfword Modulo */
4032 case 35: /* Vector Multiply-Sum Unsigned Doubleword Modulo */
4033 case 36: /* Vector Multiply-Sum Unsigned Byte Modulo */
4034 case 37: /* Vector Multiply-Sum Mixed Byte Modulo */
4035 case 38: /* Vector Multiply-Sum Unsigned Halfword Modulo */
4036 case 40: /* Vector Multiply-Sum Signed Halfword Modulo */
4037 case 46: /* Vector Multiply-Add Single-Precision */
4038 case 47: /* Vector Negative Multiply-Subtract Single-Precision */
4039 record_full_arch_list_add_reg (regcache
,
4040 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4043 case 48: /* Multiply-Add High Doubleword */
4044 case 49: /* Multiply-Add High Doubleword Unsigned */
4045 case 51: /* Multiply-Add Low Doubleword */
4046 record_full_arch_list_add_reg (regcache
,
4047 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4051 switch ((ext
& 0x1ff))
4054 if (vra
!= 0 /* Decimal Convert To Signed Quadword */
4055 && vra
!= 2 /* Decimal Convert From Signed Quadword */
4056 && vra
!= 4 /* Decimal Convert To Zoned */
4057 && vra
!= 5 /* Decimal Convert To National */
4058 && vra
!= 6 /* Decimal Convert From Zoned */
4059 && vra
!= 7 /* Decimal Convert From National */
4060 && vra
!= 31) /* Decimal Set Sign */
4063 /* 5.16 Decimal Integer Arithmetic Instructions */
4064 case 1: /* Decimal Add Modulo */
4065 case 65: /* Decimal Subtract Modulo */
4067 case 193: /* Decimal Shift */
4068 case 129: /* Decimal Unsigned Shift */
4069 case 449: /* Decimal Shift and Round */
4071 case 257: /* Decimal Truncate */
4072 case 321: /* Decimal Unsigned Truncate */
4074 /* Bit-21 should be set. */
4075 if (!PPC_BIT (insn
, 21))
4078 record_full_arch_list_add_reg (regcache
,
4079 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4080 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4084 /* Bit-21 is used for RC */
4085 switch (ext
& 0x3ff)
4087 case 6: /* Vector Compare Equal To Unsigned Byte */
4088 case 70: /* Vector Compare Equal To Unsigned Halfword */
4089 case 134: /* Vector Compare Equal To Unsigned Word */
4090 case 199: /* Vector Compare Equal To Unsigned Doubleword */
4091 case 774: /* Vector Compare Greater Than Signed Byte */
4092 case 838: /* Vector Compare Greater Than Signed Halfword */
4093 case 902: /* Vector Compare Greater Than Signed Word */
4094 case 967: /* Vector Compare Greater Than Signed Doubleword */
4095 case 518: /* Vector Compare Greater Than Unsigned Byte */
4096 case 646: /* Vector Compare Greater Than Unsigned Word */
4097 case 582: /* Vector Compare Greater Than Unsigned Halfword */
4098 case 711: /* Vector Compare Greater Than Unsigned Doubleword */
4099 case 966: /* Vector Compare Bounds Single-Precision */
4100 case 198: /* Vector Compare Equal To Single-Precision */
4101 case 454: /* Vector Compare Greater Than or Equal To Single-Precision */
4102 case 710: /* Vector Compare Greater Than Single-Precision */
4103 case 7: /* Vector Compare Not Equal Byte */
4104 case 71: /* Vector Compare Not Equal Halfword */
4105 case 135: /* Vector Compare Not Equal Word */
4106 case 263: /* Vector Compare Not Equal or Zero Byte */
4107 case 327: /* Vector Compare Not Equal or Zero Halfword */
4108 case 391: /* Vector Compare Not Equal or Zero Word */
4110 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4111 record_full_arch_list_add_reg (regcache
,
4112 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4120 case 0: /* Vector Count Leading Zero Least-Significant Bits
4122 case 1: /* Vector Count Trailing Zero Least-Significant Bits
4124 record_full_arch_list_add_reg (regcache
,
4125 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4128 case 6: /* Vector Negate Word */
4129 case 7: /* Vector Negate Doubleword */
4130 case 8: /* Vector Parity Byte Word */
4131 case 9: /* Vector Parity Byte Doubleword */
4132 case 10: /* Vector Parity Byte Quadword */
4133 case 16: /* Vector Extend Sign Byte To Word */
4134 case 17: /* Vector Extend Sign Halfword To Word */
4135 case 24: /* Vector Extend Sign Byte To Doubleword */
4136 case 25: /* Vector Extend Sign Halfword To Doubleword */
4137 case 26: /* Vector Extend Sign Word To Doubleword */
4138 case 28: /* Vector Count Trailing Zeros Byte */
4139 case 29: /* Vector Count Trailing Zeros Halfword */
4140 case 30: /* Vector Count Trailing Zeros Word */
4141 case 31: /* Vector Count Trailing Zeros Doubleword */
4142 record_full_arch_list_add_reg (regcache
,
4143 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4150 case 142: /* Vector Pack Unsigned Halfword Unsigned Saturate */
4151 case 206: /* Vector Pack Unsigned Word Unsigned Saturate */
4152 case 270: /* Vector Pack Signed Halfword Unsigned Saturate */
4153 case 334: /* Vector Pack Signed Word Unsigned Saturate */
4154 case 398: /* Vector Pack Signed Halfword Signed Saturate */
4155 case 462: /* Vector Pack Signed Word Signed Saturate */
4156 case 1230: /* Vector Pack Unsigned Doubleword Unsigned Saturate */
4157 case 1358: /* Vector Pack Signed Doubleword Unsigned Saturate */
4158 case 1486: /* Vector Pack Signed Doubleword Signed Saturate */
4159 case 512: /* Vector Add Unsigned Byte Saturate */
4160 case 576: /* Vector Add Unsigned Halfword Saturate */
4161 case 640: /* Vector Add Unsigned Word Saturate */
4162 case 768: /* Vector Add Signed Byte Saturate */
4163 case 832: /* Vector Add Signed Halfword Saturate */
4164 case 896: /* Vector Add Signed Word Saturate */
4165 case 1536: /* Vector Subtract Unsigned Byte Saturate */
4166 case 1600: /* Vector Subtract Unsigned Halfword Saturate */
4167 case 1664: /* Vector Subtract Unsigned Word Saturate */
4168 case 1792: /* Vector Subtract Signed Byte Saturate */
4169 case 1856: /* Vector Subtract Signed Halfword Saturate */
4170 case 1920: /* Vector Subtract Signed Word Saturate */
4172 case 1544: /* Vector Sum across Quarter Unsigned Byte Saturate */
4173 case 1800: /* Vector Sum across Quarter Signed Byte Saturate */
4174 case 1608: /* Vector Sum across Quarter Signed Halfword Saturate */
4175 case 1672: /* Vector Sum across Half Signed Word Saturate */
4176 case 1928: /* Vector Sum across Signed Word Saturate */
4177 case 970: /* Vector Convert To Signed Fixed-Point Word Saturate */
4178 case 906: /* Vector Convert To Unsigned Fixed-Point Word Saturate */
4179 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
4181 case 12: /* Vector Merge High Byte */
4182 case 14: /* Vector Pack Unsigned Halfword Unsigned Modulo */
4183 case 76: /* Vector Merge High Halfword */
4184 case 78: /* Vector Pack Unsigned Word Unsigned Modulo */
4185 case 140: /* Vector Merge High Word */
4186 case 268: /* Vector Merge Low Byte */
4187 case 332: /* Vector Merge Low Halfword */
4188 case 396: /* Vector Merge Low Word */
4189 case 526: /* Vector Unpack High Signed Byte */
4190 case 590: /* Vector Unpack High Signed Halfword */
4191 case 654: /* Vector Unpack Low Signed Byte */
4192 case 718: /* Vector Unpack Low Signed Halfword */
4193 case 782: /* Vector Pack Pixel */
4194 case 846: /* Vector Unpack High Pixel */
4195 case 974: /* Vector Unpack Low Pixel */
4196 case 1102: /* Vector Pack Unsigned Doubleword Unsigned Modulo */
4197 case 1614: /* Vector Unpack High Signed Word */
4198 case 1676: /* Vector Merge Odd Word */
4199 case 1742: /* Vector Unpack Low Signed Word */
4200 case 1932: /* Vector Merge Even Word */
4201 case 524: /* Vector Splat Byte */
4202 case 588: /* Vector Splat Halfword */
4203 case 652: /* Vector Splat Word */
4204 case 780: /* Vector Splat Immediate Signed Byte */
4205 case 844: /* Vector Splat Immediate Signed Halfword */
4206 case 908: /* Vector Splat Immediate Signed Word */
4207 case 452: /* Vector Shift Left */
4208 case 708: /* Vector Shift Right */
4209 case 1036: /* Vector Shift Left by Octet */
4210 case 1100: /* Vector Shift Right by Octet */
4211 case 0: /* Vector Add Unsigned Byte Modulo */
4212 case 64: /* Vector Add Unsigned Halfword Modulo */
4213 case 128: /* Vector Add Unsigned Word Modulo */
4214 case 192: /* Vector Add Unsigned Doubleword Modulo */
4215 case 256: /* Vector Add Unsigned Quadword Modulo */
4216 case 320: /* Vector Add & write Carry Unsigned Quadword */
4217 case 384: /* Vector Add and Write Carry-Out Unsigned Word */
4218 case 8: /* Vector Multiply Odd Unsigned Byte */
4219 case 72: /* Vector Multiply Odd Unsigned Halfword */
4220 case 136: /* Vector Multiply Odd Unsigned Word */
4221 case 264: /* Vector Multiply Odd Signed Byte */
4222 case 328: /* Vector Multiply Odd Signed Halfword */
4223 case 392: /* Vector Multiply Odd Signed Word */
4224 case 520: /* Vector Multiply Even Unsigned Byte */
4225 case 584: /* Vector Multiply Even Unsigned Halfword */
4226 case 648: /* Vector Multiply Even Unsigned Word */
4227 case 776: /* Vector Multiply Even Signed Byte */
4228 case 840: /* Vector Multiply Even Signed Halfword */
4229 case 904: /* Vector Multiply Even Signed Word */
4230 case 137: /* Vector Multiply Unsigned Word Modulo */
4231 case 1024: /* Vector Subtract Unsigned Byte Modulo */
4232 case 1088: /* Vector Subtract Unsigned Halfword Modulo */
4233 case 1152: /* Vector Subtract Unsigned Word Modulo */
4234 case 1216: /* Vector Subtract Unsigned Doubleword Modulo */
4235 case 1280: /* Vector Subtract Unsigned Quadword Modulo */
4236 case 1344: /* Vector Subtract & write Carry Unsigned Quadword */
4237 case 1408: /* Vector Subtract and Write Carry-Out Unsigned Word */
4238 case 1282: /* Vector Average Signed Byte */
4239 case 1346: /* Vector Average Signed Halfword */
4240 case 1410: /* Vector Average Signed Word */
4241 case 1026: /* Vector Average Unsigned Byte */
4242 case 1090: /* Vector Average Unsigned Halfword */
4243 case 1154: /* Vector Average Unsigned Word */
4244 case 258: /* Vector Maximum Signed Byte */
4245 case 322: /* Vector Maximum Signed Halfword */
4246 case 386: /* Vector Maximum Signed Word */
4247 case 450: /* Vector Maximum Signed Doubleword */
4248 case 2: /* Vector Maximum Unsigned Byte */
4249 case 66: /* Vector Maximum Unsigned Halfword */
4250 case 130: /* Vector Maximum Unsigned Word */
4251 case 194: /* Vector Maximum Unsigned Doubleword */
4252 case 770: /* Vector Minimum Signed Byte */
4253 case 834: /* Vector Minimum Signed Halfword */
4254 case 898: /* Vector Minimum Signed Word */
4255 case 962: /* Vector Minimum Signed Doubleword */
4256 case 514: /* Vector Minimum Unsigned Byte */
4257 case 578: /* Vector Minimum Unsigned Halfword */
4258 case 642: /* Vector Minimum Unsigned Word */
4259 case 706: /* Vector Minimum Unsigned Doubleword */
4260 case 1028: /* Vector Logical AND */
4261 case 1668: /* Vector Logical Equivalent */
4262 case 1092: /* Vector Logical AND with Complement */
4263 case 1412: /* Vector Logical NAND */
4264 case 1348: /* Vector Logical OR with Complement */
4265 case 1156: /* Vector Logical OR */
4266 case 1284: /* Vector Logical NOR */
4267 case 1220: /* Vector Logical XOR */
4268 case 4: /* Vector Rotate Left Byte */
4269 case 132: /* Vector Rotate Left Word VX-form */
4270 case 68: /* Vector Rotate Left Halfword */
4271 case 196: /* Vector Rotate Left Doubleword */
4272 case 260: /* Vector Shift Left Byte */
4273 case 388: /* Vector Shift Left Word */
4274 case 324: /* Vector Shift Left Halfword */
4275 case 1476: /* Vector Shift Left Doubleword */
4276 case 516: /* Vector Shift Right Byte */
4277 case 644: /* Vector Shift Right Word */
4278 case 580: /* Vector Shift Right Halfword */
4279 case 1732: /* Vector Shift Right Doubleword */
4280 case 772: /* Vector Shift Right Algebraic Byte */
4281 case 900: /* Vector Shift Right Algebraic Word */
4282 case 836: /* Vector Shift Right Algebraic Halfword */
4283 case 964: /* Vector Shift Right Algebraic Doubleword */
4284 case 10: /* Vector Add Single-Precision */
4285 case 74: /* Vector Subtract Single-Precision */
4286 case 1034: /* Vector Maximum Single-Precision */
4287 case 1098: /* Vector Minimum Single-Precision */
4288 case 842: /* Vector Convert From Signed Fixed-Point Word */
4289 case 778: /* Vector Convert From Unsigned Fixed-Point Word */
4290 case 714: /* Vector Round to Single-Precision Integer toward -Infinity */
4291 case 522: /* Vector Round to Single-Precision Integer Nearest */
4292 case 650: /* Vector Round to Single-Precision Integer toward +Infinity */
4293 case 586: /* Vector Round to Single-Precision Integer toward Zero */
4294 case 394: /* Vector 2 Raised to the Exponent Estimate Floating-Point */
4295 case 458: /* Vector Log Base 2 Estimate Floating-Point */
4296 case 266: /* Vector Reciprocal Estimate Single-Precision */
4297 case 330: /* Vector Reciprocal Square Root Estimate Single-Precision */
4298 case 1288: /* Vector AES Cipher */
4299 case 1289: /* Vector AES Cipher Last */
4300 case 1352: /* Vector AES Inverse Cipher */
4301 case 1353: /* Vector AES Inverse Cipher Last */
4302 case 1480: /* Vector AES SubBytes */
4303 case 1730: /* Vector SHA-512 Sigma Doubleword */
4304 case 1666: /* Vector SHA-256 Sigma Word */
4305 case 1032: /* Vector Polynomial Multiply-Sum Byte */
4306 case 1160: /* Vector Polynomial Multiply-Sum Word */
4307 case 1096: /* Vector Polynomial Multiply-Sum Halfword */
4308 case 1224: /* Vector Polynomial Multiply-Sum Doubleword */
4309 case 1292: /* Vector Gather Bits by Bytes by Doubleword */
4310 case 1794: /* Vector Count Leading Zeros Byte */
4311 case 1858: /* Vector Count Leading Zeros Halfword */
4312 case 1922: /* Vector Count Leading Zeros Word */
4313 case 1986: /* Vector Count Leading Zeros Doubleword */
4314 case 1795: /* Vector Population Count Byte */
4315 case 1859: /* Vector Population Count Halfword */
4316 case 1923: /* Vector Population Count Word */
4317 case 1987: /* Vector Population Count Doubleword */
4318 case 1356: /* Vector Bit Permute Quadword */
4319 case 1484: /* Vector Bit Permute Doubleword */
4320 case 513: /* Vector Multiply-by-10 Unsigned Quadword */
4321 case 1: /* Vector Multiply-by-10 & write Carry Unsigned
4323 case 577: /* Vector Multiply-by-10 Extended Unsigned Quadword */
4324 case 65: /* Vector Multiply-by-10 Extended & write Carry
4325 Unsigned Quadword */
4326 case 1027: /* Vector Absolute Difference Unsigned Byte */
4327 case 1091: /* Vector Absolute Difference Unsigned Halfword */
4328 case 1155: /* Vector Absolute Difference Unsigned Word */
4329 case 1796: /* Vector Shift Right Variable */
4330 case 1860: /* Vector Shift Left Variable */
4331 case 133: /* Vector Rotate Left Word then Mask Insert */
4332 case 197: /* Vector Rotate Left Doubleword then Mask Insert */
4333 case 389: /* Vector Rotate Left Word then AND with Mask */
4334 case 453: /* Vector Rotate Left Doubleword then AND with Mask */
4335 case 525: /* Vector Extract Unsigned Byte */
4336 case 589: /* Vector Extract Unsigned Halfword */
4337 case 653: /* Vector Extract Unsigned Word */
4338 case 717: /* Vector Extract Doubleword */
4339 case 781: /* Vector Insert Byte */
4340 case 845: /* Vector Insert Halfword */
4341 case 909: /* Vector Insert Word */
4342 case 973: /* Vector Insert Doubleword */
4343 record_full_arch_list_add_reg (regcache
,
4344 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4347 case 1549: /* Vector Extract Unsigned Byte Left-Indexed */
4348 case 1613: /* Vector Extract Unsigned Halfword Left-Indexed */
4349 case 1677: /* Vector Extract Unsigned Word Left-Indexed */
4350 case 1805: /* Vector Extract Unsigned Byte Right-Indexed */
4351 case 1869: /* Vector Extract Unsigned Halfword Right-Indexed */
4352 case 1933: /* Vector Extract Unsigned Word Right-Indexed */
4353 record_full_arch_list_add_reg (regcache
,
4354 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4357 case 1604: /* Move To Vector Status and Control Register */
4358 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
4360 case 1540: /* Move From Vector Status and Control Register */
4361 record_full_arch_list_add_reg (regcache
,
4362 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4364 case 833: /* Decimal Copy Sign */
4365 record_full_arch_list_add_reg (regcache
,
4366 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4367 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4371 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4372 "at %s, 4-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4376 /* Parse and record instructions of primary opcode-19 at ADDR.
4377 Return 0 if successful. */
4380 ppc_process_record_op19 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4381 CORE_ADDR addr
, uint32_t insn
)
4383 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4384 int ext
= PPC_EXTOP (insn
);
4386 switch (ext
& 0x01f)
4388 case 2: /* Add PC Immediate Shifted */
4389 record_full_arch_list_add_reg (regcache
,
4390 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4396 case 0: /* Move Condition Register Field */
4397 case 33: /* Condition Register NOR */
4398 case 129: /* Condition Register AND with Complement */
4399 case 193: /* Condition Register XOR */
4400 case 225: /* Condition Register NAND */
4401 case 257: /* Condition Register AND */
4402 case 289: /* Condition Register Equivalent */
4403 case 417: /* Condition Register OR with Complement */
4404 case 449: /* Condition Register OR */
4405 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4408 case 16: /* Branch Conditional */
4409 case 560: /* Branch Conditional to Branch Target Address Register */
4410 if ((PPC_BO (insn
) & 0x4) == 0)
4411 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
4413 case 528: /* Branch Conditional to Count Register */
4415 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
4418 case 150: /* Instruction Synchronize */
4423 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4424 "at %s, 19-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4428 /* Parse and record instructions of primary opcode-31 at ADDR.
4429 Return 0 if successful. */
4432 ppc_process_record_op31 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4433 CORE_ADDR addr
, uint32_t insn
)
4435 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4436 int ext
= PPC_EXTOP (insn
);
4438 CORE_ADDR at_dcsz
, ea
= 0;
4439 ULONGEST rb
, ra
, xer
;
4442 /* These instructions have OE bit. */
4443 switch (ext
& 0x1ff)
4445 /* These write RT and XER. Update CR if RC is set. */
4446 case 8: /* Subtract from carrying */
4447 case 10: /* Add carrying */
4448 case 136: /* Subtract from extended */
4449 case 138: /* Add extended */
4450 case 200: /* Subtract from zero extended */
4451 case 202: /* Add to zero extended */
4452 case 232: /* Subtract from minus one extended */
4453 case 234: /* Add to minus one extended */
4454 /* CA is always altered, but SO/OV are only altered when OE=1.
4455 In any case, XER is always altered. */
4456 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4458 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4459 record_full_arch_list_add_reg (regcache
,
4460 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4463 /* These write RT. Update CR if RC is set and update XER if OE is set. */
4464 case 40: /* Subtract from */
4465 case 104: /* Negate */
4466 case 233: /* Multiply low doubleword */
4467 case 235: /* Multiply low word */
4469 case 393: /* Divide Doubleword Extended Unsigned */
4470 case 395: /* Divide Word Extended Unsigned */
4471 case 425: /* Divide Doubleword Extended */
4472 case 427: /* Divide Word Extended */
4473 case 457: /* Divide Doubleword Unsigned */
4474 case 459: /* Divide Word Unsigned */
4475 case 489: /* Divide Doubleword */
4476 case 491: /* Divide Word */
4478 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4480 case 9: /* Multiply High Doubleword Unsigned */
4481 case 11: /* Multiply High Word Unsigned */
4482 case 73: /* Multiply High Doubleword */
4483 case 75: /* Multiply High Word */
4485 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4486 record_full_arch_list_add_reg (regcache
,
4487 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4491 if ((ext
& 0x1f) == 15)
4493 /* Integer Select. bit[16:20] is used for BC. */
4494 record_full_arch_list_add_reg (regcache
,
4495 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4499 if ((ext
& 0xff) == 170)
4501 /* Add Extended using alternate carry bits */
4502 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4503 record_full_arch_list_add_reg (regcache
,
4504 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4510 case 78: /* Determine Leftmost Zero Byte */
4512 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4513 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4514 record_full_arch_list_add_reg (regcache
,
4515 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4518 /* These only write RT. */
4519 case 19: /* Move from condition register */
4520 /* Move From One Condition Register Field */
4521 case 74: /* Add and Generate Sixes */
4522 case 74 | 0x200: /* Add and Generate Sixes (bit-21 dont-care) */
4523 case 302: /* Move From Branch History Rolling Buffer */
4524 case 339: /* Move From Special Purpose Register */
4525 case 371: /* Move From Time Base [Phased-Out] */
4526 case 309: /* Load Doubleword Monitored Indexed */
4527 case 128: /* Set Boolean */
4528 case 755: /* Deliver A Random Number */
4529 record_full_arch_list_add_reg (regcache
,
4530 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4533 /* These only write to RA. */
4534 case 51: /* Move From VSR Doubleword */
4535 case 115: /* Move From VSR Word and Zero */
4536 case 122: /* Population count bytes */
4537 case 378: /* Population count words */
4538 case 506: /* Population count doublewords */
4539 case 154: /* Parity Word */
4540 case 186: /* Parity Doubleword */
4541 case 252: /* Bit Permute Doubleword */
4542 case 282: /* Convert Declets To Binary Coded Decimal */
4543 case 314: /* Convert Binary Coded Decimal To Declets */
4544 case 508: /* Compare bytes */
4545 case 307: /* Move From VSR Lower Doubleword */
4546 record_full_arch_list_add_reg (regcache
,
4547 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4550 /* These write CR and optional RA. */
4551 case 792: /* Shift Right Algebraic Word */
4552 case 794: /* Shift Right Algebraic Doubleword */
4553 case 824: /* Shift Right Algebraic Word Immediate */
4554 case 826: /* Shift Right Algebraic Doubleword Immediate (413) */
4555 case 826 | 1: /* Shift Right Algebraic Doubleword Immediate (413) */
4556 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4557 record_full_arch_list_add_reg (regcache
,
4558 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4560 case 0: /* Compare */
4561 case 32: /* Compare logical */
4562 case 144: /* Move To Condition Register Fields */
4563 /* Move To One Condition Register Field */
4564 case 192: /* Compare Ranged Byte */
4565 case 224: /* Compare Equal Byte */
4566 case 576: /* Move XER to CR Extended */
4567 case 902: /* Paste (should always fail due to single-stepping and
4568 the memory location might not be accessible, so
4570 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4573 /* These write to RT. Update RA if 'update indexed.' */
4574 case 53: /* Load Doubleword with Update Indexed */
4575 case 119: /* Load Byte and Zero with Update Indexed */
4576 case 311: /* Load Halfword and Zero with Update Indexed */
4577 case 55: /* Load Word and Zero with Update Indexed */
4578 case 375: /* Load Halfword Algebraic with Update Indexed */
4579 case 373: /* Load Word Algebraic with Update Indexed */
4580 record_full_arch_list_add_reg (regcache
,
4581 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4583 case 21: /* Load Doubleword Indexed */
4584 case 52: /* Load Byte And Reserve Indexed */
4585 case 116: /* Load Halfword And Reserve Indexed */
4586 case 20: /* Load Word And Reserve Indexed */
4587 case 84: /* Load Doubleword And Reserve Indexed */
4588 case 87: /* Load Byte and Zero Indexed */
4589 case 279: /* Load Halfword and Zero Indexed */
4590 case 23: /* Load Word and Zero Indexed */
4591 case 343: /* Load Halfword Algebraic Indexed */
4592 case 341: /* Load Word Algebraic Indexed */
4593 case 790: /* Load Halfword Byte-Reverse Indexed */
4594 case 534: /* Load Word Byte-Reverse Indexed */
4595 case 532: /* Load Doubleword Byte-Reverse Indexed */
4596 case 582: /* Load Word Atomic */
4597 case 614: /* Load Doubleword Atomic */
4598 case 265: /* Modulo Unsigned Doubleword */
4599 case 777: /* Modulo Signed Doubleword */
4600 case 267: /* Modulo Unsigned Word */
4601 case 779: /* Modulo Signed Word */
4602 record_full_arch_list_add_reg (regcache
,
4603 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4606 case 597: /* Load String Word Immediate */
4607 case 533: /* Load String Word Indexed */
4616 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &xer
);
4617 nr
= PPC_XER_NB (xer
);
4622 /* If n=0, the contents of register RT are undefined. */
4626 for (i
= 0; i
< nr
; i
++)
4627 record_full_arch_list_add_reg (regcache
,
4628 tdep
->ppc_gp0_regnum
4629 + ((PPC_RT (insn
) + i
) & 0x1f));
4632 case 276: /* Load Quadword And Reserve Indexed */
4633 tmp
= tdep
->ppc_gp0_regnum
+ (PPC_RT (insn
) & ~1);
4634 record_full_arch_list_add_reg (regcache
, tmp
);
4635 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
4638 /* These write VRT. */
4639 case 6: /* Load Vector for Shift Left Indexed */
4640 case 38: /* Load Vector for Shift Right Indexed */
4641 case 7: /* Load Vector Element Byte Indexed */
4642 case 39: /* Load Vector Element Halfword Indexed */
4643 case 71: /* Load Vector Element Word Indexed */
4644 case 103: /* Load Vector Indexed */
4645 case 359: /* Load Vector Indexed LRU */
4646 record_full_arch_list_add_reg (regcache
,
4647 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4650 /* These write FRT. Update RA if 'update indexed.' */
4651 case 567: /* Load Floating-Point Single with Update Indexed */
4652 case 631: /* Load Floating-Point Double with Update Indexed */
4653 record_full_arch_list_add_reg (regcache
,
4654 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4656 case 535: /* Load Floating-Point Single Indexed */
4657 case 599: /* Load Floating-Point Double Indexed */
4658 case 855: /* Load Floating-Point as Integer Word Algebraic Indexed */
4659 case 887: /* Load Floating-Point as Integer Word and Zero Indexed */
4660 record_full_arch_list_add_reg (regcache
,
4661 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4664 case 791: /* Load Floating-Point Double Pair Indexed */
4665 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
4666 record_full_arch_list_add_reg (regcache
, tmp
);
4667 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
4670 case 179: /* Move To VSR Doubleword */
4671 case 211: /* Move To VSR Word Algebraic */
4672 case 243: /* Move To VSR Word and Zero */
4673 case 588: /* Load VSX Scalar Doubleword Indexed */
4674 case 524: /* Load VSX Scalar Single-Precision Indexed */
4675 case 76: /* Load VSX Scalar as Integer Word Algebraic Indexed */
4676 case 12: /* Load VSX Scalar as Integer Word and Zero Indexed */
4677 case 844: /* Load VSX Vector Doubleword*2 Indexed */
4678 case 332: /* Load VSX Vector Doubleword & Splat Indexed */
4679 case 780: /* Load VSX Vector Word*4 Indexed */
4680 case 268: /* Load VSX Vector Indexed */
4681 case 364: /* Load VSX Vector Word & Splat Indexed */
4682 case 812: /* Load VSX Vector Halfword*8 Indexed */
4683 case 876: /* Load VSX Vector Byte*16 Indexed */
4684 case 269: /* Load VSX Vector with Length */
4685 case 301: /* Load VSX Vector Left-justified with Length */
4686 case 781: /* Load VSX Scalar as Integer Byte & Zero Indexed */
4687 case 813: /* Load VSX Scalar as Integer Halfword & Zero Indexed */
4688 case 403: /* Move To VSR Word & Splat */
4689 case 435: /* Move To VSR Double Doubleword */
4690 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
4693 /* These write RA. Update CR if RC is set. */
4694 case 24: /* Shift Left Word */
4695 case 26: /* Count Leading Zeros Word */
4696 case 27: /* Shift Left Doubleword */
4698 case 58: /* Count Leading Zeros Doubleword */
4699 case 60: /* AND with Complement */
4701 case 284: /* Equivalent */
4703 case 476: /* NAND */
4704 case 412: /* OR with Complement */
4706 case 536: /* Shift Right Word */
4707 case 539: /* Shift Right Doubleword */
4708 case 922: /* Extend Sign Halfword */
4709 case 954: /* Extend Sign Byte */
4710 case 986: /* Extend Sign Word */
4711 case 538: /* Count Trailing Zeros Word */
4712 case 570: /* Count Trailing Zeros Doubleword */
4713 case 890: /* Extend-Sign Word and Shift Left Immediate (445) */
4714 case 890 | 1: /* Extend-Sign Word and Shift Left Immediate (445) */
4716 if (ext
== 444 && tdep
->ppc_ppr_regnum
>= 0
4717 && (PPC_RS (insn
) == PPC_RA (insn
))
4718 && (PPC_RA (insn
) == PPC_RB (insn
))
4721 /* or Rx,Rx,Rx alters PRI in PPR. */
4722 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ppr_regnum
);
4727 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4728 record_full_arch_list_add_reg (regcache
,
4729 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4733 case 181: /* Store Doubleword with Update Indexed */
4734 case 183: /* Store Word with Update Indexed */
4735 case 247: /* Store Byte with Update Indexed */
4736 case 439: /* Store Half Word with Update Indexed */
4737 case 695: /* Store Floating-Point Single with Update Indexed */
4738 case 759: /* Store Floating-Point Double with Update Indexed */
4739 record_full_arch_list_add_reg (regcache
,
4740 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4742 case 135: /* Store Vector Element Byte Indexed */
4743 case 167: /* Store Vector Element Halfword Indexed */
4744 case 199: /* Store Vector Element Word Indexed */
4745 case 231: /* Store Vector Indexed */
4746 case 487: /* Store Vector Indexed LRU */
4747 case 716: /* Store VSX Scalar Doubleword Indexed */
4748 case 140: /* Store VSX Scalar as Integer Word Indexed */
4749 case 652: /* Store VSX Scalar Single-Precision Indexed */
4750 case 972: /* Store VSX Vector Doubleword*2 Indexed */
4751 case 908: /* Store VSX Vector Word*4 Indexed */
4752 case 149: /* Store Doubleword Indexed */
4753 case 151: /* Store Word Indexed */
4754 case 215: /* Store Byte Indexed */
4755 case 407: /* Store Half Word Indexed */
4756 case 694: /* Store Byte Conditional Indexed */
4757 case 726: /* Store Halfword Conditional Indexed */
4758 case 150: /* Store Word Conditional Indexed */
4759 case 214: /* Store Doubleword Conditional Indexed */
4760 case 182: /* Store Quadword Conditional Indexed */
4761 case 662: /* Store Word Byte-Reverse Indexed */
4762 case 918: /* Store Halfword Byte-Reverse Indexed */
4763 case 660: /* Store Doubleword Byte-Reverse Indexed */
4764 case 663: /* Store Floating-Point Single Indexed */
4765 case 727: /* Store Floating-Point Double Indexed */
4766 case 919: /* Store Floating-Point Double Pair Indexed */
4767 case 983: /* Store Floating-Point as Integer Word Indexed */
4768 case 396: /* Store VSX Vector Indexed */
4769 case 940: /* Store VSX Vector Halfword*8 Indexed */
4770 case 1004: /* Store VSX Vector Byte*16 Indexed */
4771 case 909: /* Store VSX Scalar as Integer Byte Indexed */
4772 case 941: /* Store VSX Scalar as Integer Halfword Indexed */
4773 if (ext
== 694 || ext
== 726 || ext
== 150 || ext
== 214 || ext
== 182)
4774 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4777 if (PPC_RA (insn
) != 0)
4778 regcache_raw_read_unsigned (regcache
,
4779 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4780 regcache_raw_read_unsigned (regcache
,
4781 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
4786 case 183: /* Store Word with Update Indexed */
4787 case 199: /* Store Vector Element Word Indexed */
4788 case 140: /* Store VSX Scalar as Integer Word Indexed */
4789 case 652: /* Store VSX Scalar Single-Precision Indexed */
4790 case 151: /* Store Word Indexed */
4791 case 150: /* Store Word Conditional Indexed */
4792 case 662: /* Store Word Byte-Reverse Indexed */
4793 case 663: /* Store Floating-Point Single Indexed */
4794 case 695: /* Store Floating-Point Single with Update Indexed */
4795 case 983: /* Store Floating-Point as Integer Word Indexed */
4798 case 247: /* Store Byte with Update Indexed */
4799 case 135: /* Store Vector Element Byte Indexed */
4800 case 215: /* Store Byte Indexed */
4801 case 694: /* Store Byte Conditional Indexed */
4802 case 909: /* Store VSX Scalar as Integer Byte Indexed */
4805 case 439: /* Store Halfword with Update Indexed */
4806 case 167: /* Store Vector Element Halfword Indexed */
4807 case 407: /* Store Halfword Indexed */
4808 case 726: /* Store Halfword Conditional Indexed */
4809 case 918: /* Store Halfword Byte-Reverse Indexed */
4810 case 941: /* Store VSX Scalar as Integer Halfword Indexed */
4813 case 181: /* Store Doubleword with Update Indexed */
4814 case 716: /* Store VSX Scalar Doubleword Indexed */
4815 case 149: /* Store Doubleword Indexed */
4816 case 214: /* Store Doubleword Conditional Indexed */
4817 case 660: /* Store Doubleword Byte-Reverse Indexed */
4818 case 727: /* Store Floating-Point Double Indexed */
4819 case 759: /* Store Floating-Point Double with Update Indexed */
4822 case 972: /* Store VSX Vector Doubleword*2 Indexed */
4823 case 908: /* Store VSX Vector Word*4 Indexed */
4824 case 182: /* Store Quadword Conditional Indexed */
4825 case 231: /* Store Vector Indexed */
4826 case 487: /* Store Vector Indexed LRU */
4827 case 919: /* Store Floating-Point Double Pair Indexed */
4828 case 396: /* Store VSX Vector Indexed */
4829 case 940: /* Store VSX Vector Halfword*8 Indexed */
4830 case 1004: /* Store VSX Vector Byte*16 Indexed */
4837 /* Align address for Store Vector instructions. */
4840 case 167: /* Store Vector Element Halfword Indexed */
4841 addr
= addr
& ~0x1ULL
;
4844 case 199: /* Store Vector Element Word Indexed */
4845 addr
= addr
& ~0x3ULL
;
4848 case 231: /* Store Vector Indexed */
4849 case 487: /* Store Vector Indexed LRU */
4850 addr
= addr
& ~0xfULL
;
4854 record_full_arch_list_add_mem (addr
, size
);
4857 case 397: /* Store VSX Vector with Length */
4858 case 429: /* Store VSX Vector Left-justified with Length */
4860 if (PPC_RA (insn
) != 0)
4861 regcache_raw_read_unsigned (regcache
,
4862 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4864 regcache_raw_read_unsigned (regcache
,
4865 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
4866 /* Store up to 16 bytes. */
4867 nb
= (rb
& 0xff) > 16 ? 16 : (rb
& 0xff);
4869 record_full_arch_list_add_mem (ea
, nb
);
4872 case 710: /* Store Word Atomic */
4873 case 742: /* Store Doubleword Atomic */
4875 if (PPC_RA (insn
) != 0)
4876 regcache_raw_read_unsigned (regcache
,
4877 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4881 case 710: /* Store Word Atomic */
4884 case 742: /* Store Doubleword Atomic */
4890 record_full_arch_list_add_mem (ea
, size
);
4893 case 725: /* Store String Word Immediate */
4895 if (PPC_RA (insn
) != 0)
4896 regcache_raw_read_unsigned (regcache
,
4897 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4904 record_full_arch_list_add_mem (ea
, nb
);
4908 case 661: /* Store String Word Indexed */
4910 if (PPC_RA (insn
) != 0)
4911 regcache_raw_read_unsigned (regcache
,
4912 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4915 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &xer
);
4916 nb
= PPC_XER_NB (xer
);
4920 regcache_raw_read_unsigned (regcache
,
4921 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
),
4924 record_full_arch_list_add_mem (ea
, nb
);
4929 case 467: /* Move To Special Purpose Register */
4930 switch (PPC_SPR (insn
))
4933 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4936 if (tdep
->ppc_dscr_regnum
>= 0)
4937 record_full_arch_list_add_reg (regcache
, tdep
->ppc_dscr_regnum
);
4940 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
4943 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
4945 case 256: /* VRSAVE */
4946 record_full_arch_list_add_reg (regcache
, tdep
->ppc_vrsave_regnum
);
4949 if (tdep
->ppc_tar_regnum
>= 0)
4950 record_full_arch_list_add_reg (regcache
, tdep
->ppc_tar_regnum
);
4954 if (tdep
->ppc_ppr_regnum
>= 0)
4955 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ppr_regnum
);
4961 case 147: /* Move To Split Little Endian */
4962 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ps_regnum
);
4965 case 512: /* Move to Condition Register from XER */
4966 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4967 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4970 case 4: /* Trap Word */
4971 case 68: /* Trap Doubleword */
4972 case 430: /* Clear BHRB */
4973 case 598: /* Synchronize */
4974 case 62: /* Wait for Interrupt */
4976 case 22: /* Instruction Cache Block Touch */
4977 case 854: /* Enforce In-order Execution of I/O */
4978 case 246: /* Data Cache Block Touch for Store */
4979 case 54: /* Data Cache Block Store */
4980 case 86: /* Data Cache Block Flush */
4981 case 278: /* Data Cache Block Touch */
4982 case 758: /* Data Cache Block Allocate */
4983 case 982: /* Instruction Cache Block Invalidate */
4984 case 774: /* Copy */
4985 case 838: /* CP_Abort */
4988 case 654: /* Transaction Begin */
4989 case 686: /* Transaction End */
4990 case 750: /* Transaction Suspend or Resume */
4991 case 782: /* Transaction Abort Word Conditional */
4992 case 814: /* Transaction Abort Doubleword Conditional */
4993 case 846: /* Transaction Abort Word Conditional Immediate */
4994 case 878: /* Transaction Abort Doubleword Conditional Immediate */
4995 case 910: /* Transaction Abort */
4996 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ps_regnum
);
4998 case 718: /* Transaction Check */
4999 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5002 case 1014: /* Data Cache Block set to Zero */
5003 if (target_auxv_search (current_top_target (), AT_DCACHEBSIZE
, &at_dcsz
) <= 0
5005 at_dcsz
= 128; /* Assume 128-byte cache line size (POWER8) */
5008 if (PPC_RA (insn
) != 0)
5009 regcache_raw_read_unsigned (regcache
,
5010 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
5011 regcache_raw_read_unsigned (regcache
,
5012 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
5013 ea
= (ra
+ rb
) & ~((ULONGEST
) (at_dcsz
- 1));
5014 record_full_arch_list_add_mem (ea
, at_dcsz
);
5019 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5020 "at %s, 31-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5024 /* Parse and record instructions of primary opcode-59 at ADDR.
5025 Return 0 if successful. */
5028 ppc_process_record_op59 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5029 CORE_ADDR addr
, uint32_t insn
)
5031 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5032 int ext
= PPC_EXTOP (insn
);
5036 case 18: /* Floating Divide */
5037 case 20: /* Floating Subtract */
5038 case 21: /* Floating Add */
5039 case 22: /* Floating Square Root */
5040 case 24: /* Floating Reciprocal Estimate */
5041 case 25: /* Floating Multiply */
5042 case 26: /* Floating Reciprocal Square Root Estimate */
5043 case 28: /* Floating Multiply-Subtract */
5044 case 29: /* Floating Multiply-Add */
5045 case 30: /* Floating Negative Multiply-Subtract */
5046 case 31: /* Floating Negative Multiply-Add */
5047 record_full_arch_list_add_reg (regcache
,
5048 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5050 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5051 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5058 case 2: /* DFP Add */
5059 case 3: /* DFP Quantize */
5060 case 34: /* DFP Multiply */
5061 case 35: /* DFP Reround */
5062 case 67: /* DFP Quantize Immediate */
5063 case 99: /* DFP Round To FP Integer With Inexact */
5064 case 227: /* DFP Round To FP Integer Without Inexact */
5065 case 258: /* DFP Convert To DFP Long! */
5066 case 290: /* DFP Convert To Fixed */
5067 case 514: /* DFP Subtract */
5068 case 546: /* DFP Divide */
5069 case 770: /* DFP Round To DFP Short! */
5070 case 802: /* DFP Convert From Fixed */
5071 case 834: /* DFP Encode BCD To DPD */
5073 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5074 record_full_arch_list_add_reg (regcache
,
5075 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5076 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5079 case 130: /* DFP Compare Ordered */
5080 case 162: /* DFP Test Exponent */
5081 case 194: /* DFP Test Data Class */
5082 case 226: /* DFP Test Data Group */
5083 case 642: /* DFP Compare Unordered */
5084 case 674: /* DFP Test Significance */
5085 case 675: /* DFP Test Significance Immediate */
5086 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5087 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5090 case 66: /* DFP Shift Significand Left Immediate */
5091 case 98: /* DFP Shift Significand Right Immediate */
5092 case 322: /* DFP Decode DPD To BCD */
5093 case 354: /* DFP Extract Biased Exponent */
5094 case 866: /* DFP Insert Biased Exponent */
5095 record_full_arch_list_add_reg (regcache
,
5096 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5098 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5101 case 846: /* Floating Convert From Integer Doubleword Single */
5102 case 974: /* Floating Convert From Integer Doubleword Unsigned
5104 record_full_arch_list_add_reg (regcache
,
5105 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5107 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5108 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5113 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5114 "at %s, 59-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5118 /* Parse and record instructions of primary opcode-60 at ADDR.
5119 Return 0 if successful. */
5122 ppc_process_record_op60 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5123 CORE_ADDR addr
, uint32_t insn
)
5125 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5126 int ext
= PPC_EXTOP (insn
);
5130 case 0: /* VSX Scalar Add Single-Precision */
5131 case 32: /* VSX Scalar Add Double-Precision */
5132 case 24: /* VSX Scalar Divide Single-Precision */
5133 case 56: /* VSX Scalar Divide Double-Precision */
5134 case 176: /* VSX Scalar Copy Sign Double-Precision */
5135 case 33: /* VSX Scalar Multiply-Add Double-Precision */
5136 case 41: /* ditto */
5137 case 1: /* VSX Scalar Multiply-Add Single-Precision */
5139 case 160: /* VSX Scalar Maximum Double-Precision */
5140 case 168: /* VSX Scalar Minimum Double-Precision */
5141 case 49: /* VSX Scalar Multiply-Subtract Double-Precision */
5142 case 57: /* ditto */
5143 case 17: /* VSX Scalar Multiply-Subtract Single-Precision */
5144 case 25: /* ditto */
5145 case 48: /* VSX Scalar Multiply Double-Precision */
5146 case 16: /* VSX Scalar Multiply Single-Precision */
5147 case 161: /* VSX Scalar Negative Multiply-Add Double-Precision */
5148 case 169: /* ditto */
5149 case 129: /* VSX Scalar Negative Multiply-Add Single-Precision */
5150 case 137: /* ditto */
5151 case 177: /* VSX Scalar Negative Multiply-Subtract Double-Precision */
5152 case 185: /* ditto */
5153 case 145: /* VSX Scalar Negative Multiply-Subtract Single-Precision */
5154 case 153: /* ditto */
5155 case 40: /* VSX Scalar Subtract Double-Precision */
5156 case 8: /* VSX Scalar Subtract Single-Precision */
5157 case 96: /* VSX Vector Add Double-Precision */
5158 case 64: /* VSX Vector Add Single-Precision */
5159 case 120: /* VSX Vector Divide Double-Precision */
5160 case 88: /* VSX Vector Divide Single-Precision */
5161 case 97: /* VSX Vector Multiply-Add Double-Precision */
5162 case 105: /* ditto */
5163 case 65: /* VSX Vector Multiply-Add Single-Precision */
5164 case 73: /* ditto */
5165 case 224: /* VSX Vector Maximum Double-Precision */
5166 case 192: /* VSX Vector Maximum Single-Precision */
5167 case 232: /* VSX Vector Minimum Double-Precision */
5168 case 200: /* VSX Vector Minimum Single-Precision */
5169 case 113: /* VSX Vector Multiply-Subtract Double-Precision */
5170 case 121: /* ditto */
5171 case 81: /* VSX Vector Multiply-Subtract Single-Precision */
5172 case 89: /* ditto */
5173 case 112: /* VSX Vector Multiply Double-Precision */
5174 case 80: /* VSX Vector Multiply Single-Precision */
5175 case 225: /* VSX Vector Negative Multiply-Add Double-Precision */
5176 case 233: /* ditto */
5177 case 193: /* VSX Vector Negative Multiply-Add Single-Precision */
5178 case 201: /* ditto */
5179 case 241: /* VSX Vector Negative Multiply-Subtract Double-Precision */
5180 case 249: /* ditto */
5181 case 209: /* VSX Vector Negative Multiply-Subtract Single-Precision */
5182 case 217: /* ditto */
5183 case 104: /* VSX Vector Subtract Double-Precision */
5184 case 72: /* VSX Vector Subtract Single-Precision */
5185 case 128: /* VSX Scalar Maximum Type-C Double-Precision */
5186 case 136: /* VSX Scalar Minimum Type-C Double-Precision */
5187 case 144: /* VSX Scalar Maximum Type-J Double-Precision */
5188 case 152: /* VSX Scalar Minimum Type-J Double-Precision */
5189 case 3: /* VSX Scalar Compare Equal Double-Precision */
5190 case 11: /* VSX Scalar Compare Greater Than Double-Precision */
5191 case 19: /* VSX Scalar Compare Greater Than or Equal
5193 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5195 case 240: /* VSX Vector Copy Sign Double-Precision */
5196 case 208: /* VSX Vector Copy Sign Single-Precision */
5197 case 130: /* VSX Logical AND */
5198 case 138: /* VSX Logical AND with Complement */
5199 case 186: /* VSX Logical Equivalence */
5200 case 178: /* VSX Logical NAND */
5201 case 170: /* VSX Logical OR with Complement */
5202 case 162: /* VSX Logical NOR */
5203 case 146: /* VSX Logical OR */
5204 case 154: /* VSX Logical XOR */
5205 case 18: /* VSX Merge High Word */
5206 case 50: /* VSX Merge Low Word */
5207 case 10: /* VSX Permute Doubleword Immediate (DM=0) */
5208 case 10 | 0x20: /* VSX Permute Doubleword Immediate (DM=1) */
5209 case 10 | 0x40: /* VSX Permute Doubleword Immediate (DM=2) */
5210 case 10 | 0x60: /* VSX Permute Doubleword Immediate (DM=3) */
5211 case 2: /* VSX Shift Left Double by Word Immediate (SHW=0) */
5212 case 2 | 0x20: /* VSX Shift Left Double by Word Immediate (SHW=1) */
5213 case 2 | 0x40: /* VSX Shift Left Double by Word Immediate (SHW=2) */
5214 case 2 | 0x60: /* VSX Shift Left Double by Word Immediate (SHW=3) */
5215 case 216: /* VSX Vector Insert Exponent Single-Precision */
5216 case 248: /* VSX Vector Insert Exponent Double-Precision */
5217 case 26: /* VSX Vector Permute */
5218 case 58: /* VSX Vector Permute Right-indexed */
5219 case 213: /* VSX Vector Test Data Class Single-Precision (DC=0) */
5220 case 213 | 0x8: /* VSX Vector Test Data Class Single-Precision (DC=1) */
5221 case 245: /* VSX Vector Test Data Class Double-Precision (DC=0) */
5222 case 245 | 0x8: /* VSX Vector Test Data Class Double-Precision (DC=1) */
5223 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5226 case 61: /* VSX Scalar Test for software Divide Double-Precision */
5227 case 125: /* VSX Vector Test for software Divide Double-Precision */
5228 case 93: /* VSX Vector Test for software Divide Single-Precision */
5229 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5232 case 35: /* VSX Scalar Compare Unordered Double-Precision */
5233 case 43: /* VSX Scalar Compare Ordered Double-Precision */
5234 case 59: /* VSX Scalar Compare Exponents Double-Precision */
5235 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5236 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5240 switch ((ext
>> 2) & 0x7f) /* Mask out Rc-bit. */
5242 case 99: /* VSX Vector Compare Equal To Double-Precision */
5243 case 67: /* VSX Vector Compare Equal To Single-Precision */
5244 case 115: /* VSX Vector Compare Greater Than or
5245 Equal To Double-Precision */
5246 case 83: /* VSX Vector Compare Greater Than or
5247 Equal To Single-Precision */
5248 case 107: /* VSX Vector Compare Greater Than Double-Precision */
5249 case 75: /* VSX Vector Compare Greater Than Single-Precision */
5251 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5252 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5253 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5259 case 265: /* VSX Scalar round Double-Precision to
5260 Single-Precision and Convert to
5261 Single-Precision format */
5262 case 344: /* VSX Scalar truncate Double-Precision to
5263 Integer and Convert to Signed Integer
5264 Doubleword format with Saturate */
5265 case 88: /* VSX Scalar truncate Double-Precision to
5266 Integer and Convert to Signed Integer Word
5267 Format with Saturate */
5268 case 328: /* VSX Scalar truncate Double-Precision integer
5269 and Convert to Unsigned Integer Doubleword
5270 Format with Saturate */
5271 case 72: /* VSX Scalar truncate Double-Precision to
5272 Integer and Convert to Unsigned Integer Word
5273 Format with Saturate */
5274 case 329: /* VSX Scalar Convert Single-Precision to
5275 Double-Precision format */
5276 case 376: /* VSX Scalar Convert Signed Integer
5277 Doubleword to floating-point format and
5278 Round to Double-Precision format */
5279 case 312: /* VSX Scalar Convert Signed Integer
5280 Doubleword to floating-point format and
5281 round to Single-Precision */
5282 case 360: /* VSX Scalar Convert Unsigned Integer
5283 Doubleword to floating-point format and
5284 Round to Double-Precision format */
5285 case 296: /* VSX Scalar Convert Unsigned Integer
5286 Doubleword to floating-point format and
5287 Round to Single-Precision */
5288 case 73: /* VSX Scalar Round to Double-Precision Integer
5289 Using Round to Nearest Away */
5290 case 107: /* VSX Scalar Round to Double-Precision Integer
5291 Exact using Current rounding mode */
5292 case 121: /* VSX Scalar Round to Double-Precision Integer
5293 Using Round toward -Infinity */
5294 case 105: /* VSX Scalar Round to Double-Precision Integer
5295 Using Round toward +Infinity */
5296 case 89: /* VSX Scalar Round to Double-Precision Integer
5297 Using Round toward Zero */
5298 case 90: /* VSX Scalar Reciprocal Estimate Double-Precision */
5299 case 26: /* VSX Scalar Reciprocal Estimate Single-Precision */
5300 case 281: /* VSX Scalar Round to Single-Precision */
5301 case 74: /* VSX Scalar Reciprocal Square Root Estimate
5303 case 10: /* VSX Scalar Reciprocal Square Root Estimate
5305 case 75: /* VSX Scalar Square Root Double-Precision */
5306 case 11: /* VSX Scalar Square Root Single-Precision */
5307 case 393: /* VSX Vector round Double-Precision to
5308 Single-Precision and Convert to
5309 Single-Precision format */
5310 case 472: /* VSX Vector truncate Double-Precision to
5311 Integer and Convert to Signed Integer
5312 Doubleword format with Saturate */
5313 case 216: /* VSX Vector truncate Double-Precision to
5314 Integer and Convert to Signed Integer Word
5315 Format with Saturate */
5316 case 456: /* VSX Vector truncate Double-Precision to
5317 Integer and Convert to Unsigned Integer
5318 Doubleword format with Saturate */
5319 case 200: /* VSX Vector truncate Double-Precision to
5320 Integer and Convert to Unsigned Integer Word
5321 Format with Saturate */
5322 case 457: /* VSX Vector Convert Single-Precision to
5323 Double-Precision format */
5324 case 408: /* VSX Vector truncate Single-Precision to
5325 Integer and Convert to Signed Integer
5326 Doubleword format with Saturate */
5327 case 152: /* VSX Vector truncate Single-Precision to
5328 Integer and Convert to Signed Integer Word
5329 Format with Saturate */
5330 case 392: /* VSX Vector truncate Single-Precision to
5331 Integer and Convert to Unsigned Integer
5332 Doubleword format with Saturate */
5333 case 136: /* VSX Vector truncate Single-Precision to
5334 Integer and Convert to Unsigned Integer Word
5335 Format with Saturate */
5336 case 504: /* VSX Vector Convert and round Signed Integer
5337 Doubleword to Double-Precision format */
5338 case 440: /* VSX Vector Convert and round Signed Integer
5339 Doubleword to Single-Precision format */
5340 case 248: /* VSX Vector Convert Signed Integer Word to
5341 Double-Precision format */
5342 case 184: /* VSX Vector Convert and round Signed Integer
5343 Word to Single-Precision format */
5344 case 488: /* VSX Vector Convert and round Unsigned
5345 Integer Doubleword to Double-Precision format */
5346 case 424: /* VSX Vector Convert and round Unsigned
5347 Integer Doubleword to Single-Precision format */
5348 case 232: /* VSX Vector Convert and round Unsigned
5349 Integer Word to Double-Precision format */
5350 case 168: /* VSX Vector Convert and round Unsigned
5351 Integer Word to Single-Precision format */
5352 case 201: /* VSX Vector Round to Double-Precision
5353 Integer using round to Nearest Away */
5354 case 235: /* VSX Vector Round to Double-Precision
5355 Integer Exact using Current rounding mode */
5356 case 249: /* VSX Vector Round to Double-Precision
5357 Integer using round toward -Infinity */
5358 case 233: /* VSX Vector Round to Double-Precision
5359 Integer using round toward +Infinity */
5360 case 217: /* VSX Vector Round to Double-Precision
5361 Integer using round toward Zero */
5362 case 218: /* VSX Vector Reciprocal Estimate Double-Precision */
5363 case 154: /* VSX Vector Reciprocal Estimate Single-Precision */
5364 case 137: /* VSX Vector Round to Single-Precision Integer
5365 Using Round to Nearest Away */
5366 case 171: /* VSX Vector Round to Single-Precision Integer
5367 Exact Using Current rounding mode */
5368 case 185: /* VSX Vector Round to Single-Precision Integer
5369 Using Round toward -Infinity */
5370 case 169: /* VSX Vector Round to Single-Precision Integer
5371 Using Round toward +Infinity */
5372 case 153: /* VSX Vector Round to Single-Precision Integer
5373 Using round toward Zero */
5374 case 202: /* VSX Vector Reciprocal Square Root Estimate
5376 case 138: /* VSX Vector Reciprocal Square Root Estimate
5378 case 203: /* VSX Vector Square Root Double-Precision */
5379 case 139: /* VSX Vector Square Root Single-Precision */
5380 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5382 case 345: /* VSX Scalar Absolute Value Double-Precision */
5383 case 267: /* VSX Scalar Convert Scalar Single-Precision to
5384 Vector Single-Precision format Non-signalling */
5385 case 331: /* VSX Scalar Convert Single-Precision to
5386 Double-Precision format Non-signalling */
5387 case 361: /* VSX Scalar Negative Absolute Value Double-Precision */
5388 case 377: /* VSX Scalar Negate Double-Precision */
5389 case 473: /* VSX Vector Absolute Value Double-Precision */
5390 case 409: /* VSX Vector Absolute Value Single-Precision */
5391 case 489: /* VSX Vector Negative Absolute Value Double-Precision */
5392 case 425: /* VSX Vector Negative Absolute Value Single-Precision */
5393 case 505: /* VSX Vector Negate Double-Precision */
5394 case 441: /* VSX Vector Negate Single-Precision */
5395 case 164: /* VSX Splat Word */
5396 case 165: /* VSX Vector Extract Unsigned Word */
5397 case 181: /* VSX Vector Insert Word */
5398 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5401 case 298: /* VSX Scalar Test Data Class Single-Precision */
5402 case 362: /* VSX Scalar Test Data Class Double-Precision */
5403 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5405 case 106: /* VSX Scalar Test for software Square Root
5407 case 234: /* VSX Vector Test for software Square Root
5409 case 170: /* VSX Vector Test for software Square Root
5411 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5415 switch (PPC_FIELD (insn
, 11, 5))
5417 case 0: /* VSX Scalar Extract Exponent Double-Precision */
5418 case 1: /* VSX Scalar Extract Significand Double-Precision */
5419 record_full_arch_list_add_reg (regcache
,
5420 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5422 case 16: /* VSX Scalar Convert Half-Precision format to
5423 Double-Precision format */
5424 case 17: /* VSX Scalar round & Convert Double-Precision format
5425 to Half-Precision format */
5426 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5427 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5433 switch (PPC_FIELD (insn
, 11, 5))
5435 case 24: /* VSX Vector Convert Half-Precision format to
5436 Single-Precision format */
5437 case 25: /* VSX Vector round and Convert Single-Precision format
5438 to Half-Precision format */
5439 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5441 case 0: /* VSX Vector Extract Exponent Double-Precision */
5442 case 1: /* VSX Vector Extract Significand Double-Precision */
5443 case 7: /* VSX Vector Byte-Reverse Halfword */
5444 case 8: /* VSX Vector Extract Exponent Single-Precision */
5445 case 9: /* VSX Vector Extract Significand Single-Precision */
5446 case 15: /* VSX Vector Byte-Reverse Word */
5447 case 23: /* VSX Vector Byte-Reverse Doubleword */
5448 case 31: /* VSX Vector Byte-Reverse Quadword */
5449 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5457 case 360: /* VSX Vector Splat Immediate Byte */
5458 if (PPC_FIELD (insn
, 11, 2) == 0)
5460 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5464 case 918: /* VSX Scalar Insert Exponent Double-Precision */
5465 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5469 if (((ext
>> 3) & 0x3) == 3) /* VSX Select */
5471 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5475 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5476 "at %s, 60-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5480 /* Parse and record instructions of primary opcode-61 at ADDR.
5481 Return 0 if successful. */
5484 ppc_process_record_op61 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5485 CORE_ADDR addr
, uint32_t insn
)
5487 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5493 case 0: /* Store Floating-Point Double Pair */
5494 case 2: /* Store VSX Scalar Doubleword */
5495 case 3: /* Store VSX Scalar Single */
5496 if (PPC_RA (insn
) != 0)
5497 regcache_raw_read_unsigned (regcache
,
5498 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5500 ea
+= PPC_DS (insn
) << 2;
5503 case 0: /* Store Floating-Point Double Pair */
5506 case 2: /* Store VSX Scalar Doubleword */
5509 case 3: /* Store VSX Scalar Single */
5515 record_full_arch_list_add_mem (ea
, size
);
5521 case 1: /* Load VSX Vector */
5522 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5524 case 5: /* Store VSX Vector */
5525 if (PPC_RA (insn
) != 0)
5526 regcache_raw_read_unsigned (regcache
,
5527 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5529 ea
+= PPC_DQ (insn
) << 4;
5530 record_full_arch_list_add_mem (ea
, 16);
5534 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5535 "at %s.\n", insn
, paddress (gdbarch
, addr
));
5539 /* Parse and record instructions of primary opcode-63 at ADDR.
5540 Return 0 if successful. */
5543 ppc_process_record_op63 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5544 CORE_ADDR addr
, uint32_t insn
)
5546 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5547 int ext
= PPC_EXTOP (insn
);
5552 case 18: /* Floating Divide */
5553 case 20: /* Floating Subtract */
5554 case 21: /* Floating Add */
5555 case 22: /* Floating Square Root */
5556 case 24: /* Floating Reciprocal Estimate */
5557 case 25: /* Floating Multiply */
5558 case 26: /* Floating Reciprocal Square Root Estimate */
5559 case 28: /* Floating Multiply-Subtract */
5560 case 29: /* Floating Multiply-Add */
5561 case 30: /* Floating Negative Multiply-Subtract */
5562 case 31: /* Floating Negative Multiply-Add */
5563 record_full_arch_list_add_reg (regcache
,
5564 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5566 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5567 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5570 case 23: /* Floating Select */
5571 record_full_arch_list_add_reg (regcache
,
5572 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5574 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5580 case 5: /* VSX Scalar Round to Quad-Precision Integer */
5581 case 37: /* VSX Scalar Round Quad-Precision to Double-Extended
5583 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5584 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5590 case 2: /* DFP Add Quad */
5591 case 3: /* DFP Quantize Quad */
5592 case 34: /* DFP Multiply Quad */
5593 case 35: /* DFP Reround Quad */
5594 case 67: /* DFP Quantize Immediate Quad */
5595 case 99: /* DFP Round To FP Integer With Inexact Quad */
5596 case 227: /* DFP Round To FP Integer Without Inexact Quad */
5597 case 258: /* DFP Convert To DFP Extended Quad */
5598 case 514: /* DFP Subtract Quad */
5599 case 546: /* DFP Divide Quad */
5600 case 770: /* DFP Round To DFP Long Quad */
5601 case 802: /* DFP Convert From Fixed Quad */
5602 case 834: /* DFP Encode BCD To DPD Quad */
5604 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5605 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
5606 record_full_arch_list_add_reg (regcache
, tmp
);
5607 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5608 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5611 case 130: /* DFP Compare Ordered Quad */
5612 case 162: /* DFP Test Exponent Quad */
5613 case 194: /* DFP Test Data Class Quad */
5614 case 226: /* DFP Test Data Group Quad */
5615 case 642: /* DFP Compare Unordered Quad */
5616 case 674: /* DFP Test Significance Quad */
5617 case 675: /* DFP Test Significance Immediate Quad */
5618 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5619 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5622 case 66: /* DFP Shift Significand Left Immediate Quad */
5623 case 98: /* DFP Shift Significand Right Immediate Quad */
5624 case 322: /* DFP Decode DPD To BCD Quad */
5625 case 866: /* DFP Insert Biased Exponent Quad */
5626 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
5627 record_full_arch_list_add_reg (regcache
, tmp
);
5628 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5630 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5633 case 290: /* DFP Convert To Fixed Quad */
5634 record_full_arch_list_add_reg (regcache
,
5635 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5637 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5638 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5641 case 354: /* DFP Extract Biased Exponent Quad */
5642 record_full_arch_list_add_reg (regcache
,
5643 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5645 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5648 case 12: /* Floating Round to Single-Precision */
5649 case 14: /* Floating Convert To Integer Word */
5650 case 15: /* Floating Convert To Integer Word
5651 with round toward Zero */
5652 case 142: /* Floating Convert To Integer Word Unsigned */
5653 case 143: /* Floating Convert To Integer Word Unsigned
5654 with round toward Zero */
5655 case 392: /* Floating Round to Integer Nearest */
5656 case 424: /* Floating Round to Integer Toward Zero */
5657 case 456: /* Floating Round to Integer Plus */
5658 case 488: /* Floating Round to Integer Minus */
5659 case 814: /* Floating Convert To Integer Doubleword */
5660 case 815: /* Floating Convert To Integer Doubleword
5661 with round toward Zero */
5662 case 846: /* Floating Convert From Integer Doubleword */
5663 case 942: /* Floating Convert To Integer Doubleword Unsigned */
5664 case 943: /* Floating Convert To Integer Doubleword Unsigned
5665 with round toward Zero */
5666 case 974: /* Floating Convert From Integer Doubleword Unsigned */
5667 record_full_arch_list_add_reg (regcache
,
5668 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5670 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5671 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5675 switch (PPC_FIELD (insn
, 11, 5))
5677 case 1: /* Move From FPSCR & Clear Enables */
5678 case 20: /* Move From FPSCR Control & set DRN */
5679 case 21: /* Move From FPSCR Control & set DRN Immediate */
5680 case 22: /* Move From FPSCR Control & set RN */
5681 case 23: /* Move From FPSCR Control & set RN Immediate */
5682 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5684 case 0: /* Move From FPSCR */
5685 case 24: /* Move From FPSCR Lightweight */
5686 if (PPC_FIELD (insn
, 11, 5) == 0 && PPC_RC (insn
))
5687 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5688 record_full_arch_list_add_reg (regcache
,
5689 tdep
->ppc_fp0_regnum
5695 case 8: /* Floating Copy Sign */
5696 case 40: /* Floating Negate */
5697 case 72: /* Floating Move Register */
5698 case 136: /* Floating Negative Absolute Value */
5699 case 264: /* Floating Absolute Value */
5700 record_full_arch_list_add_reg (regcache
,
5701 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5703 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5706 case 838: /* Floating Merge Odd Word */
5707 case 966: /* Floating Merge Even Word */
5708 record_full_arch_list_add_reg (regcache
,
5709 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5712 case 38: /* Move To FPSCR Bit 1 */
5713 case 70: /* Move To FPSCR Bit 0 */
5714 case 134: /* Move To FPSCR Field Immediate */
5715 case 711: /* Move To FPSCR Fields */
5717 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5718 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5721 case 0: /* Floating Compare Unordered */
5722 case 32: /* Floating Compare Ordered */
5723 case 64: /* Move to Condition Register from FPSCR */
5724 case 132: /* VSX Scalar Compare Ordered Quad-Precision */
5725 case 164: /* VSX Scalar Compare Exponents Quad-Precision */
5726 case 644: /* VSX Scalar Compare Unordered Quad-Precision */
5727 case 708: /* VSX Scalar Test Data Class Quad-Precision */
5728 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5730 case 128: /* Floating Test for software Divide */
5731 case 160: /* Floating Test for software Square Root */
5732 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5735 case 4: /* VSX Scalar Add Quad-Precision */
5736 case 36: /* VSX Scalar Multiply Quad-Precision */
5737 case 388: /* VSX Scalar Multiply-Add Quad-Precision */
5738 case 420: /* VSX Scalar Multiply-Subtract Quad-Precision */
5739 case 452: /* VSX Scalar Negative Multiply-Add Quad-Precision */
5740 case 484: /* VSX Scalar Negative Multiply-Subtract
5742 case 516: /* VSX Scalar Subtract Quad-Precision */
5743 case 548: /* VSX Scalar Divide Quad-Precision */
5744 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5746 case 100: /* VSX Scalar Copy Sign Quad-Precision */
5747 case 868: /* VSX Scalar Insert Exponent Quad-Precision */
5748 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5752 switch (PPC_FIELD (insn
, 11, 5))
5754 case 27: /* VSX Scalar Square Root Quad-Precision */
5755 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5757 case 0: /* VSX Scalar Absolute Quad-Precision */
5758 case 2: /* VSX Scalar Extract Exponent Quad-Precision */
5759 case 8: /* VSX Scalar Negative Absolute Quad-Precision */
5760 case 16: /* VSX Scalar Negate Quad-Precision */
5761 case 18: /* VSX Scalar Extract Significand Quad-Precision */
5762 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5768 switch (PPC_FIELD (insn
, 11, 5))
5770 case 1: /* VSX Scalar truncate & Convert Quad-Precision format
5771 to Unsigned Word format */
5772 case 2: /* VSX Scalar Convert Unsigned Doubleword format to
5773 Quad-Precision format */
5774 case 9: /* VSX Scalar truncate & Convert Quad-Precision format
5775 to Signed Word format */
5776 case 10: /* VSX Scalar Convert Signed Doubleword format to
5777 Quad-Precision format */
5778 case 17: /* VSX Scalar truncate & Convert Quad-Precision format
5779 to Unsigned Doubleword format */
5780 case 20: /* VSX Scalar round & Convert Quad-Precision format to
5781 Double-Precision format */
5782 case 22: /* VSX Scalar Convert Double-Precision format to
5783 Quad-Precision format */
5784 case 25: /* VSX Scalar truncate & Convert Quad-Precision format
5785 to Signed Doubleword format */
5786 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5787 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5792 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5793 "at %s, 63-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5797 /* Parse the current instruction and record the values of the registers and
5798 memory that will be changed in current instruction to "record_arch_list".
5799 Return -1 if something wrong. */
5802 ppc_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5805 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5806 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5810 insn
= read_memory_unsigned_integer (addr
, 4, byte_order
);
5811 op6
= PPC_OP6 (insn
);
5815 case 2: /* Trap Doubleword Immediate */
5816 case 3: /* Trap Word Immediate */
5821 if (ppc_process_record_op4 (gdbarch
, regcache
, addr
, insn
) != 0)
5825 case 17: /* System call */
5826 if (PPC_LEV (insn
) != 0)
5829 if (tdep
->ppc_syscall_record
!= NULL
)
5831 if (tdep
->ppc_syscall_record (regcache
) != 0)
5836 printf_unfiltered (_("no syscall record support\n"));
5841 case 7: /* Multiply Low Immediate */
5842 record_full_arch_list_add_reg (regcache
,
5843 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5846 case 8: /* Subtract From Immediate Carrying */
5847 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5848 record_full_arch_list_add_reg (regcache
,
5849 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5852 case 10: /* Compare Logical Immediate */
5853 case 11: /* Compare Immediate */
5854 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5857 case 13: /* Add Immediate Carrying and Record */
5858 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5860 case 12: /* Add Immediate Carrying */
5861 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5863 case 14: /* Add Immediate */
5864 case 15: /* Add Immediate Shifted */
5865 record_full_arch_list_add_reg (regcache
,
5866 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5869 case 16: /* Branch Conditional */
5870 if ((PPC_BO (insn
) & 0x4) == 0)
5871 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
5873 case 18: /* Branch */
5875 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
5879 if (ppc_process_record_op19 (gdbarch
, regcache
, addr
, insn
) != 0)
5883 case 20: /* Rotate Left Word Immediate then Mask Insert */
5884 case 21: /* Rotate Left Word Immediate then AND with Mask */
5885 case 23: /* Rotate Left Word then AND with Mask */
5886 case 30: /* Rotate Left Doubleword Immediate then Clear Left */
5887 /* Rotate Left Doubleword Immediate then Clear Right */
5888 /* Rotate Left Doubleword Immediate then Clear */
5889 /* Rotate Left Doubleword then Clear Left */
5890 /* Rotate Left Doubleword then Clear Right */
5891 /* Rotate Left Doubleword Immediate then Mask Insert */
5893 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5894 record_full_arch_list_add_reg (regcache
,
5895 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5898 case 28: /* AND Immediate */
5899 case 29: /* AND Immediate Shifted */
5900 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5902 case 24: /* OR Immediate */
5903 case 25: /* OR Immediate Shifted */
5904 case 26: /* XOR Immediate */
5905 case 27: /* XOR Immediate Shifted */
5906 record_full_arch_list_add_reg (regcache
,
5907 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5911 if (ppc_process_record_op31 (gdbarch
, regcache
, addr
, insn
) != 0)
5915 case 33: /* Load Word and Zero with Update */
5916 case 35: /* Load Byte and Zero with Update */
5917 case 41: /* Load Halfword and Zero with Update */
5918 case 43: /* Load Halfword Algebraic with Update */
5919 record_full_arch_list_add_reg (regcache
,
5920 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5922 case 32: /* Load Word and Zero */
5923 case 34: /* Load Byte and Zero */
5924 case 40: /* Load Halfword and Zero */
5925 case 42: /* Load Halfword Algebraic */
5926 record_full_arch_list_add_reg (regcache
,
5927 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5930 case 46: /* Load Multiple Word */
5931 for (i
= PPC_RT (insn
); i
< 32; i
++)
5932 record_full_arch_list_add_reg (regcache
, tdep
->ppc_gp0_regnum
+ i
);
5935 case 56: /* Load Quadword */
5936 tmp
= tdep
->ppc_gp0_regnum
+ (PPC_RT (insn
) & ~1);
5937 record_full_arch_list_add_reg (regcache
, tmp
);
5938 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5941 case 49: /* Load Floating-Point Single with Update */
5942 case 51: /* Load Floating-Point Double with Update */
5943 record_full_arch_list_add_reg (regcache
,
5944 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5946 case 48: /* Load Floating-Point Single */
5947 case 50: /* Load Floating-Point Double */
5948 record_full_arch_list_add_reg (regcache
,
5949 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5952 case 47: /* Store Multiple Word */
5956 if (PPC_RA (insn
) != 0)
5957 regcache_raw_read_unsigned (regcache
,
5958 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5961 iaddr
+= PPC_D (insn
);
5962 record_full_arch_list_add_mem (iaddr
, 4 * (32 - PPC_RS (insn
)));
5966 case 37: /* Store Word with Update */
5967 case 39: /* Store Byte with Update */
5968 case 45: /* Store Halfword with Update */
5969 case 53: /* Store Floating-Point Single with Update */
5970 case 55: /* Store Floating-Point Double with Update */
5971 record_full_arch_list_add_reg (regcache
,
5972 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5974 case 36: /* Store Word */
5975 case 38: /* Store Byte */
5976 case 44: /* Store Halfword */
5977 case 52: /* Store Floating-Point Single */
5978 case 54: /* Store Floating-Point Double */
5983 if (PPC_RA (insn
) != 0)
5984 regcache_raw_read_unsigned (regcache
,
5985 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5987 iaddr
+= PPC_D (insn
);
5989 if (op6
== 36 || op6
== 37 || op6
== 52 || op6
== 53)
5991 else if (op6
== 54 || op6
== 55)
5993 else if (op6
== 44 || op6
== 45)
5995 else if (op6
== 38 || op6
== 39)
6000 record_full_arch_list_add_mem (iaddr
, size
);
6007 case 0: /* Load Floating-Point Double Pair */
6008 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_RT (insn
) & ~1);
6009 record_full_arch_list_add_reg (regcache
, tmp
);
6010 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
6012 case 2: /* Load VSX Scalar Doubleword */
6013 case 3: /* Load VSX Scalar Single */
6014 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
6021 case 58: /* Load Doubleword */
6022 /* Load Doubleword with Update */
6023 /* Load Word Algebraic */
6024 if (PPC_FIELD (insn
, 30, 2) > 2)
6027 record_full_arch_list_add_reg (regcache
,
6028 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
6029 if (PPC_BIT (insn
, 31))
6030 record_full_arch_list_add_reg (regcache
,
6031 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
6035 if (ppc_process_record_op59 (gdbarch
, regcache
, addr
, insn
) != 0)
6040 if (ppc_process_record_op60 (gdbarch
, regcache
, addr
, insn
) != 0)
6045 if (ppc_process_record_op61 (gdbarch
, regcache
, addr
, insn
) != 0)
6049 case 62: /* Store Doubleword */
6050 /* Store Doubleword with Update */
6051 /* Store Quadword with Update */
6055 int sub2
= PPC_FIELD (insn
, 30, 2);
6060 if (PPC_RA (insn
) != 0)
6061 regcache_raw_read_unsigned (regcache
,
6062 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
6065 size
= (sub2
== 2) ? 16 : 8;
6067 iaddr
+= PPC_DS (insn
) << 2;
6068 record_full_arch_list_add_mem (iaddr
, size
);
6070 if (op6
== 62 && sub2
== 1)
6071 record_full_arch_list_add_reg (regcache
,
6072 tdep
->ppc_gp0_regnum
+
6079 if (ppc_process_record_op63 (gdbarch
, regcache
, addr
, insn
) != 0)
6085 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
6086 "at %s, %d.\n", insn
, paddress (gdbarch
, addr
), op6
);
6090 if (record_full_arch_list_add_reg (regcache
, PPC_PC_REGNUM
))
6092 if (record_full_arch_list_add_end ())
6097 /* Initialize the current architecture based on INFO. If possible, re-use an
6098 architecture from ARCHES, which is a list of architectures already created
6099 during this debugging session.
6101 Called e.g. at program startup, when reading a core file, and when reading
6104 static struct gdbarch
*
6105 rs6000_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
6107 struct gdbarch
*gdbarch
;
6108 struct gdbarch_tdep
*tdep
;
6109 int wordsize
, from_xcoff_exec
, from_elf_exec
;
6110 enum bfd_architecture arch
;
6113 enum auto_boolean soft_float_flag
= powerpc_soft_float_global
;
6115 enum powerpc_long_double_abi long_double_abi
= POWERPC_LONG_DOUBLE_AUTO
;
6116 enum powerpc_vector_abi vector_abi
= powerpc_vector_abi_global
;
6117 enum powerpc_elf_abi elf_abi
= POWERPC_ELF_AUTO
;
6118 int have_fpu
= 0, have_spe
= 0, have_mq
= 0, have_altivec
= 0;
6119 int have_dfp
= 0, have_vsx
= 0, have_ppr
= 0, have_dscr
= 0;
6120 int have_tar
= 0, have_ebb
= 0, have_pmu
= 0, have_htm_spr
= 0;
6121 int have_htm_core
= 0, have_htm_fpu
= 0, have_htm_altivec
= 0;
6122 int have_htm_vsx
= 0, have_htm_ppr
= 0, have_htm_dscr
= 0;
6123 int have_htm_tar
= 0;
6124 int tdesc_wordsize
= -1;
6125 const struct target_desc
*tdesc
= info
.target_desc
;
6126 tdesc_arch_data_up tdesc_data
;
6127 int num_pseudoregs
= 0;
6130 from_xcoff_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
6131 bfd_get_flavour (info
.abfd
) == bfd_target_xcoff_flavour
;
6133 from_elf_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
6134 bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
;
6136 /* Check word size. If INFO is from a binary file, infer it from
6137 that, else choose a likely default. */
6138 if (from_xcoff_exec
)
6140 if (bfd_xcoff_is_xcoff64 (info
.abfd
))
6145 else if (from_elf_exec
)
6147 if (elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
6152 else if (tdesc_has_registers (tdesc
))
6156 if (info
.bfd_arch_info
!= NULL
&& info
.bfd_arch_info
->bits_per_word
!= 0)
6157 wordsize
= (info
.bfd_arch_info
->bits_per_word
6158 / info
.bfd_arch_info
->bits_per_byte
);
6163 /* Get the architecture and machine from the BFD. */
6164 arch
= info
.bfd_arch_info
->arch
;
6165 mach
= info
.bfd_arch_info
->mach
;
6167 /* For e500 executables, the apuinfo section is of help here. Such
6168 section contains the identifier and revision number of each
6169 Application-specific Processing Unit that is present on the
6170 chip. The content of the section is determined by the assembler
6171 which looks at each instruction and determines which unit (and
6172 which version of it) can execute it. Grovel through the section
6173 looking for relevant e500 APUs. */
6175 if (bfd_uses_spe_extensions (info
.abfd
))
6177 arch
= info
.bfd_arch_info
->arch
;
6178 mach
= bfd_mach_ppc_e500
;
6179 bfd_default_set_arch_mach (&abfd
, arch
, mach
);
6180 info
.bfd_arch_info
= bfd_get_arch_info (&abfd
);
6183 /* Find a default target description which describes our register
6184 layout, if we do not already have one. */
6185 if (! tdesc_has_registers (tdesc
))
6187 const struct ppc_variant
*v
;
6189 /* Choose variant. */
6190 v
= find_variant_by_arch (arch
, mach
);
6197 gdb_assert (tdesc_has_registers (tdesc
));
6199 /* Check any target description for validity. */
6200 if (tdesc_has_registers (tdesc
))
6202 static const char *const gprs
[] = {
6203 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6204 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
6205 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
6206 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
6208 const struct tdesc_feature
*feature
;
6210 static const char *const msr_names
[] = { "msr", "ps" };
6211 static const char *const cr_names
[] = { "cr", "cnd" };
6212 static const char *const ctr_names
[] = { "ctr", "cnt" };
6214 feature
= tdesc_find_feature (tdesc
,
6215 "org.gnu.gdb.power.core");
6216 if (feature
== NULL
)
6219 tdesc_data
= tdesc_data_alloc ();
6222 for (i
= 0; i
< ppc_num_gprs
; i
++)
6223 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6225 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6226 PPC_PC_REGNUM
, "pc");
6227 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6228 PPC_LR_REGNUM
, "lr");
6229 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6230 PPC_XER_REGNUM
, "xer");
6232 /* Allow alternate names for these registers, to accomodate GDB's
6234 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
.get (),
6235 PPC_MSR_REGNUM
, msr_names
);
6236 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
.get (),
6237 PPC_CR_REGNUM
, cr_names
);
6238 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
.get (),
6239 PPC_CTR_REGNUM
, ctr_names
);
6244 have_mq
= tdesc_numbered_register (feature
, tdesc_data
.get (),
6245 PPC_MQ_REGNUM
, "mq");
6247 tdesc_wordsize
= tdesc_register_bitsize (feature
, "pc") / 8;
6249 wordsize
= tdesc_wordsize
;
6251 feature
= tdesc_find_feature (tdesc
,
6252 "org.gnu.gdb.power.fpu");
6253 if (feature
!= NULL
)
6255 static const char *const fprs
[] = {
6256 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
6257 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
6258 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
6259 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
6262 for (i
= 0; i
< ppc_num_fprs
; i
++)
6263 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6264 PPC_F0_REGNUM
+ i
, fprs
[i
]);
6265 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6266 PPC_FPSCR_REGNUM
, "fpscr");
6272 /* The fpscr register was expanded in isa 2.05 to 64 bits
6273 along with the addition of the decimal floating point
6275 if (tdesc_register_bitsize (feature
, "fpscr") > 32)
6281 feature
= tdesc_find_feature (tdesc
,
6282 "org.gnu.gdb.power.altivec");
6283 if (feature
!= NULL
)
6285 static const char *const vector_regs
[] = {
6286 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
6287 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
6288 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
6289 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31"
6293 for (i
= 0; i
< ppc_num_gprs
; i
++)
6294 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6297 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6298 PPC_VSCR_REGNUM
, "vscr");
6299 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6300 PPC_VRSAVE_REGNUM
, "vrsave");
6302 if (have_spe
|| !valid_p
)
6309 /* Check for POWER7 VSX registers support. */
6310 feature
= tdesc_find_feature (tdesc
,
6311 "org.gnu.gdb.power.vsx");
6313 if (feature
!= NULL
)
6315 static const char *const vsx_regs
[] = {
6316 "vs0h", "vs1h", "vs2h", "vs3h", "vs4h", "vs5h",
6317 "vs6h", "vs7h", "vs8h", "vs9h", "vs10h", "vs11h",
6318 "vs12h", "vs13h", "vs14h", "vs15h", "vs16h", "vs17h",
6319 "vs18h", "vs19h", "vs20h", "vs21h", "vs22h", "vs23h",
6320 "vs24h", "vs25h", "vs26h", "vs27h", "vs28h", "vs29h",
6326 for (i
= 0; i
< ppc_num_vshrs
; i
++)
6327 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6328 PPC_VSR0_UPPER_REGNUM
+ i
,
6331 if (!valid_p
|| !have_fpu
|| !have_altivec
)
6339 /* On machines supporting the SPE APU, the general-purpose registers
6340 are 64 bits long. There are SIMD vector instructions to treat them
6341 as pairs of floats, but the rest of the instruction set treats them
6342 as 32-bit registers, and only operates on their lower halves.
6344 In the GDB regcache, we treat their high and low halves as separate
6345 registers. The low halves we present as the general-purpose
6346 registers, and then we have pseudo-registers that stitch together
6347 the upper and lower halves and present them as pseudo-registers.
6349 Thus, the target description is expected to supply the upper
6350 halves separately. */
6352 feature
= tdesc_find_feature (tdesc
,
6353 "org.gnu.gdb.power.spe");
6354 if (feature
!= NULL
)
6356 static const char *const upper_spe
[] = {
6357 "ev0h", "ev1h", "ev2h", "ev3h",
6358 "ev4h", "ev5h", "ev6h", "ev7h",
6359 "ev8h", "ev9h", "ev10h", "ev11h",
6360 "ev12h", "ev13h", "ev14h", "ev15h",
6361 "ev16h", "ev17h", "ev18h", "ev19h",
6362 "ev20h", "ev21h", "ev22h", "ev23h",
6363 "ev24h", "ev25h", "ev26h", "ev27h",
6364 "ev28h", "ev29h", "ev30h", "ev31h"
6368 for (i
= 0; i
< ppc_num_gprs
; i
++)
6369 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6370 PPC_SPE_UPPER_GP0_REGNUM
+ i
,
6372 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6373 PPC_SPE_ACC_REGNUM
, "acc");
6374 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6375 PPC_SPE_FSCR_REGNUM
, "spefscr");
6377 if (have_mq
|| have_fpu
|| !valid_p
)
6384 /* Program Priority Register. */
6385 feature
= tdesc_find_feature (tdesc
,
6386 "org.gnu.gdb.power.ppr");
6387 if (feature
!= NULL
)
6390 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6391 PPC_PPR_REGNUM
, "ppr");
6400 /* Data Stream Control Register. */
6401 feature
= tdesc_find_feature (tdesc
,
6402 "org.gnu.gdb.power.dscr");
6403 if (feature
!= NULL
)
6406 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6407 PPC_DSCR_REGNUM
, "dscr");
6416 /* Target Address Register. */
6417 feature
= tdesc_find_feature (tdesc
,
6418 "org.gnu.gdb.power.tar");
6419 if (feature
!= NULL
)
6422 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6423 PPC_TAR_REGNUM
, "tar");
6432 /* Event-based Branching Registers. */
6433 feature
= tdesc_find_feature (tdesc
,
6434 "org.gnu.gdb.power.ebb");
6435 if (feature
!= NULL
)
6437 static const char *const ebb_regs
[] = {
6438 "bescr", "ebbhr", "ebbrr"
6442 for (i
= 0; i
< ARRAY_SIZE (ebb_regs
); i
++)
6443 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6444 PPC_BESCR_REGNUM
+ i
,
6453 /* Subset of the ISA 2.07 Performance Monitor Registers provided
6455 feature
= tdesc_find_feature (tdesc
,
6456 "org.gnu.gdb.power.linux.pmu");
6457 if (feature
!= NULL
)
6461 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6464 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6467 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6470 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6473 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6484 /* Hardware Transactional Memory Registers. */
6485 feature
= tdesc_find_feature (tdesc
,
6486 "org.gnu.gdb.power.htm.spr");
6487 if (feature
!= NULL
)
6489 static const char *const tm_spr_regs
[] = {
6490 "tfhar", "texasr", "tfiar"
6494 for (i
= 0; i
< ARRAY_SIZE (tm_spr_regs
); i
++)
6495 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6496 PPC_TFHAR_REGNUM
+ i
,
6506 feature
= tdesc_find_feature (tdesc
,
6507 "org.gnu.gdb.power.htm.core");
6508 if (feature
!= NULL
)
6510 static const char *const cgprs
[] = {
6511 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
6512 "cr8", "cr9", "cr10", "cr11", "cr12", "cr13", "cr14",
6513 "cr15", "cr16", "cr17", "cr18", "cr19", "cr20", "cr21",
6514 "cr22", "cr23", "cr24", "cr25", "cr26", "cr27", "cr28",
6515 "cr29", "cr30", "cr31", "ccr", "cxer", "clr", "cctr"
6520 for (i
= 0; i
< ARRAY_SIZE (cgprs
); i
++)
6521 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6532 feature
= tdesc_find_feature (tdesc
,
6533 "org.gnu.gdb.power.htm.fpu");
6534 if (feature
!= NULL
)
6538 static const char *const cfprs
[] = {
6539 "cf0", "cf1", "cf2", "cf3", "cf4", "cf5", "cf6", "cf7",
6540 "cf8", "cf9", "cf10", "cf11", "cf12", "cf13", "cf14", "cf15",
6541 "cf16", "cf17", "cf18", "cf19", "cf20", "cf21", "cf22",
6542 "cf23", "cf24", "cf25", "cf26", "cf27", "cf28", "cf29",
6543 "cf30", "cf31", "cfpscr"
6546 for (i
= 0; i
< ARRAY_SIZE (cfprs
); i
++)
6547 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6558 feature
= tdesc_find_feature (tdesc
,
6559 "org.gnu.gdb.power.htm.altivec");
6560 if (feature
!= NULL
)
6564 static const char *const cvmx
[] = {
6565 "cvr0", "cvr1", "cvr2", "cvr3", "cvr4", "cvr5", "cvr6",
6566 "cvr7", "cvr8", "cvr9", "cvr10", "cvr11", "cvr12", "cvr13",
6567 "cvr14", "cvr15","cvr16", "cvr17", "cvr18", "cvr19", "cvr20",
6568 "cvr21", "cvr22", "cvr23", "cvr24", "cvr25", "cvr26",
6569 "cvr27", "cvr28", "cvr29", "cvr30", "cvr31", "cvscr",
6573 for (i
= 0; i
< ARRAY_SIZE (cvmx
); i
++)
6574 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6575 PPC_CVR0_REGNUM
+ i
,
6580 have_htm_altivec
= 1;
6583 have_htm_altivec
= 0;
6585 feature
= tdesc_find_feature (tdesc
,
6586 "org.gnu.gdb.power.htm.vsx");
6587 if (feature
!= NULL
)
6591 static const char *const cvsx
[] = {
6592 "cvs0h", "cvs1h", "cvs2h", "cvs3h", "cvs4h", "cvs5h",
6593 "cvs6h", "cvs7h", "cvs8h", "cvs9h", "cvs10h", "cvs11h",
6594 "cvs12h", "cvs13h", "cvs14h", "cvs15h", "cvs16h", "cvs17h",
6595 "cvs18h", "cvs19h", "cvs20h", "cvs21h", "cvs22h", "cvs23h",
6596 "cvs24h", "cvs25h", "cvs26h", "cvs27h", "cvs28h", "cvs29h",
6600 for (i
= 0; i
< ARRAY_SIZE (cvsx
); i
++)
6601 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
6602 (PPC_CVSR0_UPPER_REGNUM
6606 if (!valid_p
|| !have_htm_fpu
|| !have_htm_altivec
)
6613 feature
= tdesc_find_feature (tdesc
,
6614 "org.gnu.gdb.power.htm.ppr");
6615 if (feature
!= NULL
)
6617 valid_p
= tdesc_numbered_register (feature
, tdesc_data
.get (),
6618 PPC_CPPR_REGNUM
, "cppr");
6627 feature
= tdesc_find_feature (tdesc
,
6628 "org.gnu.gdb.power.htm.dscr");
6629 if (feature
!= NULL
)
6631 valid_p
= tdesc_numbered_register (feature
, tdesc_data
.get (),
6632 PPC_CDSCR_REGNUM
, "cdscr");
6641 feature
= tdesc_find_feature (tdesc
,
6642 "org.gnu.gdb.power.htm.tar");
6643 if (feature
!= NULL
)
6645 valid_p
= tdesc_numbered_register (feature
, tdesc_data
.get (),
6646 PPC_CTAR_REGNUM
, "ctar");
6656 /* If we have a 64-bit binary on a 32-bit target, complain. Also
6657 complain for a 32-bit binary on a 64-bit target; we do not yet
6658 support that. For instance, the 32-bit ABI routines expect
6661 As long as there isn't an explicit target description, we'll
6662 choose one based on the BFD architecture and get a word size
6663 matching the binary (probably powerpc:common or
6664 powerpc:common64). So there is only trouble if a 64-bit target
6665 supplies a 64-bit description while debugging a 32-bit
6667 if (tdesc_wordsize
!= -1 && tdesc_wordsize
!= wordsize
)
6673 switch (elf_elfheader (info
.abfd
)->e_flags
& EF_PPC64_ABI
)
6676 elf_abi
= POWERPC_ELF_V1
;
6679 elf_abi
= POWERPC_ELF_V2
;
6686 if (soft_float_flag
== AUTO_BOOLEAN_AUTO
&& from_elf_exec
)
6688 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6689 Tag_GNU_Power_ABI_FP
) & 3)
6692 soft_float_flag
= AUTO_BOOLEAN_FALSE
;
6695 soft_float_flag
= AUTO_BOOLEAN_TRUE
;
6702 if (long_double_abi
== POWERPC_LONG_DOUBLE_AUTO
&& from_elf_exec
)
6704 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6705 Tag_GNU_Power_ABI_FP
) >> 2)
6708 long_double_abi
= POWERPC_LONG_DOUBLE_IBM128
;
6711 long_double_abi
= POWERPC_LONG_DOUBLE_IEEE128
;
6718 if (vector_abi
== POWERPC_VEC_AUTO
&& from_elf_exec
)
6720 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6721 Tag_GNU_Power_ABI_Vector
))
6724 vector_abi
= POWERPC_VEC_GENERIC
;
6727 vector_abi
= POWERPC_VEC_ALTIVEC
;
6730 vector_abi
= POWERPC_VEC_SPE
;
6738 /* At this point, the only supported ELF-based 64-bit little-endian
6739 operating system is GNU/Linux, and this uses the ELFv2 ABI by
6740 default. All other supported ELF-based operating systems use the
6741 ELFv1 ABI by default. Therefore, if the ABI marker is missing,
6742 e.g. because we run a legacy binary, or have attached to a process
6743 and have not found any associated binary file, set the default
6744 according to this heuristic. */
6745 if (elf_abi
== POWERPC_ELF_AUTO
)
6747 if (wordsize
== 8 && info
.byte_order
== BFD_ENDIAN_LITTLE
)
6748 elf_abi
= POWERPC_ELF_V2
;
6750 elf_abi
= POWERPC_ELF_V1
;
6753 if (soft_float_flag
== AUTO_BOOLEAN_TRUE
)
6755 else if (soft_float_flag
== AUTO_BOOLEAN_FALSE
)
6758 soft_float
= !have_fpu
;
6760 /* If we have a hard float binary or setting but no floating point
6761 registers, downgrade to soft float anyway. We're still somewhat
6762 useful in this scenario. */
6763 if (!soft_float
&& !have_fpu
)
6766 /* Similarly for vector registers. */
6767 if (vector_abi
== POWERPC_VEC_ALTIVEC
&& !have_altivec
)
6768 vector_abi
= POWERPC_VEC_GENERIC
;
6770 if (vector_abi
== POWERPC_VEC_SPE
&& !have_spe
)
6771 vector_abi
= POWERPC_VEC_GENERIC
;
6773 if (vector_abi
== POWERPC_VEC_AUTO
)
6776 vector_abi
= POWERPC_VEC_ALTIVEC
;
6778 vector_abi
= POWERPC_VEC_SPE
;
6780 vector_abi
= POWERPC_VEC_GENERIC
;
6783 /* Do not limit the vector ABI based on available hardware, since we
6784 do not yet know what hardware we'll decide we have. Yuck! FIXME! */
6786 /* Find a candidate among extant architectures. */
6787 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
6789 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
6791 /* Word size in the various PowerPC bfd_arch_info structs isn't
6792 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
6793 separate word size check. */
6794 tdep
= gdbarch_tdep (arches
->gdbarch
);
6795 if (tdep
&& tdep
->elf_abi
!= elf_abi
)
6797 if (tdep
&& tdep
->soft_float
!= soft_float
)
6799 if (tdep
&& tdep
->long_double_abi
!= long_double_abi
)
6801 if (tdep
&& tdep
->vector_abi
!= vector_abi
)
6803 if (tdep
&& tdep
->wordsize
== wordsize
)
6804 return arches
->gdbarch
;
6807 /* None found, create a new architecture from INFO, whose bfd_arch_info
6808 validity depends on the source:
6809 - executable useless
6810 - rs6000_host_arch() good
6812 - "set arch" trust blindly
6813 - GDB startup useless but harmless */
6815 tdep
= XCNEW (struct gdbarch_tdep
);
6816 tdep
->wordsize
= wordsize
;
6817 tdep
->elf_abi
= elf_abi
;
6818 tdep
->soft_float
= soft_float
;
6819 tdep
->long_double_abi
= long_double_abi
;
6820 tdep
->vector_abi
= vector_abi
;
6822 gdbarch
= gdbarch_alloc (&info
, tdep
);
6824 tdep
->ppc_gp0_regnum
= PPC_R0_REGNUM
;
6825 tdep
->ppc_toc_regnum
= PPC_R0_REGNUM
+ 2;
6826 tdep
->ppc_ps_regnum
= PPC_MSR_REGNUM
;
6827 tdep
->ppc_cr_regnum
= PPC_CR_REGNUM
;
6828 tdep
->ppc_lr_regnum
= PPC_LR_REGNUM
;
6829 tdep
->ppc_ctr_regnum
= PPC_CTR_REGNUM
;
6830 tdep
->ppc_xer_regnum
= PPC_XER_REGNUM
;
6831 tdep
->ppc_mq_regnum
= have_mq
? PPC_MQ_REGNUM
: -1;
6833 tdep
->ppc_fp0_regnum
= have_fpu
? PPC_F0_REGNUM
: -1;
6834 tdep
->ppc_fpscr_regnum
= have_fpu
? PPC_FPSCR_REGNUM
: -1;
6835 tdep
->ppc_vsr0_upper_regnum
= have_vsx
? PPC_VSR0_UPPER_REGNUM
: -1;
6836 tdep
->ppc_vr0_regnum
= have_altivec
? PPC_VR0_REGNUM
: -1;
6837 tdep
->ppc_vrsave_regnum
= have_altivec
? PPC_VRSAVE_REGNUM
: -1;
6838 tdep
->ppc_ev0_upper_regnum
= have_spe
? PPC_SPE_UPPER_GP0_REGNUM
: -1;
6839 tdep
->ppc_acc_regnum
= have_spe
? PPC_SPE_ACC_REGNUM
: -1;
6840 tdep
->ppc_spefscr_regnum
= have_spe
? PPC_SPE_FSCR_REGNUM
: -1;
6841 tdep
->ppc_ppr_regnum
= have_ppr
? PPC_PPR_REGNUM
: -1;
6842 tdep
->ppc_dscr_regnum
= have_dscr
? PPC_DSCR_REGNUM
: -1;
6843 tdep
->ppc_tar_regnum
= have_tar
? PPC_TAR_REGNUM
: -1;
6844 tdep
->have_ebb
= have_ebb
;
6846 /* If additional pmu registers are added, care must be taken when
6847 setting new fields in the tdep below, to maintain compatibility
6848 with features that only provide some of the registers. Currently
6849 gdb access to the pmu registers is only supported in linux, and
6850 linux only provides a subset of the pmu registers defined in the
6853 tdep
->ppc_mmcr0_regnum
= have_pmu
? PPC_MMCR0_REGNUM
: -1;
6854 tdep
->ppc_mmcr2_regnum
= have_pmu
? PPC_MMCR2_REGNUM
: -1;
6855 tdep
->ppc_siar_regnum
= have_pmu
? PPC_SIAR_REGNUM
: -1;
6856 tdep
->ppc_sdar_regnum
= have_pmu
? PPC_SDAR_REGNUM
: -1;
6857 tdep
->ppc_sier_regnum
= have_pmu
? PPC_SIER_REGNUM
: -1;
6859 tdep
->have_htm_spr
= have_htm_spr
;
6860 tdep
->have_htm_core
= have_htm_core
;
6861 tdep
->have_htm_fpu
= have_htm_fpu
;
6862 tdep
->have_htm_altivec
= have_htm_altivec
;
6863 tdep
->have_htm_vsx
= have_htm_vsx
;
6864 tdep
->ppc_cppr_regnum
= have_htm_ppr
? PPC_CPPR_REGNUM
: -1;
6865 tdep
->ppc_cdscr_regnum
= have_htm_dscr
? PPC_CDSCR_REGNUM
: -1;
6866 tdep
->ppc_ctar_regnum
= have_htm_tar
? PPC_CTAR_REGNUM
: -1;
6868 set_gdbarch_pc_regnum (gdbarch
, PPC_PC_REGNUM
);
6869 set_gdbarch_sp_regnum (gdbarch
, PPC_R0_REGNUM
+ 1);
6870 set_gdbarch_fp0_regnum (gdbarch
, tdep
->ppc_fp0_regnum
);
6871 set_gdbarch_register_sim_regno (gdbarch
, rs6000_register_sim_regno
);
6873 /* The XML specification for PowerPC sensibly calls the MSR "msr".
6874 GDB traditionally called it "ps", though, so let GDB add an
6876 set_gdbarch_ps_regnum (gdbarch
, tdep
->ppc_ps_regnum
);
6879 set_gdbarch_return_value (gdbarch
, ppc64_sysv_abi_return_value
);
6881 set_gdbarch_return_value (gdbarch
, ppc_sysv_abi_return_value
);
6883 /* Set lr_frame_offset. */
6885 tdep
->lr_frame_offset
= 16;
6887 tdep
->lr_frame_offset
= 4;
6889 if (have_spe
|| have_dfp
|| have_altivec
6890 || have_vsx
|| have_htm_fpu
|| have_htm_vsx
)
6892 set_gdbarch_pseudo_register_read (gdbarch
, rs6000_pseudo_register_read
);
6893 set_gdbarch_pseudo_register_write (gdbarch
,
6894 rs6000_pseudo_register_write
);
6895 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
6896 rs6000_ax_pseudo_register_collect
);
6899 set_gdbarch_gen_return_address (gdbarch
, rs6000_gen_return_address
);
6901 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6903 set_gdbarch_num_regs (gdbarch
, PPC_NUM_REGS
);
6906 num_pseudoregs
+= 32;
6908 num_pseudoregs
+= 16;
6910 num_pseudoregs
+= 32;
6912 /* Include both VSX and Extended FP registers. */
6913 num_pseudoregs
+= 96;
6915 num_pseudoregs
+= 16;
6916 /* Include both checkpointed VSX and EFP registers. */
6918 num_pseudoregs
+= 64 + 32;
6920 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudoregs
);
6922 set_gdbarch_ptr_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
6923 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
6924 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
6925 set_gdbarch_long_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
6926 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
6927 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
6928 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
6929 set_gdbarch_long_double_bit (gdbarch
, 16 * TARGET_CHAR_BIT
);
6930 set_gdbarch_char_signed (gdbarch
, 0);
6932 set_gdbarch_frame_align (gdbarch
, rs6000_frame_align
);
6935 set_gdbarch_frame_red_zone_size (gdbarch
, 288);
6937 set_gdbarch_convert_register_p (gdbarch
, rs6000_convert_register_p
);
6938 set_gdbarch_register_to_value (gdbarch
, rs6000_register_to_value
);
6939 set_gdbarch_value_to_register (gdbarch
, rs6000_value_to_register
);
6941 set_gdbarch_stab_reg_to_regnum (gdbarch
, rs6000_stab_reg_to_regnum
);
6942 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, rs6000_dwarf2_reg_to_regnum
);
6945 set_gdbarch_push_dummy_call (gdbarch
, ppc_sysv_abi_push_dummy_call
);
6946 else if (wordsize
== 8)
6947 set_gdbarch_push_dummy_call (gdbarch
, ppc64_sysv_abi_push_dummy_call
);
6949 set_gdbarch_skip_prologue (gdbarch
, rs6000_skip_prologue
);
6950 set_gdbarch_stack_frame_destroyed_p (gdbarch
, rs6000_stack_frame_destroyed_p
);
6951 set_gdbarch_skip_main_prologue (gdbarch
, rs6000_skip_main_prologue
);
6953 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6955 set_gdbarch_breakpoint_kind_from_pc (gdbarch
,
6956 rs6000_breakpoint::kind_from_pc
);
6957 set_gdbarch_sw_breakpoint_from_kind (gdbarch
,
6958 rs6000_breakpoint::bp_from_kind
);
6960 /* The value of symbols of type N_SO and N_FUN maybe null when
6962 set_gdbarch_sofun_address_maybe_missing (gdbarch
, 1);
6964 /* Handles single stepping of atomic sequences. */
6965 set_gdbarch_software_single_step (gdbarch
, ppc_deal_with_atomic_sequence
);
6967 /* Not sure on this. FIXMEmgo */
6968 set_gdbarch_frame_args_skip (gdbarch
, 8);
6970 /* Helpers for function argument information. */
6971 set_gdbarch_fetch_pointer_argument (gdbarch
, rs6000_fetch_pointer_argument
);
6974 set_gdbarch_in_solib_return_trampoline
6975 (gdbarch
, rs6000_in_solib_return_trampoline
);
6976 set_gdbarch_skip_trampoline_code (gdbarch
, rs6000_skip_trampoline_code
);
6978 /* Hook in the DWARF CFI frame unwinder. */
6979 dwarf2_append_unwinders (gdbarch
);
6980 dwarf2_frame_set_adjust_regnum (gdbarch
, rs6000_adjust_frame_regnum
);
6982 /* Frame handling. */
6983 dwarf2_frame_set_init_reg (gdbarch
, ppc_dwarf2_frame_init_reg
);
6985 /* Setup displaced stepping. */
6986 set_gdbarch_displaced_step_copy_insn (gdbarch
,
6987 ppc_displaced_step_copy_insn
);
6988 set_gdbarch_displaced_step_hw_singlestep (gdbarch
,
6989 ppc_displaced_step_hw_singlestep
);
6990 set_gdbarch_displaced_step_fixup (gdbarch
, ppc_displaced_step_fixup
);
6991 set_gdbarch_displaced_step_location (gdbarch
,
6992 displaced_step_at_entry_point
);
6994 set_gdbarch_max_insn_length (gdbarch
, PPC_INSN_SIZE
);
6996 /* Hook in ABI-specific overrides, if they have been registered. */
6997 info
.target_desc
= tdesc
;
6998 info
.tdesc_data
= tdesc_data
.get ();
6999 gdbarch_init_osabi (info
, gdbarch
);
7003 case GDB_OSABI_LINUX
:
7004 case GDB_OSABI_NETBSD
:
7005 case GDB_OSABI_UNKNOWN
:
7006 frame_unwind_append_unwinder (gdbarch
, &rs6000_epilogue_frame_unwind
);
7007 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
7008 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
7011 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
7013 frame_unwind_append_unwinder (gdbarch
, &rs6000_epilogue_frame_unwind
);
7014 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
7015 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
7018 set_tdesc_pseudo_register_type (gdbarch
, rs6000_pseudo_register_type
);
7019 set_tdesc_pseudo_register_reggroup_p (gdbarch
,
7020 rs6000_pseudo_register_reggroup_p
);
7021 tdesc_use_registers (gdbarch
, tdesc
, std::move (tdesc_data
));
7023 /* Override the normal target description method to make the SPE upper
7024 halves anonymous. */
7025 set_gdbarch_register_name (gdbarch
, rs6000_register_name
);
7027 /* Choose register numbers for all supported pseudo-registers. */
7028 tdep
->ppc_ev0_regnum
= -1;
7029 tdep
->ppc_dl0_regnum
= -1;
7030 tdep
->ppc_v0_alias_regnum
= -1;
7031 tdep
->ppc_vsr0_regnum
= -1;
7032 tdep
->ppc_efpr0_regnum
= -1;
7033 tdep
->ppc_cdl0_regnum
= -1;
7034 tdep
->ppc_cvsr0_regnum
= -1;
7035 tdep
->ppc_cefpr0_regnum
= -1;
7037 cur_reg
= gdbarch_num_regs (gdbarch
);
7041 tdep
->ppc_ev0_regnum
= cur_reg
;
7046 tdep
->ppc_dl0_regnum
= cur_reg
;
7051 tdep
->ppc_v0_alias_regnum
= cur_reg
;
7056 tdep
->ppc_vsr0_regnum
= cur_reg
;
7058 tdep
->ppc_efpr0_regnum
= cur_reg
;
7063 tdep
->ppc_cdl0_regnum
= cur_reg
;
7068 tdep
->ppc_cvsr0_regnum
= cur_reg
;
7070 tdep
->ppc_cefpr0_regnum
= cur_reg
;
7074 gdb_assert (gdbarch_num_cooked_regs (gdbarch
) == cur_reg
);
7076 /* Register the ravenscar_arch_ops. */
7077 if (mach
== bfd_mach_ppc_e500
)
7078 register_e500_ravenscar_ops (gdbarch
);
7080 register_ppc_ravenscar_ops (gdbarch
);
7082 set_gdbarch_disassembler_options (gdbarch
, &powerpc_disassembler_options
);
7083 set_gdbarch_valid_disassembler_options (gdbarch
,
7084 disassembler_options_powerpc ());
7090 rs6000_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
7092 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
7097 /* FIXME: Dump gdbarch_tdep. */
7101 powerpc_set_soft_float (const char *args
, int from_tty
,
7102 struct cmd_list_element
*c
)
7104 struct gdbarch_info info
;
7106 /* Update the architecture. */
7107 gdbarch_info_init (&info
);
7108 if (!gdbarch_update_p (info
))
7109 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
7113 powerpc_set_vector_abi (const char *args
, int from_tty
,
7114 struct cmd_list_element
*c
)
7116 struct gdbarch_info info
;
7119 for (vector_abi
= POWERPC_VEC_AUTO
;
7120 vector_abi
!= POWERPC_VEC_LAST
;
7122 if (strcmp (powerpc_vector_abi_string
,
7123 powerpc_vector_strings
[vector_abi
]) == 0)
7125 powerpc_vector_abi_global
= (enum powerpc_vector_abi
) vector_abi
;
7129 if (vector_abi
== POWERPC_VEC_LAST
)
7130 internal_error (__FILE__
, __LINE__
, _("Invalid vector ABI accepted: %s."),
7131 powerpc_vector_abi_string
);
7133 /* Update the architecture. */
7134 gdbarch_info_init (&info
);
7135 if (!gdbarch_update_p (info
))
7136 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
7139 /* Show the current setting of the exact watchpoints flag. */
7142 show_powerpc_exact_watchpoints (struct ui_file
*file
, int from_tty
,
7143 struct cmd_list_element
*c
,
7146 fprintf_filtered (file
, _("Use of exact watchpoints is %s.\n"), value
);
7149 /* Read a PPC instruction from memory. */
7152 read_insn (struct frame_info
*frame
, CORE_ADDR pc
)
7154 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7155 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7157 return read_memory_unsigned_integer (pc
, 4, byte_order
);
7160 /* Return non-zero if the instructions at PC match the series
7161 described in PATTERN, or zero otherwise. PATTERN is an array of
7162 'struct ppc_insn_pattern' objects, terminated by an entry whose
7165 When the match is successful, fill INSNS[i] with what PATTERN[i]
7166 matched. If PATTERN[i] is optional, and the instruction wasn't
7167 present, set INSNS[i] to 0 (which is not a valid PPC instruction).
7168 INSNS should have as many elements as PATTERN, minus the terminator.
7169 Note that, if PATTERN contains optional instructions which aren't
7170 present in memory, then INSNS will have holes, so INSNS[i] isn't
7171 necessarily the i'th instruction in memory. */
7174 ppc_insns_match_pattern (struct frame_info
*frame
, CORE_ADDR pc
,
7175 const struct ppc_insn_pattern
*pattern
,
7176 unsigned int *insns
)
7181 for (i
= 0, insn
= 0; pattern
[i
].mask
; i
++)
7184 insn
= read_insn (frame
, pc
);
7186 if ((insn
& pattern
[i
].mask
) == pattern
[i
].data
)
7192 else if (!pattern
[i
].optional
)
7199 /* Return the 'd' field of the d-form instruction INSN, properly
7203 ppc_insn_d_field (unsigned int insn
)
7205 return ((((CORE_ADDR
) insn
& 0xffff) ^ 0x8000) - 0x8000);
7208 /* Return the 'ds' field of the ds-form instruction INSN, with the two
7209 zero bits concatenated at the right, and properly
7213 ppc_insn_ds_field (unsigned int insn
)
7215 return ((((CORE_ADDR
) insn
& 0xfffc) ^ 0x8000) - 0x8000);
7218 /* Initialization code. */
7220 void _initialize_rs6000_tdep ();
7222 _initialize_rs6000_tdep ()
7224 gdbarch_register (bfd_arch_rs6000
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
7225 gdbarch_register (bfd_arch_powerpc
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
7227 /* Initialize the standard target descriptions. */
7228 initialize_tdesc_powerpc_32 ();
7229 initialize_tdesc_powerpc_altivec32 ();
7230 initialize_tdesc_powerpc_vsx32 ();
7231 initialize_tdesc_powerpc_403 ();
7232 initialize_tdesc_powerpc_403gc ();
7233 initialize_tdesc_powerpc_405 ();
7234 initialize_tdesc_powerpc_505 ();
7235 initialize_tdesc_powerpc_601 ();
7236 initialize_tdesc_powerpc_602 ();
7237 initialize_tdesc_powerpc_603 ();
7238 initialize_tdesc_powerpc_604 ();
7239 initialize_tdesc_powerpc_64 ();
7240 initialize_tdesc_powerpc_altivec64 ();
7241 initialize_tdesc_powerpc_vsx64 ();
7242 initialize_tdesc_powerpc_7400 ();
7243 initialize_tdesc_powerpc_750 ();
7244 initialize_tdesc_powerpc_860 ();
7245 initialize_tdesc_powerpc_e500 ();
7246 initialize_tdesc_rs6000 ();
7248 /* Add root prefix command for all "set powerpc"/"show powerpc"
7250 add_basic_prefix_cmd ("powerpc", no_class
,
7251 _("Various PowerPC-specific commands."),
7252 &setpowerpccmdlist
, "set powerpc ", 0, &setlist
);
7254 add_show_prefix_cmd ("powerpc", no_class
,
7255 _("Various PowerPC-specific commands."),
7256 &showpowerpccmdlist
, "show powerpc ", 0, &showlist
);
7258 /* Add a command to allow the user to force the ABI. */
7259 add_setshow_auto_boolean_cmd ("soft-float", class_support
,
7260 &powerpc_soft_float_global
,
7261 _("Set whether to use a soft-float ABI."),
7262 _("Show whether to use a soft-float ABI."),
7264 powerpc_set_soft_float
, NULL
,
7265 &setpowerpccmdlist
, &showpowerpccmdlist
);
7267 add_setshow_enum_cmd ("vector-abi", class_support
, powerpc_vector_strings
,
7268 &powerpc_vector_abi_string
,
7269 _("Set the vector ABI."),
7270 _("Show the vector ABI."),
7271 NULL
, powerpc_set_vector_abi
, NULL
,
7272 &setpowerpccmdlist
, &showpowerpccmdlist
);
7274 add_setshow_boolean_cmd ("exact-watchpoints", class_support
,
7275 &target_exact_watchpoints
,
7277 Set whether to use just one debug register for watchpoints on scalars."),
7279 Show whether to use just one debug register for watchpoints on scalars."),
7281 If true, GDB will use only one debug register when watching a variable of\n\
7282 scalar type, thus assuming that the variable is accessed through the address\n\
7283 of its first byte."),
7284 NULL
, show_powerpc_exact_watchpoints
,
7285 &setpowerpccmdlist
, &showpowerpccmdlist
);