1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
30 #include "arch-utils.h"
35 #include "parser-defs.h"
38 #include "sim-regno.h"
39 #include "gdb/sim-ppc.h"
40 #include "reggroups.h"
41 #include "dwarf2-frame.h"
42 #include "target-descriptions.h"
43 #include "user-regs.h"
45 #include "libbfd.h" /* for bfd_default_set_arch_mach */
46 #include "coff/internal.h" /* for libcoff.h */
47 #include "libcoff.h" /* for xcoff_data */
48 #include "coff/xcoff.h"
54 #include "solib-svr4.h"
57 #include "gdb_assert.h"
60 #include "trad-frame.h"
61 #include "frame-unwind.h"
62 #include "frame-base.h"
64 #include "features/rs6000/powerpc-32.c"
65 #include "features/rs6000/powerpc-altivec32.c"
66 #include "features/rs6000/powerpc-403.c"
67 #include "features/rs6000/powerpc-403gc.c"
68 #include "features/rs6000/powerpc-505.c"
69 #include "features/rs6000/powerpc-601.c"
70 #include "features/rs6000/powerpc-602.c"
71 #include "features/rs6000/powerpc-603.c"
72 #include "features/rs6000/powerpc-604.c"
73 #include "features/rs6000/powerpc-64.c"
74 #include "features/rs6000/powerpc-altivec64.c"
75 #include "features/rs6000/powerpc-7400.c"
76 #include "features/rs6000/powerpc-750.c"
77 #include "features/rs6000/powerpc-860.c"
78 #include "features/rs6000/powerpc-e500.c"
79 #include "features/rs6000/rs6000.c"
81 /* Determine if regnum is an SPE pseudo-register. */
82 #define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \
83 && (regnum) >= (tdep)->ppc_ev0_regnum \
84 && (regnum) < (tdep)->ppc_ev0_regnum + 32)
86 /* Determine if regnum is a decimal float pseudo-register. */
87 #define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \
88 && (regnum) >= (tdep)->ppc_dl0_regnum \
89 && (regnum) < (tdep)->ppc_dl0_regnum + 16)
91 /* The list of available "set powerpc ..." and "show powerpc ..."
93 static struct cmd_list_element
*setpowerpccmdlist
= NULL
;
94 static struct cmd_list_element
*showpowerpccmdlist
= NULL
;
96 static enum auto_boolean powerpc_soft_float_global
= AUTO_BOOLEAN_AUTO
;
98 /* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */
99 static const char *powerpc_vector_strings
[] =
108 /* A variable that can be configured by the user. */
109 static enum powerpc_vector_abi powerpc_vector_abi_global
= POWERPC_VEC_AUTO
;
110 static const char *powerpc_vector_abi_string
= "auto";
112 /* To be used by skip_prologue. */
114 struct rs6000_framedata
116 int offset
; /* total size of frame --- the distance
117 by which we decrement sp to allocate
119 int saved_gpr
; /* smallest # of saved gpr */
120 int saved_fpr
; /* smallest # of saved fpr */
121 int saved_vr
; /* smallest # of saved vr */
122 int saved_ev
; /* smallest # of saved ev */
123 int alloca_reg
; /* alloca register number (frame ptr) */
124 char frameless
; /* true if frameless functions. */
125 char nosavedpc
; /* true if pc not saved. */
126 int gpr_offset
; /* offset of saved gprs from prev sp */
127 int fpr_offset
; /* offset of saved fprs from prev sp */
128 int vr_offset
; /* offset of saved vrs from prev sp */
129 int ev_offset
; /* offset of saved evs from prev sp */
130 int lr_offset
; /* offset of saved lr */
131 int cr_offset
; /* offset of saved cr */
132 int vrsave_offset
; /* offset of saved vrsave register */
136 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
138 altivec_register_p (struct gdbarch
*gdbarch
, int regno
)
140 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
141 if (tdep
->ppc_vr0_regnum
< 0 || tdep
->ppc_vrsave_regnum
< 0)
144 return (regno
>= tdep
->ppc_vr0_regnum
&& regno
<= tdep
->ppc_vrsave_regnum
);
148 /* Return true if REGNO is an SPE register, false otherwise. */
150 spe_register_p (struct gdbarch
*gdbarch
, int regno
)
152 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
154 /* Is it a reference to EV0 -- EV31, and do we have those? */
155 if (IS_SPE_PSEUDOREG (tdep
, regno
))
158 /* Is it a reference to one of the raw upper GPR halves? */
159 if (tdep
->ppc_ev0_upper_regnum
>= 0
160 && tdep
->ppc_ev0_upper_regnum
<= regno
161 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
164 /* Is it a reference to the 64-bit accumulator, and do we have that? */
165 if (tdep
->ppc_acc_regnum
>= 0
166 && tdep
->ppc_acc_regnum
== regno
)
169 /* Is it a reference to the SPE floating-point status and control register,
170 and do we have that? */
171 if (tdep
->ppc_spefscr_regnum
>= 0
172 && tdep
->ppc_spefscr_regnum
== regno
)
179 /* Return non-zero if the architecture described by GDBARCH has
180 floating-point registers (f0 --- f31 and fpscr). */
182 ppc_floating_point_unit_p (struct gdbarch
*gdbarch
)
184 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
186 return (tdep
->ppc_fp0_regnum
>= 0
187 && tdep
->ppc_fpscr_regnum
>= 0);
190 /* Return non-zero if the architecture described by GDBARCH has
191 Altivec registers (vr0 --- vr31, vrsave and vscr). */
193 ppc_altivec_support_p (struct gdbarch
*gdbarch
)
195 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
197 return (tdep
->ppc_vr0_regnum
>= 0
198 && tdep
->ppc_vrsave_regnum
>= 0);
201 /* Check that TABLE[GDB_REGNO] is not already initialized, and then
204 This is a helper function for init_sim_regno_table, constructing
205 the table mapping GDB register numbers to sim register numbers; we
206 initialize every element in that table to -1 before we start
209 set_sim_regno (int *table
, int gdb_regno
, int sim_regno
)
211 /* Make sure we don't try to assign any given GDB register a sim
212 register number more than once. */
213 gdb_assert (table
[gdb_regno
] == -1);
214 table
[gdb_regno
] = sim_regno
;
218 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
219 numbers to simulator register numbers, based on the values placed
220 in the ARCH->tdep->ppc_foo_regnum members. */
222 init_sim_regno_table (struct gdbarch
*arch
)
224 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
225 int total_regs
= gdbarch_num_regs (arch
);
226 int *sim_regno
= GDBARCH_OBSTACK_CALLOC (arch
, total_regs
, int);
228 static const char *const segment_regs
[] = {
229 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
230 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
233 /* Presume that all registers not explicitly mentioned below are
234 unavailable from the sim. */
235 for (i
= 0; i
< total_regs
; i
++)
238 /* General-purpose registers. */
239 for (i
= 0; i
< ppc_num_gprs
; i
++)
240 set_sim_regno (sim_regno
, tdep
->ppc_gp0_regnum
+ i
, sim_ppc_r0_regnum
+ i
);
242 /* Floating-point registers. */
243 if (tdep
->ppc_fp0_regnum
>= 0)
244 for (i
= 0; i
< ppc_num_fprs
; i
++)
245 set_sim_regno (sim_regno
,
246 tdep
->ppc_fp0_regnum
+ i
,
247 sim_ppc_f0_regnum
+ i
);
248 if (tdep
->ppc_fpscr_regnum
>= 0)
249 set_sim_regno (sim_regno
, tdep
->ppc_fpscr_regnum
, sim_ppc_fpscr_regnum
);
251 set_sim_regno (sim_regno
, gdbarch_pc_regnum (arch
), sim_ppc_pc_regnum
);
252 set_sim_regno (sim_regno
, tdep
->ppc_ps_regnum
, sim_ppc_ps_regnum
);
253 set_sim_regno (sim_regno
, tdep
->ppc_cr_regnum
, sim_ppc_cr_regnum
);
255 /* Segment registers. */
256 for (i
= 0; i
< ppc_num_srs
; i
++)
260 gdb_regno
= user_reg_map_name_to_regnum (arch
, segment_regs
[i
], -1);
262 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_sr0_regnum
+ i
);
265 /* Altivec registers. */
266 if (tdep
->ppc_vr0_regnum
>= 0)
268 for (i
= 0; i
< ppc_num_vrs
; i
++)
269 set_sim_regno (sim_regno
,
270 tdep
->ppc_vr0_regnum
+ i
,
271 sim_ppc_vr0_regnum
+ i
);
273 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
274 we can treat this more like the other cases. */
275 set_sim_regno (sim_regno
,
276 tdep
->ppc_vr0_regnum
+ ppc_num_vrs
,
277 sim_ppc_vscr_regnum
);
279 /* vsave is a special-purpose register, so the code below handles it. */
281 /* SPE APU (E500) registers. */
282 if (tdep
->ppc_ev0_upper_regnum
>= 0)
283 for (i
= 0; i
< ppc_num_gprs
; i
++)
284 set_sim_regno (sim_regno
,
285 tdep
->ppc_ev0_upper_regnum
+ i
,
286 sim_ppc_rh0_regnum
+ i
);
287 if (tdep
->ppc_acc_regnum
>= 0)
288 set_sim_regno (sim_regno
, tdep
->ppc_acc_regnum
, sim_ppc_acc_regnum
);
289 /* spefscr is a special-purpose register, so the code below handles it. */
292 /* Now handle all special-purpose registers. Verify that they
293 haven't mistakenly been assigned numbers by any of the above
295 for (i
= 0; i
< sim_ppc_num_sprs
; i
++)
297 const char *spr_name
= sim_spr_register_name (i
);
300 if (spr_name
!= NULL
)
301 gdb_regno
= user_reg_map_name_to_regnum (arch
, spr_name
, -1);
304 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_spr0_regnum
+ i
);
308 /* Drop the initialized array into place. */
309 tdep
->sim_regno
= sim_regno
;
313 /* Given a GDB register number REG, return the corresponding SIM
316 rs6000_register_sim_regno (struct gdbarch
*gdbarch
, int reg
)
318 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
321 if (tdep
->sim_regno
== NULL
)
322 init_sim_regno_table (gdbarch
);
325 && reg
<= gdbarch_num_regs (gdbarch
)
326 + gdbarch_num_pseudo_regs (gdbarch
));
327 sim_regno
= tdep
->sim_regno
[reg
];
332 return LEGACY_SIM_REGNO_IGNORE
;
337 /* Register set support functions. */
339 /* REGS + OFFSET contains register REGNUM in a field REGSIZE wide.
340 Write the register to REGCACHE. */
343 ppc_supply_reg (struct regcache
*regcache
, int regnum
,
344 const gdb_byte
*regs
, size_t offset
, int regsize
)
346 if (regnum
!= -1 && offset
!= -1)
350 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
351 int gdb_regsize
= register_size (gdbarch
, regnum
);
352 if (gdb_regsize
< regsize
353 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
354 offset
+= regsize
- gdb_regsize
;
356 regcache_raw_supply (regcache
, regnum
, regs
+ offset
);
360 /* Read register REGNUM from REGCACHE and store to REGS + OFFSET
361 in a field REGSIZE wide. Zero pad as necessary. */
364 ppc_collect_reg (const struct regcache
*regcache
, int regnum
,
365 gdb_byte
*regs
, size_t offset
, int regsize
)
367 if (regnum
!= -1 && offset
!= -1)
371 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
372 int gdb_regsize
= register_size (gdbarch
, regnum
);
373 if (gdb_regsize
< regsize
)
375 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
377 memset (regs
+ offset
, 0, regsize
- gdb_regsize
);
378 offset
+= regsize
- gdb_regsize
;
381 memset (regs
+ offset
+ regsize
- gdb_regsize
, 0,
382 regsize
- gdb_regsize
);
385 regcache_raw_collect (regcache
, regnum
, regs
+ offset
);
390 ppc_greg_offset (struct gdbarch
*gdbarch
,
391 struct gdbarch_tdep
*tdep
,
392 const struct ppc_reg_offsets
*offsets
,
396 *regsize
= offsets
->gpr_size
;
397 if (regnum
>= tdep
->ppc_gp0_regnum
398 && regnum
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
)
399 return (offsets
->r0_offset
400 + (regnum
- tdep
->ppc_gp0_regnum
) * offsets
->gpr_size
);
402 if (regnum
== gdbarch_pc_regnum (gdbarch
))
403 return offsets
->pc_offset
;
405 if (regnum
== tdep
->ppc_ps_regnum
)
406 return offsets
->ps_offset
;
408 if (regnum
== tdep
->ppc_lr_regnum
)
409 return offsets
->lr_offset
;
411 if (regnum
== tdep
->ppc_ctr_regnum
)
412 return offsets
->ctr_offset
;
414 *regsize
= offsets
->xr_size
;
415 if (regnum
== tdep
->ppc_cr_regnum
)
416 return offsets
->cr_offset
;
418 if (regnum
== tdep
->ppc_xer_regnum
)
419 return offsets
->xer_offset
;
421 if (regnum
== tdep
->ppc_mq_regnum
)
422 return offsets
->mq_offset
;
428 ppc_fpreg_offset (struct gdbarch_tdep
*tdep
,
429 const struct ppc_reg_offsets
*offsets
,
432 if (regnum
>= tdep
->ppc_fp0_regnum
433 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
)
434 return offsets
->f0_offset
+ (regnum
- tdep
->ppc_fp0_regnum
) * 8;
436 if (regnum
== tdep
->ppc_fpscr_regnum
)
437 return offsets
->fpscr_offset
;
443 ppc_vrreg_offset (struct gdbarch_tdep
*tdep
,
444 const struct ppc_reg_offsets
*offsets
,
447 if (regnum
>= tdep
->ppc_vr0_regnum
448 && regnum
< tdep
->ppc_vr0_regnum
+ ppc_num_vrs
)
449 return offsets
->vr0_offset
+ (regnum
- tdep
->ppc_vr0_regnum
) * 16;
451 if (regnum
== tdep
->ppc_vrsave_regnum
- 1)
452 return offsets
->vscr_offset
;
454 if (regnum
== tdep
->ppc_vrsave_regnum
)
455 return offsets
->vrsave_offset
;
460 /* Supply register REGNUM in the general-purpose register set REGSET
461 from the buffer specified by GREGS and LEN to register cache
462 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
465 ppc_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
466 int regnum
, const void *gregs
, size_t len
)
468 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
469 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
470 const struct ppc_reg_offsets
*offsets
= regset
->descr
;
477 int gpr_size
= offsets
->gpr_size
;
479 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
480 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
481 i
++, offset
+= gpr_size
)
482 ppc_supply_reg (regcache
, i
, gregs
, offset
, gpr_size
);
484 ppc_supply_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
485 gregs
, offsets
->pc_offset
, gpr_size
);
486 ppc_supply_reg (regcache
, tdep
->ppc_ps_regnum
,
487 gregs
, offsets
->ps_offset
, gpr_size
);
488 ppc_supply_reg (regcache
, tdep
->ppc_lr_regnum
,
489 gregs
, offsets
->lr_offset
, gpr_size
);
490 ppc_supply_reg (regcache
, tdep
->ppc_ctr_regnum
,
491 gregs
, offsets
->ctr_offset
, gpr_size
);
492 ppc_supply_reg (regcache
, tdep
->ppc_cr_regnum
,
493 gregs
, offsets
->cr_offset
, offsets
->xr_size
);
494 ppc_supply_reg (regcache
, tdep
->ppc_xer_regnum
,
495 gregs
, offsets
->xer_offset
, offsets
->xr_size
);
496 ppc_supply_reg (regcache
, tdep
->ppc_mq_regnum
,
497 gregs
, offsets
->mq_offset
, offsets
->xr_size
);
501 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
502 ppc_supply_reg (regcache
, regnum
, gregs
, offset
, regsize
);
505 /* Supply register REGNUM in the floating-point register set REGSET
506 from the buffer specified by FPREGS and LEN to register cache
507 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
510 ppc_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
511 int regnum
, const void *fpregs
, size_t len
)
513 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
514 struct gdbarch_tdep
*tdep
;
515 const struct ppc_reg_offsets
*offsets
;
518 if (!ppc_floating_point_unit_p (gdbarch
))
521 tdep
= gdbarch_tdep (gdbarch
);
522 offsets
= regset
->descr
;
527 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
528 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
530 ppc_supply_reg (regcache
, i
, fpregs
, offset
, 8);
532 ppc_supply_reg (regcache
, tdep
->ppc_fpscr_regnum
,
533 fpregs
, offsets
->fpscr_offset
, offsets
->fpscr_size
);
537 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
538 ppc_supply_reg (regcache
, regnum
, fpregs
, offset
,
539 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
542 /* Supply register REGNUM in the Altivec register set REGSET
543 from the buffer specified by VRREGS and LEN to register cache
544 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
547 ppc_supply_vrregset (const struct regset
*regset
, struct regcache
*regcache
,
548 int regnum
, const void *vrregs
, size_t len
)
550 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
551 struct gdbarch_tdep
*tdep
;
552 const struct ppc_reg_offsets
*offsets
;
555 if (!ppc_altivec_support_p (gdbarch
))
558 tdep
= gdbarch_tdep (gdbarch
);
559 offsets
= regset
->descr
;
564 for (i
= tdep
->ppc_vr0_regnum
, offset
= offsets
->vr0_offset
;
565 i
< tdep
->ppc_vr0_regnum
+ ppc_num_vrs
;
567 ppc_supply_reg (regcache
, i
, vrregs
, offset
, 16);
569 ppc_supply_reg (regcache
, (tdep
->ppc_vrsave_regnum
- 1),
570 vrregs
, offsets
->vscr_offset
, 4);
572 ppc_supply_reg (regcache
, tdep
->ppc_vrsave_regnum
,
573 vrregs
, offsets
->vrsave_offset
, 4);
577 offset
= ppc_vrreg_offset (tdep
, offsets
, regnum
);
578 if (regnum
!= tdep
->ppc_vrsave_regnum
579 && regnum
!= tdep
->ppc_vrsave_regnum
- 1)
580 ppc_supply_reg (regcache
, regnum
, vrregs
, offset
, 16);
582 ppc_supply_reg (regcache
, regnum
,
586 /* Collect register REGNUM in the general-purpose register set
587 REGSET from register cache REGCACHE into the buffer specified by
588 GREGS and LEN. If REGNUM is -1, do this for all registers in
592 ppc_collect_gregset (const struct regset
*regset
,
593 const struct regcache
*regcache
,
594 int regnum
, void *gregs
, size_t len
)
596 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
597 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
598 const struct ppc_reg_offsets
*offsets
= regset
->descr
;
605 int gpr_size
= offsets
->gpr_size
;
607 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
608 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
609 i
++, offset
+= gpr_size
)
610 ppc_collect_reg (regcache
, i
, gregs
, offset
, gpr_size
);
612 ppc_collect_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
613 gregs
, offsets
->pc_offset
, gpr_size
);
614 ppc_collect_reg (regcache
, tdep
->ppc_ps_regnum
,
615 gregs
, offsets
->ps_offset
, gpr_size
);
616 ppc_collect_reg (regcache
, tdep
->ppc_lr_regnum
,
617 gregs
, offsets
->lr_offset
, gpr_size
);
618 ppc_collect_reg (regcache
, tdep
->ppc_ctr_regnum
,
619 gregs
, offsets
->ctr_offset
, gpr_size
);
620 ppc_collect_reg (regcache
, tdep
->ppc_cr_regnum
,
621 gregs
, offsets
->cr_offset
, offsets
->xr_size
);
622 ppc_collect_reg (regcache
, tdep
->ppc_xer_regnum
,
623 gregs
, offsets
->xer_offset
, offsets
->xr_size
);
624 ppc_collect_reg (regcache
, tdep
->ppc_mq_regnum
,
625 gregs
, offsets
->mq_offset
, offsets
->xr_size
);
629 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
630 ppc_collect_reg (regcache
, regnum
, gregs
, offset
, regsize
);
633 /* Collect register REGNUM in the floating-point register set
634 REGSET from register cache REGCACHE into the buffer specified by
635 FPREGS and LEN. If REGNUM is -1, do this for all registers in
639 ppc_collect_fpregset (const struct regset
*regset
,
640 const struct regcache
*regcache
,
641 int regnum
, void *fpregs
, size_t len
)
643 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
644 struct gdbarch_tdep
*tdep
;
645 const struct ppc_reg_offsets
*offsets
;
648 if (!ppc_floating_point_unit_p (gdbarch
))
651 tdep
= gdbarch_tdep (gdbarch
);
652 offsets
= regset
->descr
;
657 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
658 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
660 ppc_collect_reg (regcache
, i
, fpregs
, offset
, 8);
662 ppc_collect_reg (regcache
, tdep
->ppc_fpscr_regnum
,
663 fpregs
, offsets
->fpscr_offset
, offsets
->fpscr_size
);
667 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
668 ppc_collect_reg (regcache
, regnum
, fpregs
, offset
,
669 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
672 /* Collect register REGNUM in the Altivec register set
673 REGSET from register cache REGCACHE into the buffer specified by
674 VRREGS and LEN. If REGNUM is -1, do this for all registers in
678 ppc_collect_vrregset (const struct regset
*regset
,
679 const struct regcache
*regcache
,
680 int regnum
, void *vrregs
, size_t len
)
682 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
683 struct gdbarch_tdep
*tdep
;
684 const struct ppc_reg_offsets
*offsets
;
687 if (!ppc_altivec_support_p (gdbarch
))
690 tdep
= gdbarch_tdep (gdbarch
);
691 offsets
= regset
->descr
;
696 for (i
= tdep
->ppc_vr0_regnum
, offset
= offsets
->vr0_offset
;
697 i
< tdep
->ppc_vr0_regnum
+ ppc_num_vrs
;
699 ppc_collect_reg (regcache
, i
, vrregs
, offset
, 16);
701 ppc_collect_reg (regcache
, (tdep
->ppc_vrsave_regnum
- 1),
702 vrregs
, offsets
->vscr_offset
, 4);
704 ppc_collect_reg (regcache
, tdep
->ppc_vrsave_regnum
,
705 vrregs
, offsets
->vrsave_offset
, 4);
709 offset
= ppc_vrreg_offset (tdep
, offsets
, regnum
);
710 if (regnum
!= tdep
->ppc_vrsave_regnum
711 && regnum
!= tdep
->ppc_vrsave_regnum
- 1)
712 ppc_collect_reg (regcache
, regnum
, vrregs
, offset
, 16);
714 ppc_collect_reg (regcache
, regnum
,
720 insn_changes_sp_or_jumps (unsigned long insn
)
722 int opcode
= (insn
>> 26) & 0x03f;
723 int sd
= (insn
>> 21) & 0x01f;
724 int a
= (insn
>> 16) & 0x01f;
725 int subcode
= (insn
>> 1) & 0x3ff;
727 /* Changes the stack pointer. */
729 /* NOTE: There are many ways to change the value of a given register.
730 The ways below are those used when the register is R1, the SP,
731 in a funtion's epilogue. */
733 if (opcode
== 31 && subcode
== 444 && a
== 1)
734 return 1; /* mr R1,Rn */
735 if (opcode
== 14 && sd
== 1)
736 return 1; /* addi R1,Rn,simm */
737 if (opcode
== 58 && sd
== 1)
738 return 1; /* ld R1,ds(Rn) */
740 /* Transfers control. */
746 if (opcode
== 19 && subcode
== 16)
748 if (opcode
== 19 && subcode
== 528)
749 return 1; /* bcctr */
754 /* Return true if we are in the function's epilogue, i.e. after the
755 instruction that destroyed the function's stack frame.
757 1) scan forward from the point of execution:
758 a) If you find an instruction that modifies the stack pointer
759 or transfers control (except a return), execution is not in
761 b) Stop scanning if you find a return instruction or reach the
762 end of the function or reach the hard limit for the size of
764 2) scan backward from the point of execution:
765 a) If you find an instruction that modifies the stack pointer,
766 execution *is* in an epilogue, return.
767 b) Stop scanning if you reach an instruction that transfers
768 control or the beginning of the function or reach the hard
769 limit for the size of an epilogue. */
772 rs6000_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
774 bfd_byte insn_buf
[PPC_INSN_SIZE
];
775 CORE_ADDR scan_pc
, func_start
, func_end
, epilogue_start
, epilogue_end
;
777 struct frame_info
*curfrm
;
779 /* Find the search limits based on function boundaries and hard limit. */
781 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
784 epilogue_start
= pc
- PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
785 if (epilogue_start
< func_start
) epilogue_start
= func_start
;
787 epilogue_end
= pc
+ PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
788 if (epilogue_end
> func_end
) epilogue_end
= func_end
;
790 curfrm
= get_current_frame ();
792 /* Scan forward until next 'blr'. */
794 for (scan_pc
= pc
; scan_pc
< epilogue_end
; scan_pc
+= PPC_INSN_SIZE
)
796 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
798 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
);
799 if (insn
== 0x4e800020)
801 if (insn_changes_sp_or_jumps (insn
))
805 /* Scan backward until adjustment to stack pointer (R1). */
807 for (scan_pc
= pc
- PPC_INSN_SIZE
;
808 scan_pc
>= epilogue_start
;
809 scan_pc
-= PPC_INSN_SIZE
)
811 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
813 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
);
814 if (insn_changes_sp_or_jumps (insn
))
821 /* Get the ith function argument for the current function. */
823 rs6000_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
826 return get_frame_register_unsigned (frame
, 3 + argi
);
829 /* Sequence of bytes for breakpoint instruction. */
831 const static unsigned char *
832 rs6000_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*bp_addr
,
835 static unsigned char big_breakpoint
[] = { 0x7d, 0x82, 0x10, 0x08 };
836 static unsigned char little_breakpoint
[] = { 0x08, 0x10, 0x82, 0x7d };
838 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
839 return big_breakpoint
;
841 return little_breakpoint
;
844 /* Instruction masks for displaced stepping. */
845 #define BRANCH_MASK 0xfc000000
846 #define BP_MASK 0xFC0007FE
847 #define B_INSN 0x48000000
848 #define BC_INSN 0x40000000
849 #define BXL_INSN 0x4c000000
850 #define BP_INSN 0x7C000008
852 /* Fix up the state of registers and memory after having single-stepped
853 a displaced instruction. */
855 ppc_displaced_step_fixup (struct gdbarch
*gdbarch
,
856 struct displaced_step_closure
*closure
,
857 CORE_ADDR from
, CORE_ADDR to
,
858 struct regcache
*regs
)
860 /* Since we use simple_displaced_step_copy_insn, our closure is a
861 copy of the instruction. */
862 ULONGEST insn
= extract_unsigned_integer ((gdb_byte
*) closure
,
865 /* Offset for non PC-relative instructions. */
866 LONGEST offset
= PPC_INSN_SIZE
;
868 opcode
= insn
& BRANCH_MASK
;
871 fprintf_unfiltered (gdb_stdlog
,
872 "displaced: (ppc) fixup (0x%s, 0x%s)\n",
873 paddr_nz (from
), paddr_nz (to
));
876 /* Handle PC-relative branch instructions. */
877 if (opcode
== B_INSN
|| opcode
== BC_INSN
|| opcode
== BXL_INSN
)
879 CORE_ADDR current_pc
;
881 /* Read the current PC value after the instruction has been executed
882 in a displaced location. Calculate the offset to be applied to the
883 original PC value before the displaced stepping. */
884 regcache_cooked_read_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
886 offset
= current_pc
- to
;
888 if (opcode
!= BXL_INSN
)
890 /* Check for AA bit indicating whether this is an absolute
891 addressing or PC-relative (1: absolute, 0: relative). */
894 /* PC-relative addressing is being used in the branch. */
898 "displaced: (ppc) branch instruction: 0x%s\n"
899 "displaced: (ppc) adjusted PC from 0x%s to 0x%s\n",
900 paddr_nz (insn
), paddr_nz (current_pc
),
901 paddr_nz (from
+ offset
));
903 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
909 /* If we're here, it means we have a branch to LR or CTR. If the
910 branch was taken, the offset is probably greater than 4 (the next
911 instruction), so it's safe to assume that an offset of 4 means we
912 did not take the branch. */
913 if (offset
== PPC_INSN_SIZE
)
914 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
915 from
+ PPC_INSN_SIZE
);
918 /* Check for LK bit indicating whether we should set the link
919 register to point to the next instruction
920 (1: Set, 0: Don't set). */
923 /* Link register needs to be set to the next instruction's PC. */
924 regcache_cooked_write_unsigned (regs
,
925 gdbarch_tdep (gdbarch
)->ppc_lr_regnum
,
926 from
+ PPC_INSN_SIZE
);
928 fprintf_unfiltered (gdb_stdlog
,
929 "displaced: (ppc) adjusted LR to 0x%s\n",
930 paddr_nz (from
+ PPC_INSN_SIZE
));
934 /* Check for breakpoints in the inferior. If we've found one, place the PC
935 right at the breakpoint instruction. */
936 else if ((insn
& BP_MASK
) == BP_INSN
)
937 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
), from
);
939 /* Handle any other instructions that do not fit in the categories above. */
940 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
944 /* Instruction masks used during single-stepping of atomic sequences. */
945 #define LWARX_MASK 0xfc0007fe
946 #define LWARX_INSTRUCTION 0x7c000028
947 #define LDARX_INSTRUCTION 0x7c0000A8
948 #define STWCX_MASK 0xfc0007ff
949 #define STWCX_INSTRUCTION 0x7c00012d
950 #define STDCX_INSTRUCTION 0x7c0001ad
952 /* Checks for an atomic sequence of instructions beginning with a LWARX/LDARX
953 instruction and ending with a STWCX/STDCX instruction. If such a sequence
954 is found, attempt to step through it. A breakpoint is placed at the end of
958 ppc_deal_with_atomic_sequence (struct frame_info
*frame
)
960 CORE_ADDR pc
= get_frame_pc (frame
);
961 CORE_ADDR breaks
[2] = {-1, -1};
963 CORE_ADDR closing_insn
; /* Instruction that closes the atomic sequence. */
964 int insn
= read_memory_integer (loc
, PPC_INSN_SIZE
);
967 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
968 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
969 int opcode
; /* Branch instruction's OPcode. */
970 int bc_insn_count
= 0; /* Conditional branch instruction count. */
972 /* Assume all atomic sequences start with a lwarx/ldarx instruction. */
973 if ((insn
& LWARX_MASK
) != LWARX_INSTRUCTION
974 && (insn
& LWARX_MASK
) != LDARX_INSTRUCTION
)
977 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
979 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
981 loc
+= PPC_INSN_SIZE
;
982 insn
= read_memory_integer (loc
, PPC_INSN_SIZE
);
984 /* Assume that there is at most one conditional branch in the atomic
985 sequence. If a conditional branch is found, put a breakpoint in
986 its destination address. */
987 if ((insn
& BRANCH_MASK
) == BC_INSN
)
989 int immediate
= ((insn
& ~3) << 16) >> 16;
990 int absolute
= ((insn
>> 1) & 1);
992 if (bc_insn_count
>= 1)
993 return 0; /* More than one conditional branch found, fallback
994 to the standard single-step code. */
997 breaks
[1] = immediate
;
999 breaks
[1] = pc
+ immediate
;
1005 if ((insn
& STWCX_MASK
) == STWCX_INSTRUCTION
1006 || (insn
& STWCX_MASK
) == STDCX_INSTRUCTION
)
1010 /* Assume that the atomic sequence ends with a stwcx/stdcx instruction. */
1011 if ((insn
& STWCX_MASK
) != STWCX_INSTRUCTION
1012 && (insn
& STWCX_MASK
) != STDCX_INSTRUCTION
)
1016 loc
+= PPC_INSN_SIZE
;
1017 insn
= read_memory_integer (loc
, PPC_INSN_SIZE
);
1019 /* Insert a breakpoint right after the end of the atomic sequence. */
1022 /* Check for duplicated breakpoints. Check also for a breakpoint
1023 placed (branch instruction's destination) at the stwcx/stdcx
1024 instruction, this resets the reservation and take us back to the
1025 lwarx/ldarx instruction at the beginning of the atomic sequence. */
1026 if (last_breakpoint
&& ((breaks
[1] == breaks
[0])
1027 || (breaks
[1] == closing_insn
)))
1028 last_breakpoint
= 0;
1030 /* Effectively inserts the breakpoints. */
1031 for (index
= 0; index
<= last_breakpoint
; index
++)
1032 insert_single_step_breakpoint (breaks
[index
]);
1038 #define SIGNED_SHORT(x) \
1039 ((sizeof (short) == 2) \
1040 ? ((int)(short)(x)) \
1041 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
1043 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
1045 /* Limit the number of skipped non-prologue instructions, as the examining
1046 of the prologue is expensive. */
1047 static int max_skip_non_prologue_insns
= 10;
1049 /* Return nonzero if the given instruction OP can be part of the prologue
1050 of a function and saves a parameter on the stack. FRAMEP should be
1051 set if one of the previous instructions in the function has set the
1055 store_param_on_stack_p (unsigned long op
, int framep
, int *r0_contains_arg
)
1057 /* Move parameters from argument registers to temporary register. */
1058 if ((op
& 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
1060 /* Rx must be scratch register r0. */
1061 const int rx_regno
= (op
>> 16) & 31;
1062 /* Ry: Only r3 - r10 are used for parameter passing. */
1063 const int ry_regno
= GET_SRC_REG (op
);
1065 if (rx_regno
== 0 && ry_regno
>= 3 && ry_regno
<= 10)
1067 *r0_contains_arg
= 1;
1074 /* Save a General Purpose Register on stack. */
1076 if ((op
& 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
1077 (op
& 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
1079 /* Rx: Only r3 - r10 are used for parameter passing. */
1080 const int rx_regno
= GET_SRC_REG (op
);
1082 return (rx_regno
>= 3 && rx_regno
<= 10);
1085 /* Save a General Purpose Register on stack via the Frame Pointer. */
1088 ((op
& 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
1089 (op
& 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
1090 (op
& 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
1092 /* Rx: Usually, only r3 - r10 are used for parameter passing.
1093 However, the compiler sometimes uses r0 to hold an argument. */
1094 const int rx_regno
= GET_SRC_REG (op
);
1096 return ((rx_regno
>= 3 && rx_regno
<= 10)
1097 || (rx_regno
== 0 && *r0_contains_arg
));
1100 if ((op
& 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
1102 /* Only f2 - f8 are used for parameter passing. */
1103 const int src_regno
= GET_SRC_REG (op
);
1105 return (src_regno
>= 2 && src_regno
<= 8);
1108 if (framep
&& ((op
& 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
1110 /* Only f2 - f8 are used for parameter passing. */
1111 const int src_regno
= GET_SRC_REG (op
);
1113 return (src_regno
>= 2 && src_regno
<= 8);
1116 /* Not an insn that saves a parameter on stack. */
1120 /* Assuming that INSN is a "bl" instruction located at PC, return
1121 nonzero if the destination of the branch is a "blrl" instruction.
1123 This sequence is sometimes found in certain function prologues.
1124 It allows the function to load the LR register with a value that
1125 they can use to access PIC data using PC-relative offsets. */
1128 bl_to_blrl_insn_p (CORE_ADDR pc
, int insn
)
1135 absolute
= (int) ((insn
>> 1) & 1);
1136 immediate
= ((insn
& ~3) << 6) >> 6;
1140 dest
= pc
+ immediate
;
1142 dest_insn
= read_memory_integer (dest
, 4);
1143 if ((dest_insn
& 0xfc00ffff) == 0x4c000021) /* blrl */
1149 /* return pc value after skipping a function prologue and also return
1150 information about a function frame.
1152 in struct rs6000_framedata fdata:
1153 - frameless is TRUE, if function does not have a frame.
1154 - nosavedpc is TRUE, if function does not save %pc value in its frame.
1155 - offset is the initial size of this stack frame --- the amount by
1156 which we decrement the sp to allocate the frame.
1157 - saved_gpr is the number of the first saved gpr.
1158 - saved_fpr is the number of the first saved fpr.
1159 - saved_vr is the number of the first saved vr.
1160 - saved_ev is the number of the first saved ev.
1161 - alloca_reg is the number of the register used for alloca() handling.
1163 - gpr_offset is the offset of the first saved gpr from the previous frame.
1164 - fpr_offset is the offset of the first saved fpr from the previous frame.
1165 - vr_offset is the offset of the first saved vr from the previous frame.
1166 - ev_offset is the offset of the first saved ev from the previous frame.
1167 - lr_offset is the offset of the saved lr
1168 - cr_offset is the offset of the saved cr
1169 - vrsave_offset is the offset of the saved vrsave register
1173 skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
, CORE_ADDR lim_pc
,
1174 struct rs6000_framedata
*fdata
)
1176 CORE_ADDR orig_pc
= pc
;
1177 CORE_ADDR last_prologue_pc
= pc
;
1178 CORE_ADDR li_found_pc
= 0;
1182 long vr_saved_offset
= 0;
1188 int vrsave_reg
= -1;
1191 int minimal_toc_loaded
= 0;
1192 int prev_insn_was_prologue_insn
= 1;
1193 int num_skip_non_prologue_insns
= 0;
1194 int r0_contains_arg
= 0;
1195 const struct bfd_arch_info
*arch_info
= gdbarch_bfd_arch_info (gdbarch
);
1196 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1198 memset (fdata
, 0, sizeof (struct rs6000_framedata
));
1199 fdata
->saved_gpr
= -1;
1200 fdata
->saved_fpr
= -1;
1201 fdata
->saved_vr
= -1;
1202 fdata
->saved_ev
= -1;
1203 fdata
->alloca_reg
= -1;
1204 fdata
->frameless
= 1;
1205 fdata
->nosavedpc
= 1;
1209 /* Sometimes it isn't clear if an instruction is a prologue
1210 instruction or not. When we encounter one of these ambiguous
1211 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
1212 Otherwise, we'll assume that it really is a prologue instruction. */
1213 if (prev_insn_was_prologue_insn
)
1214 last_prologue_pc
= pc
;
1216 /* Stop scanning if we've hit the limit. */
1220 prev_insn_was_prologue_insn
= 1;
1222 /* Fetch the instruction and convert it to an integer. */
1223 if (target_read_memory (pc
, buf
, 4))
1225 op
= extract_unsigned_integer (buf
, 4);
1227 if ((op
& 0xfc1fffff) == 0x7c0802a6)
1229 /* Since shared library / PIC code, which needs to get its
1230 address at runtime, can appear to save more than one link
1244 remember just the first one, but skip over additional
1247 lr_reg
= (op
& 0x03e00000);
1249 r0_contains_arg
= 0;
1252 else if ((op
& 0xfc1fffff) == 0x7c000026)
1254 cr_reg
= (op
& 0x03e00000);
1256 r0_contains_arg
= 0;
1260 else if ((op
& 0xfc1f0000) == 0xd8010000)
1261 { /* stfd Rx,NUM(r1) */
1262 reg
= GET_SRC_REG (op
);
1263 if (fdata
->saved_fpr
== -1 || fdata
->saved_fpr
> reg
)
1265 fdata
->saved_fpr
= reg
;
1266 fdata
->fpr_offset
= SIGNED_SHORT (op
) + offset
;
1271 else if (((op
& 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
1272 (((op
& 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1273 (op
& 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1274 (op
& 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
1277 reg
= GET_SRC_REG (op
);
1278 if (fdata
->saved_gpr
== -1 || fdata
->saved_gpr
> reg
)
1280 fdata
->saved_gpr
= reg
;
1281 if ((op
& 0xfc1f0003) == 0xf8010000)
1283 fdata
->gpr_offset
= SIGNED_SHORT (op
) + offset
;
1288 else if ((op
& 0xffff0000) == 0x60000000)
1291 /* Allow nops in the prologue, but do not consider them to
1292 be part of the prologue unless followed by other prologue
1294 prev_insn_was_prologue_insn
= 0;
1298 else if ((op
& 0xffff0000) == 0x3c000000)
1299 { /* addis 0,0,NUM, used
1300 for >= 32k frames */
1301 fdata
->offset
= (op
& 0x0000ffff) << 16;
1302 fdata
->frameless
= 0;
1303 r0_contains_arg
= 0;
1307 else if ((op
& 0xffff0000) == 0x60000000)
1308 { /* ori 0,0,NUM, 2nd ha
1309 lf of >= 32k frames */
1310 fdata
->offset
|= (op
& 0x0000ffff);
1311 fdata
->frameless
= 0;
1312 r0_contains_arg
= 0;
1316 else if (lr_reg
>= 0 &&
1317 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1318 (((op
& 0xffff0000) == (lr_reg
| 0xf8010000)) ||
1319 /* stw Rx, NUM(r1) */
1320 ((op
& 0xffff0000) == (lr_reg
| 0x90010000)) ||
1321 /* stwu Rx, NUM(r1) */
1322 ((op
& 0xffff0000) == (lr_reg
| 0x94010000))))
1323 { /* where Rx == lr */
1324 fdata
->lr_offset
= offset
;
1325 fdata
->nosavedpc
= 0;
1326 /* Invalidate lr_reg, but don't set it to -1.
1327 That would mean that it had never been set. */
1329 if ((op
& 0xfc000003) == 0xf8000000 || /* std */
1330 (op
& 0xfc000000) == 0x90000000) /* stw */
1332 /* Does not update r1, so add displacement to lr_offset. */
1333 fdata
->lr_offset
+= SIGNED_SHORT (op
);
1338 else if (cr_reg
>= 0 &&
1339 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1340 (((op
& 0xffff0000) == (cr_reg
| 0xf8010000)) ||
1341 /* stw Rx, NUM(r1) */
1342 ((op
& 0xffff0000) == (cr_reg
| 0x90010000)) ||
1343 /* stwu Rx, NUM(r1) */
1344 ((op
& 0xffff0000) == (cr_reg
| 0x94010000))))
1345 { /* where Rx == cr */
1346 fdata
->cr_offset
= offset
;
1347 /* Invalidate cr_reg, but don't set it to -1.
1348 That would mean that it had never been set. */
1350 if ((op
& 0xfc000003) == 0xf8000000 ||
1351 (op
& 0xfc000000) == 0x90000000)
1353 /* Does not update r1, so add displacement to cr_offset. */
1354 fdata
->cr_offset
+= SIGNED_SHORT (op
);
1359 else if ((op
& 0xfe80ffff) == 0x42800005 && lr_reg
!= -1)
1361 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1362 prediction bits. If the LR has already been saved, we can
1366 else if (op
== 0x48000005)
1372 else if (op
== 0x48000004)
1377 else if ((op
& 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1378 in V.4 -mminimal-toc */
1379 (op
& 0xffff0000) == 0x3bde0000)
1380 { /* addi 30,30,foo@l */
1384 else if ((op
& 0xfc000001) == 0x48000001)
1388 fdata
->frameless
= 0;
1390 /* If the return address has already been saved, we can skip
1391 calls to blrl (for PIC). */
1392 if (lr_reg
!= -1 && bl_to_blrl_insn_p (pc
, op
))
1395 /* Don't skip over the subroutine call if it is not within
1396 the first three instructions of the prologue and either
1397 we have no line table information or the line info tells
1398 us that the subroutine call is not part of the line
1399 associated with the prologue. */
1400 if ((pc
- orig_pc
) > 8)
1402 struct symtab_and_line prologue_sal
= find_pc_line (orig_pc
, 0);
1403 struct symtab_and_line this_sal
= find_pc_line (pc
, 0);
1405 if ((prologue_sal
.line
== 0) || (prologue_sal
.line
!= this_sal
.line
))
1409 op
= read_memory_integer (pc
+ 4, 4);
1411 /* At this point, make sure this is not a trampoline
1412 function (a function that simply calls another functions,
1413 and nothing else). If the next is not a nop, this branch
1414 was part of the function prologue. */
1416 if (op
== 0x4def7b82 || op
== 0) /* crorc 15, 15, 15 */
1417 break; /* don't skip over
1422 /* update stack pointer */
1423 else if ((op
& 0xfc1f0000) == 0x94010000)
1424 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
1425 fdata
->frameless
= 0;
1426 fdata
->offset
= SIGNED_SHORT (op
);
1427 offset
= fdata
->offset
;
1430 else if ((op
& 0xfc1f016a) == 0x7c01016e)
1431 { /* stwux rX,r1,rY */
1432 /* no way to figure out what r1 is going to be */
1433 fdata
->frameless
= 0;
1434 offset
= fdata
->offset
;
1437 else if ((op
& 0xfc1f0003) == 0xf8010001)
1438 { /* stdu rX,NUM(r1) */
1439 fdata
->frameless
= 0;
1440 fdata
->offset
= SIGNED_SHORT (op
& ~3UL);
1441 offset
= fdata
->offset
;
1444 else if ((op
& 0xfc1f016a) == 0x7c01016a)
1445 { /* stdux rX,r1,rY */
1446 /* no way to figure out what r1 is going to be */
1447 fdata
->frameless
= 0;
1448 offset
= fdata
->offset
;
1451 else if ((op
& 0xffff0000) == 0x38210000)
1452 { /* addi r1,r1,SIMM */
1453 fdata
->frameless
= 0;
1454 fdata
->offset
+= SIGNED_SHORT (op
);
1455 offset
= fdata
->offset
;
1458 /* Load up minimal toc pointer. Do not treat an epilogue restore
1459 of r31 as a minimal TOC load. */
1460 else if (((op
>> 22) == 0x20f || /* l r31,... or l r30,... */
1461 (op
>> 22) == 0x3af) /* ld r31,... or ld r30,... */
1463 && !minimal_toc_loaded
)
1465 minimal_toc_loaded
= 1;
1468 /* move parameters from argument registers to local variable
1471 else if ((op
& 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1472 (((op
>> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1473 (((op
>> 21) & 31) <= 10) &&
1474 ((long) ((op
>> 16) & 31) >= fdata
->saved_gpr
)) /* Rx: local var reg */
1478 /* store parameters in stack */
1480 /* Move parameters from argument registers to temporary register. */
1481 else if (store_param_on_stack_p (op
, framep
, &r0_contains_arg
))
1485 /* Set up frame pointer */
1487 else if (op
== 0x603f0000 /* oril r31, r1, 0x0 */
1488 || op
== 0x7c3f0b78)
1490 fdata
->frameless
= 0;
1492 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 31);
1495 /* Another way to set up the frame pointer. */
1497 else if ((op
& 0xfc1fffff) == 0x38010000)
1498 { /* addi rX, r1, 0x0 */
1499 fdata
->frameless
= 0;
1501 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
1502 + ((op
& ~0x38010000) >> 21));
1505 /* AltiVec related instructions. */
1506 /* Store the vrsave register (spr 256) in another register for
1507 later manipulation, or load a register into the vrsave
1508 register. 2 instructions are used: mfvrsave and
1509 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1510 and mtspr SPR256, Rn. */
1511 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1512 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1513 else if ((op
& 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1515 vrsave_reg
= GET_SRC_REG (op
);
1518 else if ((op
& 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1522 /* Store the register where vrsave was saved to onto the stack:
1523 rS is the register where vrsave was stored in a previous
1525 /* 100100 sssss 00001 dddddddd dddddddd */
1526 else if ((op
& 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1528 if (vrsave_reg
== GET_SRC_REG (op
))
1530 fdata
->vrsave_offset
= SIGNED_SHORT (op
) + offset
;
1535 /* Compute the new value of vrsave, by modifying the register
1536 where vrsave was saved to. */
1537 else if (((op
& 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1538 || ((op
& 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1542 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1543 in a pair of insns to save the vector registers on the
1545 /* 001110 00000 00000 iiii iiii iiii iiii */
1546 /* 001110 01110 00000 iiii iiii iiii iiii */
1547 else if ((op
& 0xffff0000) == 0x38000000 /* li r0, SIMM */
1548 || (op
& 0xffff0000) == 0x39c00000) /* li r14, SIMM */
1550 if ((op
& 0xffff0000) == 0x38000000)
1551 r0_contains_arg
= 0;
1553 vr_saved_offset
= SIGNED_SHORT (op
);
1555 /* This insn by itself is not part of the prologue, unless
1556 if part of the pair of insns mentioned above. So do not
1557 record this insn as part of the prologue yet. */
1558 prev_insn_was_prologue_insn
= 0;
1560 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1561 /* 011111 sssss 11111 00000 00111001110 */
1562 else if ((op
& 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1564 if (pc
== (li_found_pc
+ 4))
1566 vr_reg
= GET_SRC_REG (op
);
1567 /* If this is the first vector reg to be saved, or if
1568 it has a lower number than others previously seen,
1569 reupdate the frame info. */
1570 if (fdata
->saved_vr
== -1 || fdata
->saved_vr
> vr_reg
)
1572 fdata
->saved_vr
= vr_reg
;
1573 fdata
->vr_offset
= vr_saved_offset
+ offset
;
1575 vr_saved_offset
= -1;
1580 /* End AltiVec related instructions. */
1582 /* Start BookE related instructions. */
1583 /* Store gen register S at (r31+uimm).
1584 Any register less than r13 is volatile, so we don't care. */
1585 /* 000100 sssss 11111 iiiii 01100100001 */
1586 else if (arch_info
->mach
== bfd_mach_ppc_e500
1587 && (op
& 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
1589 if ((op
& 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
1592 ev_reg
= GET_SRC_REG (op
);
1593 imm
= (op
>> 11) & 0x1f;
1594 ev_offset
= imm
* 8;
1595 /* If this is the first vector reg to be saved, or if
1596 it has a lower number than others previously seen,
1597 reupdate the frame info. */
1598 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1600 fdata
->saved_ev
= ev_reg
;
1601 fdata
->ev_offset
= ev_offset
+ offset
;
1606 /* Store gen register rS at (r1+rB). */
1607 /* 000100 sssss 00001 bbbbb 01100100000 */
1608 else if (arch_info
->mach
== bfd_mach_ppc_e500
1609 && (op
& 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1611 if (pc
== (li_found_pc
+ 4))
1613 ev_reg
= GET_SRC_REG (op
);
1614 /* If this is the first vector reg to be saved, or if
1615 it has a lower number than others previously seen,
1616 reupdate the frame info. */
1617 /* We know the contents of rB from the previous instruction. */
1618 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1620 fdata
->saved_ev
= ev_reg
;
1621 fdata
->ev_offset
= vr_saved_offset
+ offset
;
1623 vr_saved_offset
= -1;
1629 /* Store gen register r31 at (rA+uimm). */
1630 /* 000100 11111 aaaaa iiiii 01100100001 */
1631 else if (arch_info
->mach
== bfd_mach_ppc_e500
1632 && (op
& 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
1634 /* Wwe know that the source register is 31 already, but
1635 it can't hurt to compute it. */
1636 ev_reg
= GET_SRC_REG (op
);
1637 ev_offset
= ((op
>> 11) & 0x1f) * 8;
1638 /* If this is the first vector reg to be saved, or if
1639 it has a lower number than others previously seen,
1640 reupdate the frame info. */
1641 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1643 fdata
->saved_ev
= ev_reg
;
1644 fdata
->ev_offset
= ev_offset
+ offset
;
1649 /* Store gen register S at (r31+r0).
1650 Store param on stack when offset from SP bigger than 4 bytes. */
1651 /* 000100 sssss 11111 00000 01100100000 */
1652 else if (arch_info
->mach
== bfd_mach_ppc_e500
1653 && (op
& 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
1655 if (pc
== (li_found_pc
+ 4))
1657 if ((op
& 0x03e00000) >= 0x01a00000)
1659 ev_reg
= GET_SRC_REG (op
);
1660 /* If this is the first vector reg to be saved, or if
1661 it has a lower number than others previously seen,
1662 reupdate the frame info. */
1663 /* We know the contents of r0 from the previous
1665 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1667 fdata
->saved_ev
= ev_reg
;
1668 fdata
->ev_offset
= vr_saved_offset
+ offset
;
1672 vr_saved_offset
= -1;
1677 /* End BookE related instructions. */
1681 /* Not a recognized prologue instruction.
1682 Handle optimizer code motions into the prologue by continuing
1683 the search if we have no valid frame yet or if the return
1684 address is not yet saved in the frame. */
1685 if (fdata
->frameless
== 0 && fdata
->nosavedpc
== 0)
1688 if (op
== 0x4e800020 /* blr */
1689 || op
== 0x4e800420) /* bctr */
1690 /* Do not scan past epilogue in frameless functions or
1693 if ((op
& 0xf4000000) == 0x40000000) /* bxx */
1694 /* Never skip branches. */
1697 if (num_skip_non_prologue_insns
++ > max_skip_non_prologue_insns
)
1698 /* Do not scan too many insns, scanning insns is expensive with
1702 /* Continue scanning. */
1703 prev_insn_was_prologue_insn
= 0;
1709 /* I have problems with skipping over __main() that I need to address
1710 * sometime. Previously, I used to use misc_function_vector which
1711 * didn't work as well as I wanted to be. -MGO */
1713 /* If the first thing after skipping a prolog is a branch to a function,
1714 this might be a call to an initializer in main(), introduced by gcc2.
1715 We'd like to skip over it as well. Fortunately, xlc does some extra
1716 work before calling a function right after a prologue, thus we can
1717 single out such gcc2 behaviour. */
1720 if ((op
& 0xfc000001) == 0x48000001)
1721 { /* bl foo, an initializer function? */
1722 op
= read_memory_integer (pc
+ 4, 4);
1724 if (op
== 0x4def7b82)
1725 { /* cror 0xf, 0xf, 0xf (nop) */
1727 /* Check and see if we are in main. If so, skip over this
1728 initializer function as well. */
1730 tmp
= find_pc_misc_function (pc
);
1732 && strcmp (misc_function_vector
[tmp
].name
, main_name ()) == 0)
1738 fdata
->offset
= -fdata
->offset
;
1739 return last_prologue_pc
;
1743 rs6000_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1745 struct rs6000_framedata frame
;
1746 CORE_ADDR limit_pc
, func_addr
;
1748 /* See if we can determine the end of the prologue via the symbol table.
1749 If so, then return either PC, or the PC after the prologue, whichever
1751 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
1753 CORE_ADDR post_prologue_pc
= skip_prologue_using_sal (func_addr
);
1754 if (post_prologue_pc
!= 0)
1755 return max (pc
, post_prologue_pc
);
1758 /* Can't determine prologue from the symbol table, need to examine
1761 /* Find an upper limit on the function prologue using the debug
1762 information. If the debug information could not be used to provide
1763 that bound, then use an arbitrary large number as the upper bound. */
1764 limit_pc
= skip_prologue_using_sal (pc
);
1766 limit_pc
= pc
+ 100; /* Magic. */
1768 pc
= skip_prologue (gdbarch
, pc
, limit_pc
, &frame
);
1773 /* All the ABI's require 16 byte alignment. */
1775 rs6000_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1777 return (addr
& -16);
1780 /* Return whether handle_inferior_event() should proceed through code
1781 starting at PC in function NAME when stepping.
1783 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
1784 handle memory references that are too distant to fit in instructions
1785 generated by the compiler. For example, if 'foo' in the following
1790 is greater than 32767, the linker might replace the lwz with a branch to
1791 somewhere in @FIX1 that does the load in 2 instructions and then branches
1792 back to where execution should continue.
1794 GDB should silently step over @FIX code, just like AIX dbx does.
1795 Unfortunately, the linker uses the "b" instruction for the
1796 branches, meaning that the link register doesn't get set.
1797 Therefore, GDB's usual step_over_function () mechanism won't work.
1799 Instead, use the gdbarch_skip_trampoline_code and
1800 gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past
1804 rs6000_in_solib_return_trampoline (CORE_ADDR pc
, char *name
)
1806 return name
&& !strncmp (name
, "@FIX", 4);
1809 /* Skip code that the user doesn't want to see when stepping:
1811 1. Indirect function calls use a piece of trampoline code to do context
1812 switching, i.e. to set the new TOC table. Skip such code if we are on
1813 its first instruction (as when we have single-stepped to here).
1815 2. Skip shared library trampoline code (which is different from
1816 indirect function call trampolines).
1818 3. Skip bigtoc fixup code.
1820 Result is desired PC to step until, or NULL if we are not in
1821 code that should be skipped. */
1824 rs6000_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
1826 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (frame
));
1827 unsigned int ii
, op
;
1829 CORE_ADDR solib_target_pc
;
1830 struct minimal_symbol
*msymbol
;
1832 static unsigned trampoline_code
[] =
1834 0x800b0000, /* l r0,0x0(r11) */
1835 0x90410014, /* st r2,0x14(r1) */
1836 0x7c0903a6, /* mtctr r0 */
1837 0x804b0004, /* l r2,0x4(r11) */
1838 0x816b0008, /* l r11,0x8(r11) */
1839 0x4e800420, /* bctr */
1840 0x4e800020, /* br */
1844 /* Check for bigtoc fixup code. */
1845 msymbol
= lookup_minimal_symbol_by_pc (pc
);
1847 && rs6000_in_solib_return_trampoline (pc
, SYMBOL_LINKAGE_NAME (msymbol
)))
1849 /* Double-check that the third instruction from PC is relative "b". */
1850 op
= read_memory_integer (pc
+ 8, 4);
1851 if ((op
& 0xfc000003) == 0x48000000)
1853 /* Extract bits 6-29 as a signed 24-bit relative word address and
1854 add it to the containing PC. */
1855 rel
= ((int)(op
<< 6) >> 6);
1856 return pc
+ 8 + rel
;
1860 /* If pc is in a shared library trampoline, return its target. */
1861 solib_target_pc
= find_solib_trampoline_target (frame
, pc
);
1862 if (solib_target_pc
)
1863 return solib_target_pc
;
1865 for (ii
= 0; trampoline_code
[ii
]; ++ii
)
1867 op
= read_memory_integer (pc
+ (ii
* 4), 4);
1868 if (op
!= trampoline_code
[ii
])
1871 ii
= get_frame_register_unsigned (frame
, 11); /* r11 holds destination addr */
1872 pc
= read_memory_unsigned_integer (ii
, tdep
->wordsize
); /* (r11) value */
1876 /* ISA-specific vector types. */
1878 static struct type
*
1879 rs6000_builtin_type_vec64 (struct gdbarch
*gdbarch
)
1881 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1883 if (!tdep
->ppc_builtin_type_vec64
)
1885 /* The type we're building is this: */
1887 union __gdb_builtin_type_vec64
1891 int32_t v2_int32
[2];
1892 int16_t v4_int16
[4];
1899 t
= init_composite_type ("__ppc_builtin_type_vec64", TYPE_CODE_UNION
);
1900 append_composite_type_field (t
, "uint64", builtin_type_int64
);
1901 append_composite_type_field (t
, "v2_float",
1902 init_vector_type (builtin_type_float
, 2));
1903 append_composite_type_field (t
, "v2_int32",
1904 init_vector_type (builtin_type_int32
, 2));
1905 append_composite_type_field (t
, "v4_int16",
1906 init_vector_type (builtin_type_int16
, 4));
1907 append_composite_type_field (t
, "v8_int8",
1908 init_vector_type (builtin_type_int8
, 8));
1910 TYPE_FLAGS (t
) |= TYPE_FLAG_VECTOR
;
1911 TYPE_NAME (t
) = "ppc_builtin_type_vec64";
1912 tdep
->ppc_builtin_type_vec64
= t
;
1915 return tdep
->ppc_builtin_type_vec64
;
1918 /* Return the name of register number REGNO, or the empty string if it
1919 is an anonymous register. */
1922 rs6000_register_name (struct gdbarch
*gdbarch
, int regno
)
1924 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1926 /* The upper half "registers" have names in the XML description,
1927 but we present only the low GPRs and the full 64-bit registers
1929 if (tdep
->ppc_ev0_upper_regnum
>= 0
1930 && tdep
->ppc_ev0_upper_regnum
<= regno
1931 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
1934 /* Check if the SPE pseudo registers are available. */
1935 if (IS_SPE_PSEUDOREG (tdep
, regno
))
1937 static const char *const spe_regnames
[] = {
1938 "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7",
1939 "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15",
1940 "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23",
1941 "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31",
1943 return spe_regnames
[regno
- tdep
->ppc_ev0_regnum
];
1946 /* Check if the decimal128 pseudo-registers are available. */
1947 if (IS_DFP_PSEUDOREG (tdep
, regno
))
1949 static const char *const dfp128_regnames
[] = {
1950 "dl0", "dl1", "dl2", "dl3",
1951 "dl4", "dl5", "dl6", "dl7",
1952 "dl8", "dl9", "dl10", "dl11",
1953 "dl12", "dl13", "dl14", "dl15"
1955 return dfp128_regnames
[regno
- tdep
->ppc_dl0_regnum
];
1958 return tdesc_register_name (gdbarch
, regno
);
1961 /* Return the GDB type object for the "standard" data type of data in
1964 static struct type
*
1965 rs6000_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
1967 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1969 /* These are the only pseudo-registers we support. */
1970 gdb_assert (IS_SPE_PSEUDOREG (tdep
, regnum
)
1971 || IS_DFP_PSEUDOREG (tdep
, regnum
));
1973 /* These are the e500 pseudo-registers. */
1974 if (IS_SPE_PSEUDOREG (tdep
, regnum
))
1975 return rs6000_builtin_type_vec64 (gdbarch
);
1977 /* Could only be the ppc decimal128 pseudo-registers. */
1978 return builtin_type (gdbarch
)->builtin_declong
;
1981 /* Is REGNUM a member of REGGROUP? */
1983 rs6000_pseudo_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
1984 struct reggroup
*group
)
1986 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1988 /* These are the only pseudo-registers we support. */
1989 gdb_assert (IS_SPE_PSEUDOREG (tdep
, regnum
)
1990 || IS_DFP_PSEUDOREG (tdep
, regnum
));
1992 /* These are the e500 pseudo-registers. */
1993 if (IS_SPE_PSEUDOREG (tdep
, regnum
))
1994 return group
== all_reggroup
|| group
== vector_reggroup
;
1996 /* Could only be the ppc decimal128 pseudo-registers. */
1997 return group
== all_reggroup
|| group
== float_reggroup
;
2000 /* The register format for RS/6000 floating point registers is always
2001 double, we need a conversion if the memory format is float. */
2004 rs6000_convert_register_p (struct gdbarch
*gdbarch
, int regnum
,
2007 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2009 return (tdep
->ppc_fp0_regnum
>= 0
2010 && regnum
>= tdep
->ppc_fp0_regnum
2011 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
2012 && TYPE_CODE (type
) == TYPE_CODE_FLT
2013 && TYPE_LENGTH (type
) != TYPE_LENGTH (builtin_type_double
));
2017 rs6000_register_to_value (struct frame_info
*frame
,
2022 gdb_byte from
[MAX_REGISTER_SIZE
];
2024 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
2026 get_frame_register (frame
, regnum
, from
);
2027 convert_typed_floating (from
, builtin_type_double
, to
, type
);
2031 rs6000_value_to_register (struct frame_info
*frame
,
2034 const gdb_byte
*from
)
2036 gdb_byte to
[MAX_REGISTER_SIZE
];
2038 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
2040 convert_typed_floating (from
, type
, to
, builtin_type_double
);
2041 put_frame_register (frame
, regnum
, to
);
2044 /* Move SPE vector register values between a 64-bit buffer and the two
2045 32-bit raw register halves in a regcache. This function handles
2046 both splitting a 64-bit value into two 32-bit halves, and joining
2047 two halves into a whole 64-bit value, depending on the function
2048 passed as the MOVE argument.
2050 EV_REG must be the number of an SPE evN vector register --- a
2051 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2054 Call MOVE once for each 32-bit half of that register, passing
2055 REGCACHE, the number of the raw register corresponding to that
2056 half, and the address of the appropriate half of BUFFER.
2058 For example, passing 'regcache_raw_read' as the MOVE function will
2059 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2060 'regcache_raw_supply' will supply the contents of BUFFER to the
2061 appropriate pair of raw registers in REGCACHE.
2063 You may need to cast away some 'const' qualifiers when passing
2064 MOVE, since this function can't tell at compile-time which of
2065 REGCACHE or BUFFER is acting as the source of the data. If C had
2066 co-variant type qualifiers, ... */
2068 e500_move_ev_register (void (*move
) (struct regcache
*regcache
,
2069 int regnum
, gdb_byte
*buf
),
2070 struct regcache
*regcache
, int ev_reg
,
2073 struct gdbarch
*arch
= get_regcache_arch (regcache
);
2074 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
2076 gdb_byte
*byte_buffer
= buffer
;
2078 gdb_assert (IS_SPE_PSEUDOREG (tdep
, ev_reg
));
2080 reg_index
= ev_reg
- tdep
->ppc_ev0_regnum
;
2082 if (gdbarch_byte_order (arch
) == BFD_ENDIAN_BIG
)
2084 move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
, byte_buffer
);
2085 move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
, byte_buffer
+ 4);
2089 move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
, byte_buffer
);
2090 move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
, byte_buffer
+ 4);
2095 e500_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2096 int reg_nr
, gdb_byte
*buffer
)
2098 e500_move_ev_register (regcache_raw_read
, regcache
, reg_nr
, buffer
);
2102 e500_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2103 int reg_nr
, const gdb_byte
*buffer
)
2105 e500_move_ev_register ((void (*) (struct regcache
*, int, gdb_byte
*))
2107 regcache
, reg_nr
, (gdb_byte
*) buffer
);
2110 /* Read method for PPC pseudo-registers. Currently this is handling the
2111 16 decimal128 registers that map into 16 pairs of FP registers. */
2113 ppc_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2114 int reg_nr
, gdb_byte
*buffer
)
2116 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2117 int reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2119 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2121 /* Read two FP registers to form a whole dl register. */
2122 regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2123 2 * reg_index
, buffer
);
2124 regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2125 2 * reg_index
+ 1, buffer
+ 8);
2129 regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2130 2 * reg_index
+ 1, buffer
+ 8);
2131 regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2132 2 * reg_index
, buffer
);
2136 /* Write method for PPC pseudo-registers. Currently this is handling the
2137 16 decimal128 registers that map into 16 pairs of FP registers. */
2139 ppc_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2140 int reg_nr
, const gdb_byte
*buffer
)
2142 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2143 int reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2145 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2147 /* Write each half of the dl register into a separate
2149 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2150 2 * reg_index
, buffer
);
2151 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2152 2 * reg_index
+ 1, buffer
+ 8);
2156 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2157 2 * reg_index
+ 1, buffer
+ 8);
2158 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2159 2 * reg_index
, buffer
);
2164 rs6000_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2165 int reg_nr
, gdb_byte
*buffer
)
2167 struct gdbarch
*regcache_arch
= get_regcache_arch (regcache
);
2168 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2170 gdb_assert (regcache_arch
== gdbarch
);
2172 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2173 e500_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2174 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2175 ppc_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2177 internal_error (__FILE__
, __LINE__
,
2178 _("rs6000_pseudo_register_read: "
2179 "called on unexpected register '%s' (%d)"),
2180 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2184 rs6000_pseudo_register_write (struct gdbarch
*gdbarch
,
2185 struct regcache
*regcache
,
2186 int reg_nr
, const gdb_byte
*buffer
)
2188 struct gdbarch
*regcache_arch
= get_regcache_arch (regcache
);
2189 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2191 gdb_assert (regcache_arch
== gdbarch
);
2193 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2194 e500_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2195 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2196 ppc_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2198 internal_error (__FILE__
, __LINE__
,
2199 _("rs6000_pseudo_register_write: "
2200 "called on unexpected register '%s' (%d)"),
2201 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2204 /* Convert a DBX STABS register number to a GDB register number. */
2206 rs6000_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
2208 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2210 if (0 <= num
&& num
<= 31)
2211 return tdep
->ppc_gp0_regnum
+ num
;
2212 else if (32 <= num
&& num
<= 63)
2213 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2214 specifies registers the architecture doesn't have? Our
2215 callers don't check the value we return. */
2216 return tdep
->ppc_fp0_regnum
+ (num
- 32);
2217 else if (77 <= num
&& num
<= 108)
2218 return tdep
->ppc_vr0_regnum
+ (num
- 77);
2219 else if (1200 <= num
&& num
< 1200 + 32)
2220 return tdep
->ppc_ev0_regnum
+ (num
- 1200);
2225 return tdep
->ppc_mq_regnum
;
2227 return tdep
->ppc_lr_regnum
;
2229 return tdep
->ppc_ctr_regnum
;
2231 return tdep
->ppc_xer_regnum
;
2233 return tdep
->ppc_vrsave_regnum
;
2235 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
2237 return tdep
->ppc_acc_regnum
;
2239 return tdep
->ppc_spefscr_regnum
;
2246 /* Convert a Dwarf 2 register number to a GDB register number. */
2248 rs6000_dwarf2_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
2250 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2252 if (0 <= num
&& num
<= 31)
2253 return tdep
->ppc_gp0_regnum
+ num
;
2254 else if (32 <= num
&& num
<= 63)
2255 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2256 specifies registers the architecture doesn't have? Our
2257 callers don't check the value we return. */
2258 return tdep
->ppc_fp0_regnum
+ (num
- 32);
2259 else if (1124 <= num
&& num
< 1124 + 32)
2260 return tdep
->ppc_vr0_regnum
+ (num
- 1124);
2261 else if (1200 <= num
&& num
< 1200 + 32)
2262 return tdep
->ppc_ev0_regnum
+ (num
- 1200);
2267 return tdep
->ppc_cr_regnum
;
2269 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
2271 return tdep
->ppc_acc_regnum
;
2273 return tdep
->ppc_mq_regnum
;
2275 return tdep
->ppc_xer_regnum
;
2277 return tdep
->ppc_lr_regnum
;
2279 return tdep
->ppc_ctr_regnum
;
2281 return tdep
->ppc_vrsave_regnum
;
2283 return tdep
->ppc_spefscr_regnum
;
2289 /* Translate a .eh_frame register to DWARF register, or adjust a
2290 .debug_frame register. */
2293 rs6000_adjust_frame_regnum (struct gdbarch
*gdbarch
, int num
, int eh_frame_p
)
2295 /* GCC releases before 3.4 use GCC internal register numbering in
2296 .debug_frame (and .debug_info, et cetera). The numbering is
2297 different from the standard SysV numbering for everything except
2298 for GPRs and FPRs. We can not detect this problem in most cases
2299 - to get accurate debug info for variables living in lr, ctr, v0,
2300 et cetera, use a newer version of GCC. But we must detect
2301 one important case - lr is in column 65 in .debug_frame output,
2304 GCC 3.4, and the "hammer" branch, have a related problem. They
2305 record lr register saves in .debug_frame as 108, but still record
2306 the return column as 65. We fix that up too.
2308 We can do this because 65 is assigned to fpsr, and GCC never
2309 generates debug info referring to it. To add support for
2310 handwritten debug info that restores fpsr, we would need to add a
2311 producer version check to this. */
2320 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
2321 internal register numbering; translate that to the standard DWARF2
2322 register numbering. */
2323 if (0 <= num
&& num
<= 63) /* r0-r31,fp0-fp31 */
2325 else if (68 <= num
&& num
<= 75) /* cr0-cr8 */
2326 return num
- 68 + 86;
2327 else if (77 <= num
&& num
<= 108) /* vr0-vr31 */
2328 return num
- 77 + 1124;
2340 case 109: /* vrsave */
2342 case 110: /* vscr */
2344 case 111: /* spe_acc */
2346 case 112: /* spefscr */
2354 /* Handling the various POWER/PowerPC variants. */
2356 /* Information about a particular processor variant. */
2360 /* Name of this variant. */
2363 /* English description of the variant. */
2366 /* bfd_arch_info.arch corresponding to variant. */
2367 enum bfd_architecture arch
;
2369 /* bfd_arch_info.mach corresponding to variant. */
2372 /* Target description for this variant. */
2373 struct target_desc
**tdesc
;
2376 static struct variant variants
[] =
2378 {"powerpc", "PowerPC user-level", bfd_arch_powerpc
,
2379 bfd_mach_ppc
, &tdesc_powerpc_altivec32
},
2380 {"power", "POWER user-level", bfd_arch_rs6000
,
2381 bfd_mach_rs6k
, &tdesc_rs6000
},
2382 {"403", "IBM PowerPC 403", bfd_arch_powerpc
,
2383 bfd_mach_ppc_403
, &tdesc_powerpc_403
},
2384 {"601", "Motorola PowerPC 601", bfd_arch_powerpc
,
2385 bfd_mach_ppc_601
, &tdesc_powerpc_601
},
2386 {"602", "Motorola PowerPC 602", bfd_arch_powerpc
,
2387 bfd_mach_ppc_602
, &tdesc_powerpc_602
},
2388 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc
,
2389 bfd_mach_ppc_603
, &tdesc_powerpc_603
},
2390 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc
,
2391 604, &tdesc_powerpc_604
},
2392 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc
,
2393 bfd_mach_ppc_403gc
, &tdesc_powerpc_403gc
},
2394 {"505", "Motorola PowerPC 505", bfd_arch_powerpc
,
2395 bfd_mach_ppc_505
, &tdesc_powerpc_505
},
2396 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc
,
2397 bfd_mach_ppc_860
, &tdesc_powerpc_860
},
2398 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc
,
2399 bfd_mach_ppc_750
, &tdesc_powerpc_750
},
2400 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc
,
2401 bfd_mach_ppc_7400
, &tdesc_powerpc_7400
},
2402 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc
,
2403 bfd_mach_ppc_e500
, &tdesc_powerpc_e500
},
2406 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc
,
2407 bfd_mach_ppc64
, &tdesc_powerpc_altivec64
},
2408 {"620", "Motorola PowerPC 620", bfd_arch_powerpc
,
2409 bfd_mach_ppc_620
, &tdesc_powerpc_64
},
2410 {"630", "Motorola PowerPC 630", bfd_arch_powerpc
,
2411 bfd_mach_ppc_630
, &tdesc_powerpc_64
},
2412 {"a35", "PowerPC A35", bfd_arch_powerpc
,
2413 bfd_mach_ppc_a35
, &tdesc_powerpc_64
},
2414 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc
,
2415 bfd_mach_ppc_rs64ii
, &tdesc_powerpc_64
},
2416 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc
,
2417 bfd_mach_ppc_rs64iii
, &tdesc_powerpc_64
},
2419 /* FIXME: I haven't checked the register sets of the following. */
2420 {"rs1", "IBM POWER RS1", bfd_arch_rs6000
,
2421 bfd_mach_rs6k_rs1
, &tdesc_rs6000
},
2422 {"rsc", "IBM POWER RSC", bfd_arch_rs6000
,
2423 bfd_mach_rs6k_rsc
, &tdesc_rs6000
},
2424 {"rs2", "IBM POWER RS2", bfd_arch_rs6000
,
2425 bfd_mach_rs6k_rs2
, &tdesc_rs6000
},
2430 /* Return the variant corresponding to architecture ARCH and machine number
2431 MACH. If no such variant exists, return null. */
2433 static const struct variant
*
2434 find_variant_by_arch (enum bfd_architecture arch
, unsigned long mach
)
2436 const struct variant
*v
;
2438 for (v
= variants
; v
->name
; v
++)
2439 if (arch
== v
->arch
&& mach
== v
->mach
)
2446 gdb_print_insn_powerpc (bfd_vma memaddr
, disassemble_info
*info
)
2448 if (!info
->disassembler_options
)
2449 info
->disassembler_options
= "any";
2451 if (info
->endian
== BFD_ENDIAN_BIG
)
2452 return print_insn_big_powerpc (memaddr
, info
);
2454 return print_insn_little_powerpc (memaddr
, info
);
2458 rs6000_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2460 return frame_unwind_register_unsigned (next_frame
,
2461 gdbarch_pc_regnum (gdbarch
));
2464 static struct frame_id
2465 rs6000_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2467 return frame_id_build (get_frame_register_unsigned
2468 (this_frame
, gdbarch_sp_regnum (gdbarch
)),
2469 get_frame_pc (this_frame
));
2472 struct rs6000_frame_cache
2475 CORE_ADDR initial_sp
;
2476 struct trad_frame_saved_reg
*saved_regs
;
2479 static struct rs6000_frame_cache
*
2480 rs6000_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2482 struct rs6000_frame_cache
*cache
;
2483 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2484 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2485 struct rs6000_framedata fdata
;
2486 int wordsize
= tdep
->wordsize
;
2489 if ((*this_cache
) != NULL
)
2490 return (*this_cache
);
2491 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
2492 (*this_cache
) = cache
;
2493 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2495 func
= get_frame_func (this_frame
);
2496 pc
= get_frame_pc (this_frame
);
2497 skip_prologue (gdbarch
, func
, pc
, &fdata
);
2499 /* Figure out the parent's stack pointer. */
2501 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
2502 address of the current frame. Things might be easier if the
2503 ->frame pointed to the outer-most address of the frame. In
2504 the mean time, the address of the prev frame is used as the
2505 base address of this frame. */
2506 cache
->base
= get_frame_register_unsigned
2507 (this_frame
, gdbarch_sp_regnum (gdbarch
));
2509 /* If the function appears to be frameless, check a couple of likely
2510 indicators that we have simply failed to find the frame setup.
2511 Two common cases of this are missing symbols (i.e.
2512 frame_func_unwind returns the wrong address or 0), and assembly
2513 stubs which have a fast exit path but set up a frame on the slow
2516 If the LR appears to return to this function, then presume that
2517 we have an ABI compliant frame that we failed to find. */
2518 if (fdata
.frameless
&& fdata
.lr_offset
== 0)
2523 saved_lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
2524 if (func
== 0 && saved_lr
== pc
)
2528 CORE_ADDR saved_func
= get_pc_function_start (saved_lr
);
2529 if (func
== saved_func
)
2535 fdata
.frameless
= 0;
2536 fdata
.lr_offset
= tdep
->lr_frame_offset
;
2540 if (!fdata
.frameless
)
2541 /* Frameless really means stackless. */
2542 cache
->base
= read_memory_unsigned_integer (cache
->base
, wordsize
);
2544 trad_frame_set_value (cache
->saved_regs
,
2545 gdbarch_sp_regnum (gdbarch
), cache
->base
);
2547 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
2548 All fpr's from saved_fpr to fp31 are saved. */
2550 if (fdata
.saved_fpr
>= 0)
2553 CORE_ADDR fpr_addr
= cache
->base
+ fdata
.fpr_offset
;
2555 /* If skip_prologue says floating-point registers were saved,
2556 but the current architecture has no floating-point registers,
2557 then that's strange. But we have no indices to even record
2558 the addresses under, so we just ignore it. */
2559 if (ppc_floating_point_unit_p (gdbarch
))
2560 for (i
= fdata
.saved_fpr
; i
< ppc_num_fprs
; i
++)
2562 cache
->saved_regs
[tdep
->ppc_fp0_regnum
+ i
].addr
= fpr_addr
;
2567 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
2568 All gpr's from saved_gpr to gpr31 are saved. */
2570 if (fdata
.saved_gpr
>= 0)
2573 CORE_ADDR gpr_addr
= cache
->base
+ fdata
.gpr_offset
;
2574 for (i
= fdata
.saved_gpr
; i
< ppc_num_gprs
; i
++)
2576 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= gpr_addr
;
2577 gpr_addr
+= wordsize
;
2581 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
2582 All vr's from saved_vr to vr31 are saved. */
2583 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
2585 if (fdata
.saved_vr
>= 0)
2588 CORE_ADDR vr_addr
= cache
->base
+ fdata
.vr_offset
;
2589 for (i
= fdata
.saved_vr
; i
< 32; i
++)
2591 cache
->saved_regs
[tdep
->ppc_vr0_regnum
+ i
].addr
= vr_addr
;
2592 vr_addr
+= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
2597 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
2598 All vr's from saved_ev to ev31 are saved. ????? */
2599 if (tdep
->ppc_ev0_regnum
!= -1)
2601 if (fdata
.saved_ev
>= 0)
2604 CORE_ADDR ev_addr
= cache
->base
+ fdata
.ev_offset
;
2605 for (i
= fdata
.saved_ev
; i
< ppc_num_gprs
; i
++)
2607 cache
->saved_regs
[tdep
->ppc_ev0_regnum
+ i
].addr
= ev_addr
;
2608 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= ev_addr
+ 4;
2609 ev_addr
+= register_size (gdbarch
, tdep
->ppc_ev0_regnum
);
2614 /* If != 0, fdata.cr_offset is the offset from the frame that
2616 if (fdata
.cr_offset
!= 0)
2617 cache
->saved_regs
[tdep
->ppc_cr_regnum
].addr
= cache
->base
+ fdata
.cr_offset
;
2619 /* If != 0, fdata.lr_offset is the offset from the frame that
2621 if (fdata
.lr_offset
!= 0)
2622 cache
->saved_regs
[tdep
->ppc_lr_regnum
].addr
= cache
->base
+ fdata
.lr_offset
;
2623 /* The PC is found in the link register. */
2624 cache
->saved_regs
[gdbarch_pc_regnum (gdbarch
)] =
2625 cache
->saved_regs
[tdep
->ppc_lr_regnum
];
2627 /* If != 0, fdata.vrsave_offset is the offset from the frame that
2628 holds the VRSAVE. */
2629 if (fdata
.vrsave_offset
!= 0)
2630 cache
->saved_regs
[tdep
->ppc_vrsave_regnum
].addr
= cache
->base
+ fdata
.vrsave_offset
;
2632 if (fdata
.alloca_reg
< 0)
2633 /* If no alloca register used, then fi->frame is the value of the
2634 %sp for this frame, and it is good enough. */
2636 = get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
2639 = get_frame_register_unsigned (this_frame
, fdata
.alloca_reg
);
2645 rs6000_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2646 struct frame_id
*this_id
)
2648 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
2650 /* This marks the outermost frame. */
2651 if (info
->base
== 0)
2654 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2657 static struct value
*
2658 rs6000_frame_prev_register (struct frame_info
*this_frame
,
2659 void **this_cache
, int regnum
)
2661 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
2663 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2666 static const struct frame_unwind rs6000_frame_unwind
=
2669 rs6000_frame_this_id
,
2670 rs6000_frame_prev_register
,
2672 default_frame_sniffer
2677 rs6000_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2679 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
2681 return info
->initial_sp
;
2684 static const struct frame_base rs6000_frame_base
= {
2685 &rs6000_frame_unwind
,
2686 rs6000_frame_base_address
,
2687 rs6000_frame_base_address
,
2688 rs6000_frame_base_address
2691 static const struct frame_base
*
2692 rs6000_frame_base_sniffer (struct frame_info
*this_frame
)
2694 return &rs6000_frame_base
;
2697 /* DWARF-2 frame support. Used to handle the detection of
2698 clobbered registers during function calls. */
2701 ppc_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
2702 struct dwarf2_frame_state_reg
*reg
,
2703 struct frame_info
*this_frame
)
2705 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2707 /* PPC32 and PPC64 ABI's are the same regarding volatile and
2708 non-volatile registers. We will use the same code for both. */
2710 /* Call-saved GP registers. */
2711 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 14
2712 && regnum
<= tdep
->ppc_gp0_regnum
+ 31)
2713 || (regnum
== tdep
->ppc_gp0_regnum
+ 1))
2714 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
2716 /* Call-clobbered GP registers. */
2717 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 3
2718 && regnum
<= tdep
->ppc_gp0_regnum
+ 12)
2719 || (regnum
== tdep
->ppc_gp0_regnum
))
2720 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
2722 /* Deal with FP registers, if supported. */
2723 if (tdep
->ppc_fp0_regnum
>= 0)
2725 /* Call-saved FP registers. */
2726 if ((regnum
>= tdep
->ppc_fp0_regnum
+ 14
2727 && regnum
<= tdep
->ppc_fp0_regnum
+ 31))
2728 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
2730 /* Call-clobbered FP registers. */
2731 if ((regnum
>= tdep
->ppc_fp0_regnum
2732 && regnum
<= tdep
->ppc_fp0_regnum
+ 13))
2733 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
2736 /* Deal with ALTIVEC registers, if supported. */
2737 if (tdep
->ppc_vr0_regnum
> 0 && tdep
->ppc_vrsave_regnum
> 0)
2739 /* Call-saved Altivec registers. */
2740 if ((regnum
>= tdep
->ppc_vr0_regnum
+ 20
2741 && regnum
<= tdep
->ppc_vr0_regnum
+ 31)
2742 || regnum
== tdep
->ppc_vrsave_regnum
)
2743 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
2745 /* Call-clobbered Altivec registers. */
2746 if ((regnum
>= tdep
->ppc_vr0_regnum
2747 && regnum
<= tdep
->ppc_vr0_regnum
+ 19))
2748 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
2751 /* Handle PC register and Stack Pointer correctly. */
2752 if (regnum
== gdbarch_pc_regnum (gdbarch
))
2753 reg
->how
= DWARF2_FRAME_REG_RA
;
2754 else if (regnum
== gdbarch_sp_regnum (gdbarch
))
2755 reg
->how
= DWARF2_FRAME_REG_CFA
;
2759 /* Initialize the current architecture based on INFO. If possible, re-use an
2760 architecture from ARCHES, which is a list of architectures already created
2761 during this debugging session.
2763 Called e.g. at program startup, when reading a core file, and when reading
2766 static struct gdbarch
*
2767 rs6000_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2769 struct gdbarch
*gdbarch
;
2770 struct gdbarch_tdep
*tdep
;
2771 int wordsize
, from_xcoff_exec
, from_elf_exec
;
2772 enum bfd_architecture arch
;
2776 enum auto_boolean soft_float_flag
= powerpc_soft_float_global
;
2778 enum powerpc_vector_abi vector_abi
= powerpc_vector_abi_global
;
2779 int have_fpu
= 1, have_spe
= 0, have_mq
= 0, have_altivec
= 0, have_dfp
= 0;
2780 int tdesc_wordsize
= -1;
2781 const struct target_desc
*tdesc
= info
.target_desc
;
2782 struct tdesc_arch_data
*tdesc_data
= NULL
;
2783 int num_pseudoregs
= 0;
2785 from_xcoff_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
2786 bfd_get_flavour (info
.abfd
) == bfd_target_xcoff_flavour
;
2788 from_elf_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
2789 bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
;
2791 /* Check word size. If INFO is from a binary file, infer it from
2792 that, else choose a likely default. */
2793 if (from_xcoff_exec
)
2795 if (bfd_xcoff_is_xcoff64 (info
.abfd
))
2800 else if (from_elf_exec
)
2802 if (elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
2807 else if (tdesc_has_registers (tdesc
))
2811 if (info
.bfd_arch_info
!= NULL
&& info
.bfd_arch_info
->bits_per_word
!= 0)
2812 wordsize
= info
.bfd_arch_info
->bits_per_word
/
2813 info
.bfd_arch_info
->bits_per_byte
;
2818 /* Get the architecture and machine from the BFD. */
2819 arch
= info
.bfd_arch_info
->arch
;
2820 mach
= info
.bfd_arch_info
->mach
;
2822 /* For e500 executables, the apuinfo section is of help here. Such
2823 section contains the identifier and revision number of each
2824 Application-specific Processing Unit that is present on the
2825 chip. The content of the section is determined by the assembler
2826 which looks at each instruction and determines which unit (and
2827 which version of it) can execute it. In our case we just look for
2828 the existance of the section. */
2832 sect
= bfd_get_section_by_name (info
.abfd
, ".PPC.EMB.apuinfo");
2835 arch
= info
.bfd_arch_info
->arch
;
2836 mach
= bfd_mach_ppc_e500
;
2837 bfd_default_set_arch_mach (&abfd
, arch
, mach
);
2838 info
.bfd_arch_info
= bfd_get_arch_info (&abfd
);
2842 /* Find a default target description which describes our register
2843 layout, if we do not already have one. */
2844 if (! tdesc_has_registers (tdesc
))
2846 const struct variant
*v
;
2848 /* Choose variant. */
2849 v
= find_variant_by_arch (arch
, mach
);
2856 gdb_assert (tdesc_has_registers (tdesc
));
2858 /* Check any target description for validity. */
2859 if (tdesc_has_registers (tdesc
))
2861 static const char *const gprs
[] = {
2862 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2863 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
2864 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
2865 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
2867 static const char *const segment_regs
[] = {
2868 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
2869 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
2871 const struct tdesc_feature
*feature
;
2873 static const char *const msr_names
[] = { "msr", "ps" };
2874 static const char *const cr_names
[] = { "cr", "cnd" };
2875 static const char *const ctr_names
[] = { "ctr", "cnt" };
2877 feature
= tdesc_find_feature (tdesc
,
2878 "org.gnu.gdb.power.core");
2879 if (feature
== NULL
)
2882 tdesc_data
= tdesc_data_alloc ();
2885 for (i
= 0; i
< ppc_num_gprs
; i
++)
2886 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
, gprs
[i
]);
2887 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_PC_REGNUM
,
2889 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_LR_REGNUM
,
2891 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_XER_REGNUM
,
2894 /* Allow alternate names for these registers, to accomodate GDB's
2896 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
2897 PPC_MSR_REGNUM
, msr_names
);
2898 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
2899 PPC_CR_REGNUM
, cr_names
);
2900 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
2901 PPC_CTR_REGNUM
, ctr_names
);
2905 tdesc_data_cleanup (tdesc_data
);
2909 have_mq
= tdesc_numbered_register (feature
, tdesc_data
, PPC_MQ_REGNUM
,
2912 tdesc_wordsize
= tdesc_register_size (feature
, "pc") / 8;
2914 wordsize
= tdesc_wordsize
;
2916 feature
= tdesc_find_feature (tdesc
,
2917 "org.gnu.gdb.power.fpu");
2918 if (feature
!= NULL
)
2920 static const char *const fprs
[] = {
2921 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
2922 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
2923 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
2924 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
2927 for (i
= 0; i
< ppc_num_fprs
; i
++)
2928 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
2929 PPC_F0_REGNUM
+ i
, fprs
[i
]);
2930 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
2931 PPC_FPSCR_REGNUM
, "fpscr");
2935 tdesc_data_cleanup (tdesc_data
);
2943 /* The DFP pseudo-registers will be available when there are floating
2945 have_dfp
= have_fpu
;
2947 feature
= tdesc_find_feature (tdesc
,
2948 "org.gnu.gdb.power.altivec");
2949 if (feature
!= NULL
)
2951 static const char *const vector_regs
[] = {
2952 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
2953 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
2954 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
2955 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31"
2959 for (i
= 0; i
< ppc_num_gprs
; i
++)
2960 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
2963 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
2964 PPC_VSCR_REGNUM
, "vscr");
2965 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
2966 PPC_VRSAVE_REGNUM
, "vrsave");
2968 if (have_spe
|| !valid_p
)
2970 tdesc_data_cleanup (tdesc_data
);
2978 /* On machines supporting the SPE APU, the general-purpose registers
2979 are 64 bits long. There are SIMD vector instructions to treat them
2980 as pairs of floats, but the rest of the instruction set treats them
2981 as 32-bit registers, and only operates on their lower halves.
2983 In the GDB regcache, we treat their high and low halves as separate
2984 registers. The low halves we present as the general-purpose
2985 registers, and then we have pseudo-registers that stitch together
2986 the upper and lower halves and present them as pseudo-registers.
2988 Thus, the target description is expected to supply the upper
2989 halves separately. */
2991 feature
= tdesc_find_feature (tdesc
,
2992 "org.gnu.gdb.power.spe");
2993 if (feature
!= NULL
)
2995 static const char *const upper_spe
[] = {
2996 "ev0h", "ev1h", "ev2h", "ev3h",
2997 "ev4h", "ev5h", "ev6h", "ev7h",
2998 "ev8h", "ev9h", "ev10h", "ev11h",
2999 "ev12h", "ev13h", "ev14h", "ev15h",
3000 "ev16h", "ev17h", "ev18h", "ev19h",
3001 "ev20h", "ev21h", "ev22h", "ev23h",
3002 "ev24h", "ev25h", "ev26h", "ev27h",
3003 "ev28h", "ev29h", "ev30h", "ev31h"
3007 for (i
= 0; i
< ppc_num_gprs
; i
++)
3008 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
3009 PPC_SPE_UPPER_GP0_REGNUM
+ i
,
3011 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
3012 PPC_SPE_ACC_REGNUM
, "acc");
3013 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
3014 PPC_SPE_FSCR_REGNUM
, "spefscr");
3016 if (have_mq
|| have_fpu
|| !valid_p
)
3018 tdesc_data_cleanup (tdesc_data
);
3027 /* If we have a 64-bit binary on a 32-bit target, complain. Also
3028 complain for a 32-bit binary on a 64-bit target; we do not yet
3029 support that. For instance, the 32-bit ABI routines expect
3032 As long as there isn't an explicit target description, we'll
3033 choose one based on the BFD architecture and get a word size
3034 matching the binary (probably powerpc:common or
3035 powerpc:common64). So there is only trouble if a 64-bit target
3036 supplies a 64-bit description while debugging a 32-bit
3038 if (tdesc_wordsize
!= -1 && tdesc_wordsize
!= wordsize
)
3040 tdesc_data_cleanup (tdesc_data
);
3045 if (soft_float_flag
== AUTO_BOOLEAN_AUTO
&& from_elf_exec
)
3047 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
3048 Tag_GNU_Power_ABI_FP
))
3051 soft_float_flag
= AUTO_BOOLEAN_FALSE
;
3054 soft_float_flag
= AUTO_BOOLEAN_TRUE
;
3061 if (vector_abi
== POWERPC_VEC_AUTO
&& from_elf_exec
)
3063 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
3064 Tag_GNU_Power_ABI_Vector
))
3067 vector_abi
= POWERPC_VEC_GENERIC
;
3070 vector_abi
= POWERPC_VEC_ALTIVEC
;
3073 vector_abi
= POWERPC_VEC_SPE
;
3081 if (soft_float_flag
== AUTO_BOOLEAN_TRUE
)
3083 else if (soft_float_flag
== AUTO_BOOLEAN_FALSE
)
3086 soft_float
= !have_fpu
;
3088 /* If we have a hard float binary or setting but no floating point
3089 registers, downgrade to soft float anyway. We're still somewhat
3090 useful in this scenario. */
3091 if (!soft_float
&& !have_fpu
)
3094 /* Similarly for vector registers. */
3095 if (vector_abi
== POWERPC_VEC_ALTIVEC
&& !have_altivec
)
3096 vector_abi
= POWERPC_VEC_GENERIC
;
3098 if (vector_abi
== POWERPC_VEC_SPE
&& !have_spe
)
3099 vector_abi
= POWERPC_VEC_GENERIC
;
3101 if (vector_abi
== POWERPC_VEC_AUTO
)
3104 vector_abi
= POWERPC_VEC_ALTIVEC
;
3106 vector_abi
= POWERPC_VEC_SPE
;
3108 vector_abi
= POWERPC_VEC_GENERIC
;
3111 /* Do not limit the vector ABI based on available hardware, since we
3112 do not yet know what hardware we'll decide we have. Yuck! FIXME! */
3114 /* Find a candidate among extant architectures. */
3115 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
3117 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
3119 /* Word size in the various PowerPC bfd_arch_info structs isn't
3120 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
3121 separate word size check. */
3122 tdep
= gdbarch_tdep (arches
->gdbarch
);
3123 if (tdep
&& tdep
->soft_float
!= soft_float
)
3125 if (tdep
&& tdep
->vector_abi
!= vector_abi
)
3127 if (tdep
&& tdep
->wordsize
== wordsize
)
3129 if (tdesc_data
!= NULL
)
3130 tdesc_data_cleanup (tdesc_data
);
3131 return arches
->gdbarch
;
3135 /* None found, create a new architecture from INFO, whose bfd_arch_info
3136 validity depends on the source:
3137 - executable useless
3138 - rs6000_host_arch() good
3140 - "set arch" trust blindly
3141 - GDB startup useless but harmless */
3143 tdep
= XCALLOC (1, struct gdbarch_tdep
);
3144 tdep
->wordsize
= wordsize
;
3145 tdep
->soft_float
= soft_float
;
3146 tdep
->vector_abi
= vector_abi
;
3148 gdbarch
= gdbarch_alloc (&info
, tdep
);
3150 tdep
->ppc_gp0_regnum
= PPC_R0_REGNUM
;
3151 tdep
->ppc_toc_regnum
= PPC_R0_REGNUM
+ 2;
3152 tdep
->ppc_ps_regnum
= PPC_MSR_REGNUM
;
3153 tdep
->ppc_cr_regnum
= PPC_CR_REGNUM
;
3154 tdep
->ppc_lr_regnum
= PPC_LR_REGNUM
;
3155 tdep
->ppc_ctr_regnum
= PPC_CTR_REGNUM
;
3156 tdep
->ppc_xer_regnum
= PPC_XER_REGNUM
;
3157 tdep
->ppc_mq_regnum
= have_mq
? PPC_MQ_REGNUM
: -1;
3159 tdep
->ppc_fp0_regnum
= have_fpu
? PPC_F0_REGNUM
: -1;
3160 tdep
->ppc_fpscr_regnum
= have_fpu
? PPC_FPSCR_REGNUM
: -1;
3161 tdep
->ppc_vr0_regnum
= have_altivec
? PPC_VR0_REGNUM
: -1;
3162 tdep
->ppc_vrsave_regnum
= have_altivec
? PPC_VRSAVE_REGNUM
: -1;
3163 tdep
->ppc_ev0_upper_regnum
= have_spe
? PPC_SPE_UPPER_GP0_REGNUM
: -1;
3164 tdep
->ppc_acc_regnum
= have_spe
? PPC_SPE_ACC_REGNUM
: -1;
3165 tdep
->ppc_spefscr_regnum
= have_spe
? PPC_SPE_FSCR_REGNUM
: -1;
3167 set_gdbarch_pc_regnum (gdbarch
, PPC_PC_REGNUM
);
3168 set_gdbarch_sp_regnum (gdbarch
, PPC_R0_REGNUM
+ 1);
3169 set_gdbarch_deprecated_fp_regnum (gdbarch
, PPC_R0_REGNUM
+ 1);
3170 set_gdbarch_fp0_regnum (gdbarch
, tdep
->ppc_fp0_regnum
);
3171 set_gdbarch_register_sim_regno (gdbarch
, rs6000_register_sim_regno
);
3173 /* The XML specification for PowerPC sensibly calls the MSR "msr".
3174 GDB traditionally called it "ps", though, so let GDB add an
3176 set_gdbarch_ps_regnum (gdbarch
, tdep
->ppc_ps_regnum
);
3179 set_gdbarch_return_value (gdbarch
, ppc64_sysv_abi_return_value
);
3181 set_gdbarch_return_value (gdbarch
, ppc_sysv_abi_return_value
);
3183 /* Set lr_frame_offset. */
3185 tdep
->lr_frame_offset
= 16;
3187 tdep
->lr_frame_offset
= 4;
3189 if (have_spe
|| have_dfp
)
3191 set_gdbarch_pseudo_register_read (gdbarch
, rs6000_pseudo_register_read
);
3192 set_gdbarch_pseudo_register_write (gdbarch
, rs6000_pseudo_register_write
);
3195 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
3197 /* Select instruction printer. */
3198 if (arch
== bfd_arch_rs6000
)
3199 set_gdbarch_print_insn (gdbarch
, print_insn_rs6000
);
3201 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_powerpc
);
3203 set_gdbarch_num_regs (gdbarch
, PPC_NUM_REGS
);
3206 num_pseudoregs
+= 32;
3208 num_pseudoregs
+= 16;
3210 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudoregs
);
3212 set_gdbarch_ptr_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
3213 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
3214 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
3215 set_gdbarch_long_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
3216 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
3217 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
3218 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
3219 set_gdbarch_long_double_bit (gdbarch
, 16 * TARGET_CHAR_BIT
);
3220 set_gdbarch_char_signed (gdbarch
, 0);
3222 set_gdbarch_frame_align (gdbarch
, rs6000_frame_align
);
3225 set_gdbarch_frame_red_zone_size (gdbarch
, 288);
3227 set_gdbarch_convert_register_p (gdbarch
, rs6000_convert_register_p
);
3228 set_gdbarch_register_to_value (gdbarch
, rs6000_register_to_value
);
3229 set_gdbarch_value_to_register (gdbarch
, rs6000_value_to_register
);
3231 set_gdbarch_stab_reg_to_regnum (gdbarch
, rs6000_stab_reg_to_regnum
);
3232 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, rs6000_dwarf2_reg_to_regnum
);
3235 set_gdbarch_push_dummy_call (gdbarch
, ppc_sysv_abi_push_dummy_call
);
3236 else if (wordsize
== 8)
3237 set_gdbarch_push_dummy_call (gdbarch
, ppc64_sysv_abi_push_dummy_call
);
3239 set_gdbarch_skip_prologue (gdbarch
, rs6000_skip_prologue
);
3240 set_gdbarch_in_function_epilogue_p (gdbarch
, rs6000_in_function_epilogue_p
);
3242 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3243 set_gdbarch_breakpoint_from_pc (gdbarch
, rs6000_breakpoint_from_pc
);
3245 /* The value of symbols of type N_SO and N_FUN maybe null when
3247 set_gdbarch_sofun_address_maybe_missing (gdbarch
, 1);
3249 /* Handles single stepping of atomic sequences. */
3250 set_gdbarch_software_single_step (gdbarch
, ppc_deal_with_atomic_sequence
);
3252 /* Not sure on this. FIXMEmgo */
3253 set_gdbarch_frame_args_skip (gdbarch
, 8);
3255 /* Helpers for function argument information. */
3256 set_gdbarch_fetch_pointer_argument (gdbarch
, rs6000_fetch_pointer_argument
);
3259 set_gdbarch_in_solib_return_trampoline
3260 (gdbarch
, rs6000_in_solib_return_trampoline
);
3261 set_gdbarch_skip_trampoline_code (gdbarch
, rs6000_skip_trampoline_code
);
3263 /* Hook in the DWARF CFI frame unwinder. */
3264 dwarf2_append_unwinders (gdbarch
);
3265 dwarf2_frame_set_adjust_regnum (gdbarch
, rs6000_adjust_frame_regnum
);
3267 /* Frame handling. */
3268 dwarf2_frame_set_init_reg (gdbarch
, ppc_dwarf2_frame_init_reg
);
3270 /* Hook in ABI-specific overrides, if they have been registered. */
3271 info
.target_desc
= tdesc
;
3272 info
.tdep_info
= (void *) tdesc_data
;
3273 gdbarch_init_osabi (info
, gdbarch
);
3277 case GDB_OSABI_LINUX
:
3278 case GDB_OSABI_NETBSD_AOUT
:
3279 case GDB_OSABI_NETBSD_ELF
:
3280 case GDB_OSABI_UNKNOWN
:
3281 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
3282 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
3283 set_gdbarch_dummy_id (gdbarch
, rs6000_dummy_id
);
3284 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
3287 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
3289 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
3290 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
3291 set_gdbarch_dummy_id (gdbarch
, rs6000_dummy_id
);
3292 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
3295 set_tdesc_pseudo_register_type (gdbarch
, rs6000_pseudo_register_type
);
3296 set_tdesc_pseudo_register_reggroup_p (gdbarch
,
3297 rs6000_pseudo_register_reggroup_p
);
3298 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
3300 /* Override the normal target description method to make the SPE upper
3301 halves anonymous. */
3302 set_gdbarch_register_name (gdbarch
, rs6000_register_name
);
3304 /* Recording the numbering of pseudo registers. */
3305 tdep
->ppc_ev0_regnum
= have_spe
? gdbarch_num_regs (gdbarch
) : -1;
3307 /* Set the register number for _Decimal128 pseudo-registers. */
3308 tdep
->ppc_dl0_regnum
= have_dfp
? gdbarch_num_regs (gdbarch
) : -1;
3310 if (have_dfp
&& have_spe
)
3311 /* Put the _Decimal128 pseudo-registers after the SPE registers. */
3312 tdep
->ppc_dl0_regnum
+= 32;
3314 /* Setup displaced stepping. */
3315 set_gdbarch_displaced_step_copy_insn (gdbarch
,
3316 simple_displaced_step_copy_insn
);
3317 set_gdbarch_displaced_step_fixup (gdbarch
, ppc_displaced_step_fixup
);
3318 set_gdbarch_displaced_step_free_closure (gdbarch
,
3319 simple_displaced_step_free_closure
);
3320 set_gdbarch_displaced_step_location (gdbarch
,
3321 displaced_step_at_entry_point
);
3323 set_gdbarch_max_insn_length (gdbarch
, PPC_INSN_SIZE
);
3329 rs6000_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
3331 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3336 /* FIXME: Dump gdbarch_tdep. */
3339 /* PowerPC-specific commands. */
3342 set_powerpc_command (char *args
, int from_tty
)
3344 printf_unfiltered (_("\
3345 \"set powerpc\" must be followed by an appropriate subcommand.\n"));
3346 help_list (setpowerpccmdlist
, "set powerpc ", all_commands
, gdb_stdout
);
3350 show_powerpc_command (char *args
, int from_tty
)
3352 cmd_show_list (showpowerpccmdlist
, from_tty
, "");
3356 powerpc_set_soft_float (char *args
, int from_tty
,
3357 struct cmd_list_element
*c
)
3359 struct gdbarch_info info
;
3361 /* Update the architecture. */
3362 gdbarch_info_init (&info
);
3363 if (!gdbarch_update_p (info
))
3364 internal_error (__FILE__
, __LINE__
, "could not update architecture");
3368 powerpc_set_vector_abi (char *args
, int from_tty
,
3369 struct cmd_list_element
*c
)
3371 struct gdbarch_info info
;
3372 enum powerpc_vector_abi vector_abi
;
3374 for (vector_abi
= POWERPC_VEC_AUTO
;
3375 vector_abi
!= POWERPC_VEC_LAST
;
3377 if (strcmp (powerpc_vector_abi_string
,
3378 powerpc_vector_strings
[vector_abi
]) == 0)
3380 powerpc_vector_abi_global
= vector_abi
;
3384 if (vector_abi
== POWERPC_VEC_LAST
)
3385 internal_error (__FILE__
, __LINE__
, _("Invalid vector ABI accepted: %s."),
3386 powerpc_vector_abi_string
);
3388 /* Update the architecture. */
3389 gdbarch_info_init (&info
);
3390 if (!gdbarch_update_p (info
))
3391 internal_error (__FILE__
, __LINE__
, "could not update architecture");
3394 /* Initialization code. */
3396 extern initialize_file_ftype _initialize_rs6000_tdep
; /* -Wmissing-prototypes */
3399 _initialize_rs6000_tdep (void)
3401 gdbarch_register (bfd_arch_rs6000
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
3402 gdbarch_register (bfd_arch_powerpc
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
3404 /* Initialize the standard target descriptions. */
3405 initialize_tdesc_powerpc_32 ();
3406 initialize_tdesc_powerpc_altivec32 ();
3407 initialize_tdesc_powerpc_403 ();
3408 initialize_tdesc_powerpc_403gc ();
3409 initialize_tdesc_powerpc_505 ();
3410 initialize_tdesc_powerpc_601 ();
3411 initialize_tdesc_powerpc_602 ();
3412 initialize_tdesc_powerpc_603 ();
3413 initialize_tdesc_powerpc_604 ();
3414 initialize_tdesc_powerpc_64 ();
3415 initialize_tdesc_powerpc_altivec64 ();
3416 initialize_tdesc_powerpc_7400 ();
3417 initialize_tdesc_powerpc_750 ();
3418 initialize_tdesc_powerpc_860 ();
3419 initialize_tdesc_powerpc_e500 ();
3420 initialize_tdesc_rs6000 ();
3422 /* Add root prefix command for all "set powerpc"/"show powerpc"
3424 add_prefix_cmd ("powerpc", no_class
, set_powerpc_command
,
3425 _("Various PowerPC-specific commands."),
3426 &setpowerpccmdlist
, "set powerpc ", 0, &setlist
);
3428 add_prefix_cmd ("powerpc", no_class
, show_powerpc_command
,
3429 _("Various PowerPC-specific commands."),
3430 &showpowerpccmdlist
, "show powerpc ", 0, &showlist
);
3432 /* Add a command to allow the user to force the ABI. */
3433 add_setshow_auto_boolean_cmd ("soft-float", class_support
,
3434 &powerpc_soft_float_global
,
3435 _("Set whether to use a soft-float ABI."),
3436 _("Show whether to use a soft-float ABI."),
3438 powerpc_set_soft_float
, NULL
,
3439 &setpowerpccmdlist
, &showpowerpccmdlist
);
3441 add_setshow_enum_cmd ("vector-abi", class_support
, powerpc_vector_strings
,
3442 &powerpc_vector_abi_string
,
3443 _("Set the vector ABI."),
3444 _("Show the vector ABI."),
3445 NULL
, powerpc_set_vector_abi
, NULL
,
3446 &setpowerpccmdlist
, &showpowerpccmdlist
);