1 /* sh-stub.c -- debugging stub for the Hitachi-SH.
3 NOTE!! This code has to be compiled with optimization, otherwise the
4 function inlining which generates the exception handlers won't work.
8 /* This is originally based on an m68k software stub written by Glenn
9 Engel at HP, but has changed quite a bit.
11 Modifications for the SH by Ben Lee and Steve Chamberlain
15 /****************************************************************************
17 THIS SOFTWARE IS NOT COPYRIGHTED
19 HP offers the following for use in the public domain. HP makes no
20 warranty with regard to the software or it's performance and the
21 user accepts the software "AS IS" with all faults.
23 HP DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD
24 TO THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES
25 OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
27 ****************************************************************************/
30 /* Remote communication protocol.
32 A debug packet whose contents are <data>
33 is encapsulated for transmission in the form:
35 $ <data> # CSUM1 CSUM2
37 <data> must be ASCII alphanumeric and cannot include characters
38 '$' or '#'. If <data> starts with two characters followed by
39 ':', then the existing stubs interpret this as a sequence number.
41 CSUM1 and CSUM2 are ascii hex representation of an 8-bit
42 checksum of <data>, the most significant nibble is sent first.
43 the hex digits 0-9,a-f are used.
45 Receiver responds with:
47 + - if CSUM is correct and ready for next packet
48 - - if CSUM is incorrect
51 All values are encoded in ascii hex digits.
56 reply XX....X Each byte of register data
57 is described by two hex digits.
58 Registers are in the internal order
59 for GDB, and the bytes in a register
60 are in the same order the machine uses.
63 write regs GXX..XX Each byte of register data
64 is described by two hex digits.
68 write reg Pn...=r... Write register n... with value r...,
69 which contains two hex digits for each
70 byte in the register (target byte
74 (not supported by all stubs).
76 read mem mAA..AA,LLLL AA..AA is address, LLLL is length.
77 reply XX..XX XX..XX is mem contents
78 Can be fewer bytes than requested
79 if able to read only part of the data.
82 write mem MAA..AA,LLLL:XX..XX
84 LLLL is number of bytes,
87 ENN for an error (this includes the case
88 where only part of the data was
91 cont cAA..AA AA..AA is address to resume
93 resume at same address.
95 step sAA..AA AA..AA is address to resume
97 resume at same address.
99 last signal ? Reply the current reason for stopping.
100 This is the same reply as is generated
101 for step or cont : SAA where AA is the
104 There is no immediate reply to step or cont.
105 The reply comes when the machine stops.
106 It is SAA AA is the "signal number"
108 or... TAAn...:r...;n:r...;n...:r...;
110 n... = register number
111 r... = register contents
112 or... WAA The process exited, and AA is
113 the exit status. This is only
114 applicable for certains sorts of
118 toggle debug d toggle debug flag (see 386 & 68k stubs)
119 reset r reset -- see sparc stub.
120 reserved <other> On other requests, the stub should
121 ignore the request and send an empty
122 response ($#<checksum>). This way
123 we can extend the protocol and GDB
124 can tell whether the stub it is
125 talking to uses the old or the new.
126 search tAA:PP,MM Search backwards starting at address
127 AA for a match with pattern PP and
128 mask MM. PP and MM are 4 bytes.
129 Not supported by all stubs.
131 general query qXXXX Request info about XXXX.
132 general set QXXXX=yyyy Set value of XXXX to yyyy.
133 query sect offs qOffsets Get section offsets. Reply is
134 Text=xxx;Data=yyy;Bss=zzz
135 console output Otext Send text to stdout. Only comes from
138 Responses can be run-length encoded to save space. A '*' means that
139 the next character is an ASCII encoding giving a repeat count which
140 stands for that many repititions of the character preceding the '*'.
141 The encoding is n+29, yielding a printable character where n >=3
142 (which is where rle starts to win). Don't use an n > 126.
145 "0* " means the same as "0000". */
152 #define COND_BR_MASK 0xff00
153 #define UCOND_DBR_MASK 0xe000
154 #define UCOND_RBR_MASK 0xf0df
155 #define TRAPA_MASK 0xff00
157 #define COND_DISP 0x00ff
158 #define UCOND_DISP 0x0fff
159 #define UCOND_REG 0x0f00
161 #define BF_INSTR 0x8b00
162 #define BT_INSTR 0x8900
163 #define BRA_INSTR 0xa000
164 #define BSR_INSTR 0xb000
165 #define JMP_INSTR 0x402b
166 #define JSR_INSTR 0x400b
167 #define RTS_INSTR 0x000b
168 #define RTE_INSTR 0x002b
169 #define TRAPA_INSTR 0xc300
171 #define SSTEP_INSTR 0xc3ff
173 #define T_BIT_MASK 0x0001
175 * BUFMAX defines the maximum number of characters in inbound/outbound
176 * buffers at least NUMREGBYTES*2 are needed for register packets
181 * Number of bytes for registers
183 #define NUMREGBYTES 112 /* 92 */
188 typedef void (*Function
) ();
191 * Forward declarations
194 static int hex (char);
195 static char *mem2hex (char *, char *, int);
196 static char *hex2mem (char *, char *, int);
197 static int hexToInt (char **, int *);
198 static void getpacket (char *);
199 static void putpacket (char *);
200 static void handle_buserror (void);
201 static int computeSignal (int exceptionVector
);
202 static void handle_exception (int exceptionVector
);
206 int putDebugChar (char);
207 char getDebugChar (void);
209 /* These are in the file but in asm statements so the compiler can't see them */
210 void catch_exception_4 (void);
211 void catch_exception_6 (void);
212 void catch_exception_9 (void);
213 void catch_exception_10 (void);
214 void catch_exception_11 (void);
215 void catch_exception_32 (void);
216 void catch_exception_33 (void);
217 void catch_exception_255 (void);
221 #define catch_exception_random catch_exception_255 /* Treat all odd ones like 255 */
223 void breakpoint (void);
226 #define init_stack_size 8*1024 /* if you change this you should also modify BINIT */
227 #define stub_stack_size 8*1024
229 int init_stack
[init_stack_size
] __attribute__ ((section ("stack"))) = {0};
230 int stub_stack
[stub_stack_size
] __attribute__ ((section ("stack"))) = {0};
234 void (*func_cold
) ();
236 void (*func_warm
) ();
238 void (*(handler
[256 - 4])) ();
246 /* When you link take care that this is at address 0 -
247 or wherever your vbr points */
249 #define CPU_BUS_ERROR_VEC 9
250 #define DMA_BUS_ERROR_VEC 10
252 #define INVALID_INSN_VEC 4
253 #define INVALID_SLOT_VEC 6
259 #define BCR (*(volatile short *)(0x05FFFFA0)) /* Bus control register */
260 #define BAS (0x800) /* Byte access select */
261 #define WCR1 (*(volatile short *)(0x05ffffA2)) /* Wait state control register */
263 const vec_type vectable
=
265 &BINIT
, /* 0: Power-on reset PC */
266 init_stack
+ init_stack_size
, /* 1: Power-on reset SP */
267 &BINIT
, /* 2: Manual reset PC */
268 init_stack
+ init_stack_size
, /* 3: Manual reset SP */
270 &catch_exception_4
, /* 4: General invalid instruction */
271 &catch_exception_random
, /* 5: Reserved for system */
272 &catch_exception_6
, /* 6: Invalid slot instruction */
273 &catch_exception_random
, /* 7: Reserved for system */
274 &catch_exception_random
, /* 8: Reserved for system */
275 &catch_exception_9
, /* 9: CPU bus error */
276 &catch_exception_10
, /* 10: DMA bus error */
277 &catch_exception_11
, /* 11: NMI */
278 &catch_exception_random
, /* 12: User break */
279 &catch_exception_random
, /* 13: Reserved for system */
280 &catch_exception_random
, /* 14: Reserved for system */
281 &catch_exception_random
, /* 15: Reserved for system */
282 &catch_exception_random
, /* 16: Reserved for system */
283 &catch_exception_random
, /* 17: Reserved for system */
284 &catch_exception_random
, /* 18: Reserved for system */
285 &catch_exception_random
, /* 19: Reserved for system */
286 &catch_exception_random
, /* 20: Reserved for system */
287 &catch_exception_random
, /* 21: Reserved for system */
288 &catch_exception_random
, /* 22: Reserved for system */
289 &catch_exception_random
, /* 23: Reserved for system */
290 &catch_exception_random
, /* 24: Reserved for system */
291 &catch_exception_random
, /* 25: Reserved for system */
292 &catch_exception_random
, /* 26: Reserved for system */
293 &catch_exception_random
, /* 27: Reserved for system */
294 &catch_exception_random
, /* 28: Reserved for system */
295 &catch_exception_random
, /* 29: Reserved for system */
296 &catch_exception_random
, /* 30: Reserved for system */
297 &catch_exception_random
, /* 31: Reserved for system */
298 &catch_exception_32
, /* 32: Trap instr (user vectors) */
299 &catch_exception_33
, /* 33: Trap instr (user vectors) */
300 &catch_exception_random
, /* 34: Trap instr (user vectors) */
301 &catch_exception_random
, /* 35: Trap instr (user vectors) */
302 &catch_exception_random
, /* 36: Trap instr (user vectors) */
303 &catch_exception_random
, /* 37: Trap instr (user vectors) */
304 &catch_exception_random
, /* 38: Trap instr (user vectors) */
305 &catch_exception_random
, /* 39: Trap instr (user vectors) */
306 &catch_exception_random
, /* 40: Trap instr (user vectors) */
307 &catch_exception_random
, /* 41: Trap instr (user vectors) */
308 &catch_exception_random
, /* 42: Trap instr (user vectors) */
309 &catch_exception_random
, /* 43: Trap instr (user vectors) */
310 &catch_exception_random
, /* 44: Trap instr (user vectors) */
311 &catch_exception_random
, /* 45: Trap instr (user vectors) */
312 &catch_exception_random
, /* 46: Trap instr (user vectors) */
313 &catch_exception_random
, /* 47: Trap instr (user vectors) */
314 &catch_exception_random
, /* 48: Trap instr (user vectors) */
315 &catch_exception_random
, /* 49: Trap instr (user vectors) */
316 &catch_exception_random
, /* 50: Trap instr (user vectors) */
317 &catch_exception_random
, /* 51: Trap instr (user vectors) */
318 &catch_exception_random
, /* 52: Trap instr (user vectors) */
319 &catch_exception_random
, /* 53: Trap instr (user vectors) */
320 &catch_exception_random
, /* 54: Trap instr (user vectors) */
321 &catch_exception_random
, /* 55: Trap instr (user vectors) */
322 &catch_exception_random
, /* 56: Trap instr (user vectors) */
323 &catch_exception_random
, /* 57: Trap instr (user vectors) */
324 &catch_exception_random
, /* 58: Trap instr (user vectors) */
325 &catch_exception_random
, /* 59: Trap instr (user vectors) */
326 &catch_exception_random
, /* 60: Trap instr (user vectors) */
327 &catch_exception_random
, /* 61: Trap instr (user vectors) */
328 &catch_exception_random
, /* 62: Trap instr (user vectors) */
329 &catch_exception_random
, /* 63: Trap instr (user vectors) */
330 &catch_exception_random
, /* 64: IRQ0 */
331 &catch_exception_random
, /* 65: IRQ1 */
332 &catch_exception_random
, /* 66: IRQ2 */
333 &catch_exception_random
, /* 67: IRQ3 */
334 &catch_exception_random
, /* 68: IRQ4 */
335 &catch_exception_random
, /* 69: IRQ5 */
336 &catch_exception_random
, /* 70: IRQ6 */
337 &catch_exception_random
, /* 71: IRQ7 */
338 &catch_exception_random
,
339 &catch_exception_random
,
340 &catch_exception_random
,
341 &catch_exception_random
,
342 &catch_exception_random
,
343 &catch_exception_random
,
344 &catch_exception_random
,
345 &catch_exception_random
,
346 &catch_exception_random
,
347 &catch_exception_random
,
348 &catch_exception_random
,
349 &catch_exception_random
,
350 &catch_exception_random
,
351 &catch_exception_random
,
352 &catch_exception_random
,
353 &catch_exception_random
,
354 &catch_exception_random
,
355 &catch_exception_random
,
356 &catch_exception_random
,
357 &catch_exception_random
,
358 &catch_exception_random
,
359 &catch_exception_random
,
360 &catch_exception_random
,
361 &catch_exception_random
,
362 &catch_exception_random
,
363 &catch_exception_random
,
364 &catch_exception_random
,
365 &catch_exception_random
,
366 &catch_exception_random
,
367 &catch_exception_random
,
368 &catch_exception_random
,
369 &catch_exception_random
,
370 &catch_exception_random
,
371 &catch_exception_random
,
372 &catch_exception_random
,
373 &catch_exception_random
,
374 &catch_exception_random
,
375 &catch_exception_random
,
376 &catch_exception_random
,
377 &catch_exception_random
,
378 &catch_exception_random
,
379 &catch_exception_random
,
380 &catch_exception_random
,
381 &catch_exception_random
,
382 &catch_exception_random
,
383 &catch_exception_random
,
384 &catch_exception_random
,
385 &catch_exception_random
,
386 &catch_exception_random
,
387 &catch_exception_random
,
388 &catch_exception_random
,
389 &catch_exception_random
,
390 &catch_exception_random
,
391 &catch_exception_random
,
392 &catch_exception_random
,
393 &catch_exception_random
,
394 &catch_exception_random
,
395 &catch_exception_random
,
396 &catch_exception_random
,
397 &catch_exception_random
,
398 &catch_exception_random
,
399 &catch_exception_random
,
400 &catch_exception_random
,
401 &catch_exception_random
,
402 &catch_exception_random
,
403 &catch_exception_random
,
404 &catch_exception_random
,
405 &catch_exception_random
,
406 &catch_exception_random
,
407 &catch_exception_random
,
408 &catch_exception_random
,
409 &catch_exception_random
,
410 &catch_exception_random
,
411 &catch_exception_random
,
412 &catch_exception_random
,
413 &catch_exception_random
,
414 &catch_exception_random
,
415 &catch_exception_random
,
416 &catch_exception_random
,
417 &catch_exception_random
,
418 &catch_exception_random
,
419 &catch_exception_random
,
420 &catch_exception_random
,
421 &catch_exception_random
,
422 &catch_exception_random
,
423 &catch_exception_random
,
424 &catch_exception_random
,
425 &catch_exception_random
,
426 &catch_exception_random
,
427 &catch_exception_random
,
428 &catch_exception_random
,
429 &catch_exception_random
,
430 &catch_exception_random
,
431 &catch_exception_random
,
432 &catch_exception_random
,
433 &catch_exception_random
,
434 &catch_exception_random
,
435 &catch_exception_random
,
436 &catch_exception_random
,
437 &catch_exception_random
,
438 &catch_exception_random
,
439 &catch_exception_random
,
440 &catch_exception_random
,
441 &catch_exception_random
,
442 &catch_exception_random
,
443 &catch_exception_random
,
444 &catch_exception_random
,
445 &catch_exception_random
,
446 &catch_exception_random
,
447 &catch_exception_random
,
448 &catch_exception_random
,
449 &catch_exception_random
,
450 &catch_exception_random
,
451 &catch_exception_random
,
452 &catch_exception_random
,
453 &catch_exception_random
,
454 &catch_exception_random
,
455 &catch_exception_random
,
456 &catch_exception_random
,
457 &catch_exception_random
,
458 &catch_exception_random
,
459 &catch_exception_random
,
460 &catch_exception_random
,
461 &catch_exception_random
,
462 &catch_exception_random
,
463 &catch_exception_random
,
464 &catch_exception_random
,
465 &catch_exception_random
,
466 &catch_exception_random
,
467 &catch_exception_random
,
468 &catch_exception_random
,
469 &catch_exception_random
,
470 &catch_exception_random
,
471 &catch_exception_random
,
472 &catch_exception_random
,
473 &catch_exception_random
,
474 &catch_exception_random
,
475 &catch_exception_random
,
476 &catch_exception_random
,
477 &catch_exception_random
,
478 &catch_exception_random
,
479 &catch_exception_random
,
480 &catch_exception_random
,
481 &catch_exception_random
,
482 &catch_exception_random
,
483 &catch_exception_random
,
484 &catch_exception_random
,
485 &catch_exception_random
,
486 &catch_exception_random
,
487 &catch_exception_random
,
488 &catch_exception_random
,
489 &catch_exception_random
,
490 &catch_exception_random
,
491 &catch_exception_random
,
492 &catch_exception_random
,
493 &catch_exception_random
,
494 &catch_exception_random
,
495 &catch_exception_random
,
496 &catch_exception_random
,
497 &catch_exception_random
,
498 &catch_exception_random
,
499 &catch_exception_random
,
500 &catch_exception_random
,
501 &catch_exception_random
,
502 &catch_exception_random
,
503 &catch_exception_random
,
504 &catch_exception_random
,
505 &catch_exception_random
,
506 &catch_exception_random
,
507 &catch_exception_random
,
508 &catch_exception_random
,
509 &catch_exception_random
,
510 &catch_exception_random
,
511 &catch_exception_random
,
512 &catch_exception_random
,
513 &catch_exception_random
,
514 &catch_exception_random
,
515 &catch_exception_random
,
516 &catch_exception_random
,
517 &catch_exception_random
,
518 &catch_exception_random
,
519 &catch_exception_random
,
520 &catch_exception_random
,
521 &catch_exception_255
}};
524 char in_nmi
; /* Set when handling an NMI, so we don't reenter */
525 int dofault
; /* Non zero, bus errors will raise exception */
529 /* debug > 0 prints ill-formed commands in valid packets & checksum errors */
532 /* jump buffer used for setjmp/longjmp */
537 R0
, R1
, R2
, R3
, R4
, R5
, R6
, R7
,
538 R8
, R9
, R10
, R11
, R12
, R13
, R14
,
539 R15
, PC
, PR
, GBR
, VBR
, MACH
, MACL
, SR
,
540 TICKS
, STALLS
, CYCLES
, INSTS
, PLR
550 int registers
[NUMREGBYTES
/ 4];
551 stepData instrBuffer
;
553 static const char hexchars
[] = "0123456789abcdef";
554 char remcomInBuffer
[BUFMAX
];
555 char remcomOutBuffer
[BUFMAX
];
559 return hexchars
[(x
>> 4) & 0xf];
564 return hexchars
[x
& 0xf];
571 #define BREAKPOINT() asm("trapa #0x20"::);
575 * Routines to handle hex data
581 if ((ch
>= 'a') && (ch
<= 'f'))
582 return (ch
- 'a' + 10);
583 if ((ch
>= '0') && (ch
<= '9'))
585 if ((ch
>= 'A') && (ch
<= 'F'))
586 return (ch
- 'A' + 10);
590 /* convert the memory, pointed to by mem into hex, placing result in buf */
591 /* return a pointer to the last char put in buf (null) */
593 mem2hex (char *mem
, char *buf
, int count
)
597 for (i
= 0; i
< count
; i
++)
600 *buf
++ = highhex (ch
);
601 *buf
++ = lowhex (ch
);
607 /* convert the hex array pointed to by buf into binary, to be placed in mem */
608 /* return a pointer to the character after the last byte written */
611 hex2mem (char *buf
, char *mem
, int count
)
615 for (i
= 0; i
< count
; i
++)
617 ch
= hex (*buf
++) << 4;
618 ch
= ch
+ hex (*buf
++);
624 /**********************************************/
625 /* WHILE WE FIND NICE HEX CHARS, BUILD AN INT */
626 /* RETURN NUMBER OF CHARS PROCESSED */
627 /**********************************************/
629 hexToInt (char **ptr
, int *intValue
)
638 hexValue
= hex (**ptr
);
641 *intValue
= (*intValue
<< 4) | hexValue
;
654 * Routines to get and put packets
657 /* scan for the sequence $<data>#<checksum> */
661 getpacket (char *buffer
)
663 unsigned char checksum
;
664 unsigned char xmitcsum
;
670 /* wait around for the start character, ignore all other characters */
671 while ((ch
= getDebugChar ()) != '$');
677 /* now, read until a # or end of buffer is found */
678 while (count
< BUFMAX
)
680 ch
= getDebugChar ();
683 checksum
= checksum
+ ch
;
691 xmitcsum
= hex (getDebugChar ()) << 4;
692 xmitcsum
+= hex (getDebugChar ());
693 if (checksum
!= xmitcsum
)
694 putDebugChar ('-'); /* failed checksum */
697 putDebugChar ('+'); /* successful transfer */
698 /* if a sequence char is present, reply the sequence ID */
699 if (buffer
[2] == ':')
701 putDebugChar (buffer
[0]);
702 putDebugChar (buffer
[1]);
703 /* remove sequence chars from buffer */
704 count
= strlen (buffer
);
705 for (i
= 3; i
<= count
; i
++)
706 buffer
[i
- 3] = buffer
[i
];
711 while (checksum
!= xmitcsum
);
716 /* send the packet in buffer. The host get's one chance to read it.
717 This routine does not wait for a positive acknowledge. */
720 putpacket (register char *buffer
)
722 register int checksum
;
725 /* $<packet info>#<checksum>. */
736 /* Do run length encoding */
737 for (runlen
= 0; runlen
< 100; runlen
++)
739 if (src
[0] != src
[runlen
])
744 /* Got a useful amount */
749 checksum
+= (encode
= runlen
+ ' ' - 4);
750 putDebugChar (encode
);
766 putDebugChar (highhex(checksum
));
767 putDebugChar (lowhex(checksum
));
769 while (getDebugChar() != '+');
774 /* a bus error has occurred, perform a longjmp
775 to return execution and allow handling of the error */
778 handle_buserror (void)
780 longjmp (remcomEnv
, 1);
784 * this function takes the SH-1 exception number and attempts to
785 * translate this number into a unix compatible signal value
788 computeSignal (int exceptionVector
)
791 switch (exceptionVector
)
793 case INVALID_INSN_VEC
:
796 case INVALID_SLOT_VEC
:
799 case CPU_BUS_ERROR_VEC
:
802 case DMA_BUS_ERROR_VEC
:
815 sigval
= 7; /* "software generated"*/
827 unsigned short opcode
;
829 instrMem
= (short *) registers
[PC
];
834 if ((opcode
& COND_BR_MASK
) == BT_INSTR
)
836 if (registers
[SR
] & T_BIT_MASK
)
838 displacement
= (opcode
& COND_DISP
) << 1;
839 if (displacement
& 0x80)
840 displacement
|= 0xffffff00;
842 * Remember PC points to second instr.
843 * after PC of branch ... so add 4
845 instrMem
= (short *) (registers
[PC
] + displacement
+ 4);
850 else if ((opcode
& COND_BR_MASK
) == BF_INSTR
)
852 if (registers
[SR
] & T_BIT_MASK
)
856 displacement
= (opcode
& COND_DISP
) << 1;
857 if (displacement
& 0x80)
858 displacement
|= 0xffffff00;
860 * Remember PC points to second instr.
861 * after PC of branch ... so add 4
863 instrMem
= (short *) (registers
[PC
] + displacement
+ 4);
866 else if ((opcode
& UCOND_DBR_MASK
) == BRA_INSTR
)
868 displacement
= (opcode
& UCOND_DISP
) << 1;
869 if (displacement
& 0x0800)
870 displacement
|= 0xfffff000;
873 * Remember PC points to second instr.
874 * after PC of branch ... so add 4
876 instrMem
= (short *) (registers
[PC
] + displacement
+ 4);
878 else if ((opcode
& UCOND_RBR_MASK
) == JSR_INSTR
)
880 reg
= (char) ((opcode
& UCOND_REG
) >> 8);
882 instrMem
= (short *) registers
[reg
];
884 else if (opcode
== RTS_INSTR
)
885 instrMem
= (short *) registers
[PR
];
886 else if (opcode
== RTE_INSTR
)
887 instrMem
= (short *) registers
[15];
888 else if ((opcode
& TRAPA_MASK
) == TRAPA_INSTR
)
889 instrMem
= (short *) ((opcode
& ~TRAPA_MASK
) << 2);
893 instrBuffer
.memAddr
= instrMem
;
894 instrBuffer
.oldInstr
= *instrMem
;
895 *instrMem
= SSTEP_INSTR
;
902 If we single stepped,
903 restore the old instruction!
907 instrMem
= instrBuffer
.memAddr
;
908 *instrMem
= instrBuffer
.oldInstr
;
914 This function does all exception handling. It only does two things -
915 it figures out why it was called and tells gdb, and then it reacts
918 When in the monitor mode we talk a human on the serial line rather than gdb.
924 gdb_handle_exception (int exceptionVector
)
930 /* reply to host that an exception has occurred */
931 sigval
= computeSignal (exceptionVector
);
932 remcomOutBuffer
[0] = 'S';
933 remcomOutBuffer
[1] = highhex(sigval
);
934 remcomOutBuffer
[2] = lowhex (sigval
);
935 remcomOutBuffer
[3] = 0;
937 putpacket (remcomOutBuffer
);
940 * exception 255 indicates a software trap
941 * inserted in place of code ... so back up
942 * PC by one instruction, since this instruction
943 * will later be replaced by its original one!
945 if (exceptionVector
== 0xff
946 || exceptionVector
== 0x20)
950 * Do the thangs needed to undo
951 * any stepping we may have done!
957 remcomOutBuffer
[0] = 0;
958 getpacket (remcomInBuffer
);
960 switch (remcomInBuffer
[0])
963 remcomOutBuffer
[0] = 'S';
964 remcomOutBuffer
[1] = highhex (sigval
);
965 remcomOutBuffer
[2] = lowhex (sigval
);
966 remcomOutBuffer
[3] = 0;
969 remote_debug
= !(remote_debug
); /* toggle debug flag */
971 case 'g': /* return the value of the CPU registers */
972 mem2hex ((char *) registers
, remcomOutBuffer
, NUMREGBYTES
);
974 case 'G': /* set the value of the CPU registers - return OK */
975 hex2mem (&remcomInBuffer
[1], (char *) registers
, NUMREGBYTES
);
976 strcpy (remcomOutBuffer
, "OK");
979 /* mAA..AA,LLLL Read LLLL bytes at address AA..AA */
981 if (setjmp (remcomEnv
) == 0)
984 /* TRY, TO READ %x,%x. IF SUCCEED, SET PTR = 0 */
985 ptr
= &remcomInBuffer
[1];
986 if (hexToInt (&ptr
, &addr
))
988 if (hexToInt (&ptr
, &length
))
991 mem2hex ((char *) addr
, remcomOutBuffer
, length
);
994 strcpy (remcomOutBuffer
, "E01");
997 strcpy (remcomOutBuffer
, "E03");
999 /* restore handler for bus error */
1003 /* MAA..AA,LLLL: Write LLLL bytes at address AA.AA return OK */
1005 if (setjmp (remcomEnv
) == 0)
1009 /* TRY, TO READ '%x,%x:'. IF SUCCEED, SET PTR = 0 */
1010 ptr
= &remcomInBuffer
[1];
1011 if (hexToInt (&ptr
, &addr
))
1012 if (*(ptr
++) == ',')
1013 if (hexToInt (&ptr
, &length
))
1014 if (*(ptr
++) == ':')
1016 hex2mem (ptr
, (char *) addr
, length
);
1018 strcpy (remcomOutBuffer
, "OK");
1021 strcpy (remcomOutBuffer
, "E02");
1024 strcpy (remcomOutBuffer
, "E03");
1026 /* restore handler for bus error */
1030 /* cAA..AA Continue at address AA..AA(optional) */
1031 /* sAA..AA Step one instruction from AA..AA(optional) */
1035 /* tRY, to read optional parameter, pc unchanged if no parm */
1036 ptr
= &remcomInBuffer
[1];
1037 if (hexToInt (&ptr
, &addr
))
1038 registers
[PC
] = addr
;
1040 if (remcomInBuffer
[0] == 's')
1046 /* kill the program */
1047 case 'k': /* do nothing */
1051 /* reply to the request */
1052 putpacket (remcomOutBuffer
);
1057 #define GDBCOOKIE 0x5ac
1058 static int ingdbmode
;
1059 /* We've had an exception - choose to go into the monitor or
1061 void handle_exception(int exceptionVector
)
1064 if (ingdbmode
!= GDBCOOKIE
)
1065 monitor_handle_exception (exceptionVector
);
1068 gdb_handle_exception (exceptionVector
);
1075 ingdbmode
= GDBCOOKIE
;
1078 /* This function will generate a breakpoint exception. It is used at the
1079 beginning of a program to sync up with a debugger and can be used
1080 otherwise as a quick means to stop program execution and "break" into
1089 asm ("_BINIT: mov.l L1,r15");
1092 asm ("L1: .long _init_stack + 8*1024*4");
1096 /* First turn on the ram */
1097 WCR1
= 0; /* Never sample wait */
1098 BCR
= BAS
; /* use lowbyte/high byte */
1111 stub_sp
= stub_stack
+ stub_stack_size
;
1123 /* Calling Reset does the same as pressing the button */
1124 asm (".global _Reset
1132 L_sp: .long _init_stack + 8000");
1135 mov.l @(L_reg, pc), r0
1136 mov.l @r15+, r1 ! pop R0
1137 mov.l r2, @(0x08, r0) ! save R2
1138 mov.l r1, @r0 ! save R0
1139 mov.l @r15+, r1 ! pop R1
1140 mov.l r3, @(0x0c, r0) ! save R3
1141 mov.l r1, @(0x04, r0) ! save R1
1142 mov.l r4, @(0x10, r0) ! save R4
1143 mov.l r5, @(0x14, r0) ! save R5
1144 mov.l r6, @(0x18, r0) ! save R6
1145 mov.l r7, @(0x1c, r0) ! save R7
1146 mov.l r8, @(0x20, r0) ! save R8
1147 mov.l r9, @(0x24, r0) ! save R9
1148 mov.l r10, @(0x28, r0) ! save R10
1149 mov.l r11, @(0x2c, r0) ! save R11
1150 mov.l r12, @(0x30, r0) ! save R12
1151 mov.l r13, @(0x34, r0) ! save R13
1152 mov.l r14, @(0x38, r0) ! save R14
1153 mov.l @r15+, r4 ! save arg to handleException
1154 add #8, r15 ! hide PC/SR values on stack
1155 mov.l r15, @(0x3c, r0) ! save R15
1156 add #-8, r15 ! save still needs old SP value
1157 add #92, r0 ! readjust register pointer
1160 mov.l @r2, r2 ! R2 has SR
1161 mov.l @r15, r1 ! R1 has PC
1162 mov.l r2, @-r0 ! save SR
1163 sts.l macl, @-r0 ! save MACL
1164 sts.l mach, @-r0 ! save MACH
1165 stc.l vbr, @-r0 ! save VBR
1166 stc.l gbr, @-r0 ! save GBR
1167 sts.l pr, @-r0 ! save PR
1168 mov.l @(L_stubstack, pc), r2
1169 mov.l @(L_hdl_except, pc), r3
1172 mov.l r1, @-r0 ! save PC
1173 mov.l @(L_stubstack, pc), r0
1174 mov.l @(L_reg, pc), r1
1175 bra restoreRegisters
1176 mov.l r15, @r0 ! save __stub_stack
1184 .long _handle_exception");
1196 add #8, r1 ! skip to R2
1197 mov.l @r1+, r2 ! restore R2
1198 mov.l @r1+, r3 ! restore R3
1199 mov.l @r1+, r4 ! restore R4
1200 mov.l @r1+, r5 ! restore R5
1201 mov.l @r1+, r6 ! restore R6
1202 mov.l @r1+, r7 ! restore R7
1203 mov.l @r1+, r8 ! restore R8
1204 mov.l @r1+, r9 ! restore R9
1205 mov.l @r1+, r10 ! restore R10
1206 mov.l @r1+, r11 ! restore R11
1207 mov.l @r1+, r12 ! restore R12
1208 mov.l @r1+, r13 ! restore R13
1209 mov.l @r1+, r14 ! restore R14
1210 mov.l @r1+, r15 ! restore programs stack
1212 add #-8, r15 ! uncover PC/SR on stack
1213 mov.l r0, @r15 ! restore PC onto stack
1214 lds.l @r1+, pr ! restore PR
1215 ldc.l @r1+, gbr ! restore GBR
1216 ldc.l @r1+, vbr ! restore VBR
1217 lds.l @r1+, mach ! restore MACH
1218 lds.l @r1+, macl ! restore MACL
1220 add #-88, r1 ! readjust reg pointer to R1
1221 mov.l r0, @(4, r15) ! restore SR onto stack+4
1227 mov.l @r1+, r0 ! restore R0
1229 mov.l @r1, r1 ! restore R1
1235 static __inline__
void code_for_catch_exception(int n
)
1237 asm(" .globl _catch_exception_%O0" : : "i" (n
) );
1238 asm(" _catch_exception_%O0:" :: "i" (n
) );
1240 asm(" add #-4, r15 ! reserve spot on stack ");
1241 asm(" mov.l r1, @-r15 ! push R1 ");
1245 /* Special case for NMI - make sure that they don't nest */
1246 asm(" mov.l r0, @-r15 ! push R0");
1247 asm(" mov.l L_in_nmi, r0");
1248 asm(" tas.b @r0 ! Fend off against addtnl NMIs");
1250 asm(" mov.l @r15+, r0");
1251 asm(" mov.l @r15+, r1");
1252 asm(" add #4, r15");
1256 asm("L_in_nmi: .long _in_nmi");
1262 if (n
== CPU_BUS_ERROR_VEC
)
1264 /* Exception 9 (bus errors) are disasbleable - so that you
1265 can probe memory and get zero instead of a fault.
1266 Because the vector table may be in ROM we don't revector
1267 the interrupt like all the other stubs, we check in here
1269 asm("mov.l L_dofault,r1");
1270 asm("mov.l @r1,r1");
1272 asm("bf faultaway");
1273 asm("bsr _handle_buserror");
1275 asm("L_dofault: .long _dofault");
1278 asm(" mov #15<<4, r1 ");
1279 asm(" ldc r1, sr ! disable interrupts ");
1280 asm(" mov.l r0, @-r15 ! push R0 ");
1283 /* Prepare for saving context, we've already pushed r0 and r1, stick exception number
1285 asm(" mov r15, r0 ");
1286 asm(" add #8, r0 ");
1287 asm(" mov %0,r1" :: "i" (n
) );
1288 asm(" extu.b r1,r1 ");
1289 asm(" bra saveRegisters ! save register values ");
1290 asm(" mov.l r1, @r0 ! save exception # ");
1297 code_for_catch_exception (CPU_BUS_ERROR_VEC
);
1298 code_for_catch_exception (DMA_BUS_ERROR_VEC
);
1299 code_for_catch_exception (INVALID_INSN_VEC
);
1300 code_for_catch_exception (INVALID_SLOT_VEC
);
1301 code_for_catch_exception (NMI_VEC
);
1302 code_for_catch_exception (TRAP_VEC
);
1303 code_for_catch_exception (USER_VEC
);
1304 code_for_catch_exception (IO_VEC
);
1312 /* Support for Serial I/O using on chip uart */
1314 #define SMR0 (*(volatile char *)(0x05FFFEC0)) /* Channel 0 serial mode register */
1315 #define BRR0 (*(volatile char *)(0x05FFFEC1)) /* Channel 0 bit rate register */
1316 #define SCR0 (*(volatile char *)(0x05FFFEC2)) /* Channel 0 serial control register */
1317 #define TDR0 (*(volatile char *)(0x05FFFEC3)) /* Channel 0 transmit data register */
1318 #define SSR0 (*(volatile char *)(0x05FFFEC4)) /* Channel 0 serial status register */
1319 #define RDR0 (*(volatile char *)(0x05FFFEC5)) /* Channel 0 receive data register */
1321 #define SMR1 (*(volatile char *)(0x05FFFEC8)) /* Channel 1 serial mode register */
1322 #define BRR1 (*(volatile char *)(0x05FFFEC9)) /* Channel 1 bit rate register */
1323 #define SCR1 (*(volatile char *)(0x05FFFECA)) /* Channel 1 serial control register */
1324 #define TDR1 (*(volatile char *)(0x05FFFECB)) /* Channel 1 transmit data register */
1325 #define SSR1 (*(volatile char *)(0x05FFFECC)) /* Channel 1 serial status register */
1326 #define RDR1 (*(volatile char *)(0x05FFFECD)) /* Channel 1 receive data register */
1329 * Serial mode register bits
1332 #define SYNC_MODE 0x80
1333 #define SEVEN_BIT_DATA 0x40
1334 #define PARITY_ON 0x20
1335 #define ODD_PARITY 0x10
1336 #define STOP_BITS_2 0x08
1337 #define ENABLE_MULTIP 0x04
1343 * Serial control register bits
1345 #define SCI_TIE 0x80 /* Transmit interrupt enable */
1346 #define SCI_RIE 0x40 /* Receive interrupt enable */
1347 #define SCI_TE 0x20 /* Transmit enable */
1348 #define SCI_RE 0x10 /* Receive enable */
1349 #define SCI_MPIE 0x08 /* Multiprocessor interrupt enable */
1350 #define SCI_TEIE 0x04 /* Transmit end interrupt enable */
1351 #define SCI_CKE1 0x02 /* Clock enable 1 */
1352 #define SCI_CKE0 0x01 /* Clock enable 0 */
1355 * Serial status register bits
1357 #define SCI_TDRE 0x80 /* Transmit data register empty */
1358 #define SCI_RDRF 0x40 /* Receive data register full */
1359 #define SCI_ORER 0x20 /* Overrun error */
1360 #define SCI_FER 0x10 /* Framing error */
1361 #define SCI_PER 0x08 /* Parity error */
1362 #define SCI_TEND 0x04 /* Transmit end */
1363 #define SCI_MPB 0x02 /* Multiprocessor bit */
1364 #define SCI_MPBT 0x01 /* Multiprocessor bit transfer */
1368 * Port B IO Register (PBIOR)
1370 #define PBIOR (*(volatile char *)(0x05FFFFC6))
1371 #define PB15IOR 0x8000
1372 #define PB14IOR 0x4000
1373 #define PB13IOR 0x2000
1374 #define PB12IOR 0x1000
1375 #define PB11IOR 0x0800
1376 #define PB10IOR 0x0400
1377 #define PB9IOR 0x0200
1378 #define PB8IOR 0x0100
1379 #define PB7IOR 0x0080
1380 #define PB6IOR 0x0040
1381 #define PB5IOR 0x0020
1382 #define PB4IOR 0x0010
1383 #define PB3IOR 0x0008
1384 #define PB2IOR 0x0004
1385 #define PB1IOR 0x0002
1386 #define PB0IOR 0x0001
1389 * Port B Control Register (PBCR1)
1391 #define PBCR1 (*(volatile short *)(0x05FFFFCC))
1392 #define PB15MD1 0x8000
1393 #define PB15MD0 0x4000
1394 #define PB14MD1 0x2000
1395 #define PB14MD0 0x1000
1396 #define PB13MD1 0x0800
1397 #define PB13MD0 0x0400
1398 #define PB12MD1 0x0200
1399 #define PB12MD0 0x0100
1400 #define PB11MD1 0x0080
1401 #define PB11MD0 0x0040
1402 #define PB10MD1 0x0020
1403 #define PB10MD0 0x0010
1404 #define PB9MD1 0x0008
1405 #define PB9MD0 0x0004
1406 #define PB8MD1 0x0002
1407 #define PB8MD0 0x0001
1409 #define PB15MD PB15MD1|PB14MD0
1410 #define PB14MD PB14MD1|PB14MD0
1411 #define PB13MD PB13MD1|PB13MD0
1412 #define PB12MD PB12MD1|PB12MD0
1413 #define PB11MD PB11MD1|PB11MD0
1414 #define PB10MD PB10MD1|PB10MD0
1415 #define PB9MD PB9MD1|PB9MD0
1416 #define PB8MD PB8MD1|PB8MD0
1418 #define PB_TXD1 PB11MD1
1419 #define PB_RXD1 PB10MD1
1420 #define PB_TXD0 PB9MD1
1421 #define PB_RXD0 PB8MD1
1424 * Port B Control Register (PBCR2)
1426 #define PBCR2 0x05FFFFCE
1427 #define PB7MD1 0x8000
1428 #define PB7MD0 0x4000
1429 #define PB6MD1 0x2000
1430 #define PB6MD0 0x1000
1431 #define PB5MD1 0x0800
1432 #define PB5MD0 0x0400
1433 #define PB4MD1 0x0200
1434 #define PB4MD0 0x0100
1435 #define PB3MD1 0x0080
1436 #define PB3MD0 0x0040
1437 #define PB2MD1 0x0020
1438 #define PB2MD0 0x0010
1439 #define PB1MD1 0x0008
1440 #define PB1MD0 0x0004
1441 #define PB0MD1 0x0002
1442 #define PB0MD0 0x0001
1444 #define PB7MD PB7MD1|PB7MD0
1445 #define PB6MD PB6MD1|PB6MD0
1446 #define PB5MD PB5MD1|PB5MD0
1447 #define PB4MD PB4MD1|PB4MD0
1448 #define PB3MD PB3MD1|PB3MD0
1449 #define PB2MD PB2MD1|PB2MD0
1450 #define PB1MD PB1MD1|PB1MD0
1451 #define PB0MD PB0MD1|PB0MD0
1455 #define BPS 32 * 9600 * MHZ / ( BAUD * 10)
1457 #define BPS 32 /* 9600 for 10 Mhz */
1460 char getDebugChar (void);
1461 int putDebugChar (char);
1462 void handleError (char theSSR
);
1474 /* Clear TE and RE in Channel 1's SCR */
1475 SCR1
&= ~(SCI_TE
| SCI_RE
);
1477 /* Set communication to be async, 8-bit data, no parity, 1 stop bit and use internal clock */
1482 SCR1
&= ~(SCI_CKE1
| SCI_CKE0
);
1484 /* let the hardware settle */
1486 for (i
= 0; i
< 1000; i
++)
1489 /* Turn on in and out */
1490 SCR1
|= SCI_RE
| SCI_TE
;
1492 /* Set the PFC to make RXD1 (pin PB8) an input pin and TXD1 (pin PB9) an output pin */
1493 PBCR1
&= ~(PB_TXD1
| PB_RXD1
);
1494 PBCR1
|= PB_TXD1
| PB_RXD1
;
1499 getDebugCharReady (void)
1502 mySSR
= SSR1
& ( SCI_PER
| SCI_FER
| SCI_ORER
);
1504 handleError ( mySSR
);
1505 return SSR1
& SCI_RDRF
;
1514 while ( ! getDebugCharReady())
1520 mySSR
= SSR1
& (SCI_PER
| SCI_FER
| SCI_ORER
);
1523 handleError (mySSR
);
1531 return (SSR1
& SCI_TDRE
);
1535 putDebugChar (char ch
)
1537 while (!putDebugCharReady())
1541 * Write data into TDR and clear TDRE
1549 handleError (char theSSR
)
1551 SSR1
&= ~(SCI_ORER
| SCI_PER
| SCI_FER
);
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