gdb/sh-tdep.c

   1 /* Target-dependent code for Renesas Super-H, for GDB.
   2
   3    Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
   4    2003, 2004, 2005, 2007 Free Software Foundation, Inc.
   5
   6    This file is part of GDB.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 2 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street, Fifth Floor,
  21    Boston, MA 02110-1301, USA.  */
  22
  23 /*
  24    Contributed by Steve Chamberlain
  25    sac@cygnus.com
  26  */
  27
  28 #include "defs.h"
  29 #include "frame.h"
  30 #include "frame-base.h"
  31 #include "frame-unwind.h"
  32 #include "dwarf2-frame.h"
  33 #include "symtab.h"
  34 #include "gdbtypes.h"
  35 #include "gdbcmd.h"
  36 #include "gdbcore.h"
  37 #include "value.h"
  38 #include "dis-asm.h"
  39 #include "inferior.h"
  40 #include "gdb_string.h"
  41 #include "gdb_assert.h"
  42 #include "arch-utils.h"
  43 #include "floatformat.h"
  44 #include "regcache.h"
  45 #include "doublest.h"
  46 #include "osabi.h"
  47 #include "reggroups.h"
  48
  49 #include "sh-tdep.h"
  50
  51 #include "elf-bfd.h"
  52 #include "solib-svr4.h"
  53
  54 /* sh flags */
  55 #include "elf/sh.h"
  56 /* registers numbers shared with the simulator */
  57 #include "gdb/sim-sh.h"
  58
  59 static void (*sh_show_regs) (struct frame_info *);
  60
  61 #define SH_NUM_REGS 67
  62
  63 struct sh_frame_cache
  64 {
  65   /* Base address.  */
  66   CORE_ADDR base;
  67   LONGEST sp_offset;
  68   CORE_ADDR pc;
  69
  70   /* Flag showing that a frame has been created in the prologue code. */
  71   int uses_fp;
  72
  73   /* Saved registers.  */
  74   CORE_ADDR saved_regs[SH_NUM_REGS];
  75   CORE_ADDR saved_sp;
  76 };
  77
  78 static const char *
  79 sh_sh_register_name (int reg_nr)
  80 {
  81   static char *register_names[] = {
  82     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
  83     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
  84     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
  85     "", "",
  86     "", "", "", "", "", "", "", "",
  87     "", "", "", "", "", "", "", "",
  88     "", "",
  89     "", "", "", "", "", "", "", "",
  90     "", "", "", "", "", "", "", "",
  91     "", "", "", "", "", "", "", "",
  92   };
  93   if (reg_nr < 0)
  94     return NULL;
  95   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
  96     return NULL;
  97   return register_names[reg_nr];
  98 }
  99
 100 static const char *
 101 sh_sh3_register_name (int reg_nr)
 102 {
 103   static char *register_names[] = {
 104     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 105     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 106     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
 107     "", "",
 108     "", "", "", "", "", "", "", "",
 109     "", "", "", "", "", "", "", "",
 110     "ssr", "spc",
 111     "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
 112     "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
 113     "", "", "", "", "", "", "", "",
 114   };
 115   if (reg_nr < 0)
 116     return NULL;
 117   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
 118     return NULL;
 119   return register_names[reg_nr];
 120 }
 121
 122 static const char *
 123 sh_sh3e_register_name (int reg_nr)
 124 {
 125   static char *register_names[] = {
 126     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 127     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 128     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
 129     "fpul", "fpscr",
 130     "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
 131     "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
 132     "ssr", "spc",
 133     "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
 134     "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
 135     "", "", "", "", "", "", "", "",
 136   };
 137   if (reg_nr < 0)
 138     return NULL;
 139   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
 140     return NULL;
 141   return register_names[reg_nr];
 142 }
 143
 144 static const char *
 145 sh_sh2e_register_name (int reg_nr)
 146 {
 147   static char *register_names[] = {
 148     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 149     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 150     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
 151     "fpul", "fpscr",
 152     "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
 153     "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
 154     "", "",
 155     "", "", "", "", "", "", "", "",
 156     "", "", "", "", "", "", "", "",
 157     "", "", "", "", "", "", "", "",
 158   };
 159   if (reg_nr < 0)
 160     return NULL;
 161   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
 162     return NULL;
 163   return register_names[reg_nr];
 164 }
 165
 166 static const char *
 167 sh_sh2a_register_name (int reg_nr)
 168 {
 169   static char *register_names[] = {
 170     /* general registers 0-15 */
 171     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 172     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 173     /* 16 - 22 */
 174     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
 175     /* 23, 24 */
 176     "fpul", "fpscr",
 177     /* floating point registers 25 - 40 */
 178     "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
 179     "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
 180     /* 41, 42 */
 181     "", "",
 182     /* 43 - 62.  Banked registers.  The bank number used is determined by
 183        the bank register (63). */
 184     "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
 185     "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
 186     "machb", "ivnb", "prb", "gbrb", "maclb",
 187     /* 63: register bank number, not a real register but used to
 188        communicate the register bank currently get/set.  This register
 189        is hidden to the user, who manipulates it using the pseudo
 190        register called "bank" (67).  See below.  */
 191     "",
 192     /* 64 - 66 */
 193     "ibcr", "ibnr", "tbr",
 194     /* 67: register bank number, the user visible pseudo register.  */
 195     "bank",
 196     /* double precision (pseudo) 68 - 75 */
 197     "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
 198   };
 199   if (reg_nr < 0)
 200     return NULL;
 201   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
 202     return NULL;
 203   return register_names[reg_nr];
 204 }
 205
 206 static const char *
 207 sh_sh2a_nofpu_register_name (int reg_nr)
 208 {
 209   static char *register_names[] = {
 210     /* general registers 0-15 */
 211     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 212     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 213     /* 16 - 22 */
 214     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
 215     /* 23, 24 */
 216     "", "",
 217     /* floating point registers 25 - 40 */
 218     "", "", "", "", "", "", "", "",
 219     "", "", "", "", "", "", "", "",
 220     /* 41, 42 */
 221     "", "",
 222     /* 43 - 62.  Banked registers.  The bank number used is determined by
 223        the bank register (63). */
 224     "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
 225     "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
 226     "machb", "ivnb", "prb", "gbrb", "maclb",
 227     /* 63: register bank number, not a real register but used to
 228        communicate the register bank currently get/set.  This register
 229        is hidden to the user, who manipulates it using the pseudo
 230        register called "bank" (67).  See below.  */
 231     "",
 232     /* 64 - 66 */
 233     "ibcr", "ibnr", "tbr",
 234     /* 67: register bank number, the user visible pseudo register.  */
 235     "bank",
 236     /* double precision (pseudo) 68 - 75 */
 237     "", "", "", "", "", "", "", "",
 238   };
 239   if (reg_nr < 0)
 240     return NULL;
 241   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
 242     return NULL;
 243   return register_names[reg_nr];
 244 }
 245
 246 static const char *
 247 sh_sh_dsp_register_name (int reg_nr)
 248 {
 249   static char *register_names[] = {
 250     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 251     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 252     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
 253     "", "dsr",
 254     "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
 255     "y0", "y1", "", "", "", "", "", "mod",
 256     "", "",
 257     "rs", "re", "", "", "", "", "", "",
 258     "", "", "", "", "", "", "", "",
 259     "", "", "", "", "", "", "", "",
 260   };
 261   if (reg_nr < 0)
 262     return NULL;
 263   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
 264     return NULL;
 265   return register_names[reg_nr];
 266 }
 267
 268 static const char *
 269 sh_sh3_dsp_register_name (int reg_nr)
 270 {
 271   static char *register_names[] = {
 272     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 273     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 274     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
 275     "", "dsr",
 276     "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
 277     "y0", "y1", "", "", "", "", "", "mod",
 278     "ssr", "spc",
 279     "rs", "re", "", "", "", "", "", "",
 280     "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
 281     "", "", "", "", "", "", "", "",
 282     "", "", "", "", "", "", "", "",
 283   };
 284   if (reg_nr < 0)
 285     return NULL;
 286   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
 287     return NULL;
 288   return register_names[reg_nr];
 289 }
 290
 291 static const char *
 292 sh_sh4_register_name (int reg_nr)
 293 {
 294   static char *register_names[] = {
 295     /* general registers 0-15 */
 296     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 297     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 298     /* 16 - 22 */
 299     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
 300     /* 23, 24 */
 301     "fpul", "fpscr",
 302     /* floating point registers 25 - 40 */
 303     "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
 304     "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
 305     /* 41, 42 */
 306     "ssr", "spc",
 307     /* bank 0 43 - 50 */
 308     "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
 309     /* bank 1 51 - 58 */
 310     "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
 311     "", "", "", "", "", "", "", "",
 312     /* pseudo bank register. */
 313     "",
 314     /* double precision (pseudo) 59 - 66 */
 315     "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
 316     /* vectors (pseudo) 67 - 70 */
 317     "fv0", "fv4", "fv8", "fv12",
 318     /* FIXME: missing XF 71 - 86 */
 319     /* FIXME: missing XD 87 - 94 */
 320   };
 321   if (reg_nr < 0)
 322     return NULL;
 323   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
 324     return NULL;
 325   return register_names[reg_nr];
 326 }
 327
 328 static const char *
 329 sh_sh4_nofpu_register_name (int reg_nr)
 330 {
 331   static char *register_names[] = {
 332     /* general registers 0-15 */
 333     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 334     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 335     /* 16 - 22 */
 336     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
 337     /* 23, 24 */
 338     "", "",
 339     /* floating point registers 25 - 40 -- not for nofpu target */
 340     "", "", "", "", "", "", "", "",
 341     "", "", "", "", "", "", "", "",
 342     /* 41, 42 */
 343     "ssr", "spc",
 344     /* bank 0 43 - 50 */
 345     "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
 346     /* bank 1 51 - 58 */
 347     "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
 348     "", "", "", "", "", "", "", "",
 349     /* pseudo bank register. */
 350     "",
 351     /* double precision (pseudo) 59 - 66 -- not for nofpu target */
 352     "", "", "", "", "", "", "", "",
 353     /* vectors (pseudo) 67 - 70 -- not for nofpu target */
 354     "", "", "", "",
 355   };
 356   if (reg_nr < 0)
 357     return NULL;
 358   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
 359     return NULL;
 360   return register_names[reg_nr];
 361 }
 362
 363 static const char *
 364 sh_sh4al_dsp_register_name (int reg_nr)
 365 {
 366   static char *register_names[] = {
 367     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 368     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 369     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
 370     "", "dsr",
 371     "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
 372     "y0", "y1", "", "", "", "", "", "mod",
 373     "ssr", "spc",
 374     "rs", "re", "", "", "", "", "", "",
 375     "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
 376     "", "", "", "", "", "", "", "",
 377     "", "", "", "", "", "", "", "",
 378   };
 379   if (reg_nr < 0)
 380     return NULL;
 381   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
 382     return NULL;
 383   return register_names[reg_nr];
 384 }
 385
 386 static const unsigned char *
 387 sh_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
 388 {
 389   /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
 390   static unsigned char breakpoint[] = { 0xc3, 0xc3 };
 391
 392   /* For remote stub targets, trapa #20 is used.  */
 393   if (strcmp (target_shortname, "remote") == 0)
 394     {
 395       static unsigned char big_remote_breakpoint[] = { 0xc3, 0x20 };
 396       static unsigned char little_remote_breakpoint[] = { 0x20, 0xc3 };
 397
 398       if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
 399         {
 400           *lenptr = sizeof (big_remote_breakpoint);
 401           return big_remote_breakpoint;
 402         }
 403       else
 404         {
 405           *lenptr = sizeof (little_remote_breakpoint);
 406           return little_remote_breakpoint;
 407         }
 408     }
 409
 410   *lenptr = sizeof (breakpoint);
 411   return breakpoint;
 412 }
 413
 414 /* Prologue looks like
 415    mov.l        r14,@-r15
 416    sts.l        pr,@-r15
 417    mov.l        <regs>,@-r15
 418    sub          <room_for_loca_vars>,r15
 419    mov          r15,r14
 420
 421    Actually it can be more complicated than this but that's it, basically.
 422  */
 423
 424 #define GET_SOURCE_REG(x)       (((x) >> 4) & 0xf)
 425 #define GET_TARGET_REG(x)       (((x) >> 8) & 0xf)
 426
 427 /* JSR @Rm         0100mmmm00001011 */
 428 #define IS_JSR(x)               (((x) & 0xf0ff) == 0x400b)
 429
 430 /* STS.L PR,@-r15  0100111100100010
 431    r15-4-->r15, PR-->(r15) */
 432 #define IS_STS(x)               ((x) == 0x4f22)
 433
 434 /* STS.L MACL,@-r15  0100111100010010
 435    r15-4-->r15, MACL-->(r15) */
 436 #define IS_MACL_STS(x)          ((x) == 0x4f12)
 437
 438 /* MOV.L Rm,@-r15  00101111mmmm0110
 439    r15-4-->r15, Rm-->(R15) */
 440 #define IS_PUSH(x)              (((x) & 0xff0f) == 0x2f06)
 441
 442 /* MOV r15,r14     0110111011110011
 443    r15-->r14  */
 444 #define IS_MOV_SP_FP(x)         ((x) == 0x6ef3)
 445
 446 /* ADD #imm,r15    01111111iiiiiiii
 447    r15+imm-->r15 */
 448 #define IS_ADD_IMM_SP(x)        (((x) & 0xff00) == 0x7f00)
 449
 450 #define IS_MOV_R3(x)            (((x) & 0xff00) == 0x1a00)
 451 #define IS_SHLL_R3(x)           ((x) == 0x4300)
 452
 453 /* ADD r3,r15      0011111100111100
 454    r15+r3-->r15 */
 455 #define IS_ADD_R3SP(x)          ((x) == 0x3f3c)
 456
 457 /* FMOV.S FRm,@-Rn  Rn-4-->Rn, FRm-->(Rn)     1111nnnnmmmm1011
 458    FMOV DRm,@-Rn    Rn-8-->Rn, DRm-->(Rn)     1111nnnnmmm01011
 459    FMOV XDm,@-Rn    Rn-8-->Rn, XDm-->(Rn)     1111nnnnmmm11011 */
 460 /* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to
 461                    make this entirely clear. */
 462 /* #define IS_FMOV(x)           (((x) & 0xf00f) == 0xf00b) */
 463 #define IS_FPUSH(x)             (((x) & 0xff0f) == 0xff0b)
 464
 465 /* MOV Rm,Rn          Rm-->Rn        0110nnnnmmmm0011  4 <= m <= 7 */
 466 #define IS_MOV_ARG_TO_REG(x) \
 467         (((x) & 0xf00f) == 0x6003 && \
 468          ((x) & 0x00f0) >= 0x0040 && \
 469          ((x) & 0x00f0) <= 0x0070)
 470 /* MOV.L Rm,@Rn               0010nnnnmmmm0010  n = 14, 4 <= m <= 7 */
 471 #define IS_MOV_ARG_TO_IND_R14(x) \
 472         (((x) & 0xff0f) == 0x2e02 && \
 473          ((x) & 0x00f0) >= 0x0040 && \
 474          ((x) & 0x00f0) <= 0x0070)
 475 /* MOV.L Rm,@(disp*4,Rn)      00011110mmmmdddd  n = 14, 4 <= m <= 7 */
 476 #define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \
 477         (((x) & 0xff00) == 0x1e00 && \
 478          ((x) & 0x00f0) >= 0x0040 && \
 479          ((x) & 0x00f0) <= 0x0070)
 480
 481 /* MOV.W @(disp*2,PC),Rn      1001nnnndddddddd */
 482 #define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000)
 483 /* MOV.L @(disp*4,PC),Rn      1101nnnndddddddd */
 484 #define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000)
 485 /* MOVI20 #imm20,Rn           0000nnnniiii0000 */
 486 #define IS_MOVI20(x)            (((x) & 0xf00f) == 0x0000)
 487 /* SUB Rn,R15                 00111111nnnn1000 */
 488 #define IS_SUB_REG_FROM_SP(x)   (((x) & 0xff0f) == 0x3f08)
 489
 490 #define FPSCR_SZ                (1 << 20)
 491
 492 /* The following instructions are used for epilogue testing. */
 493 #define IS_RESTORE_FP(x)        ((x) == 0x6ef6)
 494 #define IS_RTS(x)               ((x) == 0x000b)
 495 #define IS_LDS(x)               ((x) == 0x4f26)
 496 #define IS_MACL_LDS(x)          ((x) == 0x4f16)
 497 #define IS_MOV_FP_SP(x)         ((x) == 0x6fe3)
 498 #define IS_ADD_REG_TO_FP(x)     (((x) & 0xff0f) == 0x3e0c)
 499 #define IS_ADD_IMM_FP(x)        (((x) & 0xff00) == 0x7e00)
 500
 501 /* Disassemble an instruction.  */
 502 static int
 503 gdb_print_insn_sh (bfd_vma memaddr, disassemble_info * info)
 504 {
 505   info->endian = gdbarch_byte_order (current_gdbarch);
 506   return print_insn_sh (memaddr, info);
 507 }
 508
 509 static CORE_ADDR
 510 sh_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc,
 511                      struct sh_frame_cache *cache, ULONGEST fpscr)
 512 {
 513   ULONGEST inst;
 514   CORE_ADDR opc;
 515   int offset;
 516   int sav_offset = 0;
 517   int r3_val = 0;
 518   int reg, sav_reg = -1;
 519
 520   if (pc >= current_pc)
 521     return current_pc;
 522
 523   cache->uses_fp = 0;
 524   for (opc = pc + (2 * 28); pc < opc; pc += 2)
 525     {
 526       inst = read_memory_unsigned_integer (pc, 2);
 527       /* See where the registers will be saved to */
 528       if (IS_PUSH (inst))
 529         {
 530           cache->saved_regs[GET_SOURCE_REG (inst)] = cache->sp_offset;
 531           cache->sp_offset += 4;
 532         }
 533       else if (IS_STS (inst))
 534         {
 535           cache->saved_regs[PR_REGNUM] = cache->sp_offset;
 536           cache->sp_offset += 4;
 537         }
 538       else if (IS_MACL_STS (inst))
 539         {
 540           cache->saved_regs[MACL_REGNUM] = cache->sp_offset;
 541           cache->sp_offset += 4;
 542         }
 543       else if (IS_MOV_R3 (inst))
 544         {
 545           r3_val = ((inst & 0xff) ^ 0x80) - 0x80;
 546         }
 547       else if (IS_SHLL_R3 (inst))
 548         {
 549           r3_val <<= 1;
 550         }
 551       else if (IS_ADD_R3SP (inst))
 552         {
 553           cache->sp_offset += -r3_val;
 554         }
 555       else if (IS_ADD_IMM_SP (inst))
 556         {
 557           offset = ((inst & 0xff) ^ 0x80) - 0x80;
 558           cache->sp_offset -= offset;
 559         }
 560       else if (IS_MOVW_PCREL_TO_REG (inst))
 561         {
 562           if (sav_reg < 0)
 563             {
 564               reg = GET_TARGET_REG (inst);
 565               if (reg < 14)
 566                 {
 567                   sav_reg = reg;
 568                   offset = (inst & 0xff) << 1;
 569                   sav_offset =
 570                     read_memory_integer ((pc + 4) + offset, 2);
 571                 }
 572             }
 573         }
 574       else if (IS_MOVL_PCREL_TO_REG (inst))
 575         {
 576           if (sav_reg < 0)
 577             {
 578               reg = GET_TARGET_REG (inst);
 579               if (reg < 14)
 580                 {
 581                   sav_reg = reg;
 582                   offset = (inst & 0xff) << 2;
 583                   sav_offset =
 584                     read_memory_integer (((pc & 0xfffffffc) + 4) + offset, 4);
 585                 }
 586             }
 587         }
 588       else if (IS_MOVI20 (inst))
 589         {
 590           if (sav_reg < 0)
 591             {
 592               reg = GET_TARGET_REG (inst);
 593               if (reg < 14)
 594                 {
 595                   sav_reg = reg;
 596                   sav_offset = GET_SOURCE_REG (inst) << 16;
 597                   /* MOVI20 is a 32 bit instruction! */
 598                   pc += 2;
 599                   sav_offset |= read_memory_unsigned_integer (pc, 2);
 600                   /* Now sav_offset contains an unsigned 20 bit value.
 601                      It must still get sign extended.  */
 602                   if (sav_offset & 0x00080000)
 603                     sav_offset |= 0xfff00000;
 604                 }
 605             }
 606         }
 607       else if (IS_SUB_REG_FROM_SP (inst))
 608         {
 609           reg = GET_SOURCE_REG (inst);
 610           if (sav_reg > 0 && reg == sav_reg)
 611             {
 612               sav_reg = -1;
 613             }
 614           cache->sp_offset += sav_offset;
 615         }
 616       else if (IS_FPUSH (inst))
 617         {
 618           if (fpscr & FPSCR_SZ)
 619             {
 620               cache->sp_offset += 8;
 621             }
 622           else
 623             {
 624               cache->sp_offset += 4;
 625             }
 626         }
 627       else if (IS_MOV_SP_FP (inst))
 628         {
 629           cache->uses_fp = 1;
 630           /* At this point, only allow argument register moves to other
 631              registers or argument register moves to @(X,fp) which are
 632              moving the register arguments onto the stack area allocated
 633              by a former add somenumber to SP call.  Don't allow moving
 634              to an fp indirect address above fp + cache->sp_offset. */
 635           pc += 2;
 636           for (opc = pc + 12; pc < opc; pc += 2)
 637             {
 638               inst = read_memory_integer (pc, 2);
 639               if (IS_MOV_ARG_TO_IND_R14 (inst))
 640                 {
 641                   reg = GET_SOURCE_REG (inst);
 642                   if (cache->sp_offset > 0)
 643                     cache->saved_regs[reg] = cache->sp_offset;
 644                 }
 645               else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst))
 646                 {
 647                   reg = GET_SOURCE_REG (inst);
 648                   offset = (inst & 0xf) * 4;
 649                   if (cache->sp_offset > offset)
 650                     cache->saved_regs[reg] = cache->sp_offset - offset;
 651                 }
 652               else if (IS_MOV_ARG_TO_REG (inst))
 653                 continue;
 654               else
 655                 break;
 656             }
 657           break;
 658         }
 659       else if (IS_JSR (inst))
 660         {
 661           /* We have found a jsr that has been scheduled into the prologue.
 662              If we continue the scan and return a pc someplace after this,
 663              then setting a breakpoint on this function will cause it to
 664              appear to be called after the function it is calling via the
 665              jsr, which will be very confusing.  Most likely the next
 666              instruction is going to be IS_MOV_SP_FP in the delay slot.  If
 667              so, note that before returning the current pc. */
 668           inst = read_memory_integer (pc + 2, 2);
 669           if (IS_MOV_SP_FP (inst))
 670             cache->uses_fp = 1;
 671           break;
 672         }
 673 #if 0                           /* This used to just stop when it found an instruction that
 674                                    was not considered part of the prologue.  Now, we just
 675                                    keep going looking for likely instructions. */
 676       else
 677         break;
 678 #endif
 679     }
 680
 681   return pc;
 682 }
 683
 684 /* Skip any prologue before the guts of a function */
 685
 686 /* Skip the prologue using the debug information. If this fails we'll
 687    fall back on the 'guess' method below. */
 688 static CORE_ADDR
 689 after_prologue (CORE_ADDR pc)
 690 {
 691   struct symtab_and_line sal;
 692   CORE_ADDR func_addr, func_end;
 693
 694   /* If we can not find the symbol in the partial symbol table, then
 695      there is no hope we can determine the function's start address
 696      with this code.  */
 697   if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
 698     return 0;
 699
 700   /* Get the line associated with FUNC_ADDR.  */
 701   sal = find_pc_line (func_addr, 0);
 702
 703   /* There are only two cases to consider.  First, the end of the source line
 704      is within the function bounds.  In that case we return the end of the
 705      source line.  Second is the end of the source line extends beyond the
 706      bounds of the current function.  We need to use the slow code to
 707      examine instructions in that case.  */
 708   if (sal.end < func_end)
 709     return sal.end;
 710   else
 711     return 0;
 712 }
 713
 714 static CORE_ADDR
 715 sh_skip_prologue (CORE_ADDR start_pc)
 716 {
 717   CORE_ADDR pc;
 718   struct sh_frame_cache cache;
 719
 720   /* See if we can determine the end of the prologue via the symbol table.
 721      If so, then return either PC, or the PC after the prologue, whichever
 722      is greater.  */
 723   pc = after_prologue (start_pc);
 724
 725   /* If after_prologue returned a useful address, then use it.  Else
 726      fall back on the instruction skipping code. */
 727   if (pc)
 728     return max (pc, start_pc);
 729
 730   cache.sp_offset = -4;
 731   pc = sh_analyze_prologue (start_pc, (CORE_ADDR) -1, &cache, 0);
 732   if (!cache.uses_fp)
 733     return start_pc;
 734
 735   return pc;
 736 }
 737
 738 /* The ABI says:
 739
 740    Aggregate types not bigger than 8 bytes that have the same size and
 741    alignment as one of the integer scalar types are returned in the
 742    same registers as the integer type they match.
 743
 744    For example, a 2-byte aligned structure with size 2 bytes has the
 745    same size and alignment as a short int, and will be returned in R0.
 746    A 4-byte aligned structure with size 8 bytes has the same size and
 747    alignment as a long long int, and will be returned in R0 and R1.
 748
 749    When an aggregate type is returned in R0 and R1, R0 contains the
 750    first four bytes of the aggregate, and R1 contains the
 751    remainder. If the size of the aggregate type is not a multiple of 4
 752    bytes, the aggregate is tail-padded up to a multiple of 4
 753    bytes. The value of the padding is undefined. For little-endian
 754    targets the padding will appear at the most significant end of the
 755    last element, for big-endian targets the padding appears at the
 756    least significant end of the last element.
 757
 758    All other aggregate types are returned by address. The caller
 759    function passes the address of an area large enough to hold the
 760    aggregate value in R2. The called function stores the result in
 761    this location.
 762
 763    To reiterate, structs smaller than 8 bytes could also be returned
 764    in memory, if they don't pass the "same size and alignment as an
 765    integer type" rule.
 766
 767    For example, in
 768
 769    struct s { char c[3]; } wibble;
 770    struct s foo(void) {  return wibble; }
 771
 772    the return value from foo() will be in memory, not
 773    in R0, because there is no 3-byte integer type.
 774
 775    Similarly, in
 776
 777    struct s { char c[2]; } wibble;
 778    struct s foo(void) {  return wibble; }
 779
 780    because a struct containing two chars has alignment 1, that matches
 781    type char, but size 2, that matches type short.  There's no integer
 782    type that has alignment 1 and size 2, so the struct is returned in
 783    memory.
 784
 785 */
 786
 787 static int
 788 sh_use_struct_convention (int gcc_p, struct type *type)
 789 {
 790   int len = TYPE_LENGTH (type);
 791   int nelem = TYPE_NFIELDS (type);
 792
 793   /* Non-power of 2 length types and types bigger than 8 bytes (which don't
 794      fit in two registers anyway) use struct convention.  */
 795   if (len != 1 && len != 2 && len != 4 && len != 8)
 796     return 1;
 797
 798   /* Scalar types and aggregate types with exactly one field are aligned
 799      by definition.  They are returned in registers.  */
 800   if (nelem <= 1)
 801     return 0;
 802
 803   /* If the first field in the aggregate has the same length as the entire
 804      aggregate type, the type is returned in registers.  */
 805   if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == len)
 806     return 0;
 807
 808   /* If the size of the aggregate is 8 bytes and the first field is
 809      of size 4 bytes its alignment is equal to long long's alignment,
 810      so it's returned in registers.  */
 811   if (len == 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == 4)
 812     return 0;
 813
 814   /* Otherwise use struct convention.  */
 815   return 1;
 816 }
 817
 818 static CORE_ADDR
 819 sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
 820 {
 821   return sp & ~3;
 822 }
 823
 824 /* Function: push_dummy_call (formerly push_arguments)
 825    Setup the function arguments for calling a function in the inferior.
 826
 827    On the Renesas SH architecture, there are four registers (R4 to R7)
 828    which are dedicated for passing function arguments.  Up to the first
 829    four arguments (depending on size) may go into these registers.
 830    The rest go on the stack.
 831
 832    MVS: Except on SH variants that have floating point registers.
 833    In that case, float and double arguments are passed in the same
 834    manner, but using FP registers instead of GP registers.
 835
 836    Arguments that are smaller than 4 bytes will still take up a whole
 837    register or a whole 32-bit word on the stack, and will be
 838    right-justified in the register or the stack word.  This includes
 839    chars, shorts, and small aggregate types.
 840
 841    Arguments that are larger than 4 bytes may be split between two or
 842    more registers.  If there are not enough registers free, an argument
 843    may be passed partly in a register (or registers), and partly on the
 844    stack.  This includes doubles, long longs, and larger aggregates.
 845    As far as I know, there is no upper limit to the size of aggregates
 846    that will be passed in this way; in other words, the convention of
 847    passing a pointer to a large aggregate instead of a copy is not used.
 848
 849    MVS: The above appears to be true for the SH variants that do not
 850    have an FPU, however those that have an FPU appear to copy the
 851    aggregate argument onto the stack (and not place it in registers)
 852    if it is larger than 16 bytes (four GP registers).
 853
 854    An exceptional case exists for struct arguments (and possibly other
 855    aggregates such as arrays) if the size is larger than 4 bytes but
 856    not a multiple of 4 bytes.  In this case the argument is never split
 857    between the registers and the stack, but instead is copied in its
 858    entirety onto the stack, AND also copied into as many registers as
 859    there is room for.  In other words, space in registers permitting,
 860    two copies of the same argument are passed in.  As far as I can tell,
 861    only the one on the stack is used, although that may be a function
 862    of the level of compiler optimization.  I suspect this is a compiler
 863    bug.  Arguments of these odd sizes are left-justified within the
 864    word (as opposed to arguments smaller than 4 bytes, which are
 865    right-justified).
 866
 867    If the function is to return an aggregate type such as a struct, it
 868    is either returned in the normal return value register R0 (if its
 869    size is no greater than one byte), or else the caller must allocate
 870    space into which the callee will copy the return value (if the size
 871    is greater than one byte).  In this case, a pointer to the return
 872    value location is passed into the callee in register R2, which does
 873    not displace any of the other arguments passed in via registers R4
 874    to R7.   */
 875
 876 /* Helper function to justify value in register according to endianess. */
 877 static char *
 878 sh_justify_value_in_reg (struct value *val, int len)
 879 {
 880   static char valbuf[4];
 881
 882   memset (valbuf, 0, sizeof (valbuf));
 883   if (len < 4)
 884     {
 885       /* value gets right-justified in the register or stack word */
 886       if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
 887         memcpy (valbuf + (4 - len), (char *) value_contents (val), len);
 888       else
 889         memcpy (valbuf, (char *) value_contents (val), len);
 890       return valbuf;
 891     }
 892   return (char *) value_contents (val);
 893 }
 894
 895 /* Helper function to eval number of bytes to allocate on stack. */
 896 static CORE_ADDR
 897 sh_stack_allocsize (int nargs, struct value **args)
 898 {
 899   int stack_alloc = 0;
 900   while (nargs-- > 0)
 901     stack_alloc += ((TYPE_LENGTH (value_type (args[nargs])) + 3) & ~3);
 902   return stack_alloc;
 903 }
 904
 905 /* Helper functions for getting the float arguments right.  Registers usage
 906    depends on the ABI and the endianess.  The comments should enlighten how
 907    it's intended to work. */
 908
 909 /* This array stores which of the float arg registers are already in use. */
 910 static int flt_argreg_array[FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM + 1];
 911
 912 /* This function just resets the above array to "no reg used so far". */
 913 static void
 914 sh_init_flt_argreg (void)
 915 {
 916   memset (flt_argreg_array, 0, sizeof flt_argreg_array);
 917 }
 918
 919 /* This function returns the next register to use for float arg passing.
 920    It returns either a valid value between FLOAT_ARG0_REGNUM and
 921    FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns
 922    FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available.
 923
 924    Note that register number 0 in flt_argreg_array corresponds with the
 925    real float register fr4.  In contrast to FLOAT_ARG0_REGNUM (value is
 926    29) the parity of the register number is preserved, which is important
 927    for the double register passing test (see the "argreg & 1" test below). */
 928 static int
 929 sh_next_flt_argreg (int len)
 930 {
 931   int argreg;
 932
 933   /* First search for the next free register. */
 934   for (argreg = 0; argreg <= FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM;
 935        ++argreg)
 936     if (!flt_argreg_array[argreg])
 937       break;
 938
 939   /* No register left? */
 940   if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
 941     return FLOAT_ARGLAST_REGNUM + 1;
 942
 943   if (len == 8)
 944     {
 945       /* Doubles are always starting in a even register number. */
 946       if (argreg & 1)
 947         {
 948           flt_argreg_array[argreg] = 1;
 949
 950           ++argreg;
 951
 952           /* No register left? */
 953           if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
 954             return FLOAT_ARGLAST_REGNUM + 1;
 955         }
 956       /* Also mark the next register as used. */
 957       flt_argreg_array[argreg + 1] = 1;
 958     }
 959   else if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE)
 960     {
 961       /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */
 962       if (!flt_argreg_array[argreg + 1])
 963         ++argreg;
 964     }
 965   flt_argreg_array[argreg] = 1;
 966   return FLOAT_ARG0_REGNUM + argreg;
 967 }
 968
 969 /* Helper function which figures out, if a type is treated like a float type.
 970
 971    The FPU ABIs have a special way how to treat types as float types.
 972    Structures with exactly one member, which is of type float or double, are
 973    treated exactly as the base types float or double:
 974
 975      struct sf {
 976        float f;
 977      };
 978
 979      struct sd {
 980        double d;
 981      };
 982
 983    are handled the same way as just
 984
 985      float f;
 986
 987      double d;
 988
 989    As a result, arguments of these struct types are pushed into floating point
 990    registers exactly as floats or doubles, using the same decision algorithm.
 991
 992    The same is valid if these types are used as function return types.  The
 993    above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1
 994    or even using struct convention as it is for other structs.  */
 995
 996 static int
 997 sh_treat_as_flt_p (struct type *type)
 998 {
 999   int len = TYPE_LENGTH (type);
1000
1001   /* Ordinary float types are obviously treated as float.  */
1002   if (TYPE_CODE (type) == TYPE_CODE_FLT)
1003     return 1;
1004   /* Otherwise non-struct types are not treated as float.  */
1005   if (TYPE_CODE (type) != TYPE_CODE_STRUCT)
1006     return 0;
1007   /* Otherwise structs with more than one memeber are not treated as float.  */
1008   if (TYPE_NFIELDS (type) != 1)
1009     return 0;
1010   /* Otherwise if the type of that member is float, the whole type is
1011      treated as float.  */
1012   if (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) == TYPE_CODE_FLT)
1013     return 1;
1014   /* Otherwise it's not treated as float.  */
1015   return 0;
1016 }
1017
1018 static CORE_ADDR
1019 sh_push_dummy_call_fpu (struct gdbarch *gdbarch,
1020                         struct value *function,
1021                         struct regcache *regcache,
1022                         CORE_ADDR bp_addr, int nargs,
1023                         struct value **args,
1024                         CORE_ADDR sp, int struct_return,
1025                         CORE_ADDR struct_addr)
1026 {
1027   int stack_offset = 0;
1028   int argreg = ARG0_REGNUM;
1029   int flt_argreg = 0;
1030   int argnum;
1031   struct type *type;
1032   CORE_ADDR regval;
1033   char *val;
1034   int len, reg_size = 0;
1035   int pass_on_stack = 0;
1036   int treat_as_flt;
1037
1038   /* first force sp to a 4-byte alignment */
1039   sp = sh_frame_align (gdbarch, sp);
1040
1041   if (struct_return)
1042     regcache_cooked_write_unsigned (regcache,
1043                                     STRUCT_RETURN_REGNUM, struct_addr);
1044
1045   /* make room on stack for args */
1046   sp -= sh_stack_allocsize (nargs, args);
1047
1048   /* Initialize float argument mechanism. */
1049   sh_init_flt_argreg ();
1050
1051   /* Now load as many as possible of the first arguments into
1052      registers, and push the rest onto the stack.  There are 16 bytes
1053      in four registers available.  Loop thru args from first to last.  */
1054   for (argnum = 0; argnum < nargs; argnum++)
1055     {
1056       type = value_type (args[argnum]);
1057       len = TYPE_LENGTH (type);
1058       val = sh_justify_value_in_reg (args[argnum], len);
1059
1060       /* Some decisions have to be made how various types are handled.
1061          This also differs in different ABIs. */
1062       pass_on_stack = 0;
1063
1064       /* Find out the next register to use for a floating point value. */
1065       treat_as_flt = sh_treat_as_flt_p (type);
1066       if (treat_as_flt)
1067         flt_argreg = sh_next_flt_argreg (len);
1068       /* In contrast to non-FPU CPUs, arguments are never split between
1069          registers and stack.  If an argument doesn't fit in the remaining
1070          registers it's always pushed entirely on the stack.  */
1071       else if (len > ((ARGLAST_REGNUM - argreg + 1) * 4))
1072         pass_on_stack = 1;
1073
1074       while (len > 0)
1075         {
1076           if ((treat_as_flt && flt_argreg > FLOAT_ARGLAST_REGNUM)
1077               || (!treat_as_flt && (argreg > ARGLAST_REGNUM
1078                                     || pass_on_stack)))
1079             {
1080               /* The data goes entirely on the stack, 4-byte aligned. */
1081               reg_size = (len + 3) & ~3;
1082               write_memory (sp + stack_offset, val, reg_size);
1083               stack_offset += reg_size;
1084             }
1085           else if (treat_as_flt && flt_argreg <= FLOAT_ARGLAST_REGNUM)
1086             {
1087               /* Argument goes in a float argument register.  */
1088               reg_size = register_size (gdbarch, flt_argreg);
1089               regval = extract_unsigned_integer (val, reg_size);
1090               /* In little endian mode, float types taking two registers
1091                  (doubles on sh4, long doubles on sh2e, sh3e and sh4) must
1092                  be stored swapped in the argument registers.  The below
1093                  code first writes the first 32 bits in the next but one
1094                  register, increments the val and len values accordingly
1095                  and then proceeds as normal by writing the second 32 bits
1096                  into the next register. */
1097               if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE
1098                   && TYPE_LENGTH (type) == 2 * reg_size)
1099                 {
1100                   regcache_cooked_write_unsigned (regcache, flt_argreg + 1,
1101                                                   regval);
1102                   val += reg_size;
1103                   len -= reg_size;
1104                   regval = extract_unsigned_integer (val, reg_size);
1105                 }
1106               regcache_cooked_write_unsigned (regcache, flt_argreg++, regval);
1107             }
1108           else if (!treat_as_flt && argreg <= ARGLAST_REGNUM)
1109             {
1110               /* there's room in a register */
1111               reg_size = register_size (gdbarch, argreg);
1112               regval = extract_unsigned_integer (val, reg_size);
1113               regcache_cooked_write_unsigned (regcache, argreg++, regval);
1114             }
1115           /* Store the value one register at a time or in one step on stack.  */
1116           len -= reg_size;
1117           val += reg_size;
1118         }
1119     }
1120
1121   /* Store return address. */
1122   regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
1123
1124   /* Update stack pointer.  */
1125   regcache_cooked_write_unsigned (regcache,
1126                                   gdbarch_sp_regnum (current_gdbarch), sp);
1127
1128   return sp;
1129 }
1130
1131 static CORE_ADDR
1132 sh_push_dummy_call_nofpu (struct gdbarch *gdbarch,
1133                           struct value *function,
1134                           struct regcache *regcache,
1135                           CORE_ADDR bp_addr,
1136                           int nargs, struct value **args,
1137                           CORE_ADDR sp, int struct_return,
1138                           CORE_ADDR struct_addr)
1139 {
1140   int stack_offset = 0;
1141   int argreg = ARG0_REGNUM;
1142   int argnum;
1143   struct type *type;
1144   CORE_ADDR regval;
1145   char *val;
1146   int len, reg_size;
1147
1148   /* first force sp to a 4-byte alignment */
1149   sp = sh_frame_align (gdbarch, sp);
1150
1151   if (struct_return)
1152     regcache_cooked_write_unsigned (regcache,
1153                                     STRUCT_RETURN_REGNUM, struct_addr);
1154
1155   /* make room on stack for args */
1156   sp -= sh_stack_allocsize (nargs, args);
1157
1158   /* Now load as many as possible of the first arguments into
1159      registers, and push the rest onto the stack.  There are 16 bytes
1160      in four registers available.  Loop thru args from first to last.  */
1161   for (argnum = 0; argnum < nargs; argnum++)
1162     {
1163       type = value_type (args[argnum]);
1164       len = TYPE_LENGTH (type);
1165       val = sh_justify_value_in_reg (args[argnum], len);
1166
1167       while (len > 0)
1168         {
1169           if (argreg > ARGLAST_REGNUM)
1170             {
1171               /* The remainder of the data goes entirely on the stack,
1172                  4-byte aligned. */
1173               reg_size = (len + 3) & ~3;
1174               write_memory (sp + stack_offset, val, reg_size);
1175               stack_offset += reg_size;
1176             }
1177           else if (argreg <= ARGLAST_REGNUM)
1178             {
1179               /* there's room in a register */
1180               reg_size = register_size (gdbarch, argreg);
1181               regval = extract_unsigned_integer (val, reg_size);
1182               regcache_cooked_write_unsigned (regcache, argreg++, regval);
1183             }
1184           /* Store the value reg_size bytes at a time.  This means that things
1185              larger than reg_size bytes may go partly in registers and partly
1186              on the stack.  */
1187           len -= reg_size;
1188           val += reg_size;
1189         }
1190     }
1191
1192   /* Store return address. */
1193   regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
1194
1195   /* Update stack pointer.  */
1196   regcache_cooked_write_unsigned (regcache,
1197                                   gdbarch_sp_regnum (current_gdbarch), sp);
1198
1199   return sp;
1200 }
1201
1202 /* Find a function's return value in the appropriate registers (in
1203    regbuf), and copy it into valbuf.  Extract from an array REGBUF
1204    containing the (raw) register state a function return value of type
1205    TYPE, and copy that, in virtual format, into VALBUF.  */
1206 static void
1207 sh_extract_return_value_nofpu (struct type *type, struct regcache *regcache,
1208                                void *valbuf)
1209 {
1210   int len = TYPE_LENGTH (type);
1211   int return_register = R0_REGNUM;
1212   int offset;
1213
1214   if (len <= 4)
1215     {
1216       ULONGEST c;
1217
1218       regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c);
1219       store_unsigned_integer (valbuf, len, c);
1220     }
1221   else if (len == 8)
1222     {
1223       int i, regnum = R0_REGNUM;
1224       for (i = 0; i < len; i += 4)
1225         regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
1226     }
1227   else
1228     error (_("bad size for return value"));
1229 }
1230
1231 static void
1232 sh_extract_return_value_fpu (struct type *type, struct regcache *regcache,
1233                              void *valbuf)
1234 {
1235   if (sh_treat_as_flt_p (type))
1236     {
1237       int len = TYPE_LENGTH (type);
1238       int i, regnum = gdbarch_fp0_regnum (current_gdbarch);
1239       for (i = 0; i < len; i += 4)
1240         if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE)
1241           regcache_raw_read (regcache, regnum++, (char *) valbuf + len - 4 - i);
1242         else
1243           regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
1244     }
1245   else
1246     sh_extract_return_value_nofpu (type, regcache, valbuf);
1247 }
1248
1249 /* Write into appropriate registers a function return value
1250    of type TYPE, given in virtual format.
1251    If the architecture is sh4 or sh3e, store a function's return value
1252    in the R0 general register or in the FP0 floating point register,
1253    depending on the type of the return value. In all the other cases
1254    the result is stored in r0, left-justified. */
1255 static void
1256 sh_store_return_value_nofpu (struct type *type, struct regcache *regcache,
1257                              const void *valbuf)
1258 {
1259   ULONGEST val;
1260   int len = TYPE_LENGTH (type);
1261
1262   if (len <= 4)
1263     {
1264       val = extract_unsigned_integer (valbuf, len);
1265       regcache_cooked_write_unsigned (regcache, R0_REGNUM, val);
1266     }
1267   else
1268     {
1269       int i, regnum = R0_REGNUM;
1270       for (i = 0; i < len; i += 4)
1271         regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
1272     }
1273 }
1274
1275 static void
1276 sh_store_return_value_fpu (struct type *type, struct regcache *regcache,
1277                            const void *valbuf)
1278 {
1279   if (sh_treat_as_flt_p (type))
1280     {
1281       int len = TYPE_LENGTH (type);
1282       int i, regnum = gdbarch_fp0_regnum (current_gdbarch);
1283       for (i = 0; i < len; i += 4)
1284         if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE)
1285           regcache_raw_write (regcache, regnum++,
1286                               (char *) valbuf + len - 4 - i);
1287         else
1288           regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
1289     }
1290   else
1291     sh_store_return_value_nofpu (type, regcache, valbuf);
1292 }
1293
1294 static enum return_value_convention
1295 sh_return_value_nofpu (struct gdbarch *gdbarch, struct type *type,
1296                        struct regcache *regcache,
1297                        gdb_byte *readbuf, const gdb_byte *writebuf)
1298 {
1299   if (sh_use_struct_convention (0, type))
1300     return RETURN_VALUE_STRUCT_CONVENTION;
1301   if (writebuf)
1302     sh_store_return_value_nofpu (type, regcache, writebuf);
1303   else if (readbuf)
1304     sh_extract_return_value_nofpu (type, regcache, readbuf);
1305   return RETURN_VALUE_REGISTER_CONVENTION;
1306 }
1307
1308 static enum return_value_convention
1309 sh_return_value_fpu (struct gdbarch *gdbarch, struct type *type,
1310                      struct regcache *regcache,
1311                      gdb_byte *readbuf, const gdb_byte *writebuf)
1312 {
1313   if (sh_use_struct_convention (0, type))
1314     return RETURN_VALUE_STRUCT_CONVENTION;
1315   if (writebuf)
1316     sh_store_return_value_fpu (type, regcache, writebuf);
1317   else if (readbuf)
1318     sh_extract_return_value_fpu (type, regcache, readbuf);
1319   return RETURN_VALUE_REGISTER_CONVENTION;
1320 }
1321
1322 /* Print the registers in a form similar to the E7000 */
1323
1324 static void
1325 sh_generic_show_regs (struct frame_info *frame)
1326 {
1327   printf_filtered
1328     ("      PC %s       SR %08lx       PR %08lx     MACH %08lx\n",
1329      paddr (get_frame_register_unsigned (frame,
1330                                          gdbarch_pc_regnum (current_gdbarch))),
1331      (long) get_frame_register_unsigned (frame, SR_REGNUM),
1332      (long) get_frame_register_unsigned (frame, PR_REGNUM),
1333      (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1334
1335   printf_filtered
1336     ("     GBR %08lx      VBR %08lx                       MACL %08lx\n",
1337      (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1338      (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1339      (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1340
1341   printf_filtered
1342     ("R0-R7    %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1343      (long) get_frame_register_unsigned (frame, 0),
1344      (long) get_frame_register_unsigned (frame, 1),
1345      (long) get_frame_register_unsigned (frame, 2),
1346      (long) get_frame_register_unsigned (frame, 3),
1347      (long) get_frame_register_unsigned (frame, 4),
1348      (long) get_frame_register_unsigned (frame, 5),
1349      (long) get_frame_register_unsigned (frame, 6),
1350      (long) get_frame_register_unsigned (frame, 7));
1351   printf_filtered
1352     ("R8-R15   %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1353      (long) get_frame_register_unsigned (frame, 8),
1354      (long) get_frame_register_unsigned (frame, 9),
1355      (long) get_frame_register_unsigned (frame, 10),
1356      (long) get_frame_register_unsigned (frame, 11),
1357      (long) get_frame_register_unsigned (frame, 12),
1358      (long) get_frame_register_unsigned (frame, 13),
1359      (long) get_frame_register_unsigned (frame, 14),
1360      (long) get_frame_register_unsigned (frame, 15));
1361 }
1362
1363 static void
1364 sh3_show_regs (struct frame_info *frame)
1365 {
1366   printf_filtered
1367     ("      PC %s       SR %08lx       PR %08lx     MACH %08lx\n",
1368      paddr (get_frame_register_unsigned (frame,
1369                                          gdbarch_pc_regnum (current_gdbarch))),
1370      (long) get_frame_register_unsigned (frame, SR_REGNUM),
1371      (long) get_frame_register_unsigned (frame, PR_REGNUM),
1372      (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1373
1374   printf_filtered
1375     ("     GBR %08lx      VBR %08lx                       MACL %08lx\n",
1376      (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1377      (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1378      (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1379   printf_filtered
1380     ("     SSR %08lx      SPC %08lx\n",
1381      (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1382      (long) get_frame_register_unsigned (frame, SPC_REGNUM));
1383
1384   printf_filtered
1385     ("R0-R7    %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1386      (long) get_frame_register_unsigned (frame, 0),
1387      (long) get_frame_register_unsigned (frame, 1),
1388      (long) get_frame_register_unsigned (frame, 2),
1389      (long) get_frame_register_unsigned (frame, 3),
1390      (long) get_frame_register_unsigned (frame, 4),
1391      (long) get_frame_register_unsigned (frame, 5),
1392      (long) get_frame_register_unsigned (frame, 6),
1393      (long) get_frame_register_unsigned (frame, 7));
1394   printf_filtered
1395     ("R8-R15   %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1396      (long) get_frame_register_unsigned (frame, 8),
1397      (long) get_frame_register_unsigned (frame, 9),
1398      (long) get_frame_register_unsigned (frame, 10),
1399      (long) get_frame_register_unsigned (frame, 11),
1400      (long) get_frame_register_unsigned (frame, 12),
1401      (long) get_frame_register_unsigned (frame, 13),
1402      (long) get_frame_register_unsigned (frame, 14),
1403      (long) get_frame_register_unsigned (frame, 15));
1404 }
1405
1406 static void
1407 sh2e_show_regs (struct frame_info *frame)
1408 {
1409   printf_filtered
1410     ("      PC %s       SR %08lx       PR %08lx     MACH %08lx\n",
1411      paddr (get_frame_register_unsigned (frame,
1412                                          gdbarch_pc_regnum (current_gdbarch))),
1413      (long) get_frame_register_unsigned (frame, SR_REGNUM),
1414      (long) get_frame_register_unsigned (frame, PR_REGNUM),
1415      (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1416
1417   printf_filtered
1418     ("     GBR %08lx      VBR %08lx                       MACL %08lx\n",
1419      (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1420      (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1421      (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1422   printf_filtered
1423     ("     SSR %08lx      SPC %08lx     FPUL %08lx    FPSCR %08lx\n",
1424      (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1425      (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1426      (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1427      (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1428
1429   printf_filtered
1430     ("R0-R7    %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1431      (long) get_frame_register_unsigned (frame, 0),
1432      (long) get_frame_register_unsigned (frame, 1),
1433      (long) get_frame_register_unsigned (frame, 2),
1434      (long) get_frame_register_unsigned (frame, 3),
1435      (long) get_frame_register_unsigned (frame, 4),
1436      (long) get_frame_register_unsigned (frame, 5),
1437      (long) get_frame_register_unsigned (frame, 6),
1438      (long) get_frame_register_unsigned (frame, 7));
1439   printf_filtered
1440     ("R8-R15   %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1441      (long) get_frame_register_unsigned (frame, 8),
1442      (long) get_frame_register_unsigned (frame, 9),
1443      (long) get_frame_register_unsigned (frame, 10),
1444      (long) get_frame_register_unsigned (frame, 11),
1445      (long) get_frame_register_unsigned (frame, 12),
1446      (long) get_frame_register_unsigned (frame, 13),
1447      (long) get_frame_register_unsigned (frame, 14),
1448      (long) get_frame_register_unsigned (frame, 15));
1449
1450   printf_filtered
1451     ("FP0-FP7  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1452      (long) get_frame_register_unsigned
1453               (frame, gdbarch_fp0_regnum (current_gdbarch) + 0),
1454      (long) get_frame_register_unsigned
1455               (frame, gdbarch_fp0_regnum (current_gdbarch) + 1),
1456      (long) get_frame_register_unsigned
1457               (frame, gdbarch_fp0_regnum (current_gdbarch) + 2),
1458      (long) get_frame_register_unsigned
1459               (frame, gdbarch_fp0_regnum (current_gdbarch) + 3),
1460      (long) get_frame_register_unsigned
1461               (frame, gdbarch_fp0_regnum (current_gdbarch) + 4),
1462      (long) get_frame_register_unsigned
1463               (frame, gdbarch_fp0_regnum (current_gdbarch) + 5),
1464      (long) get_frame_register_unsigned
1465               (frame, gdbarch_fp0_regnum (current_gdbarch) + 6),
1466      (long) get_frame_register_unsigned
1467               (frame, gdbarch_fp0_regnum (current_gdbarch) + 7));
1468   printf_filtered
1469     ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1470      (long) get_frame_register_unsigned
1471               (frame, gdbarch_fp0_regnum (current_gdbarch) + 8),
1472      (long) get_frame_register_unsigned
1473               (frame, gdbarch_fp0_regnum (current_gdbarch) + 9),
1474      (long) get_frame_register_unsigned
1475               (frame, gdbarch_fp0_regnum (current_gdbarch) + 10),
1476      (long) get_frame_register_unsigned
1477               (frame, gdbarch_fp0_regnum (current_gdbarch) + 11),
1478      (long) get_frame_register_unsigned
1479               (frame, gdbarch_fp0_regnum (current_gdbarch) + 12),
1480      (long) get_frame_register_unsigned
1481               (frame, gdbarch_fp0_regnum (current_gdbarch) + 13),
1482      (long) get_frame_register_unsigned
1483               (frame, gdbarch_fp0_regnum (current_gdbarch) + 14),
1484      (long) get_frame_register_unsigned
1485               (frame, gdbarch_fp0_regnum (current_gdbarch) + 15));
1486 }
1487
1488 static void
1489 sh2a_show_regs (struct frame_info *frame)
1490 {
1491   int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000;
1492
1493   printf_filtered
1494     ("      PC %s       SR %08lx       PR %08lx     MACH %08lx\n",
1495      paddr (get_frame_register_unsigned (frame,
1496                                          gdbarch_pc_regnum (current_gdbarch))),
1497      (long) get_frame_register_unsigned (frame, SR_REGNUM),
1498      (long) get_frame_register_unsigned (frame, PR_REGNUM),
1499      (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1500
1501   printf_filtered
1502     ("     GBR %08lx      VBR %08lx      TBR %08lx     MACL %08lx\n",
1503      (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1504      (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1505      (long) get_frame_register_unsigned (frame, TBR_REGNUM),
1506      (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1507   printf_filtered
1508     ("     SSR %08lx      SPC %08lx     FPUL %08lx    FPSCR %08lx\n",
1509      (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1510      (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1511      (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1512      (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1513
1514   printf_filtered
1515     ("R0-R7    %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1516      (long) get_frame_register_unsigned (frame, 0),
1517      (long) get_frame_register_unsigned (frame, 1),
1518      (long) get_frame_register_unsigned (frame, 2),
1519      (long) get_frame_register_unsigned (frame, 3),
1520      (long) get_frame_register_unsigned (frame, 4),
1521      (long) get_frame_register_unsigned (frame, 5),
1522      (long) get_frame_register_unsigned (frame, 6),
1523      (long) get_frame_register_unsigned (frame, 7));
1524   printf_filtered
1525     ("R8-R15   %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1526      (long) get_frame_register_unsigned (frame, 8),
1527      (long) get_frame_register_unsigned (frame, 9),
1528      (long) get_frame_register_unsigned (frame, 10),
1529      (long) get_frame_register_unsigned (frame, 11),
1530      (long) get_frame_register_unsigned (frame, 12),
1531      (long) get_frame_register_unsigned (frame, 13),
1532      (long) get_frame_register_unsigned (frame, 14),
1533      (long) get_frame_register_unsigned (frame, 15));
1534
1535   printf_filtered
1536     (pr ? "DR0-DR6  %08lx%08lx  %08lx%08lx  %08lx%08lx  %08lx%08lx\n"
1537         : "FP0-FP7  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1538      (long) get_frame_register_unsigned
1539               (frame, gdbarch_fp0_regnum (current_gdbarch) + 0),
1540      (long) get_frame_register_unsigned
1541               (frame, gdbarch_fp0_regnum (current_gdbarch) + 1),
1542      (long) get_frame_register_unsigned
1543               (frame, gdbarch_fp0_regnum (current_gdbarch) + 2),
1544      (long) get_frame_register_unsigned
1545               (frame, gdbarch_fp0_regnum (current_gdbarch) + 3),
1546      (long) get_frame_register_unsigned
1547               (frame, gdbarch_fp0_regnum (current_gdbarch) + 4),
1548      (long) get_frame_register_unsigned
1549               (frame, gdbarch_fp0_regnum (current_gdbarch) + 5),
1550      (long) get_frame_register_unsigned
1551               (frame, gdbarch_fp0_regnum (current_gdbarch) + 6),
1552      (long) get_frame_register_unsigned
1553               (frame, gdbarch_fp0_regnum (current_gdbarch) + 7));
1554   printf_filtered
1555     (pr ? "DR8-DR14 %08lx%08lx  %08lx%08lx  %08lx%08lx  %08lx%08lx\n"
1556         : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1557      (long) get_frame_register_unsigned
1558               (frame, gdbarch_fp0_regnum (current_gdbarch) + 8),
1559      (long) get_frame_register_unsigned
1560               (frame, gdbarch_fp0_regnum (current_gdbarch) + 9),
1561      (long) get_frame_register_unsigned
1562               (frame, gdbarch_fp0_regnum (current_gdbarch) + 10),
1563      (long) get_frame_register_unsigned
1564               (frame, gdbarch_fp0_regnum (current_gdbarch) + 11),
1565      (long) get_frame_register_unsigned
1566               (frame, gdbarch_fp0_regnum (current_gdbarch) + 12),
1567      (long) get_frame_register_unsigned
1568               (frame, gdbarch_fp0_regnum (current_gdbarch) + 13),
1569      (long) get_frame_register_unsigned
1570               (frame, gdbarch_fp0_regnum (current_gdbarch) + 14),
1571      (long) get_frame_register_unsigned
1572               (frame, gdbarch_fp0_regnum (current_gdbarch) + 15));
1573   printf_filtered
1574     ("BANK=%-3d\n", (int) get_frame_register_unsigned (frame, BANK_REGNUM));
1575   printf_filtered
1576     ("R0b-R7b  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1577      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 0),
1578      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 1),
1579      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 2),
1580      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 3),
1581      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 4),
1582      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 5),
1583      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 6),
1584      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 7));
1585   printf_filtered
1586     ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1587      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 8),
1588      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 9),
1589      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 10),
1590      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 11),
1591      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 12),
1592      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 13),
1593      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 14));
1594   printf_filtered
1595     ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n",
1596      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 15),
1597      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 16),
1598      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 17),
1599      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 18),
1600      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 19));
1601 }
1602
1603 static void
1604 sh2a_nofpu_show_regs (struct frame_info *frame)
1605 {
1606   int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000;
1607
1608   printf_filtered
1609     ("      PC %s       SR %08lx       PR %08lx     MACH %08lx\n",
1610      paddr (get_frame_register_unsigned (frame,
1611                                          gdbarch_pc_regnum (current_gdbarch))),
1612      (long) get_frame_register_unsigned (frame, SR_REGNUM),
1613      (long) get_frame_register_unsigned (frame, PR_REGNUM),
1614      (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1615
1616   printf_filtered
1617     ("     GBR %08lx      VBR %08lx      TBR %08lx     MACL %08lx\n",
1618      (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1619      (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1620      (long) get_frame_register_unsigned (frame, TBR_REGNUM),
1621      (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1622   printf_filtered
1623     ("     SSR %08lx      SPC %08lx     FPUL %08lx    FPSCR %08lx\n",
1624      (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1625      (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1626      (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1627      (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1628
1629   printf_filtered
1630     ("R0-R7    %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1631      (long) get_frame_register_unsigned (frame, 0),
1632      (long) get_frame_register_unsigned (frame, 1),
1633      (long) get_frame_register_unsigned (frame, 2),
1634      (long) get_frame_register_unsigned (frame, 3),
1635      (long) get_frame_register_unsigned (frame, 4),
1636      (long) get_frame_register_unsigned (frame, 5),
1637      (long) get_frame_register_unsigned (frame, 6),
1638      (long) get_frame_register_unsigned (frame, 7));
1639   printf_filtered
1640     ("R8-R15   %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1641      (long) get_frame_register_unsigned (frame, 8),
1642      (long) get_frame_register_unsigned (frame, 9),
1643      (long) get_frame_register_unsigned (frame, 10),
1644      (long) get_frame_register_unsigned (frame, 11),
1645      (long) get_frame_register_unsigned (frame, 12),
1646      (long) get_frame_register_unsigned (frame, 13),
1647      (long) get_frame_register_unsigned (frame, 14),
1648      (long) get_frame_register_unsigned (frame, 15));
1649
1650   printf_filtered
1651     ("BANK=%-3d\n", (int) get_frame_register_unsigned (frame, BANK_REGNUM));
1652   printf_filtered
1653     ("R0b-R7b  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1654      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 0),
1655      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 1),
1656      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 2),
1657      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 3),
1658      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 4),
1659      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 5),
1660      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 6),
1661      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 7));
1662   printf_filtered
1663     ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1664      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 8),
1665      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 9),
1666      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 10),
1667      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 11),
1668      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 12),
1669      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 13),
1670      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 14));
1671   printf_filtered
1672     ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n",
1673      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 15),
1674      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 16),
1675      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 17),
1676      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 18),
1677      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 19));
1678 }
1679
1680 static void
1681 sh3e_show_regs (struct frame_info *frame)
1682 {
1683   printf_filtered
1684     ("      PC %s       SR %08lx       PR %08lx     MACH %08lx\n",
1685      paddr (get_frame_register_unsigned (frame,
1686                                          gdbarch_pc_regnum (current_gdbarch))),
1687      (long) get_frame_register_unsigned (frame, SR_REGNUM),
1688      (long) get_frame_register_unsigned (frame, PR_REGNUM),
1689      (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1690
1691   printf_filtered
1692     ("     GBR %08lx      VBR %08lx                       MACL %08lx\n",
1693      (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1694      (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1695      (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1696   printf_filtered
1697     ("     SSR %08lx      SPC %08lx     FPUL %08lx    FPSCR %08lx\n",
1698      (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1699      (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1700      (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1701      (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1702
1703   printf_filtered
1704     ("R0-R7    %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1705      (long) get_frame_register_unsigned (frame, 0),
1706      (long) get_frame_register_unsigned (frame, 1),
1707      (long) get_frame_register_unsigned (frame, 2),
1708      (long) get_frame_register_unsigned (frame, 3),
1709      (long) get_frame_register_unsigned (frame, 4),
1710      (long) get_frame_register_unsigned (frame, 5),
1711      (long) get_frame_register_unsigned (frame, 6),
1712      (long) get_frame_register_unsigned (frame, 7));
1713   printf_filtered
1714     ("R8-R15   %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1715      (long) get_frame_register_unsigned (frame, 8),
1716      (long) get_frame_register_unsigned (frame, 9),
1717      (long) get_frame_register_unsigned (frame, 10),
1718      (long) get_frame_register_unsigned (frame, 11),
1719      (long) get_frame_register_unsigned (frame, 12),
1720      (long) get_frame_register_unsigned (frame, 13),
1721      (long) get_frame_register_unsigned (frame, 14),
1722      (long) get_frame_register_unsigned (frame, 15));
1723
1724   printf_filtered
1725     ("FP0-FP7  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1726      (long) get_frame_register_unsigned
1727               (frame, gdbarch_fp0_regnum (current_gdbarch) + 0),
1728      (long) get_frame_register_unsigned
1729               (frame, gdbarch_fp0_regnum (current_gdbarch) + 1),
1730      (long) get_frame_register_unsigned
1731               (frame, gdbarch_fp0_regnum (current_gdbarch) + 2),
1732      (long) get_frame_register_unsigned
1733               (frame, gdbarch_fp0_regnum (current_gdbarch) + 3),
1734      (long) get_frame_register_unsigned
1735               (frame, gdbarch_fp0_regnum (current_gdbarch) + 4),
1736      (long) get_frame_register_unsigned
1737               (frame, gdbarch_fp0_regnum (current_gdbarch) + 5),
1738      (long) get_frame_register_unsigned
1739               (frame, gdbarch_fp0_regnum (current_gdbarch) + 6),
1740      (long) get_frame_register_unsigned
1741               (frame, gdbarch_fp0_regnum (current_gdbarch) + 7));
1742   printf_filtered
1743     ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1744      (long) get_frame_register_unsigned
1745               (frame, gdbarch_fp0_regnum (current_gdbarch) + 8),
1746      (long) get_frame_register_unsigned
1747               (frame, gdbarch_fp0_regnum (current_gdbarch) + 9),
1748      (long) get_frame_register_unsigned
1749               (frame, gdbarch_fp0_regnum (current_gdbarch) + 10),
1750      (long) get_frame_register_unsigned
1751               (frame, gdbarch_fp0_regnum (current_gdbarch) + 11),
1752      (long) get_frame_register_unsigned
1753               (frame, gdbarch_fp0_regnum (current_gdbarch) + 12),
1754      (long) get_frame_register_unsigned
1755               (frame, gdbarch_fp0_regnum (current_gdbarch) + 13),
1756      (long) get_frame_register_unsigned
1757               (frame, gdbarch_fp0_regnum (current_gdbarch) + 14),
1758      (long) get_frame_register_unsigned
1759               (frame, gdbarch_fp0_regnum (current_gdbarch) + 15));
1760 }
1761
1762 static void
1763 sh3_dsp_show_regs (struct frame_info *frame)
1764 {
1765   printf_filtered
1766     ("      PC %s       SR %08lx       PR %08lx     MACH %08lx\n",
1767      paddr (get_frame_register_unsigned (frame,
1768                                          gdbarch_pc_regnum (current_gdbarch))),
1769      (long) get_frame_register_unsigned (frame, SR_REGNUM),
1770      (long) get_frame_register_unsigned (frame, PR_REGNUM),
1771      (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1772
1773   printf_filtered
1774     ("     GBR %08lx      VBR %08lx                       MACL %08lx\n",
1775      (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1776      (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1777      (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1778
1779   printf_filtered
1780     ("     SSR %08lx      SPC %08lx      DSR %08lx\n",
1781      (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1782      (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1783      (long) get_frame_register_unsigned (frame, DSR_REGNUM));
1784
1785   printf_filtered
1786     ("R0-R7    %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1787      (long) get_frame_register_unsigned (frame, 0),
1788      (long) get_frame_register_unsigned (frame, 1),
1789      (long) get_frame_register_unsigned (frame, 2),
1790      (long) get_frame_register_unsigned (frame, 3),
1791      (long) get_frame_register_unsigned (frame, 4),
1792      (long) get_frame_register_unsigned (frame, 5),
1793      (long) get_frame_register_unsigned (frame, 6),
1794      (long) get_frame_register_unsigned (frame, 7));
1795   printf_filtered
1796     ("R8-R15   %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1797      (long) get_frame_register_unsigned (frame, 8),
1798      (long) get_frame_register_unsigned (frame, 9),
1799      (long) get_frame_register_unsigned (frame, 10),
1800      (long) get_frame_register_unsigned (frame, 11),
1801      (long) get_frame_register_unsigned (frame, 12),
1802      (long) get_frame_register_unsigned (frame, 13),
1803      (long) get_frame_register_unsigned (frame, 14),
1804      (long) get_frame_register_unsigned (frame, 15));
1805
1806   printf_filtered
1807     ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1808      (long) get_frame_register_unsigned (frame, A0G_REGNUM) & 0xff,
1809      (long) get_frame_register_unsigned (frame, A0_REGNUM),
1810      (long) get_frame_register_unsigned (frame, M0_REGNUM),
1811      (long) get_frame_register_unsigned (frame, X0_REGNUM),
1812      (long) get_frame_register_unsigned (frame, Y0_REGNUM),
1813      (long) get_frame_register_unsigned (frame, RS_REGNUM),
1814      (long) get_frame_register_unsigned (frame, MOD_REGNUM));
1815   printf_filtered
1816     ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1817      (long) get_frame_register_unsigned (frame, A1G_REGNUM) & 0xff,
1818      (long) get_frame_register_unsigned (frame, A1_REGNUM),
1819      (long) get_frame_register_unsigned (frame, M1_REGNUM),
1820      (long) get_frame_register_unsigned (frame, X1_REGNUM),
1821      (long) get_frame_register_unsigned (frame, Y1_REGNUM),
1822      (long) get_frame_register_unsigned (frame, RE_REGNUM));
1823 }
1824
1825 static void
1826 sh4_show_regs (struct frame_info *frame)
1827 {
1828   int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000;
1829
1830   printf_filtered
1831     ("      PC %s       SR %08lx       PR %08lx     MACH %08lx\n",
1832      paddr (get_frame_register_unsigned (frame,
1833                                          gdbarch_pc_regnum (current_gdbarch))),
1834      (long) get_frame_register_unsigned (frame, SR_REGNUM),
1835      (long) get_frame_register_unsigned (frame, PR_REGNUM),
1836      (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1837
1838   printf_filtered
1839     ("     GBR %08lx      VBR %08lx                       MACL %08lx\n",
1840      (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1841      (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1842      (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1843   printf_filtered
1844     ("     SSR %08lx      SPC %08lx     FPUL %08lx    FPSCR %08lx\n",
1845      (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1846      (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1847      (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1848      (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1849
1850   printf_filtered
1851     ("R0-R7    %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1852      (long) get_frame_register_unsigned (frame, 0),
1853      (long) get_frame_register_unsigned (frame, 1),
1854      (long) get_frame_register_unsigned (frame, 2),
1855      (long) get_frame_register_unsigned (frame, 3),
1856      (long) get_frame_register_unsigned (frame, 4),
1857      (long) get_frame_register_unsigned (frame, 5),
1858      (long) get_frame_register_unsigned (frame, 6),
1859      (long) get_frame_register_unsigned (frame, 7));
1860   printf_filtered
1861     ("R8-R15   %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1862      (long) get_frame_register_unsigned (frame, 8),
1863      (long) get_frame_register_unsigned (frame, 9),
1864      (long) get_frame_register_unsigned (frame, 10),
1865      (long) get_frame_register_unsigned (frame, 11),
1866      (long) get_frame_register_unsigned (frame, 12),
1867      (long) get_frame_register_unsigned (frame, 13),
1868      (long) get_frame_register_unsigned (frame, 14),
1869      (long) get_frame_register_unsigned (frame, 15));
1870
1871   printf_filtered
1872     (pr ? "DR0-DR6  %08lx%08lx  %08lx%08lx  %08lx%08lx  %08lx%08lx\n"
1873         : "FP0-FP7  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1874      (long) get_frame_register_unsigned
1875               (frame, gdbarch_fp0_regnum (current_gdbarch) + 0),
1876      (long) get_frame_register_unsigned
1877               (frame, gdbarch_fp0_regnum (current_gdbarch) + 1),
1878      (long) get_frame_register_unsigned
1879               (frame, gdbarch_fp0_regnum (current_gdbarch) + 2),
1880      (long) get_frame_register_unsigned
1881               (frame, gdbarch_fp0_regnum (current_gdbarch) + 3),
1882      (long) get_frame_register_unsigned
1883               (frame, gdbarch_fp0_regnum (current_gdbarch) + 4),
1884      (long) get_frame_register_unsigned
1885               (frame, gdbarch_fp0_regnum (current_gdbarch) + 5),
1886      (long) get_frame_register_unsigned
1887               (frame, gdbarch_fp0_regnum (current_gdbarch) + 6),
1888      (long) get_frame_register_unsigned
1889               (frame, gdbarch_fp0_regnum (current_gdbarch) + 7));
1890   printf_filtered
1891     (pr ? "DR8-DR14 %08lx%08lx  %08lx%08lx  %08lx%08lx  %08lx%08lx\n"
1892         : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1893      (long) get_frame_register_unsigned
1894               (frame, gdbarch_fp0_regnum (current_gdbarch) + 8),
1895      (long) get_frame_register_unsigned
1896               (frame, gdbarch_fp0_regnum (current_gdbarch) + 9),
1897      (long) get_frame_register_unsigned
1898               (frame, gdbarch_fp0_regnum (current_gdbarch) + 10),
1899      (long) get_frame_register_unsigned
1900               (frame, gdbarch_fp0_regnum (current_gdbarch) + 11),
1901      (long) get_frame_register_unsigned
1902               (frame, gdbarch_fp0_regnum (current_gdbarch) + 12),
1903      (long) get_frame_register_unsigned
1904               (frame, gdbarch_fp0_regnum (current_gdbarch) + 13),
1905      (long) get_frame_register_unsigned
1906               (frame, gdbarch_fp0_regnum (current_gdbarch) + 14),
1907      (long) get_frame_register_unsigned
1908               (frame, gdbarch_fp0_regnum (current_gdbarch) + 15));
1909 }
1910
1911 static void
1912 sh4_nofpu_show_regs (struct frame_info *frame)
1913 {
1914   printf_filtered
1915     ("      PC %s       SR %08lx       PR %08lx     MACH %08lx\n",
1916      paddr (get_frame_register_unsigned (frame,
1917                                          gdbarch_pc_regnum (current_gdbarch))),
1918      (long) get_frame_register_unsigned (frame, SR_REGNUM),
1919      (long) get_frame_register_unsigned (frame, PR_REGNUM),
1920      (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1921
1922   printf_filtered
1923     ("     GBR %08lx      VBR %08lx                       MACL %08lx\n",
1924      (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1925      (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1926      (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1927   printf_filtered
1928     ("     SSR %08lx      SPC %08lx     FPUL %08lx    FPSCR %08lx\n",
1929      (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1930      (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1931      (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1932      (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1933
1934   printf_filtered
1935     ("R0-R7    %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1936      (long) get_frame_register_unsigned (frame, 0),
1937      (long) get_frame_register_unsigned (frame, 1),
1938      (long) get_frame_register_unsigned (frame, 2),
1939      (long) get_frame_register_unsigned (frame, 3),
1940      (long) get_frame_register_unsigned (frame, 4),
1941      (long) get_frame_register_unsigned (frame, 5),
1942      (long) get_frame_register_unsigned (frame, 6),
1943      (long) get_frame_register_unsigned (frame, 7));
1944   printf_filtered
1945     ("R8-R15   %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1946      (long) get_frame_register_unsigned (frame, 8),
1947      (long) get_frame_register_unsigned (frame, 9),
1948      (long) get_frame_register_unsigned (frame, 10),
1949      (long) get_frame_register_unsigned (frame, 11),
1950      (long) get_frame_register_unsigned (frame, 12),
1951      (long) get_frame_register_unsigned (frame, 13),
1952      (long) get_frame_register_unsigned (frame, 14),
1953      (long) get_frame_register_unsigned (frame, 15));
1954 }
1955
1956 static void
1957 sh_dsp_show_regs (struct frame_info *frame)
1958 {
1959   printf_filtered
1960     ("      PC %s       SR %08lx       PR %08lx     MACH %08lx\n",
1961      paddr (get_frame_register_unsigned (frame,
1962                                          gdbarch_pc_regnum (current_gdbarch))),
1963      (long) get_frame_register_unsigned (frame, SR_REGNUM),
1964      (long) get_frame_register_unsigned (frame, PR_REGNUM),
1965      (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1966
1967   printf_filtered
1968     ("     GBR %08lx      VBR %08lx      DSR %08lx     MACL %08lx\n",
1969      (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1970      (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1971      (long) get_frame_register_unsigned (frame, DSR_REGNUM),
1972      (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1973
1974   printf_filtered
1975     ("R0-R7    %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1976      (long) get_frame_register_unsigned (frame, 0),
1977      (long) get_frame_register_unsigned (frame, 1),
1978      (long) get_frame_register_unsigned (frame, 2),
1979      (long) get_frame_register_unsigned (frame, 3),
1980      (long) get_frame_register_unsigned (frame, 4),
1981      (long) get_frame_register_unsigned (frame, 5),
1982      (long) get_frame_register_unsigned (frame, 6),
1983      (long) get_frame_register_unsigned (frame, 7));
1984   printf_filtered
1985     ("R8-R15   %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1986      (long) get_frame_register_unsigned (frame, 8),
1987      (long) get_frame_register_unsigned (frame, 9),
1988      (long) get_frame_register_unsigned (frame, 10),
1989      (long) get_frame_register_unsigned (frame, 11),
1990      (long) get_frame_register_unsigned (frame, 12),
1991      (long) get_frame_register_unsigned (frame, 13),
1992      (long) get_frame_register_unsigned (frame, 14),
1993      (long) get_frame_register_unsigned (frame, 15));
1994
1995   printf_filtered
1996     ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1997      (long) get_frame_register_unsigned (frame, A0G_REGNUM) & 0xff,
1998      (long) get_frame_register_unsigned (frame, A0_REGNUM),
1999      (long) get_frame_register_unsigned (frame, M0_REGNUM),
2000      (long) get_frame_register_unsigned (frame, X0_REGNUM),
2001      (long) get_frame_register_unsigned (frame, Y0_REGNUM),
2002      (long) get_frame_register_unsigned (frame, RS_REGNUM),
2003      (long) get_frame_register_unsigned (frame, MOD_REGNUM));
2004   printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
2005      (long) get_frame_register_unsigned (frame, A1G_REGNUM) & 0xff,
2006      (long) get_frame_register_unsigned (frame, A1_REGNUM),
2007      (long) get_frame_register_unsigned (frame, M1_REGNUM),
2008      (long) get_frame_register_unsigned (frame, X1_REGNUM),
2009      (long) get_frame_register_unsigned (frame, Y1_REGNUM),
2010      (long) get_frame_register_unsigned (frame, RE_REGNUM));
2011 }
2012
2013 static void
2014 sh_show_regs_command (char *args, int from_tty)
2015 {
2016   if (sh_show_regs)
2017     (*sh_show_regs) (get_current_frame ());
2018 }
2019
2020 static struct type *
2021 sh_sh2a_register_type (struct gdbarch *gdbarch, int reg_nr)
2022 {
2023   if ((reg_nr >= gdbarch_fp0_regnum (current_gdbarch)
2024        && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
2025     return builtin_type_float;
2026   else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
2027     return builtin_type_double;
2028   else
2029     return builtin_type_int;
2030 }
2031
2032 /* Return the GDB type object for the "standard" data type
2033    of data in register N.  */
2034 static struct type *
2035 sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr)
2036 {
2037   if ((reg_nr >= gdbarch_fp0_regnum (current_gdbarch)
2038        && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
2039     return builtin_type_float;
2040   else
2041     return builtin_type_int;
2042 }
2043
2044 static struct type *
2045 sh_sh4_build_float_register_type (int high)
2046 {
2047   struct type *temp;
2048
2049   temp = create_range_type (NULL, builtin_type_int, 0, high);
2050   return create_array_type (NULL, builtin_type_float, temp);
2051 }
2052
2053 static struct type *
2054 sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr)
2055 {
2056   if ((reg_nr >= gdbarch_fp0_regnum (current_gdbarch)
2057        && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
2058     return builtin_type_float;
2059   else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
2060     return builtin_type_double;
2061   else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
2062     return sh_sh4_build_float_register_type (3);
2063   else
2064     return builtin_type_int;
2065 }
2066
2067 static struct type *
2068 sh_default_register_type (struct gdbarch *gdbarch, int reg_nr)
2069 {
2070   return builtin_type_int;
2071 }
2072
2073 /* Is a register in a reggroup?
2074    The default code in reggroup.c doesn't identify system registers, some
2075    float registers or any of the vector registers.
2076    TODO: sh2a and dsp registers.  */
2077 int
2078 sh_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2079                         struct reggroup *reggroup)
2080 {
2081   if (gdbarch_register_name (current_gdbarch, regnum) == NULL
2082       || *gdbarch_register_name (current_gdbarch, regnum) == '\0')
2083     return 0;
2084
2085   if (reggroup == float_reggroup
2086       && (regnum == FPUL_REGNUM
2087           || regnum == FPSCR_REGNUM))
2088     return 1;
2089
2090   if (regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM)
2091     {
2092       if (reggroup == vector_reggroup || reggroup == float_reggroup)
2093         return 1;
2094       if (reggroup == general_reggroup)
2095         return 0;
2096     }
2097
2098   if (regnum == VBR_REGNUM
2099       || regnum == SR_REGNUM
2100       || regnum == FPSCR_REGNUM
2101       || regnum == SSR_REGNUM
2102       || regnum == SPC_REGNUM)
2103     {
2104       if (reggroup == system_reggroup)
2105         return 1;
2106       if (reggroup == general_reggroup)
2107         return 0;
2108     }
2109
2110   /* The default code can cope with any other registers.  */
2111   return default_register_reggroup_p (gdbarch, regnum, reggroup);
2112 }
2113
2114 /* On the sh4, the DRi pseudo registers are problematic if the target
2115    is little endian. When the user writes one of those registers, for
2116    instance with 'ser var $dr0=1', we want the double to be stored
2117    like this:
2118    fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
2119    fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2120
2121    This corresponds to little endian byte order & big endian word
2122    order.  However if we let gdb write the register w/o conversion, it
2123    will write fr0 and fr1 this way:
2124    fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2125    fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
2126    because it will consider fr0 and fr1 as a single LE stretch of memory.
2127
2128    To achieve what we want we must force gdb to store things in
2129    floatformat_ieee_double_littlebyte_bigword (which is defined in
2130    include/floatformat.h and libiberty/floatformat.c.
2131
2132    In case the target is big endian, there is no problem, the
2133    raw bytes will look like:
2134    fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
2135    fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2136
2137    The other pseudo registers (the FVs) also don't pose a problem
2138    because they are stored as 4 individual FP elements. */
2139
2140 static void
2141 sh_register_convert_to_virtual (int regnum, struct type *type,
2142                                 char *from, char *to)
2143 {
2144   if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
2145     {
2146       DOUBLEST val;
2147       floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
2148                                from, &val);
2149       store_typed_floating (to, type, val);
2150     }
2151   else
2152     error
2153       ("sh_register_convert_to_virtual called with non DR register number");
2154 }
2155
2156 static void
2157 sh_register_convert_to_raw (struct type *type, int regnum,
2158                             const void *from, void *to)
2159 {
2160   if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
2161     {
2162       DOUBLEST val = extract_typed_floating (from, type);
2163       floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword,
2164                                  &val, to);
2165     }
2166   else
2167     error (_("sh_register_convert_to_raw called with non DR register number"));
2168 }
2169
2170 /* For vectors of 4 floating point registers. */
2171 static int
2172 fv_reg_base_num (int fv_regnum)
2173 {
2174   int fp_regnum;
2175
2176   fp_regnum = gdbarch_fp0_regnum (current_gdbarch)
2177               + (fv_regnum - FV0_REGNUM) * 4;
2178   return fp_regnum;
2179 }
2180
2181 /* For double precision floating point registers, i.e 2 fp regs.*/
2182 static int
2183 dr_reg_base_num (int dr_regnum)
2184 {
2185   int fp_regnum;
2186
2187   fp_regnum = gdbarch_fp0_regnum (current_gdbarch)
2188               + (dr_regnum - DR0_REGNUM) * 2;
2189   return fp_regnum;
2190 }
2191
2192 static void
2193 sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2194                          int reg_nr, gdb_byte *buffer)
2195 {
2196   int base_regnum, portion;
2197   char temp_buffer[MAX_REGISTER_SIZE];
2198
2199   if (reg_nr == PSEUDO_BANK_REGNUM)
2200     regcache_raw_read (regcache, BANK_REGNUM, buffer);
2201   else
2202   if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
2203     {
2204       base_regnum = dr_reg_base_num (reg_nr);
2205
2206       /* Build the value in the provided buffer. */
2207       /* Read the real regs for which this one is an alias.  */
2208       for (portion = 0; portion < 2; portion++)
2209         regcache_raw_read (regcache, base_regnum + portion,
2210                            (temp_buffer
2211                             + register_size (gdbarch,
2212                                              base_regnum) * portion));
2213       /* We must pay attention to the endiannes. */
2214       sh_register_convert_to_virtual (reg_nr,
2215                                       register_type (gdbarch, reg_nr),
2216                                       temp_buffer, buffer);
2217     }
2218   else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
2219     {
2220       base_regnum = fv_reg_base_num (reg_nr);
2221
2222       /* Read the real regs for which this one is an alias.  */
2223       for (portion = 0; portion < 4; portion++)
2224         regcache_raw_read (regcache, base_regnum + portion,
2225                            ((char *) buffer
2226                             + register_size (gdbarch,
2227                                              base_regnum) * portion));
2228     }
2229 }
2230
2231 static void
2232 sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2233                           int reg_nr, const gdb_byte *buffer)
2234 {
2235   int base_regnum, portion;
2236   char temp_buffer[MAX_REGISTER_SIZE];
2237
2238   if (reg_nr == PSEUDO_BANK_REGNUM)
2239     {
2240       /* When the bank register is written to, the whole register bank
2241          is switched and all values in the bank registers must be read
2242          from the target/sim again. We're just invalidating the regcache
2243          so that a re-read happens next time it's necessary.  */
2244       int bregnum;
2245
2246       regcache_raw_write (regcache, BANK_REGNUM, buffer);
2247       for (bregnum = R0_BANK0_REGNUM; bregnum < MACLB_REGNUM; ++bregnum)
2248         regcache_invalidate (regcache, bregnum);
2249     }
2250   else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
2251     {
2252       base_regnum = dr_reg_base_num (reg_nr);
2253
2254       /* We must pay attention to the endiannes. */
2255       sh_register_convert_to_raw (register_type (gdbarch, reg_nr),
2256                                   reg_nr, buffer, temp_buffer);
2257
2258       /* Write the real regs for which this one is an alias.  */
2259       for (portion = 0; portion < 2; portion++)
2260         regcache_raw_write (regcache, base_regnum + portion,
2261                             (temp_buffer
2262                              + register_size (gdbarch,
2263                                               base_regnum) * portion));
2264     }
2265   else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
2266     {
2267       base_regnum = fv_reg_base_num (reg_nr);
2268
2269       /* Write the real regs for which this one is an alias.  */
2270       for (portion = 0; portion < 4; portion++)
2271         regcache_raw_write (regcache, base_regnum + portion,
2272                             ((char *) buffer
2273                              + register_size (gdbarch,
2274                                               base_regnum) * portion));
2275     }
2276 }
2277
2278 static int
2279 sh_dsp_register_sim_regno (int nr)
2280 {
2281   if (legacy_register_sim_regno (nr) < 0)
2282     return legacy_register_sim_regno (nr);
2283   if (nr >= DSR_REGNUM && nr <= Y1_REGNUM)
2284     return nr - DSR_REGNUM + SIM_SH_DSR_REGNUM;
2285   if (nr == MOD_REGNUM)
2286     return SIM_SH_MOD_REGNUM;
2287   if (nr == RS_REGNUM)
2288     return SIM_SH_RS_REGNUM;
2289   if (nr == RE_REGNUM)
2290     return SIM_SH_RE_REGNUM;
2291   if (nr >= DSP_R0_BANK_REGNUM && nr <= DSP_R7_BANK_REGNUM)
2292     return nr - DSP_R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM;
2293   return nr;
2294 }
2295
2296 static int
2297 sh_sh2a_register_sim_regno (int nr)
2298 {
2299   switch (nr)
2300     {
2301       case TBR_REGNUM:
2302         return SIM_SH_TBR_REGNUM;
2303       case IBNR_REGNUM:
2304         return SIM_SH_IBNR_REGNUM;
2305       case IBCR_REGNUM:
2306         return SIM_SH_IBCR_REGNUM;
2307       case BANK_REGNUM:
2308         return SIM_SH_BANK_REGNUM;
2309       case MACLB_REGNUM:
2310         return SIM_SH_BANK_MACL_REGNUM;
2311       case GBRB_REGNUM:
2312         return SIM_SH_BANK_GBR_REGNUM;
2313       case PRB_REGNUM:
2314         return SIM_SH_BANK_PR_REGNUM;
2315       case IVNB_REGNUM:
2316         return SIM_SH_BANK_IVN_REGNUM;
2317       case MACHB_REGNUM:
2318         return SIM_SH_BANK_MACH_REGNUM;
2319       default:
2320         break;
2321     }
2322   return legacy_register_sim_regno (nr);
2323 }
2324
2325 /* Set up the register unwinding such that call-clobbered registers are
2326    not displayed in frames >0 because the true value is not certain.
2327    The 'undefined' registers will show up as 'not available' unless the
2328    CFI says otherwise.
2329
2330    This function is currently set up for SH4 and compatible only.  */
2331
2332 static void
2333 sh_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
2334                           struct dwarf2_frame_state_reg *reg,
2335                           struct frame_info *next_frame)
2336 {
2337   /* Mark the PC as the destination for the return address.  */
2338   if (regnum == gdbarch_pc_regnum (current_gdbarch))
2339     reg->how = DWARF2_FRAME_REG_RA;
2340
2341   /* Mark the stack pointer as the call frame address.  */
2342   else if (regnum == gdbarch_sp_regnum (current_gdbarch))
2343     reg->how = DWARF2_FRAME_REG_CFA;
2344
2345   /* The above was taken from the default init_reg in dwarf2-frame.c
2346      while the below is SH specific.  */
2347
2348   /* Caller save registers.  */
2349   else if ((regnum >= R0_REGNUM && regnum <= R0_REGNUM+7)
2350            || (regnum >= FR0_REGNUM && regnum <= FR0_REGNUM+11)
2351            || (regnum >= DR0_REGNUM && regnum <= DR0_REGNUM+5)
2352            || (regnum >= FV0_REGNUM && regnum <= FV0_REGNUM+2)
2353            || (regnum == MACH_REGNUM)
2354            || (regnum == MACL_REGNUM)
2355            || (regnum == FPUL_REGNUM)
2356            || (regnum == SR_REGNUM))
2357     reg->how = DWARF2_FRAME_REG_UNDEFINED;
2358
2359   /* Callee save registers.  */
2360   else if ((regnum >= R0_REGNUM+8 && regnum <= R0_REGNUM+15)
2361            || (regnum >= FR0_REGNUM+12 && regnum <= FR0_REGNUM+15)
2362            || (regnum >= DR0_REGNUM+6 && regnum <= DR0_REGNUM+8)
2363            || (regnum == FV0_REGNUM+3))
2364     reg->how = DWARF2_FRAME_REG_SAME_VALUE;
2365
2366   /* Other registers.  These are not in the ABI and may or may not
2367      mean anything in frames >0 so don't show them.  */
2368   else if ((regnum >= R0_BANK0_REGNUM && regnum <= R0_BANK0_REGNUM+15)
2369            || (regnum == GBR_REGNUM)
2370            || (regnum == VBR_REGNUM)
2371            || (regnum == FPSCR_REGNUM)
2372            || (regnum == SSR_REGNUM)
2373            || (regnum == SPC_REGNUM))
2374     reg->how = DWARF2_FRAME_REG_UNDEFINED;
2375 }
2376
2377 static struct sh_frame_cache *
2378 sh_alloc_frame_cache (void)
2379 {
2380   struct sh_frame_cache *cache;
2381   int i;
2382
2383   cache = FRAME_OBSTACK_ZALLOC (struct sh_frame_cache);
2384
2385   /* Base address.  */
2386   cache->base = 0;
2387   cache->saved_sp = 0;
2388   cache->sp_offset = 0;
2389   cache->pc = 0;
2390
2391   /* Frameless until proven otherwise.  */
2392   cache->uses_fp = 0;
2393
2394   /* Saved registers.  We initialize these to -1 since zero is a valid
2395      offset (that's where fp is supposed to be stored).  */
2396   for (i = 0; i < SH_NUM_REGS; i++)
2397     {
2398       cache->saved_regs[i] = -1;
2399     }
2400
2401   return cache;
2402 }
2403
2404 static struct sh_frame_cache *
2405 sh_frame_cache (struct frame_info *next_frame, void **this_cache)
2406 {
2407   struct sh_frame_cache *cache;
2408   CORE_ADDR current_pc;
2409   int i;
2410
2411   if (*this_cache)
2412     return *this_cache;
2413
2414   cache = sh_alloc_frame_cache ();
2415   *this_cache = cache;
2416
2417   /* In principle, for normal frames, fp holds the frame pointer,
2418      which holds the base address for the current stack frame.
2419      However, for functions that don't need it, the frame pointer is
2420      optional.  For these "frameless" functions the frame pointer is
2421      actually the frame pointer of the calling frame. */
2422   cache->base = frame_unwind_register_unsigned (next_frame, FP_REGNUM);
2423   if (cache->base == 0)
2424     return cache;
2425
2426   cache->pc = frame_func_unwind (next_frame, NORMAL_FRAME);
2427   current_pc = frame_pc_unwind (next_frame);
2428   if (cache->pc != 0)
2429     {
2430       ULONGEST fpscr;
2431       fpscr = frame_unwind_register_unsigned (next_frame, FPSCR_REGNUM);
2432       sh_analyze_prologue (cache->pc, current_pc, cache, fpscr);
2433     }
2434
2435   if (!cache->uses_fp)
2436     {
2437       /* We didn't find a valid frame, which means that CACHE->base
2438          currently holds the frame pointer for our calling frame.  If
2439          we're at the start of a function, or somewhere half-way its
2440          prologue, the function's frame probably hasn't been fully
2441          setup yet.  Try to reconstruct the base address for the stack
2442          frame by looking at the stack pointer.  For truly "frameless"
2443          functions this might work too.  */
2444       cache->base = frame_unwind_register_unsigned
2445                     (next_frame, gdbarch_sp_regnum (current_gdbarch));
2446     }
2447
2448   /* Now that we have the base address for the stack frame we can
2449      calculate the value of sp in the calling frame.  */
2450   cache->saved_sp = cache->base + cache->sp_offset;
2451
2452   /* Adjust all the saved registers such that they contain addresses
2453      instead of offsets.  */
2454   for (i = 0; i < SH_NUM_REGS; i++)
2455     if (cache->saved_regs[i] != -1)
2456       cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i] - 4;
2457
2458   return cache;
2459 }
2460
2461 static void
2462 sh_frame_prev_register (struct frame_info *next_frame, void **this_cache,
2463                         int regnum, int *optimizedp,
2464                         enum lval_type *lvalp, CORE_ADDR *addrp,
2465                         int *realnump, gdb_byte *valuep)
2466 {
2467   struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
2468
2469   gdb_assert (regnum >= 0);
2470
2471   if (regnum == gdbarch_sp_regnum (current_gdbarch) && cache->saved_sp)
2472     {
2473       *optimizedp = 0;
2474       *lvalp = not_lval;
2475       *addrp = 0;
2476       *realnump = -1;
2477       if (valuep)
2478         {
2479           /* Store the value.  */
2480           store_unsigned_integer (valuep, 4, cache->saved_sp);
2481         }
2482       return;
2483     }
2484
2485   /* The PC of the previous frame is stored in the PR register of
2486      the current frame.  Frob regnum so that we pull the value from
2487      the correct place.  */
2488   if (regnum == gdbarch_pc_regnum (current_gdbarch))
2489     regnum = PR_REGNUM;
2490
2491   if (regnum < SH_NUM_REGS && cache->saved_regs[regnum] != -1)
2492     {
2493       *optimizedp = 0;
2494       *lvalp = lval_memory;
2495       *addrp = cache->saved_regs[regnum];
2496       *realnump = -1;
2497       if (valuep)
2498         {
2499           /* Read the value in from memory.  */
2500           read_memory (*addrp, valuep,
2501                        register_size (current_gdbarch, regnum));
2502         }
2503       return;
2504     }
2505
2506   *optimizedp = 0;
2507   *lvalp = lval_register;
2508   *addrp = 0;
2509   *realnump = regnum;
2510   if (valuep)
2511     frame_unwind_register (next_frame, (*realnump), valuep);
2512 }
2513
2514 static void
2515 sh_frame_this_id (struct frame_info *next_frame, void **this_cache,
2516                   struct frame_id *this_id)
2517 {
2518   struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
2519
2520   /* This marks the outermost frame.  */
2521   if (cache->base == 0)
2522     return;
2523
2524   *this_id = frame_id_build (cache->saved_sp, cache->pc);
2525 }
2526
2527 static const struct frame_unwind sh_frame_unwind = {
2528   NORMAL_FRAME,
2529   sh_frame_this_id,
2530   sh_frame_prev_register
2531 };
2532
2533 static const struct frame_unwind *
2534 sh_frame_sniffer (struct frame_info *next_frame)
2535 {
2536   return &sh_frame_unwind;
2537 }
2538
2539 static CORE_ADDR
2540 sh_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
2541 {
2542   return frame_unwind_register_unsigned (next_frame,
2543                                          gdbarch_sp_regnum (current_gdbarch));
2544 }
2545
2546 static CORE_ADDR
2547 sh_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2548 {
2549   return frame_unwind_register_unsigned (next_frame,
2550                                          gdbarch_pc_regnum (current_gdbarch));
2551 }
2552
2553 static struct frame_id
2554 sh_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
2555 {
2556   return frame_id_build (sh_unwind_sp (gdbarch, next_frame),
2557                          frame_pc_unwind (next_frame));
2558 }
2559
2560 static CORE_ADDR
2561 sh_frame_base_address (struct frame_info *next_frame, void **this_cache)
2562 {
2563   struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
2564
2565   return cache->base;
2566 }
2567
2568 static const struct frame_base sh_frame_base = {
2569   &sh_frame_unwind,
2570   sh_frame_base_address,
2571   sh_frame_base_address,
2572   sh_frame_base_address
2573 };
2574
2575 /* The epilogue is defined here as the area at the end of a function,
2576    either on the `ret' instruction itself or after an instruction which
2577    destroys the function's stack frame. */
2578 static int
2579 sh_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2580 {
2581   CORE_ADDR func_addr = 0, func_end = 0;
2582
2583   if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
2584     {
2585       ULONGEST inst;
2586       /* The sh epilogue is max. 14 bytes long.  Give another 14 bytes
2587          for a nop and some fixed data (e.g. big offsets) which are
2588          unfortunately also treated as part of the function (which
2589          means, they are below func_end. */
2590       CORE_ADDR addr = func_end - 28;
2591       if (addr < func_addr + 4)
2592         addr = func_addr + 4;
2593       if (pc < addr)
2594         return 0;
2595
2596       /* First search forward until hitting an rts. */
2597       while (addr < func_end
2598              && !IS_RTS (read_memory_unsigned_integer (addr, 2)))
2599         addr += 2;
2600       if (addr >= func_end)
2601         return 0;
2602
2603       /* At this point we should find a mov.l @r15+,r14 instruction,
2604          either before or after the rts.  If not, then the function has
2605          probably no "normal" epilogue and we bail out here. */
2606       inst = read_memory_unsigned_integer (addr - 2, 2);
2607       if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2)))
2608         addr -= 2;
2609       else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2)))
2610         return 0;
2611
2612       inst = read_memory_unsigned_integer (addr - 2, 2);
2613
2614       /* Step over possible lds.l @r15+,macl. */
2615       if (IS_MACL_LDS (inst))
2616         {
2617           addr -= 2;
2618           inst = read_memory_unsigned_integer (addr - 2, 2);
2619         }
2620
2621       /* Step over possible lds.l @r15+,pr. */
2622       if (IS_LDS (inst))
2623         {
2624           addr -= 2;
2625           inst = read_memory_unsigned_integer (addr - 2, 2);
2626         }
2627
2628       /* Step over possible mov r14,r15. */
2629       if (IS_MOV_FP_SP (inst))
2630         {
2631           addr -= 2;
2632           inst = read_memory_unsigned_integer (addr - 2, 2);
2633         }
2634
2635       /* Now check for FP adjustments, using add #imm,r14 or add rX, r14
2636          instructions. */
2637       while (addr > func_addr + 4
2638              && (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst)))
2639         {
2640           addr -= 2;
2641           inst = read_memory_unsigned_integer (addr - 2, 2);
2642         }
2643
2644       /* On SH2a check if the previous instruction was perhaps a MOVI20.
2645          That's allowed for the epilogue.  */
2646       if ((gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a
2647            || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a_nofpu)
2648           && addr > func_addr + 6
2649           && IS_MOVI20 (read_memory_unsigned_integer (addr - 4, 2)))
2650         addr -= 4;
2651
2652       if (pc >= addr)
2653         return 1;
2654     }
2655   return 0;
2656 }
2657 \f
2658
2659 static struct gdbarch *
2660 sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2661 {
2662   struct gdbarch *gdbarch;
2663
2664   sh_show_regs = sh_generic_show_regs;
2665   switch (info.bfd_arch_info->mach)
2666     {
2667     case bfd_mach_sh2e:
2668       sh_show_regs = sh2e_show_regs;
2669       break;
2670     case bfd_mach_sh2a:
2671       sh_show_regs = sh2a_show_regs;
2672       break;
2673     case bfd_mach_sh2a_nofpu:
2674       sh_show_regs = sh2a_nofpu_show_regs;
2675       break;
2676     case bfd_mach_sh_dsp:
2677       sh_show_regs = sh_dsp_show_regs;
2678       break;
2679
2680     case bfd_mach_sh3:
2681       sh_show_regs = sh3_show_regs;
2682       break;
2683
2684     case bfd_mach_sh3e:
2685       sh_show_regs = sh3e_show_regs;
2686       break;
2687
2688     case bfd_mach_sh3_dsp:
2689     case bfd_mach_sh4al_dsp:
2690       sh_show_regs = sh3_dsp_show_regs;
2691       break;
2692
2693     case bfd_mach_sh4:
2694     case bfd_mach_sh4a:
2695       sh_show_regs = sh4_show_regs;
2696       break;
2697
2698     case bfd_mach_sh4_nofpu:
2699     case bfd_mach_sh4a_nofpu:
2700       sh_show_regs = sh4_nofpu_show_regs;
2701       break;
2702
2703     case bfd_mach_sh5:
2704       sh_show_regs = sh64_show_regs;
2705       /* SH5 is handled entirely in sh64-tdep.c */
2706       return sh64_gdbarch_init (info, arches);
2707     }
2708
2709   /* If there is already a candidate, use it.  */
2710   arches = gdbarch_list_lookup_by_info (arches, &info);
2711   if (arches != NULL)
2712     return arches->gdbarch;
2713
2714   /* None found, create a new architecture from the information
2715      provided. */
2716   gdbarch = gdbarch_alloc (&info, NULL);
2717
2718   set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2719   set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2720   set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2721   set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2722   set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2723   set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2724   set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2725   set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2726
2727   set_gdbarch_num_regs (gdbarch, SH_NUM_REGS);
2728   set_gdbarch_sp_regnum (gdbarch, 15);
2729   set_gdbarch_pc_regnum (gdbarch, 16);
2730   set_gdbarch_fp0_regnum (gdbarch, -1);
2731   set_gdbarch_num_pseudo_regs (gdbarch, 0);
2732
2733   set_gdbarch_register_type (gdbarch, sh_default_register_type);
2734   set_gdbarch_register_reggroup_p (gdbarch, sh_register_reggroup_p);
2735
2736   set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);
2737
2738   set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh);
2739   set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
2740
2741   set_gdbarch_return_value (gdbarch, sh_return_value_nofpu);
2742
2743   set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
2744   set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2745
2746   set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu);
2747
2748   set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2749
2750   set_gdbarch_frame_align (gdbarch, sh_frame_align);
2751   set_gdbarch_unwind_sp (gdbarch, sh_unwind_sp);
2752   set_gdbarch_unwind_pc (gdbarch, sh_unwind_pc);
2753   set_gdbarch_unwind_dummy_id (gdbarch, sh_unwind_dummy_id);
2754   frame_base_set_default (gdbarch, &sh_frame_base);
2755
2756   set_gdbarch_in_function_epilogue_p (gdbarch, sh_in_function_epilogue_p);
2757
2758   dwarf2_frame_set_init_reg (gdbarch, sh_dwarf2_frame_init_reg);
2759
2760   switch (info.bfd_arch_info->mach)
2761     {
2762     case bfd_mach_sh:
2763       set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2764       break;
2765
2766     case bfd_mach_sh2:
2767       set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2768       break;
2769
2770     case bfd_mach_sh2e:
2771       /* doubles on sh2e and sh3e are actually 4 byte. */
2772       set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2773
2774       set_gdbarch_register_name (gdbarch, sh_sh2e_register_name);
2775       set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2776       set_gdbarch_fp0_regnum (gdbarch, 25);
2777       set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
2778       set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2779       break;
2780
2781     case bfd_mach_sh2a:
2782       set_gdbarch_register_name (gdbarch, sh_sh2a_register_name);
2783       set_gdbarch_register_type (gdbarch, sh_sh2a_register_type);
2784       set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno);
2785
2786       set_gdbarch_fp0_regnum (gdbarch, 25);
2787       set_gdbarch_num_pseudo_regs (gdbarch, 9);
2788       set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2789       set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
2790       set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
2791       set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2792       break;
2793
2794     case bfd_mach_sh2a_nofpu:
2795       set_gdbarch_register_name (gdbarch, sh_sh2a_nofpu_register_name);
2796       set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno);
2797
2798       set_gdbarch_num_pseudo_regs (gdbarch, 1);
2799       set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2800       set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
2801       break;
2802
2803     case bfd_mach_sh_dsp:
2804       set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name);
2805       set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2806       break;
2807
2808     case bfd_mach_sh3:
2809     case bfd_mach_sh3_nommu:
2810     case bfd_mach_sh2a_nofpu_or_sh3_nommu:
2811       set_gdbarch_register_name (gdbarch, sh_sh3_register_name);
2812       break;
2813
2814     case bfd_mach_sh3e:
2815     case bfd_mach_sh2a_or_sh3e:
2816       /* doubles on sh2e and sh3e are actually 4 byte. */
2817       set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2818
2819       set_gdbarch_register_name (gdbarch, sh_sh3e_register_name);
2820       set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2821       set_gdbarch_fp0_regnum (gdbarch, 25);
2822       set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
2823       set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2824       break;
2825
2826     case bfd_mach_sh3_dsp:
2827       set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name);
2828       set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2829       break;
2830
2831     case bfd_mach_sh4:
2832     case bfd_mach_sh4a:
2833       set_gdbarch_register_name (gdbarch, sh_sh4_register_name);
2834       set_gdbarch_register_type (gdbarch, sh_sh4_register_type);
2835       set_gdbarch_fp0_regnum (gdbarch, 25);
2836       set_gdbarch_num_pseudo_regs (gdbarch, 13);
2837       set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2838       set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
2839       set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
2840       set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2841       break;
2842
2843     case bfd_mach_sh4_nofpu:
2844     case bfd_mach_sh4a_nofpu:
2845     case bfd_mach_sh4_nommu_nofpu:
2846     case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu:
2847     case bfd_mach_sh2a_or_sh4:
2848       set_gdbarch_register_name (gdbarch, sh_sh4_nofpu_register_name);
2849       break;
2850
2851     case bfd_mach_sh4al_dsp:
2852       set_gdbarch_register_name (gdbarch, sh_sh4al_dsp_register_name);
2853       set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2854       break;
2855
2856     default:
2857       set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2858       break;
2859     }
2860
2861   /* Hook in ABI-specific overrides, if they have been registered.  */
2862   gdbarch_init_osabi (info, gdbarch);
2863
2864   frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer);
2865   frame_unwind_append_sniffer (gdbarch, sh_frame_sniffer);
2866
2867   return gdbarch;
2868 }
2869
2870 extern initialize_file_ftype _initialize_sh_tdep;       /* -Wmissing-prototypes */
2871
2872 void
2873 _initialize_sh_tdep (void)
2874 {
2875   struct cmd_list_element *c;
2876
2877   gdbarch_register (bfd_arch_sh, sh_gdbarch_init, NULL);
2878
2879   add_com ("regs", class_vars, sh_show_regs_command, _("Print all registers"));
2880 }