1 /* Target-dependent code for Hitachi Super-H, for GDB.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 2000 Free Software
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 Contributed by Steve Chamberlain
37 #include "inferior.h" /* for BEFORE_TEXT_END etc. */
38 #include "gdb_string.h"
39 #include "arch-utils.h"
41 /* A set of original names, to be used when restoring back to generic
42 registers from a specific set. */
44 static char *sh_generic_reg_names
[] = {
45 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
46 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
47 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
49 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
50 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
52 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
53 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
56 static char *sh_reg_names
[] = {
57 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
58 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
59 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
61 "", "", "", "", "", "", "", "",
62 "", "", "", "", "", "", "", "",
64 "", "", "", "", "", "", "", "",
65 "", "", "", "", "", "", "", "",
68 static char *sh3_reg_names
[] = {
69 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
70 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
71 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
73 "", "", "", "", "", "", "", "",
74 "", "", "", "", "", "", "", "",
76 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
77 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
80 static char *sh3e_reg_names
[] = {
81 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
82 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
83 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
85 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
86 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
88 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
89 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
92 static char *sh_dsp_reg_names
[] = {
93 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
94 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
95 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
97 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
98 "y0", "y1", "", "", "", "", "", "mod",
100 "rs", "re", "", "", "", "", "", "",
101 "", "", "", "", "", "", "", "",
104 static char *sh3_dsp_reg_names
[] = {
105 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
106 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
107 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
109 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
110 "y0", "y1", "", "", "", "", "", "mod",
112 "rs", "re", "", "", "", "", "", "",
113 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
118 char **sh_register_names
= sh3_reg_names
;
120 char **sh_register_names
= sh_generic_reg_names
;
128 sh_processor_type_table
[] =
131 sh_reg_names
, bfd_mach_sh
135 sh_reg_names
, bfd_mach_sh2
139 sh_dsp_reg_names
, bfd_mach_sh_dsp
143 sh3_reg_names
, bfd_mach_sh3
147 sh3_dsp_reg_names
, bfd_mach_sh3_dsp
151 sh3e_reg_names
, bfd_mach_sh3e
159 /* Prologue looks like
160 [mov.l <regs>,@-r15]...
165 Actually it can be more complicated than this. For instance, with
183 /* STS.L PR,@-r15 0100111100100010
184 r15-4-->r15, PR-->(r15) */
185 #define IS_STS(x) ((x) == 0x4f22)
187 /* MOV.L Rm,@-r15 00101111mmmm0110
188 r15-4-->r15, Rm-->(R15) */
189 #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
191 #define GET_PUSHED_REG(x) (((x) >> 4) & 0xf)
193 /* MOV r15,r14 0110111011110011
195 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
197 /* ADD #imm,r15 01111111iiiiiiii
199 #define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00)
201 #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
202 #define IS_SHLL_R3(x) ((x) == 0x4300)
204 /* ADD r3,r15 0011111100111100
206 #define IS_ADD_R3SP(x) ((x) == 0x3f3c)
208 /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
210 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
212 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
213 #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b)
215 /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011
217 MOV.L Rm,@(disp,Rn) Rm-->(dispx4+Rn) 0001nnnnmmmmdddd
219 MOV.L Rm,@Rn Rm-->(Rn) 0010nnnnmmmm0010
220 where Rm is one of r4,r5,r6,r7 which are the argument registers. */
221 #define IS_ARG_MOV(x) \
222 (((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \
223 || ((((x) & 0xf000) == 0x1000) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \
224 || ((((x) & 0xf00f) == 0x2002) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)))
226 /* MOV.L Rm,@(disp,r14) 00011110mmmmdddd
227 Rm-->(dispx4+r14) where Rm is one of r4,r5,r6,r7 */
228 #define IS_MOV_R14(x) \
229 ((((x) & 0xff00) == 0x1e) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070))
231 #define FPSCR_SZ (1 << 20)
233 /* Should call_function allocate stack space for a struct return? */
235 sh_use_struct_convention (gcc_p
, type
)
239 return (TYPE_LENGTH (type
) > 1);
242 /* Skip any prologue before the guts of a function */
244 /* Skip the prologue using the debug information. If this fails we'll
245 fall back on the 'guess' method below. */
250 struct symtab_and_line sal
;
251 CORE_ADDR func_addr
, func_end
;
253 /* If we can not find the symbol in the partial symbol table, then
254 there is no hope we can determine the function's start address
256 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
259 /* Get the line associated with FUNC_ADDR. */
260 sal
= find_pc_line (func_addr
, 0);
262 /* There are only two cases to consider. First, the end of the source line
263 is within the function bounds. In that case we return the end of the
264 source line. Second is the end of the source line extends beyond the
265 bounds of the current function. We need to use the slow code to
266 examine instructions in that case. */
267 if (sal
.end
< func_end
)
273 /* Here we look at each instruction in the function, and try to guess
274 where the prologue ends. Unfortunately this is not always
277 skip_prologue_hard_way (start_pc
)
286 for (here
= start_pc
, end
= start_pc
+ (2 * 28); here
< end
;)
288 int w
= read_memory_integer (here
, 2);
290 if (IS_FMOV (w
) || IS_PUSH (w
) || IS_STS (w
) || IS_MOV_R3 (w
)
291 || IS_ADD_R3SP (w
) || IS_ADD_SP (w
) || IS_SHLL_R3 (w
)
292 || IS_ARG_MOV (w
) || IS_MOV_R14 (w
))
296 else if (IS_MOV_SP_FP (w
))
302 /* Don't bail out yet, if we are before the copy of sp. */
311 sh_skip_prologue (pc
)
314 CORE_ADDR post_prologue_pc
;
316 /* See if we can determine the end of the prologue via the symbol table.
317 If so, then return either PC, or the PC after the prologue, whichever
320 post_prologue_pc
= after_prologue (pc
);
322 /* If after_prologue returned a useful address, then use it. Else
323 fall back on the instruction skipping code. */
324 if (post_prologue_pc
!= 0)
325 return max (pc
, post_prologue_pc
);
327 return (skip_prologue_hard_way (pc
));
330 /* Disassemble an instruction. */
333 gdb_print_insn_sh (memaddr
, info
)
335 disassemble_info
*info
;
337 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
338 return print_insn_sh (memaddr
, info
);
340 return print_insn_shl (memaddr
, info
);
343 /* Given a GDB frame, determine the address of the calling function's frame.
344 This will be used to create a new GDB frame struct, and then
345 INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
347 For us, the frame address is its stack pointer value, so we look up
348 the function prologue to determine the caller's sp value, and return it. */
351 sh_frame_chain (frame
)
352 struct frame_info
*frame
;
354 if (PC_IN_CALL_DUMMY (frame
->pc
, frame
->frame
, frame
->frame
))
355 return frame
->frame
; /* dummy frame same as caller's frame */
356 if (frame
->pc
&& !inside_entry_file (frame
->pc
))
357 return read_memory_integer (FRAME_FP (frame
) + frame
->f_offset
, 4);
362 /* Find REGNUM on the stack. Otherwise, it's in an active register. One thing
363 we might want to do here is to check REGNUM against the clobber mask, and
364 somehow flag it as invalid if it isn't saved on the stack somewhere. This
365 would provide a graceful failure mode when trying to get the value of
366 caller-saves registers for an inner frame. */
369 sh_find_callers_reg (fi
, regnum
)
370 struct frame_info
*fi
;
373 struct frame_saved_regs fsr
;
375 for (; fi
; fi
= fi
->next
)
376 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
377 /* When the caller requests PR from the dummy frame, we return PC because
378 that's where the previous routine appears to have done a call from. */
379 return generic_read_register_dummy (fi
->pc
, fi
->frame
, regnum
);
382 FRAME_FIND_SAVED_REGS (fi
, fsr
);
385 if (fsr
.regs
[regnum
] != 0)
386 return read_memory_integer (fsr
.regs
[regnum
],
387 REGISTER_RAW_SIZE (regnum
));
389 return read_register (regnum
);
392 /* Put here the code to store, into a struct frame_saved_regs, the
393 addresses of the saved registers of frame described by FRAME_INFO.
394 This includes special registers such as pc and fp saved in special
395 ways in the stack frame. sp is even more special: the address we
396 return for it IS the sp for the next frame. */
399 sh_frame_find_saved_regs (fi
, fsr
)
400 struct frame_info
*fi
;
401 struct frame_saved_regs
*fsr
;
411 char *dummy_regs
= generic_find_dummy_frame (fi
->pc
, fi
->frame
);
415 /* DANGER! This is ONLY going to work if the char buffer format of
416 the saved registers is byte-for-byte identical to the
417 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
418 memcpy (&fsr
->regs
, dummy_regs
, sizeof (fsr
));
422 fi
->leaf_function
= 1;
425 for (rn
= 0; rn
< NUM_REGS
; rn
++)
430 /* Loop around examining the prologue insns until we find something
431 that does not appear to be part of the prologue. But give up
432 after 20 of them, since we're getting silly then. */
434 pc
= get_pc_function_start (fi
->pc
);
441 for (opc
= pc
+ (2 * 28); pc
< opc
; pc
+= 2)
443 insn
= read_memory_integer (pc
, 2);
444 /* See where the registers will be saved to */
447 rn
= GET_PUSHED_REG (insn
);
451 else if (IS_STS (insn
))
453 where
[PR_REGNUM
] = depth
;
454 /* If we're storing the pr then this isn't a leaf */
455 fi
->leaf_function
= 0;
458 else if (IS_MOV_R3 (insn
))
460 r3_val
= ((insn
& 0xff) ^ 0x80) - 0x80;
462 else if (IS_SHLL_R3 (insn
))
466 else if (IS_ADD_R3SP (insn
))
470 else if (IS_ADD_SP (insn
))
472 depth
-= ((insn
& 0xff) ^ 0x80) - 0x80;
474 else if (IS_FMOV (insn
))
476 if (read_register (FPSCR_REGNUM
) & FPSCR_SZ
)
485 else if (IS_MOV_SP_FP (insn
))
487 #if 0 /* This used to just stop when it found an instruction that
488 was not considered part of the prologue. Now, we just
489 keep going looking for likely instructions. */
495 /* Now we know how deep things are, we can work out their addresses */
497 for (rn
= 0; rn
< NUM_REGS
; rn
++)
504 fsr
->regs
[rn
] = fi
->frame
- where
[rn
] + depth
- 4;
514 fsr
->regs
[SP_REGNUM
] = read_memory_integer (fsr
->regs
[FP_REGNUM
], 4);
518 fsr
->regs
[SP_REGNUM
] = fi
->frame
- 4;
521 fi
->f_offset
= depth
- where
[FP_REGNUM
] - 4;
522 /* Work out the return pc - either from the saved pr or the pr
526 /* initialize the extra info saved in a FRAME */
529 sh_init_extra_frame_info (fromleaf
, fi
)
531 struct frame_info
*fi
;
533 struct frame_saved_regs fsr
;
536 fi
->pc
= FRAME_SAVED_PC (fi
->next
);
538 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
540 /* We need to setup fi->frame here because run_stack_dummy gets it wrong
541 by assuming it's always FP. */
542 fi
->frame
= generic_read_register_dummy (fi
->pc
, fi
->frame
,
544 fi
->return_pc
= generic_read_register_dummy (fi
->pc
, fi
->frame
,
546 fi
->f_offset
= -(CALL_DUMMY_LENGTH
+ 4);
547 fi
->leaf_function
= 0;
552 FRAME_FIND_SAVED_REGS (fi
, fsr
);
553 fi
->return_pc
= sh_find_callers_reg (fi
, PR_REGNUM
);
557 /* Discard from the stack the innermost frame,
558 restoring all saved registers. */
563 register struct frame_info
*frame
= get_current_frame ();
564 register CORE_ADDR fp
;
566 struct frame_saved_regs fsr
;
568 if (PC_IN_CALL_DUMMY (frame
->pc
, frame
->frame
, frame
->frame
))
569 generic_pop_dummy_frame ();
572 fp
= FRAME_FP (frame
);
573 get_frame_saved_regs (frame
, &fsr
);
575 /* Copy regs from where they were saved in the frame */
576 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
577 if (fsr
.regs
[regnum
])
578 write_register (regnum
, read_memory_integer (fsr
.regs
[regnum
], 4));
580 write_register (PC_REGNUM
, frame
->return_pc
);
581 write_register (SP_REGNUM
, fp
+ 4);
583 flush_cached_frames ();
586 /* Function: push_arguments
587 Setup the function arguments for calling a function in the inferior.
589 On the Hitachi SH architecture, there are four registers (R4 to R7)
590 which are dedicated for passing function arguments. Up to the first
591 four arguments (depending on size) may go into these registers.
592 The rest go on the stack.
594 Arguments that are smaller than 4 bytes will still take up a whole
595 register or a whole 32-bit word on the stack, and will be
596 right-justified in the register or the stack word. This includes
597 chars, shorts, and small aggregate types.
599 Arguments that are larger than 4 bytes may be split between two or
600 more registers. If there are not enough registers free, an argument
601 may be passed partly in a register (or registers), and partly on the
602 stack. This includes doubles, long longs, and larger aggregates.
603 As far as I know, there is no upper limit to the size of aggregates
604 that will be passed in this way; in other words, the convention of
605 passing a pointer to a large aggregate instead of a copy is not used.
607 An exceptional case exists for struct arguments (and possibly other
608 aggregates such as arrays) if the size is larger than 4 bytes but
609 not a multiple of 4 bytes. In this case the argument is never split
610 between the registers and the stack, but instead is copied in its
611 entirety onto the stack, AND also copied into as many registers as
612 there is room for. In other words, space in registers permitting,
613 two copies of the same argument are passed in. As far as I can tell,
614 only the one on the stack is used, although that may be a function
615 of the level of compiler optimization. I suspect this is a compiler
616 bug. Arguments of these odd sizes are left-justified within the
617 word (as opposed to arguments smaller than 4 bytes, which are
621 If the function is to return an aggregate type such as a struct, it
622 is either returned in the normal return value register R0 (if its
623 size is no greater than one byte), or else the caller must allocate
624 space into which the callee will copy the return value (if the size
625 is greater than one byte). In this case, a pointer to the return
626 value location is passed into the callee in register R2, which does
627 not displace any of the other arguments passed in via registers R4
631 sh_push_arguments (nargs
, args
, sp
, struct_return
, struct_addr
)
635 unsigned char struct_return
;
636 CORE_ADDR struct_addr
;
638 int stack_offset
, stack_alloc
;
646 int odd_sized_struct
;
648 /* first force sp to a 4-byte alignment */
651 /* The "struct return pointer" pseudo-argument has its own dedicated
654 write_register (STRUCT_RETURN_REGNUM
, struct_addr
);
656 /* Now make sure there's space on the stack */
657 for (argnum
= 0, stack_alloc
= 0;
658 argnum
< nargs
; argnum
++)
659 stack_alloc
+= ((TYPE_LENGTH (VALUE_TYPE (args
[argnum
])) + 3) & ~3);
660 sp
-= stack_alloc
; /* make room on stack for args */
663 /* Now load as many as possible of the first arguments into
664 registers, and push the rest onto the stack. There are 16 bytes
665 in four registers available. Loop thru args from first to last. */
667 argreg
= ARG0_REGNUM
;
668 for (argnum
= 0, stack_offset
= 0; argnum
< nargs
; argnum
++)
670 type
= VALUE_TYPE (args
[argnum
]);
671 len
= TYPE_LENGTH (type
);
672 memset (valbuf
, 0, sizeof (valbuf
));
674 { /* value gets right-justified in the register or stack word */
675 memcpy (valbuf
+ (4 - len
),
676 (char *) VALUE_CONTENTS (args
[argnum
]), len
);
680 val
= (char *) VALUE_CONTENTS (args
[argnum
]);
682 if (len
> 4 && (len
& 3) != 0)
683 odd_sized_struct
= 1; /* such structs go entirely on stack */
685 odd_sized_struct
= 0;
688 if (argreg
> ARGLAST_REGNUM
|| odd_sized_struct
)
689 { /* must go on the stack */
690 write_memory (sp
+ stack_offset
, val
, 4);
693 /* NOTE WELL!!!!! This is not an "else if" clause!!!
694 That's because some *&^%$ things get passed on the stack
695 AND in the registers! */
696 if (argreg
<= ARGLAST_REGNUM
)
697 { /* there's room in a register */
698 regval
= extract_address (val
, REGISTER_RAW_SIZE (argreg
));
699 write_register (argreg
++, regval
);
701 /* Store the value 4 bytes at a time. This means that things
702 larger than 4 bytes may go partly in registers and partly
704 len
-= REGISTER_RAW_SIZE (argreg
);
705 val
+= REGISTER_RAW_SIZE (argreg
);
711 /* Function: push_return_address (pc)
712 Set up the return address for the inferior function call.
713 Needed for targets where we don't actually execute a JSR/BSR instruction */
716 sh_push_return_address (pc
, sp
)
720 write_register (PR_REGNUM
, CALL_DUMMY_ADDRESS ());
724 /* Function: fix_call_dummy
725 Poke the callee function's address into the destination part of
726 the CALL_DUMMY. The address is actually stored in a data word
727 following the actualy CALL_DUMMY instructions, which will load
728 it into a register using PC-relative addressing. This function
729 expects the CALL_DUMMY to look like this:
740 sh_fix_call_dummy (dummy
, pc
, fun
, nargs
, args
, type
, gcc_p
)
749 *(unsigned long *) (dummy
+ 8) = fun
;
754 /* Modify the actual processor type. */
757 sh_target_architecture_hook (ap
)
758 const bfd_arch_info_type
*ap
;
762 if (ap
->arch
!= bfd_arch_sh
)
765 for (i
= 0; sh_processor_type_table
[i
].regnames
!= NULL
; i
++)
767 if (sh_processor_type_table
[i
].mach
== ap
->mach
)
769 sh_register_names
= sh_processor_type_table
[i
].regnames
;
774 internal_error ("Architecture `%s' unreconized", ap
->printable_name
);
777 /* Print the registers in a form similar to the E7000 */
780 sh_show_regs (args
, from_tty
)
785 if (TARGET_ARCHITECTURE
->arch
== bfd_arch_sh
)
786 cpu
= TARGET_ARCHITECTURE
->mach
;
790 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
791 paddr (read_register (PC_REGNUM
)),
792 (long) read_register (SR_REGNUM
),
793 (long) read_register (PR_REGNUM
),
794 (long) read_register (MACH_REGNUM
),
795 (long) read_register (MACL_REGNUM
));
797 printf_filtered ("GBR=%08lx VBR=%08lx",
798 (long) read_register (GBR_REGNUM
),
799 (long) read_register (VBR_REGNUM
));
800 if (cpu
== bfd_mach_sh3
|| cpu
== bfd_mach_sh3e
|| cpu
== bfd_mach_sh3_dsp
801 || cpu
== bfd_mach_sh4
)
803 printf_filtered (" SSR=%08lx SPC=%08lx",
804 (long) read_register (SSR_REGNUM
),
805 (long) read_register (SPC_REGNUM
));
806 if (cpu
== bfd_mach_sh3e
|| cpu
== bfd_mach_sh4
)
808 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
809 (long) read_register (FPUL_REGNUM
),
810 (long) read_register (FPSCR_REGNUM
));
813 if (cpu
== bfd_mach_sh_dsp
|| cpu
== bfd_mach_sh3_dsp
)
814 printf_filtered (" DSR=%08lx", (long) read_register (DSR_REGNUM
));
816 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
817 (long) read_register (0),
818 (long) read_register (1),
819 (long) read_register (2),
820 (long) read_register (3),
821 (long) read_register (4),
822 (long) read_register (5),
823 (long) read_register (6),
824 (long) read_register (7));
825 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
826 (long) read_register (8),
827 (long) read_register (9),
828 (long) read_register (10),
829 (long) read_register (11),
830 (long) read_register (12),
831 (long) read_register (13),
832 (long) read_register (14),
833 (long) read_register (15));
834 if (cpu
== bfd_mach_sh3e
|| cpu
== bfd_mach_sh4
)
836 int pr
= cpu
== bfd_mach_sh4
&& (read_register (FPSCR_REGNUM
) & 0x80000);
839 ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
840 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
841 (long) read_register (FP0_REGNUM
+ 0),
842 (long) read_register (FP0_REGNUM
+ 1),
843 (long) read_register (FP0_REGNUM
+ 2),
844 (long) read_register (FP0_REGNUM
+ 3),
845 (long) read_register (FP0_REGNUM
+ 4),
846 (long) read_register (FP0_REGNUM
+ 5),
847 (long) read_register (FP0_REGNUM
+ 6),
848 (long) read_register (FP0_REGNUM
+ 7));
850 ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
851 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
852 (long) read_register (FP0_REGNUM
+ 8),
853 (long) read_register (FP0_REGNUM
+ 9),
854 (long) read_register (FP0_REGNUM
+ 10),
855 (long) read_register (FP0_REGNUM
+ 11),
856 (long) read_register (FP0_REGNUM
+ 12),
857 (long) read_register (FP0_REGNUM
+ 13),
858 (long) read_register (FP0_REGNUM
+ 14),
859 (long) read_register (FP0_REGNUM
+ 15));
861 /* FIXME: sh4 has more registers */
862 if (cpu
== bfd_mach_sh_dsp
|| cpu
== bfd_mach_sh3_dsp
)
864 printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
865 (long) read_register (A0G_REGNUM
) & 0xff,
866 (long) read_register (A0_REGNUM
),
867 (long) read_register (M0_REGNUM
),
868 (long) read_register (X0_REGNUM
),
869 (long) read_register (Y0_REGNUM
),
870 (long) read_register (RS_REGNUM
),
871 (long) read_register (MOD_REGNUM
));
872 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
873 (long) read_register (A1G_REGNUM
) & 0xff,
874 (long) read_register (A1_REGNUM
),
875 (long) read_register (M1_REGNUM
),
876 (long) read_register (X1_REGNUM
),
877 (long) read_register (Y1_REGNUM
),
878 (long) read_register (RE_REGNUM
));
882 /* Function: extract_return_value
883 Find a function's return value in the appropriate registers (in regbuf),
884 and copy it into valbuf. */
887 sh_extract_return_value (type
, regbuf
, valbuf
)
892 int len
= TYPE_LENGTH (type
);
895 memcpy (valbuf
, ((char *) regbuf
) + 4 - len
, len
);
897 memcpy (valbuf
, ((char *) regbuf
) + 8 - len
, len
);
899 error ("bad size for return value");
902 /* If the architecture is sh4 or sh3e, store a function's return value
903 in the R0 general register or in the FP0 floating point register,
904 depending on the type of the return value. In all the other cases
905 the result is stored in r0. */
907 sh_store_return_value (struct type
*type
, void *valbuf
)
910 if (TARGET_ARCHITECTURE
->arch
== bfd_arch_sh
)
911 cpu
= TARGET_ARCHITECTURE
->mach
;
914 if (cpu
== bfd_mach_sh3e
|| cpu
== bfd_mach_sh4
)
916 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
917 write_register_bytes (REGISTER_BYTE (FP0_REGNUM
), valbuf
, TYPE_LENGTH (type
));
919 write_register_bytes (REGISTER_BYTE (0), valbuf
, TYPE_LENGTH (type
));
922 write_register_bytes (REGISTER_BYTE (0), valbuf
, TYPE_LENGTH (type
));
926 _initialize_sh_tdep ()
928 struct cmd_list_element
*c
;
930 tm_print_insn
= gdb_print_insn_sh
;
932 target_architecture_hook
= sh_target_architecture_hook
;
934 add_com ("regs", class_vars
, sh_show_regs
, "Print all registers");