1 /* Target-dependent code for Renesas Super-H, for GDB.
3 Copyright (C) 1993-2005, 2007-2012 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20 /* Contributed by Steve Chamberlain
25 #include "frame-base.h"
26 #include "frame-unwind.h"
27 #include "dwarf2-frame.h"
35 #include "gdb_string.h"
36 #include "gdb_assert.h"
37 #include "arch-utils.h"
38 #include "floatformat.h"
42 #include "reggroups.h"
47 #include "sh64-tdep.h"
50 #include "solib-svr4.h"
55 /* registers numbers shared with the simulator. */
56 #include "gdb/sim-sh.h"
58 /* List of "set sh ..." and "show sh ..." commands. */
59 static struct cmd_list_element
*setshcmdlist
= NULL
;
60 static struct cmd_list_element
*showshcmdlist
= NULL
;
62 static const char sh_cc_gcc
[] = "gcc";
63 static const char sh_cc_renesas
[] = "renesas";
64 static const char *const sh_cc_enum
[] = {
70 static const char *sh_active_calling_convention
= sh_cc_gcc
;
72 #define SH_NUM_REGS 67
81 /* Flag showing that a frame has been created in the prologue code. */
84 /* Saved registers. */
85 CORE_ADDR saved_regs
[SH_NUM_REGS
];
90 sh_is_renesas_calling_convention (struct type
*func_type
)
96 func_type
= check_typedef (func_type
);
98 if (TYPE_CODE (func_type
) == TYPE_CODE_PTR
)
99 func_type
= check_typedef (TYPE_TARGET_TYPE (func_type
));
101 if (TYPE_CODE (func_type
) == TYPE_CODE_FUNC
102 && TYPE_CALLING_CONVENTION (func_type
) == DW_CC_GNU_renesas_sh
)
106 if (sh_active_calling_convention
== sh_cc_renesas
)
113 sh_sh_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
115 static char *register_names
[] = {
116 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
117 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
118 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
120 "", "", "", "", "", "", "", "",
121 "", "", "", "", "", "", "", "",
123 "", "", "", "", "", "", "", "",
124 "", "", "", "", "", "", "", "",
125 "", "", "", "", "", "", "", "",
129 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
131 return register_names
[reg_nr
];
135 sh_sh3_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
137 static char *register_names
[] = {
138 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
139 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
140 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
142 "", "", "", "", "", "", "", "",
143 "", "", "", "", "", "", "", "",
145 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
146 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
147 "", "", "", "", "", "", "", "",
151 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
153 return register_names
[reg_nr
];
157 sh_sh3e_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
159 static char *register_names
[] = {
160 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
161 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
162 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
164 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
165 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
167 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
168 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
169 "", "", "", "", "", "", "", "",
173 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
175 return register_names
[reg_nr
];
179 sh_sh2e_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
181 static char *register_names
[] = {
182 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
183 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
184 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
186 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
187 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
189 "", "", "", "", "", "", "", "",
190 "", "", "", "", "", "", "", "",
191 "", "", "", "", "", "", "", "",
195 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
197 return register_names
[reg_nr
];
201 sh_sh2a_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
203 static char *register_names
[] = {
204 /* general registers 0-15 */
205 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
206 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
208 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
211 /* floating point registers 25 - 40 */
212 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
213 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
216 /* 43 - 62. Banked registers. The bank number used is determined by
217 the bank register (63). */
218 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
219 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
220 "machb", "ivnb", "prb", "gbrb", "maclb",
221 /* 63: register bank number, not a real register but used to
222 communicate the register bank currently get/set. This register
223 is hidden to the user, who manipulates it using the pseudo
224 register called "bank" (67). See below. */
227 "ibcr", "ibnr", "tbr",
228 /* 67: register bank number, the user visible pseudo register. */
230 /* double precision (pseudo) 68 - 75 */
231 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
235 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
237 return register_names
[reg_nr
];
241 sh_sh2a_nofpu_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
243 static char *register_names
[] = {
244 /* general registers 0-15 */
245 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
246 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
248 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
251 /* floating point registers 25 - 40 */
252 "", "", "", "", "", "", "", "",
253 "", "", "", "", "", "", "", "",
256 /* 43 - 62. Banked registers. The bank number used is determined by
257 the bank register (63). */
258 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
259 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
260 "machb", "ivnb", "prb", "gbrb", "maclb",
261 /* 63: register bank number, not a real register but used to
262 communicate the register bank currently get/set. This register
263 is hidden to the user, who manipulates it using the pseudo
264 register called "bank" (67). See below. */
267 "ibcr", "ibnr", "tbr",
268 /* 67: register bank number, the user visible pseudo register. */
270 /* double precision (pseudo) 68 - 75 */
271 "", "", "", "", "", "", "", "",
275 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
277 return register_names
[reg_nr
];
281 sh_sh_dsp_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
283 static char *register_names
[] = {
284 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
285 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
286 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
288 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
289 "y0", "y1", "", "", "", "", "", "mod",
291 "rs", "re", "", "", "", "", "", "",
292 "", "", "", "", "", "", "", "",
293 "", "", "", "", "", "", "", "",
297 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
299 return register_names
[reg_nr
];
303 sh_sh3_dsp_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
305 static char *register_names
[] = {
306 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
307 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
308 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
310 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
311 "y0", "y1", "", "", "", "", "", "mod",
313 "rs", "re", "", "", "", "", "", "",
314 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
315 "", "", "", "", "", "", "", "",
316 "", "", "", "", "", "", "", "",
320 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
322 return register_names
[reg_nr
];
326 sh_sh4_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
328 static char *register_names
[] = {
329 /* general registers 0-15 */
330 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
331 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
333 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
336 /* floating point registers 25 - 40 */
337 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
338 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
342 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
344 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
345 "", "", "", "", "", "", "", "",
346 /* pseudo bank register. */
348 /* double precision (pseudo) 59 - 66 */
349 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
350 /* vectors (pseudo) 67 - 70 */
351 "fv0", "fv4", "fv8", "fv12",
352 /* FIXME: missing XF 71 - 86 */
353 /* FIXME: missing XD 87 - 94 */
357 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
359 return register_names
[reg_nr
];
363 sh_sh4_nofpu_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
365 static char *register_names
[] = {
366 /* general registers 0-15 */
367 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
368 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
370 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
373 /* floating point registers 25 - 40 -- not for nofpu target */
374 "", "", "", "", "", "", "", "",
375 "", "", "", "", "", "", "", "",
379 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
381 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
382 "", "", "", "", "", "", "", "",
383 /* pseudo bank register. */
385 /* double precision (pseudo) 59 - 66 -- not for nofpu target */
386 "", "", "", "", "", "", "", "",
387 /* vectors (pseudo) 67 - 70 -- not for nofpu target */
392 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
394 return register_names
[reg_nr
];
398 sh_sh4al_dsp_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
400 static char *register_names
[] = {
401 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
402 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
403 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
405 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
406 "y0", "y1", "", "", "", "", "", "mod",
408 "rs", "re", "", "", "", "", "", "",
409 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
410 "", "", "", "", "", "", "", "",
411 "", "", "", "", "", "", "", "",
415 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
417 return register_names
[reg_nr
];
420 static const unsigned char *
421 sh_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
, int *lenptr
)
423 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes. */
424 static unsigned char breakpoint
[] = { 0xc3, 0xc3 };
426 /* For remote stub targets, trapa #20 is used. */
427 if (strcmp (target_shortname
, "remote") == 0)
429 static unsigned char big_remote_breakpoint
[] = { 0xc3, 0x20 };
430 static unsigned char little_remote_breakpoint
[] = { 0x20, 0xc3 };
432 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
434 *lenptr
= sizeof (big_remote_breakpoint
);
435 return big_remote_breakpoint
;
439 *lenptr
= sizeof (little_remote_breakpoint
);
440 return little_remote_breakpoint
;
444 *lenptr
= sizeof (breakpoint
);
448 /* Prologue looks like
452 sub <room_for_loca_vars>,r15
455 Actually it can be more complicated than this but that's it, basically. */
457 #define GET_SOURCE_REG(x) (((x) >> 4) & 0xf)
458 #define GET_TARGET_REG(x) (((x) >> 8) & 0xf)
460 /* JSR @Rm 0100mmmm00001011 */
461 #define IS_JSR(x) (((x) & 0xf0ff) == 0x400b)
463 /* STS.L PR,@-r15 0100111100100010
464 r15-4-->r15, PR-->(r15) */
465 #define IS_STS(x) ((x) == 0x4f22)
467 /* STS.L MACL,@-r15 0100111100010010
468 r15-4-->r15, MACL-->(r15) */
469 #define IS_MACL_STS(x) ((x) == 0x4f12)
471 /* MOV.L Rm,@-r15 00101111mmmm0110
472 r15-4-->r15, Rm-->(R15) */
473 #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
475 /* MOV r15,r14 0110111011110011
477 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
479 /* ADD #imm,r15 01111111iiiiiiii
481 #define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00)
483 #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
484 #define IS_SHLL_R3(x) ((x) == 0x4300)
486 /* ADD r3,r15 0011111100111100
488 #define IS_ADD_R3SP(x) ((x) == 0x3f3c)
490 /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
491 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
492 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
493 /* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to
494 make this entirely clear. */
495 /* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */
496 #define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b)
498 /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */
499 #define IS_MOV_ARG_TO_REG(x) \
500 (((x) & 0xf00f) == 0x6003 && \
501 ((x) & 0x00f0) >= 0x0040 && \
502 ((x) & 0x00f0) <= 0x0070)
503 /* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */
504 #define IS_MOV_ARG_TO_IND_R14(x) \
505 (((x) & 0xff0f) == 0x2e02 && \
506 ((x) & 0x00f0) >= 0x0040 && \
507 ((x) & 0x00f0) <= 0x0070)
508 /* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */
509 #define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \
510 (((x) & 0xff00) == 0x1e00 && \
511 ((x) & 0x00f0) >= 0x0040 && \
512 ((x) & 0x00f0) <= 0x0070)
514 /* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */
515 #define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000)
516 /* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */
517 #define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000)
518 /* MOVI20 #imm20,Rn 0000nnnniiii0000 */
519 #define IS_MOVI20(x) (((x) & 0xf00f) == 0x0000)
520 /* SUB Rn,R15 00111111nnnn1000 */
521 #define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08)
523 #define FPSCR_SZ (1 << 20)
525 /* The following instructions are used for epilogue testing. */
526 #define IS_RESTORE_FP(x) ((x) == 0x6ef6)
527 #define IS_RTS(x) ((x) == 0x000b)
528 #define IS_LDS(x) ((x) == 0x4f26)
529 #define IS_MACL_LDS(x) ((x) == 0x4f16)
530 #define IS_MOV_FP_SP(x) ((x) == 0x6fe3)
531 #define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c)
532 #define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00)
535 sh_analyze_prologue (struct gdbarch
*gdbarch
,
536 CORE_ADDR pc
, CORE_ADDR limit_pc
,
537 struct sh_frame_cache
*cache
, ULONGEST fpscr
)
539 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
544 int reg
, sav_reg
= -1;
547 for (; pc
< limit_pc
; pc
+= 2)
549 inst
= read_memory_unsigned_integer (pc
, 2, byte_order
);
550 /* See where the registers will be saved to. */
553 cache
->saved_regs
[GET_SOURCE_REG (inst
)] = cache
->sp_offset
;
554 cache
->sp_offset
+= 4;
556 else if (IS_STS (inst
))
558 cache
->saved_regs
[PR_REGNUM
] = cache
->sp_offset
;
559 cache
->sp_offset
+= 4;
561 else if (IS_MACL_STS (inst
))
563 cache
->saved_regs
[MACL_REGNUM
] = cache
->sp_offset
;
564 cache
->sp_offset
+= 4;
566 else if (IS_MOV_R3 (inst
))
568 r3_val
= ((inst
& 0xff) ^ 0x80) - 0x80;
570 else if (IS_SHLL_R3 (inst
))
574 else if (IS_ADD_R3SP (inst
))
576 cache
->sp_offset
+= -r3_val
;
578 else if (IS_ADD_IMM_SP (inst
))
580 offset
= ((inst
& 0xff) ^ 0x80) - 0x80;
581 cache
->sp_offset
-= offset
;
583 else if (IS_MOVW_PCREL_TO_REG (inst
))
587 reg
= GET_TARGET_REG (inst
);
591 offset
= (inst
& 0xff) << 1;
593 read_memory_integer ((pc
+ 4) + offset
, 2, byte_order
);
597 else if (IS_MOVL_PCREL_TO_REG (inst
))
601 reg
= GET_TARGET_REG (inst
);
605 offset
= (inst
& 0xff) << 2;
607 read_memory_integer (((pc
& 0xfffffffc) + 4) + offset
,
612 else if (IS_MOVI20 (inst
)
613 && (pc
+ 2 < limit_pc
))
617 reg
= GET_TARGET_REG (inst
);
621 sav_offset
= GET_SOURCE_REG (inst
) << 16;
622 /* MOVI20 is a 32 bit instruction! */
625 |= read_memory_unsigned_integer (pc
, 2, byte_order
);
626 /* Now sav_offset contains an unsigned 20 bit value.
627 It must still get sign extended. */
628 if (sav_offset
& 0x00080000)
629 sav_offset
|= 0xfff00000;
633 else if (IS_SUB_REG_FROM_SP (inst
))
635 reg
= GET_SOURCE_REG (inst
);
636 if (sav_reg
> 0 && reg
== sav_reg
)
640 cache
->sp_offset
+= sav_offset
;
642 else if (IS_FPUSH (inst
))
644 if (fpscr
& FPSCR_SZ
)
646 cache
->sp_offset
+= 8;
650 cache
->sp_offset
+= 4;
653 else if (IS_MOV_SP_FP (inst
))
656 /* Don't go any further than six more instructions. */
657 limit_pc
= min (limit_pc
, pc
+ (2 * 6));
660 /* At this point, only allow argument register moves to other
661 registers or argument register moves to @(X,fp) which are
662 moving the register arguments onto the stack area allocated
663 by a former add somenumber to SP call. Don't allow moving
664 to an fp indirect address above fp + cache->sp_offset. */
665 for (; pc
< limit_pc
; pc
+= 2)
667 inst
= read_memory_integer (pc
, 2, byte_order
);
668 if (IS_MOV_ARG_TO_IND_R14 (inst
))
670 reg
= GET_SOURCE_REG (inst
);
671 if (cache
->sp_offset
> 0)
672 cache
->saved_regs
[reg
] = cache
->sp_offset
;
674 else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst
))
676 reg
= GET_SOURCE_REG (inst
);
677 offset
= (inst
& 0xf) * 4;
678 if (cache
->sp_offset
> offset
)
679 cache
->saved_regs
[reg
] = cache
->sp_offset
- offset
;
681 else if (IS_MOV_ARG_TO_REG (inst
))
688 else if (IS_JSR (inst
))
690 /* We have found a jsr that has been scheduled into the prologue.
691 If we continue the scan and return a pc someplace after this,
692 then setting a breakpoint on this function will cause it to
693 appear to be called after the function it is calling via the
694 jsr, which will be very confusing. Most likely the next
695 instruction is going to be IS_MOV_SP_FP in the delay slot. If
696 so, note that before returning the current pc. */
697 if (pc
+ 2 < limit_pc
)
699 inst
= read_memory_integer (pc
+ 2, 2, byte_order
);
700 if (IS_MOV_SP_FP (inst
))
705 #if 0 /* This used to just stop when it found an instruction
706 that was not considered part of the prologue. Now,
707 we just keep going looking for likely
717 /* Skip any prologue before the guts of a function. */
719 sh_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
721 CORE_ADDR post_prologue_pc
, func_addr
, func_end_addr
, limit_pc
;
722 struct sh_frame_cache cache
;
724 /* See if we can determine the end of the prologue via the symbol table.
725 If so, then return either PC, or the PC after the prologue, whichever
727 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end_addr
))
729 post_prologue_pc
= skip_prologue_using_sal (gdbarch
, func_addr
);
730 if (post_prologue_pc
!= 0)
731 return max (pc
, post_prologue_pc
);
734 /* Can't determine prologue from the symbol table, need to examine
737 /* Find an upper limit on the function prologue using the debug
738 information. If the debug information could not be used to provide
739 that bound, then use an arbitrary large number as the upper bound. */
740 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
742 /* Don't go any further than 28 instructions. */
743 limit_pc
= pc
+ (2 * 28);
745 /* Do not allow limit_pc to be past the function end, if we know
746 where that end is... */
747 if (func_end_addr
!= 0)
748 limit_pc
= min (limit_pc
, func_end_addr
);
750 cache
.sp_offset
= -4;
751 post_prologue_pc
= sh_analyze_prologue (gdbarch
, pc
, limit_pc
, &cache
, 0);
753 pc
= post_prologue_pc
;
760 Aggregate types not bigger than 8 bytes that have the same size and
761 alignment as one of the integer scalar types are returned in the
762 same registers as the integer type they match.
764 For example, a 2-byte aligned structure with size 2 bytes has the
765 same size and alignment as a short int, and will be returned in R0.
766 A 4-byte aligned structure with size 8 bytes has the same size and
767 alignment as a long long int, and will be returned in R0 and R1.
769 When an aggregate type is returned in R0 and R1, R0 contains the
770 first four bytes of the aggregate, and R1 contains the
771 remainder. If the size of the aggregate type is not a multiple of 4
772 bytes, the aggregate is tail-padded up to a multiple of 4
773 bytes. The value of the padding is undefined. For little-endian
774 targets the padding will appear at the most significant end of the
775 last element, for big-endian targets the padding appears at the
776 least significant end of the last element.
778 All other aggregate types are returned by address. The caller
779 function passes the address of an area large enough to hold the
780 aggregate value in R2. The called function stores the result in
783 To reiterate, structs smaller than 8 bytes could also be returned
784 in memory, if they don't pass the "same size and alignment as an
789 struct s { char c[3]; } wibble;
790 struct s foo(void) { return wibble; }
792 the return value from foo() will be in memory, not
793 in R0, because there is no 3-byte integer type.
797 struct s { char c[2]; } wibble;
798 struct s foo(void) { return wibble; }
800 because a struct containing two chars has alignment 1, that matches
801 type char, but size 2, that matches type short. There's no integer
802 type that has alignment 1 and size 2, so the struct is returned in
806 sh_use_struct_convention (int renesas_abi
, struct type
*type
)
808 int len
= TYPE_LENGTH (type
);
809 int nelem
= TYPE_NFIELDS (type
);
811 /* The Renesas ABI returns aggregate types always on stack. */
812 if (renesas_abi
&& (TYPE_CODE (type
) == TYPE_CODE_STRUCT
813 || TYPE_CODE (type
) == TYPE_CODE_UNION
))
816 /* Non-power of 2 length types and types bigger than 8 bytes (which don't
817 fit in two registers anyway) use struct convention. */
818 if (len
!= 1 && len
!= 2 && len
!= 4 && len
!= 8)
821 /* Scalar types and aggregate types with exactly one field are aligned
822 by definition. They are returned in registers. */
826 /* If the first field in the aggregate has the same length as the entire
827 aggregate type, the type is returned in registers. */
828 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, 0)) == len
)
831 /* If the size of the aggregate is 8 bytes and the first field is
832 of size 4 bytes its alignment is equal to long long's alignment,
833 so it's returned in registers. */
834 if (len
== 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type
, 0)) == 4)
837 /* Otherwise use struct convention. */
842 sh_use_struct_convention_nofpu (int renesas_abi
, struct type
*type
)
844 /* The Renesas ABI returns long longs/doubles etc. always on stack. */
845 if (renesas_abi
&& TYPE_NFIELDS (type
) == 0 && TYPE_LENGTH (type
) >= 8)
847 return sh_use_struct_convention (renesas_abi
, type
);
851 sh_frame_align (struct gdbarch
*ignore
, CORE_ADDR sp
)
856 /* Function: push_dummy_call (formerly push_arguments)
857 Setup the function arguments for calling a function in the inferior.
859 On the Renesas SH architecture, there are four registers (R4 to R7)
860 which are dedicated for passing function arguments. Up to the first
861 four arguments (depending on size) may go into these registers.
862 The rest go on the stack.
864 MVS: Except on SH variants that have floating point registers.
865 In that case, float and double arguments are passed in the same
866 manner, but using FP registers instead of GP registers.
868 Arguments that are smaller than 4 bytes will still take up a whole
869 register or a whole 32-bit word on the stack, and will be
870 right-justified in the register or the stack word. This includes
871 chars, shorts, and small aggregate types.
873 Arguments that are larger than 4 bytes may be split between two or
874 more registers. If there are not enough registers free, an argument
875 may be passed partly in a register (or registers), and partly on the
876 stack. This includes doubles, long longs, and larger aggregates.
877 As far as I know, there is no upper limit to the size of aggregates
878 that will be passed in this way; in other words, the convention of
879 passing a pointer to a large aggregate instead of a copy is not used.
881 MVS: The above appears to be true for the SH variants that do not
882 have an FPU, however those that have an FPU appear to copy the
883 aggregate argument onto the stack (and not place it in registers)
884 if it is larger than 16 bytes (four GP registers).
886 An exceptional case exists for struct arguments (and possibly other
887 aggregates such as arrays) if the size is larger than 4 bytes but
888 not a multiple of 4 bytes. In this case the argument is never split
889 between the registers and the stack, but instead is copied in its
890 entirety onto the stack, AND also copied into as many registers as
891 there is room for. In other words, space in registers permitting,
892 two copies of the same argument are passed in. As far as I can tell,
893 only the one on the stack is used, although that may be a function
894 of the level of compiler optimization. I suspect this is a compiler
895 bug. Arguments of these odd sizes are left-justified within the
896 word (as opposed to arguments smaller than 4 bytes, which are
899 If the function is to return an aggregate type such as a struct, it
900 is either returned in the normal return value register R0 (if its
901 size is no greater than one byte), or else the caller must allocate
902 space into which the callee will copy the return value (if the size
903 is greater than one byte). In this case, a pointer to the return
904 value location is passed into the callee in register R2, which does
905 not displace any of the other arguments passed in via registers R4
908 /* Helper function to justify value in register according to endianess. */
910 sh_justify_value_in_reg (struct gdbarch
*gdbarch
, struct value
*val
, int len
)
912 static char valbuf
[4];
914 memset (valbuf
, 0, sizeof (valbuf
));
917 /* value gets right-justified in the register or stack word. */
918 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
919 memcpy (valbuf
+ (4 - len
), (char *) value_contents (val
), len
);
921 memcpy (valbuf
, (char *) value_contents (val
), len
);
924 return (char *) value_contents (val
);
927 /* Helper function to eval number of bytes to allocate on stack. */
929 sh_stack_allocsize (int nargs
, struct value
**args
)
933 stack_alloc
+= ((TYPE_LENGTH (value_type (args
[nargs
])) + 3) & ~3);
937 /* Helper functions for getting the float arguments right. Registers usage
938 depends on the ABI and the endianess. The comments should enlighten how
939 it's intended to work. */
941 /* This array stores which of the float arg registers are already in use. */
942 static int flt_argreg_array
[FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
+ 1];
944 /* This function just resets the above array to "no reg used so far". */
946 sh_init_flt_argreg (void)
948 memset (flt_argreg_array
, 0, sizeof flt_argreg_array
);
951 /* This function returns the next register to use for float arg passing.
952 It returns either a valid value between FLOAT_ARG0_REGNUM and
953 FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns
954 FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available.
956 Note that register number 0 in flt_argreg_array corresponds with the
957 real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is
958 29) the parity of the register number is preserved, which is important
959 for the double register passing test (see the "argreg & 1" test below). */
961 sh_next_flt_argreg (struct gdbarch
*gdbarch
, int len
, struct type
*func_type
)
965 /* First search for the next free register. */
966 for (argreg
= 0; argreg
<= FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
;
968 if (!flt_argreg_array
[argreg
])
971 /* No register left? */
972 if (argreg
> FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
)
973 return FLOAT_ARGLAST_REGNUM
+ 1;
977 /* Doubles are always starting in a even register number. */
980 /* In gcc ABI, the skipped register is lost for further argument
981 passing now. Not so in Renesas ABI. */
982 if (!sh_is_renesas_calling_convention (func_type
))
983 flt_argreg_array
[argreg
] = 1;
987 /* No register left? */
988 if (argreg
> FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
)
989 return FLOAT_ARGLAST_REGNUM
+ 1;
991 /* Also mark the next register as used. */
992 flt_argreg_array
[argreg
+ 1] = 1;
994 else if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
995 && !sh_is_renesas_calling_convention (func_type
))
997 /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */
998 if (!flt_argreg_array
[argreg
+ 1])
1001 flt_argreg_array
[argreg
] = 1;
1002 return FLOAT_ARG0_REGNUM
+ argreg
;
1005 /* Helper function which figures out, if a type is treated like a float type.
1007 The FPU ABIs have a special way how to treat types as float types.
1008 Structures with exactly one member, which is of type float or double, are
1009 treated exactly as the base types float or double:
1019 are handled the same way as just
1025 As a result, arguments of these struct types are pushed into floating point
1026 registers exactly as floats or doubles, using the same decision algorithm.
1028 The same is valid if these types are used as function return types. The
1029 above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1
1030 or even using struct convention as it is for other structs. */
1033 sh_treat_as_flt_p (struct type
*type
)
1035 /* Ordinary float types are obviously treated as float. */
1036 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1038 /* Otherwise non-struct types are not treated as float. */
1039 if (TYPE_CODE (type
) != TYPE_CODE_STRUCT
)
1041 /* Otherwise structs with more than one memeber are not treated as float. */
1042 if (TYPE_NFIELDS (type
) != 1)
1044 /* Otherwise if the type of that member is float, the whole type is
1045 treated as float. */
1046 if (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0)) == TYPE_CODE_FLT
)
1048 /* Otherwise it's not treated as float. */
1053 sh_push_dummy_call_fpu (struct gdbarch
*gdbarch
,
1054 struct value
*function
,
1055 struct regcache
*regcache
,
1056 CORE_ADDR bp_addr
, int nargs
,
1057 struct value
**args
,
1058 CORE_ADDR sp
, int struct_return
,
1059 CORE_ADDR struct_addr
)
1061 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1062 int stack_offset
= 0;
1063 int argreg
= ARG0_REGNUM
;
1066 struct type
*func_type
= value_type (function
);
1070 int len
, reg_size
= 0;
1071 int pass_on_stack
= 0;
1073 int last_reg_arg
= INT_MAX
;
1075 /* The Renesas ABI expects all varargs arguments, plus the last
1076 non-vararg argument to be on the stack, no matter how many
1077 registers have been used so far. */
1078 if (sh_is_renesas_calling_convention (func_type
)
1079 && TYPE_VARARGS (func_type
))
1080 last_reg_arg
= TYPE_NFIELDS (func_type
) - 2;
1082 /* First force sp to a 4-byte alignment. */
1083 sp
= sh_frame_align (gdbarch
, sp
);
1085 /* Make room on stack for args. */
1086 sp
-= sh_stack_allocsize (nargs
, args
);
1088 /* Initialize float argument mechanism. */
1089 sh_init_flt_argreg ();
1091 /* Now load as many as possible of the first arguments into
1092 registers, and push the rest onto the stack. There are 16 bytes
1093 in four registers available. Loop thru args from first to last. */
1094 for (argnum
= 0; argnum
< nargs
; argnum
++)
1096 type
= value_type (args
[argnum
]);
1097 len
= TYPE_LENGTH (type
);
1098 val
= sh_justify_value_in_reg (gdbarch
, args
[argnum
], len
);
1100 /* Some decisions have to be made how various types are handled.
1101 This also differs in different ABIs. */
1104 /* Find out the next register to use for a floating point value. */
1105 treat_as_flt
= sh_treat_as_flt_p (type
);
1107 flt_argreg
= sh_next_flt_argreg (gdbarch
, len
, func_type
);
1108 /* In Renesas ABI, long longs and aggregate types are always passed
1110 else if (sh_is_renesas_calling_convention (func_type
)
1111 && ((TYPE_CODE (type
) == TYPE_CODE_INT
&& len
== 8)
1112 || TYPE_CODE (type
) == TYPE_CODE_STRUCT
1113 || TYPE_CODE (type
) == TYPE_CODE_UNION
))
1115 /* In contrast to non-FPU CPUs, arguments are never split between
1116 registers and stack. If an argument doesn't fit in the remaining
1117 registers it's always pushed entirely on the stack. */
1118 else if (len
> ((ARGLAST_REGNUM
- argreg
+ 1) * 4))
1123 if ((treat_as_flt
&& flt_argreg
> FLOAT_ARGLAST_REGNUM
)
1124 || (!treat_as_flt
&& (argreg
> ARGLAST_REGNUM
1126 || argnum
> last_reg_arg
)
1128 /* The data goes entirely on the stack, 4-byte aligned. */
1129 reg_size
= (len
+ 3) & ~3;
1130 write_memory (sp
+ stack_offset
, val
, reg_size
);
1131 stack_offset
+= reg_size
;
1133 else if (treat_as_flt
&& flt_argreg
<= FLOAT_ARGLAST_REGNUM
)
1135 /* Argument goes in a float argument register. */
1136 reg_size
= register_size (gdbarch
, flt_argreg
);
1137 regval
= extract_unsigned_integer (val
, reg_size
, byte_order
);
1138 /* In little endian mode, float types taking two registers
1139 (doubles on sh4, long doubles on sh2e, sh3e and sh4) must
1140 be stored swapped in the argument registers. The below
1141 code first writes the first 32 bits in the next but one
1142 register, increments the val and len values accordingly
1143 and then proceeds as normal by writing the second 32 bits
1144 into the next register. */
1145 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
1146 && TYPE_LENGTH (type
) == 2 * reg_size
)
1148 regcache_cooked_write_unsigned (regcache
, flt_argreg
+ 1,
1152 regval
= extract_unsigned_integer (val
, reg_size
,
1155 regcache_cooked_write_unsigned (regcache
, flt_argreg
++, regval
);
1157 else if (!treat_as_flt
&& argreg
<= ARGLAST_REGNUM
)
1159 /* there's room in a register */
1160 reg_size
= register_size (gdbarch
, argreg
);
1161 regval
= extract_unsigned_integer (val
, reg_size
, byte_order
);
1162 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
1164 /* Store the value one register at a time or in one step on
1173 if (sh_is_renesas_calling_convention (func_type
))
1174 /* If the function uses the Renesas ABI, subtract another 4 bytes from
1175 the stack and store the struct return address there. */
1176 write_memory_unsigned_integer (sp
-= 4, 4, byte_order
, struct_addr
);
1178 /* Using the gcc ABI, the "struct return pointer" pseudo-argument has
1179 its own dedicated register. */
1180 regcache_cooked_write_unsigned (regcache
,
1181 STRUCT_RETURN_REGNUM
, struct_addr
);
1184 /* Store return address. */
1185 regcache_cooked_write_unsigned (regcache
, PR_REGNUM
, bp_addr
);
1187 /* Update stack pointer. */
1188 regcache_cooked_write_unsigned (regcache
,
1189 gdbarch_sp_regnum (gdbarch
), sp
);
1195 sh_push_dummy_call_nofpu (struct gdbarch
*gdbarch
,
1196 struct value
*function
,
1197 struct regcache
*regcache
,
1199 int nargs
, struct value
**args
,
1200 CORE_ADDR sp
, int struct_return
,
1201 CORE_ADDR struct_addr
)
1203 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1204 int stack_offset
= 0;
1205 int argreg
= ARG0_REGNUM
;
1207 struct type
*func_type
= value_type (function
);
1211 int len
, reg_size
= 0;
1212 int pass_on_stack
= 0;
1213 int last_reg_arg
= INT_MAX
;
1215 /* The Renesas ABI expects all varargs arguments, plus the last
1216 non-vararg argument to be on the stack, no matter how many
1217 registers have been used so far. */
1218 if (sh_is_renesas_calling_convention (func_type
)
1219 && TYPE_VARARGS (func_type
))
1220 last_reg_arg
= TYPE_NFIELDS (func_type
) - 2;
1222 /* First force sp to a 4-byte alignment. */
1223 sp
= sh_frame_align (gdbarch
, sp
);
1225 /* Make room on stack for args. */
1226 sp
-= sh_stack_allocsize (nargs
, args
);
1228 /* Now load as many as possible of the first arguments into
1229 registers, and push the rest onto the stack. There are 16 bytes
1230 in four registers available. Loop thru args from first to last. */
1231 for (argnum
= 0; argnum
< nargs
; argnum
++)
1233 type
= value_type (args
[argnum
]);
1234 len
= TYPE_LENGTH (type
);
1235 val
= sh_justify_value_in_reg (gdbarch
, args
[argnum
], len
);
1237 /* Some decisions have to be made how various types are handled.
1238 This also differs in different ABIs. */
1240 /* Renesas ABI pushes doubles and long longs entirely on stack.
1241 Same goes for aggregate types. */
1242 if (sh_is_renesas_calling_convention (func_type
)
1243 && ((TYPE_CODE (type
) == TYPE_CODE_INT
&& len
>= 8)
1244 || (TYPE_CODE (type
) == TYPE_CODE_FLT
&& len
>= 8)
1245 || TYPE_CODE (type
) == TYPE_CODE_STRUCT
1246 || TYPE_CODE (type
) == TYPE_CODE_UNION
))
1250 if (argreg
> ARGLAST_REGNUM
|| pass_on_stack
1251 || argnum
> last_reg_arg
)
1253 /* The remainder of the data goes entirely on the stack,
1255 reg_size
= (len
+ 3) & ~3;
1256 write_memory (sp
+ stack_offset
, val
, reg_size
);
1257 stack_offset
+= reg_size
;
1259 else if (argreg
<= ARGLAST_REGNUM
)
1261 /* There's room in a register. */
1262 reg_size
= register_size (gdbarch
, argreg
);
1263 regval
= extract_unsigned_integer (val
, reg_size
, byte_order
);
1264 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
1266 /* Store the value reg_size bytes at a time. This means that things
1267 larger than reg_size bytes may go partly in registers and partly
1276 if (sh_is_renesas_calling_convention (func_type
))
1277 /* If the function uses the Renesas ABI, subtract another 4 bytes from
1278 the stack and store the struct return address there. */
1279 write_memory_unsigned_integer (sp
-= 4, 4, byte_order
, struct_addr
);
1281 /* Using the gcc ABI, the "struct return pointer" pseudo-argument has
1282 its own dedicated register. */
1283 regcache_cooked_write_unsigned (regcache
,
1284 STRUCT_RETURN_REGNUM
, struct_addr
);
1287 /* Store return address. */
1288 regcache_cooked_write_unsigned (regcache
, PR_REGNUM
, bp_addr
);
1290 /* Update stack pointer. */
1291 regcache_cooked_write_unsigned (regcache
,
1292 gdbarch_sp_regnum (gdbarch
), sp
);
1297 /* Find a function's return value in the appropriate registers (in
1298 regbuf), and copy it into valbuf. Extract from an array REGBUF
1299 containing the (raw) register state a function return value of type
1300 TYPE, and copy that, in virtual format, into VALBUF. */
1302 sh_extract_return_value_nofpu (struct type
*type
, struct regcache
*regcache
,
1305 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1306 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1307 int len
= TYPE_LENGTH (type
);
1308 int return_register
= R0_REGNUM
;
1315 regcache_cooked_read_unsigned (regcache
, R0_REGNUM
, &c
);
1316 store_unsigned_integer (valbuf
, len
, byte_order
, c
);
1320 int i
, regnum
= R0_REGNUM
;
1321 for (i
= 0; i
< len
; i
+= 4)
1322 regcache_raw_read (regcache
, regnum
++, (char *) valbuf
+ i
);
1325 error (_("bad size for return value"));
1329 sh_extract_return_value_fpu (struct type
*type
, struct regcache
*regcache
,
1332 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1333 if (sh_treat_as_flt_p (type
))
1335 int len
= TYPE_LENGTH (type
);
1336 int i
, regnum
= gdbarch_fp0_regnum (gdbarch
);
1337 for (i
= 0; i
< len
; i
+= 4)
1338 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
1339 regcache_raw_read (regcache
, regnum
++,
1340 (char *) valbuf
+ len
- 4 - i
);
1342 regcache_raw_read (regcache
, regnum
++, (char *) valbuf
+ i
);
1345 sh_extract_return_value_nofpu (type
, regcache
, valbuf
);
1348 /* Write into appropriate registers a function return value
1349 of type TYPE, given in virtual format.
1350 If the architecture is sh4 or sh3e, store a function's return value
1351 in the R0 general register or in the FP0 floating point register,
1352 depending on the type of the return value. In all the other cases
1353 the result is stored in r0, left-justified. */
1355 sh_store_return_value_nofpu (struct type
*type
, struct regcache
*regcache
,
1358 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1359 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1361 int len
= TYPE_LENGTH (type
);
1365 val
= extract_unsigned_integer (valbuf
, len
, byte_order
);
1366 regcache_cooked_write_unsigned (regcache
, R0_REGNUM
, val
);
1370 int i
, regnum
= R0_REGNUM
;
1371 for (i
= 0; i
< len
; i
+= 4)
1372 regcache_raw_write (regcache
, regnum
++, (char *) valbuf
+ i
);
1377 sh_store_return_value_fpu (struct type
*type
, struct regcache
*regcache
,
1380 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1381 if (sh_treat_as_flt_p (type
))
1383 int len
= TYPE_LENGTH (type
);
1384 int i
, regnum
= gdbarch_fp0_regnum (gdbarch
);
1385 for (i
= 0; i
< len
; i
+= 4)
1386 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
1387 regcache_raw_write (regcache
, regnum
++,
1388 (char *) valbuf
+ len
- 4 - i
);
1390 regcache_raw_write (regcache
, regnum
++, (char *) valbuf
+ i
);
1393 sh_store_return_value_nofpu (type
, regcache
, valbuf
);
1396 static enum return_value_convention
1397 sh_return_value_nofpu (struct gdbarch
*gdbarch
, struct value
*function
,
1398 struct type
*type
, struct regcache
*regcache
,
1399 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1401 struct type
*func_type
= function
? value_type (function
) : NULL
;
1403 if (sh_use_struct_convention_nofpu (
1404 sh_is_renesas_calling_convention (func_type
), type
))
1405 return RETURN_VALUE_STRUCT_CONVENTION
;
1407 sh_store_return_value_nofpu (type
, regcache
, writebuf
);
1409 sh_extract_return_value_nofpu (type
, regcache
, readbuf
);
1410 return RETURN_VALUE_REGISTER_CONVENTION
;
1413 static enum return_value_convention
1414 sh_return_value_fpu (struct gdbarch
*gdbarch
, struct value
*function
,
1415 struct type
*type
, struct regcache
*regcache
,
1416 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1418 struct type
*func_type
= function
? value_type (function
) : NULL
;
1420 if (sh_use_struct_convention (
1421 sh_is_renesas_calling_convention (func_type
), type
))
1422 return RETURN_VALUE_STRUCT_CONVENTION
;
1424 sh_store_return_value_fpu (type
, regcache
, writebuf
);
1426 sh_extract_return_value_fpu (type
, regcache
, readbuf
);
1427 return RETURN_VALUE_REGISTER_CONVENTION
;
1430 static struct type
*
1431 sh_sh2a_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
1433 if ((reg_nr
>= gdbarch_fp0_regnum (gdbarch
)
1434 && (reg_nr
<= FP_LAST_REGNUM
)) || (reg_nr
== FPUL_REGNUM
))
1435 return builtin_type (gdbarch
)->builtin_float
;
1436 else if (reg_nr
>= DR0_REGNUM
&& reg_nr
<= DR_LAST_REGNUM
)
1437 return builtin_type (gdbarch
)->builtin_double
;
1439 return builtin_type (gdbarch
)->builtin_int
;
1442 /* Return the GDB type object for the "standard" data type
1443 of data in register N. */
1444 static struct type
*
1445 sh_sh3e_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
1447 if ((reg_nr
>= gdbarch_fp0_regnum (gdbarch
)
1448 && (reg_nr
<= FP_LAST_REGNUM
)) || (reg_nr
== FPUL_REGNUM
))
1449 return builtin_type (gdbarch
)->builtin_float
;
1451 return builtin_type (gdbarch
)->builtin_int
;
1454 static struct type
*
1455 sh_sh4_build_float_register_type (struct gdbarch
*gdbarch
, int high
)
1457 return lookup_array_range_type (builtin_type (gdbarch
)->builtin_float
,
1461 static struct type
*
1462 sh_sh4_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
1464 if ((reg_nr
>= gdbarch_fp0_regnum (gdbarch
)
1465 && (reg_nr
<= FP_LAST_REGNUM
)) || (reg_nr
== FPUL_REGNUM
))
1466 return builtin_type (gdbarch
)->builtin_float
;
1467 else if (reg_nr
>= DR0_REGNUM
&& reg_nr
<= DR_LAST_REGNUM
)
1468 return builtin_type (gdbarch
)->builtin_double
;
1469 else if (reg_nr
>= FV0_REGNUM
&& reg_nr
<= FV_LAST_REGNUM
)
1470 return sh_sh4_build_float_register_type (gdbarch
, 3);
1472 return builtin_type (gdbarch
)->builtin_int
;
1475 static struct type
*
1476 sh_default_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
1478 return builtin_type (gdbarch
)->builtin_int
;
1481 /* Is a register in a reggroup?
1482 The default code in reggroup.c doesn't identify system registers, some
1483 float registers or any of the vector registers.
1484 TODO: sh2a and dsp registers. */
1486 sh_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
1487 struct reggroup
*reggroup
)
1489 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
1490 || *gdbarch_register_name (gdbarch
, regnum
) == '\0')
1493 if (reggroup
== float_reggroup
1494 && (regnum
== FPUL_REGNUM
1495 || regnum
== FPSCR_REGNUM
))
1498 if (regnum
>= FV0_REGNUM
&& regnum
<= FV_LAST_REGNUM
)
1500 if (reggroup
== vector_reggroup
|| reggroup
== float_reggroup
)
1502 if (reggroup
== general_reggroup
)
1506 if (regnum
== VBR_REGNUM
1507 || regnum
== SR_REGNUM
1508 || regnum
== FPSCR_REGNUM
1509 || regnum
== SSR_REGNUM
1510 || regnum
== SPC_REGNUM
)
1512 if (reggroup
== system_reggroup
)
1514 if (reggroup
== general_reggroup
)
1518 /* The default code can cope with any other registers. */
1519 return default_register_reggroup_p (gdbarch
, regnum
, reggroup
);
1522 /* On the sh4, the DRi pseudo registers are problematic if the target
1523 is little endian. When the user writes one of those registers, for
1524 instance with 'ser var $dr0=1', we want the double to be stored
1526 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1527 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1529 This corresponds to little endian byte order & big endian word
1530 order. However if we let gdb write the register w/o conversion, it
1531 will write fr0 and fr1 this way:
1532 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1533 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1534 because it will consider fr0 and fr1 as a single LE stretch of memory.
1536 To achieve what we want we must force gdb to store things in
1537 floatformat_ieee_double_littlebyte_bigword (which is defined in
1538 include/floatformat.h and libiberty/floatformat.c.
1540 In case the target is big endian, there is no problem, the
1541 raw bytes will look like:
1542 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
1543 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1545 The other pseudo registers (the FVs) also don't pose a problem
1546 because they are stored as 4 individual FP elements. */
1549 sh_register_convert_to_virtual (int regnum
, struct type
*type
,
1550 char *from
, char *to
)
1552 if (regnum
>= DR0_REGNUM
&& regnum
<= DR_LAST_REGNUM
)
1555 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword
,
1557 store_typed_floating (to
, type
, val
);
1561 ("sh_register_convert_to_virtual called with non DR register number");
1565 sh_register_convert_to_raw (struct type
*type
, int regnum
,
1566 const void *from
, void *to
)
1568 if (regnum
>= DR0_REGNUM
&& regnum
<= DR_LAST_REGNUM
)
1570 DOUBLEST val
= extract_typed_floating (from
, type
);
1571 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword
,
1575 error (_("sh_register_convert_to_raw called with non DR register number"));
1578 /* For vectors of 4 floating point registers. */
1580 fv_reg_base_num (struct gdbarch
*gdbarch
, int fv_regnum
)
1584 fp_regnum
= gdbarch_fp0_regnum (gdbarch
)
1585 + (fv_regnum
- FV0_REGNUM
) * 4;
1589 /* For double precision floating point registers, i.e 2 fp regs. */
1591 dr_reg_base_num (struct gdbarch
*gdbarch
, int dr_regnum
)
1595 fp_regnum
= gdbarch_fp0_regnum (gdbarch
)
1596 + (dr_regnum
- DR0_REGNUM
) * 2;
1600 /* Concatenate PORTIONS contiguous raw registers starting at
1601 BASE_REGNUM into BUFFER. */
1603 static enum register_status
1604 pseudo_register_read_portions (struct gdbarch
*gdbarch
,
1605 struct regcache
*regcache
,
1607 int base_regnum
, gdb_byte
*buffer
)
1611 for (portion
= 0; portion
< portions
; portion
++)
1613 enum register_status status
;
1616 b
= buffer
+ register_size (gdbarch
, base_regnum
) * portion
;
1617 status
= regcache_raw_read (regcache
, base_regnum
+ portion
, b
);
1618 if (status
!= REG_VALID
)
1625 static enum register_status
1626 sh_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1627 int reg_nr
, gdb_byte
*buffer
)
1630 char temp_buffer
[MAX_REGISTER_SIZE
];
1631 enum register_status status
;
1633 if (reg_nr
== PSEUDO_BANK_REGNUM
)
1634 return regcache_raw_read (regcache
, BANK_REGNUM
, buffer
);
1635 else if (reg_nr
>= DR0_REGNUM
&& reg_nr
<= DR_LAST_REGNUM
)
1637 base_regnum
= dr_reg_base_num (gdbarch
, reg_nr
);
1639 /* Build the value in the provided buffer. */
1640 /* Read the real regs for which this one is an alias. */
1641 status
= pseudo_register_read_portions (gdbarch
, regcache
,
1642 2, base_regnum
, temp_buffer
);
1643 if (status
== REG_VALID
)
1645 /* We must pay attention to the endiannes. */
1646 sh_register_convert_to_virtual (reg_nr
,
1647 register_type (gdbarch
, reg_nr
),
1648 temp_buffer
, buffer
);
1652 else if (reg_nr
>= FV0_REGNUM
&& reg_nr
<= FV_LAST_REGNUM
)
1654 base_regnum
= fv_reg_base_num (gdbarch
, reg_nr
);
1656 /* Read the real regs for which this one is an alias. */
1657 return pseudo_register_read_portions (gdbarch
, regcache
,
1658 4, base_regnum
, buffer
);
1661 gdb_assert_not_reached ("invalid pseudo register number");
1665 sh_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1666 int reg_nr
, const gdb_byte
*buffer
)
1668 int base_regnum
, portion
;
1669 char temp_buffer
[MAX_REGISTER_SIZE
];
1671 if (reg_nr
== PSEUDO_BANK_REGNUM
)
1673 /* When the bank register is written to, the whole register bank
1674 is switched and all values in the bank registers must be read
1675 from the target/sim again. We're just invalidating the regcache
1676 so that a re-read happens next time it's necessary. */
1679 regcache_raw_write (regcache
, BANK_REGNUM
, buffer
);
1680 for (bregnum
= R0_BANK0_REGNUM
; bregnum
< MACLB_REGNUM
; ++bregnum
)
1681 regcache_invalidate (regcache
, bregnum
);
1683 else if (reg_nr
>= DR0_REGNUM
&& reg_nr
<= DR_LAST_REGNUM
)
1685 base_regnum
= dr_reg_base_num (gdbarch
, reg_nr
);
1687 /* We must pay attention to the endiannes. */
1688 sh_register_convert_to_raw (register_type (gdbarch
, reg_nr
),
1689 reg_nr
, buffer
, temp_buffer
);
1691 /* Write the real regs for which this one is an alias. */
1692 for (portion
= 0; portion
< 2; portion
++)
1693 regcache_raw_write (regcache
, base_regnum
+ portion
,
1695 + register_size (gdbarch
,
1696 base_regnum
) * portion
));
1698 else if (reg_nr
>= FV0_REGNUM
&& reg_nr
<= FV_LAST_REGNUM
)
1700 base_regnum
= fv_reg_base_num (gdbarch
, reg_nr
);
1702 /* Write the real regs for which this one is an alias. */
1703 for (portion
= 0; portion
< 4; portion
++)
1704 regcache_raw_write (regcache
, base_regnum
+ portion
,
1706 + register_size (gdbarch
,
1707 base_regnum
) * portion
));
1712 sh_dsp_register_sim_regno (struct gdbarch
*gdbarch
, int nr
)
1714 if (legacy_register_sim_regno (gdbarch
, nr
) < 0)
1715 return legacy_register_sim_regno (gdbarch
, nr
);
1716 if (nr
>= DSR_REGNUM
&& nr
<= Y1_REGNUM
)
1717 return nr
- DSR_REGNUM
+ SIM_SH_DSR_REGNUM
;
1718 if (nr
== MOD_REGNUM
)
1719 return SIM_SH_MOD_REGNUM
;
1720 if (nr
== RS_REGNUM
)
1721 return SIM_SH_RS_REGNUM
;
1722 if (nr
== RE_REGNUM
)
1723 return SIM_SH_RE_REGNUM
;
1724 if (nr
>= DSP_R0_BANK_REGNUM
&& nr
<= DSP_R7_BANK_REGNUM
)
1725 return nr
- DSP_R0_BANK_REGNUM
+ SIM_SH_R0_BANK_REGNUM
;
1730 sh_sh2a_register_sim_regno (struct gdbarch
*gdbarch
, int nr
)
1735 return SIM_SH_TBR_REGNUM
;
1737 return SIM_SH_IBNR_REGNUM
;
1739 return SIM_SH_IBCR_REGNUM
;
1741 return SIM_SH_BANK_REGNUM
;
1743 return SIM_SH_BANK_MACL_REGNUM
;
1745 return SIM_SH_BANK_GBR_REGNUM
;
1747 return SIM_SH_BANK_PR_REGNUM
;
1749 return SIM_SH_BANK_IVN_REGNUM
;
1751 return SIM_SH_BANK_MACH_REGNUM
;
1755 return legacy_register_sim_regno (gdbarch
, nr
);
1758 /* Set up the register unwinding such that call-clobbered registers are
1759 not displayed in frames >0 because the true value is not certain.
1760 The 'undefined' registers will show up as 'not available' unless the
1763 This function is currently set up for SH4 and compatible only. */
1766 sh_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1767 struct dwarf2_frame_state_reg
*reg
,
1768 struct frame_info
*this_frame
)
1770 /* Mark the PC as the destination for the return address. */
1771 if (regnum
== gdbarch_pc_regnum (gdbarch
))
1772 reg
->how
= DWARF2_FRAME_REG_RA
;
1774 /* Mark the stack pointer as the call frame address. */
1775 else if (regnum
== gdbarch_sp_regnum (gdbarch
))
1776 reg
->how
= DWARF2_FRAME_REG_CFA
;
1778 /* The above was taken from the default init_reg in dwarf2-frame.c
1779 while the below is SH specific. */
1781 /* Caller save registers. */
1782 else if ((regnum
>= R0_REGNUM
&& regnum
<= R0_REGNUM
+7)
1783 || (regnum
>= FR0_REGNUM
&& regnum
<= FR0_REGNUM
+11)
1784 || (regnum
>= DR0_REGNUM
&& regnum
<= DR0_REGNUM
+5)
1785 || (regnum
>= FV0_REGNUM
&& regnum
<= FV0_REGNUM
+2)
1786 || (regnum
== MACH_REGNUM
)
1787 || (regnum
== MACL_REGNUM
)
1788 || (regnum
== FPUL_REGNUM
)
1789 || (regnum
== SR_REGNUM
))
1790 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
1792 /* Callee save registers. */
1793 else if ((regnum
>= R0_REGNUM
+8 && regnum
<= R0_REGNUM
+15)
1794 || (regnum
>= FR0_REGNUM
+12 && regnum
<= FR0_REGNUM
+15)
1795 || (regnum
>= DR0_REGNUM
+6 && regnum
<= DR0_REGNUM
+8)
1796 || (regnum
== FV0_REGNUM
+3))
1797 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
1799 /* Other registers. These are not in the ABI and may or may not
1800 mean anything in frames >0 so don't show them. */
1801 else if ((regnum
>= R0_BANK0_REGNUM
&& regnum
<= R0_BANK0_REGNUM
+15)
1802 || (regnum
== GBR_REGNUM
)
1803 || (regnum
== VBR_REGNUM
)
1804 || (regnum
== FPSCR_REGNUM
)
1805 || (regnum
== SSR_REGNUM
)
1806 || (regnum
== SPC_REGNUM
))
1807 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
1810 static struct sh_frame_cache
*
1811 sh_alloc_frame_cache (void)
1813 struct sh_frame_cache
*cache
;
1816 cache
= FRAME_OBSTACK_ZALLOC (struct sh_frame_cache
);
1820 cache
->saved_sp
= 0;
1821 cache
->sp_offset
= 0;
1824 /* Frameless until proven otherwise. */
1827 /* Saved registers. We initialize these to -1 since zero is a valid
1828 offset (that's where fp is supposed to be stored). */
1829 for (i
= 0; i
< SH_NUM_REGS
; i
++)
1831 cache
->saved_regs
[i
] = -1;
1837 static struct sh_frame_cache
*
1838 sh_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1840 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1841 struct sh_frame_cache
*cache
;
1842 CORE_ADDR current_pc
;
1848 cache
= sh_alloc_frame_cache ();
1849 *this_cache
= cache
;
1851 /* In principle, for normal frames, fp holds the frame pointer,
1852 which holds the base address for the current stack frame.
1853 However, for functions that don't need it, the frame pointer is
1854 optional. For these "frameless" functions the frame pointer is
1855 actually the frame pointer of the calling frame. */
1856 cache
->base
= get_frame_register_unsigned (this_frame
, FP_REGNUM
);
1857 if (cache
->base
== 0)
1860 cache
->pc
= get_frame_func (this_frame
);
1861 current_pc
= get_frame_pc (this_frame
);
1866 /* Check for the existence of the FPSCR register. If it exists,
1867 fetch its value for use in prologue analysis. Passing a zero
1868 value is the best choice for architecture variants upon which
1869 there's no FPSCR register. */
1870 if (gdbarch_register_reggroup_p (gdbarch
, FPSCR_REGNUM
, all_reggroup
))
1871 fpscr
= get_frame_register_unsigned (this_frame
, FPSCR_REGNUM
);
1875 sh_analyze_prologue (gdbarch
, cache
->pc
, current_pc
, cache
, fpscr
);
1878 if (!cache
->uses_fp
)
1880 /* We didn't find a valid frame, which means that CACHE->base
1881 currently holds the frame pointer for our calling frame. If
1882 we're at the start of a function, or somewhere half-way its
1883 prologue, the function's frame probably hasn't been fully
1884 setup yet. Try to reconstruct the base address for the stack
1885 frame by looking at the stack pointer. For truly "frameless"
1886 functions this might work too. */
1887 cache
->base
= get_frame_register_unsigned
1888 (this_frame
, gdbarch_sp_regnum (gdbarch
));
1891 /* Now that we have the base address for the stack frame we can
1892 calculate the value of sp in the calling frame. */
1893 cache
->saved_sp
= cache
->base
+ cache
->sp_offset
;
1895 /* Adjust all the saved registers such that they contain addresses
1896 instead of offsets. */
1897 for (i
= 0; i
< SH_NUM_REGS
; i
++)
1898 if (cache
->saved_regs
[i
] != -1)
1899 cache
->saved_regs
[i
] = cache
->saved_sp
- cache
->saved_regs
[i
] - 4;
1904 static struct value
*
1905 sh_frame_prev_register (struct frame_info
*this_frame
,
1906 void **this_cache
, int regnum
)
1908 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1909 struct sh_frame_cache
*cache
= sh_frame_cache (this_frame
, this_cache
);
1911 gdb_assert (regnum
>= 0);
1913 if (regnum
== gdbarch_sp_regnum (gdbarch
) && cache
->saved_sp
)
1914 return frame_unwind_got_constant (this_frame
, regnum
, cache
->saved_sp
);
1916 /* The PC of the previous frame is stored in the PR register of
1917 the current frame. Frob regnum so that we pull the value from
1918 the correct place. */
1919 if (regnum
== gdbarch_pc_regnum (gdbarch
))
1922 if (regnum
< SH_NUM_REGS
&& cache
->saved_regs
[regnum
] != -1)
1923 return frame_unwind_got_memory (this_frame
, regnum
,
1924 cache
->saved_regs
[regnum
]);
1926 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1930 sh_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1931 struct frame_id
*this_id
)
1933 struct sh_frame_cache
*cache
= sh_frame_cache (this_frame
, this_cache
);
1935 /* This marks the outermost frame. */
1936 if (cache
->base
== 0)
1939 *this_id
= frame_id_build (cache
->saved_sp
, cache
->pc
);
1942 static const struct frame_unwind sh_frame_unwind
= {
1944 default_frame_unwind_stop_reason
,
1946 sh_frame_prev_register
,
1948 default_frame_sniffer
1952 sh_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1954 return frame_unwind_register_unsigned (next_frame
,
1955 gdbarch_sp_regnum (gdbarch
));
1959 sh_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1961 return frame_unwind_register_unsigned (next_frame
,
1962 gdbarch_pc_regnum (gdbarch
));
1965 static struct frame_id
1966 sh_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1968 CORE_ADDR sp
= get_frame_register_unsigned (this_frame
,
1969 gdbarch_sp_regnum (gdbarch
));
1970 return frame_id_build (sp
, get_frame_pc (this_frame
));
1974 sh_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
1976 struct sh_frame_cache
*cache
= sh_frame_cache (this_frame
, this_cache
);
1981 static const struct frame_base sh_frame_base
= {
1983 sh_frame_base_address
,
1984 sh_frame_base_address
,
1985 sh_frame_base_address
1988 static struct sh_frame_cache
*
1989 sh_make_stub_cache (struct frame_info
*this_frame
)
1991 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1992 struct sh_frame_cache
*cache
;
1994 cache
= sh_alloc_frame_cache ();
1997 = get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
2003 sh_stub_this_id (struct frame_info
*this_frame
, void **this_cache
,
2004 struct frame_id
*this_id
)
2006 struct sh_frame_cache
*cache
;
2008 if (*this_cache
== NULL
)
2009 *this_cache
= sh_make_stub_cache (this_frame
);
2010 cache
= *this_cache
;
2012 *this_id
= frame_id_build (cache
->saved_sp
, get_frame_pc (this_frame
));
2016 sh_stub_unwind_sniffer (const struct frame_unwind
*self
,
2017 struct frame_info
*this_frame
,
2018 void **this_prologue_cache
)
2020 CORE_ADDR addr_in_block
;
2022 addr_in_block
= get_frame_address_in_block (this_frame
);
2023 if (in_plt_section (addr_in_block
, NULL
))
2029 static const struct frame_unwind sh_stub_unwind
=
2032 default_frame_unwind_stop_reason
,
2034 sh_frame_prev_register
,
2036 sh_stub_unwind_sniffer
2039 /* The epilogue is defined here as the area at the end of a function,
2040 either on the `ret' instruction itself or after an instruction which
2041 destroys the function's stack frame. */
2043 sh_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2045 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2046 CORE_ADDR func_addr
= 0, func_end
= 0;
2048 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
2051 /* The sh epilogue is max. 14 bytes long. Give another 14 bytes
2052 for a nop and some fixed data (e.g. big offsets) which are
2053 unfortunately also treated as part of the function (which
2054 means, they are below func_end. */
2055 CORE_ADDR addr
= func_end
- 28;
2056 if (addr
< func_addr
+ 4)
2057 addr
= func_addr
+ 4;
2061 /* First search forward until hitting an rts. */
2062 while (addr
< func_end
2063 && !IS_RTS (read_memory_unsigned_integer (addr
, 2, byte_order
)))
2065 if (addr
>= func_end
)
2068 /* At this point we should find a mov.l @r15+,r14 instruction,
2069 either before or after the rts. If not, then the function has
2070 probably no "normal" epilogue and we bail out here. */
2071 inst
= read_memory_unsigned_integer (addr
- 2, 2, byte_order
);
2072 if (IS_RESTORE_FP (read_memory_unsigned_integer (addr
- 2, 2,
2075 else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr
+ 2, 2,
2079 inst
= read_memory_unsigned_integer (addr
- 2, 2, byte_order
);
2081 /* Step over possible lds.l @r15+,macl. */
2082 if (IS_MACL_LDS (inst
))
2085 inst
= read_memory_unsigned_integer (addr
- 2, 2, byte_order
);
2088 /* Step over possible lds.l @r15+,pr. */
2092 inst
= read_memory_unsigned_integer (addr
- 2, 2, byte_order
);
2095 /* Step over possible mov r14,r15. */
2096 if (IS_MOV_FP_SP (inst
))
2099 inst
= read_memory_unsigned_integer (addr
- 2, 2, byte_order
);
2102 /* Now check for FP adjustments, using add #imm,r14 or add rX, r14
2104 while (addr
> func_addr
+ 4
2105 && (IS_ADD_REG_TO_FP (inst
) || IS_ADD_IMM_FP (inst
)))
2108 inst
= read_memory_unsigned_integer (addr
- 2, 2, byte_order
);
2111 /* On SH2a check if the previous instruction was perhaps a MOVI20.
2112 That's allowed for the epilogue. */
2113 if ((gdbarch_bfd_arch_info (gdbarch
)->mach
== bfd_mach_sh2a
2114 || gdbarch_bfd_arch_info (gdbarch
)->mach
== bfd_mach_sh2a_nofpu
)
2115 && addr
> func_addr
+ 6
2116 && IS_MOVI20 (read_memory_unsigned_integer (addr
- 4, 2,
2127 /* Supply register REGNUM from the buffer specified by REGS and LEN
2128 in the register set REGSET to register cache REGCACHE.
2129 REGTABLE specifies where each register can be found in REGS.
2130 If REGNUM is -1, do this for all registers in REGSET. */
2133 sh_corefile_supply_regset (const struct regset
*regset
,
2134 struct regcache
*regcache
,
2135 int regnum
, const void *regs
, size_t len
)
2137 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
2138 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2139 const struct sh_corefile_regmap
*regmap
= (regset
== &sh_corefile_gregset
2140 ? tdep
->core_gregmap
2141 : tdep
->core_fpregmap
);
2144 for (i
= 0; regmap
[i
].regnum
!= -1; i
++)
2146 if ((regnum
== -1 || regnum
== regmap
[i
].regnum
)
2147 && regmap
[i
].offset
+ 4 <= len
)
2148 regcache_raw_supply (regcache
, regmap
[i
].regnum
,
2149 (char *)regs
+ regmap
[i
].offset
);
2153 /* Collect register REGNUM in the register set REGSET from register cache
2154 REGCACHE into the buffer specified by REGS and LEN.
2155 REGTABLE specifies where each register can be found in REGS.
2156 If REGNUM is -1, do this for all registers in REGSET. */
2159 sh_corefile_collect_regset (const struct regset
*regset
,
2160 const struct regcache
*regcache
,
2161 int regnum
, void *regs
, size_t len
)
2163 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
2164 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2165 const struct sh_corefile_regmap
*regmap
= (regset
== &sh_corefile_gregset
2166 ? tdep
->core_gregmap
2167 : tdep
->core_fpregmap
);
2170 for (i
= 0; regmap
[i
].regnum
!= -1; i
++)
2172 if ((regnum
== -1 || regnum
== regmap
[i
].regnum
)
2173 && regmap
[i
].offset
+ 4 <= len
)
2174 regcache_raw_collect (regcache
, regmap
[i
].regnum
,
2175 (char *)regs
+ regmap
[i
].offset
);
2179 /* The following two regsets have the same contents, so it is tempting to
2180 unify them, but they are distiguished by their address, so don't. */
2182 struct regset sh_corefile_gregset
=
2185 sh_corefile_supply_regset
,
2186 sh_corefile_collect_regset
2189 static struct regset sh_corefile_fpregset
=
2192 sh_corefile_supply_regset
,
2193 sh_corefile_collect_regset
2196 static const struct regset
*
2197 sh_regset_from_core_section (struct gdbarch
*gdbarch
, const char *sect_name
,
2200 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2202 if (tdep
->core_gregmap
&& strcmp (sect_name
, ".reg") == 0)
2203 return &sh_corefile_gregset
;
2205 if (tdep
->core_fpregmap
&& strcmp (sect_name
, ".reg2") == 0)
2206 return &sh_corefile_fpregset
;
2211 /* This is the implementation of gdbarch method
2212 return_in_first_hidden_param_p. */
2215 sh_return_in_first_hidden_param_p (struct gdbarch
*gdbarch
,
2223 static struct gdbarch
*
2224 sh_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2226 struct gdbarch
*gdbarch
;
2227 struct gdbarch_tdep
*tdep
;
2229 /* SH5 is handled entirely in sh64-tdep.c. */
2230 if (info
.bfd_arch_info
->mach
== bfd_mach_sh5
)
2231 return sh64_gdbarch_init (info
, arches
);
2233 /* If there is already a candidate, use it. */
2234 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2236 return arches
->gdbarch
;
2238 /* None found, create a new architecture from the information
2240 tdep
= XZALLOC (struct gdbarch_tdep
);
2241 gdbarch
= gdbarch_alloc (&info
, tdep
);
2243 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
2244 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2245 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2246 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2247 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2248 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2249 set_gdbarch_long_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2250 set_gdbarch_ptr_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2252 set_gdbarch_num_regs (gdbarch
, SH_NUM_REGS
);
2253 set_gdbarch_sp_regnum (gdbarch
, 15);
2254 set_gdbarch_pc_regnum (gdbarch
, 16);
2255 set_gdbarch_fp0_regnum (gdbarch
, -1);
2256 set_gdbarch_num_pseudo_regs (gdbarch
, 0);
2258 set_gdbarch_register_type (gdbarch
, sh_default_register_type
);
2259 set_gdbarch_register_reggroup_p (gdbarch
, sh_register_reggroup_p
);
2261 set_gdbarch_breakpoint_from_pc (gdbarch
, sh_breakpoint_from_pc
);
2263 set_gdbarch_print_insn (gdbarch
, print_insn_sh
);
2264 set_gdbarch_register_sim_regno (gdbarch
, legacy_register_sim_regno
);
2266 set_gdbarch_return_value (gdbarch
, sh_return_value_nofpu
);
2268 set_gdbarch_skip_prologue (gdbarch
, sh_skip_prologue
);
2269 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2271 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_nofpu
);
2272 set_gdbarch_return_in_first_hidden_param_p (gdbarch
,
2273 sh_return_in_first_hidden_param_p
);
2275 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
2277 set_gdbarch_frame_align (gdbarch
, sh_frame_align
);
2278 set_gdbarch_unwind_sp (gdbarch
, sh_unwind_sp
);
2279 set_gdbarch_unwind_pc (gdbarch
, sh_unwind_pc
);
2280 set_gdbarch_dummy_id (gdbarch
, sh_dummy_id
);
2281 frame_base_set_default (gdbarch
, &sh_frame_base
);
2283 set_gdbarch_in_function_epilogue_p (gdbarch
, sh_in_function_epilogue_p
);
2285 dwarf2_frame_set_init_reg (gdbarch
, sh_dwarf2_frame_init_reg
);
2287 set_gdbarch_regset_from_core_section (gdbarch
, sh_regset_from_core_section
);
2289 switch (info
.bfd_arch_info
->mach
)
2292 set_gdbarch_register_name (gdbarch
, sh_sh_register_name
);
2296 set_gdbarch_register_name (gdbarch
, sh_sh_register_name
);
2300 /* doubles on sh2e and sh3e are actually 4 byte. */
2301 set_gdbarch_double_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2303 set_gdbarch_register_name (gdbarch
, sh_sh2e_register_name
);
2304 set_gdbarch_register_type (gdbarch
, sh_sh3e_register_type
);
2305 set_gdbarch_fp0_regnum (gdbarch
, 25);
2306 set_gdbarch_return_value (gdbarch
, sh_return_value_fpu
);
2307 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_fpu
);
2311 set_gdbarch_register_name (gdbarch
, sh_sh2a_register_name
);
2312 set_gdbarch_register_type (gdbarch
, sh_sh2a_register_type
);
2313 set_gdbarch_register_sim_regno (gdbarch
, sh_sh2a_register_sim_regno
);
2315 set_gdbarch_fp0_regnum (gdbarch
, 25);
2316 set_gdbarch_num_pseudo_regs (gdbarch
, 9);
2317 set_gdbarch_pseudo_register_read (gdbarch
, sh_pseudo_register_read
);
2318 set_gdbarch_pseudo_register_write (gdbarch
, sh_pseudo_register_write
);
2319 set_gdbarch_return_value (gdbarch
, sh_return_value_fpu
);
2320 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_fpu
);
2323 case bfd_mach_sh2a_nofpu
:
2324 set_gdbarch_register_name (gdbarch
, sh_sh2a_nofpu_register_name
);
2325 set_gdbarch_register_sim_regno (gdbarch
, sh_sh2a_register_sim_regno
);
2327 set_gdbarch_num_pseudo_regs (gdbarch
, 1);
2328 set_gdbarch_pseudo_register_read (gdbarch
, sh_pseudo_register_read
);
2329 set_gdbarch_pseudo_register_write (gdbarch
, sh_pseudo_register_write
);
2332 case bfd_mach_sh_dsp
:
2333 set_gdbarch_register_name (gdbarch
, sh_sh_dsp_register_name
);
2334 set_gdbarch_register_sim_regno (gdbarch
, sh_dsp_register_sim_regno
);
2338 case bfd_mach_sh3_nommu
:
2339 case bfd_mach_sh2a_nofpu_or_sh3_nommu
:
2340 set_gdbarch_register_name (gdbarch
, sh_sh3_register_name
);
2344 case bfd_mach_sh2a_or_sh3e
:
2345 /* doubles on sh2e and sh3e are actually 4 byte. */
2346 set_gdbarch_double_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2348 set_gdbarch_register_name (gdbarch
, sh_sh3e_register_name
);
2349 set_gdbarch_register_type (gdbarch
, sh_sh3e_register_type
);
2350 set_gdbarch_fp0_regnum (gdbarch
, 25);
2351 set_gdbarch_return_value (gdbarch
, sh_return_value_fpu
);
2352 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_fpu
);
2355 case bfd_mach_sh3_dsp
:
2356 set_gdbarch_register_name (gdbarch
, sh_sh3_dsp_register_name
);
2357 set_gdbarch_register_sim_regno (gdbarch
, sh_dsp_register_sim_regno
);
2362 case bfd_mach_sh2a_or_sh4
:
2363 set_gdbarch_register_name (gdbarch
, sh_sh4_register_name
);
2364 set_gdbarch_register_type (gdbarch
, sh_sh4_register_type
);
2365 set_gdbarch_fp0_regnum (gdbarch
, 25);
2366 set_gdbarch_num_pseudo_regs (gdbarch
, 13);
2367 set_gdbarch_pseudo_register_read (gdbarch
, sh_pseudo_register_read
);
2368 set_gdbarch_pseudo_register_write (gdbarch
, sh_pseudo_register_write
);
2369 set_gdbarch_return_value (gdbarch
, sh_return_value_fpu
);
2370 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_fpu
);
2373 case bfd_mach_sh4_nofpu
:
2374 case bfd_mach_sh4a_nofpu
:
2375 case bfd_mach_sh4_nommu_nofpu
:
2376 case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu
:
2377 set_gdbarch_register_name (gdbarch
, sh_sh4_nofpu_register_name
);
2380 case bfd_mach_sh4al_dsp
:
2381 set_gdbarch_register_name (gdbarch
, sh_sh4al_dsp_register_name
);
2382 set_gdbarch_register_sim_regno (gdbarch
, sh_dsp_register_sim_regno
);
2386 set_gdbarch_register_name (gdbarch
, sh_sh_register_name
);
2390 /* Hook in ABI-specific overrides, if they have been registered. */
2391 gdbarch_init_osabi (info
, gdbarch
);
2393 dwarf2_append_unwinders (gdbarch
);
2394 frame_unwind_append_unwinder (gdbarch
, &sh_stub_unwind
);
2395 frame_unwind_append_unwinder (gdbarch
, &sh_frame_unwind
);
2401 show_sh_command (char *args
, int from_tty
)
2403 help_list (showshcmdlist
, "show sh ", all_commands
, gdb_stdout
);
2407 set_sh_command (char *args
, int from_tty
)
2410 ("\"set sh\" must be followed by an appropriate subcommand.\n");
2411 help_list (setshcmdlist
, "set sh ", all_commands
, gdb_stdout
);
2414 extern initialize_file_ftype _initialize_sh_tdep
; /* -Wmissing-prototypes */
2417 _initialize_sh_tdep (void)
2419 struct cmd_list_element
*c
;
2421 gdbarch_register (bfd_arch_sh
, sh_gdbarch_init
, NULL
);
2423 /* We can't use an alias here because 'info registers' has not yet been
2425 c
= add_com ("regs", class_vars
, all_registers_info
,
2426 _("Print all registers"));
2427 deprecate_cmd (c
, "info all-registers");
2429 add_prefix_cmd ("sh", no_class
, set_sh_command
, "SH specific commands.",
2430 &setshcmdlist
, "set sh ", 0, &setlist
);
2431 add_prefix_cmd ("sh", no_class
, show_sh_command
, "SH specific commands.",
2432 &showshcmdlist
, "show sh ", 0, &showlist
);
2434 add_setshow_enum_cmd ("calling-convention", class_vars
, sh_cc_enum
,
2435 &sh_active_calling_convention
,
2436 _("Set calling convention used when calling target "
2437 "functions from GDB."),
2438 _("Show calling convention used when calling target "
2439 "functions from GDB."),
2440 _("gcc - Use GCC calling convention (default).\n"
2441 "renesas - Enforce Renesas calling convention."),
2443 &setshcmdlist
, &showshcmdlist
);