1 /* Target-dependent code for Renesas Super-H, for GDB.
3 Copyright (C) 1993-2014 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20 /* Contributed by Steve Chamberlain
25 #include "frame-base.h"
26 #include "frame-unwind.h"
27 #include "dwarf2-frame.h"
36 #include "arch-utils.h"
37 #include "floatformat.h"
41 #include "reggroups.h"
46 #include "sh64-tdep.h"
49 #include "solib-svr4.h"
54 /* registers numbers shared with the simulator. */
55 #include "gdb/sim-sh.h"
57 /* List of "set sh ..." and "show sh ..." commands. */
58 static struct cmd_list_element
*setshcmdlist
= NULL
;
59 static struct cmd_list_element
*showshcmdlist
= NULL
;
61 static const char sh_cc_gcc
[] = "gcc";
62 static const char sh_cc_renesas
[] = "renesas";
63 static const char *const sh_cc_enum
[] = {
69 static const char *sh_active_calling_convention
= sh_cc_gcc
;
71 #define SH_NUM_REGS 67
80 /* Flag showing that a frame has been created in the prologue code. */
83 /* Saved registers. */
84 CORE_ADDR saved_regs
[SH_NUM_REGS
];
89 sh_is_renesas_calling_convention (struct type
*func_type
)
95 func_type
= check_typedef (func_type
);
97 if (TYPE_CODE (func_type
) == TYPE_CODE_PTR
)
98 func_type
= check_typedef (TYPE_TARGET_TYPE (func_type
));
100 if (TYPE_CODE (func_type
) == TYPE_CODE_FUNC
101 && TYPE_CALLING_CONVENTION (func_type
) == DW_CC_GNU_renesas_sh
)
105 if (sh_active_calling_convention
== sh_cc_renesas
)
112 sh_sh_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
114 static char *register_names
[] = {
115 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
116 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
117 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
119 "", "", "", "", "", "", "", "",
120 "", "", "", "", "", "", "", "",
122 "", "", "", "", "", "", "", "",
123 "", "", "", "", "", "", "", "",
124 "", "", "", "", "", "", "", "",
128 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
130 return register_names
[reg_nr
];
134 sh_sh3_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
136 static char *register_names
[] = {
137 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
138 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
139 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
141 "", "", "", "", "", "", "", "",
142 "", "", "", "", "", "", "", "",
144 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
145 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
146 "", "", "", "", "", "", "", "",
150 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
152 return register_names
[reg_nr
];
156 sh_sh3e_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
158 static char *register_names
[] = {
159 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
160 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
161 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
163 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
164 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
166 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
167 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
168 "", "", "", "", "", "", "", "",
172 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
174 return register_names
[reg_nr
];
178 sh_sh2e_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
180 static char *register_names
[] = {
181 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
182 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
183 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
185 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
186 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
188 "", "", "", "", "", "", "", "",
189 "", "", "", "", "", "", "", "",
190 "", "", "", "", "", "", "", "",
194 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
196 return register_names
[reg_nr
];
200 sh_sh2a_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
202 static char *register_names
[] = {
203 /* general registers 0-15 */
204 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
205 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
207 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
210 /* floating point registers 25 - 40 */
211 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
212 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
215 /* 43 - 62. Banked registers. The bank number used is determined by
216 the bank register (63). */
217 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
218 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
219 "machb", "ivnb", "prb", "gbrb", "maclb",
220 /* 63: register bank number, not a real register but used to
221 communicate the register bank currently get/set. This register
222 is hidden to the user, who manipulates it using the pseudo
223 register called "bank" (67). See below. */
226 "ibcr", "ibnr", "tbr",
227 /* 67: register bank number, the user visible pseudo register. */
229 /* double precision (pseudo) 68 - 75 */
230 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
234 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
236 return register_names
[reg_nr
];
240 sh_sh2a_nofpu_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
242 static char *register_names
[] = {
243 /* general registers 0-15 */
244 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
245 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
247 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
250 /* floating point registers 25 - 40 */
251 "", "", "", "", "", "", "", "",
252 "", "", "", "", "", "", "", "",
255 /* 43 - 62. Banked registers. The bank number used is determined by
256 the bank register (63). */
257 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
258 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
259 "machb", "ivnb", "prb", "gbrb", "maclb",
260 /* 63: register bank number, not a real register but used to
261 communicate the register bank currently get/set. This register
262 is hidden to the user, who manipulates it using the pseudo
263 register called "bank" (67). See below. */
266 "ibcr", "ibnr", "tbr",
267 /* 67: register bank number, the user visible pseudo register. */
269 /* double precision (pseudo) 68 - 75 */
270 "", "", "", "", "", "", "", "",
274 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
276 return register_names
[reg_nr
];
280 sh_sh_dsp_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
282 static char *register_names
[] = {
283 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
284 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
285 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
287 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
288 "y0", "y1", "", "", "", "", "", "mod",
290 "rs", "re", "", "", "", "", "", "",
291 "", "", "", "", "", "", "", "",
292 "", "", "", "", "", "", "", "",
296 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
298 return register_names
[reg_nr
];
302 sh_sh3_dsp_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
304 static char *register_names
[] = {
305 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
306 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
307 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
309 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
310 "y0", "y1", "", "", "", "", "", "mod",
312 "rs", "re", "", "", "", "", "", "",
313 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
314 "", "", "", "", "", "", "", "",
315 "", "", "", "", "", "", "", "",
319 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
321 return register_names
[reg_nr
];
325 sh_sh4_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
327 static char *register_names
[] = {
328 /* general registers 0-15 */
329 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
330 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
332 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
335 /* floating point registers 25 - 40 */
336 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
337 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
341 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
343 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
345 "", "", "", "", "", "", "", "",
346 /* pseudo bank register. */
348 /* double precision (pseudo) 68 - 75 */
349 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
350 /* vectors (pseudo) 76 - 79 */
351 "fv0", "fv4", "fv8", "fv12",
352 /* FIXME: missing XF */
353 /* FIXME: missing XD */
357 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
359 return register_names
[reg_nr
];
363 sh_sh4_nofpu_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
365 static char *register_names
[] = {
366 /* general registers 0-15 */
367 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
368 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
370 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
373 /* floating point registers 25 - 40 -- not for nofpu target */
374 "", "", "", "", "", "", "", "",
375 "", "", "", "", "", "", "", "",
379 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
381 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
383 "", "", "", "", "", "", "", "",
384 /* pseudo bank register. */
386 /* double precision (pseudo) 68 - 75 -- not for nofpu target */
387 "", "", "", "", "", "", "", "",
388 /* vectors (pseudo) 76 - 79 -- not for nofpu target */
393 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
395 return register_names
[reg_nr
];
399 sh_sh4al_dsp_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
401 static char *register_names
[] = {
402 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
403 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
404 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
406 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
407 "y0", "y1", "", "", "", "", "", "mod",
409 "rs", "re", "", "", "", "", "", "",
410 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
411 "", "", "", "", "", "", "", "",
412 "", "", "", "", "", "", "", "",
416 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
418 return register_names
[reg_nr
];
421 static const unsigned char *
422 sh_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
, int *lenptr
)
424 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes. */
425 static unsigned char breakpoint
[] = { 0xc3, 0xc3 };
427 /* For remote stub targets, trapa #20 is used. */
428 if (strcmp (target_shortname
, "remote") == 0)
430 static unsigned char big_remote_breakpoint
[] = { 0xc3, 0x20 };
431 static unsigned char little_remote_breakpoint
[] = { 0x20, 0xc3 };
433 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
435 *lenptr
= sizeof (big_remote_breakpoint
);
436 return big_remote_breakpoint
;
440 *lenptr
= sizeof (little_remote_breakpoint
);
441 return little_remote_breakpoint
;
445 *lenptr
= sizeof (breakpoint
);
449 /* Prologue looks like
453 sub <room_for_loca_vars>,r15
456 Actually it can be more complicated than this but that's it, basically. */
458 #define GET_SOURCE_REG(x) (((x) >> 4) & 0xf)
459 #define GET_TARGET_REG(x) (((x) >> 8) & 0xf)
461 /* JSR @Rm 0100mmmm00001011 */
462 #define IS_JSR(x) (((x) & 0xf0ff) == 0x400b)
464 /* STS.L PR,@-r15 0100111100100010
465 r15-4-->r15, PR-->(r15) */
466 #define IS_STS(x) ((x) == 0x4f22)
468 /* STS.L MACL,@-r15 0100111100010010
469 r15-4-->r15, MACL-->(r15) */
470 #define IS_MACL_STS(x) ((x) == 0x4f12)
472 /* MOV.L Rm,@-r15 00101111mmmm0110
473 r15-4-->r15, Rm-->(R15) */
474 #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
476 /* MOV r15,r14 0110111011110011
478 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
480 /* ADD #imm,r15 01111111iiiiiiii
482 #define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00)
484 #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
485 #define IS_SHLL_R3(x) ((x) == 0x4300)
487 /* ADD r3,r15 0011111100111100
489 #define IS_ADD_R3SP(x) ((x) == 0x3f3c)
491 /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
492 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
493 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
494 /* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to
495 make this entirely clear. */
496 /* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */
497 #define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b)
499 /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */
500 #define IS_MOV_ARG_TO_REG(x) \
501 (((x) & 0xf00f) == 0x6003 && \
502 ((x) & 0x00f0) >= 0x0040 && \
503 ((x) & 0x00f0) <= 0x0070)
504 /* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */
505 #define IS_MOV_ARG_TO_IND_R14(x) \
506 (((x) & 0xff0f) == 0x2e02 && \
507 ((x) & 0x00f0) >= 0x0040 && \
508 ((x) & 0x00f0) <= 0x0070)
509 /* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */
510 #define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \
511 (((x) & 0xff00) == 0x1e00 && \
512 ((x) & 0x00f0) >= 0x0040 && \
513 ((x) & 0x00f0) <= 0x0070)
515 /* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */
516 #define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000)
517 /* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */
518 #define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000)
519 /* MOVI20 #imm20,Rn 0000nnnniiii0000 */
520 #define IS_MOVI20(x) (((x) & 0xf00f) == 0x0000)
521 /* SUB Rn,R15 00111111nnnn1000 */
522 #define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08)
524 #define FPSCR_SZ (1 << 20)
526 /* The following instructions are used for epilogue testing. */
527 #define IS_RESTORE_FP(x) ((x) == 0x6ef6)
528 #define IS_RTS(x) ((x) == 0x000b)
529 #define IS_LDS(x) ((x) == 0x4f26)
530 #define IS_MACL_LDS(x) ((x) == 0x4f16)
531 #define IS_MOV_FP_SP(x) ((x) == 0x6fe3)
532 #define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c)
533 #define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00)
536 sh_analyze_prologue (struct gdbarch
*gdbarch
,
537 CORE_ADDR pc
, CORE_ADDR limit_pc
,
538 struct sh_frame_cache
*cache
, ULONGEST fpscr
)
540 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
545 int reg
, sav_reg
= -1;
548 for (; pc
< limit_pc
; pc
+= 2)
550 inst
= read_memory_unsigned_integer (pc
, 2, byte_order
);
551 /* See where the registers will be saved to. */
554 cache
->saved_regs
[GET_SOURCE_REG (inst
)] = cache
->sp_offset
;
555 cache
->sp_offset
+= 4;
557 else if (IS_STS (inst
))
559 cache
->saved_regs
[PR_REGNUM
] = cache
->sp_offset
;
560 cache
->sp_offset
+= 4;
562 else if (IS_MACL_STS (inst
))
564 cache
->saved_regs
[MACL_REGNUM
] = cache
->sp_offset
;
565 cache
->sp_offset
+= 4;
567 else if (IS_MOV_R3 (inst
))
569 r3_val
= ((inst
& 0xff) ^ 0x80) - 0x80;
571 else if (IS_SHLL_R3 (inst
))
575 else if (IS_ADD_R3SP (inst
))
577 cache
->sp_offset
+= -r3_val
;
579 else if (IS_ADD_IMM_SP (inst
))
581 offset
= ((inst
& 0xff) ^ 0x80) - 0x80;
582 cache
->sp_offset
-= offset
;
584 else if (IS_MOVW_PCREL_TO_REG (inst
))
588 reg
= GET_TARGET_REG (inst
);
592 offset
= (inst
& 0xff) << 1;
594 read_memory_integer ((pc
+ 4) + offset
, 2, byte_order
);
598 else if (IS_MOVL_PCREL_TO_REG (inst
))
602 reg
= GET_TARGET_REG (inst
);
606 offset
= (inst
& 0xff) << 2;
608 read_memory_integer (((pc
& 0xfffffffc) + 4) + offset
,
613 else if (IS_MOVI20 (inst
)
614 && (pc
+ 2 < limit_pc
))
618 reg
= GET_TARGET_REG (inst
);
622 sav_offset
= GET_SOURCE_REG (inst
) << 16;
623 /* MOVI20 is a 32 bit instruction! */
626 |= read_memory_unsigned_integer (pc
, 2, byte_order
);
627 /* Now sav_offset contains an unsigned 20 bit value.
628 It must still get sign extended. */
629 if (sav_offset
& 0x00080000)
630 sav_offset
|= 0xfff00000;
634 else if (IS_SUB_REG_FROM_SP (inst
))
636 reg
= GET_SOURCE_REG (inst
);
637 if (sav_reg
> 0 && reg
== sav_reg
)
641 cache
->sp_offset
+= sav_offset
;
643 else if (IS_FPUSH (inst
))
645 if (fpscr
& FPSCR_SZ
)
647 cache
->sp_offset
+= 8;
651 cache
->sp_offset
+= 4;
654 else if (IS_MOV_SP_FP (inst
))
657 /* Don't go any further than six more instructions. */
658 limit_pc
= min (limit_pc
, pc
+ (2 * 6));
661 /* At this point, only allow argument register moves to other
662 registers or argument register moves to @(X,fp) which are
663 moving the register arguments onto the stack area allocated
664 by a former add somenumber to SP call. Don't allow moving
665 to an fp indirect address above fp + cache->sp_offset. */
666 for (; pc
< limit_pc
; pc
+= 2)
668 inst
= read_memory_integer (pc
, 2, byte_order
);
669 if (IS_MOV_ARG_TO_IND_R14 (inst
))
671 reg
= GET_SOURCE_REG (inst
);
672 if (cache
->sp_offset
> 0)
673 cache
->saved_regs
[reg
] = cache
->sp_offset
;
675 else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst
))
677 reg
= GET_SOURCE_REG (inst
);
678 offset
= (inst
& 0xf) * 4;
679 if (cache
->sp_offset
> offset
)
680 cache
->saved_regs
[reg
] = cache
->sp_offset
- offset
;
682 else if (IS_MOV_ARG_TO_REG (inst
))
689 else if (IS_JSR (inst
))
691 /* We have found a jsr that has been scheduled into the prologue.
692 If we continue the scan and return a pc someplace after this,
693 then setting a breakpoint on this function will cause it to
694 appear to be called after the function it is calling via the
695 jsr, which will be very confusing. Most likely the next
696 instruction is going to be IS_MOV_SP_FP in the delay slot. If
697 so, note that before returning the current pc. */
698 if (pc
+ 2 < limit_pc
)
700 inst
= read_memory_integer (pc
+ 2, 2, byte_order
);
701 if (IS_MOV_SP_FP (inst
))
706 #if 0 /* This used to just stop when it found an instruction
707 that was not considered part of the prologue. Now,
708 we just keep going looking for likely
718 /* Skip any prologue before the guts of a function. */
720 sh_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
722 CORE_ADDR post_prologue_pc
, func_addr
, func_end_addr
, limit_pc
;
723 struct sh_frame_cache cache
;
725 /* See if we can determine the end of the prologue via the symbol table.
726 If so, then return either PC, or the PC after the prologue, whichever
728 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end_addr
))
730 post_prologue_pc
= skip_prologue_using_sal (gdbarch
, func_addr
);
731 if (post_prologue_pc
!= 0)
732 return max (pc
, post_prologue_pc
);
735 /* Can't determine prologue from the symbol table, need to examine
738 /* Find an upper limit on the function prologue using the debug
739 information. If the debug information could not be used to provide
740 that bound, then use an arbitrary large number as the upper bound. */
741 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
743 /* Don't go any further than 28 instructions. */
744 limit_pc
= pc
+ (2 * 28);
746 /* Do not allow limit_pc to be past the function end, if we know
747 where that end is... */
748 if (func_end_addr
!= 0)
749 limit_pc
= min (limit_pc
, func_end_addr
);
751 cache
.sp_offset
= -4;
752 post_prologue_pc
= sh_analyze_prologue (gdbarch
, pc
, limit_pc
, &cache
, 0);
754 pc
= post_prologue_pc
;
761 Aggregate types not bigger than 8 bytes that have the same size and
762 alignment as one of the integer scalar types are returned in the
763 same registers as the integer type they match.
765 For example, a 2-byte aligned structure with size 2 bytes has the
766 same size and alignment as a short int, and will be returned in R0.
767 A 4-byte aligned structure with size 8 bytes has the same size and
768 alignment as a long long int, and will be returned in R0 and R1.
770 When an aggregate type is returned in R0 and R1, R0 contains the
771 first four bytes of the aggregate, and R1 contains the
772 remainder. If the size of the aggregate type is not a multiple of 4
773 bytes, the aggregate is tail-padded up to a multiple of 4
774 bytes. The value of the padding is undefined. For little-endian
775 targets the padding will appear at the most significant end of the
776 last element, for big-endian targets the padding appears at the
777 least significant end of the last element.
779 All other aggregate types are returned by address. The caller
780 function passes the address of an area large enough to hold the
781 aggregate value in R2. The called function stores the result in
784 To reiterate, structs smaller than 8 bytes could also be returned
785 in memory, if they don't pass the "same size and alignment as an
790 struct s { char c[3]; } wibble;
791 struct s foo(void) { return wibble; }
793 the return value from foo() will be in memory, not
794 in R0, because there is no 3-byte integer type.
798 struct s { char c[2]; } wibble;
799 struct s foo(void) { return wibble; }
801 because a struct containing two chars has alignment 1, that matches
802 type char, but size 2, that matches type short. There's no integer
803 type that has alignment 1 and size 2, so the struct is returned in
807 sh_use_struct_convention (int renesas_abi
, struct type
*type
)
809 int len
= TYPE_LENGTH (type
);
810 int nelem
= TYPE_NFIELDS (type
);
812 /* The Renesas ABI returns aggregate types always on stack. */
813 if (renesas_abi
&& (TYPE_CODE (type
) == TYPE_CODE_STRUCT
814 || TYPE_CODE (type
) == TYPE_CODE_UNION
))
817 /* Non-power of 2 length types and types bigger than 8 bytes (which don't
818 fit in two registers anyway) use struct convention. */
819 if (len
!= 1 && len
!= 2 && len
!= 4 && len
!= 8)
822 /* Scalar types and aggregate types with exactly one field are aligned
823 by definition. They are returned in registers. */
827 /* If the first field in the aggregate has the same length as the entire
828 aggregate type, the type is returned in registers. */
829 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, 0)) == len
)
832 /* If the size of the aggregate is 8 bytes and the first field is
833 of size 4 bytes its alignment is equal to long long's alignment,
834 so it's returned in registers. */
835 if (len
== 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type
, 0)) == 4)
838 /* Otherwise use struct convention. */
843 sh_use_struct_convention_nofpu (int renesas_abi
, struct type
*type
)
845 /* The Renesas ABI returns long longs/doubles etc. always on stack. */
846 if (renesas_abi
&& TYPE_NFIELDS (type
) == 0 && TYPE_LENGTH (type
) >= 8)
848 return sh_use_struct_convention (renesas_abi
, type
);
852 sh_frame_align (struct gdbarch
*ignore
, CORE_ADDR sp
)
857 /* Function: push_dummy_call (formerly push_arguments)
858 Setup the function arguments for calling a function in the inferior.
860 On the Renesas SH architecture, there are four registers (R4 to R7)
861 which are dedicated for passing function arguments. Up to the first
862 four arguments (depending on size) may go into these registers.
863 The rest go on the stack.
865 MVS: Except on SH variants that have floating point registers.
866 In that case, float and double arguments are passed in the same
867 manner, but using FP registers instead of GP registers.
869 Arguments that are smaller than 4 bytes will still take up a whole
870 register or a whole 32-bit word on the stack, and will be
871 right-justified in the register or the stack word. This includes
872 chars, shorts, and small aggregate types.
874 Arguments that are larger than 4 bytes may be split between two or
875 more registers. If there are not enough registers free, an argument
876 may be passed partly in a register (or registers), and partly on the
877 stack. This includes doubles, long longs, and larger aggregates.
878 As far as I know, there is no upper limit to the size of aggregates
879 that will be passed in this way; in other words, the convention of
880 passing a pointer to a large aggregate instead of a copy is not used.
882 MVS: The above appears to be true for the SH variants that do not
883 have an FPU, however those that have an FPU appear to copy the
884 aggregate argument onto the stack (and not place it in registers)
885 if it is larger than 16 bytes (four GP registers).
887 An exceptional case exists for struct arguments (and possibly other
888 aggregates such as arrays) if the size is larger than 4 bytes but
889 not a multiple of 4 bytes. In this case the argument is never split
890 between the registers and the stack, but instead is copied in its
891 entirety onto the stack, AND also copied into as many registers as
892 there is room for. In other words, space in registers permitting,
893 two copies of the same argument are passed in. As far as I can tell,
894 only the one on the stack is used, although that may be a function
895 of the level of compiler optimization. I suspect this is a compiler
896 bug. Arguments of these odd sizes are left-justified within the
897 word (as opposed to arguments smaller than 4 bytes, which are
900 If the function is to return an aggregate type such as a struct, it
901 is either returned in the normal return value register R0 (if its
902 size is no greater than one byte), or else the caller must allocate
903 space into which the callee will copy the return value (if the size
904 is greater than one byte). In this case, a pointer to the return
905 value location is passed into the callee in register R2, which does
906 not displace any of the other arguments passed in via registers R4
909 /* Helper function to justify value in register according to endianess. */
910 static const gdb_byte
*
911 sh_justify_value_in_reg (struct gdbarch
*gdbarch
, struct value
*val
, int len
)
913 static gdb_byte valbuf
[4];
915 memset (valbuf
, 0, sizeof (valbuf
));
918 /* value gets right-justified in the register or stack word. */
919 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
920 memcpy (valbuf
+ (4 - len
), value_contents (val
), len
);
922 memcpy (valbuf
, value_contents (val
), len
);
925 return value_contents (val
);
928 /* Helper function to eval number of bytes to allocate on stack. */
930 sh_stack_allocsize (int nargs
, struct value
**args
)
934 stack_alloc
+= ((TYPE_LENGTH (value_type (args
[nargs
])) + 3) & ~3);
938 /* Helper functions for getting the float arguments right. Registers usage
939 depends on the ABI and the endianess. The comments should enlighten how
940 it's intended to work. */
942 /* This array stores which of the float arg registers are already in use. */
943 static int flt_argreg_array
[FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
+ 1];
945 /* This function just resets the above array to "no reg used so far". */
947 sh_init_flt_argreg (void)
949 memset (flt_argreg_array
, 0, sizeof flt_argreg_array
);
952 /* This function returns the next register to use for float arg passing.
953 It returns either a valid value between FLOAT_ARG0_REGNUM and
954 FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns
955 FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available.
957 Note that register number 0 in flt_argreg_array corresponds with the
958 real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is
959 29) the parity of the register number is preserved, which is important
960 for the double register passing test (see the "argreg & 1" test below). */
962 sh_next_flt_argreg (struct gdbarch
*gdbarch
, int len
, struct type
*func_type
)
966 /* First search for the next free register. */
967 for (argreg
= 0; argreg
<= FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
;
969 if (!flt_argreg_array
[argreg
])
972 /* No register left? */
973 if (argreg
> FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
)
974 return FLOAT_ARGLAST_REGNUM
+ 1;
978 /* Doubles are always starting in a even register number. */
981 /* In gcc ABI, the skipped register is lost for further argument
982 passing now. Not so in Renesas ABI. */
983 if (!sh_is_renesas_calling_convention (func_type
))
984 flt_argreg_array
[argreg
] = 1;
988 /* No register left? */
989 if (argreg
> FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
)
990 return FLOAT_ARGLAST_REGNUM
+ 1;
992 /* Also mark the next register as used. */
993 flt_argreg_array
[argreg
+ 1] = 1;
995 else if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
996 && !sh_is_renesas_calling_convention (func_type
))
998 /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */
999 if (!flt_argreg_array
[argreg
+ 1])
1002 flt_argreg_array
[argreg
] = 1;
1003 return FLOAT_ARG0_REGNUM
+ argreg
;
1006 /* Helper function which figures out, if a type is treated like a float type.
1008 The FPU ABIs have a special way how to treat types as float types.
1009 Structures with exactly one member, which is of type float or double, are
1010 treated exactly as the base types float or double:
1020 are handled the same way as just
1026 As a result, arguments of these struct types are pushed into floating point
1027 registers exactly as floats or doubles, using the same decision algorithm.
1029 The same is valid if these types are used as function return types. The
1030 above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1
1031 or even using struct convention as it is for other structs. */
1034 sh_treat_as_flt_p (struct type
*type
)
1036 /* Ordinary float types are obviously treated as float. */
1037 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1039 /* Otherwise non-struct types are not treated as float. */
1040 if (TYPE_CODE (type
) != TYPE_CODE_STRUCT
)
1042 /* Otherwise structs with more than one memeber are not treated as float. */
1043 if (TYPE_NFIELDS (type
) != 1)
1045 /* Otherwise if the type of that member is float, the whole type is
1046 treated as float. */
1047 if (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0)) == TYPE_CODE_FLT
)
1049 /* Otherwise it's not treated as float. */
1054 sh_push_dummy_call_fpu (struct gdbarch
*gdbarch
,
1055 struct value
*function
,
1056 struct regcache
*regcache
,
1057 CORE_ADDR bp_addr
, int nargs
,
1058 struct value
**args
,
1059 CORE_ADDR sp
, int struct_return
,
1060 CORE_ADDR struct_addr
)
1062 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1063 int stack_offset
= 0;
1064 int argreg
= ARG0_REGNUM
;
1067 struct type
*func_type
= value_type (function
);
1070 const gdb_byte
*val
;
1071 int len
, reg_size
= 0;
1072 int pass_on_stack
= 0;
1074 int last_reg_arg
= INT_MAX
;
1076 /* The Renesas ABI expects all varargs arguments, plus the last
1077 non-vararg argument to be on the stack, no matter how many
1078 registers have been used so far. */
1079 if (sh_is_renesas_calling_convention (func_type
)
1080 && TYPE_VARARGS (func_type
))
1081 last_reg_arg
= TYPE_NFIELDS (func_type
) - 2;
1083 /* First force sp to a 4-byte alignment. */
1084 sp
= sh_frame_align (gdbarch
, sp
);
1086 /* Make room on stack for args. */
1087 sp
-= sh_stack_allocsize (nargs
, args
);
1089 /* Initialize float argument mechanism. */
1090 sh_init_flt_argreg ();
1092 /* Now load as many as possible of the first arguments into
1093 registers, and push the rest onto the stack. There are 16 bytes
1094 in four registers available. Loop thru args from first to last. */
1095 for (argnum
= 0; argnum
< nargs
; argnum
++)
1097 type
= value_type (args
[argnum
]);
1098 len
= TYPE_LENGTH (type
);
1099 val
= sh_justify_value_in_reg (gdbarch
, args
[argnum
], len
);
1101 /* Some decisions have to be made how various types are handled.
1102 This also differs in different ABIs. */
1105 /* Find out the next register to use for a floating point value. */
1106 treat_as_flt
= sh_treat_as_flt_p (type
);
1108 flt_argreg
= sh_next_flt_argreg (gdbarch
, len
, func_type
);
1109 /* In Renesas ABI, long longs and aggregate types are always passed
1111 else if (sh_is_renesas_calling_convention (func_type
)
1112 && ((TYPE_CODE (type
) == TYPE_CODE_INT
&& len
== 8)
1113 || TYPE_CODE (type
) == TYPE_CODE_STRUCT
1114 || TYPE_CODE (type
) == TYPE_CODE_UNION
))
1116 /* In contrast to non-FPU CPUs, arguments are never split between
1117 registers and stack. If an argument doesn't fit in the remaining
1118 registers it's always pushed entirely on the stack. */
1119 else if (len
> ((ARGLAST_REGNUM
- argreg
+ 1) * 4))
1124 if ((treat_as_flt
&& flt_argreg
> FLOAT_ARGLAST_REGNUM
)
1125 || (!treat_as_flt
&& (argreg
> ARGLAST_REGNUM
1127 || argnum
> last_reg_arg
)
1129 /* The data goes entirely on the stack, 4-byte aligned. */
1130 reg_size
= (len
+ 3) & ~3;
1131 write_memory (sp
+ stack_offset
, val
, reg_size
);
1132 stack_offset
+= reg_size
;
1134 else if (treat_as_flt
&& flt_argreg
<= FLOAT_ARGLAST_REGNUM
)
1136 /* Argument goes in a float argument register. */
1137 reg_size
= register_size (gdbarch
, flt_argreg
);
1138 regval
= extract_unsigned_integer (val
, reg_size
, byte_order
);
1139 /* In little endian mode, float types taking two registers
1140 (doubles on sh4, long doubles on sh2e, sh3e and sh4) must
1141 be stored swapped in the argument registers. The below
1142 code first writes the first 32 bits in the next but one
1143 register, increments the val and len values accordingly
1144 and then proceeds as normal by writing the second 32 bits
1145 into the next register. */
1146 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
1147 && TYPE_LENGTH (type
) == 2 * reg_size
)
1149 regcache_cooked_write_unsigned (regcache
, flt_argreg
+ 1,
1153 regval
= extract_unsigned_integer (val
, reg_size
,
1156 regcache_cooked_write_unsigned (regcache
, flt_argreg
++, regval
);
1158 else if (!treat_as_flt
&& argreg
<= ARGLAST_REGNUM
)
1160 /* there's room in a register */
1161 reg_size
= register_size (gdbarch
, argreg
);
1162 regval
= extract_unsigned_integer (val
, reg_size
, byte_order
);
1163 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
1165 /* Store the value one register at a time or in one step on
1174 if (sh_is_renesas_calling_convention (func_type
))
1175 /* If the function uses the Renesas ABI, subtract another 4 bytes from
1176 the stack and store the struct return address there. */
1177 write_memory_unsigned_integer (sp
-= 4, 4, byte_order
, struct_addr
);
1179 /* Using the gcc ABI, the "struct return pointer" pseudo-argument has
1180 its own dedicated register. */
1181 regcache_cooked_write_unsigned (regcache
,
1182 STRUCT_RETURN_REGNUM
, struct_addr
);
1185 /* Store return address. */
1186 regcache_cooked_write_unsigned (regcache
, PR_REGNUM
, bp_addr
);
1188 /* Update stack pointer. */
1189 regcache_cooked_write_unsigned (regcache
,
1190 gdbarch_sp_regnum (gdbarch
), sp
);
1196 sh_push_dummy_call_nofpu (struct gdbarch
*gdbarch
,
1197 struct value
*function
,
1198 struct regcache
*regcache
,
1200 int nargs
, struct value
**args
,
1201 CORE_ADDR sp
, int struct_return
,
1202 CORE_ADDR struct_addr
)
1204 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1205 int stack_offset
= 0;
1206 int argreg
= ARG0_REGNUM
;
1208 struct type
*func_type
= value_type (function
);
1211 const gdb_byte
*val
;
1212 int len
, reg_size
= 0;
1213 int pass_on_stack
= 0;
1214 int last_reg_arg
= INT_MAX
;
1216 /* The Renesas ABI expects all varargs arguments, plus the last
1217 non-vararg argument to be on the stack, no matter how many
1218 registers have been used so far. */
1219 if (sh_is_renesas_calling_convention (func_type
)
1220 && TYPE_VARARGS (func_type
))
1221 last_reg_arg
= TYPE_NFIELDS (func_type
) - 2;
1223 /* First force sp to a 4-byte alignment. */
1224 sp
= sh_frame_align (gdbarch
, sp
);
1226 /* Make room on stack for args. */
1227 sp
-= sh_stack_allocsize (nargs
, args
);
1229 /* Now load as many as possible of the first arguments into
1230 registers, and push the rest onto the stack. There are 16 bytes
1231 in four registers available. Loop thru args from first to last. */
1232 for (argnum
= 0; argnum
< nargs
; argnum
++)
1234 type
= value_type (args
[argnum
]);
1235 len
= TYPE_LENGTH (type
);
1236 val
= sh_justify_value_in_reg (gdbarch
, args
[argnum
], len
);
1238 /* Some decisions have to be made how various types are handled.
1239 This also differs in different ABIs. */
1241 /* Renesas ABI pushes doubles and long longs entirely on stack.
1242 Same goes for aggregate types. */
1243 if (sh_is_renesas_calling_convention (func_type
)
1244 && ((TYPE_CODE (type
) == TYPE_CODE_INT
&& len
>= 8)
1245 || (TYPE_CODE (type
) == TYPE_CODE_FLT
&& len
>= 8)
1246 || TYPE_CODE (type
) == TYPE_CODE_STRUCT
1247 || TYPE_CODE (type
) == TYPE_CODE_UNION
))
1251 if (argreg
> ARGLAST_REGNUM
|| pass_on_stack
1252 || argnum
> last_reg_arg
)
1254 /* The remainder of the data goes entirely on the stack,
1256 reg_size
= (len
+ 3) & ~3;
1257 write_memory (sp
+ stack_offset
, val
, reg_size
);
1258 stack_offset
+= reg_size
;
1260 else if (argreg
<= ARGLAST_REGNUM
)
1262 /* There's room in a register. */
1263 reg_size
= register_size (gdbarch
, argreg
);
1264 regval
= extract_unsigned_integer (val
, reg_size
, byte_order
);
1265 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
1267 /* Store the value reg_size bytes at a time. This means that things
1268 larger than reg_size bytes may go partly in registers and partly
1277 if (sh_is_renesas_calling_convention (func_type
))
1278 /* If the function uses the Renesas ABI, subtract another 4 bytes from
1279 the stack and store the struct return address there. */
1280 write_memory_unsigned_integer (sp
-= 4, 4, byte_order
, struct_addr
);
1282 /* Using the gcc ABI, the "struct return pointer" pseudo-argument has
1283 its own dedicated register. */
1284 regcache_cooked_write_unsigned (regcache
,
1285 STRUCT_RETURN_REGNUM
, struct_addr
);
1288 /* Store return address. */
1289 regcache_cooked_write_unsigned (regcache
, PR_REGNUM
, bp_addr
);
1291 /* Update stack pointer. */
1292 regcache_cooked_write_unsigned (regcache
,
1293 gdbarch_sp_regnum (gdbarch
), sp
);
1298 /* Find a function's return value in the appropriate registers (in
1299 regbuf), and copy it into valbuf. Extract from an array REGBUF
1300 containing the (raw) register state a function return value of type
1301 TYPE, and copy that, in virtual format, into VALBUF. */
1303 sh_extract_return_value_nofpu (struct type
*type
, struct regcache
*regcache
,
1306 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1307 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1308 int len
= TYPE_LENGTH (type
);
1309 int return_register
= R0_REGNUM
;
1316 regcache_cooked_read_unsigned (regcache
, R0_REGNUM
, &c
);
1317 store_unsigned_integer (valbuf
, len
, byte_order
, c
);
1321 int i
, regnum
= R0_REGNUM
;
1322 for (i
= 0; i
< len
; i
+= 4)
1323 regcache_raw_read (regcache
, regnum
++, valbuf
+ i
);
1326 error (_("bad size for return value"));
1330 sh_extract_return_value_fpu (struct type
*type
, struct regcache
*regcache
,
1333 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1334 if (sh_treat_as_flt_p (type
))
1336 int len
= TYPE_LENGTH (type
);
1337 int i
, regnum
= gdbarch_fp0_regnum (gdbarch
);
1338 for (i
= 0; i
< len
; i
+= 4)
1339 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
1340 regcache_raw_read (regcache
, regnum
++,
1341 valbuf
+ len
- 4 - i
);
1343 regcache_raw_read (regcache
, regnum
++, valbuf
+ i
);
1346 sh_extract_return_value_nofpu (type
, regcache
, valbuf
);
1349 /* Write into appropriate registers a function return value
1350 of type TYPE, given in virtual format.
1351 If the architecture is sh4 or sh3e, store a function's return value
1352 in the R0 general register or in the FP0 floating point register,
1353 depending on the type of the return value. In all the other cases
1354 the result is stored in r0, left-justified. */
1356 sh_store_return_value_nofpu (struct type
*type
, struct regcache
*regcache
,
1357 const gdb_byte
*valbuf
)
1359 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1360 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1362 int len
= TYPE_LENGTH (type
);
1366 val
= extract_unsigned_integer (valbuf
, len
, byte_order
);
1367 regcache_cooked_write_unsigned (regcache
, R0_REGNUM
, val
);
1371 int i
, regnum
= R0_REGNUM
;
1372 for (i
= 0; i
< len
; i
+= 4)
1373 regcache_raw_write (regcache
, regnum
++, valbuf
+ i
);
1378 sh_store_return_value_fpu (struct type
*type
, struct regcache
*regcache
,
1379 const gdb_byte
*valbuf
)
1381 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1382 if (sh_treat_as_flt_p (type
))
1384 int len
= TYPE_LENGTH (type
);
1385 int i
, regnum
= gdbarch_fp0_regnum (gdbarch
);
1386 for (i
= 0; i
< len
; i
+= 4)
1387 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
1388 regcache_raw_write (regcache
, regnum
++,
1389 valbuf
+ len
- 4 - i
);
1391 regcache_raw_write (regcache
, regnum
++, valbuf
+ i
);
1394 sh_store_return_value_nofpu (type
, regcache
, valbuf
);
1397 static enum return_value_convention
1398 sh_return_value_nofpu (struct gdbarch
*gdbarch
, struct value
*function
,
1399 struct type
*type
, struct regcache
*regcache
,
1400 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1402 struct type
*func_type
= function
? value_type (function
) : NULL
;
1404 if (sh_use_struct_convention_nofpu (
1405 sh_is_renesas_calling_convention (func_type
), type
))
1406 return RETURN_VALUE_STRUCT_CONVENTION
;
1408 sh_store_return_value_nofpu (type
, regcache
, writebuf
);
1410 sh_extract_return_value_nofpu (type
, regcache
, readbuf
);
1411 return RETURN_VALUE_REGISTER_CONVENTION
;
1414 static enum return_value_convention
1415 sh_return_value_fpu (struct gdbarch
*gdbarch
, struct value
*function
,
1416 struct type
*type
, struct regcache
*regcache
,
1417 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1419 struct type
*func_type
= function
? value_type (function
) : NULL
;
1421 if (sh_use_struct_convention (
1422 sh_is_renesas_calling_convention (func_type
), type
))
1423 return RETURN_VALUE_STRUCT_CONVENTION
;
1425 sh_store_return_value_fpu (type
, regcache
, writebuf
);
1427 sh_extract_return_value_fpu (type
, regcache
, readbuf
);
1428 return RETURN_VALUE_REGISTER_CONVENTION
;
1431 static struct type
*
1432 sh_sh2a_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
1434 if ((reg_nr
>= gdbarch_fp0_regnum (gdbarch
)
1435 && (reg_nr
<= FP_LAST_REGNUM
)) || (reg_nr
== FPUL_REGNUM
))
1436 return builtin_type (gdbarch
)->builtin_float
;
1437 else if (reg_nr
>= DR0_REGNUM
&& reg_nr
<= DR_LAST_REGNUM
)
1438 return builtin_type (gdbarch
)->builtin_double
;
1440 return builtin_type (gdbarch
)->builtin_int
;
1443 /* Return the GDB type object for the "standard" data type
1444 of data in register N. */
1445 static struct type
*
1446 sh_sh3e_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
1448 if ((reg_nr
>= gdbarch_fp0_regnum (gdbarch
)
1449 && (reg_nr
<= FP_LAST_REGNUM
)) || (reg_nr
== FPUL_REGNUM
))
1450 return builtin_type (gdbarch
)->builtin_float
;
1452 return builtin_type (gdbarch
)->builtin_int
;
1455 static struct type
*
1456 sh_sh4_build_float_register_type (struct gdbarch
*gdbarch
, int high
)
1458 return lookup_array_range_type (builtin_type (gdbarch
)->builtin_float
,
1462 static struct type
*
1463 sh_sh4_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
1465 if ((reg_nr
>= gdbarch_fp0_regnum (gdbarch
)
1466 && (reg_nr
<= FP_LAST_REGNUM
)) || (reg_nr
== FPUL_REGNUM
))
1467 return builtin_type (gdbarch
)->builtin_float
;
1468 else if (reg_nr
>= DR0_REGNUM
&& reg_nr
<= DR_LAST_REGNUM
)
1469 return builtin_type (gdbarch
)->builtin_double
;
1470 else if (reg_nr
>= FV0_REGNUM
&& reg_nr
<= FV_LAST_REGNUM
)
1471 return sh_sh4_build_float_register_type (gdbarch
, 3);
1473 return builtin_type (gdbarch
)->builtin_int
;
1476 static struct type
*
1477 sh_default_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
1479 return builtin_type (gdbarch
)->builtin_int
;
1482 /* Is a register in a reggroup?
1483 The default code in reggroup.c doesn't identify system registers, some
1484 float registers or any of the vector registers.
1485 TODO: sh2a and dsp registers. */
1487 sh_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
1488 struct reggroup
*reggroup
)
1490 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
1491 || *gdbarch_register_name (gdbarch
, regnum
) == '\0')
1494 if (reggroup
== float_reggroup
1495 && (regnum
== FPUL_REGNUM
1496 || regnum
== FPSCR_REGNUM
))
1499 if (regnum
>= FV0_REGNUM
&& regnum
<= FV_LAST_REGNUM
)
1501 if (reggroup
== vector_reggroup
|| reggroup
== float_reggroup
)
1503 if (reggroup
== general_reggroup
)
1507 if (regnum
== VBR_REGNUM
1508 || regnum
== SR_REGNUM
1509 || regnum
== FPSCR_REGNUM
1510 || regnum
== SSR_REGNUM
1511 || regnum
== SPC_REGNUM
)
1513 if (reggroup
== system_reggroup
)
1515 if (reggroup
== general_reggroup
)
1519 /* The default code can cope with any other registers. */
1520 return default_register_reggroup_p (gdbarch
, regnum
, reggroup
);
1523 /* On the sh4, the DRi pseudo registers are problematic if the target
1524 is little endian. When the user writes one of those registers, for
1525 instance with 'set var $dr0=1', we want the double to be stored
1527 fr0 = 0x00 0x00 0xf0 0x3f
1528 fr1 = 0x00 0x00 0x00 0x00
1530 This corresponds to little endian byte order & big endian word
1531 order. However if we let gdb write the register w/o conversion, it
1532 will write fr0 and fr1 this way:
1533 fr0 = 0x00 0x00 0x00 0x00
1534 fr1 = 0x00 0x00 0xf0 0x3f
1535 because it will consider fr0 and fr1 as a single LE stretch of memory.
1537 To achieve what we want we must force gdb to store things in
1538 floatformat_ieee_double_littlebyte_bigword (which is defined in
1539 include/floatformat.h and libiberty/floatformat.c.
1541 In case the target is big endian, there is no problem, the
1542 raw bytes will look like:
1543 fr0 = 0x3f 0xf0 0x00 0x00
1544 fr1 = 0x00 0x00 0x00 0x00
1546 The other pseudo registers (the FVs) also don't pose a problem
1547 because they are stored as 4 individual FP elements. */
1550 sh_register_convert_to_virtual (struct gdbarch
*gdbarch
, int regnum
,
1551 struct type
*type
, gdb_byte
*from
, gdb_byte
*to
)
1553 if (gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_LITTLE
)
1555 /* It is a no-op. */
1556 memcpy (to
, from
, register_size (gdbarch
, regnum
));
1560 if (regnum
>= DR0_REGNUM
&& regnum
<= DR_LAST_REGNUM
)
1563 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword
,
1565 store_typed_floating (to
, type
, val
);
1569 ("sh_register_convert_to_virtual called with non DR register number");
1573 sh_register_convert_to_raw (struct gdbarch
*gdbarch
, struct type
*type
,
1574 int regnum
, const gdb_byte
*from
, gdb_byte
*to
)
1576 if (gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_LITTLE
)
1578 /* It is a no-op. */
1579 memcpy (to
, from
, register_size (gdbarch
, regnum
));
1583 if (regnum
>= DR0_REGNUM
&& regnum
<= DR_LAST_REGNUM
)
1585 DOUBLEST val
= extract_typed_floating (from
, type
);
1586 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword
,
1590 error (_("sh_register_convert_to_raw called with non DR register number"));
1593 /* For vectors of 4 floating point registers. */
1595 fv_reg_base_num (struct gdbarch
*gdbarch
, int fv_regnum
)
1599 fp_regnum
= gdbarch_fp0_regnum (gdbarch
)
1600 + (fv_regnum
- FV0_REGNUM
) * 4;
1604 /* For double precision floating point registers, i.e 2 fp regs. */
1606 dr_reg_base_num (struct gdbarch
*gdbarch
, int dr_regnum
)
1610 fp_regnum
= gdbarch_fp0_regnum (gdbarch
)
1611 + (dr_regnum
- DR0_REGNUM
) * 2;
1615 /* Concatenate PORTIONS contiguous raw registers starting at
1616 BASE_REGNUM into BUFFER. */
1618 static enum register_status
1619 pseudo_register_read_portions (struct gdbarch
*gdbarch
,
1620 struct regcache
*regcache
,
1622 int base_regnum
, gdb_byte
*buffer
)
1626 for (portion
= 0; portion
< portions
; portion
++)
1628 enum register_status status
;
1631 b
= buffer
+ register_size (gdbarch
, base_regnum
) * portion
;
1632 status
= regcache_raw_read (regcache
, base_regnum
+ portion
, b
);
1633 if (status
!= REG_VALID
)
1640 static enum register_status
1641 sh_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1642 int reg_nr
, gdb_byte
*buffer
)
1645 gdb_byte temp_buffer
[MAX_REGISTER_SIZE
];
1646 enum register_status status
;
1648 if (reg_nr
== PSEUDO_BANK_REGNUM
)
1649 return regcache_raw_read (regcache
, BANK_REGNUM
, buffer
);
1650 else if (reg_nr
>= DR0_REGNUM
&& reg_nr
<= DR_LAST_REGNUM
)
1652 base_regnum
= dr_reg_base_num (gdbarch
, reg_nr
);
1654 /* Build the value in the provided buffer. */
1655 /* Read the real regs for which this one is an alias. */
1656 status
= pseudo_register_read_portions (gdbarch
, regcache
,
1657 2, base_regnum
, temp_buffer
);
1658 if (status
== REG_VALID
)
1660 /* We must pay attention to the endiannes. */
1661 sh_register_convert_to_virtual (gdbarch
, reg_nr
,
1662 register_type (gdbarch
, reg_nr
),
1663 temp_buffer
, buffer
);
1667 else if (reg_nr
>= FV0_REGNUM
&& reg_nr
<= FV_LAST_REGNUM
)
1669 base_regnum
= fv_reg_base_num (gdbarch
, reg_nr
);
1671 /* Read the real regs for which this one is an alias. */
1672 return pseudo_register_read_portions (gdbarch
, regcache
,
1673 4, base_regnum
, buffer
);
1676 gdb_assert_not_reached ("invalid pseudo register number");
1680 sh_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1681 int reg_nr
, const gdb_byte
*buffer
)
1683 int base_regnum
, portion
;
1684 gdb_byte temp_buffer
[MAX_REGISTER_SIZE
];
1686 if (reg_nr
== PSEUDO_BANK_REGNUM
)
1688 /* When the bank register is written to, the whole register bank
1689 is switched and all values in the bank registers must be read
1690 from the target/sim again. We're just invalidating the regcache
1691 so that a re-read happens next time it's necessary. */
1694 regcache_raw_write (regcache
, BANK_REGNUM
, buffer
);
1695 for (bregnum
= R0_BANK0_REGNUM
; bregnum
< MACLB_REGNUM
; ++bregnum
)
1696 regcache_invalidate (regcache
, bregnum
);
1698 else if (reg_nr
>= DR0_REGNUM
&& reg_nr
<= DR_LAST_REGNUM
)
1700 base_regnum
= dr_reg_base_num (gdbarch
, reg_nr
);
1702 /* We must pay attention to the endiannes. */
1703 sh_register_convert_to_raw (gdbarch
, register_type (gdbarch
, reg_nr
),
1704 reg_nr
, buffer
, temp_buffer
);
1706 /* Write the real regs for which this one is an alias. */
1707 for (portion
= 0; portion
< 2; portion
++)
1708 regcache_raw_write (regcache
, base_regnum
+ portion
,
1710 + register_size (gdbarch
,
1711 base_regnum
) * portion
));
1713 else if (reg_nr
>= FV0_REGNUM
&& reg_nr
<= FV_LAST_REGNUM
)
1715 base_regnum
= fv_reg_base_num (gdbarch
, reg_nr
);
1717 /* Write the real regs for which this one is an alias. */
1718 for (portion
= 0; portion
< 4; portion
++)
1719 regcache_raw_write (regcache
, base_regnum
+ portion
,
1721 + register_size (gdbarch
,
1722 base_regnum
) * portion
));
1727 sh_dsp_register_sim_regno (struct gdbarch
*gdbarch
, int nr
)
1729 if (legacy_register_sim_regno (gdbarch
, nr
) < 0)
1730 return legacy_register_sim_regno (gdbarch
, nr
);
1731 if (nr
>= DSR_REGNUM
&& nr
<= Y1_REGNUM
)
1732 return nr
- DSR_REGNUM
+ SIM_SH_DSR_REGNUM
;
1733 if (nr
== MOD_REGNUM
)
1734 return SIM_SH_MOD_REGNUM
;
1735 if (nr
== RS_REGNUM
)
1736 return SIM_SH_RS_REGNUM
;
1737 if (nr
== RE_REGNUM
)
1738 return SIM_SH_RE_REGNUM
;
1739 if (nr
>= DSP_R0_BANK_REGNUM
&& nr
<= DSP_R7_BANK_REGNUM
)
1740 return nr
- DSP_R0_BANK_REGNUM
+ SIM_SH_R0_BANK_REGNUM
;
1745 sh_sh2a_register_sim_regno (struct gdbarch
*gdbarch
, int nr
)
1750 return SIM_SH_TBR_REGNUM
;
1752 return SIM_SH_IBNR_REGNUM
;
1754 return SIM_SH_IBCR_REGNUM
;
1756 return SIM_SH_BANK_REGNUM
;
1758 return SIM_SH_BANK_MACL_REGNUM
;
1760 return SIM_SH_BANK_GBR_REGNUM
;
1762 return SIM_SH_BANK_PR_REGNUM
;
1764 return SIM_SH_BANK_IVN_REGNUM
;
1766 return SIM_SH_BANK_MACH_REGNUM
;
1770 return legacy_register_sim_regno (gdbarch
, nr
);
1773 /* Set up the register unwinding such that call-clobbered registers are
1774 not displayed in frames >0 because the true value is not certain.
1775 The 'undefined' registers will show up as 'not available' unless the
1778 This function is currently set up for SH4 and compatible only. */
1781 sh_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1782 struct dwarf2_frame_state_reg
*reg
,
1783 struct frame_info
*this_frame
)
1785 /* Mark the PC as the destination for the return address. */
1786 if (regnum
== gdbarch_pc_regnum (gdbarch
))
1787 reg
->how
= DWARF2_FRAME_REG_RA
;
1789 /* Mark the stack pointer as the call frame address. */
1790 else if (regnum
== gdbarch_sp_regnum (gdbarch
))
1791 reg
->how
= DWARF2_FRAME_REG_CFA
;
1793 /* The above was taken from the default init_reg in dwarf2-frame.c
1794 while the below is SH specific. */
1796 /* Caller save registers. */
1797 else if ((regnum
>= R0_REGNUM
&& regnum
<= R0_REGNUM
+7)
1798 || (regnum
>= FR0_REGNUM
&& regnum
<= FR0_REGNUM
+11)
1799 || (regnum
>= DR0_REGNUM
&& regnum
<= DR0_REGNUM
+5)
1800 || (regnum
>= FV0_REGNUM
&& regnum
<= FV0_REGNUM
+2)
1801 || (regnum
== MACH_REGNUM
)
1802 || (regnum
== MACL_REGNUM
)
1803 || (regnum
== FPUL_REGNUM
)
1804 || (regnum
== SR_REGNUM
))
1805 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
1807 /* Callee save registers. */
1808 else if ((regnum
>= R0_REGNUM
+8 && regnum
<= R0_REGNUM
+15)
1809 || (regnum
>= FR0_REGNUM
+12 && regnum
<= FR0_REGNUM
+15)
1810 || (regnum
>= DR0_REGNUM
+6 && regnum
<= DR0_REGNUM
+8)
1811 || (regnum
== FV0_REGNUM
+3))
1812 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
1814 /* Other registers. These are not in the ABI and may or may not
1815 mean anything in frames >0 so don't show them. */
1816 else if ((regnum
>= R0_BANK0_REGNUM
&& regnum
<= R0_BANK0_REGNUM
+15)
1817 || (regnum
== GBR_REGNUM
)
1818 || (regnum
== VBR_REGNUM
)
1819 || (regnum
== FPSCR_REGNUM
)
1820 || (regnum
== SSR_REGNUM
)
1821 || (regnum
== SPC_REGNUM
))
1822 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
1825 static struct sh_frame_cache
*
1826 sh_alloc_frame_cache (void)
1828 struct sh_frame_cache
*cache
;
1831 cache
= FRAME_OBSTACK_ZALLOC (struct sh_frame_cache
);
1835 cache
->saved_sp
= 0;
1836 cache
->sp_offset
= 0;
1839 /* Frameless until proven otherwise. */
1842 /* Saved registers. We initialize these to -1 since zero is a valid
1843 offset (that's where fp is supposed to be stored). */
1844 for (i
= 0; i
< SH_NUM_REGS
; i
++)
1846 cache
->saved_regs
[i
] = -1;
1852 static struct sh_frame_cache
*
1853 sh_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1855 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1856 struct sh_frame_cache
*cache
;
1857 CORE_ADDR current_pc
;
1863 cache
= sh_alloc_frame_cache ();
1864 *this_cache
= cache
;
1866 /* In principle, for normal frames, fp holds the frame pointer,
1867 which holds the base address for the current stack frame.
1868 However, for functions that don't need it, the frame pointer is
1869 optional. For these "frameless" functions the frame pointer is
1870 actually the frame pointer of the calling frame. */
1871 cache
->base
= get_frame_register_unsigned (this_frame
, FP_REGNUM
);
1872 if (cache
->base
== 0)
1875 cache
->pc
= get_frame_func (this_frame
);
1876 current_pc
= get_frame_pc (this_frame
);
1881 /* Check for the existence of the FPSCR register. If it exists,
1882 fetch its value for use in prologue analysis. Passing a zero
1883 value is the best choice for architecture variants upon which
1884 there's no FPSCR register. */
1885 if (gdbarch_register_reggroup_p (gdbarch
, FPSCR_REGNUM
, all_reggroup
))
1886 fpscr
= get_frame_register_unsigned (this_frame
, FPSCR_REGNUM
);
1890 sh_analyze_prologue (gdbarch
, cache
->pc
, current_pc
, cache
, fpscr
);
1893 if (!cache
->uses_fp
)
1895 /* We didn't find a valid frame, which means that CACHE->base
1896 currently holds the frame pointer for our calling frame. If
1897 we're at the start of a function, or somewhere half-way its
1898 prologue, the function's frame probably hasn't been fully
1899 setup yet. Try to reconstruct the base address for the stack
1900 frame by looking at the stack pointer. For truly "frameless"
1901 functions this might work too. */
1902 cache
->base
= get_frame_register_unsigned
1903 (this_frame
, gdbarch_sp_regnum (gdbarch
));
1906 /* Now that we have the base address for the stack frame we can
1907 calculate the value of sp in the calling frame. */
1908 cache
->saved_sp
= cache
->base
+ cache
->sp_offset
;
1910 /* Adjust all the saved registers such that they contain addresses
1911 instead of offsets. */
1912 for (i
= 0; i
< SH_NUM_REGS
; i
++)
1913 if (cache
->saved_regs
[i
] != -1)
1914 cache
->saved_regs
[i
] = cache
->saved_sp
- cache
->saved_regs
[i
] - 4;
1919 static struct value
*
1920 sh_frame_prev_register (struct frame_info
*this_frame
,
1921 void **this_cache
, int regnum
)
1923 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1924 struct sh_frame_cache
*cache
= sh_frame_cache (this_frame
, this_cache
);
1926 gdb_assert (regnum
>= 0);
1928 if (regnum
== gdbarch_sp_regnum (gdbarch
) && cache
->saved_sp
)
1929 return frame_unwind_got_constant (this_frame
, regnum
, cache
->saved_sp
);
1931 /* The PC of the previous frame is stored in the PR register of
1932 the current frame. Frob regnum so that we pull the value from
1933 the correct place. */
1934 if (regnum
== gdbarch_pc_regnum (gdbarch
))
1937 if (regnum
< SH_NUM_REGS
&& cache
->saved_regs
[regnum
] != -1)
1938 return frame_unwind_got_memory (this_frame
, regnum
,
1939 cache
->saved_regs
[regnum
]);
1941 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1945 sh_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1946 struct frame_id
*this_id
)
1948 struct sh_frame_cache
*cache
= sh_frame_cache (this_frame
, this_cache
);
1950 /* This marks the outermost frame. */
1951 if (cache
->base
== 0)
1954 *this_id
= frame_id_build (cache
->saved_sp
, cache
->pc
);
1957 static const struct frame_unwind sh_frame_unwind
= {
1959 default_frame_unwind_stop_reason
,
1961 sh_frame_prev_register
,
1963 default_frame_sniffer
1967 sh_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1969 return frame_unwind_register_unsigned (next_frame
,
1970 gdbarch_sp_regnum (gdbarch
));
1974 sh_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1976 return frame_unwind_register_unsigned (next_frame
,
1977 gdbarch_pc_regnum (gdbarch
));
1980 static struct frame_id
1981 sh_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1983 CORE_ADDR sp
= get_frame_register_unsigned (this_frame
,
1984 gdbarch_sp_regnum (gdbarch
));
1985 return frame_id_build (sp
, get_frame_pc (this_frame
));
1989 sh_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
1991 struct sh_frame_cache
*cache
= sh_frame_cache (this_frame
, this_cache
);
1996 static const struct frame_base sh_frame_base
= {
1998 sh_frame_base_address
,
1999 sh_frame_base_address
,
2000 sh_frame_base_address
2003 static struct sh_frame_cache
*
2004 sh_make_stub_cache (struct frame_info
*this_frame
)
2006 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2007 struct sh_frame_cache
*cache
;
2009 cache
= sh_alloc_frame_cache ();
2012 = get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
2018 sh_stub_this_id (struct frame_info
*this_frame
, void **this_cache
,
2019 struct frame_id
*this_id
)
2021 struct sh_frame_cache
*cache
;
2023 if (*this_cache
== NULL
)
2024 *this_cache
= sh_make_stub_cache (this_frame
);
2025 cache
= *this_cache
;
2027 *this_id
= frame_id_build (cache
->saved_sp
, get_frame_pc (this_frame
));
2031 sh_stub_unwind_sniffer (const struct frame_unwind
*self
,
2032 struct frame_info
*this_frame
,
2033 void **this_prologue_cache
)
2035 CORE_ADDR addr_in_block
;
2037 addr_in_block
= get_frame_address_in_block (this_frame
);
2038 if (in_plt_section (addr_in_block
))
2044 static const struct frame_unwind sh_stub_unwind
=
2047 default_frame_unwind_stop_reason
,
2049 sh_frame_prev_register
,
2051 sh_stub_unwind_sniffer
2054 /* The epilogue is defined here as the area at the end of a function,
2055 either on the `ret' instruction itself or after an instruction which
2056 destroys the function's stack frame. */
2058 sh_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2060 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2061 CORE_ADDR func_addr
= 0, func_end
= 0;
2063 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
2066 /* The sh epilogue is max. 14 bytes long. Give another 14 bytes
2067 for a nop and some fixed data (e.g. big offsets) which are
2068 unfortunately also treated as part of the function (which
2069 means, they are below func_end. */
2070 CORE_ADDR addr
= func_end
- 28;
2071 if (addr
< func_addr
+ 4)
2072 addr
= func_addr
+ 4;
2076 /* First search forward until hitting an rts. */
2077 while (addr
< func_end
2078 && !IS_RTS (read_memory_unsigned_integer (addr
, 2, byte_order
)))
2080 if (addr
>= func_end
)
2083 /* At this point we should find a mov.l @r15+,r14 instruction,
2084 either before or after the rts. If not, then the function has
2085 probably no "normal" epilogue and we bail out here. */
2086 inst
= read_memory_unsigned_integer (addr
- 2, 2, byte_order
);
2087 if (IS_RESTORE_FP (read_memory_unsigned_integer (addr
- 2, 2,
2090 else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr
+ 2, 2,
2094 inst
= read_memory_unsigned_integer (addr
- 2, 2, byte_order
);
2096 /* Step over possible lds.l @r15+,macl. */
2097 if (IS_MACL_LDS (inst
))
2100 inst
= read_memory_unsigned_integer (addr
- 2, 2, byte_order
);
2103 /* Step over possible lds.l @r15+,pr. */
2107 inst
= read_memory_unsigned_integer (addr
- 2, 2, byte_order
);
2110 /* Step over possible mov r14,r15. */
2111 if (IS_MOV_FP_SP (inst
))
2114 inst
= read_memory_unsigned_integer (addr
- 2, 2, byte_order
);
2117 /* Now check for FP adjustments, using add #imm,r14 or add rX, r14
2119 while (addr
> func_addr
+ 4
2120 && (IS_ADD_REG_TO_FP (inst
) || IS_ADD_IMM_FP (inst
)))
2123 inst
= read_memory_unsigned_integer (addr
- 2, 2, byte_order
);
2126 /* On SH2a check if the previous instruction was perhaps a MOVI20.
2127 That's allowed for the epilogue. */
2128 if ((gdbarch_bfd_arch_info (gdbarch
)->mach
== bfd_mach_sh2a
2129 || gdbarch_bfd_arch_info (gdbarch
)->mach
== bfd_mach_sh2a_nofpu
)
2130 && addr
> func_addr
+ 6
2131 && IS_MOVI20 (read_memory_unsigned_integer (addr
- 4, 2,
2142 /* Supply register REGNUM from the buffer specified by REGS and LEN
2143 in the register set REGSET to register cache REGCACHE.
2144 REGTABLE specifies where each register can be found in REGS.
2145 If REGNUM is -1, do this for all registers in REGSET. */
2148 sh_corefile_supply_regset (const struct regset
*regset
,
2149 struct regcache
*regcache
,
2150 int regnum
, const void *regs
, size_t len
)
2152 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
2153 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2154 const struct sh_corefile_regmap
*regmap
= (regset
== &sh_corefile_gregset
2155 ? tdep
->core_gregmap
2156 : tdep
->core_fpregmap
);
2159 for (i
= 0; regmap
[i
].regnum
!= -1; i
++)
2161 if ((regnum
== -1 || regnum
== regmap
[i
].regnum
)
2162 && regmap
[i
].offset
+ 4 <= len
)
2163 regcache_raw_supply (regcache
, regmap
[i
].regnum
,
2164 (char *)regs
+ regmap
[i
].offset
);
2168 /* Collect register REGNUM in the register set REGSET from register cache
2169 REGCACHE into the buffer specified by REGS and LEN.
2170 REGTABLE specifies where each register can be found in REGS.
2171 If REGNUM is -1, do this for all registers in REGSET. */
2174 sh_corefile_collect_regset (const struct regset
*regset
,
2175 const struct regcache
*regcache
,
2176 int regnum
, void *regs
, size_t len
)
2178 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
2179 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2180 const struct sh_corefile_regmap
*regmap
= (regset
== &sh_corefile_gregset
2181 ? tdep
->core_gregmap
2182 : tdep
->core_fpregmap
);
2185 for (i
= 0; regmap
[i
].regnum
!= -1; i
++)
2187 if ((regnum
== -1 || regnum
== regmap
[i
].regnum
)
2188 && regmap
[i
].offset
+ 4 <= len
)
2189 regcache_raw_collect (regcache
, regmap
[i
].regnum
,
2190 (char *)regs
+ regmap
[i
].offset
);
2194 /* The following two regsets have the same contents, so it is tempting to
2195 unify them, but they are distiguished by their address, so don't. */
2197 const struct regset sh_corefile_gregset
=
2200 sh_corefile_supply_regset
,
2201 sh_corefile_collect_regset
2204 static const struct regset sh_corefile_fpregset
=
2207 sh_corefile_supply_regset
,
2208 sh_corefile_collect_regset
2211 static const struct regset
*
2212 sh_regset_from_core_section (struct gdbarch
*gdbarch
, const char *sect_name
,
2215 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2217 if (tdep
->core_gregmap
&& strcmp (sect_name
, ".reg") == 0)
2218 return &sh_corefile_gregset
;
2220 if (tdep
->core_fpregmap
&& strcmp (sect_name
, ".reg2") == 0)
2221 return &sh_corefile_fpregset
;
2226 /* This is the implementation of gdbarch method
2227 return_in_first_hidden_param_p. */
2230 sh_return_in_first_hidden_param_p (struct gdbarch
*gdbarch
,
2238 static struct gdbarch
*
2239 sh_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2241 struct gdbarch
*gdbarch
;
2242 struct gdbarch_tdep
*tdep
;
2244 /* SH5 is handled entirely in sh64-tdep.c. */
2245 if (info
.bfd_arch_info
->mach
== bfd_mach_sh5
)
2246 return sh64_gdbarch_init (info
, arches
);
2248 /* If there is already a candidate, use it. */
2249 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2251 return arches
->gdbarch
;
2253 /* None found, create a new architecture from the information
2255 tdep
= XCNEW (struct gdbarch_tdep
);
2256 gdbarch
= gdbarch_alloc (&info
, tdep
);
2258 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
2259 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2260 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2261 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2262 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2263 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2264 set_gdbarch_long_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2265 set_gdbarch_ptr_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2267 set_gdbarch_num_regs (gdbarch
, SH_NUM_REGS
);
2268 set_gdbarch_sp_regnum (gdbarch
, 15);
2269 set_gdbarch_pc_regnum (gdbarch
, 16);
2270 set_gdbarch_fp0_regnum (gdbarch
, -1);
2271 set_gdbarch_num_pseudo_regs (gdbarch
, 0);
2273 set_gdbarch_register_type (gdbarch
, sh_default_register_type
);
2274 set_gdbarch_register_reggroup_p (gdbarch
, sh_register_reggroup_p
);
2276 set_gdbarch_breakpoint_from_pc (gdbarch
, sh_breakpoint_from_pc
);
2278 set_gdbarch_print_insn (gdbarch
, print_insn_sh
);
2279 set_gdbarch_register_sim_regno (gdbarch
, legacy_register_sim_regno
);
2281 set_gdbarch_return_value (gdbarch
, sh_return_value_nofpu
);
2283 set_gdbarch_skip_prologue (gdbarch
, sh_skip_prologue
);
2284 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2286 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_nofpu
);
2287 set_gdbarch_return_in_first_hidden_param_p (gdbarch
,
2288 sh_return_in_first_hidden_param_p
);
2290 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
2292 set_gdbarch_frame_align (gdbarch
, sh_frame_align
);
2293 set_gdbarch_unwind_sp (gdbarch
, sh_unwind_sp
);
2294 set_gdbarch_unwind_pc (gdbarch
, sh_unwind_pc
);
2295 set_gdbarch_dummy_id (gdbarch
, sh_dummy_id
);
2296 frame_base_set_default (gdbarch
, &sh_frame_base
);
2298 set_gdbarch_in_function_epilogue_p (gdbarch
, sh_in_function_epilogue_p
);
2300 dwarf2_frame_set_init_reg (gdbarch
, sh_dwarf2_frame_init_reg
);
2302 set_gdbarch_regset_from_core_section (gdbarch
, sh_regset_from_core_section
);
2304 switch (info
.bfd_arch_info
->mach
)
2307 set_gdbarch_register_name (gdbarch
, sh_sh_register_name
);
2311 set_gdbarch_register_name (gdbarch
, sh_sh_register_name
);
2315 /* doubles on sh2e and sh3e are actually 4 byte. */
2316 set_gdbarch_double_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2317 set_gdbarch_double_format (gdbarch
, floatformats_ieee_single
);
2319 set_gdbarch_register_name (gdbarch
, sh_sh2e_register_name
);
2320 set_gdbarch_register_type (gdbarch
, sh_sh3e_register_type
);
2321 set_gdbarch_fp0_regnum (gdbarch
, 25);
2322 set_gdbarch_return_value (gdbarch
, sh_return_value_fpu
);
2323 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_fpu
);
2327 set_gdbarch_register_name (gdbarch
, sh_sh2a_register_name
);
2328 set_gdbarch_register_type (gdbarch
, sh_sh2a_register_type
);
2329 set_gdbarch_register_sim_regno (gdbarch
, sh_sh2a_register_sim_regno
);
2331 set_gdbarch_fp0_regnum (gdbarch
, 25);
2332 set_gdbarch_num_pseudo_regs (gdbarch
, 9);
2333 set_gdbarch_pseudo_register_read (gdbarch
, sh_pseudo_register_read
);
2334 set_gdbarch_pseudo_register_write (gdbarch
, sh_pseudo_register_write
);
2335 set_gdbarch_return_value (gdbarch
, sh_return_value_fpu
);
2336 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_fpu
);
2339 case bfd_mach_sh2a_nofpu
:
2340 set_gdbarch_register_name (gdbarch
, sh_sh2a_nofpu_register_name
);
2341 set_gdbarch_register_sim_regno (gdbarch
, sh_sh2a_register_sim_regno
);
2343 set_gdbarch_num_pseudo_regs (gdbarch
, 1);
2344 set_gdbarch_pseudo_register_read (gdbarch
, sh_pseudo_register_read
);
2345 set_gdbarch_pseudo_register_write (gdbarch
, sh_pseudo_register_write
);
2348 case bfd_mach_sh_dsp
:
2349 set_gdbarch_register_name (gdbarch
, sh_sh_dsp_register_name
);
2350 set_gdbarch_register_sim_regno (gdbarch
, sh_dsp_register_sim_regno
);
2354 case bfd_mach_sh3_nommu
:
2355 case bfd_mach_sh2a_nofpu_or_sh3_nommu
:
2356 set_gdbarch_register_name (gdbarch
, sh_sh3_register_name
);
2360 case bfd_mach_sh2a_or_sh3e
:
2361 /* doubles on sh2e and sh3e are actually 4 byte. */
2362 set_gdbarch_double_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2363 set_gdbarch_double_format (gdbarch
, floatformats_ieee_single
);
2365 set_gdbarch_register_name (gdbarch
, sh_sh3e_register_name
);
2366 set_gdbarch_register_type (gdbarch
, sh_sh3e_register_type
);
2367 set_gdbarch_fp0_regnum (gdbarch
, 25);
2368 set_gdbarch_return_value (gdbarch
, sh_return_value_fpu
);
2369 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_fpu
);
2372 case bfd_mach_sh3_dsp
:
2373 set_gdbarch_register_name (gdbarch
, sh_sh3_dsp_register_name
);
2374 set_gdbarch_register_sim_regno (gdbarch
, sh_dsp_register_sim_regno
);
2379 case bfd_mach_sh2a_or_sh4
:
2380 set_gdbarch_register_name (gdbarch
, sh_sh4_register_name
);
2381 set_gdbarch_register_type (gdbarch
, sh_sh4_register_type
);
2382 set_gdbarch_fp0_regnum (gdbarch
, 25);
2383 set_gdbarch_num_pseudo_regs (gdbarch
, 13);
2384 set_gdbarch_pseudo_register_read (gdbarch
, sh_pseudo_register_read
);
2385 set_gdbarch_pseudo_register_write (gdbarch
, sh_pseudo_register_write
);
2386 set_gdbarch_return_value (gdbarch
, sh_return_value_fpu
);
2387 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_fpu
);
2390 case bfd_mach_sh4_nofpu
:
2391 case bfd_mach_sh4a_nofpu
:
2392 case bfd_mach_sh4_nommu_nofpu
:
2393 case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu
:
2394 set_gdbarch_register_name (gdbarch
, sh_sh4_nofpu_register_name
);
2397 case bfd_mach_sh4al_dsp
:
2398 set_gdbarch_register_name (gdbarch
, sh_sh4al_dsp_register_name
);
2399 set_gdbarch_register_sim_regno (gdbarch
, sh_dsp_register_sim_regno
);
2403 set_gdbarch_register_name (gdbarch
, sh_sh_register_name
);
2407 /* Hook in ABI-specific overrides, if they have been registered. */
2408 gdbarch_init_osabi (info
, gdbarch
);
2410 dwarf2_append_unwinders (gdbarch
);
2411 frame_unwind_append_unwinder (gdbarch
, &sh_stub_unwind
);
2412 frame_unwind_append_unwinder (gdbarch
, &sh_frame_unwind
);
2418 show_sh_command (char *args
, int from_tty
)
2420 help_list (showshcmdlist
, "show sh ", all_commands
, gdb_stdout
);
2424 set_sh_command (char *args
, int from_tty
)
2427 ("\"set sh\" must be followed by an appropriate subcommand.\n");
2428 help_list (setshcmdlist
, "set sh ", all_commands
, gdb_stdout
);
2431 extern initialize_file_ftype _initialize_sh_tdep
; /* -Wmissing-prototypes */
2434 _initialize_sh_tdep (void)
2436 gdbarch_register (bfd_arch_sh
, sh_gdbarch_init
, NULL
);
2438 add_prefix_cmd ("sh", no_class
, set_sh_command
, "SH specific commands.",
2439 &setshcmdlist
, "set sh ", 0, &setlist
);
2440 add_prefix_cmd ("sh", no_class
, show_sh_command
, "SH specific commands.",
2441 &showshcmdlist
, "show sh ", 0, &showlist
);
2443 add_setshow_enum_cmd ("calling-convention", class_vars
, sh_cc_enum
,
2444 &sh_active_calling_convention
,
2445 _("Set calling convention used when calling target "
2446 "functions from GDB."),
2447 _("Show calling convention used when calling target "
2448 "functions from GDB."),
2449 _("gcc - Use GCC calling convention (default).\n"
2450 "renesas - Enforce Renesas calling convention."),
2452 &setshcmdlist
, &showshcmdlist
);