1 /* Target-dependent code for Renesas Super-H, for GDB.
3 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
4 2003, 2004, 2005, 2007, 2008, 2009 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 Contributed by Steve Chamberlain
28 #include "frame-base.h"
29 #include "frame-unwind.h"
30 #include "dwarf2-frame.h"
38 #include "gdb_string.h"
39 #include "gdb_assert.h"
40 #include "arch-utils.h"
41 #include "floatformat.h"
45 #include "reggroups.h"
50 #include "solib-svr4.h"
54 #include "elf/dwarf2.h"
55 /* registers numbers shared with the simulator */
56 #include "gdb/sim-sh.h"
58 /* List of "set sh ..." and "show sh ..." commands. */
59 static struct cmd_list_element
*setshcmdlist
= NULL
;
60 static struct cmd_list_element
*showshcmdlist
= NULL
;
62 static const char sh_cc_gcc
[] = "gcc";
63 static const char sh_cc_renesas
[] = "renesas";
64 static const char *sh_cc_enum
[] = {
70 static const char *sh_active_calling_convention
= sh_cc_gcc
;
72 static void (*sh_show_regs
) (struct frame_info
*);
74 #define SH_NUM_REGS 67
83 /* Flag showing that a frame has been created in the prologue code. */
86 /* Saved registers. */
87 CORE_ADDR saved_regs
[SH_NUM_REGS
];
92 sh_is_renesas_calling_convention (struct type
*func_type
)
95 && TYPE_CALLING_CONVENTION (func_type
) == DW_CC_GNU_renesas_sh
)
96 || sh_active_calling_convention
== sh_cc_renesas
);
100 sh_sh_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
102 static char *register_names
[] = {
103 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
104 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
105 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
107 "", "", "", "", "", "", "", "",
108 "", "", "", "", "", "", "", "",
110 "", "", "", "", "", "", "", "",
111 "", "", "", "", "", "", "", "",
112 "", "", "", "", "", "", "", "",
116 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
118 return register_names
[reg_nr
];
122 sh_sh3_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
124 static char *register_names
[] = {
125 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
126 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
127 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
129 "", "", "", "", "", "", "", "",
130 "", "", "", "", "", "", "", "",
132 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
133 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
134 "", "", "", "", "", "", "", "",
138 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
140 return register_names
[reg_nr
];
144 sh_sh3e_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
146 static char *register_names
[] = {
147 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
148 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
149 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
151 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
152 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
154 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
155 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
156 "", "", "", "", "", "", "", "",
160 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
162 return register_names
[reg_nr
];
166 sh_sh2e_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
168 static char *register_names
[] = {
169 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
170 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
171 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
173 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
174 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
176 "", "", "", "", "", "", "", "",
177 "", "", "", "", "", "", "", "",
178 "", "", "", "", "", "", "", "",
182 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
184 return register_names
[reg_nr
];
188 sh_sh2a_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
190 static char *register_names
[] = {
191 /* general registers 0-15 */
192 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
193 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
195 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
198 /* floating point registers 25 - 40 */
199 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
200 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
203 /* 43 - 62. Banked registers. The bank number used is determined by
204 the bank register (63). */
205 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
206 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
207 "machb", "ivnb", "prb", "gbrb", "maclb",
208 /* 63: register bank number, not a real register but used to
209 communicate the register bank currently get/set. This register
210 is hidden to the user, who manipulates it using the pseudo
211 register called "bank" (67). See below. */
214 "ibcr", "ibnr", "tbr",
215 /* 67: register bank number, the user visible pseudo register. */
217 /* double precision (pseudo) 68 - 75 */
218 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
222 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
224 return register_names
[reg_nr
];
228 sh_sh2a_nofpu_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
230 static char *register_names
[] = {
231 /* general registers 0-15 */
232 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
233 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
235 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
238 /* floating point registers 25 - 40 */
239 "", "", "", "", "", "", "", "",
240 "", "", "", "", "", "", "", "",
243 /* 43 - 62. Banked registers. The bank number used is determined by
244 the bank register (63). */
245 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
246 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
247 "machb", "ivnb", "prb", "gbrb", "maclb",
248 /* 63: register bank number, not a real register but used to
249 communicate the register bank currently get/set. This register
250 is hidden to the user, who manipulates it using the pseudo
251 register called "bank" (67). See below. */
254 "ibcr", "ibnr", "tbr",
255 /* 67: register bank number, the user visible pseudo register. */
257 /* double precision (pseudo) 68 - 75 */
258 "", "", "", "", "", "", "", "",
262 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
264 return register_names
[reg_nr
];
268 sh_sh_dsp_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
270 static char *register_names
[] = {
271 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
272 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
273 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
275 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
276 "y0", "y1", "", "", "", "", "", "mod",
278 "rs", "re", "", "", "", "", "", "",
279 "", "", "", "", "", "", "", "",
280 "", "", "", "", "", "", "", "",
284 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
286 return register_names
[reg_nr
];
290 sh_sh3_dsp_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
292 static char *register_names
[] = {
293 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
294 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
295 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
297 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
298 "y0", "y1", "", "", "", "", "", "mod",
300 "rs", "re", "", "", "", "", "", "",
301 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
302 "", "", "", "", "", "", "", "",
303 "", "", "", "", "", "", "", "",
307 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
309 return register_names
[reg_nr
];
313 sh_sh4_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
315 static char *register_names
[] = {
316 /* general registers 0-15 */
317 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
318 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
320 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
323 /* floating point registers 25 - 40 */
324 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
325 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
329 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
331 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
332 "", "", "", "", "", "", "", "",
333 /* pseudo bank register. */
335 /* double precision (pseudo) 59 - 66 */
336 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
337 /* vectors (pseudo) 67 - 70 */
338 "fv0", "fv4", "fv8", "fv12",
339 /* FIXME: missing XF 71 - 86 */
340 /* FIXME: missing XD 87 - 94 */
344 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
346 return register_names
[reg_nr
];
350 sh_sh4_nofpu_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
352 static char *register_names
[] = {
353 /* general registers 0-15 */
354 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
355 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
357 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
360 /* floating point registers 25 - 40 -- not for nofpu target */
361 "", "", "", "", "", "", "", "",
362 "", "", "", "", "", "", "", "",
366 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
368 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
369 "", "", "", "", "", "", "", "",
370 /* pseudo bank register. */
372 /* double precision (pseudo) 59 - 66 -- not for nofpu target */
373 "", "", "", "", "", "", "", "",
374 /* vectors (pseudo) 67 - 70 -- not for nofpu target */
379 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
381 return register_names
[reg_nr
];
385 sh_sh4al_dsp_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
387 static char *register_names
[] = {
388 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
389 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
390 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
392 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
393 "y0", "y1", "", "", "", "", "", "mod",
395 "rs", "re", "", "", "", "", "", "",
396 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
397 "", "", "", "", "", "", "", "",
398 "", "", "", "", "", "", "", "",
402 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
404 return register_names
[reg_nr
];
407 static const unsigned char *
408 sh_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
, int *lenptr
)
410 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
411 static unsigned char breakpoint
[] = { 0xc3, 0xc3 };
413 /* For remote stub targets, trapa #20 is used. */
414 if (strcmp (target_shortname
, "remote") == 0)
416 static unsigned char big_remote_breakpoint
[] = { 0xc3, 0x20 };
417 static unsigned char little_remote_breakpoint
[] = { 0x20, 0xc3 };
419 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
421 *lenptr
= sizeof (big_remote_breakpoint
);
422 return big_remote_breakpoint
;
426 *lenptr
= sizeof (little_remote_breakpoint
);
427 return little_remote_breakpoint
;
431 *lenptr
= sizeof (breakpoint
);
435 /* Prologue looks like
439 sub <room_for_loca_vars>,r15
442 Actually it can be more complicated than this but that's it, basically.
445 #define GET_SOURCE_REG(x) (((x) >> 4) & 0xf)
446 #define GET_TARGET_REG(x) (((x) >> 8) & 0xf)
448 /* JSR @Rm 0100mmmm00001011 */
449 #define IS_JSR(x) (((x) & 0xf0ff) == 0x400b)
451 /* STS.L PR,@-r15 0100111100100010
452 r15-4-->r15, PR-->(r15) */
453 #define IS_STS(x) ((x) == 0x4f22)
455 /* STS.L MACL,@-r15 0100111100010010
456 r15-4-->r15, MACL-->(r15) */
457 #define IS_MACL_STS(x) ((x) == 0x4f12)
459 /* MOV.L Rm,@-r15 00101111mmmm0110
460 r15-4-->r15, Rm-->(R15) */
461 #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
463 /* MOV r15,r14 0110111011110011
465 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
467 /* ADD #imm,r15 01111111iiiiiiii
469 #define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00)
471 #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
472 #define IS_SHLL_R3(x) ((x) == 0x4300)
474 /* ADD r3,r15 0011111100111100
476 #define IS_ADD_R3SP(x) ((x) == 0x3f3c)
478 /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
479 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
480 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
481 /* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to
482 make this entirely clear. */
483 /* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */
484 #define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b)
486 /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */
487 #define IS_MOV_ARG_TO_REG(x) \
488 (((x) & 0xf00f) == 0x6003 && \
489 ((x) & 0x00f0) >= 0x0040 && \
490 ((x) & 0x00f0) <= 0x0070)
491 /* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */
492 #define IS_MOV_ARG_TO_IND_R14(x) \
493 (((x) & 0xff0f) == 0x2e02 && \
494 ((x) & 0x00f0) >= 0x0040 && \
495 ((x) & 0x00f0) <= 0x0070)
496 /* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */
497 #define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \
498 (((x) & 0xff00) == 0x1e00 && \
499 ((x) & 0x00f0) >= 0x0040 && \
500 ((x) & 0x00f0) <= 0x0070)
502 /* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */
503 #define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000)
504 /* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */
505 #define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000)
506 /* MOVI20 #imm20,Rn 0000nnnniiii0000 */
507 #define IS_MOVI20(x) (((x) & 0xf00f) == 0x0000)
508 /* SUB Rn,R15 00111111nnnn1000 */
509 #define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08)
511 #define FPSCR_SZ (1 << 20)
513 /* The following instructions are used for epilogue testing. */
514 #define IS_RESTORE_FP(x) ((x) == 0x6ef6)
515 #define IS_RTS(x) ((x) == 0x000b)
516 #define IS_LDS(x) ((x) == 0x4f26)
517 #define IS_MACL_LDS(x) ((x) == 0x4f16)
518 #define IS_MOV_FP_SP(x) ((x) == 0x6fe3)
519 #define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c)
520 #define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00)
523 sh_analyze_prologue (CORE_ADDR pc
, CORE_ADDR current_pc
,
524 struct sh_frame_cache
*cache
, ULONGEST fpscr
)
531 int reg
, sav_reg
= -1;
533 if (pc
>= current_pc
)
537 for (opc
= pc
+ (2 * 28); pc
< opc
; pc
+= 2)
539 inst
= read_memory_unsigned_integer (pc
, 2);
540 /* See where the registers will be saved to */
543 cache
->saved_regs
[GET_SOURCE_REG (inst
)] = cache
->sp_offset
;
544 cache
->sp_offset
+= 4;
546 else if (IS_STS (inst
))
548 cache
->saved_regs
[PR_REGNUM
] = cache
->sp_offset
;
549 cache
->sp_offset
+= 4;
551 else if (IS_MACL_STS (inst
))
553 cache
->saved_regs
[MACL_REGNUM
] = cache
->sp_offset
;
554 cache
->sp_offset
+= 4;
556 else if (IS_MOV_R3 (inst
))
558 r3_val
= ((inst
& 0xff) ^ 0x80) - 0x80;
560 else if (IS_SHLL_R3 (inst
))
564 else if (IS_ADD_R3SP (inst
))
566 cache
->sp_offset
+= -r3_val
;
568 else if (IS_ADD_IMM_SP (inst
))
570 offset
= ((inst
& 0xff) ^ 0x80) - 0x80;
571 cache
->sp_offset
-= offset
;
573 else if (IS_MOVW_PCREL_TO_REG (inst
))
577 reg
= GET_TARGET_REG (inst
);
581 offset
= (inst
& 0xff) << 1;
583 read_memory_integer ((pc
+ 4) + offset
, 2);
587 else if (IS_MOVL_PCREL_TO_REG (inst
))
591 reg
= GET_TARGET_REG (inst
);
595 offset
= (inst
& 0xff) << 2;
597 read_memory_integer (((pc
& 0xfffffffc) + 4) + offset
, 4);
601 else if (IS_MOVI20 (inst
))
605 reg
= GET_TARGET_REG (inst
);
609 sav_offset
= GET_SOURCE_REG (inst
) << 16;
610 /* MOVI20 is a 32 bit instruction! */
612 sav_offset
|= read_memory_unsigned_integer (pc
, 2);
613 /* Now sav_offset contains an unsigned 20 bit value.
614 It must still get sign extended. */
615 if (sav_offset
& 0x00080000)
616 sav_offset
|= 0xfff00000;
620 else if (IS_SUB_REG_FROM_SP (inst
))
622 reg
= GET_SOURCE_REG (inst
);
623 if (sav_reg
> 0 && reg
== sav_reg
)
627 cache
->sp_offset
+= sav_offset
;
629 else if (IS_FPUSH (inst
))
631 if (fpscr
& FPSCR_SZ
)
633 cache
->sp_offset
+= 8;
637 cache
->sp_offset
+= 4;
640 else if (IS_MOV_SP_FP (inst
))
643 /* At this point, only allow argument register moves to other
644 registers or argument register moves to @(X,fp) which are
645 moving the register arguments onto the stack area allocated
646 by a former add somenumber to SP call. Don't allow moving
647 to an fp indirect address above fp + cache->sp_offset. */
649 for (opc
= pc
+ 12; pc
< opc
; pc
+= 2)
651 inst
= read_memory_integer (pc
, 2);
652 if (IS_MOV_ARG_TO_IND_R14 (inst
))
654 reg
= GET_SOURCE_REG (inst
);
655 if (cache
->sp_offset
> 0)
656 cache
->saved_regs
[reg
] = cache
->sp_offset
;
658 else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst
))
660 reg
= GET_SOURCE_REG (inst
);
661 offset
= (inst
& 0xf) * 4;
662 if (cache
->sp_offset
> offset
)
663 cache
->saved_regs
[reg
] = cache
->sp_offset
- offset
;
665 else if (IS_MOV_ARG_TO_REG (inst
))
672 else if (IS_JSR (inst
))
674 /* We have found a jsr that has been scheduled into the prologue.
675 If we continue the scan and return a pc someplace after this,
676 then setting a breakpoint on this function will cause it to
677 appear to be called after the function it is calling via the
678 jsr, which will be very confusing. Most likely the next
679 instruction is going to be IS_MOV_SP_FP in the delay slot. If
680 so, note that before returning the current pc. */
681 inst
= read_memory_integer (pc
+ 2, 2);
682 if (IS_MOV_SP_FP (inst
))
686 #if 0 /* This used to just stop when it found an instruction that
687 was not considered part of the prologue. Now, we just
688 keep going looking for likely instructions. */
697 /* Skip any prologue before the guts of a function */
699 /* Skip the prologue using the debug information. If this fails we'll
700 fall back on the 'guess' method below. */
702 after_prologue (CORE_ADDR pc
)
704 struct symtab_and_line sal
;
705 CORE_ADDR func_addr
, func_end
;
707 /* If we can not find the symbol in the partial symbol table, then
708 there is no hope we can determine the function's start address
710 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
713 /* Get the line associated with FUNC_ADDR. */
714 sal
= find_pc_line (func_addr
, 0);
716 /* There are only two cases to consider. First, the end of the source line
717 is within the function bounds. In that case we return the end of the
718 source line. Second is the end of the source line extends beyond the
719 bounds of the current function. We need to use the slow code to
720 examine instructions in that case. */
721 if (sal
.end
< func_end
)
728 sh_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
731 struct sh_frame_cache cache
;
733 /* See if we can determine the end of the prologue via the symbol table.
734 If so, then return either PC, or the PC after the prologue, whichever
736 pc
= after_prologue (start_pc
);
738 /* If after_prologue returned a useful address, then use it. Else
739 fall back on the instruction skipping code. */
741 return max (pc
, start_pc
);
743 cache
.sp_offset
= -4;
744 pc
= sh_analyze_prologue (start_pc
, (CORE_ADDR
) -1, &cache
, 0);
753 Aggregate types not bigger than 8 bytes that have the same size and
754 alignment as one of the integer scalar types are returned in the
755 same registers as the integer type they match.
757 For example, a 2-byte aligned structure with size 2 bytes has the
758 same size and alignment as a short int, and will be returned in R0.
759 A 4-byte aligned structure with size 8 bytes has the same size and
760 alignment as a long long int, and will be returned in R0 and R1.
762 When an aggregate type is returned in R0 and R1, R0 contains the
763 first four bytes of the aggregate, and R1 contains the
764 remainder. If the size of the aggregate type is not a multiple of 4
765 bytes, the aggregate is tail-padded up to a multiple of 4
766 bytes. The value of the padding is undefined. For little-endian
767 targets the padding will appear at the most significant end of the
768 last element, for big-endian targets the padding appears at the
769 least significant end of the last element.
771 All other aggregate types are returned by address. The caller
772 function passes the address of an area large enough to hold the
773 aggregate value in R2. The called function stores the result in
776 To reiterate, structs smaller than 8 bytes could also be returned
777 in memory, if they don't pass the "same size and alignment as an
782 struct s { char c[3]; } wibble;
783 struct s foo(void) { return wibble; }
785 the return value from foo() will be in memory, not
786 in R0, because there is no 3-byte integer type.
790 struct s { char c[2]; } wibble;
791 struct s foo(void) { return wibble; }
793 because a struct containing two chars has alignment 1, that matches
794 type char, but size 2, that matches type short. There's no integer
795 type that has alignment 1 and size 2, so the struct is returned in
801 sh_use_struct_convention (int renesas_abi
, struct type
*type
)
803 int len
= TYPE_LENGTH (type
);
804 int nelem
= TYPE_NFIELDS (type
);
806 /* The Renesas ABI returns aggregate types always on stack. */
807 if (renesas_abi
&& (TYPE_CODE (type
) == TYPE_CODE_STRUCT
808 || TYPE_CODE (type
) == TYPE_CODE_UNION
))
811 /* Non-power of 2 length types and types bigger than 8 bytes (which don't
812 fit in two registers anyway) use struct convention. */
813 if (len
!= 1 && len
!= 2 && len
!= 4 && len
!= 8)
816 /* Scalar types and aggregate types with exactly one field are aligned
817 by definition. They are returned in registers. */
821 /* If the first field in the aggregate has the same length as the entire
822 aggregate type, the type is returned in registers. */
823 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, 0)) == len
)
826 /* If the size of the aggregate is 8 bytes and the first field is
827 of size 4 bytes its alignment is equal to long long's alignment,
828 so it's returned in registers. */
829 if (len
== 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type
, 0)) == 4)
832 /* Otherwise use struct convention. */
837 sh_use_struct_convention_nofpu (int renesas_abi
, struct type
*type
)
839 /* The Renesas ABI returns long longs/doubles etc. always on stack. */
840 if (renesas_abi
&& TYPE_NFIELDS (type
) == 0 && TYPE_LENGTH (type
) >= 8)
842 return sh_use_struct_convention (renesas_abi
, type
);
846 sh_frame_align (struct gdbarch
*ignore
, CORE_ADDR sp
)
851 /* Function: push_dummy_call (formerly push_arguments)
852 Setup the function arguments for calling a function in the inferior.
854 On the Renesas SH architecture, there are four registers (R4 to R7)
855 which are dedicated for passing function arguments. Up to the first
856 four arguments (depending on size) may go into these registers.
857 The rest go on the stack.
859 MVS: Except on SH variants that have floating point registers.
860 In that case, float and double arguments are passed in the same
861 manner, but using FP registers instead of GP registers.
863 Arguments that are smaller than 4 bytes will still take up a whole
864 register or a whole 32-bit word on the stack, and will be
865 right-justified in the register or the stack word. This includes
866 chars, shorts, and small aggregate types.
868 Arguments that are larger than 4 bytes may be split between two or
869 more registers. If there are not enough registers free, an argument
870 may be passed partly in a register (or registers), and partly on the
871 stack. This includes doubles, long longs, and larger aggregates.
872 As far as I know, there is no upper limit to the size of aggregates
873 that will be passed in this way; in other words, the convention of
874 passing a pointer to a large aggregate instead of a copy is not used.
876 MVS: The above appears to be true for the SH variants that do not
877 have an FPU, however those that have an FPU appear to copy the
878 aggregate argument onto the stack (and not place it in registers)
879 if it is larger than 16 bytes (four GP registers).
881 An exceptional case exists for struct arguments (and possibly other
882 aggregates such as arrays) if the size is larger than 4 bytes but
883 not a multiple of 4 bytes. In this case the argument is never split
884 between the registers and the stack, but instead is copied in its
885 entirety onto the stack, AND also copied into as many registers as
886 there is room for. In other words, space in registers permitting,
887 two copies of the same argument are passed in. As far as I can tell,
888 only the one on the stack is used, although that may be a function
889 of the level of compiler optimization. I suspect this is a compiler
890 bug. Arguments of these odd sizes are left-justified within the
891 word (as opposed to arguments smaller than 4 bytes, which are
894 If the function is to return an aggregate type such as a struct, it
895 is either returned in the normal return value register R0 (if its
896 size is no greater than one byte), or else the caller must allocate
897 space into which the callee will copy the return value (if the size
898 is greater than one byte). In this case, a pointer to the return
899 value location is passed into the callee in register R2, which does
900 not displace any of the other arguments passed in via registers R4
903 /* Helper function to justify value in register according to endianess. */
905 sh_justify_value_in_reg (struct gdbarch
*gdbarch
, struct value
*val
, int len
)
907 static char valbuf
[4];
909 memset (valbuf
, 0, sizeof (valbuf
));
912 /* value gets right-justified in the register or stack word */
913 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
914 memcpy (valbuf
+ (4 - len
), (char *) value_contents (val
), len
);
916 memcpy (valbuf
, (char *) value_contents (val
), len
);
919 return (char *) value_contents (val
);
922 /* Helper function to eval number of bytes to allocate on stack. */
924 sh_stack_allocsize (int nargs
, struct value
**args
)
928 stack_alloc
+= ((TYPE_LENGTH (value_type (args
[nargs
])) + 3) & ~3);
932 /* Helper functions for getting the float arguments right. Registers usage
933 depends on the ABI and the endianess. The comments should enlighten how
934 it's intended to work. */
936 /* This array stores which of the float arg registers are already in use. */
937 static int flt_argreg_array
[FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
+ 1];
939 /* This function just resets the above array to "no reg used so far". */
941 sh_init_flt_argreg (void)
943 memset (flt_argreg_array
, 0, sizeof flt_argreg_array
);
946 /* This function returns the next register to use for float arg passing.
947 It returns either a valid value between FLOAT_ARG0_REGNUM and
948 FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns
949 FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available.
951 Note that register number 0 in flt_argreg_array corresponds with the
952 real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is
953 29) the parity of the register number is preserved, which is important
954 for the double register passing test (see the "argreg & 1" test below). */
956 sh_next_flt_argreg (struct gdbarch
*gdbarch
, int len
, struct type
*func_type
)
960 /* First search for the next free register. */
961 for (argreg
= 0; argreg
<= FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
;
963 if (!flt_argreg_array
[argreg
])
966 /* No register left? */
967 if (argreg
> FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
)
968 return FLOAT_ARGLAST_REGNUM
+ 1;
972 /* Doubles are always starting in a even register number. */
975 /* In gcc ABI, the skipped register is lost for further argument
976 passing now. Not so in Renesas ABI. */
977 if (!sh_is_renesas_calling_convention (func_type
))
978 flt_argreg_array
[argreg
] = 1;
982 /* No register left? */
983 if (argreg
> FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
)
984 return FLOAT_ARGLAST_REGNUM
+ 1;
986 /* Also mark the next register as used. */
987 flt_argreg_array
[argreg
+ 1] = 1;
989 else if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
990 && !sh_is_renesas_calling_convention (func_type
))
992 /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */
993 if (!flt_argreg_array
[argreg
+ 1])
996 flt_argreg_array
[argreg
] = 1;
997 return FLOAT_ARG0_REGNUM
+ argreg
;
1000 /* Helper function which figures out, if a type is treated like a float type.
1002 The FPU ABIs have a special way how to treat types as float types.
1003 Structures with exactly one member, which is of type float or double, are
1004 treated exactly as the base types float or double:
1014 are handled the same way as just
1020 As a result, arguments of these struct types are pushed into floating point
1021 registers exactly as floats or doubles, using the same decision algorithm.
1023 The same is valid if these types are used as function return types. The
1024 above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1
1025 or even using struct convention as it is for other structs. */
1028 sh_treat_as_flt_p (struct type
*type
)
1030 int len
= TYPE_LENGTH (type
);
1032 /* Ordinary float types are obviously treated as float. */
1033 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1035 /* Otherwise non-struct types are not treated as float. */
1036 if (TYPE_CODE (type
) != TYPE_CODE_STRUCT
)
1038 /* Otherwise structs with more than one memeber are not treated as float. */
1039 if (TYPE_NFIELDS (type
) != 1)
1041 /* Otherwise if the type of that member is float, the whole type is
1042 treated as float. */
1043 if (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0)) == TYPE_CODE_FLT
)
1045 /* Otherwise it's not treated as float. */
1050 sh_push_dummy_call_fpu (struct gdbarch
*gdbarch
,
1051 struct value
*function
,
1052 struct regcache
*regcache
,
1053 CORE_ADDR bp_addr
, int nargs
,
1054 struct value
**args
,
1055 CORE_ADDR sp
, int struct_return
,
1056 CORE_ADDR struct_addr
)
1058 int stack_offset
= 0;
1059 int argreg
= ARG0_REGNUM
;
1062 struct type
*func_type
= value_type (function
);
1066 int len
, reg_size
= 0;
1067 int pass_on_stack
= 0;
1069 int last_reg_arg
= INT_MAX
;
1071 /* The Renesas ABI expects all varargs arguments, plus the last
1072 non-vararg argument to be on the stack, no matter how many
1073 registers have been used so far. */
1074 if (sh_is_renesas_calling_convention (func_type
)
1075 && TYPE_VARARGS (func_type
))
1076 last_reg_arg
= TYPE_NFIELDS (func_type
) - 2;
1078 /* first force sp to a 4-byte alignment */
1079 sp
= sh_frame_align (gdbarch
, sp
);
1081 /* make room on stack for args */
1082 sp
-= sh_stack_allocsize (nargs
, args
);
1084 /* Initialize float argument mechanism. */
1085 sh_init_flt_argreg ();
1087 /* Now load as many as possible of the first arguments into
1088 registers, and push the rest onto the stack. There are 16 bytes
1089 in four registers available. Loop thru args from first to last. */
1090 for (argnum
= 0; argnum
< nargs
; argnum
++)
1092 type
= value_type (args
[argnum
]);
1093 len
= TYPE_LENGTH (type
);
1094 val
= sh_justify_value_in_reg (gdbarch
, args
[argnum
], len
);
1096 /* Some decisions have to be made how various types are handled.
1097 This also differs in different ABIs. */
1100 /* Find out the next register to use for a floating point value. */
1101 treat_as_flt
= sh_treat_as_flt_p (type
);
1103 flt_argreg
= sh_next_flt_argreg (gdbarch
, len
, func_type
);
1104 /* In Renesas ABI, long longs and aggregate types are always passed
1106 else if (sh_is_renesas_calling_convention (func_type
)
1107 && ((TYPE_CODE (type
) == TYPE_CODE_INT
&& len
== 8)
1108 || TYPE_CODE (type
) == TYPE_CODE_STRUCT
1109 || TYPE_CODE (type
) == TYPE_CODE_UNION
))
1111 /* In contrast to non-FPU CPUs, arguments are never split between
1112 registers and stack. If an argument doesn't fit in the remaining
1113 registers it's always pushed entirely on the stack. */
1114 else if (len
> ((ARGLAST_REGNUM
- argreg
+ 1) * 4))
1119 if ((treat_as_flt
&& flt_argreg
> FLOAT_ARGLAST_REGNUM
)
1120 || (!treat_as_flt
&& (argreg
> ARGLAST_REGNUM
1122 || argnum
> last_reg_arg
)
1124 /* The data goes entirely on the stack, 4-byte aligned. */
1125 reg_size
= (len
+ 3) & ~3;
1126 write_memory (sp
+ stack_offset
, val
, reg_size
);
1127 stack_offset
+= reg_size
;
1129 else if (treat_as_flt
&& flt_argreg
<= FLOAT_ARGLAST_REGNUM
)
1131 /* Argument goes in a float argument register. */
1132 reg_size
= register_size (gdbarch
, flt_argreg
);
1133 regval
= extract_unsigned_integer (val
, reg_size
);
1134 /* In little endian mode, float types taking two registers
1135 (doubles on sh4, long doubles on sh2e, sh3e and sh4) must
1136 be stored swapped in the argument registers. The below
1137 code first writes the first 32 bits in the next but one
1138 register, increments the val and len values accordingly
1139 and then proceeds as normal by writing the second 32 bits
1140 into the next register. */
1141 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
1142 && TYPE_LENGTH (type
) == 2 * reg_size
)
1144 regcache_cooked_write_unsigned (regcache
, flt_argreg
+ 1,
1148 regval
= extract_unsigned_integer (val
, reg_size
);
1150 regcache_cooked_write_unsigned (regcache
, flt_argreg
++, regval
);
1152 else if (!treat_as_flt
&& argreg
<= ARGLAST_REGNUM
)
1154 /* there's room in a register */
1155 reg_size
= register_size (gdbarch
, argreg
);
1156 regval
= extract_unsigned_integer (val
, reg_size
);
1157 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
1159 /* Store the value one register at a time or in one step on stack. */
1167 if (sh_is_renesas_calling_convention (func_type
))
1168 /* If the function uses the Renesas ABI, subtract another 4 bytes from
1169 the stack and store the struct return address there. */
1170 write_memory_unsigned_integer (sp
-= 4, 4, struct_addr
);
1172 /* Using the gcc ABI, the "struct return pointer" pseudo-argument has
1173 its own dedicated register. */
1174 regcache_cooked_write_unsigned (regcache
,
1175 STRUCT_RETURN_REGNUM
, struct_addr
);
1178 /* Store return address. */
1179 regcache_cooked_write_unsigned (regcache
, PR_REGNUM
, bp_addr
);
1181 /* Update stack pointer. */
1182 regcache_cooked_write_unsigned (regcache
,
1183 gdbarch_sp_regnum (gdbarch
), sp
);
1189 sh_push_dummy_call_nofpu (struct gdbarch
*gdbarch
,
1190 struct value
*function
,
1191 struct regcache
*regcache
,
1193 int nargs
, struct value
**args
,
1194 CORE_ADDR sp
, int struct_return
,
1195 CORE_ADDR struct_addr
)
1197 int stack_offset
= 0;
1198 int argreg
= ARG0_REGNUM
;
1200 struct type
*func_type
= value_type (function
);
1204 int len
, reg_size
= 0;
1205 int pass_on_stack
= 0;
1206 int last_reg_arg
= INT_MAX
;
1208 /* The Renesas ABI expects all varargs arguments, plus the last
1209 non-vararg argument to be on the stack, no matter how many
1210 registers have been used so far. */
1211 if (sh_is_renesas_calling_convention (func_type
)
1212 && TYPE_VARARGS (func_type
))
1213 last_reg_arg
= TYPE_NFIELDS (func_type
) - 2;
1215 /* first force sp to a 4-byte alignment */
1216 sp
= sh_frame_align (gdbarch
, sp
);
1218 /* make room on stack for args */
1219 sp
-= sh_stack_allocsize (nargs
, args
);
1221 /* Now load as many as possible of the first arguments into
1222 registers, and push the rest onto the stack. There are 16 bytes
1223 in four registers available. Loop thru args from first to last. */
1224 for (argnum
= 0; argnum
< nargs
; argnum
++)
1226 type
= value_type (args
[argnum
]);
1227 len
= TYPE_LENGTH (type
);
1228 val
= sh_justify_value_in_reg (gdbarch
, args
[argnum
], len
);
1230 /* Some decisions have to be made how various types are handled.
1231 This also differs in different ABIs. */
1233 /* Renesas ABI pushes doubles and long longs entirely on stack.
1234 Same goes for aggregate types. */
1235 if (sh_is_renesas_calling_convention (func_type
)
1236 && ((TYPE_CODE (type
) == TYPE_CODE_INT
&& len
>= 8)
1237 || (TYPE_CODE (type
) == TYPE_CODE_FLT
&& len
>= 8)
1238 || TYPE_CODE (type
) == TYPE_CODE_STRUCT
1239 || TYPE_CODE (type
) == TYPE_CODE_UNION
))
1243 if (argreg
> ARGLAST_REGNUM
|| pass_on_stack
1244 || argnum
> last_reg_arg
)
1246 /* The remainder of the data goes entirely on the stack,
1248 reg_size
= (len
+ 3) & ~3;
1249 write_memory (sp
+ stack_offset
, val
, reg_size
);
1250 stack_offset
+= reg_size
;
1252 else if (argreg
<= ARGLAST_REGNUM
)
1254 /* there's room in a register */
1255 reg_size
= register_size (gdbarch
, argreg
);
1256 regval
= extract_unsigned_integer (val
, reg_size
);
1257 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
1259 /* Store the value reg_size bytes at a time. This means that things
1260 larger than reg_size bytes may go partly in registers and partly
1269 if (sh_is_renesas_calling_convention (func_type
))
1270 /* If the function uses the Renesas ABI, subtract another 4 bytes from
1271 the stack and store the struct return address there. */
1272 write_memory_unsigned_integer (sp
-= 4, 4, struct_addr
);
1274 /* Using the gcc ABI, the "struct return pointer" pseudo-argument has
1275 its own dedicated register. */
1276 regcache_cooked_write_unsigned (regcache
,
1277 STRUCT_RETURN_REGNUM
, struct_addr
);
1280 /* Store return address. */
1281 regcache_cooked_write_unsigned (regcache
, PR_REGNUM
, bp_addr
);
1283 /* Update stack pointer. */
1284 regcache_cooked_write_unsigned (regcache
,
1285 gdbarch_sp_regnum (gdbarch
), sp
);
1290 /* Find a function's return value in the appropriate registers (in
1291 regbuf), and copy it into valbuf. Extract from an array REGBUF
1292 containing the (raw) register state a function return value of type
1293 TYPE, and copy that, in virtual format, into VALBUF. */
1295 sh_extract_return_value_nofpu (struct type
*type
, struct regcache
*regcache
,
1298 int len
= TYPE_LENGTH (type
);
1299 int return_register
= R0_REGNUM
;
1306 regcache_cooked_read_unsigned (regcache
, R0_REGNUM
, &c
);
1307 store_unsigned_integer (valbuf
, len
, c
);
1311 int i
, regnum
= R0_REGNUM
;
1312 for (i
= 0; i
< len
; i
+= 4)
1313 regcache_raw_read (regcache
, regnum
++, (char *) valbuf
+ i
);
1316 error (_("bad size for return value"));
1320 sh_extract_return_value_fpu (struct type
*type
, struct regcache
*regcache
,
1323 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1324 if (sh_treat_as_flt_p (type
))
1326 int len
= TYPE_LENGTH (type
);
1327 int i
, regnum
= gdbarch_fp0_regnum (gdbarch
);
1328 for (i
= 0; i
< len
; i
+= 4)
1329 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
1330 regcache_raw_read (regcache
, regnum
++, (char *) valbuf
+ len
- 4 - i
);
1332 regcache_raw_read (regcache
, regnum
++, (char *) valbuf
+ i
);
1335 sh_extract_return_value_nofpu (type
, regcache
, valbuf
);
1338 /* Write into appropriate registers a function return value
1339 of type TYPE, given in virtual format.
1340 If the architecture is sh4 or sh3e, store a function's return value
1341 in the R0 general register or in the FP0 floating point register,
1342 depending on the type of the return value. In all the other cases
1343 the result is stored in r0, left-justified. */
1345 sh_store_return_value_nofpu (struct type
*type
, struct regcache
*regcache
,
1349 int len
= TYPE_LENGTH (type
);
1353 val
= extract_unsigned_integer (valbuf
, len
);
1354 regcache_cooked_write_unsigned (regcache
, R0_REGNUM
, val
);
1358 int i
, regnum
= R0_REGNUM
;
1359 for (i
= 0; i
< len
; i
+= 4)
1360 regcache_raw_write (regcache
, regnum
++, (char *) valbuf
+ i
);
1365 sh_store_return_value_fpu (struct type
*type
, struct regcache
*regcache
,
1368 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1369 if (sh_treat_as_flt_p (type
))
1371 int len
= TYPE_LENGTH (type
);
1372 int i
, regnum
= gdbarch_fp0_regnum (gdbarch
);
1373 for (i
= 0; i
< len
; i
+= 4)
1374 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
1375 regcache_raw_write (regcache
, regnum
++,
1376 (char *) valbuf
+ len
- 4 - i
);
1378 regcache_raw_write (regcache
, regnum
++, (char *) valbuf
+ i
);
1381 sh_store_return_value_nofpu (type
, regcache
, valbuf
);
1384 static enum return_value_convention
1385 sh_return_value_nofpu (struct gdbarch
*gdbarch
, struct type
*func_type
,
1386 struct type
*type
, struct regcache
*regcache
,
1387 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1389 if (sh_use_struct_convention_nofpu (
1390 sh_is_renesas_calling_convention (func_type
), type
))
1391 return RETURN_VALUE_STRUCT_CONVENTION
;
1393 sh_store_return_value_nofpu (type
, regcache
, writebuf
);
1395 sh_extract_return_value_nofpu (type
, regcache
, readbuf
);
1396 return RETURN_VALUE_REGISTER_CONVENTION
;
1399 static enum return_value_convention
1400 sh_return_value_fpu (struct gdbarch
*gdbarch
, struct type
*func_type
,
1401 struct type
*type
, struct regcache
*regcache
,
1402 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1404 if (sh_use_struct_convention (
1405 sh_is_renesas_calling_convention (func_type
), type
))
1406 return RETURN_VALUE_STRUCT_CONVENTION
;
1408 sh_store_return_value_fpu (type
, regcache
, writebuf
);
1410 sh_extract_return_value_fpu (type
, regcache
, readbuf
);
1411 return RETURN_VALUE_REGISTER_CONVENTION
;
1414 /* Print the registers in a form similar to the E7000 */
1417 sh_generic_show_regs (struct frame_info
*frame
)
1420 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1421 paddr (get_frame_register_unsigned (frame
,
1423 (get_frame_arch (frame
)))),
1424 (long) get_frame_register_unsigned (frame
, SR_REGNUM
),
1425 (long) get_frame_register_unsigned (frame
, PR_REGNUM
),
1426 (long) get_frame_register_unsigned (frame
, MACH_REGNUM
));
1429 (" GBR %08lx VBR %08lx MACL %08lx\n",
1430 (long) get_frame_register_unsigned (frame
, GBR_REGNUM
),
1431 (long) get_frame_register_unsigned (frame
, VBR_REGNUM
),
1432 (long) get_frame_register_unsigned (frame
, MACL_REGNUM
));
1435 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1436 (long) get_frame_register_unsigned (frame
, 0),
1437 (long) get_frame_register_unsigned (frame
, 1),
1438 (long) get_frame_register_unsigned (frame
, 2),
1439 (long) get_frame_register_unsigned (frame
, 3),
1440 (long) get_frame_register_unsigned (frame
, 4),
1441 (long) get_frame_register_unsigned (frame
, 5),
1442 (long) get_frame_register_unsigned (frame
, 6),
1443 (long) get_frame_register_unsigned (frame
, 7));
1445 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1446 (long) get_frame_register_unsigned (frame
, 8),
1447 (long) get_frame_register_unsigned (frame
, 9),
1448 (long) get_frame_register_unsigned (frame
, 10),
1449 (long) get_frame_register_unsigned (frame
, 11),
1450 (long) get_frame_register_unsigned (frame
, 12),
1451 (long) get_frame_register_unsigned (frame
, 13),
1452 (long) get_frame_register_unsigned (frame
, 14),
1453 (long) get_frame_register_unsigned (frame
, 15));
1457 sh3_show_regs (struct frame_info
*frame
)
1460 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1461 paddr (get_frame_register_unsigned (frame
,
1463 (get_frame_arch (frame
)))),
1464 (long) get_frame_register_unsigned (frame
, SR_REGNUM
),
1465 (long) get_frame_register_unsigned (frame
, PR_REGNUM
),
1466 (long) get_frame_register_unsigned (frame
, MACH_REGNUM
));
1469 (" GBR %08lx VBR %08lx MACL %08lx\n",
1470 (long) get_frame_register_unsigned (frame
, GBR_REGNUM
),
1471 (long) get_frame_register_unsigned (frame
, VBR_REGNUM
),
1472 (long) get_frame_register_unsigned (frame
, MACL_REGNUM
));
1474 (" SSR %08lx SPC %08lx\n",
1475 (long) get_frame_register_unsigned (frame
, SSR_REGNUM
),
1476 (long) get_frame_register_unsigned (frame
, SPC_REGNUM
));
1479 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1480 (long) get_frame_register_unsigned (frame
, 0),
1481 (long) get_frame_register_unsigned (frame
, 1),
1482 (long) get_frame_register_unsigned (frame
, 2),
1483 (long) get_frame_register_unsigned (frame
, 3),
1484 (long) get_frame_register_unsigned (frame
, 4),
1485 (long) get_frame_register_unsigned (frame
, 5),
1486 (long) get_frame_register_unsigned (frame
, 6),
1487 (long) get_frame_register_unsigned (frame
, 7));
1489 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1490 (long) get_frame_register_unsigned (frame
, 8),
1491 (long) get_frame_register_unsigned (frame
, 9),
1492 (long) get_frame_register_unsigned (frame
, 10),
1493 (long) get_frame_register_unsigned (frame
, 11),
1494 (long) get_frame_register_unsigned (frame
, 12),
1495 (long) get_frame_register_unsigned (frame
, 13),
1496 (long) get_frame_register_unsigned (frame
, 14),
1497 (long) get_frame_register_unsigned (frame
, 15));
1501 sh2e_show_regs (struct frame_info
*frame
)
1503 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1505 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1506 paddr (get_frame_register_unsigned (frame
,
1507 gdbarch_pc_regnum (gdbarch
))),
1508 (long) get_frame_register_unsigned (frame
, SR_REGNUM
),
1509 (long) get_frame_register_unsigned (frame
, PR_REGNUM
),
1510 (long) get_frame_register_unsigned (frame
, MACH_REGNUM
));
1513 (" GBR %08lx VBR %08lx MACL %08lx\n",
1514 (long) get_frame_register_unsigned (frame
, GBR_REGNUM
),
1515 (long) get_frame_register_unsigned (frame
, VBR_REGNUM
),
1516 (long) get_frame_register_unsigned (frame
, MACL_REGNUM
));
1518 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1519 (long) get_frame_register_unsigned (frame
, SSR_REGNUM
),
1520 (long) get_frame_register_unsigned (frame
, SPC_REGNUM
),
1521 (long) get_frame_register_unsigned (frame
, FPUL_REGNUM
),
1522 (long) get_frame_register_unsigned (frame
, FPSCR_REGNUM
));
1525 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1526 (long) get_frame_register_unsigned (frame
, 0),
1527 (long) get_frame_register_unsigned (frame
, 1),
1528 (long) get_frame_register_unsigned (frame
, 2),
1529 (long) get_frame_register_unsigned (frame
, 3),
1530 (long) get_frame_register_unsigned (frame
, 4),
1531 (long) get_frame_register_unsigned (frame
, 5),
1532 (long) get_frame_register_unsigned (frame
, 6),
1533 (long) get_frame_register_unsigned (frame
, 7));
1535 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1536 (long) get_frame_register_unsigned (frame
, 8),
1537 (long) get_frame_register_unsigned (frame
, 9),
1538 (long) get_frame_register_unsigned (frame
, 10),
1539 (long) get_frame_register_unsigned (frame
, 11),
1540 (long) get_frame_register_unsigned (frame
, 12),
1541 (long) get_frame_register_unsigned (frame
, 13),
1542 (long) get_frame_register_unsigned (frame
, 14),
1543 (long) get_frame_register_unsigned (frame
, 15));
1546 ("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1547 (long) get_frame_register_unsigned
1548 (frame
, gdbarch_fp0_regnum (gdbarch
) + 0),
1549 (long) get_frame_register_unsigned
1550 (frame
, gdbarch_fp0_regnum (gdbarch
) + 1),
1551 (long) get_frame_register_unsigned
1552 (frame
, gdbarch_fp0_regnum (gdbarch
) + 2),
1553 (long) get_frame_register_unsigned
1554 (frame
, gdbarch_fp0_regnum (gdbarch
) + 3),
1555 (long) get_frame_register_unsigned
1556 (frame
, gdbarch_fp0_regnum (gdbarch
) + 4),
1557 (long) get_frame_register_unsigned
1558 (frame
, gdbarch_fp0_regnum (gdbarch
) + 5),
1559 (long) get_frame_register_unsigned
1560 (frame
, gdbarch_fp0_regnum (gdbarch
) + 6),
1561 (long) get_frame_register_unsigned
1562 (frame
, gdbarch_fp0_regnum (gdbarch
) + 7));
1564 ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1565 (long) get_frame_register_unsigned
1566 (frame
, gdbarch_fp0_regnum (gdbarch
) + 8),
1567 (long) get_frame_register_unsigned
1568 (frame
, gdbarch_fp0_regnum (gdbarch
) + 9),
1569 (long) get_frame_register_unsigned
1570 (frame
, gdbarch_fp0_regnum (gdbarch
) + 10),
1571 (long) get_frame_register_unsigned
1572 (frame
, gdbarch_fp0_regnum (gdbarch
) + 11),
1573 (long) get_frame_register_unsigned
1574 (frame
, gdbarch_fp0_regnum (gdbarch
) + 12),
1575 (long) get_frame_register_unsigned
1576 (frame
, gdbarch_fp0_regnum (gdbarch
) + 13),
1577 (long) get_frame_register_unsigned
1578 (frame
, gdbarch_fp0_regnum (gdbarch
) + 14),
1579 (long) get_frame_register_unsigned
1580 (frame
, gdbarch_fp0_regnum (gdbarch
) + 15));
1584 sh2a_show_regs (struct frame_info
*frame
)
1586 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1587 int pr
= get_frame_register_unsigned (frame
, FPSCR_REGNUM
) & 0x80000;
1590 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1591 paddr (get_frame_register_unsigned (frame
,
1592 gdbarch_pc_regnum (gdbarch
))),
1593 (long) get_frame_register_unsigned (frame
, SR_REGNUM
),
1594 (long) get_frame_register_unsigned (frame
, PR_REGNUM
),
1595 (long) get_frame_register_unsigned (frame
, MACH_REGNUM
));
1598 (" GBR %08lx VBR %08lx TBR %08lx MACL %08lx\n",
1599 (long) get_frame_register_unsigned (frame
, GBR_REGNUM
),
1600 (long) get_frame_register_unsigned (frame
, VBR_REGNUM
),
1601 (long) get_frame_register_unsigned (frame
, TBR_REGNUM
),
1602 (long) get_frame_register_unsigned (frame
, MACL_REGNUM
));
1604 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1605 (long) get_frame_register_unsigned (frame
, SSR_REGNUM
),
1606 (long) get_frame_register_unsigned (frame
, SPC_REGNUM
),
1607 (long) get_frame_register_unsigned (frame
, FPUL_REGNUM
),
1608 (long) get_frame_register_unsigned (frame
, FPSCR_REGNUM
));
1611 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1612 (long) get_frame_register_unsigned (frame
, 0),
1613 (long) get_frame_register_unsigned (frame
, 1),
1614 (long) get_frame_register_unsigned (frame
, 2),
1615 (long) get_frame_register_unsigned (frame
, 3),
1616 (long) get_frame_register_unsigned (frame
, 4),
1617 (long) get_frame_register_unsigned (frame
, 5),
1618 (long) get_frame_register_unsigned (frame
, 6),
1619 (long) get_frame_register_unsigned (frame
, 7));
1621 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1622 (long) get_frame_register_unsigned (frame
, 8),
1623 (long) get_frame_register_unsigned (frame
, 9),
1624 (long) get_frame_register_unsigned (frame
, 10),
1625 (long) get_frame_register_unsigned (frame
, 11),
1626 (long) get_frame_register_unsigned (frame
, 12),
1627 (long) get_frame_register_unsigned (frame
, 13),
1628 (long) get_frame_register_unsigned (frame
, 14),
1629 (long) get_frame_register_unsigned (frame
, 15));
1632 (pr
? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1633 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1634 (long) get_frame_register_unsigned
1635 (frame
, gdbarch_fp0_regnum (gdbarch
) + 0),
1636 (long) get_frame_register_unsigned
1637 (frame
, gdbarch_fp0_regnum (gdbarch
) + 1),
1638 (long) get_frame_register_unsigned
1639 (frame
, gdbarch_fp0_regnum (gdbarch
) + 2),
1640 (long) get_frame_register_unsigned
1641 (frame
, gdbarch_fp0_regnum (gdbarch
) + 3),
1642 (long) get_frame_register_unsigned
1643 (frame
, gdbarch_fp0_regnum (gdbarch
) + 4),
1644 (long) get_frame_register_unsigned
1645 (frame
, gdbarch_fp0_regnum (gdbarch
) + 5),
1646 (long) get_frame_register_unsigned
1647 (frame
, gdbarch_fp0_regnum (gdbarch
) + 6),
1648 (long) get_frame_register_unsigned
1649 (frame
, gdbarch_fp0_regnum (gdbarch
) + 7));
1651 (pr
? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1652 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1653 (long) get_frame_register_unsigned
1654 (frame
, gdbarch_fp0_regnum (gdbarch
) + 8),
1655 (long) get_frame_register_unsigned
1656 (frame
, gdbarch_fp0_regnum (gdbarch
) + 9),
1657 (long) get_frame_register_unsigned
1658 (frame
, gdbarch_fp0_regnum (gdbarch
) + 10),
1659 (long) get_frame_register_unsigned
1660 (frame
, gdbarch_fp0_regnum (gdbarch
) + 11),
1661 (long) get_frame_register_unsigned
1662 (frame
, gdbarch_fp0_regnum (gdbarch
) + 12),
1663 (long) get_frame_register_unsigned
1664 (frame
, gdbarch_fp0_regnum (gdbarch
) + 13),
1665 (long) get_frame_register_unsigned
1666 (frame
, gdbarch_fp0_regnum (gdbarch
) + 14),
1667 (long) get_frame_register_unsigned
1668 (frame
, gdbarch_fp0_regnum (gdbarch
) + 15));
1670 ("BANK=%-3d\n", (int) get_frame_register_unsigned (frame
, BANK_REGNUM
));
1672 ("R0b-R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1673 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 0),
1674 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 1),
1675 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 2),
1676 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 3),
1677 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 4),
1678 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 5),
1679 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 6),
1680 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 7));
1682 ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1683 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 8),
1684 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 9),
1685 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 10),
1686 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 11),
1687 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 12),
1688 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 13),
1689 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 14));
1691 ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n",
1692 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 15),
1693 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 16),
1694 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 17),
1695 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 18),
1696 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 19));
1700 sh2a_nofpu_show_regs (struct frame_info
*frame
)
1702 int pr
= get_frame_register_unsigned (frame
, FPSCR_REGNUM
) & 0x80000;
1705 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1706 paddr (get_frame_register_unsigned (frame
,
1708 (get_frame_arch (frame
)))),
1709 (long) get_frame_register_unsigned (frame
, SR_REGNUM
),
1710 (long) get_frame_register_unsigned (frame
, PR_REGNUM
),
1711 (long) get_frame_register_unsigned (frame
, MACH_REGNUM
));
1714 (" GBR %08lx VBR %08lx TBR %08lx MACL %08lx\n",
1715 (long) get_frame_register_unsigned (frame
, GBR_REGNUM
),
1716 (long) get_frame_register_unsigned (frame
, VBR_REGNUM
),
1717 (long) get_frame_register_unsigned (frame
, TBR_REGNUM
),
1718 (long) get_frame_register_unsigned (frame
, MACL_REGNUM
));
1720 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1721 (long) get_frame_register_unsigned (frame
, SSR_REGNUM
),
1722 (long) get_frame_register_unsigned (frame
, SPC_REGNUM
),
1723 (long) get_frame_register_unsigned (frame
, FPUL_REGNUM
),
1724 (long) get_frame_register_unsigned (frame
, FPSCR_REGNUM
));
1727 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1728 (long) get_frame_register_unsigned (frame
, 0),
1729 (long) get_frame_register_unsigned (frame
, 1),
1730 (long) get_frame_register_unsigned (frame
, 2),
1731 (long) get_frame_register_unsigned (frame
, 3),
1732 (long) get_frame_register_unsigned (frame
, 4),
1733 (long) get_frame_register_unsigned (frame
, 5),
1734 (long) get_frame_register_unsigned (frame
, 6),
1735 (long) get_frame_register_unsigned (frame
, 7));
1737 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1738 (long) get_frame_register_unsigned (frame
, 8),
1739 (long) get_frame_register_unsigned (frame
, 9),
1740 (long) get_frame_register_unsigned (frame
, 10),
1741 (long) get_frame_register_unsigned (frame
, 11),
1742 (long) get_frame_register_unsigned (frame
, 12),
1743 (long) get_frame_register_unsigned (frame
, 13),
1744 (long) get_frame_register_unsigned (frame
, 14),
1745 (long) get_frame_register_unsigned (frame
, 15));
1748 ("BANK=%-3d\n", (int) get_frame_register_unsigned (frame
, BANK_REGNUM
));
1750 ("R0b-R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1751 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 0),
1752 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 1),
1753 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 2),
1754 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 3),
1755 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 4),
1756 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 5),
1757 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 6),
1758 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 7));
1760 ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1761 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 8),
1762 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 9),
1763 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 10),
1764 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 11),
1765 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 12),
1766 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 13),
1767 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 14));
1769 ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n",
1770 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 15),
1771 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 16),
1772 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 17),
1773 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 18),
1774 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 19));
1778 sh3e_show_regs (struct frame_info
*frame
)
1780 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1782 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1783 paddr (get_frame_register_unsigned (frame
,
1784 gdbarch_pc_regnum (gdbarch
))),
1785 (long) get_frame_register_unsigned (frame
, SR_REGNUM
),
1786 (long) get_frame_register_unsigned (frame
, PR_REGNUM
),
1787 (long) get_frame_register_unsigned (frame
, MACH_REGNUM
));
1790 (" GBR %08lx VBR %08lx MACL %08lx\n",
1791 (long) get_frame_register_unsigned (frame
, GBR_REGNUM
),
1792 (long) get_frame_register_unsigned (frame
, VBR_REGNUM
),
1793 (long) get_frame_register_unsigned (frame
, MACL_REGNUM
));
1795 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1796 (long) get_frame_register_unsigned (frame
, SSR_REGNUM
),
1797 (long) get_frame_register_unsigned (frame
, SPC_REGNUM
),
1798 (long) get_frame_register_unsigned (frame
, FPUL_REGNUM
),
1799 (long) get_frame_register_unsigned (frame
, FPSCR_REGNUM
));
1802 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1803 (long) get_frame_register_unsigned (frame
, 0),
1804 (long) get_frame_register_unsigned (frame
, 1),
1805 (long) get_frame_register_unsigned (frame
, 2),
1806 (long) get_frame_register_unsigned (frame
, 3),
1807 (long) get_frame_register_unsigned (frame
, 4),
1808 (long) get_frame_register_unsigned (frame
, 5),
1809 (long) get_frame_register_unsigned (frame
, 6),
1810 (long) get_frame_register_unsigned (frame
, 7));
1812 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1813 (long) get_frame_register_unsigned (frame
, 8),
1814 (long) get_frame_register_unsigned (frame
, 9),
1815 (long) get_frame_register_unsigned (frame
, 10),
1816 (long) get_frame_register_unsigned (frame
, 11),
1817 (long) get_frame_register_unsigned (frame
, 12),
1818 (long) get_frame_register_unsigned (frame
, 13),
1819 (long) get_frame_register_unsigned (frame
, 14),
1820 (long) get_frame_register_unsigned (frame
, 15));
1823 ("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1824 (long) get_frame_register_unsigned
1825 (frame
, gdbarch_fp0_regnum (gdbarch
) + 0),
1826 (long) get_frame_register_unsigned
1827 (frame
, gdbarch_fp0_regnum (gdbarch
) + 1),
1828 (long) get_frame_register_unsigned
1829 (frame
, gdbarch_fp0_regnum (gdbarch
) + 2),
1830 (long) get_frame_register_unsigned
1831 (frame
, gdbarch_fp0_regnum (gdbarch
) + 3),
1832 (long) get_frame_register_unsigned
1833 (frame
, gdbarch_fp0_regnum (gdbarch
) + 4),
1834 (long) get_frame_register_unsigned
1835 (frame
, gdbarch_fp0_regnum (gdbarch
) + 5),
1836 (long) get_frame_register_unsigned
1837 (frame
, gdbarch_fp0_regnum (gdbarch
) + 6),
1838 (long) get_frame_register_unsigned
1839 (frame
, gdbarch_fp0_regnum (gdbarch
) + 7));
1841 ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1842 (long) get_frame_register_unsigned
1843 (frame
, gdbarch_fp0_regnum (gdbarch
) + 8),
1844 (long) get_frame_register_unsigned
1845 (frame
, gdbarch_fp0_regnum (gdbarch
) + 9),
1846 (long) get_frame_register_unsigned
1847 (frame
, gdbarch_fp0_regnum (gdbarch
) + 10),
1848 (long) get_frame_register_unsigned
1849 (frame
, gdbarch_fp0_regnum (gdbarch
) + 11),
1850 (long) get_frame_register_unsigned
1851 (frame
, gdbarch_fp0_regnum (gdbarch
) + 12),
1852 (long) get_frame_register_unsigned
1853 (frame
, gdbarch_fp0_regnum (gdbarch
) + 13),
1854 (long) get_frame_register_unsigned
1855 (frame
, gdbarch_fp0_regnum (gdbarch
) + 14),
1856 (long) get_frame_register_unsigned
1857 (frame
, gdbarch_fp0_regnum (gdbarch
) + 15));
1861 sh3_dsp_show_regs (struct frame_info
*frame
)
1864 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1865 paddr (get_frame_register_unsigned (frame
,
1867 (get_frame_arch (frame
)))),
1868 (long) get_frame_register_unsigned (frame
, SR_REGNUM
),
1869 (long) get_frame_register_unsigned (frame
, PR_REGNUM
),
1870 (long) get_frame_register_unsigned (frame
, MACH_REGNUM
));
1873 (" GBR %08lx VBR %08lx MACL %08lx\n",
1874 (long) get_frame_register_unsigned (frame
, GBR_REGNUM
),
1875 (long) get_frame_register_unsigned (frame
, VBR_REGNUM
),
1876 (long) get_frame_register_unsigned (frame
, MACL_REGNUM
));
1879 (" SSR %08lx SPC %08lx DSR %08lx\n",
1880 (long) get_frame_register_unsigned (frame
, SSR_REGNUM
),
1881 (long) get_frame_register_unsigned (frame
, SPC_REGNUM
),
1882 (long) get_frame_register_unsigned (frame
, DSR_REGNUM
));
1885 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1886 (long) get_frame_register_unsigned (frame
, 0),
1887 (long) get_frame_register_unsigned (frame
, 1),
1888 (long) get_frame_register_unsigned (frame
, 2),
1889 (long) get_frame_register_unsigned (frame
, 3),
1890 (long) get_frame_register_unsigned (frame
, 4),
1891 (long) get_frame_register_unsigned (frame
, 5),
1892 (long) get_frame_register_unsigned (frame
, 6),
1893 (long) get_frame_register_unsigned (frame
, 7));
1895 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1896 (long) get_frame_register_unsigned (frame
, 8),
1897 (long) get_frame_register_unsigned (frame
, 9),
1898 (long) get_frame_register_unsigned (frame
, 10),
1899 (long) get_frame_register_unsigned (frame
, 11),
1900 (long) get_frame_register_unsigned (frame
, 12),
1901 (long) get_frame_register_unsigned (frame
, 13),
1902 (long) get_frame_register_unsigned (frame
, 14),
1903 (long) get_frame_register_unsigned (frame
, 15));
1906 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1907 (long) get_frame_register_unsigned (frame
, A0G_REGNUM
) & 0xff,
1908 (long) get_frame_register_unsigned (frame
, A0_REGNUM
),
1909 (long) get_frame_register_unsigned (frame
, M0_REGNUM
),
1910 (long) get_frame_register_unsigned (frame
, X0_REGNUM
),
1911 (long) get_frame_register_unsigned (frame
, Y0_REGNUM
),
1912 (long) get_frame_register_unsigned (frame
, RS_REGNUM
),
1913 (long) get_frame_register_unsigned (frame
, MOD_REGNUM
));
1915 ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1916 (long) get_frame_register_unsigned (frame
, A1G_REGNUM
) & 0xff,
1917 (long) get_frame_register_unsigned (frame
, A1_REGNUM
),
1918 (long) get_frame_register_unsigned (frame
, M1_REGNUM
),
1919 (long) get_frame_register_unsigned (frame
, X1_REGNUM
),
1920 (long) get_frame_register_unsigned (frame
, Y1_REGNUM
),
1921 (long) get_frame_register_unsigned (frame
, RE_REGNUM
));
1925 sh4_show_regs (struct frame_info
*frame
)
1927 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1928 int pr
= get_frame_register_unsigned (frame
, FPSCR_REGNUM
) & 0x80000;
1931 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1932 paddr (get_frame_register_unsigned (frame
,
1933 gdbarch_pc_regnum (gdbarch
))),
1934 (long) get_frame_register_unsigned (frame
, SR_REGNUM
),
1935 (long) get_frame_register_unsigned (frame
, PR_REGNUM
),
1936 (long) get_frame_register_unsigned (frame
, MACH_REGNUM
));
1939 (" GBR %08lx VBR %08lx MACL %08lx\n",
1940 (long) get_frame_register_unsigned (frame
, GBR_REGNUM
),
1941 (long) get_frame_register_unsigned (frame
, VBR_REGNUM
),
1942 (long) get_frame_register_unsigned (frame
, MACL_REGNUM
));
1944 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1945 (long) get_frame_register_unsigned (frame
, SSR_REGNUM
),
1946 (long) get_frame_register_unsigned (frame
, SPC_REGNUM
),
1947 (long) get_frame_register_unsigned (frame
, FPUL_REGNUM
),
1948 (long) get_frame_register_unsigned (frame
, FPSCR_REGNUM
));
1951 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1952 (long) get_frame_register_unsigned (frame
, 0),
1953 (long) get_frame_register_unsigned (frame
, 1),
1954 (long) get_frame_register_unsigned (frame
, 2),
1955 (long) get_frame_register_unsigned (frame
, 3),
1956 (long) get_frame_register_unsigned (frame
, 4),
1957 (long) get_frame_register_unsigned (frame
, 5),
1958 (long) get_frame_register_unsigned (frame
, 6),
1959 (long) get_frame_register_unsigned (frame
, 7));
1961 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1962 (long) get_frame_register_unsigned (frame
, 8),
1963 (long) get_frame_register_unsigned (frame
, 9),
1964 (long) get_frame_register_unsigned (frame
, 10),
1965 (long) get_frame_register_unsigned (frame
, 11),
1966 (long) get_frame_register_unsigned (frame
, 12),
1967 (long) get_frame_register_unsigned (frame
, 13),
1968 (long) get_frame_register_unsigned (frame
, 14),
1969 (long) get_frame_register_unsigned (frame
, 15));
1972 (pr
? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1973 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1974 (long) get_frame_register_unsigned
1975 (frame
, gdbarch_fp0_regnum (gdbarch
) + 0),
1976 (long) get_frame_register_unsigned
1977 (frame
, gdbarch_fp0_regnum (gdbarch
) + 1),
1978 (long) get_frame_register_unsigned
1979 (frame
, gdbarch_fp0_regnum (gdbarch
) + 2),
1980 (long) get_frame_register_unsigned
1981 (frame
, gdbarch_fp0_regnum (gdbarch
) + 3),
1982 (long) get_frame_register_unsigned
1983 (frame
, gdbarch_fp0_regnum (gdbarch
) + 4),
1984 (long) get_frame_register_unsigned
1985 (frame
, gdbarch_fp0_regnum (gdbarch
) + 5),
1986 (long) get_frame_register_unsigned
1987 (frame
, gdbarch_fp0_regnum (gdbarch
) + 6),
1988 (long) get_frame_register_unsigned
1989 (frame
, gdbarch_fp0_regnum (gdbarch
) + 7));
1991 (pr
? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1992 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1993 (long) get_frame_register_unsigned
1994 (frame
, gdbarch_fp0_regnum (gdbarch
) + 8),
1995 (long) get_frame_register_unsigned
1996 (frame
, gdbarch_fp0_regnum (gdbarch
) + 9),
1997 (long) get_frame_register_unsigned
1998 (frame
, gdbarch_fp0_regnum (gdbarch
) + 10),
1999 (long) get_frame_register_unsigned
2000 (frame
, gdbarch_fp0_regnum (gdbarch
) + 11),
2001 (long) get_frame_register_unsigned
2002 (frame
, gdbarch_fp0_regnum (gdbarch
) + 12),
2003 (long) get_frame_register_unsigned
2004 (frame
, gdbarch_fp0_regnum (gdbarch
) + 13),
2005 (long) get_frame_register_unsigned
2006 (frame
, gdbarch_fp0_regnum (gdbarch
) + 14),
2007 (long) get_frame_register_unsigned
2008 (frame
, gdbarch_fp0_regnum (gdbarch
) + 15));
2012 sh4_nofpu_show_regs (struct frame_info
*frame
)
2015 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
2016 paddr (get_frame_register_unsigned (frame
,
2018 (get_frame_arch (frame
)))),
2019 (long) get_frame_register_unsigned (frame
, SR_REGNUM
),
2020 (long) get_frame_register_unsigned (frame
, PR_REGNUM
),
2021 (long) get_frame_register_unsigned (frame
, MACH_REGNUM
));
2024 (" GBR %08lx VBR %08lx MACL %08lx\n",
2025 (long) get_frame_register_unsigned (frame
, GBR_REGNUM
),
2026 (long) get_frame_register_unsigned (frame
, VBR_REGNUM
),
2027 (long) get_frame_register_unsigned (frame
, MACL_REGNUM
));
2029 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
2030 (long) get_frame_register_unsigned (frame
, SSR_REGNUM
),
2031 (long) get_frame_register_unsigned (frame
, SPC_REGNUM
),
2032 (long) get_frame_register_unsigned (frame
, FPUL_REGNUM
),
2033 (long) get_frame_register_unsigned (frame
, FPSCR_REGNUM
));
2036 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2037 (long) get_frame_register_unsigned (frame
, 0),
2038 (long) get_frame_register_unsigned (frame
, 1),
2039 (long) get_frame_register_unsigned (frame
, 2),
2040 (long) get_frame_register_unsigned (frame
, 3),
2041 (long) get_frame_register_unsigned (frame
, 4),
2042 (long) get_frame_register_unsigned (frame
, 5),
2043 (long) get_frame_register_unsigned (frame
, 6),
2044 (long) get_frame_register_unsigned (frame
, 7));
2046 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2047 (long) get_frame_register_unsigned (frame
, 8),
2048 (long) get_frame_register_unsigned (frame
, 9),
2049 (long) get_frame_register_unsigned (frame
, 10),
2050 (long) get_frame_register_unsigned (frame
, 11),
2051 (long) get_frame_register_unsigned (frame
, 12),
2052 (long) get_frame_register_unsigned (frame
, 13),
2053 (long) get_frame_register_unsigned (frame
, 14),
2054 (long) get_frame_register_unsigned (frame
, 15));
2058 sh_dsp_show_regs (struct frame_info
*frame
)
2061 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
2062 paddr (get_frame_register_unsigned (frame
,
2064 (get_frame_arch (frame
)))),
2065 (long) get_frame_register_unsigned (frame
, SR_REGNUM
),
2066 (long) get_frame_register_unsigned (frame
, PR_REGNUM
),
2067 (long) get_frame_register_unsigned (frame
, MACH_REGNUM
));
2070 (" GBR %08lx VBR %08lx DSR %08lx MACL %08lx\n",
2071 (long) get_frame_register_unsigned (frame
, GBR_REGNUM
),
2072 (long) get_frame_register_unsigned (frame
, VBR_REGNUM
),
2073 (long) get_frame_register_unsigned (frame
, DSR_REGNUM
),
2074 (long) get_frame_register_unsigned (frame
, MACL_REGNUM
));
2077 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2078 (long) get_frame_register_unsigned (frame
, 0),
2079 (long) get_frame_register_unsigned (frame
, 1),
2080 (long) get_frame_register_unsigned (frame
, 2),
2081 (long) get_frame_register_unsigned (frame
, 3),
2082 (long) get_frame_register_unsigned (frame
, 4),
2083 (long) get_frame_register_unsigned (frame
, 5),
2084 (long) get_frame_register_unsigned (frame
, 6),
2085 (long) get_frame_register_unsigned (frame
, 7));
2087 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2088 (long) get_frame_register_unsigned (frame
, 8),
2089 (long) get_frame_register_unsigned (frame
, 9),
2090 (long) get_frame_register_unsigned (frame
, 10),
2091 (long) get_frame_register_unsigned (frame
, 11),
2092 (long) get_frame_register_unsigned (frame
, 12),
2093 (long) get_frame_register_unsigned (frame
, 13),
2094 (long) get_frame_register_unsigned (frame
, 14),
2095 (long) get_frame_register_unsigned (frame
, 15));
2098 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
2099 (long) get_frame_register_unsigned (frame
, A0G_REGNUM
) & 0xff,
2100 (long) get_frame_register_unsigned (frame
, A0_REGNUM
),
2101 (long) get_frame_register_unsigned (frame
, M0_REGNUM
),
2102 (long) get_frame_register_unsigned (frame
, X0_REGNUM
),
2103 (long) get_frame_register_unsigned (frame
, Y0_REGNUM
),
2104 (long) get_frame_register_unsigned (frame
, RS_REGNUM
),
2105 (long) get_frame_register_unsigned (frame
, MOD_REGNUM
));
2106 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
2107 (long) get_frame_register_unsigned (frame
, A1G_REGNUM
) & 0xff,
2108 (long) get_frame_register_unsigned (frame
, A1_REGNUM
),
2109 (long) get_frame_register_unsigned (frame
, M1_REGNUM
),
2110 (long) get_frame_register_unsigned (frame
, X1_REGNUM
),
2111 (long) get_frame_register_unsigned (frame
, Y1_REGNUM
),
2112 (long) get_frame_register_unsigned (frame
, RE_REGNUM
));
2116 sh_show_regs_command (char *args
, int from_tty
)
2119 (*sh_show_regs
) (get_current_frame ());
2122 static struct type
*
2123 sh_sh2a_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
2125 if ((reg_nr
>= gdbarch_fp0_regnum (gdbarch
)
2126 && (reg_nr
<= FP_LAST_REGNUM
)) || (reg_nr
== FPUL_REGNUM
))
2127 return builtin_type (gdbarch
)->builtin_float
;
2128 else if (reg_nr
>= DR0_REGNUM
&& reg_nr
<= DR_LAST_REGNUM
)
2129 return builtin_type (gdbarch
)->builtin_double
;
2131 return builtin_type (gdbarch
)->builtin_int
;
2134 /* Return the GDB type object for the "standard" data type
2135 of data in register N. */
2136 static struct type
*
2137 sh_sh3e_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
2139 if ((reg_nr
>= gdbarch_fp0_regnum (gdbarch
)
2140 && (reg_nr
<= FP_LAST_REGNUM
)) || (reg_nr
== FPUL_REGNUM
))
2141 return builtin_type (gdbarch
)->builtin_float
;
2143 return builtin_type (gdbarch
)->builtin_int
;
2146 static struct type
*
2147 sh_sh4_build_float_register_type (struct gdbarch
*gdbarch
, int high
)
2149 return lookup_array_range_type (builtin_type (gdbarch
)->builtin_float
,
2153 static struct type
*
2154 sh_sh4_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
2156 if ((reg_nr
>= gdbarch_fp0_regnum (gdbarch
)
2157 && (reg_nr
<= FP_LAST_REGNUM
)) || (reg_nr
== FPUL_REGNUM
))
2158 return builtin_type (gdbarch
)->builtin_float
;
2159 else if (reg_nr
>= DR0_REGNUM
&& reg_nr
<= DR_LAST_REGNUM
)
2160 return builtin_type (gdbarch
)->builtin_double
;
2161 else if (reg_nr
>= FV0_REGNUM
&& reg_nr
<= FV_LAST_REGNUM
)
2162 return sh_sh4_build_float_register_type (gdbarch
, 3);
2164 return builtin_type (gdbarch
)->builtin_int
;
2167 static struct type
*
2168 sh_default_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
2170 return builtin_type (gdbarch
)->builtin_int
;
2173 /* Is a register in a reggroup?
2174 The default code in reggroup.c doesn't identify system registers, some
2175 float registers or any of the vector registers.
2176 TODO: sh2a and dsp registers. */
2178 sh_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2179 struct reggroup
*reggroup
)
2181 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
2182 || *gdbarch_register_name (gdbarch
, regnum
) == '\0')
2185 if (reggroup
== float_reggroup
2186 && (regnum
== FPUL_REGNUM
2187 || regnum
== FPSCR_REGNUM
))
2190 if (regnum
>= FV0_REGNUM
&& regnum
<= FV_LAST_REGNUM
)
2192 if (reggroup
== vector_reggroup
|| reggroup
== float_reggroup
)
2194 if (reggroup
== general_reggroup
)
2198 if (regnum
== VBR_REGNUM
2199 || regnum
== SR_REGNUM
2200 || regnum
== FPSCR_REGNUM
2201 || regnum
== SSR_REGNUM
2202 || regnum
== SPC_REGNUM
)
2204 if (reggroup
== system_reggroup
)
2206 if (reggroup
== general_reggroup
)
2210 /* The default code can cope with any other registers. */
2211 return default_register_reggroup_p (gdbarch
, regnum
, reggroup
);
2214 /* On the sh4, the DRi pseudo registers are problematic if the target
2215 is little endian. When the user writes one of those registers, for
2216 instance with 'ser var $dr0=1', we want the double to be stored
2218 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
2219 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2221 This corresponds to little endian byte order & big endian word
2222 order. However if we let gdb write the register w/o conversion, it
2223 will write fr0 and fr1 this way:
2224 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2225 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
2226 because it will consider fr0 and fr1 as a single LE stretch of memory.
2228 To achieve what we want we must force gdb to store things in
2229 floatformat_ieee_double_littlebyte_bigword (which is defined in
2230 include/floatformat.h and libiberty/floatformat.c.
2232 In case the target is big endian, there is no problem, the
2233 raw bytes will look like:
2234 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
2235 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2237 The other pseudo registers (the FVs) also don't pose a problem
2238 because they are stored as 4 individual FP elements. */
2241 sh_register_convert_to_virtual (int regnum
, struct type
*type
,
2242 char *from
, char *to
)
2244 if (regnum
>= DR0_REGNUM
&& regnum
<= DR_LAST_REGNUM
)
2247 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword
,
2249 store_typed_floating (to
, type
, val
);
2253 ("sh_register_convert_to_virtual called with non DR register number");
2257 sh_register_convert_to_raw (struct type
*type
, int regnum
,
2258 const void *from
, void *to
)
2260 if (regnum
>= DR0_REGNUM
&& regnum
<= DR_LAST_REGNUM
)
2262 DOUBLEST val
= extract_typed_floating (from
, type
);
2263 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword
,
2267 error (_("sh_register_convert_to_raw called with non DR register number"));
2270 /* For vectors of 4 floating point registers. */
2272 fv_reg_base_num (struct gdbarch
*gdbarch
, int fv_regnum
)
2276 fp_regnum
= gdbarch_fp0_regnum (gdbarch
)
2277 + (fv_regnum
- FV0_REGNUM
) * 4;
2281 /* For double precision floating point registers, i.e 2 fp regs.*/
2283 dr_reg_base_num (struct gdbarch
*gdbarch
, int dr_regnum
)
2287 fp_regnum
= gdbarch_fp0_regnum (gdbarch
)
2288 + (dr_regnum
- DR0_REGNUM
) * 2;
2293 sh_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2294 int reg_nr
, gdb_byte
*buffer
)
2296 int base_regnum
, portion
;
2297 char temp_buffer
[MAX_REGISTER_SIZE
];
2299 if (reg_nr
== PSEUDO_BANK_REGNUM
)
2300 regcache_raw_read (regcache
, BANK_REGNUM
, buffer
);
2302 if (reg_nr
>= DR0_REGNUM
&& reg_nr
<= DR_LAST_REGNUM
)
2304 base_regnum
= dr_reg_base_num (gdbarch
, reg_nr
);
2306 /* Build the value in the provided buffer. */
2307 /* Read the real regs for which this one is an alias. */
2308 for (portion
= 0; portion
< 2; portion
++)
2309 regcache_raw_read (regcache
, base_regnum
+ portion
,
2311 + register_size (gdbarch
,
2312 base_regnum
) * portion
));
2313 /* We must pay attention to the endiannes. */
2314 sh_register_convert_to_virtual (reg_nr
,
2315 register_type (gdbarch
, reg_nr
),
2316 temp_buffer
, buffer
);
2318 else if (reg_nr
>= FV0_REGNUM
&& reg_nr
<= FV_LAST_REGNUM
)
2320 base_regnum
= fv_reg_base_num (gdbarch
, reg_nr
);
2322 /* Read the real regs for which this one is an alias. */
2323 for (portion
= 0; portion
< 4; portion
++)
2324 regcache_raw_read (regcache
, base_regnum
+ portion
,
2326 + register_size (gdbarch
,
2327 base_regnum
) * portion
));
2332 sh_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2333 int reg_nr
, const gdb_byte
*buffer
)
2335 int base_regnum
, portion
;
2336 char temp_buffer
[MAX_REGISTER_SIZE
];
2338 if (reg_nr
== PSEUDO_BANK_REGNUM
)
2340 /* When the bank register is written to, the whole register bank
2341 is switched and all values in the bank registers must be read
2342 from the target/sim again. We're just invalidating the regcache
2343 so that a re-read happens next time it's necessary. */
2346 regcache_raw_write (regcache
, BANK_REGNUM
, buffer
);
2347 for (bregnum
= R0_BANK0_REGNUM
; bregnum
< MACLB_REGNUM
; ++bregnum
)
2348 regcache_invalidate (regcache
, bregnum
);
2350 else if (reg_nr
>= DR0_REGNUM
&& reg_nr
<= DR_LAST_REGNUM
)
2352 base_regnum
= dr_reg_base_num (gdbarch
, reg_nr
);
2354 /* We must pay attention to the endiannes. */
2355 sh_register_convert_to_raw (register_type (gdbarch
, reg_nr
),
2356 reg_nr
, buffer
, temp_buffer
);
2358 /* Write the real regs for which this one is an alias. */
2359 for (portion
= 0; portion
< 2; portion
++)
2360 regcache_raw_write (regcache
, base_regnum
+ portion
,
2362 + register_size (gdbarch
,
2363 base_regnum
) * portion
));
2365 else if (reg_nr
>= FV0_REGNUM
&& reg_nr
<= FV_LAST_REGNUM
)
2367 base_regnum
= fv_reg_base_num (gdbarch
, reg_nr
);
2369 /* Write the real regs for which this one is an alias. */
2370 for (portion
= 0; portion
< 4; portion
++)
2371 regcache_raw_write (regcache
, base_regnum
+ portion
,
2373 + register_size (gdbarch
,
2374 base_regnum
) * portion
));
2379 sh_dsp_register_sim_regno (struct gdbarch
*gdbarch
, int nr
)
2381 if (legacy_register_sim_regno (gdbarch
, nr
) < 0)
2382 return legacy_register_sim_regno (gdbarch
, nr
);
2383 if (nr
>= DSR_REGNUM
&& nr
<= Y1_REGNUM
)
2384 return nr
- DSR_REGNUM
+ SIM_SH_DSR_REGNUM
;
2385 if (nr
== MOD_REGNUM
)
2386 return SIM_SH_MOD_REGNUM
;
2387 if (nr
== RS_REGNUM
)
2388 return SIM_SH_RS_REGNUM
;
2389 if (nr
== RE_REGNUM
)
2390 return SIM_SH_RE_REGNUM
;
2391 if (nr
>= DSP_R0_BANK_REGNUM
&& nr
<= DSP_R7_BANK_REGNUM
)
2392 return nr
- DSP_R0_BANK_REGNUM
+ SIM_SH_R0_BANK_REGNUM
;
2397 sh_sh2a_register_sim_regno (struct gdbarch
*gdbarch
, int nr
)
2402 return SIM_SH_TBR_REGNUM
;
2404 return SIM_SH_IBNR_REGNUM
;
2406 return SIM_SH_IBCR_REGNUM
;
2408 return SIM_SH_BANK_REGNUM
;
2410 return SIM_SH_BANK_MACL_REGNUM
;
2412 return SIM_SH_BANK_GBR_REGNUM
;
2414 return SIM_SH_BANK_PR_REGNUM
;
2416 return SIM_SH_BANK_IVN_REGNUM
;
2418 return SIM_SH_BANK_MACH_REGNUM
;
2422 return legacy_register_sim_regno (gdbarch
, nr
);
2425 /* Set up the register unwinding such that call-clobbered registers are
2426 not displayed in frames >0 because the true value is not certain.
2427 The 'undefined' registers will show up as 'not available' unless the
2430 This function is currently set up for SH4 and compatible only. */
2433 sh_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
2434 struct dwarf2_frame_state_reg
*reg
,
2435 struct frame_info
*this_frame
)
2437 /* Mark the PC as the destination for the return address. */
2438 if (regnum
== gdbarch_pc_regnum (gdbarch
))
2439 reg
->how
= DWARF2_FRAME_REG_RA
;
2441 /* Mark the stack pointer as the call frame address. */
2442 else if (regnum
== gdbarch_sp_regnum (gdbarch
))
2443 reg
->how
= DWARF2_FRAME_REG_CFA
;
2445 /* The above was taken from the default init_reg in dwarf2-frame.c
2446 while the below is SH specific. */
2448 /* Caller save registers. */
2449 else if ((regnum
>= R0_REGNUM
&& regnum
<= R0_REGNUM
+7)
2450 || (regnum
>= FR0_REGNUM
&& regnum
<= FR0_REGNUM
+11)
2451 || (regnum
>= DR0_REGNUM
&& regnum
<= DR0_REGNUM
+5)
2452 || (regnum
>= FV0_REGNUM
&& regnum
<= FV0_REGNUM
+2)
2453 || (regnum
== MACH_REGNUM
)
2454 || (regnum
== MACL_REGNUM
)
2455 || (regnum
== FPUL_REGNUM
)
2456 || (regnum
== SR_REGNUM
))
2457 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
2459 /* Callee save registers. */
2460 else if ((regnum
>= R0_REGNUM
+8 && regnum
<= R0_REGNUM
+15)
2461 || (regnum
>= FR0_REGNUM
+12 && regnum
<= FR0_REGNUM
+15)
2462 || (regnum
>= DR0_REGNUM
+6 && regnum
<= DR0_REGNUM
+8)
2463 || (regnum
== FV0_REGNUM
+3))
2464 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
2466 /* Other registers. These are not in the ABI and may or may not
2467 mean anything in frames >0 so don't show them. */
2468 else if ((regnum
>= R0_BANK0_REGNUM
&& regnum
<= R0_BANK0_REGNUM
+15)
2469 || (regnum
== GBR_REGNUM
)
2470 || (regnum
== VBR_REGNUM
)
2471 || (regnum
== FPSCR_REGNUM
)
2472 || (regnum
== SSR_REGNUM
)
2473 || (regnum
== SPC_REGNUM
))
2474 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
2477 static struct sh_frame_cache
*
2478 sh_alloc_frame_cache (void)
2480 struct sh_frame_cache
*cache
;
2483 cache
= FRAME_OBSTACK_ZALLOC (struct sh_frame_cache
);
2487 cache
->saved_sp
= 0;
2488 cache
->sp_offset
= 0;
2491 /* Frameless until proven otherwise. */
2494 /* Saved registers. We initialize these to -1 since zero is a valid
2495 offset (that's where fp is supposed to be stored). */
2496 for (i
= 0; i
< SH_NUM_REGS
; i
++)
2498 cache
->saved_regs
[i
] = -1;
2504 static struct sh_frame_cache
*
2505 sh_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2507 struct sh_frame_cache
*cache
;
2508 CORE_ADDR current_pc
;
2514 cache
= sh_alloc_frame_cache ();
2515 *this_cache
= cache
;
2517 /* In principle, for normal frames, fp holds the frame pointer,
2518 which holds the base address for the current stack frame.
2519 However, for functions that don't need it, the frame pointer is
2520 optional. For these "frameless" functions the frame pointer is
2521 actually the frame pointer of the calling frame. */
2522 cache
->base
= get_frame_register_unsigned (this_frame
, FP_REGNUM
);
2523 if (cache
->base
== 0)
2526 cache
->pc
= get_frame_func (this_frame
);
2527 current_pc
= get_frame_pc (this_frame
);
2531 fpscr
= get_frame_register_unsigned (this_frame
, FPSCR_REGNUM
);
2532 sh_analyze_prologue (cache
->pc
, current_pc
, cache
, fpscr
);
2535 if (!cache
->uses_fp
)
2537 /* We didn't find a valid frame, which means that CACHE->base
2538 currently holds the frame pointer for our calling frame. If
2539 we're at the start of a function, or somewhere half-way its
2540 prologue, the function's frame probably hasn't been fully
2541 setup yet. Try to reconstruct the base address for the stack
2542 frame by looking at the stack pointer. For truly "frameless"
2543 functions this might work too. */
2544 cache
->base
= get_frame_register_unsigned
2546 gdbarch_sp_regnum (get_frame_arch (this_frame
)));
2549 /* Now that we have the base address for the stack frame we can
2550 calculate the value of sp in the calling frame. */
2551 cache
->saved_sp
= cache
->base
+ cache
->sp_offset
;
2553 /* Adjust all the saved registers such that they contain addresses
2554 instead of offsets. */
2555 for (i
= 0; i
< SH_NUM_REGS
; i
++)
2556 if (cache
->saved_regs
[i
] != -1)
2557 cache
->saved_regs
[i
] = cache
->saved_sp
- cache
->saved_regs
[i
] - 4;
2562 static struct value
*
2563 sh_frame_prev_register (struct frame_info
*this_frame
,
2564 void **this_cache
, int regnum
)
2566 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2567 struct sh_frame_cache
*cache
= sh_frame_cache (this_frame
, this_cache
);
2569 gdb_assert (regnum
>= 0);
2571 if (regnum
== gdbarch_sp_regnum (gdbarch
) && cache
->saved_sp
)
2572 return frame_unwind_got_constant (this_frame
, regnum
, cache
->saved_sp
);
2574 /* The PC of the previous frame is stored in the PR register of
2575 the current frame. Frob regnum so that we pull the value from
2576 the correct place. */
2577 if (regnum
== gdbarch_pc_regnum (gdbarch
))
2580 if (regnum
< SH_NUM_REGS
&& cache
->saved_regs
[regnum
] != -1)
2581 return frame_unwind_got_memory (this_frame
, regnum
,
2582 cache
->saved_regs
[regnum
]);
2584 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
2588 sh_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2589 struct frame_id
*this_id
)
2591 struct sh_frame_cache
*cache
= sh_frame_cache (this_frame
, this_cache
);
2593 /* This marks the outermost frame. */
2594 if (cache
->base
== 0)
2597 *this_id
= frame_id_build (cache
->saved_sp
, cache
->pc
);
2600 static const struct frame_unwind sh_frame_unwind
= {
2603 sh_frame_prev_register
,
2605 default_frame_sniffer
2609 sh_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2611 return frame_unwind_register_unsigned (next_frame
,
2612 gdbarch_sp_regnum (gdbarch
));
2616 sh_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2618 return frame_unwind_register_unsigned (next_frame
,
2619 gdbarch_pc_regnum (gdbarch
));
2622 static struct frame_id
2623 sh_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2625 CORE_ADDR sp
= get_frame_register_unsigned (this_frame
,
2626 gdbarch_sp_regnum (gdbarch
));
2627 return frame_id_build (sp
, get_frame_pc (this_frame
));
2631 sh_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2633 struct sh_frame_cache
*cache
= sh_frame_cache (this_frame
, this_cache
);
2638 static const struct frame_base sh_frame_base
= {
2640 sh_frame_base_address
,
2641 sh_frame_base_address
,
2642 sh_frame_base_address
2645 /* The epilogue is defined here as the area at the end of a function,
2646 either on the `ret' instruction itself or after an instruction which
2647 destroys the function's stack frame. */
2649 sh_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2651 CORE_ADDR func_addr
= 0, func_end
= 0;
2653 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
2656 /* The sh epilogue is max. 14 bytes long. Give another 14 bytes
2657 for a nop and some fixed data (e.g. big offsets) which are
2658 unfortunately also treated as part of the function (which
2659 means, they are below func_end. */
2660 CORE_ADDR addr
= func_end
- 28;
2661 if (addr
< func_addr
+ 4)
2662 addr
= func_addr
+ 4;
2666 /* First search forward until hitting an rts. */
2667 while (addr
< func_end
2668 && !IS_RTS (read_memory_unsigned_integer (addr
, 2)))
2670 if (addr
>= func_end
)
2673 /* At this point we should find a mov.l @r15+,r14 instruction,
2674 either before or after the rts. If not, then the function has
2675 probably no "normal" epilogue and we bail out here. */
2676 inst
= read_memory_unsigned_integer (addr
- 2, 2);
2677 if (IS_RESTORE_FP (read_memory_unsigned_integer (addr
- 2, 2)))
2679 else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr
+ 2, 2)))
2682 inst
= read_memory_unsigned_integer (addr
- 2, 2);
2684 /* Step over possible lds.l @r15+,macl. */
2685 if (IS_MACL_LDS (inst
))
2688 inst
= read_memory_unsigned_integer (addr
- 2, 2);
2691 /* Step over possible lds.l @r15+,pr. */
2695 inst
= read_memory_unsigned_integer (addr
- 2, 2);
2698 /* Step over possible mov r14,r15. */
2699 if (IS_MOV_FP_SP (inst
))
2702 inst
= read_memory_unsigned_integer (addr
- 2, 2);
2705 /* Now check for FP adjustments, using add #imm,r14 or add rX, r14
2707 while (addr
> func_addr
+ 4
2708 && (IS_ADD_REG_TO_FP (inst
) || IS_ADD_IMM_FP (inst
)))
2711 inst
= read_memory_unsigned_integer (addr
- 2, 2);
2714 /* On SH2a check if the previous instruction was perhaps a MOVI20.
2715 That's allowed for the epilogue. */
2716 if ((gdbarch_bfd_arch_info (gdbarch
)->mach
== bfd_mach_sh2a
2717 || gdbarch_bfd_arch_info (gdbarch
)->mach
== bfd_mach_sh2a_nofpu
)
2718 && addr
> func_addr
+ 6
2719 && IS_MOVI20 (read_memory_unsigned_integer (addr
- 4, 2)))
2729 static struct gdbarch
*
2730 sh_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2732 struct gdbarch
*gdbarch
;
2734 sh_show_regs
= sh_generic_show_regs
;
2735 switch (info
.bfd_arch_info
->mach
)
2738 sh_show_regs
= sh2e_show_regs
;
2741 sh_show_regs
= sh2a_show_regs
;
2743 case bfd_mach_sh2a_nofpu
:
2744 sh_show_regs
= sh2a_nofpu_show_regs
;
2746 case bfd_mach_sh_dsp
:
2747 sh_show_regs
= sh_dsp_show_regs
;
2751 sh_show_regs
= sh3_show_regs
;
2755 sh_show_regs
= sh3e_show_regs
;
2758 case bfd_mach_sh3_dsp
:
2759 case bfd_mach_sh4al_dsp
:
2760 sh_show_regs
= sh3_dsp_show_regs
;
2765 sh_show_regs
= sh4_show_regs
;
2768 case bfd_mach_sh4_nofpu
:
2769 case bfd_mach_sh4a_nofpu
:
2770 sh_show_regs
= sh4_nofpu_show_regs
;
2774 sh_show_regs
= sh64_show_regs
;
2775 /* SH5 is handled entirely in sh64-tdep.c */
2776 return sh64_gdbarch_init (info
, arches
);
2779 /* If there is already a candidate, use it. */
2780 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2782 return arches
->gdbarch
;
2784 /* None found, create a new architecture from the information
2786 gdbarch
= gdbarch_alloc (&info
, NULL
);
2788 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
2789 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2790 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2791 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2792 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2793 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2794 set_gdbarch_long_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2795 set_gdbarch_ptr_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2797 set_gdbarch_num_regs (gdbarch
, SH_NUM_REGS
);
2798 set_gdbarch_sp_regnum (gdbarch
, 15);
2799 set_gdbarch_pc_regnum (gdbarch
, 16);
2800 set_gdbarch_fp0_regnum (gdbarch
, -1);
2801 set_gdbarch_num_pseudo_regs (gdbarch
, 0);
2803 set_gdbarch_register_type (gdbarch
, sh_default_register_type
);
2804 set_gdbarch_register_reggroup_p (gdbarch
, sh_register_reggroup_p
);
2806 set_gdbarch_breakpoint_from_pc (gdbarch
, sh_breakpoint_from_pc
);
2808 set_gdbarch_print_insn (gdbarch
, print_insn_sh
);
2809 set_gdbarch_register_sim_regno (gdbarch
, legacy_register_sim_regno
);
2811 set_gdbarch_return_value (gdbarch
, sh_return_value_nofpu
);
2813 set_gdbarch_skip_prologue (gdbarch
, sh_skip_prologue
);
2814 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2816 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_nofpu
);
2818 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
2820 set_gdbarch_frame_align (gdbarch
, sh_frame_align
);
2821 set_gdbarch_unwind_sp (gdbarch
, sh_unwind_sp
);
2822 set_gdbarch_unwind_pc (gdbarch
, sh_unwind_pc
);
2823 set_gdbarch_dummy_id (gdbarch
, sh_dummy_id
);
2824 frame_base_set_default (gdbarch
, &sh_frame_base
);
2826 set_gdbarch_in_function_epilogue_p (gdbarch
, sh_in_function_epilogue_p
);
2828 dwarf2_frame_set_init_reg (gdbarch
, sh_dwarf2_frame_init_reg
);
2830 switch (info
.bfd_arch_info
->mach
)
2833 set_gdbarch_register_name (gdbarch
, sh_sh_register_name
);
2837 set_gdbarch_register_name (gdbarch
, sh_sh_register_name
);
2841 /* doubles on sh2e and sh3e are actually 4 byte. */
2842 set_gdbarch_double_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2844 set_gdbarch_register_name (gdbarch
, sh_sh2e_register_name
);
2845 set_gdbarch_register_type (gdbarch
, sh_sh3e_register_type
);
2846 set_gdbarch_fp0_regnum (gdbarch
, 25);
2847 set_gdbarch_return_value (gdbarch
, sh_return_value_fpu
);
2848 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_fpu
);
2852 set_gdbarch_register_name (gdbarch
, sh_sh2a_register_name
);
2853 set_gdbarch_register_type (gdbarch
, sh_sh2a_register_type
);
2854 set_gdbarch_register_sim_regno (gdbarch
, sh_sh2a_register_sim_regno
);
2856 set_gdbarch_fp0_regnum (gdbarch
, 25);
2857 set_gdbarch_num_pseudo_regs (gdbarch
, 9);
2858 set_gdbarch_pseudo_register_read (gdbarch
, sh_pseudo_register_read
);
2859 set_gdbarch_pseudo_register_write (gdbarch
, sh_pseudo_register_write
);
2860 set_gdbarch_return_value (gdbarch
, sh_return_value_fpu
);
2861 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_fpu
);
2864 case bfd_mach_sh2a_nofpu
:
2865 set_gdbarch_register_name (gdbarch
, sh_sh2a_nofpu_register_name
);
2866 set_gdbarch_register_sim_regno (gdbarch
, sh_sh2a_register_sim_regno
);
2868 set_gdbarch_num_pseudo_regs (gdbarch
, 1);
2869 set_gdbarch_pseudo_register_read (gdbarch
, sh_pseudo_register_read
);
2870 set_gdbarch_pseudo_register_write (gdbarch
, sh_pseudo_register_write
);
2873 case bfd_mach_sh_dsp
:
2874 set_gdbarch_register_name (gdbarch
, sh_sh_dsp_register_name
);
2875 set_gdbarch_register_sim_regno (gdbarch
, sh_dsp_register_sim_regno
);
2879 case bfd_mach_sh3_nommu
:
2880 case bfd_mach_sh2a_nofpu_or_sh3_nommu
:
2881 set_gdbarch_register_name (gdbarch
, sh_sh3_register_name
);
2885 case bfd_mach_sh2a_or_sh3e
:
2886 /* doubles on sh2e and sh3e are actually 4 byte. */
2887 set_gdbarch_double_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2889 set_gdbarch_register_name (gdbarch
, sh_sh3e_register_name
);
2890 set_gdbarch_register_type (gdbarch
, sh_sh3e_register_type
);
2891 set_gdbarch_fp0_regnum (gdbarch
, 25);
2892 set_gdbarch_return_value (gdbarch
, sh_return_value_fpu
);
2893 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_fpu
);
2896 case bfd_mach_sh3_dsp
:
2897 set_gdbarch_register_name (gdbarch
, sh_sh3_dsp_register_name
);
2898 set_gdbarch_register_sim_regno (gdbarch
, sh_dsp_register_sim_regno
);
2903 set_gdbarch_register_name (gdbarch
, sh_sh4_register_name
);
2904 set_gdbarch_register_type (gdbarch
, sh_sh4_register_type
);
2905 set_gdbarch_fp0_regnum (gdbarch
, 25);
2906 set_gdbarch_num_pseudo_regs (gdbarch
, 13);
2907 set_gdbarch_pseudo_register_read (gdbarch
, sh_pseudo_register_read
);
2908 set_gdbarch_pseudo_register_write (gdbarch
, sh_pseudo_register_write
);
2909 set_gdbarch_return_value (gdbarch
, sh_return_value_fpu
);
2910 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_fpu
);
2913 case bfd_mach_sh4_nofpu
:
2914 case bfd_mach_sh4a_nofpu
:
2915 case bfd_mach_sh4_nommu_nofpu
:
2916 case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu
:
2917 case bfd_mach_sh2a_or_sh4
:
2918 set_gdbarch_register_name (gdbarch
, sh_sh4_nofpu_register_name
);
2921 case bfd_mach_sh4al_dsp
:
2922 set_gdbarch_register_name (gdbarch
, sh_sh4al_dsp_register_name
);
2923 set_gdbarch_register_sim_regno (gdbarch
, sh_dsp_register_sim_regno
);
2927 set_gdbarch_register_name (gdbarch
, sh_sh_register_name
);
2931 /* Hook in ABI-specific overrides, if they have been registered. */
2932 gdbarch_init_osabi (info
, gdbarch
);
2934 dwarf2_append_unwinders (gdbarch
);
2935 frame_unwind_append_unwinder (gdbarch
, &sh_frame_unwind
);
2941 show_sh_command (char *args
, int from_tty
)
2943 help_list (showshcmdlist
, "show sh ", all_commands
, gdb_stdout
);
2947 set_sh_command (char *args
, int from_tty
)
2950 ("\"set sh\" must be followed by an appropriate subcommand.\n");
2951 help_list (setshcmdlist
, "set sh ", all_commands
, gdb_stdout
);
2954 extern initialize_file_ftype _initialize_sh_tdep
; /* -Wmissing-prototypes */
2957 _initialize_sh_tdep (void)
2959 struct cmd_list_element
*c
;
2961 gdbarch_register (bfd_arch_sh
, sh_gdbarch_init
, NULL
);
2963 add_com ("regs", class_vars
, sh_show_regs_command
, _("Print all registers"));
2965 add_prefix_cmd ("sh", no_class
, set_sh_command
, "SH specific commands.",
2966 &setshcmdlist
, "set sh ", 0, &setlist
);
2967 add_prefix_cmd ("sh", no_class
, show_sh_command
, "SH specific commands.",
2968 &showshcmdlist
, "show sh ", 0, &showlist
);
2970 add_setshow_enum_cmd ("calling-convention", class_vars
, sh_cc_enum
,
2971 &sh_active_calling_convention
,
2972 _("Set calling convention used when calling target "
2973 "functions from GDB."),
2974 _("Show calling convention used when calling target "
2975 "functions from GDB."),
2976 _("gcc - Use GCC calling convention (default).\n"
2977 "renesas - Enforce Renesas calling convention."),
2979 &setshcmdlist
, &showshcmdlist
);