gdb/sh-tdep.c

   1 /* Target-dependent code for Renesas Super-H, for GDB.
   2    Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
   3    2003, 2004 Free Software Foundation, Inc.
   4
   5    This file is part of GDB.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 2 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program; if not, write to the Free Software
  19    Foundation, Inc., 59 Temple Place - Suite 330,
  20    Boston, MA 02111-1307, USA.  */
  21
  22 /*
  23    Contributed by Steve Chamberlain
  24    sac@cygnus.com
  25  */
  26
  27 #include "defs.h"
  28 #include "frame.h"
  29 #include "frame-base.h"
  30 #include "frame-unwind.h"
  31 #include "dwarf2-frame.h"
  32 #include "symtab.h"
  33 #include "gdbtypes.h"
  34 #include "gdbcmd.h"
  35 #include "gdbcore.h"
  36 #include "value.h"
  37 #include "dis-asm.h"
  38 #include "inferior.h"
  39 #include "gdb_string.h"
  40 #include "gdb_assert.h"
  41 #include "arch-utils.h"
  42 #include "floatformat.h"
  43 #include "regcache.h"
  44 #include "doublest.h"
  45 #include "osabi.h"
  46
  47 #include "sh-tdep.h"
  48
  49 #include "elf-bfd.h"
  50 #include "solib-svr4.h"
  51
  52 /* sh flags */
  53 #include "elf/sh.h"
  54 /* registers numbers shared with the simulator */
  55 #include "gdb/sim-sh.h"
  56
  57 static void (*sh_show_regs) (void);
  58
  59 #define SH_NUM_REGS 59
  60
  61 struct sh_frame_cache
  62 {
  63   /* Base address.  */
  64   CORE_ADDR base;
  65   LONGEST sp_offset;
  66   CORE_ADDR pc;
  67
  68   /* Flag showing that a frame has been created in the prologue code. */
  69   int uses_fp;
  70
  71   /* Saved registers.  */
  72   CORE_ADDR saved_regs[SH_NUM_REGS];
  73   CORE_ADDR saved_sp;
  74 };
  75
  76 static const char *
  77 sh_generic_register_name (int reg_nr)
  78 {
  79   static char *register_names[] = {
  80     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
  81     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
  82     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
  83     "fpul", "fpscr",
  84     "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
  85     "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
  86     "ssr", "spc",
  87     "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
  88     "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
  89   };
  90   if (reg_nr < 0)
  91     return NULL;
  92   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
  93     return NULL;
  94   return register_names[reg_nr];
  95 }
  96
  97 static const char *
  98 sh_sh_register_name (int reg_nr)
  99 {
 100   static char *register_names[] = {
 101     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 102     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 103     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
 104     "", "",
 105     "", "", "", "", "", "", "", "",
 106     "", "", "", "", "", "", "", "",
 107     "", "",
 108     "", "", "", "", "", "", "", "",
 109     "", "", "", "", "", "", "", "",
 110   };
 111   if (reg_nr < 0)
 112     return NULL;
 113   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
 114     return NULL;
 115   return register_names[reg_nr];
 116 }
 117
 118 static const char *
 119 sh_sh3_register_name (int reg_nr)
 120 {
 121   static char *register_names[] = {
 122     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 123     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 124     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
 125     "", "",
 126     "", "", "", "", "", "", "", "",
 127     "", "", "", "", "", "", "", "",
 128     "ssr", "spc",
 129     "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
 130     "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
 131   };
 132   if (reg_nr < 0)
 133     return NULL;
 134   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
 135     return NULL;
 136   return register_names[reg_nr];
 137 }
 138
 139 static const char *
 140 sh_sh3e_register_name (int reg_nr)
 141 {
 142   static char *register_names[] = {
 143     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 144     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 145     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
 146     "fpul", "fpscr",
 147     "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
 148     "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
 149     "ssr", "spc",
 150     "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
 151     "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
 152   };
 153   if (reg_nr < 0)
 154     return NULL;
 155   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
 156     return NULL;
 157   return register_names[reg_nr];
 158 }
 159
 160 static const char *
 161 sh_sh2e_register_name (int reg_nr)
 162 {
 163   static char *register_names[] = {
 164     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 165     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 166     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
 167     "fpul", "fpscr",
 168     "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
 169     "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
 170     "", "",
 171     "", "", "", "", "", "", "", "",
 172     "", "", "", "", "", "", "", "",
 173   };
 174   if (reg_nr < 0)
 175     return NULL;
 176   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
 177     return NULL;
 178   return register_names[reg_nr];
 179 }
 180
 181 static const char *
 182 sh_sh_dsp_register_name (int reg_nr)
 183 {
 184   static char *register_names[] = {
 185     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 186     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 187     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
 188     "", "dsr",
 189     "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
 190     "y0", "y1", "", "", "", "", "", "mod",
 191     "", "",
 192     "rs", "re", "", "", "", "", "", "",
 193     "", "", "", "", "", "", "", "",
 194   };
 195   if (reg_nr < 0)
 196     return NULL;
 197   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
 198     return NULL;
 199   return register_names[reg_nr];
 200 }
 201
 202 static const char *
 203 sh_sh3_dsp_register_name (int reg_nr)
 204 {
 205   static char *register_names[] = {
 206     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 207     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 208     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
 209     "", "dsr",
 210     "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
 211     "y0", "y1", "", "", "", "", "", "mod",
 212     "ssr", "spc",
 213     "rs", "re", "", "", "", "", "", "",
 214     "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
 215     "", "", "", "", "", "", "", "",
 216   };
 217   if (reg_nr < 0)
 218     return NULL;
 219   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
 220     return NULL;
 221   return register_names[reg_nr];
 222 }
 223
 224 static const char *
 225 sh_sh4_register_name (int reg_nr)
 226 {
 227   static char *register_names[] = {
 228     /* general registers 0-15 */
 229     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 230     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 231     /* 16 - 22 */
 232     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
 233     /* 23, 24 */
 234     "fpul", "fpscr",
 235     /* floating point registers 25 - 40 */
 236     "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
 237     "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
 238     /* 41, 42 */
 239     "ssr", "spc",
 240     /* bank 0 43 - 50 */
 241     "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
 242     /* bank 1 51 - 58 */
 243     "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
 244     /* double precision (pseudo) 59 - 66 */
 245     "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
 246     /* vectors (pseudo) 67 - 70 */
 247     "fv0", "fv4", "fv8", "fv12",
 248     /* FIXME: missing XF 71 - 86 */
 249     /* FIXME: missing XD 87 - 94 */
 250   };
 251   if (reg_nr < 0)
 252     return NULL;
 253   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
 254     return NULL;
 255   return register_names[reg_nr];
 256 }
 257
 258 static const char *
 259 sh_sh4_nofpu_register_name (int reg_nr)
 260 {
 261   static char *register_names[] = {
 262     /* general registers 0-15 */
 263     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 264     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 265     /* 16 - 22 */
 266     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
 267     /* 23, 24 */
 268     "", "",
 269     /* floating point registers 25 - 40 -- not for nofpu target */
 270     "", "", "", "", "", "", "", "",
 271     "", "", "", "", "", "", "", "",
 272     /* 41, 42 */
 273     "ssr", "spc",
 274     /* bank 0 43 - 50 */
 275     "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
 276     /* bank 1 51 - 58 */
 277     "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
 278     /* double precision (pseudo) 59 - 66 -- not for nofpu target */
 279     "", "", "", "", "", "", "", "",
 280     /* vectors (pseudo) 67 - 70 -- not for nofpu target */
 281     "", "", "", "",
 282   };
 283   if (reg_nr < 0)
 284     return NULL;
 285   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
 286     return NULL;
 287   return register_names[reg_nr];
 288 }
 289
 290 static const char *
 291 sh_sh4al_dsp_register_name (int reg_nr)
 292 {
 293   static char *register_names[] = {
 294     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 295     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 296     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
 297     "", "dsr",
 298     "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
 299     "y0", "y1", "", "", "", "", "", "mod",
 300     "ssr", "spc",
 301     "rs", "re", "", "", "", "", "", "",
 302     "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
 303     "", "", "", "", "", "", "", "",
 304   };
 305   if (reg_nr < 0)
 306     return NULL;
 307   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
 308     return NULL;
 309   return register_names[reg_nr];
 310 }
 311
 312 static const unsigned char *
 313 sh_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
 314 {
 315   /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
 316   static unsigned char breakpoint[] = { 0xc3, 0xc3 };
 317
 318   *lenptr = sizeof (breakpoint);
 319   return breakpoint;
 320 }
 321
 322 /* Prologue looks like
 323    mov.l        r14,@-r15
 324    sts.l        pr,@-r15
 325    mov.l        <regs>,@-r15
 326    sub          <room_for_loca_vars>,r15
 327    mov          r15,r14
 328
 329    Actually it can be more complicated than this but that's it, basically.
 330  */
 331
 332 #define GET_SOURCE_REG(x)       (((x) >> 4) & 0xf)
 333 #define GET_TARGET_REG(x)       (((x) >> 8) & 0xf)
 334
 335 /* STS.L PR,@-r15  0100111100100010
 336    r15-4-->r15, PR-->(r15) */
 337 #define IS_STS(x)               ((x) == 0x4f22)
 338
 339 /* MOV.L Rm,@-r15  00101111mmmm0110
 340    r15-4-->r15, Rm-->(R15) */
 341 #define IS_PUSH(x)              (((x) & 0xff0f) == 0x2f06)
 342
 343 /* MOV r15,r14     0110111011110011
 344    r15-->r14  */
 345 #define IS_MOV_SP_FP(x)         ((x) == 0x6ef3)
 346
 347 /* ADD #imm,r15    01111111iiiiiiii
 348    r15+imm-->r15 */
 349 #define IS_ADD_IMM_SP(x)        (((x) & 0xff00) == 0x7f00)
 350
 351 #define IS_MOV_R3(x)            (((x) & 0xff00) == 0x1a00)
 352 #define IS_SHLL_R3(x)           ((x) == 0x4300)
 353
 354 /* ADD r3,r15      0011111100111100
 355    r15+r3-->r15 */
 356 #define IS_ADD_R3SP(x)          ((x) == 0x3f3c)
 357
 358 /* FMOV.S FRm,@-Rn  Rn-4-->Rn, FRm-->(Rn)     1111nnnnmmmm1011
 359    FMOV DRm,@-Rn    Rn-8-->Rn, DRm-->(Rn)     1111nnnnmmm01011
 360    FMOV XDm,@-Rn    Rn-8-->Rn, XDm-->(Rn)     1111nnnnmmm11011 */
 361 /* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to
 362                    make this entirely clear. */
 363 /* #define IS_FMOV(x)           (((x) & 0xf00f) == 0xf00b) */
 364 #define IS_FPUSH(x)             (((x) & 0xff0f) == 0xff0b)
 365
 366 /* MOV Rm,Rn          Rm-->Rn        0110nnnnmmmm0011  4 <= m <= 7 */
 367 #define IS_MOV_ARG_TO_REG(x) \
 368         (((x) & 0xf00f) == 0x6003 && \
 369          ((x) & 0x00f0) >= 0x0040 && \
 370          ((x) & 0x00f0) <= 0x0070)
 371 /* MOV.L Rm,@Rn               0010nnnnmmmm0010  n = 14, 4 <= m <= 7 */
 372 #define IS_MOV_ARG_TO_IND_R14(x) \
 373         (((x) & 0xff0f) == 0x2e02 && \
 374          ((x) & 0x00f0) >= 0x0040 && \
 375          ((x) & 0x00f0) <= 0x0070)
 376 /* MOV.L Rm,@(disp*4,Rn)      00011110mmmmdddd  n = 14, 4 <= m <= 7 */
 377 #define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \
 378         (((x) & 0xff00) == 0x1e00 && \
 379          ((x) & 0x00f0) >= 0x0040 && \
 380          ((x) & 0x00f0) <= 0x0070)
 381
 382 /* MOV.W @(disp*2,PC),Rn      1001nnnndddddddd */
 383 #define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000)
 384 /* MOV.L @(disp*4,PC),Rn      1101nnnndddddddd */
 385 #define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000)
 386 /* SUB Rn,R15                 00111111nnnn1000 */
 387 #define IS_SUB_REG_FROM_SP(x)   (((x) & 0xff0f) == 0x3f08)
 388
 389 #define FPSCR_SZ                (1 << 20)
 390
 391 /* The following instructions are used for epilogue testing. */
 392 #define IS_RESTORE_FP(x)        ((x) == 0x6ef6)
 393 #define IS_RTS(x)               ((x) == 0x000b)
 394 #define IS_LDS(x)               ((x) == 0x4f26)
 395 #define IS_MOV_FP_SP(x)         ((x) == 0x6fe3)
 396 #define IS_ADD_REG_TO_FP(x)     (((x) & 0xff0f) == 0x3e0c)
 397 #define IS_ADD_IMM_FP(x)        (((x) & 0xff00) == 0x7e00)
 398
 399 /* Disassemble an instruction.  */
 400 static int
 401 gdb_print_insn_sh (bfd_vma memaddr, disassemble_info * info)
 402 {
 403   info->endian = TARGET_BYTE_ORDER;
 404   return print_insn_sh (memaddr, info);
 405 }
 406
 407 static CORE_ADDR
 408 sh_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc,
 409                      struct sh_frame_cache *cache)
 410 {
 411   ULONGEST inst;
 412   CORE_ADDR opc;
 413   int offset;
 414   int sav_offset = 0;
 415   int r3_val = 0;
 416   int reg, sav_reg = -1;
 417
 418   if (pc >= current_pc)
 419     return current_pc;
 420
 421   cache->uses_fp = 0;
 422   for (opc = pc + (2 * 28); pc < opc; pc += 2)
 423     {
 424       inst = read_memory_unsigned_integer (pc, 2);
 425       /* See where the registers will be saved to */
 426       if (IS_PUSH (inst))
 427         {
 428           cache->saved_regs[GET_SOURCE_REG (inst)] = cache->sp_offset;
 429           cache->sp_offset += 4;
 430         }
 431       else if (IS_STS (inst))
 432         {
 433           cache->saved_regs[PR_REGNUM] = cache->sp_offset;
 434           cache->sp_offset += 4;
 435         }
 436       else if (IS_MOV_R3 (inst))
 437         {
 438           r3_val = ((inst & 0xff) ^ 0x80) - 0x80;
 439         }
 440       else if (IS_SHLL_R3 (inst))
 441         {
 442           r3_val <<= 1;
 443         }
 444       else if (IS_ADD_R3SP (inst))
 445         {
 446           cache->sp_offset += -r3_val;
 447         }
 448       else if (IS_ADD_IMM_SP (inst))
 449         {
 450           offset = ((inst & 0xff) ^ 0x80) - 0x80;
 451           cache->sp_offset -= offset;
 452         }
 453       else if (IS_MOVW_PCREL_TO_REG (inst))
 454         {
 455           if (sav_reg < 0)
 456             {
 457               reg = GET_TARGET_REG (inst);
 458               if (reg < 14)
 459                 {
 460                   sav_reg = reg;
 461                   offset = (((inst & 0xff) ^ 0x80) - 0x80) << 1;
 462                   sav_offset =
 463                     read_memory_integer (((pc + 4) & ~3) + offset, 2);
 464                 }
 465             }
 466         }
 467       else if (IS_MOVL_PCREL_TO_REG (inst))
 468         {
 469           if (sav_reg < 0)
 470             {
 471               reg = (inst & 0x0f00) >> 8;
 472               if (reg < 14)
 473                 {
 474                   sav_reg = reg;
 475                   offset = (((inst & 0xff) ^ 0x80) - 0x80) << 1;
 476                   sav_offset =
 477                     read_memory_integer (((pc + 4) & ~3) + offset, 4);
 478                 }
 479             }
 480         }
 481       else if (IS_SUB_REG_FROM_SP (inst))
 482         {
 483           reg = GET_SOURCE_REG (inst);
 484           if (sav_reg > 0 && reg == sav_reg)
 485             {
 486               sav_reg = -1;
 487             }
 488           cache->sp_offset += sav_offset;
 489         }
 490       else if (IS_FPUSH (inst))
 491         {
 492           if (read_register (FPSCR_REGNUM) & FPSCR_SZ)
 493             {
 494               cache->sp_offset += 8;
 495             }
 496           else
 497             {
 498               cache->sp_offset += 4;
 499             }
 500         }
 501       else if (IS_MOV_SP_FP (inst))
 502         {
 503           if (!cache->uses_fp)
 504             cache->uses_fp = 1;
 505           /* At this point, only allow argument register moves to other
 506              registers or argument register moves to @(X,fp) which are
 507              moving the register arguments onto the stack area allocated
 508              by a former add somenumber to SP call.  Don't allow moving
 509              to an fp indirect address above fp + cache->sp_offset. */
 510           pc += 2;
 511           for (opc = pc + 12; pc < opc; pc += 2)
 512             {
 513               inst = read_memory_integer (pc, 2);
 514               if (IS_MOV_ARG_TO_IND_R14 (inst))
 515                 {
 516                   reg = GET_SOURCE_REG (inst);
 517                   if (cache->sp_offset > 0)
 518                     cache->saved_regs[reg] = cache->sp_offset;
 519                 }
 520               else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst))
 521                 {
 522                   reg = GET_SOURCE_REG (inst);
 523                   offset = (inst & 0xf) * 4;
 524                   if (cache->sp_offset > offset)
 525                     cache->saved_regs[reg] = cache->sp_offset - offset;
 526                 }
 527               else if (IS_MOV_ARG_TO_REG (inst))
 528                 continue;
 529               else
 530                 break;
 531             }
 532           break;
 533         }
 534 #if 0                           /* This used to just stop when it found an instruction that
 535                                    was not considered part of the prologue.  Now, we just
 536                                    keep going looking for likely instructions. */
 537       else
 538         break;
 539 #endif
 540     }
 541
 542   return pc;
 543 }
 544
 545 /* Skip any prologue before the guts of a function */
 546
 547 /* Skip the prologue using the debug information. If this fails we'll
 548    fall back on the 'guess' method below. */
 549 static CORE_ADDR
 550 after_prologue (CORE_ADDR pc)
 551 {
 552   struct symtab_and_line sal;
 553   CORE_ADDR func_addr, func_end;
 554
 555   /* If we can not find the symbol in the partial symbol table, then
 556      there is no hope we can determine the function's start address
 557      with this code.  */
 558   if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
 559     return 0;
 560
 561   /* Get the line associated with FUNC_ADDR.  */
 562   sal = find_pc_line (func_addr, 0);
 563
 564   /* There are only two cases to consider.  First, the end of the source line
 565      is within the function bounds.  In that case we return the end of the
 566      source line.  Second is the end of the source line extends beyond the
 567      bounds of the current function.  We need to use the slow code to
 568      examine instructions in that case.  */
 569   if (sal.end < func_end)
 570     return sal.end;
 571   else
 572     return 0;
 573 }
 574
 575 static CORE_ADDR
 576 sh_skip_prologue (CORE_ADDR start_pc)
 577 {
 578   CORE_ADDR pc;
 579   struct sh_frame_cache cache;
 580
 581   /* See if we can determine the end of the prologue via the symbol table.
 582      If so, then return either PC, or the PC after the prologue, whichever
 583      is greater.  */
 584   pc = after_prologue (start_pc);
 585
 586   /* If after_prologue returned a useful address, then use it.  Else
 587      fall back on the instruction skipping code. */
 588   if (pc)
 589     return max (pc, start_pc);
 590
 591   cache.sp_offset = -4;
 592   pc = sh_analyze_prologue (start_pc, (CORE_ADDR) -1, &cache);
 593   if (!cache.uses_fp)
 594     return start_pc;
 595
 596   return pc;
 597 }
 598
 599 /* The ABI says:
 600
 601    Aggregate types not bigger than 8 bytes that have the same size and
 602    alignment as one of the integer scalar types are returned in the
 603    same registers as the integer type they match.
 604
 605    For example, a 2-byte aligned structure with size 2 bytes has the
 606    same size and alignment as a short int, and will be returned in R0.
 607    A 4-byte aligned structure with size 8 bytes has the same size and
 608    alignment as a long long int, and will be returned in R0 and R1.
 609
 610    When an aggregate type is returned in R0 and R1, R0 contains the
 611    first four bytes of the aggregate, and R1 contains the
 612    remainder. If the size of the aggregate type is not a multiple of 4
 613    bytes, the aggregate is tail-padded up to a multiple of 4
 614    bytes. The value of the padding is undefined. For little-endian
 615    targets the padding will appear at the most significant end of the
 616    last element, for big-endian targets the padding appears at the
 617    least significant end of the last element.
 618
 619    All other aggregate types are returned by address. The caller
 620    function passes the address of an area large enough to hold the
 621    aggregate value in R2. The called function stores the result in
 622    this location.
 623
 624    To reiterate, structs smaller than 8 bytes could also be returned
 625    in memory, if they don't pass the "same size and alignment as an
 626    integer type" rule.
 627
 628    For example, in
 629
 630    struct s { char c[3]; } wibble;
 631    struct s foo(void) {  return wibble; }
 632
 633    the return value from foo() will be in memory, not
 634    in R0, because there is no 3-byte integer type.
 635
 636    Similarly, in
 637
 638    struct s { char c[2]; } wibble;
 639    struct s foo(void) {  return wibble; }
 640
 641    because a struct containing two chars has alignment 1, that matches
 642    type char, but size 2, that matches type short.  There's no integer
 643    type that has alignment 1 and size 2, so the struct is returned in
 644    memory.
 645
 646 */
 647
 648 static int
 649 sh_use_struct_convention (int gcc_p, struct type *type)
 650 {
 651   int len = TYPE_LENGTH (type);
 652   int nelem = TYPE_NFIELDS (type);
 653
 654   /* Non-power of 2 length types and types bigger than 8 bytes (which don't
 655      fit in two registers anyway) use struct convention.  */
 656   if (len != 1 && len != 2 && len != 4 && len != 8)
 657     return 1;
 658
 659   /* Scalar types and aggregate types with exactly one field are aligned
 660      by definition.  They are returned in registers.  */
 661   if (nelem <= 1)
 662     return 0;
 663
 664   /* If the first field in the aggregate has the same length as the entire
 665      aggregate type, the type is returned in registers.  */
 666   if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == len)
 667     return 0;
 668
 669   /* If the size of the aggregate is 8 bytes and the first field is
 670      of size 4 bytes its alignment is equal to long long's alignment,
 671      so it's returned in registers.  */
 672   if (len == 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == 4)
 673     return 0;
 674
 675   /* Otherwise use struct convention.  */
 676   return 1;
 677 }
 678
 679 /* Extract from an array REGBUF containing the (raw) register state
 680    the address in which a function should return its structure value,
 681    as a CORE_ADDR (or an expression that can be used as one).  */
 682 static CORE_ADDR
 683 sh_extract_struct_value_address (struct regcache *regcache)
 684 {
 685   ULONGEST addr;
 686
 687   regcache_cooked_read_unsigned (regcache, STRUCT_RETURN_REGNUM, &addr);
 688   return addr;
 689 }
 690
 691 static CORE_ADDR
 692 sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
 693 {
 694   return sp & ~3;
 695 }
 696
 697 /* Function: push_dummy_call (formerly push_arguments)
 698    Setup the function arguments for calling a function in the inferior.
 699
 700    On the Renesas SH architecture, there are four registers (R4 to R7)
 701    which are dedicated for passing function arguments.  Up to the first
 702    four arguments (depending on size) may go into these registers.
 703    The rest go on the stack.
 704
 705    MVS: Except on SH variants that have floating point registers.
 706    In that case, float and double arguments are passed in the same
 707    manner, but using FP registers instead of GP registers.
 708
 709    Arguments that are smaller than 4 bytes will still take up a whole
 710    register or a whole 32-bit word on the stack, and will be
 711    right-justified in the register or the stack word.  This includes
 712    chars, shorts, and small aggregate types.
 713
 714    Arguments that are larger than 4 bytes may be split between two or
 715    more registers.  If there are not enough registers free, an argument
 716    may be passed partly in a register (or registers), and partly on the
 717    stack.  This includes doubles, long longs, and larger aggregates.
 718    As far as I know, there is no upper limit to the size of aggregates
 719    that will be passed in this way; in other words, the convention of
 720    passing a pointer to a large aggregate instead of a copy is not used.
 721
 722    MVS: The above appears to be true for the SH variants that do not
 723    have an FPU, however those that have an FPU appear to copy the
 724    aggregate argument onto the stack (and not place it in registers)
 725    if it is larger than 16 bytes (four GP registers).
 726
 727    An exceptional case exists for struct arguments (and possibly other
 728    aggregates such as arrays) if the size is larger than 4 bytes but
 729    not a multiple of 4 bytes.  In this case the argument is never split
 730    between the registers and the stack, but instead is copied in its
 731    entirety onto the stack, AND also copied into as many registers as
 732    there is room for.  In other words, space in registers permitting,
 733    two copies of the same argument are passed in.  As far as I can tell,
 734    only the one on the stack is used, although that may be a function
 735    of the level of compiler optimization.  I suspect this is a compiler
 736    bug.  Arguments of these odd sizes are left-justified within the
 737    word (as opposed to arguments smaller than 4 bytes, which are
 738    right-justified).
 739
 740    If the function is to return an aggregate type such as a struct, it
 741    is either returned in the normal return value register R0 (if its
 742    size is no greater than one byte), or else the caller must allocate
 743    space into which the callee will copy the return value (if the size
 744    is greater than one byte).  In this case, a pointer to the return
 745    value location is passed into the callee in register R2, which does
 746    not displace any of the other arguments passed in via registers R4
 747    to R7.   */
 748
 749 /* Helper function to justify value in register according to endianess. */
 750 static char *
 751 sh_justify_value_in_reg (struct value *val, int len)
 752 {
 753   static char valbuf[4];
 754
 755   memset (valbuf, 0, sizeof (valbuf));
 756   if (len < 4)
 757     {
 758       /* value gets right-justified in the register or stack word */
 759       if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
 760         memcpy (valbuf + (4 - len), (char *) VALUE_CONTENTS (val), len);
 761       else
 762         memcpy (valbuf, (char *) VALUE_CONTENTS (val), len);
 763       return valbuf;
 764     }
 765   return (char *) VALUE_CONTENTS (val);
 766 }
 767
 768 /* Helper function to eval number of bytes to allocate on stack. */
 769 static CORE_ADDR
 770 sh_stack_allocsize (int nargs, struct value **args)
 771 {
 772   int stack_alloc = 0;
 773   while (nargs-- > 0)
 774     stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[nargs])) + 3) & ~3);
 775   return stack_alloc;
 776 }
 777
 778 /* Helper functions for getting the float arguments right.  Registers usage
 779    depends on the ABI and the endianess.  The comments should enlighten how
 780    it's intended to work. */
 781
 782 /* This array stores which of the float arg registers are already in use. */
 783 static int flt_argreg_array[FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM + 1];
 784
 785 /* This function just resets the above array to "no reg used so far". */
 786 static void
 787 sh_init_flt_argreg (void)
 788 {
 789   memset (flt_argreg_array, 0, sizeof flt_argreg_array);
 790 }
 791
 792 /* This function returns the next register to use for float arg passing.
 793    It returns either a valid value between FLOAT_ARG0_REGNUM and
 794    FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns
 795    FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available.
 796
 797    Note that register number 0 in flt_argreg_array corresponds with the
 798    real float register fr4.  In contrast to FLOAT_ARG0_REGNUM (value is
 799    29) the parity of the register number is preserved, which is important
 800    for the double register passing test (see the "argreg & 1" test below). */
 801 static int
 802 sh_next_flt_argreg (int len)
 803 {
 804   int argreg;
 805
 806   /* First search for the next free register. */
 807   for (argreg = 0; argreg <= FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM;
 808        ++argreg)
 809     if (!flt_argreg_array[argreg])
 810       break;
 811
 812   /* No register left? */
 813   if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
 814     return FLOAT_ARGLAST_REGNUM + 1;
 815
 816   if (len == 8)
 817     {
 818       /* Doubles are always starting in a even register number. */
 819       if (argreg & 1)
 820         {
 821           flt_argreg_array[argreg] = 1;
 822
 823           ++argreg;
 824
 825           /* No register left? */
 826           if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
 827             return FLOAT_ARGLAST_REGNUM + 1;
 828         }
 829       /* Also mark the next register as used. */
 830       flt_argreg_array[argreg + 1] = 1;
 831     }
 832   else if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
 833     {
 834       /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */
 835       if (!flt_argreg_array[argreg + 1])
 836         ++argreg;
 837     }
 838   flt_argreg_array[argreg] = 1;
 839   return FLOAT_ARG0_REGNUM + argreg;
 840 }
 841
 842 /* Helper function which figures out, if a type is treated like a float type.
 843
 844    The FPU ABIs have a special way how to treat types as float types.
 845    Structures with exactly one member, which is of type float or double, are
 846    treated exactly as the base types float or double:
 847
 848      struct sf {
 849        float f;
 850      };
 851
 852      struct sd {
 853        double d;
 854      };
 855
 856    are handled the same way as just
 857
 858      float f;
 859
 860      double d;
 861
 862    As a result, arguments of these struct types are pushed into floating point
 863    registers exactly as floats or doubles, using the same decision algorithm.
 864
 865    The same is valid if these types are used as function return types.  The
 866    above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1
 867    or even using struct convention as it is for other structs.  */
 868
 869 static int
 870 sh_treat_as_flt_p (struct type *type)
 871 {
 872   int len = TYPE_LENGTH (type);
 873
 874   /* Ordinary float types are obviously treated as float.  */
 875   if (TYPE_CODE (type) == TYPE_CODE_FLT)
 876     return 1;
 877   /* Otherwise non-struct types are not treated as float.  */
 878   if (TYPE_CODE (type) != TYPE_CODE_STRUCT)
 879     return 0;
 880   /* Otherwise structs with more than one memeber are not treated as float.  */
 881   if (TYPE_NFIELDS (type) != 1)
 882     return 0;
 883   /* Otherwise if the type of that member is float, the whole type is
 884      treated as float.  */
 885   if (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) == TYPE_CODE_FLT)
 886     return 1;
 887   /* Otherwise it's not treated as float.  */
 888   return 0;
 889 }
 890
 891 static CORE_ADDR
 892 sh_push_dummy_call_fpu (struct gdbarch *gdbarch,
 893                         CORE_ADDR func_addr,
 894                         struct regcache *regcache,
 895                         CORE_ADDR bp_addr, int nargs,
 896                         struct value **args,
 897                         CORE_ADDR sp, int struct_return,
 898                         CORE_ADDR struct_addr)
 899 {
 900   int stack_offset = 0;
 901   int argreg = ARG0_REGNUM;
 902   int flt_argreg = 0;
 903   int argnum;
 904   struct type *type;
 905   CORE_ADDR regval;
 906   char *val;
 907   int len, reg_size = 0;
 908   int pass_on_stack = 0;
 909   int treat_as_flt;
 910
 911   /* first force sp to a 4-byte alignment */
 912   sp = sh_frame_align (gdbarch, sp);
 913
 914   if (struct_return)
 915     regcache_cooked_write_unsigned (regcache,
 916                                     STRUCT_RETURN_REGNUM, struct_addr);
 917
 918   /* make room on stack for args */
 919   sp -= sh_stack_allocsize (nargs, args);
 920
 921   /* Initialize float argument mechanism. */
 922   sh_init_flt_argreg ();
 923
 924   /* Now load as many as possible of the first arguments into
 925      registers, and push the rest onto the stack.  There are 16 bytes
 926      in four registers available.  Loop thru args from first to last.  */
 927   for (argnum = 0; argnum < nargs; argnum++)
 928     {
 929       type = VALUE_TYPE (args[argnum]);
 930       len = TYPE_LENGTH (type);
 931       val = sh_justify_value_in_reg (args[argnum], len);
 932
 933       /* Some decisions have to be made how various types are handled.
 934          This also differs in different ABIs. */
 935       pass_on_stack = 0;
 936
 937       /* Find out the next register to use for a floating point value. */
 938       treat_as_flt = sh_treat_as_flt_p (type);
 939       if (treat_as_flt)
 940         flt_argreg = sh_next_flt_argreg (len);
 941       /* In contrast to non-FPU CPUs, arguments are never split between
 942          registers and stack.  If an argument doesn't fit in the remaining
 943          registers it's always pushed entirely on the stack.  */
 944       else if (len > ((ARGLAST_REGNUM - argreg + 1) * 4))
 945         pass_on_stack = 1;
 946
 947       while (len > 0)
 948         {
 949           if ((treat_as_flt && flt_argreg > FLOAT_ARGLAST_REGNUM)
 950               || (!treat_as_flt && (argreg > ARGLAST_REGNUM
 951                                     || pass_on_stack)))
 952             {
 953               /* The data goes entirely on the stack, 4-byte aligned. */
 954               reg_size = (len + 3) & ~3;
 955               write_memory (sp + stack_offset, val, reg_size);
 956               stack_offset += reg_size;
 957             }
 958           else if (treat_as_flt && flt_argreg <= FLOAT_ARGLAST_REGNUM)
 959             {
 960               /* Argument goes in a float argument register.  */
 961               reg_size = register_size (gdbarch, flt_argreg);
 962               regval = extract_unsigned_integer (val, reg_size);
 963               /* In little endian mode, float types taking two registers
 964                  (doubles on sh4, long doubles on sh2e, sh3e and sh4) must
 965                  be stored swapped in the argument registers.  The below
 966                  code first writes the first 32 bits in the next but one
 967                  register, increments the val and len values accordingly
 968                  and then proceeds as normal by writing the second 32 bits
 969                  into the next register. */
 970               if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE
 971                   && TYPE_LENGTH (type) == 2 * reg_size)
 972                 {
 973                   regcache_cooked_write_unsigned (regcache, flt_argreg + 1,
 974                                                   regval);
 975                   val += reg_size;
 976                   len -= reg_size;
 977                   regval = extract_unsigned_integer (val, reg_size);
 978                 }
 979               regcache_cooked_write_unsigned (regcache, flt_argreg++, regval);
 980             }
 981           else if (!treat_as_flt && argreg <= ARGLAST_REGNUM)
 982             {
 983               /* there's room in a register */
 984               reg_size = register_size (gdbarch, argreg);
 985               regval = extract_unsigned_integer (val, reg_size);
 986               regcache_cooked_write_unsigned (regcache, argreg++, regval);
 987             }
 988           /* Store the value one register at a time or in one step on stack.  */
 989           len -= reg_size;
 990           val += reg_size;
 991         }
 992     }
 993
 994   /* Store return address. */
 995   regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
 996
 997   /* Update stack pointer.  */
 998   regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp);
 999
1000   return sp;
1001 }
1002
1003 static CORE_ADDR
1004 sh_push_dummy_call_nofpu (struct gdbarch *gdbarch,
1005                           CORE_ADDR func_addr,
1006                           struct regcache *regcache,
1007                           CORE_ADDR bp_addr,
1008                           int nargs, struct value **args,
1009                           CORE_ADDR sp, int struct_return,
1010                           CORE_ADDR struct_addr)
1011 {
1012   int stack_offset = 0;
1013   int argreg = ARG0_REGNUM;
1014   int argnum;
1015   struct type *type;
1016   CORE_ADDR regval;
1017   char *val;
1018   int len, reg_size;
1019
1020   /* first force sp to a 4-byte alignment */
1021   sp = sh_frame_align (gdbarch, sp);
1022
1023   if (struct_return)
1024     regcache_cooked_write_unsigned (regcache,
1025                                     STRUCT_RETURN_REGNUM, struct_addr);
1026
1027   /* make room on stack for args */
1028   sp -= sh_stack_allocsize (nargs, args);
1029
1030   /* Now load as many as possible of the first arguments into
1031      registers, and push the rest onto the stack.  There are 16 bytes
1032      in four registers available.  Loop thru args from first to last.  */
1033   for (argnum = 0; argnum < nargs; argnum++)
1034     {
1035       type = VALUE_TYPE (args[argnum]);
1036       len = TYPE_LENGTH (type);
1037       val = sh_justify_value_in_reg (args[argnum], len);
1038
1039       while (len > 0)
1040         {
1041           if (argreg > ARGLAST_REGNUM)
1042             {
1043               /* The remainder of the data goes entirely on the stack,
1044                  4-byte aligned. */
1045               reg_size = (len + 3) & ~3;
1046               write_memory (sp + stack_offset, val, reg_size);
1047               stack_offset += reg_size;
1048             }
1049           else if (argreg <= ARGLAST_REGNUM)
1050             {
1051               /* there's room in a register */
1052               reg_size = register_size (gdbarch, argreg);
1053               regval = extract_unsigned_integer (val, reg_size);
1054               regcache_cooked_write_unsigned (regcache, argreg++, regval);
1055             }
1056           /* Store the value reg_size bytes at a time.  This means that things
1057              larger than reg_size bytes may go partly in registers and partly
1058              on the stack.  */
1059           len -= reg_size;
1060           val += reg_size;
1061         }
1062     }
1063
1064   /* Store return address. */
1065   regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
1066
1067   /* Update stack pointer.  */
1068   regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp);
1069
1070   return sp;
1071 }
1072
1073 /* Find a function's return value in the appropriate registers (in
1074    regbuf), and copy it into valbuf.  Extract from an array REGBUF
1075    containing the (raw) register state a function return value of type
1076    TYPE, and copy that, in virtual format, into VALBUF.  */
1077 static void
1078 sh_default_extract_return_value (struct type *type, struct regcache *regcache,
1079                                  void *valbuf)
1080 {
1081   int len = TYPE_LENGTH (type);
1082   int return_register = R0_REGNUM;
1083   int offset;
1084
1085   if (len <= 4)
1086     {
1087       ULONGEST c;
1088
1089       regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c);
1090       store_unsigned_integer (valbuf, len, c);
1091     }
1092   else if (len == 8)
1093     {
1094       int i, regnum = R0_REGNUM;
1095       for (i = 0; i < len; i += 4)
1096         regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
1097     }
1098   else
1099     error ("bad size for return value");
1100 }
1101
1102 static void
1103 sh3e_sh4_extract_return_value (struct type *type, struct regcache *regcache,
1104                                void *valbuf)
1105 {
1106   if (sh_treat_as_flt_p (type))
1107     {
1108       int len = TYPE_LENGTH (type);
1109       int i, regnum = FP0_REGNUM;
1110       for (i = 0; i < len; i += 4)
1111         if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
1112           regcache_raw_read (regcache, regnum++, (char *) valbuf + len - 4 - i);
1113         else
1114           regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
1115     }
1116   else
1117     sh_default_extract_return_value (type, regcache, valbuf);
1118 }
1119
1120 /* Write into appropriate registers a function return value
1121    of type TYPE, given in virtual format.
1122    If the architecture is sh4 or sh3e, store a function's return value
1123    in the R0 general register or in the FP0 floating point register,
1124    depending on the type of the return value. In all the other cases
1125    the result is stored in r0, left-justified. */
1126 static void
1127 sh_default_store_return_value (struct type *type, struct regcache *regcache,
1128                                const void *valbuf)
1129 {
1130   ULONGEST val;
1131   int len = TYPE_LENGTH (type);
1132
1133   if (len <= 4)
1134     {
1135       val = extract_unsigned_integer (valbuf, len);
1136       regcache_cooked_write_unsigned (regcache, R0_REGNUM, val);
1137     }
1138   else
1139     {
1140       int i, regnum = R0_REGNUM;
1141       for (i = 0; i < len; i += 4)
1142         regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
1143     }
1144 }
1145
1146 static void
1147 sh3e_sh4_store_return_value (struct type *type, struct regcache *regcache,
1148                              const void *valbuf)
1149 {
1150   if (sh_treat_as_flt_p (type))
1151     {
1152       int len = TYPE_LENGTH (type);
1153       int i, regnum = FP0_REGNUM;
1154       for (i = 0; i < len; i += 4)
1155         regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
1156     }
1157   else
1158     sh_default_store_return_value (type, regcache, valbuf);
1159 }
1160
1161 /* Print the registers in a form similar to the E7000 */
1162
1163 static void
1164 sh_generic_show_regs (void)
1165 {
1166   printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1167                    paddr (read_register (PC_REGNUM)),
1168                    (long) read_register (SR_REGNUM),
1169                    (long) read_register (PR_REGNUM),
1170                    (long) read_register (MACH_REGNUM),
1171                    (long) read_register (MACL_REGNUM));
1172
1173   printf_filtered ("GBR=%08lx VBR=%08lx",
1174                    (long) read_register (GBR_REGNUM),
1175                    (long) read_register (VBR_REGNUM));
1176
1177   printf_filtered
1178     ("\nR0-R7  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1179      (long) read_register (0), (long) read_register (1),
1180      (long) read_register (2), (long) read_register (3),
1181      (long) read_register (4), (long) read_register (5),
1182      (long) read_register (6), (long) read_register (7));
1183   printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1184                    (long) read_register (8), (long) read_register (9),
1185                    (long) read_register (10), (long) read_register (11),
1186                    (long) read_register (12), (long) read_register (13),
1187                    (long) read_register (14), (long) read_register (15));
1188 }
1189
1190 static void
1191 sh3_show_regs (void)
1192 {
1193   printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1194                    paddr (read_register (PC_REGNUM)),
1195                    (long) read_register (SR_REGNUM),
1196                    (long) read_register (PR_REGNUM),
1197                    (long) read_register (MACH_REGNUM),
1198                    (long) read_register (MACL_REGNUM));
1199
1200   printf_filtered ("GBR=%08lx VBR=%08lx",
1201                    (long) read_register (GBR_REGNUM),
1202                    (long) read_register (VBR_REGNUM));
1203   printf_filtered (" SSR=%08lx SPC=%08lx",
1204                    (long) read_register (SSR_REGNUM),
1205                    (long) read_register (SPC_REGNUM));
1206
1207   printf_filtered
1208     ("\nR0-R7  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1209      (long) read_register (0), (long) read_register (1),
1210      (long) read_register (2), (long) read_register (3),
1211      (long) read_register (4), (long) read_register (5),
1212      (long) read_register (6), (long) read_register (7));
1213   printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1214                    (long) read_register (8), (long) read_register (9),
1215                    (long) read_register (10), (long) read_register (11),
1216                    (long) read_register (12), (long) read_register (13),
1217                    (long) read_register (14), (long) read_register (15));
1218 }
1219
1220
1221 static void
1222 sh2e_show_regs (void)
1223 {
1224   printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1225                    paddr (read_register (PC_REGNUM)),
1226                    (long) read_register (SR_REGNUM),
1227                    (long) read_register (PR_REGNUM),
1228                    (long) read_register (MACH_REGNUM),
1229                    (long) read_register (MACL_REGNUM));
1230
1231   printf_filtered ("GBR=%08lx VBR=%08lx",
1232                    (long) read_register (GBR_REGNUM),
1233                    (long) read_register (VBR_REGNUM));
1234   printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1235                    (long) read_register (FPUL_REGNUM),
1236                    (long) read_register (FPSCR_REGNUM));
1237
1238   printf_filtered
1239     ("\nR0-R7  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1240      (long) read_register (0), (long) read_register (1),
1241      (long) read_register (2), (long) read_register (3),
1242      (long) read_register (4), (long) read_register (5),
1243      (long) read_register (6), (long) read_register (7));
1244   printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1245                    (long) read_register (8), (long) read_register (9),
1246                    (long) read_register (10), (long) read_register (11),
1247                    (long) read_register (12), (long) read_register (13),
1248                    (long) read_register (14), (long) read_register (15));
1249
1250   printf_filtered (("FP0-FP7  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 0), (long) read_register (FP0_REGNUM + 1), (long) read_register (FP0_REGNUM + 2), (long) read_register (FP0_REGNUM + 3), (long) read_register (FP0_REGNUM + 4), (long) read_register (FP0_REGNUM + 5), (long) read_register (FP0_REGNUM + 6), (long) read_register (FP0_REGNUM + 7));
1251   printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 8), (long) read_register (FP0_REGNUM + 9), (long) read_register (FP0_REGNUM + 10), (long) read_register (FP0_REGNUM + 11), (long) read_register (FP0_REGNUM + 12), (long) read_register (FP0_REGNUM + 13), (long) read_register (FP0_REGNUM + 14), (long) read_register (FP0_REGNUM + 15));
1252 }
1253
1254 static void
1255 sh3e_show_regs (void)
1256 {
1257   printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1258                    paddr (read_register (PC_REGNUM)),
1259                    (long) read_register (SR_REGNUM),
1260                    (long) read_register (PR_REGNUM),
1261                    (long) read_register (MACH_REGNUM),
1262                    (long) read_register (MACL_REGNUM));
1263
1264   printf_filtered ("GBR=%08lx VBR=%08lx",
1265                    (long) read_register (GBR_REGNUM),
1266                    (long) read_register (VBR_REGNUM));
1267   printf_filtered (" SSR=%08lx SPC=%08lx",
1268                    (long) read_register (SSR_REGNUM),
1269                    (long) read_register (SPC_REGNUM));
1270   printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1271                    (long) read_register (FPUL_REGNUM),
1272                    (long) read_register (FPSCR_REGNUM));
1273
1274   printf_filtered
1275     ("\nR0-R7  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1276      (long) read_register (0), (long) read_register (1),
1277      (long) read_register (2), (long) read_register (3),
1278      (long) read_register (4), (long) read_register (5),
1279      (long) read_register (6), (long) read_register (7));
1280   printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1281                    (long) read_register (8), (long) read_register (9),
1282                    (long) read_register (10), (long) read_register (11),
1283                    (long) read_register (12), (long) read_register (13),
1284                    (long) read_register (14), (long) read_register (15));
1285
1286   printf_filtered (("FP0-FP7  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 0), (long) read_register (FP0_REGNUM + 1), (long) read_register (FP0_REGNUM + 2), (long) read_register (FP0_REGNUM + 3), (long) read_register (FP0_REGNUM + 4), (long) read_register (FP0_REGNUM + 5), (long) read_register (FP0_REGNUM + 6), (long) read_register (FP0_REGNUM + 7));
1287   printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 8), (long) read_register (FP0_REGNUM + 9), (long) read_register (FP0_REGNUM + 10), (long) read_register (FP0_REGNUM + 11), (long) read_register (FP0_REGNUM + 12), (long) read_register (FP0_REGNUM + 13), (long) read_register (FP0_REGNUM + 14), (long) read_register (FP0_REGNUM + 15));
1288 }
1289
1290 static void
1291 sh3_dsp_show_regs (void)
1292 {
1293   printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1294                    paddr (read_register (PC_REGNUM)),
1295                    (long) read_register (SR_REGNUM),
1296                    (long) read_register (PR_REGNUM),
1297                    (long) read_register (MACH_REGNUM),
1298                    (long) read_register (MACL_REGNUM));
1299
1300   printf_filtered ("GBR=%08lx VBR=%08lx",
1301                    (long) read_register (GBR_REGNUM),
1302                    (long) read_register (VBR_REGNUM));
1303
1304   printf_filtered (" SSR=%08lx SPC=%08lx",
1305                    (long) read_register (SSR_REGNUM),
1306                    (long) read_register (SPC_REGNUM));
1307
1308   printf_filtered (" DSR=%08lx", (long) read_register (DSR_REGNUM));
1309
1310   printf_filtered
1311     ("\nR0-R7  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1312      (long) read_register (0), (long) read_register (1),
1313      (long) read_register (2), (long) read_register (3),
1314      (long) read_register (4), (long) read_register (5),
1315      (long) read_register (6), (long) read_register (7));
1316   printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1317                    (long) read_register (8), (long) read_register (9),
1318                    (long) read_register (10), (long) read_register (11),
1319                    (long) read_register (12), (long) read_register (13),
1320                    (long) read_register (14), (long) read_register (15));
1321
1322   printf_filtered
1323     ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1324      (long) read_register (A0G_REGNUM) & 0xff,
1325      (long) read_register (A0_REGNUM), (long) read_register (M0_REGNUM),
1326      (long) read_register (X0_REGNUM), (long) read_register (Y0_REGNUM),
1327      (long) read_register (RS_REGNUM), (long) read_register (MOD_REGNUM));
1328   printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1329                    (long) read_register (A1G_REGNUM) & 0xff,
1330                    (long) read_register (A1_REGNUM),
1331                    (long) read_register (M1_REGNUM),
1332                    (long) read_register (X1_REGNUM),
1333                    (long) read_register (Y1_REGNUM),
1334                    (long) read_register (RE_REGNUM));
1335 }
1336
1337 static void
1338 sh4_show_regs (void)
1339 {
1340   int pr = read_register (FPSCR_REGNUM) & 0x80000;
1341   printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1342                    paddr (read_register (PC_REGNUM)),
1343                    (long) read_register (SR_REGNUM),
1344                    (long) read_register (PR_REGNUM),
1345                    (long) read_register (MACH_REGNUM),
1346                    (long) read_register (MACL_REGNUM));
1347
1348   printf_filtered ("GBR=%08lx VBR=%08lx",
1349                    (long) read_register (GBR_REGNUM),
1350                    (long) read_register (VBR_REGNUM));
1351   printf_filtered (" SSR=%08lx SPC=%08lx",
1352                    (long) read_register (SSR_REGNUM),
1353                    (long) read_register (SPC_REGNUM));
1354   printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1355                    (long) read_register (FPUL_REGNUM),
1356                    (long) read_register (FPSCR_REGNUM));
1357
1358   printf_filtered
1359     ("\nR0-R7  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1360      (long) read_register (0), (long) read_register (1),
1361      (long) read_register (2), (long) read_register (3),
1362      (long) read_register (4), (long) read_register (5),
1363      (long) read_register (6), (long) read_register (7));
1364   printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1365                    (long) read_register (8), (long) read_register (9),
1366                    (long) read_register (10), (long) read_register (11),
1367                    (long) read_register (12), (long) read_register (13),
1368                    (long) read_register (14), (long) read_register (15));
1369
1370   printf_filtered ((pr
1371                     ? "DR0-DR6  %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1372                     :
1373                     "FP0-FP7  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1374                    (long) read_register (FP0_REGNUM + 0),
1375                    (long) read_register (FP0_REGNUM + 1),
1376                    (long) read_register (FP0_REGNUM + 2),
1377                    (long) read_register (FP0_REGNUM + 3),
1378                    (long) read_register (FP0_REGNUM + 4),
1379                    (long) read_register (FP0_REGNUM + 5),
1380                    (long) read_register (FP0_REGNUM + 6),
1381                    (long) read_register (FP0_REGNUM + 7));
1382   printf_filtered ((pr ?
1383                     "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" :
1384                     "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1385                    (long) read_register (FP0_REGNUM + 8),
1386                    (long) read_register (FP0_REGNUM + 9),
1387                    (long) read_register (FP0_REGNUM + 10),
1388                    (long) read_register (FP0_REGNUM + 11),
1389                    (long) read_register (FP0_REGNUM + 12),
1390                    (long) read_register (FP0_REGNUM + 13),
1391                    (long) read_register (FP0_REGNUM + 14),
1392                    (long) read_register (FP0_REGNUM + 15));
1393 }
1394
1395 static void
1396 sh4_nofpu_show_regs (void)
1397 {
1398   printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1399                    paddr (read_register (PC_REGNUM)),
1400                    (long) read_register (SR_REGNUM),
1401                    (long) read_register (PR_REGNUM),
1402                    (long) read_register (MACH_REGNUM),
1403                    (long) read_register (MACL_REGNUM));
1404
1405   printf_filtered ("GBR=%08lx VBR=%08lx",
1406                    (long) read_register (GBR_REGNUM),
1407                    (long) read_register (VBR_REGNUM));
1408   printf_filtered (" SSR=%08lx SPC=%08lx",
1409                    (long) read_register (SSR_REGNUM),
1410                    (long) read_register (SPC_REGNUM));
1411
1412   printf_filtered
1413     ("\nR0-R7  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1414      (long) read_register (0), (long) read_register (1),
1415      (long) read_register (2), (long) read_register (3),
1416      (long) read_register (4), (long) read_register (5),
1417      (long) read_register (6), (long) read_register (7));
1418   printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1419                    (long) read_register (8), (long) read_register (9),
1420                    (long) read_register (10), (long) read_register (11),
1421                    (long) read_register (12), (long) read_register (13),
1422                    (long) read_register (14), (long) read_register (15));
1423 }
1424
1425 static void
1426 sh_dsp_show_regs (void)
1427 {
1428   printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1429                    paddr (read_register (PC_REGNUM)),
1430                    (long) read_register (SR_REGNUM),
1431                    (long) read_register (PR_REGNUM),
1432                    (long) read_register (MACH_REGNUM),
1433                    (long) read_register (MACL_REGNUM));
1434
1435   printf_filtered ("GBR=%08lx VBR=%08lx",
1436                    (long) read_register (GBR_REGNUM),
1437                    (long) read_register (VBR_REGNUM));
1438
1439   printf_filtered (" DSR=%08lx", (long) read_register (DSR_REGNUM));
1440
1441   printf_filtered
1442     ("\nR0-R7  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1443      (long) read_register (0), (long) read_register (1),
1444      (long) read_register (2), (long) read_register (3),
1445      (long) read_register (4), (long) read_register (5),
1446      (long) read_register (6), (long) read_register (7));
1447   printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1448                    (long) read_register (8), (long) read_register (9),
1449                    (long) read_register (10), (long) read_register (11),
1450                    (long) read_register (12), (long) read_register (13),
1451                    (long) read_register (14), (long) read_register (15));
1452
1453   printf_filtered
1454     ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1455      (long) read_register (A0G_REGNUM) & 0xff,
1456      (long) read_register (A0_REGNUM), (long) read_register (M0_REGNUM),
1457      (long) read_register (X0_REGNUM), (long) read_register (Y0_REGNUM),
1458      (long) read_register (RS_REGNUM), (long) read_register (MOD_REGNUM));
1459   printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1460                    (long) read_register (A1G_REGNUM) & 0xff,
1461                    (long) read_register (A1_REGNUM),
1462                    (long) read_register (M1_REGNUM),
1463                    (long) read_register (X1_REGNUM),
1464                    (long) read_register (Y1_REGNUM),
1465                    (long) read_register (RE_REGNUM));
1466 }
1467
1468 static void
1469 sh_show_regs_command (char *args, int from_tty)
1470 {
1471   if (sh_show_regs)
1472     (*sh_show_regs) ();
1473 }
1474
1475 /* Return the GDB type object for the "standard" data type
1476    of data in register N.  */
1477 static struct type *
1478 sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr)
1479 {
1480   if ((reg_nr >= FP0_REGNUM
1481        && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
1482     return builtin_type_float;
1483   else
1484     return builtin_type_int;
1485 }
1486
1487 static struct type *
1488 sh_sh4_build_float_register_type (int high)
1489 {
1490   struct type *temp;
1491
1492   temp = create_range_type (NULL, builtin_type_int, 0, high);
1493   return create_array_type (NULL, builtin_type_float, temp);
1494 }
1495
1496 static struct type *
1497 sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr)
1498 {
1499   if ((reg_nr >= FP0_REGNUM
1500        && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
1501     return builtin_type_float;
1502   else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
1503     return builtin_type_double;
1504   else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
1505     return sh_sh4_build_float_register_type (3);
1506   else
1507     return builtin_type_int;
1508 }
1509
1510 static struct type *
1511 sh_default_register_type (struct gdbarch *gdbarch, int reg_nr)
1512 {
1513   return builtin_type_int;
1514 }
1515
1516 /* On the sh4, the DRi pseudo registers are problematic if the target
1517    is little endian. When the user writes one of those registers, for
1518    instance with 'ser var $dr0=1', we want the double to be stored
1519    like this:
1520    fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1521    fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1522
1523    This corresponds to little endian byte order & big endian word
1524    order.  However if we let gdb write the register w/o conversion, it
1525    will write fr0 and fr1 this way:
1526    fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1527    fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1528    because it will consider fr0 and fr1 as a single LE stretch of memory.
1529
1530    To achieve what we want we must force gdb to store things in
1531    floatformat_ieee_double_littlebyte_bigword (which is defined in
1532    include/floatformat.h and libiberty/floatformat.c.
1533
1534    In case the target is big endian, there is no problem, the
1535    raw bytes will look like:
1536    fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
1537    fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1538
1539    The other pseudo registers (the FVs) also don't pose a problem
1540    because they are stored as 4 individual FP elements. */
1541
1542 static void
1543 sh_sh4_register_convert_to_virtual (int regnum, struct type *type,
1544                                     char *from, char *to)
1545 {
1546   if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
1547     {
1548       DOUBLEST val;
1549       floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
1550                                from, &val);
1551       store_typed_floating (to, type, val);
1552     }
1553   else
1554     error
1555       ("sh_register_convert_to_virtual called with non DR register number");
1556 }
1557
1558 static void
1559 sh_sh4_register_convert_to_raw (struct type *type, int regnum,
1560                                 const void *from, void *to)
1561 {
1562   if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
1563     {
1564       DOUBLEST val = extract_typed_floating (from, type);
1565       floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword,
1566                                  &val, to);
1567     }
1568   else
1569     error ("sh_register_convert_to_raw called with non DR register number");
1570 }
1571
1572 /* For vectors of 4 floating point registers. */
1573 static int
1574 fv_reg_base_num (int fv_regnum)
1575 {
1576   int fp_regnum;
1577
1578   fp_regnum = FP0_REGNUM + (fv_regnum - FV0_REGNUM) * 4;
1579   return fp_regnum;
1580 }
1581
1582 /* For double precision floating point registers, i.e 2 fp regs.*/
1583 static int
1584 dr_reg_base_num (int dr_regnum)
1585 {
1586   int fp_regnum;
1587
1588   fp_regnum = FP0_REGNUM + (dr_regnum - DR0_REGNUM) * 2;
1589   return fp_regnum;
1590 }
1591
1592 static void
1593 sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
1594                          int reg_nr, void *buffer)
1595 {
1596   int base_regnum, portion;
1597   char temp_buffer[MAX_REGISTER_SIZE];
1598
1599   if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
1600     {
1601       base_regnum = dr_reg_base_num (reg_nr);
1602
1603       /* Build the value in the provided buffer. */
1604       /* Read the real regs for which this one is an alias.  */
1605       for (portion = 0; portion < 2; portion++)
1606         regcache_raw_read (regcache, base_regnum + portion,
1607                            (temp_buffer
1608                             + register_size (gdbarch,
1609                                              base_regnum) * portion));
1610       /* We must pay attention to the endiannes. */
1611       sh_sh4_register_convert_to_virtual (reg_nr,
1612                                           gdbarch_register_type (gdbarch,
1613                                                                  reg_nr),
1614                                           temp_buffer, buffer);
1615     }
1616   else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
1617     {
1618       base_regnum = fv_reg_base_num (reg_nr);
1619
1620       /* Read the real regs for which this one is an alias.  */
1621       for (portion = 0; portion < 4; portion++)
1622         regcache_raw_read (regcache, base_regnum + portion,
1623                            ((char *) buffer
1624                             + register_size (gdbarch,
1625                                              base_regnum) * portion));
1626     }
1627 }
1628
1629 static void
1630 sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
1631                           int reg_nr, const void *buffer)
1632 {
1633   int base_regnum, portion;
1634   char temp_buffer[MAX_REGISTER_SIZE];
1635
1636   if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
1637     {
1638       base_regnum = dr_reg_base_num (reg_nr);
1639
1640       /* We must pay attention to the endiannes. */
1641       sh_sh4_register_convert_to_raw (gdbarch_register_type (gdbarch, reg_nr),
1642                                       reg_nr, buffer, temp_buffer);
1643
1644       /* Write the real regs for which this one is an alias.  */
1645       for (portion = 0; portion < 2; portion++)
1646         regcache_raw_write (regcache, base_regnum + portion,
1647                             (temp_buffer
1648                              + register_size (gdbarch,
1649                                               base_regnum) * portion));
1650     }
1651   else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
1652     {
1653       base_regnum = fv_reg_base_num (reg_nr);
1654
1655       /* Write the real regs for which this one is an alias.  */
1656       for (portion = 0; portion < 4; portion++)
1657         regcache_raw_write (regcache, base_regnum + portion,
1658                             ((char *) buffer
1659                              + register_size (gdbarch,
1660                                               base_regnum) * portion));
1661     }
1662 }
1663
1664 /* Floating point vector of 4 float registers. */
1665 static void
1666 do_fv_register_info (struct gdbarch *gdbarch, struct ui_file *file,
1667                      int fv_regnum)
1668 {
1669   int first_fp_reg_num = fv_reg_base_num (fv_regnum);
1670   fprintf_filtered (file, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
1671                     fv_regnum - FV0_REGNUM,
1672                     (int) read_register (first_fp_reg_num),
1673                     (int) read_register (first_fp_reg_num + 1),
1674                     (int) read_register (first_fp_reg_num + 2),
1675                     (int) read_register (first_fp_reg_num + 3));
1676 }
1677
1678 /* Double precision registers. */
1679 static void
1680 do_dr_register_info (struct gdbarch *gdbarch, struct ui_file *file,
1681                      int dr_regnum)
1682 {
1683   int first_fp_reg_num = dr_reg_base_num (dr_regnum);
1684
1685   fprintf_filtered (file, "dr%d\t0x%08x%08x\n",
1686                     dr_regnum - DR0_REGNUM,
1687                     (int) read_register (first_fp_reg_num),
1688                     (int) read_register (first_fp_reg_num + 1));
1689 }
1690
1691 static void
1692 sh_print_pseudo_register (struct gdbarch *gdbarch, struct ui_file *file,
1693                           int regnum)
1694 {
1695   if (regnum < NUM_REGS || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
1696     internal_error (__FILE__, __LINE__,
1697                     "Invalid pseudo register number %d\n", regnum);
1698   else if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
1699     do_dr_register_info (gdbarch, file, regnum);
1700   else if (regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM)
1701     do_fv_register_info (gdbarch, file, regnum);
1702 }
1703
1704 static void
1705 sh_do_fp_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
1706 {                               /* do values for FP (float) regs */
1707   char *raw_buffer;
1708   double flt;                   /* double extracted from raw hex data */
1709   int inv;
1710   int j;
1711
1712   /* Allocate space for the float. */
1713   raw_buffer = (char *) alloca (register_size (gdbarch, FP0_REGNUM));
1714
1715   /* Get the data in raw format.  */
1716   if (!frame_register_read (get_selected_frame (), regnum, raw_buffer))
1717     error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
1718
1719   /* Get the register as a number */
1720   flt = unpack_double (builtin_type_float, raw_buffer, &inv);
1721
1722   /* Print the name and some spaces. */
1723   fputs_filtered (REGISTER_NAME (regnum), file);
1724   print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
1725
1726   /* Print the value. */
1727   if (inv)
1728     fprintf_filtered (file, "<invalid float>");
1729   else
1730     fprintf_filtered (file, "%-10.9g", flt);
1731
1732   /* Print the fp register as hex. */
1733   fprintf_filtered (file, "\t(raw 0x");
1734   for (j = 0; j < register_size (gdbarch, regnum); j++)
1735     {
1736       int idx = (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
1737                  ? j
1738                  : register_size (gdbarch, regnum) - 1 - j);
1739       fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[idx]);
1740     }
1741   fprintf_filtered (file, ")");
1742   fprintf_filtered (file, "\n");
1743 }
1744
1745 static void
1746 sh_do_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
1747 {
1748   char raw_buffer[MAX_REGISTER_SIZE];
1749
1750   fputs_filtered (REGISTER_NAME (regnum), file);
1751   print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
1752
1753   /* Get the data in raw format.  */
1754   if (!frame_register_read (get_selected_frame (), regnum, raw_buffer))
1755     fprintf_filtered (file, "*value not available*\n");
1756
1757   val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
1758              file, 'x', 1, 0, Val_pretty_default);
1759   fprintf_filtered (file, "\t");
1760   val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
1761              file, 0, 1, 0, Val_pretty_default);
1762   fprintf_filtered (file, "\n");
1763 }
1764
1765 static void
1766 sh_print_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
1767 {
1768   if (regnum < 0 || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
1769     internal_error (__FILE__, __LINE__,
1770                     "Invalid register number %d\n", regnum);
1771
1772   else if (regnum >= 0 && regnum < NUM_REGS)
1773     {
1774       if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) ==
1775           TYPE_CODE_FLT)
1776         sh_do_fp_register (gdbarch, file, regnum);      /* FP regs */
1777       else
1778         sh_do_register (gdbarch, file, regnum); /* All other regs */
1779     }
1780
1781   else if (regnum < NUM_REGS + NUM_PSEUDO_REGS)
1782     {
1783       sh_print_pseudo_register (gdbarch, file, regnum);
1784     }
1785 }
1786
1787 static void
1788 sh_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
1789                          struct frame_info *frame, int regnum, int fpregs)
1790 {
1791   if (regnum != -1)             /* do one specified register */
1792     {
1793       if (*(REGISTER_NAME (regnum)) == '\0')
1794         error ("Not a valid register for the current processor type");
1795
1796       sh_print_register (gdbarch, file, regnum);
1797     }
1798   else
1799     /* do all (or most) registers */
1800     {
1801       regnum = 0;
1802       while (regnum < NUM_REGS)
1803         {
1804           /* If the register name is empty, it is undefined for this
1805              processor, so don't display anything.  */
1806           if (REGISTER_NAME (regnum) == NULL
1807               || *(REGISTER_NAME (regnum)) == '\0')
1808             {
1809               regnum++;
1810               continue;
1811             }
1812
1813           if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) ==
1814               TYPE_CODE_FLT)
1815             {
1816               if (fpregs)
1817                 {
1818                   /* true for "INFO ALL-REGISTERS" command */
1819                   sh_do_fp_register (gdbarch, file, regnum);    /* FP regs */
1820                   regnum++;
1821                 }
1822               else
1823                 regnum += (FP_LAST_REGNUM - FP0_REGNUM);        /* skip FP regs */
1824             }
1825           else
1826             {
1827               sh_do_register (gdbarch, file, regnum);   /* All other regs */
1828               regnum++;
1829             }
1830         }
1831
1832       if (fpregs)
1833         while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
1834           {
1835             sh_print_pseudo_register (gdbarch, file, regnum);
1836             regnum++;
1837           }
1838     }
1839 }
1840
1841 #ifdef SVR4_SHARED_LIBS
1842
1843 /* Fetch (and possibly build) an appropriate link_map_offsets structure
1844    for native i386 linux targets using the struct offsets defined in
1845    link.h (but without actual reference to that file).
1846
1847    This makes it possible to access i386-linux shared libraries from
1848    a gdb that was not built on an i386-linux host (for cross debugging).
1849    */
1850
1851 struct link_map_offsets *
1852 sh_linux_svr4_fetch_link_map_offsets (void)
1853 {
1854   static struct link_map_offsets lmo;
1855   static struct link_map_offsets *lmp = 0;
1856
1857   if (lmp == 0)
1858     {
1859       lmp = &lmo;
1860
1861       lmo.r_debug_size = 8;     /* 20 not actual size but all we need */
1862
1863       lmo.r_map_offset = 4;
1864       lmo.r_map_size = 4;
1865
1866       lmo.link_map_size = 20;   /* 552 not actual size but all we need */
1867
1868       lmo.l_addr_offset = 0;
1869       lmo.l_addr_size = 4;
1870
1871       lmo.l_name_offset = 4;
1872       lmo.l_name_size = 4;
1873
1874       lmo.l_next_offset = 12;
1875       lmo.l_next_size = 4;
1876
1877       lmo.l_prev_offset = 16;
1878       lmo.l_prev_size = 4;
1879     }
1880
1881   return lmp;
1882 }
1883 #endif /* SVR4_SHARED_LIBS */
1884
1885 static int
1886 sh_dsp_register_sim_regno (int nr)
1887 {
1888   if (legacy_register_sim_regno (nr) < 0)
1889     return legacy_register_sim_regno (nr);
1890   if (nr >= DSR_REGNUM && nr <= Y1_REGNUM)
1891     return nr - DSR_REGNUM + SIM_SH_DSR_REGNUM;
1892   if (nr == MOD_REGNUM)
1893     return SIM_SH_MOD_REGNUM;
1894   if (nr == RS_REGNUM)
1895     return SIM_SH_RS_REGNUM;
1896   if (nr == RE_REGNUM)
1897     return SIM_SH_RE_REGNUM;
1898   if (nr >= R0_BANK_REGNUM && nr <= R7_BANK_REGNUM)
1899     return nr - R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM;
1900   return nr;
1901 }
1902
1903 static struct sh_frame_cache *
1904 sh_alloc_frame_cache (void)
1905 {
1906   struct sh_frame_cache *cache;
1907   int i;
1908
1909   cache = FRAME_OBSTACK_ZALLOC (struct sh_frame_cache);
1910
1911   /* Base address.  */
1912   cache->base = 0;
1913   cache->saved_sp = 0;
1914   cache->sp_offset = 0;
1915   cache->pc = 0;
1916
1917   /* Frameless until proven otherwise.  */
1918   cache->uses_fp = 0;
1919
1920   /* Saved registers.  We initialize these to -1 since zero is a valid
1921      offset (that's where fp is supposed to be stored).  */
1922   for (i = 0; i < SH_NUM_REGS; i++)
1923     {
1924       cache->saved_regs[i] = -1;
1925     }
1926
1927   return cache;
1928 }
1929
1930 static struct sh_frame_cache *
1931 sh_frame_cache (struct frame_info *next_frame, void **this_cache)
1932 {
1933   struct sh_frame_cache *cache;
1934   CORE_ADDR current_pc;
1935   int i;
1936
1937   if (*this_cache)
1938     return *this_cache;
1939
1940   cache = sh_alloc_frame_cache ();
1941   *this_cache = cache;
1942
1943   /* In principle, for normal frames, fp holds the frame pointer,
1944      which holds the base address for the current stack frame.
1945      However, for functions that don't need it, the frame pointer is
1946      optional.  For these "frameless" functions the frame pointer is
1947      actually the frame pointer of the calling frame. */
1948   cache->base = frame_unwind_register_unsigned (next_frame, FP_REGNUM);
1949   if (cache->base == 0)
1950     return cache;
1951
1952   cache->pc = frame_func_unwind (next_frame);
1953   current_pc = frame_pc_unwind (next_frame);
1954   if (cache->pc != 0)
1955     sh_analyze_prologue (cache->pc, current_pc, cache);
1956
1957   if (!cache->uses_fp)
1958     {
1959       /* We didn't find a valid frame, which means that CACHE->base
1960          currently holds the frame pointer for our calling frame.  If
1961          we're at the start of a function, or somewhere half-way its
1962          prologue, the function's frame probably hasn't been fully
1963          setup yet.  Try to reconstruct the base address for the stack
1964          frame by looking at the stack pointer.  For truly "frameless"
1965          functions this might work too.  */
1966       cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
1967     }
1968
1969   /* Now that we have the base address for the stack frame we can
1970      calculate the value of sp in the calling frame.  */
1971   cache->saved_sp = cache->base + cache->sp_offset;
1972
1973   /* Adjust all the saved registers such that they contain addresses
1974      instead of offsets.  */
1975   for (i = 0; i < SH_NUM_REGS; i++)
1976     if (cache->saved_regs[i] != -1)
1977       cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i] - 4;
1978
1979   return cache;
1980 }
1981
1982 static void
1983 sh_frame_prev_register (struct frame_info *next_frame, void **this_cache,
1984                         int regnum, int *optimizedp,
1985                         enum lval_type *lvalp, CORE_ADDR *addrp,
1986                         int *realnump, void *valuep)
1987 {
1988   struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
1989
1990   gdb_assert (regnum >= 0);
1991
1992   if (regnum == SP_REGNUM && cache->saved_sp)
1993     {
1994       *optimizedp = 0;
1995       *lvalp = not_lval;
1996       *addrp = 0;
1997       *realnump = -1;
1998       if (valuep)
1999         {
2000           /* Store the value.  */
2001           store_unsigned_integer (valuep, 4, cache->saved_sp);
2002         }
2003       return;
2004     }
2005
2006   /* The PC of the previous frame is stored in the PR register of
2007      the current frame.  Frob regnum so that we pull the value from
2008      the correct place.  */
2009   if (regnum == PC_REGNUM)
2010     regnum = PR_REGNUM;
2011
2012   if (regnum < SH_NUM_REGS && cache->saved_regs[regnum] != -1)
2013     {
2014       *optimizedp = 0;
2015       *lvalp = lval_memory;
2016       *addrp = cache->saved_regs[regnum];
2017       *realnump = -1;
2018       if (valuep)
2019         {
2020           /* Read the value in from memory.  */
2021           read_memory (*addrp, valuep,
2022                        register_size (current_gdbarch, regnum));
2023         }
2024       return;
2025     }
2026
2027   frame_register_unwind (next_frame, regnum,
2028                          optimizedp, lvalp, addrp, realnump, valuep);
2029 }
2030
2031 static void
2032 sh_frame_this_id (struct frame_info *next_frame, void **this_cache,
2033                   struct frame_id *this_id)
2034 {
2035   struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
2036
2037   /* This marks the outermost frame.  */
2038   if (cache->base == 0)
2039     return;
2040
2041   *this_id = frame_id_build (cache->saved_sp, cache->pc);
2042 }
2043
2044 static const struct frame_unwind sh_frame_unwind = {
2045   NORMAL_FRAME,
2046   sh_frame_this_id,
2047   sh_frame_prev_register
2048 };
2049
2050 static const struct frame_unwind *
2051 sh_frame_sniffer (struct frame_info *next_frame)
2052 {
2053   return &sh_frame_unwind;
2054 }
2055
2056 static CORE_ADDR
2057 sh_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
2058 {
2059   return frame_unwind_register_unsigned (next_frame, SP_REGNUM);
2060 }
2061
2062 static CORE_ADDR
2063 sh_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2064 {
2065   return frame_unwind_register_unsigned (next_frame, PC_REGNUM);
2066 }
2067
2068 static struct frame_id
2069 sh_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
2070 {
2071   return frame_id_build (sh_unwind_sp (gdbarch, next_frame),
2072                          frame_pc_unwind (next_frame));
2073 }
2074
2075 static CORE_ADDR
2076 sh_frame_base_address (struct frame_info *next_frame, void **this_cache)
2077 {
2078   struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
2079
2080   return cache->base;
2081 }
2082
2083 static const struct frame_base sh_frame_base = {
2084   &sh_frame_unwind,
2085   sh_frame_base_address,
2086   sh_frame_base_address,
2087   sh_frame_base_address
2088 };
2089
2090 /* The epilogue is defined here as the area at the end of a function,
2091    either on the `ret' instruction itself or after an instruction which
2092    destroys the function's stack frame. */
2093 static int
2094 sh_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2095 {
2096   CORE_ADDR func_addr = 0, func_end = 0;
2097
2098   if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
2099     {
2100       ULONGEST inst;
2101       /* The sh epilogue is max. 14 bytes long.  Give another 14 bytes
2102          for a nop and some fixed data (e.g. big offsets) which are
2103          unfortunately also treated as part of the function (which
2104          means, they are below func_end. */
2105       CORE_ADDR addr = func_end - 28;
2106       if (addr < func_addr + 4)
2107         addr = func_addr + 4;
2108       if (pc < addr)
2109         return 0;
2110
2111       /* First search forward until hitting an rts. */
2112       while (addr < func_end
2113              && !IS_RTS (read_memory_unsigned_integer (addr, 2)))
2114         addr += 2;
2115       if (addr >= func_end)
2116         return 0;
2117
2118       /* At this point we should find a mov.l @r15+,r14 instruction,
2119          either before or after the rts.  If not, then the function has
2120          probably no "normal" epilogue and we bail out here. */
2121       inst = read_memory_unsigned_integer (addr - 2, 2);
2122       if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2)))
2123         addr -= 2;
2124       else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2)))
2125         return 0;
2126
2127       /* Step over possible lds.l @r15+,pr. */
2128       inst = read_memory_unsigned_integer (addr - 2, 2);
2129       if (IS_LDS (inst))
2130         {
2131           addr -= 2;
2132           inst = read_memory_unsigned_integer (addr - 2, 2);
2133         }
2134
2135       /* Step over possible mov r14,r15. */
2136       if (IS_MOV_FP_SP (inst))
2137         {
2138           addr -= 2;
2139           inst = read_memory_unsigned_integer (addr - 2, 2);
2140         }
2141
2142       /* Now check for FP adjustments, using add #imm,r14 or add rX, r14
2143          instructions. */
2144       while (addr > func_addr + 4
2145              && (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst)))
2146         {
2147           addr -= 2;
2148           inst = read_memory_unsigned_integer (addr - 2, 2);
2149         }
2150
2151       if (pc >= addr)
2152         return 1;
2153     }
2154   return 0;
2155 }
2156
2157 static gdbarch_init_ftype sh_gdbarch_init;
2158
2159 static struct gdbarch *
2160 sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2161 {
2162   struct gdbarch *gdbarch;
2163
2164   sh_show_regs = sh_generic_show_regs;
2165   switch (info.bfd_arch_info->mach)
2166     {
2167     case bfd_mach_sh2e:
2168       sh_show_regs = sh2e_show_regs;
2169       break;
2170     case bfd_mach_sh_dsp:
2171       sh_show_regs = sh_dsp_show_regs;
2172       break;
2173
2174     case bfd_mach_sh3:
2175       sh_show_regs = sh3_show_regs;
2176       break;
2177
2178     case bfd_mach_sh3e:
2179       sh_show_regs = sh3e_show_regs;
2180       break;
2181
2182     case bfd_mach_sh3_dsp:
2183     case bfd_mach_sh4al_dsp:
2184       sh_show_regs = sh3_dsp_show_regs;
2185       break;
2186
2187     case bfd_mach_sh4:
2188     case bfd_mach_sh4a:
2189       sh_show_regs = sh4_show_regs;
2190       break;
2191
2192     case bfd_mach_sh4_nofpu:
2193     case bfd_mach_sh4a_nofpu:
2194       sh_show_regs = sh4_nofpu_show_regs;
2195       break;
2196
2197     case bfd_mach_sh5:
2198       sh_show_regs = sh64_show_regs;
2199       /* SH5 is handled entirely in sh64-tdep.c */
2200       return sh64_gdbarch_init (info, arches);
2201     }
2202
2203   /* If there is already a candidate, use it.  */
2204   arches = gdbarch_list_lookup_by_info (arches, &info);
2205   if (arches != NULL)
2206     return arches->gdbarch;
2207
2208   /* None found, create a new architecture from the information
2209      provided. */
2210   gdbarch = gdbarch_alloc (&info, NULL);
2211
2212   set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2213   set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2214   set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2215   set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2216   set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2217   set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2218   set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2219   set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2220
2221   set_gdbarch_num_regs (gdbarch, SH_NUM_REGS);
2222   set_gdbarch_sp_regnum (gdbarch, 15);
2223   set_gdbarch_pc_regnum (gdbarch, 16);
2224   set_gdbarch_fp0_regnum (gdbarch, -1);
2225   set_gdbarch_num_pseudo_regs (gdbarch, 0);
2226
2227   set_gdbarch_register_type (gdbarch, sh_default_register_type);
2228
2229   set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info);
2230
2231   set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);
2232   set_gdbarch_use_struct_convention (gdbarch, sh_use_struct_convention);
2233
2234   set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh);
2235   set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
2236
2237   set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
2238
2239   set_gdbarch_store_return_value (gdbarch, sh_default_store_return_value);
2240   set_gdbarch_extract_return_value (gdbarch, sh_default_extract_return_value);
2241   set_gdbarch_deprecated_extract_struct_value_address (gdbarch, sh_extract_struct_value_address);
2242
2243   set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
2244   set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2245
2246   set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu);
2247
2248   set_gdbarch_frameless_function_invocation (gdbarch,
2249                                              frameless_look_for_prologue);
2250   set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2251
2252   set_gdbarch_frame_align (gdbarch, sh_frame_align);
2253   set_gdbarch_unwind_sp (gdbarch, sh_unwind_sp);
2254   set_gdbarch_unwind_pc (gdbarch, sh_unwind_pc);
2255   set_gdbarch_unwind_dummy_id (gdbarch, sh_unwind_dummy_id);
2256   frame_base_set_default (gdbarch, &sh_frame_base);
2257
2258   set_gdbarch_in_function_epilogue_p (gdbarch, sh_in_function_epilogue_p);
2259
2260   switch (info.bfd_arch_info->mach)
2261     {
2262     case bfd_mach_sh:
2263       set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2264       break;
2265
2266     case bfd_mach_sh2:
2267       set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2268       break;
2269
2270     case bfd_mach_sh2e:
2271       /* doubles on sh2e and sh3e are actually 4 byte. */
2272       set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2273
2274       set_gdbarch_register_name (gdbarch, sh_sh2e_register_name);
2275       set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2276       set_gdbarch_fp0_regnum (gdbarch, 25);
2277       set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
2278       set_gdbarch_extract_return_value (gdbarch,
2279                                         sh3e_sh4_extract_return_value);
2280       set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2281       break;
2282
2283     case bfd_mach_sh_dsp:
2284       set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name);
2285       set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2286       break;
2287
2288     case bfd_mach_sh3:
2289       set_gdbarch_register_name (gdbarch, sh_sh3_register_name);
2290       break;
2291
2292     case bfd_mach_sh3e:
2293       /* doubles on sh2e and sh3e are actually 4 byte. */
2294       set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2295
2296       set_gdbarch_register_name (gdbarch, sh_sh3e_register_name);
2297       set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2298       set_gdbarch_fp0_regnum (gdbarch, 25);
2299       set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
2300       set_gdbarch_extract_return_value (gdbarch,
2301                                         sh3e_sh4_extract_return_value);
2302       set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2303       break;
2304
2305     case bfd_mach_sh3_dsp:
2306       set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name);
2307       set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2308       break;
2309
2310     case bfd_mach_sh4:
2311     case bfd_mach_sh4a:
2312       set_gdbarch_register_name (gdbarch, sh_sh4_register_name);
2313       set_gdbarch_register_type (gdbarch, sh_sh4_register_type);
2314       set_gdbarch_fp0_regnum (gdbarch, 25);
2315       set_gdbarch_num_pseudo_regs (gdbarch, 12);
2316       set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2317       set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
2318       set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
2319       set_gdbarch_extract_return_value (gdbarch,
2320                                         sh3e_sh4_extract_return_value);
2321       set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2322       break;
2323
2324     case bfd_mach_sh4_nofpu:
2325     case bfd_mach_sh4a_nofpu:
2326       set_gdbarch_register_name (gdbarch, sh_sh4_nofpu_register_name);
2327       break;
2328
2329     case bfd_mach_sh4al_dsp:
2330       set_gdbarch_register_name (gdbarch, sh_sh4al_dsp_register_name);
2331       set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2332       break;
2333
2334     default:
2335       set_gdbarch_register_name (gdbarch, sh_generic_register_name);
2336       break;
2337     }
2338
2339   /* Hook in ABI-specific overrides, if they have been registered.  */
2340   gdbarch_init_osabi (info, gdbarch);
2341
2342   frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer);
2343   frame_unwind_append_sniffer (gdbarch, sh_frame_sniffer);
2344
2345   return gdbarch;
2346 }
2347
2348 extern initialize_file_ftype _initialize_sh_tdep;       /* -Wmissing-prototypes */
2349
2350 void
2351 _initialize_sh_tdep (void)
2352 {
2353   struct cmd_list_element *c;
2354
2355   gdbarch_register (bfd_arch_sh, sh_gdbarch_init, NULL);
2356
2357   add_com ("regs", class_vars, sh_show_regs_command, "Print all registers");
2358 }