1 /* Target-dependent code for Renesas Super-H, for GDB.
3 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
4 2003, 2004, 2005, 2007, 2008 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 Contributed by Steve Chamberlain
28 #include "frame-base.h"
29 #include "frame-unwind.h"
30 #include "dwarf2-frame.h"
38 #include "gdb_string.h"
39 #include "gdb_assert.h"
40 #include "arch-utils.h"
41 #include "floatformat.h"
45 #include "reggroups.h"
50 #include "solib-svr4.h"
54 #include "elf/dwarf2.h"
55 /* registers numbers shared with the simulator */
56 #include "gdb/sim-sh.h"
58 /* List of "set sh ..." and "show sh ..." commands. */
59 static struct cmd_list_element
*setshcmdlist
= NULL
;
60 static struct cmd_list_element
*showshcmdlist
= NULL
;
62 static const char sh_cc_gcc
[] = "gcc";
63 static const char sh_cc_renesas
[] = "renesas";
64 static const char *sh_cc_enum
[] = {
70 static const char *sh_active_calling_convention
= sh_cc_gcc
;
72 static void (*sh_show_regs
) (struct frame_info
*);
74 #define SH_NUM_REGS 67
83 /* Flag showing that a frame has been created in the prologue code. */
86 /* Saved registers. */
87 CORE_ADDR saved_regs
[SH_NUM_REGS
];
92 sh_is_renesas_calling_convention (struct type
*func_type
)
95 && TYPE_CALLING_CONVENTION (func_type
) == DW_CC_GNU_renesas_sh
)
96 || sh_active_calling_convention
== sh_cc_renesas
);
100 sh_sh_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
102 static char *register_names
[] = {
103 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
104 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
105 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
107 "", "", "", "", "", "", "", "",
108 "", "", "", "", "", "", "", "",
110 "", "", "", "", "", "", "", "",
111 "", "", "", "", "", "", "", "",
112 "", "", "", "", "", "", "", "",
116 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
118 return register_names
[reg_nr
];
122 sh_sh3_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
124 static char *register_names
[] = {
125 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
126 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
127 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
129 "", "", "", "", "", "", "", "",
130 "", "", "", "", "", "", "", "",
132 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
133 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
134 "", "", "", "", "", "", "", "",
138 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
140 return register_names
[reg_nr
];
144 sh_sh3e_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
146 static char *register_names
[] = {
147 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
148 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
149 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
151 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
152 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
154 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
155 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
156 "", "", "", "", "", "", "", "",
160 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
162 return register_names
[reg_nr
];
166 sh_sh2e_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
168 static char *register_names
[] = {
169 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
170 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
171 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
173 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
174 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
176 "", "", "", "", "", "", "", "",
177 "", "", "", "", "", "", "", "",
178 "", "", "", "", "", "", "", "",
182 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
184 return register_names
[reg_nr
];
188 sh_sh2a_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
190 static char *register_names
[] = {
191 /* general registers 0-15 */
192 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
193 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
195 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
198 /* floating point registers 25 - 40 */
199 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
200 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
203 /* 43 - 62. Banked registers. The bank number used is determined by
204 the bank register (63). */
205 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
206 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
207 "machb", "ivnb", "prb", "gbrb", "maclb",
208 /* 63: register bank number, not a real register but used to
209 communicate the register bank currently get/set. This register
210 is hidden to the user, who manipulates it using the pseudo
211 register called "bank" (67). See below. */
214 "ibcr", "ibnr", "tbr",
215 /* 67: register bank number, the user visible pseudo register. */
217 /* double precision (pseudo) 68 - 75 */
218 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
222 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
224 return register_names
[reg_nr
];
228 sh_sh2a_nofpu_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
230 static char *register_names
[] = {
231 /* general registers 0-15 */
232 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
233 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
235 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
238 /* floating point registers 25 - 40 */
239 "", "", "", "", "", "", "", "",
240 "", "", "", "", "", "", "", "",
243 /* 43 - 62. Banked registers. The bank number used is determined by
244 the bank register (63). */
245 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
246 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
247 "machb", "ivnb", "prb", "gbrb", "maclb",
248 /* 63: register bank number, not a real register but used to
249 communicate the register bank currently get/set. This register
250 is hidden to the user, who manipulates it using the pseudo
251 register called "bank" (67). See below. */
254 "ibcr", "ibnr", "tbr",
255 /* 67: register bank number, the user visible pseudo register. */
257 /* double precision (pseudo) 68 - 75 */
258 "", "", "", "", "", "", "", "",
262 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
264 return register_names
[reg_nr
];
268 sh_sh_dsp_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
270 static char *register_names
[] = {
271 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
272 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
273 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
275 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
276 "y0", "y1", "", "", "", "", "", "mod",
278 "rs", "re", "", "", "", "", "", "",
279 "", "", "", "", "", "", "", "",
280 "", "", "", "", "", "", "", "",
284 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
286 return register_names
[reg_nr
];
290 sh_sh3_dsp_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
292 static char *register_names
[] = {
293 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
294 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
295 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
297 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
298 "y0", "y1", "", "", "", "", "", "mod",
300 "rs", "re", "", "", "", "", "", "",
301 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
302 "", "", "", "", "", "", "", "",
303 "", "", "", "", "", "", "", "",
307 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
309 return register_names
[reg_nr
];
313 sh_sh4_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
315 static char *register_names
[] = {
316 /* general registers 0-15 */
317 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
318 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
320 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
323 /* floating point registers 25 - 40 */
324 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
325 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
329 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
331 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
332 "", "", "", "", "", "", "", "",
333 /* pseudo bank register. */
335 /* double precision (pseudo) 59 - 66 */
336 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
337 /* vectors (pseudo) 67 - 70 */
338 "fv0", "fv4", "fv8", "fv12",
339 /* FIXME: missing XF 71 - 86 */
340 /* FIXME: missing XD 87 - 94 */
344 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
346 return register_names
[reg_nr
];
350 sh_sh4_nofpu_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
352 static char *register_names
[] = {
353 /* general registers 0-15 */
354 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
355 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
357 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
360 /* floating point registers 25 - 40 -- not for nofpu target */
361 "", "", "", "", "", "", "", "",
362 "", "", "", "", "", "", "", "",
366 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
368 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
369 "", "", "", "", "", "", "", "",
370 /* pseudo bank register. */
372 /* double precision (pseudo) 59 - 66 -- not for nofpu target */
373 "", "", "", "", "", "", "", "",
374 /* vectors (pseudo) 67 - 70 -- not for nofpu target */
379 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
381 return register_names
[reg_nr
];
385 sh_sh4al_dsp_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
387 static char *register_names
[] = {
388 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
389 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
390 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
392 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
393 "y0", "y1", "", "", "", "", "", "mod",
395 "rs", "re", "", "", "", "", "", "",
396 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
397 "", "", "", "", "", "", "", "",
398 "", "", "", "", "", "", "", "",
402 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
404 return register_names
[reg_nr
];
407 static const unsigned char *
408 sh_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
, int *lenptr
)
410 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
411 static unsigned char breakpoint
[] = { 0xc3, 0xc3 };
413 /* For remote stub targets, trapa #20 is used. */
414 if (strcmp (target_shortname
, "remote") == 0)
416 static unsigned char big_remote_breakpoint
[] = { 0xc3, 0x20 };
417 static unsigned char little_remote_breakpoint
[] = { 0x20, 0xc3 };
419 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
421 *lenptr
= sizeof (big_remote_breakpoint
);
422 return big_remote_breakpoint
;
426 *lenptr
= sizeof (little_remote_breakpoint
);
427 return little_remote_breakpoint
;
431 *lenptr
= sizeof (breakpoint
);
435 /* Prologue looks like
439 sub <room_for_loca_vars>,r15
442 Actually it can be more complicated than this but that's it, basically.
445 #define GET_SOURCE_REG(x) (((x) >> 4) & 0xf)
446 #define GET_TARGET_REG(x) (((x) >> 8) & 0xf)
448 /* JSR @Rm 0100mmmm00001011 */
449 #define IS_JSR(x) (((x) & 0xf0ff) == 0x400b)
451 /* STS.L PR,@-r15 0100111100100010
452 r15-4-->r15, PR-->(r15) */
453 #define IS_STS(x) ((x) == 0x4f22)
455 /* STS.L MACL,@-r15 0100111100010010
456 r15-4-->r15, MACL-->(r15) */
457 #define IS_MACL_STS(x) ((x) == 0x4f12)
459 /* MOV.L Rm,@-r15 00101111mmmm0110
460 r15-4-->r15, Rm-->(R15) */
461 #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
463 /* MOV r15,r14 0110111011110011
465 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
467 /* ADD #imm,r15 01111111iiiiiiii
469 #define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00)
471 #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
472 #define IS_SHLL_R3(x) ((x) == 0x4300)
474 /* ADD r3,r15 0011111100111100
476 #define IS_ADD_R3SP(x) ((x) == 0x3f3c)
478 /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
479 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
480 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
481 /* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to
482 make this entirely clear. */
483 /* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */
484 #define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b)
486 /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */
487 #define IS_MOV_ARG_TO_REG(x) \
488 (((x) & 0xf00f) == 0x6003 && \
489 ((x) & 0x00f0) >= 0x0040 && \
490 ((x) & 0x00f0) <= 0x0070)
491 /* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */
492 #define IS_MOV_ARG_TO_IND_R14(x) \
493 (((x) & 0xff0f) == 0x2e02 && \
494 ((x) & 0x00f0) >= 0x0040 && \
495 ((x) & 0x00f0) <= 0x0070)
496 /* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */
497 #define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \
498 (((x) & 0xff00) == 0x1e00 && \
499 ((x) & 0x00f0) >= 0x0040 && \
500 ((x) & 0x00f0) <= 0x0070)
502 /* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */
503 #define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000)
504 /* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */
505 #define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000)
506 /* MOVI20 #imm20,Rn 0000nnnniiii0000 */
507 #define IS_MOVI20(x) (((x) & 0xf00f) == 0x0000)
508 /* SUB Rn,R15 00111111nnnn1000 */
509 #define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08)
511 #define FPSCR_SZ (1 << 20)
513 /* The following instructions are used for epilogue testing. */
514 #define IS_RESTORE_FP(x) ((x) == 0x6ef6)
515 #define IS_RTS(x) ((x) == 0x000b)
516 #define IS_LDS(x) ((x) == 0x4f26)
517 #define IS_MACL_LDS(x) ((x) == 0x4f16)
518 #define IS_MOV_FP_SP(x) ((x) == 0x6fe3)
519 #define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c)
520 #define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00)
522 /* Disassemble an instruction. */
524 gdb_print_insn_sh (bfd_vma memaddr
, disassemble_info
* info
)
526 info
->endian
= gdbarch_byte_order (current_gdbarch
);
527 return print_insn_sh (memaddr
, info
);
531 sh_analyze_prologue (CORE_ADDR pc
, CORE_ADDR current_pc
,
532 struct sh_frame_cache
*cache
, ULONGEST fpscr
)
539 int reg
, sav_reg
= -1;
541 if (pc
>= current_pc
)
545 for (opc
= pc
+ (2 * 28); pc
< opc
; pc
+= 2)
547 inst
= read_memory_unsigned_integer (pc
, 2);
548 /* See where the registers will be saved to */
551 cache
->saved_regs
[GET_SOURCE_REG (inst
)] = cache
->sp_offset
;
552 cache
->sp_offset
+= 4;
554 else if (IS_STS (inst
))
556 cache
->saved_regs
[PR_REGNUM
] = cache
->sp_offset
;
557 cache
->sp_offset
+= 4;
559 else if (IS_MACL_STS (inst
))
561 cache
->saved_regs
[MACL_REGNUM
] = cache
->sp_offset
;
562 cache
->sp_offset
+= 4;
564 else if (IS_MOV_R3 (inst
))
566 r3_val
= ((inst
& 0xff) ^ 0x80) - 0x80;
568 else if (IS_SHLL_R3 (inst
))
572 else if (IS_ADD_R3SP (inst
))
574 cache
->sp_offset
+= -r3_val
;
576 else if (IS_ADD_IMM_SP (inst
))
578 offset
= ((inst
& 0xff) ^ 0x80) - 0x80;
579 cache
->sp_offset
-= offset
;
581 else if (IS_MOVW_PCREL_TO_REG (inst
))
585 reg
= GET_TARGET_REG (inst
);
589 offset
= (inst
& 0xff) << 1;
591 read_memory_integer ((pc
+ 4) + offset
, 2);
595 else if (IS_MOVL_PCREL_TO_REG (inst
))
599 reg
= GET_TARGET_REG (inst
);
603 offset
= (inst
& 0xff) << 2;
605 read_memory_integer (((pc
& 0xfffffffc) + 4) + offset
, 4);
609 else if (IS_MOVI20 (inst
))
613 reg
= GET_TARGET_REG (inst
);
617 sav_offset
= GET_SOURCE_REG (inst
) << 16;
618 /* MOVI20 is a 32 bit instruction! */
620 sav_offset
|= read_memory_unsigned_integer (pc
, 2);
621 /* Now sav_offset contains an unsigned 20 bit value.
622 It must still get sign extended. */
623 if (sav_offset
& 0x00080000)
624 sav_offset
|= 0xfff00000;
628 else if (IS_SUB_REG_FROM_SP (inst
))
630 reg
= GET_SOURCE_REG (inst
);
631 if (sav_reg
> 0 && reg
== sav_reg
)
635 cache
->sp_offset
+= sav_offset
;
637 else if (IS_FPUSH (inst
))
639 if (fpscr
& FPSCR_SZ
)
641 cache
->sp_offset
+= 8;
645 cache
->sp_offset
+= 4;
648 else if (IS_MOV_SP_FP (inst
))
651 /* At this point, only allow argument register moves to other
652 registers or argument register moves to @(X,fp) which are
653 moving the register arguments onto the stack area allocated
654 by a former add somenumber to SP call. Don't allow moving
655 to an fp indirect address above fp + cache->sp_offset. */
657 for (opc
= pc
+ 12; pc
< opc
; pc
+= 2)
659 inst
= read_memory_integer (pc
, 2);
660 if (IS_MOV_ARG_TO_IND_R14 (inst
))
662 reg
= GET_SOURCE_REG (inst
);
663 if (cache
->sp_offset
> 0)
664 cache
->saved_regs
[reg
] = cache
->sp_offset
;
666 else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst
))
668 reg
= GET_SOURCE_REG (inst
);
669 offset
= (inst
& 0xf) * 4;
670 if (cache
->sp_offset
> offset
)
671 cache
->saved_regs
[reg
] = cache
->sp_offset
- offset
;
673 else if (IS_MOV_ARG_TO_REG (inst
))
680 else if (IS_JSR (inst
))
682 /* We have found a jsr that has been scheduled into the prologue.
683 If we continue the scan and return a pc someplace after this,
684 then setting a breakpoint on this function will cause it to
685 appear to be called after the function it is calling via the
686 jsr, which will be very confusing. Most likely the next
687 instruction is going to be IS_MOV_SP_FP in the delay slot. If
688 so, note that before returning the current pc. */
689 inst
= read_memory_integer (pc
+ 2, 2);
690 if (IS_MOV_SP_FP (inst
))
694 #if 0 /* This used to just stop when it found an instruction that
695 was not considered part of the prologue. Now, we just
696 keep going looking for likely instructions. */
705 /* Skip any prologue before the guts of a function */
707 /* Skip the prologue using the debug information. If this fails we'll
708 fall back on the 'guess' method below. */
710 after_prologue (CORE_ADDR pc
)
712 struct symtab_and_line sal
;
713 CORE_ADDR func_addr
, func_end
;
715 /* If we can not find the symbol in the partial symbol table, then
716 there is no hope we can determine the function's start address
718 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
721 /* Get the line associated with FUNC_ADDR. */
722 sal
= find_pc_line (func_addr
, 0);
724 /* There are only two cases to consider. First, the end of the source line
725 is within the function bounds. In that case we return the end of the
726 source line. Second is the end of the source line extends beyond the
727 bounds of the current function. We need to use the slow code to
728 examine instructions in that case. */
729 if (sal
.end
< func_end
)
736 sh_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
739 struct sh_frame_cache cache
;
741 /* See if we can determine the end of the prologue via the symbol table.
742 If so, then return either PC, or the PC after the prologue, whichever
744 pc
= after_prologue (start_pc
);
746 /* If after_prologue returned a useful address, then use it. Else
747 fall back on the instruction skipping code. */
749 return max (pc
, start_pc
);
751 cache
.sp_offset
= -4;
752 pc
= sh_analyze_prologue (start_pc
, (CORE_ADDR
) -1, &cache
, 0);
761 Aggregate types not bigger than 8 bytes that have the same size and
762 alignment as one of the integer scalar types are returned in the
763 same registers as the integer type they match.
765 For example, a 2-byte aligned structure with size 2 bytes has the
766 same size and alignment as a short int, and will be returned in R0.
767 A 4-byte aligned structure with size 8 bytes has the same size and
768 alignment as a long long int, and will be returned in R0 and R1.
770 When an aggregate type is returned in R0 and R1, R0 contains the
771 first four bytes of the aggregate, and R1 contains the
772 remainder. If the size of the aggregate type is not a multiple of 4
773 bytes, the aggregate is tail-padded up to a multiple of 4
774 bytes. The value of the padding is undefined. For little-endian
775 targets the padding will appear at the most significant end of the
776 last element, for big-endian targets the padding appears at the
777 least significant end of the last element.
779 All other aggregate types are returned by address. The caller
780 function passes the address of an area large enough to hold the
781 aggregate value in R2. The called function stores the result in
784 To reiterate, structs smaller than 8 bytes could also be returned
785 in memory, if they don't pass the "same size and alignment as an
790 struct s { char c[3]; } wibble;
791 struct s foo(void) { return wibble; }
793 the return value from foo() will be in memory, not
794 in R0, because there is no 3-byte integer type.
798 struct s { char c[2]; } wibble;
799 struct s foo(void) { return wibble; }
801 because a struct containing two chars has alignment 1, that matches
802 type char, but size 2, that matches type short. There's no integer
803 type that has alignment 1 and size 2, so the struct is returned in
809 sh_use_struct_convention (int renesas_abi
, struct type
*type
)
811 int len
= TYPE_LENGTH (type
);
812 int nelem
= TYPE_NFIELDS (type
);
814 /* The Renesas ABI returns aggregate types always on stack. */
815 if (renesas_abi
&& (TYPE_CODE (type
) == TYPE_CODE_STRUCT
816 || TYPE_CODE (type
) == TYPE_CODE_UNION
))
819 /* Non-power of 2 length types and types bigger than 8 bytes (which don't
820 fit in two registers anyway) use struct convention. */
821 if (len
!= 1 && len
!= 2 && len
!= 4 && len
!= 8)
824 /* Scalar types and aggregate types with exactly one field are aligned
825 by definition. They are returned in registers. */
829 /* If the first field in the aggregate has the same length as the entire
830 aggregate type, the type is returned in registers. */
831 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, 0)) == len
)
834 /* If the size of the aggregate is 8 bytes and the first field is
835 of size 4 bytes its alignment is equal to long long's alignment,
836 so it's returned in registers. */
837 if (len
== 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type
, 0)) == 4)
840 /* Otherwise use struct convention. */
845 sh_use_struct_convention_nofpu (int renesas_abi
, struct type
*type
)
847 /* The Renesas ABI returns long longs/doubles etc. always on stack. */
848 if (renesas_abi
&& TYPE_NFIELDS (type
) == 0 && TYPE_LENGTH (type
) >= 8)
850 return sh_use_struct_convention (renesas_abi
, type
);
854 sh_frame_align (struct gdbarch
*ignore
, CORE_ADDR sp
)
859 /* Function: push_dummy_call (formerly push_arguments)
860 Setup the function arguments for calling a function in the inferior.
862 On the Renesas SH architecture, there are four registers (R4 to R7)
863 which are dedicated for passing function arguments. Up to the first
864 four arguments (depending on size) may go into these registers.
865 The rest go on the stack.
867 MVS: Except on SH variants that have floating point registers.
868 In that case, float and double arguments are passed in the same
869 manner, but using FP registers instead of GP registers.
871 Arguments that are smaller than 4 bytes will still take up a whole
872 register or a whole 32-bit word on the stack, and will be
873 right-justified in the register or the stack word. This includes
874 chars, shorts, and small aggregate types.
876 Arguments that are larger than 4 bytes may be split between two or
877 more registers. If there are not enough registers free, an argument
878 may be passed partly in a register (or registers), and partly on the
879 stack. This includes doubles, long longs, and larger aggregates.
880 As far as I know, there is no upper limit to the size of aggregates
881 that will be passed in this way; in other words, the convention of
882 passing a pointer to a large aggregate instead of a copy is not used.
884 MVS: The above appears to be true for the SH variants that do not
885 have an FPU, however those that have an FPU appear to copy the
886 aggregate argument onto the stack (and not place it in registers)
887 if it is larger than 16 bytes (four GP registers).
889 An exceptional case exists for struct arguments (and possibly other
890 aggregates such as arrays) if the size is larger than 4 bytes but
891 not a multiple of 4 bytes. In this case the argument is never split
892 between the registers and the stack, but instead is copied in its
893 entirety onto the stack, AND also copied into as many registers as
894 there is room for. In other words, space in registers permitting,
895 two copies of the same argument are passed in. As far as I can tell,
896 only the one on the stack is used, although that may be a function
897 of the level of compiler optimization. I suspect this is a compiler
898 bug. Arguments of these odd sizes are left-justified within the
899 word (as opposed to arguments smaller than 4 bytes, which are
902 If the function is to return an aggregate type such as a struct, it
903 is either returned in the normal return value register R0 (if its
904 size is no greater than one byte), or else the caller must allocate
905 space into which the callee will copy the return value (if the size
906 is greater than one byte). In this case, a pointer to the return
907 value location is passed into the callee in register R2, which does
908 not displace any of the other arguments passed in via registers R4
911 /* Helper function to justify value in register according to endianess. */
913 sh_justify_value_in_reg (struct gdbarch
*gdbarch
, struct value
*val
, int len
)
915 static char valbuf
[4];
917 memset (valbuf
, 0, sizeof (valbuf
));
920 /* value gets right-justified in the register or stack word */
921 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
922 memcpy (valbuf
+ (4 - len
), (char *) value_contents (val
), len
);
924 memcpy (valbuf
, (char *) value_contents (val
), len
);
927 return (char *) value_contents (val
);
930 /* Helper function to eval number of bytes to allocate on stack. */
932 sh_stack_allocsize (int nargs
, struct value
**args
)
936 stack_alloc
+= ((TYPE_LENGTH (value_type (args
[nargs
])) + 3) & ~3);
940 /* Helper functions for getting the float arguments right. Registers usage
941 depends on the ABI and the endianess. The comments should enlighten how
942 it's intended to work. */
944 /* This array stores which of the float arg registers are already in use. */
945 static int flt_argreg_array
[FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
+ 1];
947 /* This function just resets the above array to "no reg used so far". */
949 sh_init_flt_argreg (void)
951 memset (flt_argreg_array
, 0, sizeof flt_argreg_array
);
954 /* This function returns the next register to use for float arg passing.
955 It returns either a valid value between FLOAT_ARG0_REGNUM and
956 FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns
957 FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available.
959 Note that register number 0 in flt_argreg_array corresponds with the
960 real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is
961 29) the parity of the register number is preserved, which is important
962 for the double register passing test (see the "argreg & 1" test below). */
964 sh_next_flt_argreg (struct gdbarch
*gdbarch
, int len
, struct type
*func_type
)
968 /* First search for the next free register. */
969 for (argreg
= 0; argreg
<= FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
;
971 if (!flt_argreg_array
[argreg
])
974 /* No register left? */
975 if (argreg
> FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
)
976 return FLOAT_ARGLAST_REGNUM
+ 1;
980 /* Doubles are always starting in a even register number. */
983 /* In gcc ABI, the skipped register is lost for further argument
984 passing now. Not so in Renesas ABI. */
985 if (!sh_is_renesas_calling_convention (func_type
))
986 flt_argreg_array
[argreg
] = 1;
990 /* No register left? */
991 if (argreg
> FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
)
992 return FLOAT_ARGLAST_REGNUM
+ 1;
994 /* Also mark the next register as used. */
995 flt_argreg_array
[argreg
+ 1] = 1;
997 else if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
998 && !sh_is_renesas_calling_convention (func_type
))
1000 /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */
1001 if (!flt_argreg_array
[argreg
+ 1])
1004 flt_argreg_array
[argreg
] = 1;
1005 return FLOAT_ARG0_REGNUM
+ argreg
;
1008 /* Helper function which figures out, if a type is treated like a float type.
1010 The FPU ABIs have a special way how to treat types as float types.
1011 Structures with exactly one member, which is of type float or double, are
1012 treated exactly as the base types float or double:
1022 are handled the same way as just
1028 As a result, arguments of these struct types are pushed into floating point
1029 registers exactly as floats or doubles, using the same decision algorithm.
1031 The same is valid if these types are used as function return types. The
1032 above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1
1033 or even using struct convention as it is for other structs. */
1036 sh_treat_as_flt_p (struct type
*type
)
1038 int len
= TYPE_LENGTH (type
);
1040 /* Ordinary float types are obviously treated as float. */
1041 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1043 /* Otherwise non-struct types are not treated as float. */
1044 if (TYPE_CODE (type
) != TYPE_CODE_STRUCT
)
1046 /* Otherwise structs with more than one memeber are not treated as float. */
1047 if (TYPE_NFIELDS (type
) != 1)
1049 /* Otherwise if the type of that member is float, the whole type is
1050 treated as float. */
1051 if (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0)) == TYPE_CODE_FLT
)
1053 /* Otherwise it's not treated as float. */
1058 sh_push_dummy_call_fpu (struct gdbarch
*gdbarch
,
1059 struct value
*function
,
1060 struct regcache
*regcache
,
1061 CORE_ADDR bp_addr
, int nargs
,
1062 struct value
**args
,
1063 CORE_ADDR sp
, int struct_return
,
1064 CORE_ADDR struct_addr
)
1066 int stack_offset
= 0;
1067 int argreg
= ARG0_REGNUM
;
1070 struct type
*func_type
= value_type (function
);
1074 int len
, reg_size
= 0;
1075 int pass_on_stack
= 0;
1077 int last_reg_arg
= INT_MAX
;
1079 /* The Renesas ABI expects all varargs arguments, plus the last
1080 non-vararg argument to be on the stack, no matter how many
1081 registers have been used so far. */
1082 if (sh_is_renesas_calling_convention (func_type
)
1083 && TYPE_VARARGS (func_type
))
1084 last_reg_arg
= TYPE_NFIELDS (func_type
) - 2;
1086 /* first force sp to a 4-byte alignment */
1087 sp
= sh_frame_align (gdbarch
, sp
);
1089 /* make room on stack for args */
1090 sp
-= sh_stack_allocsize (nargs
, args
);
1092 /* Initialize float argument mechanism. */
1093 sh_init_flt_argreg ();
1095 /* Now load as many as possible of the first arguments into
1096 registers, and push the rest onto the stack. There are 16 bytes
1097 in four registers available. Loop thru args from first to last. */
1098 for (argnum
= 0; argnum
< nargs
; argnum
++)
1100 type
= value_type (args
[argnum
]);
1101 len
= TYPE_LENGTH (type
);
1102 val
= sh_justify_value_in_reg (gdbarch
, args
[argnum
], len
);
1104 /* Some decisions have to be made how various types are handled.
1105 This also differs in different ABIs. */
1108 /* Find out the next register to use for a floating point value. */
1109 treat_as_flt
= sh_treat_as_flt_p (type
);
1111 flt_argreg
= sh_next_flt_argreg (gdbarch
, len
, func_type
);
1112 /* In Renesas ABI, long longs and aggregate types are always passed
1114 else if (sh_is_renesas_calling_convention (func_type
)
1115 && ((TYPE_CODE (type
) == TYPE_CODE_INT
&& len
== 8)
1116 || TYPE_CODE (type
) == TYPE_CODE_STRUCT
1117 || TYPE_CODE (type
) == TYPE_CODE_UNION
))
1119 /* In contrast to non-FPU CPUs, arguments are never split between
1120 registers and stack. If an argument doesn't fit in the remaining
1121 registers it's always pushed entirely on the stack. */
1122 else if (len
> ((ARGLAST_REGNUM
- argreg
+ 1) * 4))
1127 if ((treat_as_flt
&& flt_argreg
> FLOAT_ARGLAST_REGNUM
)
1128 || (!treat_as_flt
&& (argreg
> ARGLAST_REGNUM
1130 || argnum
> last_reg_arg
)
1132 /* The data goes entirely on the stack, 4-byte aligned. */
1133 reg_size
= (len
+ 3) & ~3;
1134 write_memory (sp
+ stack_offset
, val
, reg_size
);
1135 stack_offset
+= reg_size
;
1137 else if (treat_as_flt
&& flt_argreg
<= FLOAT_ARGLAST_REGNUM
)
1139 /* Argument goes in a float argument register. */
1140 reg_size
= register_size (gdbarch
, flt_argreg
);
1141 regval
= extract_unsigned_integer (val
, reg_size
);
1142 /* In little endian mode, float types taking two registers
1143 (doubles on sh4, long doubles on sh2e, sh3e and sh4) must
1144 be stored swapped in the argument registers. The below
1145 code first writes the first 32 bits in the next but one
1146 register, increments the val and len values accordingly
1147 and then proceeds as normal by writing the second 32 bits
1148 into the next register. */
1149 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
1150 && TYPE_LENGTH (type
) == 2 * reg_size
)
1152 regcache_cooked_write_unsigned (regcache
, flt_argreg
+ 1,
1156 regval
= extract_unsigned_integer (val
, reg_size
);
1158 regcache_cooked_write_unsigned (regcache
, flt_argreg
++, regval
);
1160 else if (!treat_as_flt
&& argreg
<= ARGLAST_REGNUM
)
1162 /* there's room in a register */
1163 reg_size
= register_size (gdbarch
, argreg
);
1164 regval
= extract_unsigned_integer (val
, reg_size
);
1165 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
1167 /* Store the value one register at a time or in one step on stack. */
1175 if (sh_is_renesas_calling_convention (func_type
))
1176 /* If the function uses the Renesas ABI, subtract another 4 bytes from
1177 the stack and store the struct return address there. */
1178 write_memory_unsigned_integer (sp
-= 4, 4, struct_addr
);
1180 /* Using the gcc ABI, the "struct return pointer" pseudo-argument has
1181 its own dedicated register. */
1182 regcache_cooked_write_unsigned (regcache
,
1183 STRUCT_RETURN_REGNUM
, struct_addr
);
1186 /* Store return address. */
1187 regcache_cooked_write_unsigned (regcache
, PR_REGNUM
, bp_addr
);
1189 /* Update stack pointer. */
1190 regcache_cooked_write_unsigned (regcache
,
1191 gdbarch_sp_regnum (gdbarch
), sp
);
1197 sh_push_dummy_call_nofpu (struct gdbarch
*gdbarch
,
1198 struct value
*function
,
1199 struct regcache
*regcache
,
1201 int nargs
, struct value
**args
,
1202 CORE_ADDR sp
, int struct_return
,
1203 CORE_ADDR struct_addr
)
1205 int stack_offset
= 0;
1206 int argreg
= ARG0_REGNUM
;
1208 struct type
*func_type
= value_type (function
);
1212 int len
, reg_size
= 0;
1213 int pass_on_stack
= 0;
1214 int last_reg_arg
= INT_MAX
;
1216 /* The Renesas ABI expects all varargs arguments, plus the last
1217 non-vararg argument to be on the stack, no matter how many
1218 registers have been used so far. */
1219 if (sh_is_renesas_calling_convention (func_type
)
1220 && TYPE_VARARGS (func_type
))
1221 last_reg_arg
= TYPE_NFIELDS (func_type
) - 2;
1223 /* first force sp to a 4-byte alignment */
1224 sp
= sh_frame_align (gdbarch
, sp
);
1226 /* make room on stack for args */
1227 sp
-= sh_stack_allocsize (nargs
, args
);
1229 /* Now load as many as possible of the first arguments into
1230 registers, and push the rest onto the stack. There are 16 bytes
1231 in four registers available. Loop thru args from first to last. */
1232 for (argnum
= 0; argnum
< nargs
; argnum
++)
1234 type
= value_type (args
[argnum
]);
1235 len
= TYPE_LENGTH (type
);
1236 val
= sh_justify_value_in_reg (gdbarch
, args
[argnum
], len
);
1238 /* Some decisions have to be made how various types are handled.
1239 This also differs in different ABIs. */
1241 /* Renesas ABI pushes doubles and long longs entirely on stack.
1242 Same goes for aggregate types. */
1243 if (sh_is_renesas_calling_convention (func_type
)
1244 && ((TYPE_CODE (type
) == TYPE_CODE_INT
&& len
>= 8)
1245 || (TYPE_CODE (type
) == TYPE_CODE_FLT
&& len
>= 8)
1246 || TYPE_CODE (type
) == TYPE_CODE_STRUCT
1247 || TYPE_CODE (type
) == TYPE_CODE_UNION
))
1251 if (argreg
> ARGLAST_REGNUM
|| pass_on_stack
1252 || argnum
> last_reg_arg
)
1254 /* The remainder of the data goes entirely on the stack,
1256 reg_size
= (len
+ 3) & ~3;
1257 write_memory (sp
+ stack_offset
, val
, reg_size
);
1258 stack_offset
+= reg_size
;
1260 else if (argreg
<= ARGLAST_REGNUM
)
1262 /* there's room in a register */
1263 reg_size
= register_size (gdbarch
, argreg
);
1264 regval
= extract_unsigned_integer (val
, reg_size
);
1265 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
1267 /* Store the value reg_size bytes at a time. This means that things
1268 larger than reg_size bytes may go partly in registers and partly
1277 if (sh_is_renesas_calling_convention (func_type
))
1278 /* If the function uses the Renesas ABI, subtract another 4 bytes from
1279 the stack and store the struct return address there. */
1280 write_memory_unsigned_integer (sp
-= 4, 4, struct_addr
);
1282 /* Using the gcc ABI, the "struct return pointer" pseudo-argument has
1283 its own dedicated register. */
1284 regcache_cooked_write_unsigned (regcache
,
1285 STRUCT_RETURN_REGNUM
, struct_addr
);
1288 /* Store return address. */
1289 regcache_cooked_write_unsigned (regcache
, PR_REGNUM
, bp_addr
);
1291 /* Update stack pointer. */
1292 regcache_cooked_write_unsigned (regcache
,
1293 gdbarch_sp_regnum (gdbarch
), sp
);
1298 /* Find a function's return value in the appropriate registers (in
1299 regbuf), and copy it into valbuf. Extract from an array REGBUF
1300 containing the (raw) register state a function return value of type
1301 TYPE, and copy that, in virtual format, into VALBUF. */
1303 sh_extract_return_value_nofpu (struct type
*type
, struct regcache
*regcache
,
1306 int len
= TYPE_LENGTH (type
);
1307 int return_register
= R0_REGNUM
;
1314 regcache_cooked_read_unsigned (regcache
, R0_REGNUM
, &c
);
1315 store_unsigned_integer (valbuf
, len
, c
);
1319 int i
, regnum
= R0_REGNUM
;
1320 for (i
= 0; i
< len
; i
+= 4)
1321 regcache_raw_read (regcache
, regnum
++, (char *) valbuf
+ i
);
1324 error (_("bad size for return value"));
1328 sh_extract_return_value_fpu (struct type
*type
, struct regcache
*regcache
,
1331 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1332 if (sh_treat_as_flt_p (type
))
1334 int len
= TYPE_LENGTH (type
);
1335 int i
, regnum
= gdbarch_fp0_regnum (gdbarch
);
1336 for (i
= 0; i
< len
; i
+= 4)
1337 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
1338 regcache_raw_read (regcache
, regnum
++, (char *) valbuf
+ len
- 4 - i
);
1340 regcache_raw_read (regcache
, regnum
++, (char *) valbuf
+ i
);
1343 sh_extract_return_value_nofpu (type
, regcache
, valbuf
);
1346 /* Write into appropriate registers a function return value
1347 of type TYPE, given in virtual format.
1348 If the architecture is sh4 or sh3e, store a function's return value
1349 in the R0 general register or in the FP0 floating point register,
1350 depending on the type of the return value. In all the other cases
1351 the result is stored in r0, left-justified. */
1353 sh_store_return_value_nofpu (struct type
*type
, struct regcache
*regcache
,
1357 int len
= TYPE_LENGTH (type
);
1361 val
= extract_unsigned_integer (valbuf
, len
);
1362 regcache_cooked_write_unsigned (regcache
, R0_REGNUM
, val
);
1366 int i
, regnum
= R0_REGNUM
;
1367 for (i
= 0; i
< len
; i
+= 4)
1368 regcache_raw_write (regcache
, regnum
++, (char *) valbuf
+ i
);
1373 sh_store_return_value_fpu (struct type
*type
, struct regcache
*regcache
,
1376 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1377 if (sh_treat_as_flt_p (type
))
1379 int len
= TYPE_LENGTH (type
);
1380 int i
, regnum
= gdbarch_fp0_regnum (gdbarch
);
1381 for (i
= 0; i
< len
; i
+= 4)
1382 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
1383 regcache_raw_write (regcache
, regnum
++,
1384 (char *) valbuf
+ len
- 4 - i
);
1386 regcache_raw_write (regcache
, regnum
++, (char *) valbuf
+ i
);
1389 sh_store_return_value_nofpu (type
, regcache
, valbuf
);
1392 static enum return_value_convention
1393 sh_return_value_nofpu (struct gdbarch
*gdbarch
, struct type
*func_type
,
1394 struct type
*type
, struct regcache
*regcache
,
1395 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1397 if (sh_use_struct_convention_nofpu (
1398 sh_is_renesas_calling_convention (func_type
), type
))
1399 return RETURN_VALUE_STRUCT_CONVENTION
;
1401 sh_store_return_value_nofpu (type
, regcache
, writebuf
);
1403 sh_extract_return_value_nofpu (type
, regcache
, readbuf
);
1404 return RETURN_VALUE_REGISTER_CONVENTION
;
1407 static enum return_value_convention
1408 sh_return_value_fpu (struct gdbarch
*gdbarch
, struct type
*func_type
,
1409 struct type
*type
, struct regcache
*regcache
,
1410 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1412 if (sh_use_struct_convention (
1413 sh_is_renesas_calling_convention (func_type
), type
))
1414 return RETURN_VALUE_STRUCT_CONVENTION
;
1416 sh_store_return_value_fpu (type
, regcache
, writebuf
);
1418 sh_extract_return_value_fpu (type
, regcache
, readbuf
);
1419 return RETURN_VALUE_REGISTER_CONVENTION
;
1422 /* Print the registers in a form similar to the E7000 */
1425 sh_generic_show_regs (struct frame_info
*frame
)
1428 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1429 paddr (get_frame_register_unsigned (frame
,
1431 (get_frame_arch (frame
)))),
1432 (long) get_frame_register_unsigned (frame
, SR_REGNUM
),
1433 (long) get_frame_register_unsigned (frame
, PR_REGNUM
),
1434 (long) get_frame_register_unsigned (frame
, MACH_REGNUM
));
1437 (" GBR %08lx VBR %08lx MACL %08lx\n",
1438 (long) get_frame_register_unsigned (frame
, GBR_REGNUM
),
1439 (long) get_frame_register_unsigned (frame
, VBR_REGNUM
),
1440 (long) get_frame_register_unsigned (frame
, MACL_REGNUM
));
1443 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1444 (long) get_frame_register_unsigned (frame
, 0),
1445 (long) get_frame_register_unsigned (frame
, 1),
1446 (long) get_frame_register_unsigned (frame
, 2),
1447 (long) get_frame_register_unsigned (frame
, 3),
1448 (long) get_frame_register_unsigned (frame
, 4),
1449 (long) get_frame_register_unsigned (frame
, 5),
1450 (long) get_frame_register_unsigned (frame
, 6),
1451 (long) get_frame_register_unsigned (frame
, 7));
1453 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1454 (long) get_frame_register_unsigned (frame
, 8),
1455 (long) get_frame_register_unsigned (frame
, 9),
1456 (long) get_frame_register_unsigned (frame
, 10),
1457 (long) get_frame_register_unsigned (frame
, 11),
1458 (long) get_frame_register_unsigned (frame
, 12),
1459 (long) get_frame_register_unsigned (frame
, 13),
1460 (long) get_frame_register_unsigned (frame
, 14),
1461 (long) get_frame_register_unsigned (frame
, 15));
1465 sh3_show_regs (struct frame_info
*frame
)
1468 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1469 paddr (get_frame_register_unsigned (frame
,
1471 (get_frame_arch (frame
)))),
1472 (long) get_frame_register_unsigned (frame
, SR_REGNUM
),
1473 (long) get_frame_register_unsigned (frame
, PR_REGNUM
),
1474 (long) get_frame_register_unsigned (frame
, MACH_REGNUM
));
1477 (" GBR %08lx VBR %08lx MACL %08lx\n",
1478 (long) get_frame_register_unsigned (frame
, GBR_REGNUM
),
1479 (long) get_frame_register_unsigned (frame
, VBR_REGNUM
),
1480 (long) get_frame_register_unsigned (frame
, MACL_REGNUM
));
1482 (" SSR %08lx SPC %08lx\n",
1483 (long) get_frame_register_unsigned (frame
, SSR_REGNUM
),
1484 (long) get_frame_register_unsigned (frame
, SPC_REGNUM
));
1487 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1488 (long) get_frame_register_unsigned (frame
, 0),
1489 (long) get_frame_register_unsigned (frame
, 1),
1490 (long) get_frame_register_unsigned (frame
, 2),
1491 (long) get_frame_register_unsigned (frame
, 3),
1492 (long) get_frame_register_unsigned (frame
, 4),
1493 (long) get_frame_register_unsigned (frame
, 5),
1494 (long) get_frame_register_unsigned (frame
, 6),
1495 (long) get_frame_register_unsigned (frame
, 7));
1497 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1498 (long) get_frame_register_unsigned (frame
, 8),
1499 (long) get_frame_register_unsigned (frame
, 9),
1500 (long) get_frame_register_unsigned (frame
, 10),
1501 (long) get_frame_register_unsigned (frame
, 11),
1502 (long) get_frame_register_unsigned (frame
, 12),
1503 (long) get_frame_register_unsigned (frame
, 13),
1504 (long) get_frame_register_unsigned (frame
, 14),
1505 (long) get_frame_register_unsigned (frame
, 15));
1509 sh2e_show_regs (struct frame_info
*frame
)
1511 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1513 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1514 paddr (get_frame_register_unsigned (frame
,
1515 gdbarch_pc_regnum (gdbarch
))),
1516 (long) get_frame_register_unsigned (frame
, SR_REGNUM
),
1517 (long) get_frame_register_unsigned (frame
, PR_REGNUM
),
1518 (long) get_frame_register_unsigned (frame
, MACH_REGNUM
));
1521 (" GBR %08lx VBR %08lx MACL %08lx\n",
1522 (long) get_frame_register_unsigned (frame
, GBR_REGNUM
),
1523 (long) get_frame_register_unsigned (frame
, VBR_REGNUM
),
1524 (long) get_frame_register_unsigned (frame
, MACL_REGNUM
));
1526 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1527 (long) get_frame_register_unsigned (frame
, SSR_REGNUM
),
1528 (long) get_frame_register_unsigned (frame
, SPC_REGNUM
),
1529 (long) get_frame_register_unsigned (frame
, FPUL_REGNUM
),
1530 (long) get_frame_register_unsigned (frame
, FPSCR_REGNUM
));
1533 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1534 (long) get_frame_register_unsigned (frame
, 0),
1535 (long) get_frame_register_unsigned (frame
, 1),
1536 (long) get_frame_register_unsigned (frame
, 2),
1537 (long) get_frame_register_unsigned (frame
, 3),
1538 (long) get_frame_register_unsigned (frame
, 4),
1539 (long) get_frame_register_unsigned (frame
, 5),
1540 (long) get_frame_register_unsigned (frame
, 6),
1541 (long) get_frame_register_unsigned (frame
, 7));
1543 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1544 (long) get_frame_register_unsigned (frame
, 8),
1545 (long) get_frame_register_unsigned (frame
, 9),
1546 (long) get_frame_register_unsigned (frame
, 10),
1547 (long) get_frame_register_unsigned (frame
, 11),
1548 (long) get_frame_register_unsigned (frame
, 12),
1549 (long) get_frame_register_unsigned (frame
, 13),
1550 (long) get_frame_register_unsigned (frame
, 14),
1551 (long) get_frame_register_unsigned (frame
, 15));
1554 ("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1555 (long) get_frame_register_unsigned
1556 (frame
, gdbarch_fp0_regnum (gdbarch
) + 0),
1557 (long) get_frame_register_unsigned
1558 (frame
, gdbarch_fp0_regnum (gdbarch
) + 1),
1559 (long) get_frame_register_unsigned
1560 (frame
, gdbarch_fp0_regnum (gdbarch
) + 2),
1561 (long) get_frame_register_unsigned
1562 (frame
, gdbarch_fp0_regnum (gdbarch
) + 3),
1563 (long) get_frame_register_unsigned
1564 (frame
, gdbarch_fp0_regnum (gdbarch
) + 4),
1565 (long) get_frame_register_unsigned
1566 (frame
, gdbarch_fp0_regnum (gdbarch
) + 5),
1567 (long) get_frame_register_unsigned
1568 (frame
, gdbarch_fp0_regnum (gdbarch
) + 6),
1569 (long) get_frame_register_unsigned
1570 (frame
, gdbarch_fp0_regnum (gdbarch
) + 7));
1572 ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1573 (long) get_frame_register_unsigned
1574 (frame
, gdbarch_fp0_regnum (gdbarch
) + 8),
1575 (long) get_frame_register_unsigned
1576 (frame
, gdbarch_fp0_regnum (gdbarch
) + 9),
1577 (long) get_frame_register_unsigned
1578 (frame
, gdbarch_fp0_regnum (gdbarch
) + 10),
1579 (long) get_frame_register_unsigned
1580 (frame
, gdbarch_fp0_regnum (gdbarch
) + 11),
1581 (long) get_frame_register_unsigned
1582 (frame
, gdbarch_fp0_regnum (gdbarch
) + 12),
1583 (long) get_frame_register_unsigned
1584 (frame
, gdbarch_fp0_regnum (gdbarch
) + 13),
1585 (long) get_frame_register_unsigned
1586 (frame
, gdbarch_fp0_regnum (gdbarch
) + 14),
1587 (long) get_frame_register_unsigned
1588 (frame
, gdbarch_fp0_regnum (gdbarch
) + 15));
1592 sh2a_show_regs (struct frame_info
*frame
)
1594 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1595 int pr
= get_frame_register_unsigned (frame
, FPSCR_REGNUM
) & 0x80000;
1598 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1599 paddr (get_frame_register_unsigned (frame
,
1600 gdbarch_pc_regnum (gdbarch
))),
1601 (long) get_frame_register_unsigned (frame
, SR_REGNUM
),
1602 (long) get_frame_register_unsigned (frame
, PR_REGNUM
),
1603 (long) get_frame_register_unsigned (frame
, MACH_REGNUM
));
1606 (" GBR %08lx VBR %08lx TBR %08lx MACL %08lx\n",
1607 (long) get_frame_register_unsigned (frame
, GBR_REGNUM
),
1608 (long) get_frame_register_unsigned (frame
, VBR_REGNUM
),
1609 (long) get_frame_register_unsigned (frame
, TBR_REGNUM
),
1610 (long) get_frame_register_unsigned (frame
, MACL_REGNUM
));
1612 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1613 (long) get_frame_register_unsigned (frame
, SSR_REGNUM
),
1614 (long) get_frame_register_unsigned (frame
, SPC_REGNUM
),
1615 (long) get_frame_register_unsigned (frame
, FPUL_REGNUM
),
1616 (long) get_frame_register_unsigned (frame
, FPSCR_REGNUM
));
1619 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1620 (long) get_frame_register_unsigned (frame
, 0),
1621 (long) get_frame_register_unsigned (frame
, 1),
1622 (long) get_frame_register_unsigned (frame
, 2),
1623 (long) get_frame_register_unsigned (frame
, 3),
1624 (long) get_frame_register_unsigned (frame
, 4),
1625 (long) get_frame_register_unsigned (frame
, 5),
1626 (long) get_frame_register_unsigned (frame
, 6),
1627 (long) get_frame_register_unsigned (frame
, 7));
1629 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1630 (long) get_frame_register_unsigned (frame
, 8),
1631 (long) get_frame_register_unsigned (frame
, 9),
1632 (long) get_frame_register_unsigned (frame
, 10),
1633 (long) get_frame_register_unsigned (frame
, 11),
1634 (long) get_frame_register_unsigned (frame
, 12),
1635 (long) get_frame_register_unsigned (frame
, 13),
1636 (long) get_frame_register_unsigned (frame
, 14),
1637 (long) get_frame_register_unsigned (frame
, 15));
1640 (pr
? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1641 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1642 (long) get_frame_register_unsigned
1643 (frame
, gdbarch_fp0_regnum (gdbarch
) + 0),
1644 (long) get_frame_register_unsigned
1645 (frame
, gdbarch_fp0_regnum (gdbarch
) + 1),
1646 (long) get_frame_register_unsigned
1647 (frame
, gdbarch_fp0_regnum (gdbarch
) + 2),
1648 (long) get_frame_register_unsigned
1649 (frame
, gdbarch_fp0_regnum (gdbarch
) + 3),
1650 (long) get_frame_register_unsigned
1651 (frame
, gdbarch_fp0_regnum (gdbarch
) + 4),
1652 (long) get_frame_register_unsigned
1653 (frame
, gdbarch_fp0_regnum (gdbarch
) + 5),
1654 (long) get_frame_register_unsigned
1655 (frame
, gdbarch_fp0_regnum (gdbarch
) + 6),
1656 (long) get_frame_register_unsigned
1657 (frame
, gdbarch_fp0_regnum (gdbarch
) + 7));
1659 (pr
? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1660 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1661 (long) get_frame_register_unsigned
1662 (frame
, gdbarch_fp0_regnum (gdbarch
) + 8),
1663 (long) get_frame_register_unsigned
1664 (frame
, gdbarch_fp0_regnum (gdbarch
) + 9),
1665 (long) get_frame_register_unsigned
1666 (frame
, gdbarch_fp0_regnum (gdbarch
) + 10),
1667 (long) get_frame_register_unsigned
1668 (frame
, gdbarch_fp0_regnum (gdbarch
) + 11),
1669 (long) get_frame_register_unsigned
1670 (frame
, gdbarch_fp0_regnum (gdbarch
) + 12),
1671 (long) get_frame_register_unsigned
1672 (frame
, gdbarch_fp0_regnum (gdbarch
) + 13),
1673 (long) get_frame_register_unsigned
1674 (frame
, gdbarch_fp0_regnum (gdbarch
) + 14),
1675 (long) get_frame_register_unsigned
1676 (frame
, gdbarch_fp0_regnum (gdbarch
) + 15));
1678 ("BANK=%-3d\n", (int) get_frame_register_unsigned (frame
, BANK_REGNUM
));
1680 ("R0b-R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1681 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 0),
1682 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 1),
1683 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 2),
1684 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 3),
1685 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 4),
1686 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 5),
1687 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 6),
1688 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 7));
1690 ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1691 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 8),
1692 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 9),
1693 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 10),
1694 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 11),
1695 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 12),
1696 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 13),
1697 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 14));
1699 ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n",
1700 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 15),
1701 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 16),
1702 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 17),
1703 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 18),
1704 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 19));
1708 sh2a_nofpu_show_regs (struct frame_info
*frame
)
1710 int pr
= get_frame_register_unsigned (frame
, FPSCR_REGNUM
) & 0x80000;
1713 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1714 paddr (get_frame_register_unsigned (frame
,
1716 (get_frame_arch (frame
)))),
1717 (long) get_frame_register_unsigned (frame
, SR_REGNUM
),
1718 (long) get_frame_register_unsigned (frame
, PR_REGNUM
),
1719 (long) get_frame_register_unsigned (frame
, MACH_REGNUM
));
1722 (" GBR %08lx VBR %08lx TBR %08lx MACL %08lx\n",
1723 (long) get_frame_register_unsigned (frame
, GBR_REGNUM
),
1724 (long) get_frame_register_unsigned (frame
, VBR_REGNUM
),
1725 (long) get_frame_register_unsigned (frame
, TBR_REGNUM
),
1726 (long) get_frame_register_unsigned (frame
, MACL_REGNUM
));
1728 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1729 (long) get_frame_register_unsigned (frame
, SSR_REGNUM
),
1730 (long) get_frame_register_unsigned (frame
, SPC_REGNUM
),
1731 (long) get_frame_register_unsigned (frame
, FPUL_REGNUM
),
1732 (long) get_frame_register_unsigned (frame
, FPSCR_REGNUM
));
1735 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1736 (long) get_frame_register_unsigned (frame
, 0),
1737 (long) get_frame_register_unsigned (frame
, 1),
1738 (long) get_frame_register_unsigned (frame
, 2),
1739 (long) get_frame_register_unsigned (frame
, 3),
1740 (long) get_frame_register_unsigned (frame
, 4),
1741 (long) get_frame_register_unsigned (frame
, 5),
1742 (long) get_frame_register_unsigned (frame
, 6),
1743 (long) get_frame_register_unsigned (frame
, 7));
1745 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1746 (long) get_frame_register_unsigned (frame
, 8),
1747 (long) get_frame_register_unsigned (frame
, 9),
1748 (long) get_frame_register_unsigned (frame
, 10),
1749 (long) get_frame_register_unsigned (frame
, 11),
1750 (long) get_frame_register_unsigned (frame
, 12),
1751 (long) get_frame_register_unsigned (frame
, 13),
1752 (long) get_frame_register_unsigned (frame
, 14),
1753 (long) get_frame_register_unsigned (frame
, 15));
1756 ("BANK=%-3d\n", (int) get_frame_register_unsigned (frame
, BANK_REGNUM
));
1758 ("R0b-R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1759 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 0),
1760 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 1),
1761 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 2),
1762 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 3),
1763 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 4),
1764 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 5),
1765 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 6),
1766 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 7));
1768 ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1769 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 8),
1770 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 9),
1771 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 10),
1772 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 11),
1773 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 12),
1774 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 13),
1775 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 14));
1777 ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n",
1778 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 15),
1779 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 16),
1780 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 17),
1781 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 18),
1782 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 19));
1786 sh3e_show_regs (struct frame_info
*frame
)
1788 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1790 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1791 paddr (get_frame_register_unsigned (frame
,
1792 gdbarch_pc_regnum (gdbarch
))),
1793 (long) get_frame_register_unsigned (frame
, SR_REGNUM
),
1794 (long) get_frame_register_unsigned (frame
, PR_REGNUM
),
1795 (long) get_frame_register_unsigned (frame
, MACH_REGNUM
));
1798 (" GBR %08lx VBR %08lx MACL %08lx\n",
1799 (long) get_frame_register_unsigned (frame
, GBR_REGNUM
),
1800 (long) get_frame_register_unsigned (frame
, VBR_REGNUM
),
1801 (long) get_frame_register_unsigned (frame
, MACL_REGNUM
));
1803 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1804 (long) get_frame_register_unsigned (frame
, SSR_REGNUM
),
1805 (long) get_frame_register_unsigned (frame
, SPC_REGNUM
),
1806 (long) get_frame_register_unsigned (frame
, FPUL_REGNUM
),
1807 (long) get_frame_register_unsigned (frame
, FPSCR_REGNUM
));
1810 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1811 (long) get_frame_register_unsigned (frame
, 0),
1812 (long) get_frame_register_unsigned (frame
, 1),
1813 (long) get_frame_register_unsigned (frame
, 2),
1814 (long) get_frame_register_unsigned (frame
, 3),
1815 (long) get_frame_register_unsigned (frame
, 4),
1816 (long) get_frame_register_unsigned (frame
, 5),
1817 (long) get_frame_register_unsigned (frame
, 6),
1818 (long) get_frame_register_unsigned (frame
, 7));
1820 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1821 (long) get_frame_register_unsigned (frame
, 8),
1822 (long) get_frame_register_unsigned (frame
, 9),
1823 (long) get_frame_register_unsigned (frame
, 10),
1824 (long) get_frame_register_unsigned (frame
, 11),
1825 (long) get_frame_register_unsigned (frame
, 12),
1826 (long) get_frame_register_unsigned (frame
, 13),
1827 (long) get_frame_register_unsigned (frame
, 14),
1828 (long) get_frame_register_unsigned (frame
, 15));
1831 ("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1832 (long) get_frame_register_unsigned
1833 (frame
, gdbarch_fp0_regnum (gdbarch
) + 0),
1834 (long) get_frame_register_unsigned
1835 (frame
, gdbarch_fp0_regnum (gdbarch
) + 1),
1836 (long) get_frame_register_unsigned
1837 (frame
, gdbarch_fp0_regnum (gdbarch
) + 2),
1838 (long) get_frame_register_unsigned
1839 (frame
, gdbarch_fp0_regnum (gdbarch
) + 3),
1840 (long) get_frame_register_unsigned
1841 (frame
, gdbarch_fp0_regnum (gdbarch
) + 4),
1842 (long) get_frame_register_unsigned
1843 (frame
, gdbarch_fp0_regnum (gdbarch
) + 5),
1844 (long) get_frame_register_unsigned
1845 (frame
, gdbarch_fp0_regnum (gdbarch
) + 6),
1846 (long) get_frame_register_unsigned
1847 (frame
, gdbarch_fp0_regnum (gdbarch
) + 7));
1849 ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1850 (long) get_frame_register_unsigned
1851 (frame
, gdbarch_fp0_regnum (gdbarch
) + 8),
1852 (long) get_frame_register_unsigned
1853 (frame
, gdbarch_fp0_regnum (gdbarch
) + 9),
1854 (long) get_frame_register_unsigned
1855 (frame
, gdbarch_fp0_regnum (gdbarch
) + 10),
1856 (long) get_frame_register_unsigned
1857 (frame
, gdbarch_fp0_regnum (gdbarch
) + 11),
1858 (long) get_frame_register_unsigned
1859 (frame
, gdbarch_fp0_regnum (gdbarch
) + 12),
1860 (long) get_frame_register_unsigned
1861 (frame
, gdbarch_fp0_regnum (gdbarch
) + 13),
1862 (long) get_frame_register_unsigned
1863 (frame
, gdbarch_fp0_regnum (gdbarch
) + 14),
1864 (long) get_frame_register_unsigned
1865 (frame
, gdbarch_fp0_regnum (gdbarch
) + 15));
1869 sh3_dsp_show_regs (struct frame_info
*frame
)
1872 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1873 paddr (get_frame_register_unsigned (frame
,
1875 (get_frame_arch (frame
)))),
1876 (long) get_frame_register_unsigned (frame
, SR_REGNUM
),
1877 (long) get_frame_register_unsigned (frame
, PR_REGNUM
),
1878 (long) get_frame_register_unsigned (frame
, MACH_REGNUM
));
1881 (" GBR %08lx VBR %08lx MACL %08lx\n",
1882 (long) get_frame_register_unsigned (frame
, GBR_REGNUM
),
1883 (long) get_frame_register_unsigned (frame
, VBR_REGNUM
),
1884 (long) get_frame_register_unsigned (frame
, MACL_REGNUM
));
1887 (" SSR %08lx SPC %08lx DSR %08lx\n",
1888 (long) get_frame_register_unsigned (frame
, SSR_REGNUM
),
1889 (long) get_frame_register_unsigned (frame
, SPC_REGNUM
),
1890 (long) get_frame_register_unsigned (frame
, DSR_REGNUM
));
1893 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1894 (long) get_frame_register_unsigned (frame
, 0),
1895 (long) get_frame_register_unsigned (frame
, 1),
1896 (long) get_frame_register_unsigned (frame
, 2),
1897 (long) get_frame_register_unsigned (frame
, 3),
1898 (long) get_frame_register_unsigned (frame
, 4),
1899 (long) get_frame_register_unsigned (frame
, 5),
1900 (long) get_frame_register_unsigned (frame
, 6),
1901 (long) get_frame_register_unsigned (frame
, 7));
1903 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1904 (long) get_frame_register_unsigned (frame
, 8),
1905 (long) get_frame_register_unsigned (frame
, 9),
1906 (long) get_frame_register_unsigned (frame
, 10),
1907 (long) get_frame_register_unsigned (frame
, 11),
1908 (long) get_frame_register_unsigned (frame
, 12),
1909 (long) get_frame_register_unsigned (frame
, 13),
1910 (long) get_frame_register_unsigned (frame
, 14),
1911 (long) get_frame_register_unsigned (frame
, 15));
1914 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1915 (long) get_frame_register_unsigned (frame
, A0G_REGNUM
) & 0xff,
1916 (long) get_frame_register_unsigned (frame
, A0_REGNUM
),
1917 (long) get_frame_register_unsigned (frame
, M0_REGNUM
),
1918 (long) get_frame_register_unsigned (frame
, X0_REGNUM
),
1919 (long) get_frame_register_unsigned (frame
, Y0_REGNUM
),
1920 (long) get_frame_register_unsigned (frame
, RS_REGNUM
),
1921 (long) get_frame_register_unsigned (frame
, MOD_REGNUM
));
1923 ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1924 (long) get_frame_register_unsigned (frame
, A1G_REGNUM
) & 0xff,
1925 (long) get_frame_register_unsigned (frame
, A1_REGNUM
),
1926 (long) get_frame_register_unsigned (frame
, M1_REGNUM
),
1927 (long) get_frame_register_unsigned (frame
, X1_REGNUM
),
1928 (long) get_frame_register_unsigned (frame
, Y1_REGNUM
),
1929 (long) get_frame_register_unsigned (frame
, RE_REGNUM
));
1933 sh4_show_regs (struct frame_info
*frame
)
1935 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1936 int pr
= get_frame_register_unsigned (frame
, FPSCR_REGNUM
) & 0x80000;
1939 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1940 paddr (get_frame_register_unsigned (frame
,
1941 gdbarch_pc_regnum (gdbarch
))),
1942 (long) get_frame_register_unsigned (frame
, SR_REGNUM
),
1943 (long) get_frame_register_unsigned (frame
, PR_REGNUM
),
1944 (long) get_frame_register_unsigned (frame
, MACH_REGNUM
));
1947 (" GBR %08lx VBR %08lx MACL %08lx\n",
1948 (long) get_frame_register_unsigned (frame
, GBR_REGNUM
),
1949 (long) get_frame_register_unsigned (frame
, VBR_REGNUM
),
1950 (long) get_frame_register_unsigned (frame
, MACL_REGNUM
));
1952 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1953 (long) get_frame_register_unsigned (frame
, SSR_REGNUM
),
1954 (long) get_frame_register_unsigned (frame
, SPC_REGNUM
),
1955 (long) get_frame_register_unsigned (frame
, FPUL_REGNUM
),
1956 (long) get_frame_register_unsigned (frame
, FPSCR_REGNUM
));
1959 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1960 (long) get_frame_register_unsigned (frame
, 0),
1961 (long) get_frame_register_unsigned (frame
, 1),
1962 (long) get_frame_register_unsigned (frame
, 2),
1963 (long) get_frame_register_unsigned (frame
, 3),
1964 (long) get_frame_register_unsigned (frame
, 4),
1965 (long) get_frame_register_unsigned (frame
, 5),
1966 (long) get_frame_register_unsigned (frame
, 6),
1967 (long) get_frame_register_unsigned (frame
, 7));
1969 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1970 (long) get_frame_register_unsigned (frame
, 8),
1971 (long) get_frame_register_unsigned (frame
, 9),
1972 (long) get_frame_register_unsigned (frame
, 10),
1973 (long) get_frame_register_unsigned (frame
, 11),
1974 (long) get_frame_register_unsigned (frame
, 12),
1975 (long) get_frame_register_unsigned (frame
, 13),
1976 (long) get_frame_register_unsigned (frame
, 14),
1977 (long) get_frame_register_unsigned (frame
, 15));
1980 (pr
? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1981 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1982 (long) get_frame_register_unsigned
1983 (frame
, gdbarch_fp0_regnum (gdbarch
) + 0),
1984 (long) get_frame_register_unsigned
1985 (frame
, gdbarch_fp0_regnum (gdbarch
) + 1),
1986 (long) get_frame_register_unsigned
1987 (frame
, gdbarch_fp0_regnum (gdbarch
) + 2),
1988 (long) get_frame_register_unsigned
1989 (frame
, gdbarch_fp0_regnum (gdbarch
) + 3),
1990 (long) get_frame_register_unsigned
1991 (frame
, gdbarch_fp0_regnum (gdbarch
) + 4),
1992 (long) get_frame_register_unsigned
1993 (frame
, gdbarch_fp0_regnum (gdbarch
) + 5),
1994 (long) get_frame_register_unsigned
1995 (frame
, gdbarch_fp0_regnum (gdbarch
) + 6),
1996 (long) get_frame_register_unsigned
1997 (frame
, gdbarch_fp0_regnum (gdbarch
) + 7));
1999 (pr
? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
2000 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2001 (long) get_frame_register_unsigned
2002 (frame
, gdbarch_fp0_regnum (gdbarch
) + 8),
2003 (long) get_frame_register_unsigned
2004 (frame
, gdbarch_fp0_regnum (gdbarch
) + 9),
2005 (long) get_frame_register_unsigned
2006 (frame
, gdbarch_fp0_regnum (gdbarch
) + 10),
2007 (long) get_frame_register_unsigned
2008 (frame
, gdbarch_fp0_regnum (gdbarch
) + 11),
2009 (long) get_frame_register_unsigned
2010 (frame
, gdbarch_fp0_regnum (gdbarch
) + 12),
2011 (long) get_frame_register_unsigned
2012 (frame
, gdbarch_fp0_regnum (gdbarch
) + 13),
2013 (long) get_frame_register_unsigned
2014 (frame
, gdbarch_fp0_regnum (gdbarch
) + 14),
2015 (long) get_frame_register_unsigned
2016 (frame
, gdbarch_fp0_regnum (gdbarch
) + 15));
2020 sh4_nofpu_show_regs (struct frame_info
*frame
)
2023 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
2024 paddr (get_frame_register_unsigned (frame
,
2026 (get_frame_arch (frame
)))),
2027 (long) get_frame_register_unsigned (frame
, SR_REGNUM
),
2028 (long) get_frame_register_unsigned (frame
, PR_REGNUM
),
2029 (long) get_frame_register_unsigned (frame
, MACH_REGNUM
));
2032 (" GBR %08lx VBR %08lx MACL %08lx\n",
2033 (long) get_frame_register_unsigned (frame
, GBR_REGNUM
),
2034 (long) get_frame_register_unsigned (frame
, VBR_REGNUM
),
2035 (long) get_frame_register_unsigned (frame
, MACL_REGNUM
));
2037 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
2038 (long) get_frame_register_unsigned (frame
, SSR_REGNUM
),
2039 (long) get_frame_register_unsigned (frame
, SPC_REGNUM
),
2040 (long) get_frame_register_unsigned (frame
, FPUL_REGNUM
),
2041 (long) get_frame_register_unsigned (frame
, FPSCR_REGNUM
));
2044 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2045 (long) get_frame_register_unsigned (frame
, 0),
2046 (long) get_frame_register_unsigned (frame
, 1),
2047 (long) get_frame_register_unsigned (frame
, 2),
2048 (long) get_frame_register_unsigned (frame
, 3),
2049 (long) get_frame_register_unsigned (frame
, 4),
2050 (long) get_frame_register_unsigned (frame
, 5),
2051 (long) get_frame_register_unsigned (frame
, 6),
2052 (long) get_frame_register_unsigned (frame
, 7));
2054 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2055 (long) get_frame_register_unsigned (frame
, 8),
2056 (long) get_frame_register_unsigned (frame
, 9),
2057 (long) get_frame_register_unsigned (frame
, 10),
2058 (long) get_frame_register_unsigned (frame
, 11),
2059 (long) get_frame_register_unsigned (frame
, 12),
2060 (long) get_frame_register_unsigned (frame
, 13),
2061 (long) get_frame_register_unsigned (frame
, 14),
2062 (long) get_frame_register_unsigned (frame
, 15));
2066 sh_dsp_show_regs (struct frame_info
*frame
)
2069 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
2070 paddr (get_frame_register_unsigned (frame
,
2072 (get_frame_arch (frame
)))),
2073 (long) get_frame_register_unsigned (frame
, SR_REGNUM
),
2074 (long) get_frame_register_unsigned (frame
, PR_REGNUM
),
2075 (long) get_frame_register_unsigned (frame
, MACH_REGNUM
));
2078 (" GBR %08lx VBR %08lx DSR %08lx MACL %08lx\n",
2079 (long) get_frame_register_unsigned (frame
, GBR_REGNUM
),
2080 (long) get_frame_register_unsigned (frame
, VBR_REGNUM
),
2081 (long) get_frame_register_unsigned (frame
, DSR_REGNUM
),
2082 (long) get_frame_register_unsigned (frame
, MACL_REGNUM
));
2085 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2086 (long) get_frame_register_unsigned (frame
, 0),
2087 (long) get_frame_register_unsigned (frame
, 1),
2088 (long) get_frame_register_unsigned (frame
, 2),
2089 (long) get_frame_register_unsigned (frame
, 3),
2090 (long) get_frame_register_unsigned (frame
, 4),
2091 (long) get_frame_register_unsigned (frame
, 5),
2092 (long) get_frame_register_unsigned (frame
, 6),
2093 (long) get_frame_register_unsigned (frame
, 7));
2095 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2096 (long) get_frame_register_unsigned (frame
, 8),
2097 (long) get_frame_register_unsigned (frame
, 9),
2098 (long) get_frame_register_unsigned (frame
, 10),
2099 (long) get_frame_register_unsigned (frame
, 11),
2100 (long) get_frame_register_unsigned (frame
, 12),
2101 (long) get_frame_register_unsigned (frame
, 13),
2102 (long) get_frame_register_unsigned (frame
, 14),
2103 (long) get_frame_register_unsigned (frame
, 15));
2106 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
2107 (long) get_frame_register_unsigned (frame
, A0G_REGNUM
) & 0xff,
2108 (long) get_frame_register_unsigned (frame
, A0_REGNUM
),
2109 (long) get_frame_register_unsigned (frame
, M0_REGNUM
),
2110 (long) get_frame_register_unsigned (frame
, X0_REGNUM
),
2111 (long) get_frame_register_unsigned (frame
, Y0_REGNUM
),
2112 (long) get_frame_register_unsigned (frame
, RS_REGNUM
),
2113 (long) get_frame_register_unsigned (frame
, MOD_REGNUM
));
2114 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
2115 (long) get_frame_register_unsigned (frame
, A1G_REGNUM
) & 0xff,
2116 (long) get_frame_register_unsigned (frame
, A1_REGNUM
),
2117 (long) get_frame_register_unsigned (frame
, M1_REGNUM
),
2118 (long) get_frame_register_unsigned (frame
, X1_REGNUM
),
2119 (long) get_frame_register_unsigned (frame
, Y1_REGNUM
),
2120 (long) get_frame_register_unsigned (frame
, RE_REGNUM
));
2124 sh_show_regs_command (char *args
, int from_tty
)
2127 (*sh_show_regs
) (get_current_frame ());
2130 static struct type
*
2131 sh_sh2a_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
2133 if ((reg_nr
>= gdbarch_fp0_regnum (gdbarch
)
2134 && (reg_nr
<= FP_LAST_REGNUM
)) || (reg_nr
== FPUL_REGNUM
))
2135 return builtin_type_float
;
2136 else if (reg_nr
>= DR0_REGNUM
&& reg_nr
<= DR_LAST_REGNUM
)
2137 return builtin_type_double
;
2139 return builtin_type_int
;
2142 /* Return the GDB type object for the "standard" data type
2143 of data in register N. */
2144 static struct type
*
2145 sh_sh3e_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
2147 if ((reg_nr
>= gdbarch_fp0_regnum (gdbarch
)
2148 && (reg_nr
<= FP_LAST_REGNUM
)) || (reg_nr
== FPUL_REGNUM
))
2149 return builtin_type_float
;
2151 return builtin_type_int
;
2154 static struct type
*
2155 sh_sh4_build_float_register_type (int high
)
2159 temp
= create_range_type (NULL
, builtin_type_int
, 0, high
);
2160 return create_array_type (NULL
, builtin_type_float
, temp
);
2163 static struct type
*
2164 sh_sh4_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
2166 if ((reg_nr
>= gdbarch_fp0_regnum (gdbarch
)
2167 && (reg_nr
<= FP_LAST_REGNUM
)) || (reg_nr
== FPUL_REGNUM
))
2168 return builtin_type_float
;
2169 else if (reg_nr
>= DR0_REGNUM
&& reg_nr
<= DR_LAST_REGNUM
)
2170 return builtin_type_double
;
2171 else if (reg_nr
>= FV0_REGNUM
&& reg_nr
<= FV_LAST_REGNUM
)
2172 return sh_sh4_build_float_register_type (3);
2174 return builtin_type_int
;
2177 static struct type
*
2178 sh_default_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
2180 return builtin_type_int
;
2183 /* Is a register in a reggroup?
2184 The default code in reggroup.c doesn't identify system registers, some
2185 float registers or any of the vector registers.
2186 TODO: sh2a and dsp registers. */
2188 sh_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2189 struct reggroup
*reggroup
)
2191 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
2192 || *gdbarch_register_name (gdbarch
, regnum
) == '\0')
2195 if (reggroup
== float_reggroup
2196 && (regnum
== FPUL_REGNUM
2197 || regnum
== FPSCR_REGNUM
))
2200 if (regnum
>= FV0_REGNUM
&& regnum
<= FV_LAST_REGNUM
)
2202 if (reggroup
== vector_reggroup
|| reggroup
== float_reggroup
)
2204 if (reggroup
== general_reggroup
)
2208 if (regnum
== VBR_REGNUM
2209 || regnum
== SR_REGNUM
2210 || regnum
== FPSCR_REGNUM
2211 || regnum
== SSR_REGNUM
2212 || regnum
== SPC_REGNUM
)
2214 if (reggroup
== system_reggroup
)
2216 if (reggroup
== general_reggroup
)
2220 /* The default code can cope with any other registers. */
2221 return default_register_reggroup_p (gdbarch
, regnum
, reggroup
);
2224 /* On the sh4, the DRi pseudo registers are problematic if the target
2225 is little endian. When the user writes one of those registers, for
2226 instance with 'ser var $dr0=1', we want the double to be stored
2228 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
2229 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2231 This corresponds to little endian byte order & big endian word
2232 order. However if we let gdb write the register w/o conversion, it
2233 will write fr0 and fr1 this way:
2234 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2235 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
2236 because it will consider fr0 and fr1 as a single LE stretch of memory.
2238 To achieve what we want we must force gdb to store things in
2239 floatformat_ieee_double_littlebyte_bigword (which is defined in
2240 include/floatformat.h and libiberty/floatformat.c.
2242 In case the target is big endian, there is no problem, the
2243 raw bytes will look like:
2244 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
2245 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2247 The other pseudo registers (the FVs) also don't pose a problem
2248 because they are stored as 4 individual FP elements. */
2251 sh_register_convert_to_virtual (int regnum
, struct type
*type
,
2252 char *from
, char *to
)
2254 if (regnum
>= DR0_REGNUM
&& regnum
<= DR_LAST_REGNUM
)
2257 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword
,
2259 store_typed_floating (to
, type
, val
);
2263 ("sh_register_convert_to_virtual called with non DR register number");
2267 sh_register_convert_to_raw (struct type
*type
, int regnum
,
2268 const void *from
, void *to
)
2270 if (regnum
>= DR0_REGNUM
&& regnum
<= DR_LAST_REGNUM
)
2272 DOUBLEST val
= extract_typed_floating (from
, type
);
2273 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword
,
2277 error (_("sh_register_convert_to_raw called with non DR register number"));
2280 /* For vectors of 4 floating point registers. */
2282 fv_reg_base_num (struct gdbarch
*gdbarch
, int fv_regnum
)
2286 fp_regnum
= gdbarch_fp0_regnum (gdbarch
)
2287 + (fv_regnum
- FV0_REGNUM
) * 4;
2291 /* For double precision floating point registers, i.e 2 fp regs.*/
2293 dr_reg_base_num (struct gdbarch
*gdbarch
, int dr_regnum
)
2297 fp_regnum
= gdbarch_fp0_regnum (gdbarch
)
2298 + (dr_regnum
- DR0_REGNUM
) * 2;
2303 sh_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2304 int reg_nr
, gdb_byte
*buffer
)
2306 int base_regnum
, portion
;
2307 char temp_buffer
[MAX_REGISTER_SIZE
];
2309 if (reg_nr
== PSEUDO_BANK_REGNUM
)
2310 regcache_raw_read (regcache
, BANK_REGNUM
, buffer
);
2312 if (reg_nr
>= DR0_REGNUM
&& reg_nr
<= DR_LAST_REGNUM
)
2314 base_regnum
= dr_reg_base_num (gdbarch
, reg_nr
);
2316 /* Build the value in the provided buffer. */
2317 /* Read the real regs for which this one is an alias. */
2318 for (portion
= 0; portion
< 2; portion
++)
2319 regcache_raw_read (regcache
, base_regnum
+ portion
,
2321 + register_size (gdbarch
,
2322 base_regnum
) * portion
));
2323 /* We must pay attention to the endiannes. */
2324 sh_register_convert_to_virtual (reg_nr
,
2325 register_type (gdbarch
, reg_nr
),
2326 temp_buffer
, buffer
);
2328 else if (reg_nr
>= FV0_REGNUM
&& reg_nr
<= FV_LAST_REGNUM
)
2330 base_regnum
= fv_reg_base_num (gdbarch
, reg_nr
);
2332 /* Read the real regs for which this one is an alias. */
2333 for (portion
= 0; portion
< 4; portion
++)
2334 regcache_raw_read (regcache
, base_regnum
+ portion
,
2336 + register_size (gdbarch
,
2337 base_regnum
) * portion
));
2342 sh_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2343 int reg_nr
, const gdb_byte
*buffer
)
2345 int base_regnum
, portion
;
2346 char temp_buffer
[MAX_REGISTER_SIZE
];
2348 if (reg_nr
== PSEUDO_BANK_REGNUM
)
2350 /* When the bank register is written to, the whole register bank
2351 is switched and all values in the bank registers must be read
2352 from the target/sim again. We're just invalidating the regcache
2353 so that a re-read happens next time it's necessary. */
2356 regcache_raw_write (regcache
, BANK_REGNUM
, buffer
);
2357 for (bregnum
= R0_BANK0_REGNUM
; bregnum
< MACLB_REGNUM
; ++bregnum
)
2358 regcache_invalidate (regcache
, bregnum
);
2360 else if (reg_nr
>= DR0_REGNUM
&& reg_nr
<= DR_LAST_REGNUM
)
2362 base_regnum
= dr_reg_base_num (gdbarch
, reg_nr
);
2364 /* We must pay attention to the endiannes. */
2365 sh_register_convert_to_raw (register_type (gdbarch
, reg_nr
),
2366 reg_nr
, buffer
, temp_buffer
);
2368 /* Write the real regs for which this one is an alias. */
2369 for (portion
= 0; portion
< 2; portion
++)
2370 regcache_raw_write (regcache
, base_regnum
+ portion
,
2372 + register_size (gdbarch
,
2373 base_regnum
) * portion
));
2375 else if (reg_nr
>= FV0_REGNUM
&& reg_nr
<= FV_LAST_REGNUM
)
2377 base_regnum
= fv_reg_base_num (gdbarch
, reg_nr
);
2379 /* Write the real regs for which this one is an alias. */
2380 for (portion
= 0; portion
< 4; portion
++)
2381 regcache_raw_write (regcache
, base_regnum
+ portion
,
2383 + register_size (gdbarch
,
2384 base_regnum
) * portion
));
2389 sh_dsp_register_sim_regno (struct gdbarch
*gdbarch
, int nr
)
2391 if (legacy_register_sim_regno (gdbarch
, nr
) < 0)
2392 return legacy_register_sim_regno (gdbarch
, nr
);
2393 if (nr
>= DSR_REGNUM
&& nr
<= Y1_REGNUM
)
2394 return nr
- DSR_REGNUM
+ SIM_SH_DSR_REGNUM
;
2395 if (nr
== MOD_REGNUM
)
2396 return SIM_SH_MOD_REGNUM
;
2397 if (nr
== RS_REGNUM
)
2398 return SIM_SH_RS_REGNUM
;
2399 if (nr
== RE_REGNUM
)
2400 return SIM_SH_RE_REGNUM
;
2401 if (nr
>= DSP_R0_BANK_REGNUM
&& nr
<= DSP_R7_BANK_REGNUM
)
2402 return nr
- DSP_R0_BANK_REGNUM
+ SIM_SH_R0_BANK_REGNUM
;
2407 sh_sh2a_register_sim_regno (struct gdbarch
*gdbarch
, int nr
)
2412 return SIM_SH_TBR_REGNUM
;
2414 return SIM_SH_IBNR_REGNUM
;
2416 return SIM_SH_IBCR_REGNUM
;
2418 return SIM_SH_BANK_REGNUM
;
2420 return SIM_SH_BANK_MACL_REGNUM
;
2422 return SIM_SH_BANK_GBR_REGNUM
;
2424 return SIM_SH_BANK_PR_REGNUM
;
2426 return SIM_SH_BANK_IVN_REGNUM
;
2428 return SIM_SH_BANK_MACH_REGNUM
;
2432 return legacy_register_sim_regno (gdbarch
, nr
);
2435 /* Set up the register unwinding such that call-clobbered registers are
2436 not displayed in frames >0 because the true value is not certain.
2437 The 'undefined' registers will show up as 'not available' unless the
2440 This function is currently set up for SH4 and compatible only. */
2443 sh_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
2444 struct dwarf2_frame_state_reg
*reg
,
2445 struct frame_info
*this_frame
)
2447 /* Mark the PC as the destination for the return address. */
2448 if (regnum
== gdbarch_pc_regnum (gdbarch
))
2449 reg
->how
= DWARF2_FRAME_REG_RA
;
2451 /* Mark the stack pointer as the call frame address. */
2452 else if (regnum
== gdbarch_sp_regnum (gdbarch
))
2453 reg
->how
= DWARF2_FRAME_REG_CFA
;
2455 /* The above was taken from the default init_reg in dwarf2-frame.c
2456 while the below is SH specific. */
2458 /* Caller save registers. */
2459 else if ((regnum
>= R0_REGNUM
&& regnum
<= R0_REGNUM
+7)
2460 || (regnum
>= FR0_REGNUM
&& regnum
<= FR0_REGNUM
+11)
2461 || (regnum
>= DR0_REGNUM
&& regnum
<= DR0_REGNUM
+5)
2462 || (regnum
>= FV0_REGNUM
&& regnum
<= FV0_REGNUM
+2)
2463 || (regnum
== MACH_REGNUM
)
2464 || (regnum
== MACL_REGNUM
)
2465 || (regnum
== FPUL_REGNUM
)
2466 || (regnum
== SR_REGNUM
))
2467 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
2469 /* Callee save registers. */
2470 else if ((regnum
>= R0_REGNUM
+8 && regnum
<= R0_REGNUM
+15)
2471 || (regnum
>= FR0_REGNUM
+12 && regnum
<= FR0_REGNUM
+15)
2472 || (regnum
>= DR0_REGNUM
+6 && regnum
<= DR0_REGNUM
+8)
2473 || (regnum
== FV0_REGNUM
+3))
2474 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
2476 /* Other registers. These are not in the ABI and may or may not
2477 mean anything in frames >0 so don't show them. */
2478 else if ((regnum
>= R0_BANK0_REGNUM
&& regnum
<= R0_BANK0_REGNUM
+15)
2479 || (regnum
== GBR_REGNUM
)
2480 || (regnum
== VBR_REGNUM
)
2481 || (regnum
== FPSCR_REGNUM
)
2482 || (regnum
== SSR_REGNUM
)
2483 || (regnum
== SPC_REGNUM
))
2484 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
2487 static struct sh_frame_cache
*
2488 sh_alloc_frame_cache (void)
2490 struct sh_frame_cache
*cache
;
2493 cache
= FRAME_OBSTACK_ZALLOC (struct sh_frame_cache
);
2497 cache
->saved_sp
= 0;
2498 cache
->sp_offset
= 0;
2501 /* Frameless until proven otherwise. */
2504 /* Saved registers. We initialize these to -1 since zero is a valid
2505 offset (that's where fp is supposed to be stored). */
2506 for (i
= 0; i
< SH_NUM_REGS
; i
++)
2508 cache
->saved_regs
[i
] = -1;
2514 static struct sh_frame_cache
*
2515 sh_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2517 struct sh_frame_cache
*cache
;
2518 CORE_ADDR current_pc
;
2524 cache
= sh_alloc_frame_cache ();
2525 *this_cache
= cache
;
2527 /* In principle, for normal frames, fp holds the frame pointer,
2528 which holds the base address for the current stack frame.
2529 However, for functions that don't need it, the frame pointer is
2530 optional. For these "frameless" functions the frame pointer is
2531 actually the frame pointer of the calling frame. */
2532 cache
->base
= get_frame_register_unsigned (this_frame
, FP_REGNUM
);
2533 if (cache
->base
== 0)
2536 cache
->pc
= get_frame_func (this_frame
);
2537 current_pc
= get_frame_pc (this_frame
);
2541 fpscr
= get_frame_register_unsigned (this_frame
, FPSCR_REGNUM
);
2542 sh_analyze_prologue (cache
->pc
, current_pc
, cache
, fpscr
);
2545 if (!cache
->uses_fp
)
2547 /* We didn't find a valid frame, which means that CACHE->base
2548 currently holds the frame pointer for our calling frame. If
2549 we're at the start of a function, or somewhere half-way its
2550 prologue, the function's frame probably hasn't been fully
2551 setup yet. Try to reconstruct the base address for the stack
2552 frame by looking at the stack pointer. For truly "frameless"
2553 functions this might work too. */
2554 cache
->base
= get_frame_register_unsigned
2556 gdbarch_sp_regnum (get_frame_arch (this_frame
)));
2559 /* Now that we have the base address for the stack frame we can
2560 calculate the value of sp in the calling frame. */
2561 cache
->saved_sp
= cache
->base
+ cache
->sp_offset
;
2563 /* Adjust all the saved registers such that they contain addresses
2564 instead of offsets. */
2565 for (i
= 0; i
< SH_NUM_REGS
; i
++)
2566 if (cache
->saved_regs
[i
] != -1)
2567 cache
->saved_regs
[i
] = cache
->saved_sp
- cache
->saved_regs
[i
] - 4;
2572 static struct value
*
2573 sh_frame_prev_register (struct frame_info
*this_frame
,
2574 void **this_cache
, int regnum
)
2576 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2577 struct sh_frame_cache
*cache
= sh_frame_cache (this_frame
, this_cache
);
2579 gdb_assert (regnum
>= 0);
2581 if (regnum
== gdbarch_sp_regnum (gdbarch
) && cache
->saved_sp
)
2582 return frame_unwind_got_constant (this_frame
, regnum
, cache
->saved_sp
);
2584 /* The PC of the previous frame is stored in the PR register of
2585 the current frame. Frob regnum so that we pull the value from
2586 the correct place. */
2587 if (regnum
== gdbarch_pc_regnum (gdbarch
))
2590 if (regnum
< SH_NUM_REGS
&& cache
->saved_regs
[regnum
] != -1)
2591 return frame_unwind_got_memory (this_frame
, regnum
,
2592 cache
->saved_regs
[regnum
]);
2594 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
2598 sh_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2599 struct frame_id
*this_id
)
2601 struct sh_frame_cache
*cache
= sh_frame_cache (this_frame
, this_cache
);
2603 /* This marks the outermost frame. */
2604 if (cache
->base
== 0)
2607 *this_id
= frame_id_build (cache
->saved_sp
, cache
->pc
);
2610 static const struct frame_unwind sh_frame_unwind
= {
2613 sh_frame_prev_register
,
2615 default_frame_sniffer
2619 sh_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2621 return frame_unwind_register_unsigned (next_frame
,
2622 gdbarch_sp_regnum (gdbarch
));
2626 sh_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2628 return frame_unwind_register_unsigned (next_frame
,
2629 gdbarch_pc_regnum (gdbarch
));
2632 static struct frame_id
2633 sh_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2635 CORE_ADDR sp
= get_frame_register_unsigned (this_frame
,
2636 gdbarch_sp_regnum (gdbarch
));
2637 return frame_id_build (sp
, get_frame_pc (this_frame
));
2641 sh_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2643 struct sh_frame_cache
*cache
= sh_frame_cache (this_frame
, this_cache
);
2648 static const struct frame_base sh_frame_base
= {
2650 sh_frame_base_address
,
2651 sh_frame_base_address
,
2652 sh_frame_base_address
2655 /* The epilogue is defined here as the area at the end of a function,
2656 either on the `ret' instruction itself or after an instruction which
2657 destroys the function's stack frame. */
2659 sh_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2661 CORE_ADDR func_addr
= 0, func_end
= 0;
2663 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
2666 /* The sh epilogue is max. 14 bytes long. Give another 14 bytes
2667 for a nop and some fixed data (e.g. big offsets) which are
2668 unfortunately also treated as part of the function (which
2669 means, they are below func_end. */
2670 CORE_ADDR addr
= func_end
- 28;
2671 if (addr
< func_addr
+ 4)
2672 addr
= func_addr
+ 4;
2676 /* First search forward until hitting an rts. */
2677 while (addr
< func_end
2678 && !IS_RTS (read_memory_unsigned_integer (addr
, 2)))
2680 if (addr
>= func_end
)
2683 /* At this point we should find a mov.l @r15+,r14 instruction,
2684 either before or after the rts. If not, then the function has
2685 probably no "normal" epilogue and we bail out here. */
2686 inst
= read_memory_unsigned_integer (addr
- 2, 2);
2687 if (IS_RESTORE_FP (read_memory_unsigned_integer (addr
- 2, 2)))
2689 else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr
+ 2, 2)))
2692 inst
= read_memory_unsigned_integer (addr
- 2, 2);
2694 /* Step over possible lds.l @r15+,macl. */
2695 if (IS_MACL_LDS (inst
))
2698 inst
= read_memory_unsigned_integer (addr
- 2, 2);
2701 /* Step over possible lds.l @r15+,pr. */
2705 inst
= read_memory_unsigned_integer (addr
- 2, 2);
2708 /* Step over possible mov r14,r15. */
2709 if (IS_MOV_FP_SP (inst
))
2712 inst
= read_memory_unsigned_integer (addr
- 2, 2);
2715 /* Now check for FP adjustments, using add #imm,r14 or add rX, r14
2717 while (addr
> func_addr
+ 4
2718 && (IS_ADD_REG_TO_FP (inst
) || IS_ADD_IMM_FP (inst
)))
2721 inst
= read_memory_unsigned_integer (addr
- 2, 2);
2724 /* On SH2a check if the previous instruction was perhaps a MOVI20.
2725 That's allowed for the epilogue. */
2726 if ((gdbarch_bfd_arch_info (gdbarch
)->mach
== bfd_mach_sh2a
2727 || gdbarch_bfd_arch_info (gdbarch
)->mach
== bfd_mach_sh2a_nofpu
)
2728 && addr
> func_addr
+ 6
2729 && IS_MOVI20 (read_memory_unsigned_integer (addr
- 4, 2)))
2739 static struct gdbarch
*
2740 sh_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2742 struct gdbarch
*gdbarch
;
2744 sh_show_regs
= sh_generic_show_regs
;
2745 switch (info
.bfd_arch_info
->mach
)
2748 sh_show_regs
= sh2e_show_regs
;
2751 sh_show_regs
= sh2a_show_regs
;
2753 case bfd_mach_sh2a_nofpu
:
2754 sh_show_regs
= sh2a_nofpu_show_regs
;
2756 case bfd_mach_sh_dsp
:
2757 sh_show_regs
= sh_dsp_show_regs
;
2761 sh_show_regs
= sh3_show_regs
;
2765 sh_show_regs
= sh3e_show_regs
;
2768 case bfd_mach_sh3_dsp
:
2769 case bfd_mach_sh4al_dsp
:
2770 sh_show_regs
= sh3_dsp_show_regs
;
2775 sh_show_regs
= sh4_show_regs
;
2778 case bfd_mach_sh4_nofpu
:
2779 case bfd_mach_sh4a_nofpu
:
2780 sh_show_regs
= sh4_nofpu_show_regs
;
2784 sh_show_regs
= sh64_show_regs
;
2785 /* SH5 is handled entirely in sh64-tdep.c */
2786 return sh64_gdbarch_init (info
, arches
);
2789 /* If there is already a candidate, use it. */
2790 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2792 return arches
->gdbarch
;
2794 /* None found, create a new architecture from the information
2796 gdbarch
= gdbarch_alloc (&info
, NULL
);
2798 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
2799 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2800 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2801 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2802 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2803 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2804 set_gdbarch_long_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2805 set_gdbarch_ptr_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2807 set_gdbarch_num_regs (gdbarch
, SH_NUM_REGS
);
2808 set_gdbarch_sp_regnum (gdbarch
, 15);
2809 set_gdbarch_pc_regnum (gdbarch
, 16);
2810 set_gdbarch_fp0_regnum (gdbarch
, -1);
2811 set_gdbarch_num_pseudo_regs (gdbarch
, 0);
2813 set_gdbarch_register_type (gdbarch
, sh_default_register_type
);
2814 set_gdbarch_register_reggroup_p (gdbarch
, sh_register_reggroup_p
);
2816 set_gdbarch_breakpoint_from_pc (gdbarch
, sh_breakpoint_from_pc
);
2818 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_sh
);
2819 set_gdbarch_register_sim_regno (gdbarch
, legacy_register_sim_regno
);
2821 set_gdbarch_return_value (gdbarch
, sh_return_value_nofpu
);
2823 set_gdbarch_skip_prologue (gdbarch
, sh_skip_prologue
);
2824 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2826 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_nofpu
);
2828 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
2830 set_gdbarch_frame_align (gdbarch
, sh_frame_align
);
2831 set_gdbarch_unwind_sp (gdbarch
, sh_unwind_sp
);
2832 set_gdbarch_unwind_pc (gdbarch
, sh_unwind_pc
);
2833 set_gdbarch_dummy_id (gdbarch
, sh_dummy_id
);
2834 frame_base_set_default (gdbarch
, &sh_frame_base
);
2836 set_gdbarch_in_function_epilogue_p (gdbarch
, sh_in_function_epilogue_p
);
2838 dwarf2_frame_set_init_reg (gdbarch
, sh_dwarf2_frame_init_reg
);
2840 switch (info
.bfd_arch_info
->mach
)
2843 set_gdbarch_register_name (gdbarch
, sh_sh_register_name
);
2847 set_gdbarch_register_name (gdbarch
, sh_sh_register_name
);
2851 /* doubles on sh2e and sh3e are actually 4 byte. */
2852 set_gdbarch_double_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2854 set_gdbarch_register_name (gdbarch
, sh_sh2e_register_name
);
2855 set_gdbarch_register_type (gdbarch
, sh_sh3e_register_type
);
2856 set_gdbarch_fp0_regnum (gdbarch
, 25);
2857 set_gdbarch_return_value (gdbarch
, sh_return_value_fpu
);
2858 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_fpu
);
2862 set_gdbarch_register_name (gdbarch
, sh_sh2a_register_name
);
2863 set_gdbarch_register_type (gdbarch
, sh_sh2a_register_type
);
2864 set_gdbarch_register_sim_regno (gdbarch
, sh_sh2a_register_sim_regno
);
2866 set_gdbarch_fp0_regnum (gdbarch
, 25);
2867 set_gdbarch_num_pseudo_regs (gdbarch
, 9);
2868 set_gdbarch_pseudo_register_read (gdbarch
, sh_pseudo_register_read
);
2869 set_gdbarch_pseudo_register_write (gdbarch
, sh_pseudo_register_write
);
2870 set_gdbarch_return_value (gdbarch
, sh_return_value_fpu
);
2871 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_fpu
);
2874 case bfd_mach_sh2a_nofpu
:
2875 set_gdbarch_register_name (gdbarch
, sh_sh2a_nofpu_register_name
);
2876 set_gdbarch_register_sim_regno (gdbarch
, sh_sh2a_register_sim_regno
);
2878 set_gdbarch_num_pseudo_regs (gdbarch
, 1);
2879 set_gdbarch_pseudo_register_read (gdbarch
, sh_pseudo_register_read
);
2880 set_gdbarch_pseudo_register_write (gdbarch
, sh_pseudo_register_write
);
2883 case bfd_mach_sh_dsp
:
2884 set_gdbarch_register_name (gdbarch
, sh_sh_dsp_register_name
);
2885 set_gdbarch_register_sim_regno (gdbarch
, sh_dsp_register_sim_regno
);
2889 case bfd_mach_sh3_nommu
:
2890 case bfd_mach_sh2a_nofpu_or_sh3_nommu
:
2891 set_gdbarch_register_name (gdbarch
, sh_sh3_register_name
);
2895 case bfd_mach_sh2a_or_sh3e
:
2896 /* doubles on sh2e and sh3e are actually 4 byte. */
2897 set_gdbarch_double_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2899 set_gdbarch_register_name (gdbarch
, sh_sh3e_register_name
);
2900 set_gdbarch_register_type (gdbarch
, sh_sh3e_register_type
);
2901 set_gdbarch_fp0_regnum (gdbarch
, 25);
2902 set_gdbarch_return_value (gdbarch
, sh_return_value_fpu
);
2903 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_fpu
);
2906 case bfd_mach_sh3_dsp
:
2907 set_gdbarch_register_name (gdbarch
, sh_sh3_dsp_register_name
);
2908 set_gdbarch_register_sim_regno (gdbarch
, sh_dsp_register_sim_regno
);
2913 set_gdbarch_register_name (gdbarch
, sh_sh4_register_name
);
2914 set_gdbarch_register_type (gdbarch
, sh_sh4_register_type
);
2915 set_gdbarch_fp0_regnum (gdbarch
, 25);
2916 set_gdbarch_num_pseudo_regs (gdbarch
, 13);
2917 set_gdbarch_pseudo_register_read (gdbarch
, sh_pseudo_register_read
);
2918 set_gdbarch_pseudo_register_write (gdbarch
, sh_pseudo_register_write
);
2919 set_gdbarch_return_value (gdbarch
, sh_return_value_fpu
);
2920 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_fpu
);
2923 case bfd_mach_sh4_nofpu
:
2924 case bfd_mach_sh4a_nofpu
:
2925 case bfd_mach_sh4_nommu_nofpu
:
2926 case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu
:
2927 case bfd_mach_sh2a_or_sh4
:
2928 set_gdbarch_register_name (gdbarch
, sh_sh4_nofpu_register_name
);
2931 case bfd_mach_sh4al_dsp
:
2932 set_gdbarch_register_name (gdbarch
, sh_sh4al_dsp_register_name
);
2933 set_gdbarch_register_sim_regno (gdbarch
, sh_dsp_register_sim_regno
);
2937 set_gdbarch_register_name (gdbarch
, sh_sh_register_name
);
2941 /* Hook in ABI-specific overrides, if they have been registered. */
2942 gdbarch_init_osabi (info
, gdbarch
);
2944 dwarf2_append_unwinders (gdbarch
);
2945 frame_unwind_append_unwinder (gdbarch
, &sh_frame_unwind
);
2951 show_sh_command (char *args
, int from_tty
)
2953 help_list (showshcmdlist
, "show sh ", all_commands
, gdb_stdout
);
2957 set_sh_command (char *args
, int from_tty
)
2960 ("\"set sh\" must be followed by an appropriate subcommand.\n");
2961 help_list (setshcmdlist
, "set sh ", all_commands
, gdb_stdout
);
2964 extern initialize_file_ftype _initialize_sh_tdep
; /* -Wmissing-prototypes */
2967 _initialize_sh_tdep (void)
2969 struct cmd_list_element
*c
;
2971 gdbarch_register (bfd_arch_sh
, sh_gdbarch_init
, NULL
);
2973 add_com ("regs", class_vars
, sh_show_regs_command
, _("Print all registers"));
2975 add_prefix_cmd ("sh", no_class
, set_sh_command
, "SH specific commands.",
2976 &setshcmdlist
, "set sh ", 0, &setlist
);
2977 add_prefix_cmd ("sh", no_class
, show_sh_command
, "SH specific commands.",
2978 &showshcmdlist
, "show sh ", 0, &showlist
);
2980 add_setshow_enum_cmd ("calling-convention", class_vars
, sh_cc_enum
,
2981 &sh_active_calling_convention
,
2982 _("Set calling convention used when calling target "
2983 "functions from GDB."),
2984 _("Show calling convention used when calling target "
2985 "functions from GDB."),
2986 _("gcc - Use GCC calling convention (default).\n"
2987 "renesas - Enforce Renesas calling convention."),
2989 &setshcmdlist
, &showshcmdlist
);