1 /* Target-dependent code for Renesas Super-H, for GDB.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 Contributed by Steve Chamberlain
29 #include "frame-base.h"
30 #include "frame-unwind.h"
31 #include "dwarf2-frame.h"
40 #include "gdb_string.h"
41 #include "gdb_assert.h"
42 #include "arch-utils.h"
43 #include "floatformat.h"
51 #include "solib-svr4.h"
55 /* registers numbers shared with the simulator */
56 #include "gdb/sim-sh.h"
58 static void (*sh_show_regs
) (void);
60 #define SH_NUM_REGS 59
69 /* Flag showing that a frame has been created in the prologue code. */
72 /* Saved registers. */
73 CORE_ADDR saved_regs
[SH_NUM_REGS
];
78 sh_generic_register_name (int reg_nr
)
80 static char *register_names
[] = {
81 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
82 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
83 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
85 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
86 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
88 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
89 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
93 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
95 return register_names
[reg_nr
];
99 sh_sh_register_name (int reg_nr
)
101 static char *register_names
[] = {
102 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
103 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
104 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
106 "", "", "", "", "", "", "", "",
107 "", "", "", "", "", "", "", "",
109 "", "", "", "", "", "", "", "",
110 "", "", "", "", "", "", "", "",
114 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
116 return register_names
[reg_nr
];
120 sh_sh3_register_name (int reg_nr
)
122 static char *register_names
[] = {
123 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
124 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
125 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
127 "", "", "", "", "", "", "", "",
128 "", "", "", "", "", "", "", "",
130 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
131 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
135 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
137 return register_names
[reg_nr
];
141 sh_sh3e_register_name (int reg_nr
)
143 static char *register_names
[] = {
144 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
145 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
146 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
148 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
149 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
151 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
152 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
156 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
158 return register_names
[reg_nr
];
162 sh_sh2e_register_name (int reg_nr
)
164 static char *register_names
[] = {
165 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
166 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
167 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
169 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
170 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
172 "", "", "", "", "", "", "", "",
173 "", "", "", "", "", "", "", "",
177 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
179 return register_names
[reg_nr
];
183 sh_sh_dsp_register_name (int reg_nr
)
185 static char *register_names
[] = {
186 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
187 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
188 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
190 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
191 "y0", "y1", "", "", "", "", "", "mod",
193 "rs", "re", "", "", "", "", "", "",
194 "", "", "", "", "", "", "", "",
198 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
200 return register_names
[reg_nr
];
204 sh_sh3_dsp_register_name (int reg_nr
)
206 static char *register_names
[] = {
207 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
208 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
209 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
211 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
212 "y0", "y1", "", "", "", "", "", "mod",
214 "rs", "re", "", "", "", "", "", "",
215 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b"
216 "", "", "", "", "", "", "", "",
220 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
222 return register_names
[reg_nr
];
226 sh_sh4_register_name (int reg_nr
)
228 static char *register_names
[] = {
229 /* general registers 0-15 */
230 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
231 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
233 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
236 /* floating point registers 25 - 40 */
237 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
238 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
242 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
244 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
245 /* double precision (pseudo) 59 - 66 */
246 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
247 /* vectors (pseudo) 67 - 70 */
248 "fv0", "fv4", "fv8", "fv12",
249 /* FIXME: missing XF 71 - 86 */
250 /* FIXME: missing XD 87 - 94 */
254 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
256 return register_names
[reg_nr
];
260 sh_sh4_nofpu_register_name (int reg_nr
)
262 static char *register_names
[] = {
263 /* general registers 0-15 */
264 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
265 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
267 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
270 /* floating point registers 25 - 40 -- not for nofpu target */
271 "", "", "", "", "", "", "", "",
272 "", "", "", "", "", "", "", "",
276 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
278 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
279 /* double precision (pseudo) 59 - 66 -- not for nofpu target */
280 "", "", "", "", "", "", "", "",
281 /* vectors (pseudo) 67 - 70 -- not for nofpu target */
286 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
288 return register_names
[reg_nr
];
292 sh_sh4al_dsp_register_name (int reg_nr
)
294 static char *register_names
[] = {
295 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
296 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
297 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
299 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
300 "y0", "y1", "", "", "", "", "", "mod",
302 "rs", "re", "", "", "", "", "", "",
303 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b"
304 "", "", "", "", "", "", "", "",
308 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
310 return register_names
[reg_nr
];
313 static const unsigned char *
314 sh_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
316 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
317 static unsigned char breakpoint
[] = { 0xc3, 0xc3 };
319 *lenptr
= sizeof (breakpoint
);
323 /* Prologue looks like
327 sub <room_for_loca_vars>,r15
330 Actually it can be more complicated than this but that's it, basically.
333 #define GET_SOURCE_REG(x) (((x) >> 4) & 0xf)
334 #define GET_TARGET_REG(x) (((x) >> 8) & 0xf)
336 /* STS.L PR,@-r15 0100111100100010
337 r15-4-->r15, PR-->(r15) */
338 #define IS_STS(x) ((x) == 0x4f22)
340 /* MOV.L Rm,@-r15 00101111mmmm0110
341 r15-4-->r15, Rm-->(R15) */
342 #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
344 /* MOV r15,r14 0110111011110011
346 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
348 /* ADD #imm,r15 01111111iiiiiiii
350 #define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00)
352 #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
353 #define IS_SHLL_R3(x) ((x) == 0x4300)
355 /* ADD r3,r15 0011111100111100
357 #define IS_ADD_R3SP(x) ((x) == 0x3f3c)
359 /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
360 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
361 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
362 /* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to
363 make this entirely clear. */
364 /* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */
365 #define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b)
367 /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */
368 #define IS_MOV_ARG_TO_REG(x) \
369 (((x) & 0xf00f) == 0x6003 && \
370 ((x) & 0x00f0) >= 0x0040 && \
371 ((x) & 0x00f0) <= 0x0070)
372 /* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */
373 #define IS_MOV_ARG_TO_IND_R14(x) \
374 (((x) & 0xff0f) == 0x2e02 && \
375 ((x) & 0x00f0) >= 0x0040 && \
376 ((x) & 0x00f0) <= 0x0070)
377 /* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */
378 #define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \
379 (((x) & 0xff00) == 0x1e00 && \
380 ((x) & 0x00f0) >= 0x0040 && \
381 ((x) & 0x00f0) <= 0x0070)
383 /* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */
384 #define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000)
385 /* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */
386 #define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000)
387 /* SUB Rn,R15 00111111nnnn1000 */
388 #define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08)
390 #define FPSCR_SZ (1 << 20)
392 /* The following instructions are used for epilogue testing. */
393 #define IS_RESTORE_FP(x) ((x) == 0x6ef6)
394 #define IS_RTS(x) ((x) == 0x000b)
395 #define IS_LDS(x) ((x) == 0x4f26)
396 #define IS_MOV_FP_SP(x) ((x) == 0x6fe3)
397 #define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c)
398 #define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00)
400 /* Disassemble an instruction. */
402 gdb_print_insn_sh (bfd_vma memaddr
, disassemble_info
* info
)
404 info
->endian
= TARGET_BYTE_ORDER
;
405 return print_insn_sh (memaddr
, info
);
409 sh_analyze_prologue (CORE_ADDR pc
, CORE_ADDR current_pc
,
410 struct sh_frame_cache
*cache
)
417 int reg
, sav_reg
= -1;
419 if (pc
>= current_pc
)
423 for (opc
= pc
+ (2 * 28); pc
< opc
; pc
+= 2)
425 inst
= read_memory_unsigned_integer (pc
, 2);
426 /* See where the registers will be saved to */
429 cache
->saved_regs
[GET_SOURCE_REG (inst
)] = cache
->sp_offset
;
430 cache
->sp_offset
+= 4;
432 else if (IS_STS (inst
))
434 cache
->saved_regs
[PR_REGNUM
] = cache
->sp_offset
;
435 cache
->sp_offset
+= 4;
437 else if (IS_MOV_R3 (inst
))
439 r3_val
= ((inst
& 0xff) ^ 0x80) - 0x80;
441 else if (IS_SHLL_R3 (inst
))
445 else if (IS_ADD_R3SP (inst
))
447 cache
->sp_offset
+= -r3_val
;
449 else if (IS_ADD_IMM_SP (inst
))
451 offset
= ((inst
& 0xff) ^ 0x80) - 0x80;
452 cache
->sp_offset
-= offset
;
454 else if (IS_MOVW_PCREL_TO_REG (inst
))
458 reg
= GET_TARGET_REG (inst
);
462 offset
= (((inst
& 0xff) ^ 0x80) - 0x80) << 1;
464 read_memory_integer (((pc
+ 4) & ~3) + offset
, 2);
468 else if (IS_MOVL_PCREL_TO_REG (inst
))
472 reg
= (inst
& 0x0f00) >> 8;
476 offset
= (((inst
& 0xff) ^ 0x80) - 0x80) << 1;
478 read_memory_integer (((pc
+ 4) & ~3) + offset
, 4);
482 else if (IS_SUB_REG_FROM_SP (inst
))
484 reg
= GET_SOURCE_REG (inst
);
485 if (sav_reg
> 0 && reg
== sav_reg
)
489 cache
->sp_offset
+= sav_offset
;
491 else if (IS_FPUSH (inst
))
493 if (read_register (FPSCR_REGNUM
) & FPSCR_SZ
)
495 cache
->sp_offset
+= 8;
499 cache
->sp_offset
+= 4;
502 else if (IS_MOV_SP_FP (inst
))
506 /* At this point, only allow argument register moves to other
507 registers or argument register moves to @(X,fp) which are
508 moving the register arguments onto the stack area allocated
509 by a former add somenumber to SP call. Don't allow moving
510 to an fp indirect address above fp + cache->sp_offset. */
512 for (opc
= pc
+ 12; pc
< opc
; pc
+= 2)
514 inst
= read_memory_integer (pc
, 2);
515 if (IS_MOV_ARG_TO_IND_R14 (inst
))
517 reg
= GET_SOURCE_REG (inst
);
518 if (cache
->sp_offset
> 0)
519 cache
->saved_regs
[reg
] = cache
->sp_offset
;
521 else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst
))
523 reg
= GET_SOURCE_REG (inst
);
524 offset
= (inst
& 0xf) * 4;
525 if (cache
->sp_offset
> offset
)
526 cache
->saved_regs
[reg
] = cache
->sp_offset
- offset
;
528 else if (IS_MOV_ARG_TO_REG (inst
))
535 #if 0 /* This used to just stop when it found an instruction that
536 was not considered part of the prologue. Now, we just
537 keep going looking for likely instructions. */
546 /* Skip any prologue before the guts of a function */
548 /* Skip the prologue using the debug information. If this fails we'll
549 fall back on the 'guess' method below. */
551 after_prologue (CORE_ADDR pc
)
553 struct symtab_and_line sal
;
554 CORE_ADDR func_addr
, func_end
;
556 /* If we can not find the symbol in the partial symbol table, then
557 there is no hope we can determine the function's start address
559 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
562 /* Get the line associated with FUNC_ADDR. */
563 sal
= find_pc_line (func_addr
, 0);
565 /* There are only two cases to consider. First, the end of the source line
566 is within the function bounds. In that case we return the end of the
567 source line. Second is the end of the source line extends beyond the
568 bounds of the current function. We need to use the slow code to
569 examine instructions in that case. */
570 if (sal
.end
< func_end
)
577 sh_skip_prologue (CORE_ADDR start_pc
)
580 struct sh_frame_cache cache
;
582 /* See if we can determine the end of the prologue via the symbol table.
583 If so, then return either PC, or the PC after the prologue, whichever
585 pc
= after_prologue (start_pc
);
587 /* If after_prologue returned a useful address, then use it. Else
588 fall back on the instruction skipping code. */
590 return max (pc
, start_pc
);
592 cache
.sp_offset
= -4;
593 pc
= sh_analyze_prologue (start_pc
, (CORE_ADDR
) -1, &cache
);
602 Aggregate types not bigger than 8 bytes that have the same size and
603 alignment as one of the integer scalar types are returned in the
604 same registers as the integer type they match.
606 For example, a 2-byte aligned structure with size 2 bytes has the
607 same size and alignment as a short int, and will be returned in R0.
608 A 4-byte aligned structure with size 8 bytes has the same size and
609 alignment as a long long int, and will be returned in R0 and R1.
611 When an aggregate type is returned in R0 and R1, R0 contains the
612 first four bytes of the aggregate, and R1 contains the
613 remainder. If the size of the aggregate type is not a multiple of 4
614 bytes, the aggregate is tail-padded up to a multiple of 4
615 bytes. The value of the padding is undefined. For little-endian
616 targets the padding will appear at the most significant end of the
617 last element, for big-endian targets the padding appears at the
618 least significant end of the last element.
620 All other aggregate types are returned by address. The caller
621 function passes the address of an area large enough to hold the
622 aggregate value in R2. The called function stores the result in
625 To reiterate, structs smaller than 8 bytes could also be returned
626 in memory, if they don't pass the "same size and alignment as an
631 struct s { char c[3]; } wibble;
632 struct s foo(void) { return wibble; }
634 the return value from foo() will be in memory, not
635 in R0, because there is no 3-byte integer type.
639 struct s { char c[2]; } wibble;
640 struct s foo(void) { return wibble; }
642 because a struct containing two chars has alignment 1, that matches
643 type char, but size 2, that matches type short. There's no integer
644 type that has alignment 1 and size 2, so the struct is returned in
650 sh_use_struct_convention (int gcc_p
, struct type
*type
)
652 int len
= TYPE_LENGTH (type
);
653 int nelem
= TYPE_NFIELDS (type
);
655 /* Non-power of 2 length types and types bigger than 8 bytes (which don't
656 fit in two registers anyway) use struct convention. */
657 if (len
!= 1 && len
!= 2 && len
!= 4 && len
!= 8)
660 /* Scalar types and aggregate types with exactly one field are aligned
661 by definition. They are returned in registers. */
665 /* If the first field in the aggregate has the same length as the entire
666 aggregate type, the type is returned in registers. */
667 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, 0)) == len
)
670 /* If the size of the aggregate is 8 bytes and the first field is
671 of size 4 bytes its alignment is equal to long long's alignment,
672 so it's returned in registers. */
673 if (len
== 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type
, 0)) == 4)
676 /* Otherwise use struct convention. */
680 /* Extract from an array REGBUF containing the (raw) register state
681 the address in which a function should return its structure value,
682 as a CORE_ADDR (or an expression that can be used as one). */
684 sh_extract_struct_value_address (struct regcache
*regcache
)
688 regcache_cooked_read_unsigned (regcache
, STRUCT_RETURN_REGNUM
, &addr
);
693 sh_frame_align (struct gdbarch
*ignore
, CORE_ADDR sp
)
698 /* Function: push_dummy_call (formerly push_arguments)
699 Setup the function arguments for calling a function in the inferior.
701 On the Renesas SH architecture, there are four registers (R4 to R7)
702 which are dedicated for passing function arguments. Up to the first
703 four arguments (depending on size) may go into these registers.
704 The rest go on the stack.
706 MVS: Except on SH variants that have floating point registers.
707 In that case, float and double arguments are passed in the same
708 manner, but using FP registers instead of GP registers.
710 Arguments that are smaller than 4 bytes will still take up a whole
711 register or a whole 32-bit word on the stack, and will be
712 right-justified in the register or the stack word. This includes
713 chars, shorts, and small aggregate types.
715 Arguments that are larger than 4 bytes may be split between two or
716 more registers. If there are not enough registers free, an argument
717 may be passed partly in a register (or registers), and partly on the
718 stack. This includes doubles, long longs, and larger aggregates.
719 As far as I know, there is no upper limit to the size of aggregates
720 that will be passed in this way; in other words, the convention of
721 passing a pointer to a large aggregate instead of a copy is not used.
723 MVS: The above appears to be true for the SH variants that do not
724 have an FPU, however those that have an FPU appear to copy the
725 aggregate argument onto the stack (and not place it in registers)
726 if it is larger than 16 bytes (four GP registers).
728 An exceptional case exists for struct arguments (and possibly other
729 aggregates such as arrays) if the size is larger than 4 bytes but
730 not a multiple of 4 bytes. In this case the argument is never split
731 between the registers and the stack, but instead is copied in its
732 entirety onto the stack, AND also copied into as many registers as
733 there is room for. In other words, space in registers permitting,
734 two copies of the same argument are passed in. As far as I can tell,
735 only the one on the stack is used, although that may be a function
736 of the level of compiler optimization. I suspect this is a compiler
737 bug. Arguments of these odd sizes are left-justified within the
738 word (as opposed to arguments smaller than 4 bytes, which are
741 If the function is to return an aggregate type such as a struct, it
742 is either returned in the normal return value register R0 (if its
743 size is no greater than one byte), or else the caller must allocate
744 space into which the callee will copy the return value (if the size
745 is greater than one byte). In this case, a pointer to the return
746 value location is passed into the callee in register R2, which does
747 not displace any of the other arguments passed in via registers R4
750 /* Helper function to justify value in register according to endianess. */
752 sh_justify_value_in_reg (struct value
*val
, int len
)
754 static char valbuf
[4];
756 memset (valbuf
, 0, sizeof (valbuf
));
759 /* value gets right-justified in the register or stack word */
760 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
761 memcpy (valbuf
+ (4 - len
), (char *) VALUE_CONTENTS (val
), len
);
763 memcpy (valbuf
, (char *) VALUE_CONTENTS (val
), len
);
766 return (char *) VALUE_CONTENTS (val
);
769 /* Helper function to eval number of bytes to allocate on stack. */
771 sh_stack_allocsize (int nargs
, struct value
**args
)
775 stack_alloc
+= ((TYPE_LENGTH (VALUE_TYPE (args
[nargs
])) + 3) & ~3);
779 /* Helper functions for getting the float arguments right. Registers usage
780 depends on the ABI and the endianess. The comments should enlighten how
781 it's intended to work. */
783 /* This array stores which of the float arg registers are already in use. */
784 static int flt_argreg_array
[FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
+ 1];
786 /* This function just resets the above array to "no reg used so far". */
788 sh_init_flt_argreg (void)
790 memset (flt_argreg_array
, 0, sizeof flt_argreg_array
);
793 /* This function returns the next register to use for float arg passing.
794 It returns either a valid value between FLOAT_ARG0_REGNUM and
795 FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns
796 FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available.
798 Note that register number 0 in flt_argreg_array corresponds with the
799 real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is
800 29) the parity of the register number is preserved, which is important
801 for the double register passing test (see the "argreg & 1" test below). */
803 sh_next_flt_argreg (int len
)
807 /* First search for the next free register. */
808 for (argreg
= 0; argreg
<= FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
;
810 if (!flt_argreg_array
[argreg
])
813 /* No register left? */
814 if (argreg
> FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
)
815 return FLOAT_ARGLAST_REGNUM
+ 1;
819 /* Doubles are always starting in a even register number. */
822 flt_argreg_array
[argreg
] = 1;
826 /* No register left? */
827 if (argreg
> FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
)
828 return FLOAT_ARGLAST_REGNUM
+ 1;
830 /* Also mark the next register as used. */
831 flt_argreg_array
[argreg
+ 1] = 1;
833 else if (TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
835 /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */
836 if (!flt_argreg_array
[argreg
+ 1])
839 flt_argreg_array
[argreg
] = 1;
840 return FLOAT_ARG0_REGNUM
+ argreg
;
843 /* Helper function which figures out, if a type is treated like a float type.
845 The FPU ABIs have a special way how to treat types as float types.
846 Structures with exactly one member, which is of type float or double, are
847 treated exactly as the base types float or double:
857 are handled the same way as just
863 As a result, arguments of these struct types are pushed into floating point
864 registers exactly as floats or doubles, using the same decision algorithm.
866 The same is valid if these types are used as function return types. The
867 above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1
868 or even using struct convention as it is for other structs. */
871 sh_treat_as_flt_p (struct type
*type
)
873 int len
= TYPE_LENGTH (type
);
875 /* Ordinary float types are obviously treated as float. */
876 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
878 /* Otherwise non-struct types are not treated as float. */
879 if (TYPE_CODE (type
) != TYPE_CODE_STRUCT
)
881 /* Otherwise structs with more than one memeber are not treated as float. */
882 if (TYPE_NFIELDS (type
) != 1)
884 /* Otherwise if the type of that member is float, the whole type is
886 if (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0)) == TYPE_CODE_FLT
)
888 /* Otherwise it's not treated as float. */
893 sh_push_dummy_call_fpu (struct gdbarch
*gdbarch
,
895 struct regcache
*regcache
,
896 CORE_ADDR bp_addr
, int nargs
,
898 CORE_ADDR sp
, int struct_return
,
899 CORE_ADDR struct_addr
)
901 int stack_offset
= 0;
902 int argreg
= ARG0_REGNUM
;
908 int len
, reg_size
= 0;
909 int pass_on_stack
= 0;
912 /* first force sp to a 4-byte alignment */
913 sp
= sh_frame_align (gdbarch
, sp
);
916 regcache_cooked_write_unsigned (regcache
,
917 STRUCT_RETURN_REGNUM
, struct_addr
);
919 /* make room on stack for args */
920 sp
-= sh_stack_allocsize (nargs
, args
);
922 /* Initialize float argument mechanism. */
923 sh_init_flt_argreg ();
925 /* Now load as many as possible of the first arguments into
926 registers, and push the rest onto the stack. There are 16 bytes
927 in four registers available. Loop thru args from first to last. */
928 for (argnum
= 0; argnum
< nargs
; argnum
++)
930 type
= VALUE_TYPE (args
[argnum
]);
931 len
= TYPE_LENGTH (type
);
932 val
= sh_justify_value_in_reg (args
[argnum
], len
);
934 /* Some decisions have to be made how various types are handled.
935 This also differs in different ABIs. */
938 /* Find out the next register to use for a floating point value. */
939 treat_as_flt
= sh_treat_as_flt_p (type
);
941 flt_argreg
= sh_next_flt_argreg (len
);
942 /* In contrast to non-FPU CPUs, arguments are never split between
943 registers and stack. If an argument doesn't fit in the remaining
944 registers it's always pushed entirely on the stack. */
945 else if (len
> ((ARGLAST_REGNUM
- argreg
+ 1) * 4))
950 if ((treat_as_flt
&& flt_argreg
> FLOAT_ARGLAST_REGNUM
)
951 || (!treat_as_flt
&& (argreg
> ARGLAST_REGNUM
954 /* The data goes entirely on the stack, 4-byte aligned. */
955 reg_size
= (len
+ 3) & ~3;
956 write_memory (sp
+ stack_offset
, val
, reg_size
);
957 stack_offset
+= reg_size
;
959 else if (treat_as_flt
&& flt_argreg
<= FLOAT_ARGLAST_REGNUM
)
961 /* Argument goes in a float argument register. */
962 reg_size
= register_size (gdbarch
, flt_argreg
);
963 regval
= extract_unsigned_integer (val
, reg_size
);
964 /* In little endian mode, float types taking two registers
965 (doubles on sh4, long doubles on sh2e, sh3e and sh4) must
966 be stored swapped in the argument registers. The below
967 code first writes the first 32 bits in the next but one
968 register, increments the val and len values accordingly
969 and then proceeds as normal by writing the second 32 bits
970 into the next register. */
971 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
972 && TYPE_LENGTH (type
) == 2 * reg_size
)
974 regcache_cooked_write_unsigned (regcache
, flt_argreg
+ 1,
978 regval
= extract_unsigned_integer (val
, reg_size
);
980 regcache_cooked_write_unsigned (regcache
, flt_argreg
++, regval
);
982 else if (!treat_as_flt
&& argreg
<= ARGLAST_REGNUM
)
984 /* there's room in a register */
985 reg_size
= register_size (gdbarch
, argreg
);
986 regval
= extract_unsigned_integer (val
, reg_size
);
987 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
989 /* Store the value one register at a time or in one step on stack. */
995 /* Store return address. */
996 regcache_cooked_write_unsigned (regcache
, PR_REGNUM
, bp_addr
);
998 /* Update stack pointer. */
999 regcache_cooked_write_unsigned (regcache
, SP_REGNUM
, sp
);
1005 sh_push_dummy_call_nofpu (struct gdbarch
*gdbarch
,
1006 CORE_ADDR func_addr
,
1007 struct regcache
*regcache
,
1009 int nargs
, struct value
**args
,
1010 CORE_ADDR sp
, int struct_return
,
1011 CORE_ADDR struct_addr
)
1013 int stack_offset
= 0;
1014 int argreg
= ARG0_REGNUM
;
1021 /* first force sp to a 4-byte alignment */
1022 sp
= sh_frame_align (gdbarch
, sp
);
1025 regcache_cooked_write_unsigned (regcache
,
1026 STRUCT_RETURN_REGNUM
, struct_addr
);
1028 /* make room on stack for args */
1029 sp
-= sh_stack_allocsize (nargs
, args
);
1031 /* Now load as many as possible of the first arguments into
1032 registers, and push the rest onto the stack. There are 16 bytes
1033 in four registers available. Loop thru args from first to last. */
1034 for (argnum
= 0; argnum
< nargs
; argnum
++)
1036 type
= VALUE_TYPE (args
[argnum
]);
1037 len
= TYPE_LENGTH (type
);
1038 val
= sh_justify_value_in_reg (args
[argnum
], len
);
1042 if (argreg
> ARGLAST_REGNUM
)
1044 /* The remainder of the data goes entirely on the stack,
1046 reg_size
= (len
+ 3) & ~3;
1047 write_memory (sp
+ stack_offset
, val
, reg_size
);
1048 stack_offset
+= reg_size
;
1050 else if (argreg
<= ARGLAST_REGNUM
)
1052 /* there's room in a register */
1053 reg_size
= register_size (gdbarch
, argreg
);
1054 regval
= extract_unsigned_integer (val
, reg_size
);
1055 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
1057 /* Store the value reg_size bytes at a time. This means that things
1058 larger than reg_size bytes may go partly in registers and partly
1065 /* Store return address. */
1066 regcache_cooked_write_unsigned (regcache
, PR_REGNUM
, bp_addr
);
1068 /* Update stack pointer. */
1069 regcache_cooked_write_unsigned (regcache
, SP_REGNUM
, sp
);
1074 /* Find a function's return value in the appropriate registers (in
1075 regbuf), and copy it into valbuf. Extract from an array REGBUF
1076 containing the (raw) register state a function return value of type
1077 TYPE, and copy that, in virtual format, into VALBUF. */
1079 sh_default_extract_return_value (struct type
*type
, struct regcache
*regcache
,
1082 int len
= TYPE_LENGTH (type
);
1083 int return_register
= R0_REGNUM
;
1090 regcache_cooked_read_unsigned (regcache
, R0_REGNUM
, &c
);
1091 store_unsigned_integer (valbuf
, len
, c
);
1095 int i
, regnum
= R0_REGNUM
;
1096 for (i
= 0; i
< len
; i
+= 4)
1097 regcache_raw_read (regcache
, regnum
++, (char *) valbuf
+ i
);
1100 error ("bad size for return value");
1104 sh3e_sh4_extract_return_value (struct type
*type
, struct regcache
*regcache
,
1107 if (sh_treat_as_flt_p (type
))
1109 int len
= TYPE_LENGTH (type
);
1110 int i
, regnum
= FP0_REGNUM
;
1111 for (i
= 0; i
< len
; i
+= 4)
1112 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
1113 regcache_raw_read (regcache
, regnum
++, (char *) valbuf
+ len
- 4 - i
);
1115 regcache_raw_read (regcache
, regnum
++, (char *) valbuf
+ i
);
1118 sh_default_extract_return_value (type
, regcache
, valbuf
);
1121 /* Write into appropriate registers a function return value
1122 of type TYPE, given in virtual format.
1123 If the architecture is sh4 or sh3e, store a function's return value
1124 in the R0 general register or in the FP0 floating point register,
1125 depending on the type of the return value. In all the other cases
1126 the result is stored in r0, left-justified. */
1128 sh_default_store_return_value (struct type
*type
, struct regcache
*regcache
,
1132 int len
= TYPE_LENGTH (type
);
1136 val
= extract_unsigned_integer (valbuf
, len
);
1137 regcache_cooked_write_unsigned (regcache
, R0_REGNUM
, val
);
1141 int i
, regnum
= R0_REGNUM
;
1142 for (i
= 0; i
< len
; i
+= 4)
1143 regcache_raw_write (regcache
, regnum
++, (char *) valbuf
+ i
);
1148 sh3e_sh4_store_return_value (struct type
*type
, struct regcache
*regcache
,
1151 if (sh_treat_as_flt_p (type
))
1153 int len
= TYPE_LENGTH (type
);
1154 int i
, regnum
= FP0_REGNUM
;
1155 for (i
= 0; i
< len
; i
+= 4)
1156 regcache_raw_write (regcache
, regnum
++, (char *) valbuf
+ i
);
1159 sh_default_store_return_value (type
, regcache
, valbuf
);
1162 /* Print the registers in a form similar to the E7000 */
1165 sh_generic_show_regs (void)
1167 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1168 paddr (read_register (PC_REGNUM
)),
1169 (long) read_register (SR_REGNUM
),
1170 (long) read_register (PR_REGNUM
),
1171 (long) read_register (MACH_REGNUM
),
1172 (long) read_register (MACL_REGNUM
));
1174 printf_filtered ("GBR=%08lx VBR=%08lx",
1175 (long) read_register (GBR_REGNUM
),
1176 (long) read_register (VBR_REGNUM
));
1179 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1180 (long) read_register (0), (long) read_register (1),
1181 (long) read_register (2), (long) read_register (3),
1182 (long) read_register (4), (long) read_register (5),
1183 (long) read_register (6), (long) read_register (7));
1184 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1185 (long) read_register (8), (long) read_register (9),
1186 (long) read_register (10), (long) read_register (11),
1187 (long) read_register (12), (long) read_register (13),
1188 (long) read_register (14), (long) read_register (15));
1192 sh3_show_regs (void)
1194 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1195 paddr (read_register (PC_REGNUM
)),
1196 (long) read_register (SR_REGNUM
),
1197 (long) read_register (PR_REGNUM
),
1198 (long) read_register (MACH_REGNUM
),
1199 (long) read_register (MACL_REGNUM
));
1201 printf_filtered ("GBR=%08lx VBR=%08lx",
1202 (long) read_register (GBR_REGNUM
),
1203 (long) read_register (VBR_REGNUM
));
1204 printf_filtered (" SSR=%08lx SPC=%08lx",
1205 (long) read_register (SSR_REGNUM
),
1206 (long) read_register (SPC_REGNUM
));
1209 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1210 (long) read_register (0), (long) read_register (1),
1211 (long) read_register (2), (long) read_register (3),
1212 (long) read_register (4), (long) read_register (5),
1213 (long) read_register (6), (long) read_register (7));
1214 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1215 (long) read_register (8), (long) read_register (9),
1216 (long) read_register (10), (long) read_register (11),
1217 (long) read_register (12), (long) read_register (13),
1218 (long) read_register (14), (long) read_register (15));
1223 sh2e_show_regs (void)
1225 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1226 paddr (read_register (PC_REGNUM
)),
1227 (long) read_register (SR_REGNUM
),
1228 (long) read_register (PR_REGNUM
),
1229 (long) read_register (MACH_REGNUM
),
1230 (long) read_register (MACL_REGNUM
));
1232 printf_filtered ("GBR=%08lx VBR=%08lx",
1233 (long) read_register (GBR_REGNUM
),
1234 (long) read_register (VBR_REGNUM
));
1235 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1236 (long) read_register (FPUL_REGNUM
),
1237 (long) read_register (FPSCR_REGNUM
));
1240 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1241 (long) read_register (0), (long) read_register (1),
1242 (long) read_register (2), (long) read_register (3),
1243 (long) read_register (4), (long) read_register (5),
1244 (long) read_register (6), (long) read_register (7));
1245 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1246 (long) read_register (8), (long) read_register (9),
1247 (long) read_register (10), (long) read_register (11),
1248 (long) read_register (12), (long) read_register (13),
1249 (long) read_register (14), (long) read_register (15));
1251 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM
+ 0), (long) read_register (FP0_REGNUM
+ 1), (long) read_register (FP0_REGNUM
+ 2), (long) read_register (FP0_REGNUM
+ 3), (long) read_register (FP0_REGNUM
+ 4), (long) read_register (FP0_REGNUM
+ 5), (long) read_register (FP0_REGNUM
+ 6), (long) read_register (FP0_REGNUM
+ 7));
1252 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM
+ 8), (long) read_register (FP0_REGNUM
+ 9), (long) read_register (FP0_REGNUM
+ 10), (long) read_register (FP0_REGNUM
+ 11), (long) read_register (FP0_REGNUM
+ 12), (long) read_register (FP0_REGNUM
+ 13), (long) read_register (FP0_REGNUM
+ 14), (long) read_register (FP0_REGNUM
+ 15));
1256 sh3e_show_regs (void)
1258 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1259 paddr (read_register (PC_REGNUM
)),
1260 (long) read_register (SR_REGNUM
),
1261 (long) read_register (PR_REGNUM
),
1262 (long) read_register (MACH_REGNUM
),
1263 (long) read_register (MACL_REGNUM
));
1265 printf_filtered ("GBR=%08lx VBR=%08lx",
1266 (long) read_register (GBR_REGNUM
),
1267 (long) read_register (VBR_REGNUM
));
1268 printf_filtered (" SSR=%08lx SPC=%08lx",
1269 (long) read_register (SSR_REGNUM
),
1270 (long) read_register (SPC_REGNUM
));
1271 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1272 (long) read_register (FPUL_REGNUM
),
1273 (long) read_register (FPSCR_REGNUM
));
1276 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1277 (long) read_register (0), (long) read_register (1),
1278 (long) read_register (2), (long) read_register (3),
1279 (long) read_register (4), (long) read_register (5),
1280 (long) read_register (6), (long) read_register (7));
1281 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1282 (long) read_register (8), (long) read_register (9),
1283 (long) read_register (10), (long) read_register (11),
1284 (long) read_register (12), (long) read_register (13),
1285 (long) read_register (14), (long) read_register (15));
1287 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM
+ 0), (long) read_register (FP0_REGNUM
+ 1), (long) read_register (FP0_REGNUM
+ 2), (long) read_register (FP0_REGNUM
+ 3), (long) read_register (FP0_REGNUM
+ 4), (long) read_register (FP0_REGNUM
+ 5), (long) read_register (FP0_REGNUM
+ 6), (long) read_register (FP0_REGNUM
+ 7));
1288 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM
+ 8), (long) read_register (FP0_REGNUM
+ 9), (long) read_register (FP0_REGNUM
+ 10), (long) read_register (FP0_REGNUM
+ 11), (long) read_register (FP0_REGNUM
+ 12), (long) read_register (FP0_REGNUM
+ 13), (long) read_register (FP0_REGNUM
+ 14), (long) read_register (FP0_REGNUM
+ 15));
1292 sh3_dsp_show_regs (void)
1294 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1295 paddr (read_register (PC_REGNUM
)),
1296 (long) read_register (SR_REGNUM
),
1297 (long) read_register (PR_REGNUM
),
1298 (long) read_register (MACH_REGNUM
),
1299 (long) read_register (MACL_REGNUM
));
1301 printf_filtered ("GBR=%08lx VBR=%08lx",
1302 (long) read_register (GBR_REGNUM
),
1303 (long) read_register (VBR_REGNUM
));
1305 printf_filtered (" SSR=%08lx SPC=%08lx",
1306 (long) read_register (SSR_REGNUM
),
1307 (long) read_register (SPC_REGNUM
));
1309 printf_filtered (" DSR=%08lx", (long) read_register (DSR_REGNUM
));
1312 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1313 (long) read_register (0), (long) read_register (1),
1314 (long) read_register (2), (long) read_register (3),
1315 (long) read_register (4), (long) read_register (5),
1316 (long) read_register (6), (long) read_register (7));
1317 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1318 (long) read_register (8), (long) read_register (9),
1319 (long) read_register (10), (long) read_register (11),
1320 (long) read_register (12), (long) read_register (13),
1321 (long) read_register (14), (long) read_register (15));
1324 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1325 (long) read_register (A0G_REGNUM
) & 0xff,
1326 (long) read_register (A0_REGNUM
), (long) read_register (M0_REGNUM
),
1327 (long) read_register (X0_REGNUM
), (long) read_register (Y0_REGNUM
),
1328 (long) read_register (RS_REGNUM
), (long) read_register (MOD_REGNUM
));
1329 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1330 (long) read_register (A1G_REGNUM
) & 0xff,
1331 (long) read_register (A1_REGNUM
),
1332 (long) read_register (M1_REGNUM
),
1333 (long) read_register (X1_REGNUM
),
1334 (long) read_register (Y1_REGNUM
),
1335 (long) read_register (RE_REGNUM
));
1339 sh4_show_regs (void)
1341 int pr
= read_register (FPSCR_REGNUM
) & 0x80000;
1342 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1343 paddr (read_register (PC_REGNUM
)),
1344 (long) read_register (SR_REGNUM
),
1345 (long) read_register (PR_REGNUM
),
1346 (long) read_register (MACH_REGNUM
),
1347 (long) read_register (MACL_REGNUM
));
1349 printf_filtered ("GBR=%08lx VBR=%08lx",
1350 (long) read_register (GBR_REGNUM
),
1351 (long) read_register (VBR_REGNUM
));
1352 printf_filtered (" SSR=%08lx SPC=%08lx",
1353 (long) read_register (SSR_REGNUM
),
1354 (long) read_register (SPC_REGNUM
));
1355 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1356 (long) read_register (FPUL_REGNUM
),
1357 (long) read_register (FPSCR_REGNUM
));
1360 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1361 (long) read_register (0), (long) read_register (1),
1362 (long) read_register (2), (long) read_register (3),
1363 (long) read_register (4), (long) read_register (5),
1364 (long) read_register (6), (long) read_register (7));
1365 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1366 (long) read_register (8), (long) read_register (9),
1367 (long) read_register (10), (long) read_register (11),
1368 (long) read_register (12), (long) read_register (13),
1369 (long) read_register (14), (long) read_register (15));
1371 printf_filtered ((pr
1372 ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1374 "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1375 (long) read_register (FP0_REGNUM
+ 0),
1376 (long) read_register (FP0_REGNUM
+ 1),
1377 (long) read_register (FP0_REGNUM
+ 2),
1378 (long) read_register (FP0_REGNUM
+ 3),
1379 (long) read_register (FP0_REGNUM
+ 4),
1380 (long) read_register (FP0_REGNUM
+ 5),
1381 (long) read_register (FP0_REGNUM
+ 6),
1382 (long) read_register (FP0_REGNUM
+ 7));
1383 printf_filtered ((pr
?
1384 "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" :
1385 "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1386 (long) read_register (FP0_REGNUM
+ 8),
1387 (long) read_register (FP0_REGNUM
+ 9),
1388 (long) read_register (FP0_REGNUM
+ 10),
1389 (long) read_register (FP0_REGNUM
+ 11),
1390 (long) read_register (FP0_REGNUM
+ 12),
1391 (long) read_register (FP0_REGNUM
+ 13),
1392 (long) read_register (FP0_REGNUM
+ 14),
1393 (long) read_register (FP0_REGNUM
+ 15));
1397 sh4_nofpu_show_regs (void)
1399 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1400 paddr (read_register (PC_REGNUM
)),
1401 (long) read_register (SR_REGNUM
),
1402 (long) read_register (PR_REGNUM
),
1403 (long) read_register (MACH_REGNUM
),
1404 (long) read_register (MACL_REGNUM
));
1406 printf_filtered ("GBR=%08lx VBR=%08lx",
1407 (long) read_register (GBR_REGNUM
),
1408 (long) read_register (VBR_REGNUM
));
1409 printf_filtered (" SSR=%08lx SPC=%08lx",
1410 (long) read_register (SSR_REGNUM
),
1411 (long) read_register (SPC_REGNUM
));
1414 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1415 (long) read_register (0), (long) read_register (1),
1416 (long) read_register (2), (long) read_register (3),
1417 (long) read_register (4), (long) read_register (5),
1418 (long) read_register (6), (long) read_register (7));
1419 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1420 (long) read_register (8), (long) read_register (9),
1421 (long) read_register (10), (long) read_register (11),
1422 (long) read_register (12), (long) read_register (13),
1423 (long) read_register (14), (long) read_register (15));
1427 sh_dsp_show_regs (void)
1429 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1430 paddr (read_register (PC_REGNUM
)),
1431 (long) read_register (SR_REGNUM
),
1432 (long) read_register (PR_REGNUM
),
1433 (long) read_register (MACH_REGNUM
),
1434 (long) read_register (MACL_REGNUM
));
1436 printf_filtered ("GBR=%08lx VBR=%08lx",
1437 (long) read_register (GBR_REGNUM
),
1438 (long) read_register (VBR_REGNUM
));
1440 printf_filtered (" DSR=%08lx", (long) read_register (DSR_REGNUM
));
1443 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1444 (long) read_register (0), (long) read_register (1),
1445 (long) read_register (2), (long) read_register (3),
1446 (long) read_register (4), (long) read_register (5),
1447 (long) read_register (6), (long) read_register (7));
1448 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1449 (long) read_register (8), (long) read_register (9),
1450 (long) read_register (10), (long) read_register (11),
1451 (long) read_register (12), (long) read_register (13),
1452 (long) read_register (14), (long) read_register (15));
1455 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1456 (long) read_register (A0G_REGNUM
) & 0xff,
1457 (long) read_register (A0_REGNUM
), (long) read_register (M0_REGNUM
),
1458 (long) read_register (X0_REGNUM
), (long) read_register (Y0_REGNUM
),
1459 (long) read_register (RS_REGNUM
), (long) read_register (MOD_REGNUM
));
1460 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1461 (long) read_register (A1G_REGNUM
) & 0xff,
1462 (long) read_register (A1_REGNUM
),
1463 (long) read_register (M1_REGNUM
),
1464 (long) read_register (X1_REGNUM
),
1465 (long) read_register (Y1_REGNUM
),
1466 (long) read_register (RE_REGNUM
));
1470 sh_show_regs_command (char *args
, int from_tty
)
1476 /* Return the GDB type object for the "standard" data type
1477 of data in register N. */
1478 static struct type
*
1479 sh_sh3e_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
1481 if ((reg_nr
>= FP0_REGNUM
1482 && (reg_nr
<= FP_LAST_REGNUM
)) || (reg_nr
== FPUL_REGNUM
))
1483 return builtin_type_float
;
1485 return builtin_type_int
;
1488 static struct type
*
1489 sh_sh4_build_float_register_type (int high
)
1493 temp
= create_range_type (NULL
, builtin_type_int
, 0, high
);
1494 return create_array_type (NULL
, builtin_type_float
, temp
);
1497 static struct type
*
1498 sh_sh4_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
1500 if ((reg_nr
>= FP0_REGNUM
1501 && (reg_nr
<= FP_LAST_REGNUM
)) || (reg_nr
== FPUL_REGNUM
))
1502 return builtin_type_float
;
1503 else if (reg_nr
>= DR0_REGNUM
&& reg_nr
<= DR_LAST_REGNUM
)
1504 return builtin_type_double
;
1505 else if (reg_nr
>= FV0_REGNUM
&& reg_nr
<= FV_LAST_REGNUM
)
1506 return sh_sh4_build_float_register_type (3);
1508 return builtin_type_int
;
1511 static struct type
*
1512 sh_default_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
1514 return builtin_type_int
;
1517 /* On the sh4, the DRi pseudo registers are problematic if the target
1518 is little endian. When the user writes one of those registers, for
1519 instance with 'ser var $dr0=1', we want the double to be stored
1521 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1522 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1524 This corresponds to little endian byte order & big endian word
1525 order. However if we let gdb write the register w/o conversion, it
1526 will write fr0 and fr1 this way:
1527 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1528 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1529 because it will consider fr0 and fr1 as a single LE stretch of memory.
1531 To achieve what we want we must force gdb to store things in
1532 floatformat_ieee_double_littlebyte_bigword (which is defined in
1533 include/floatformat.h and libiberty/floatformat.c.
1535 In case the target is big endian, there is no problem, the
1536 raw bytes will look like:
1537 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
1538 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1540 The other pseudo registers (the FVs) also don't pose a problem
1541 because they are stored as 4 individual FP elements. */
1544 sh_sh4_register_convert_to_virtual (int regnum
, struct type
*type
,
1545 char *from
, char *to
)
1547 if (regnum
>= DR0_REGNUM
&& regnum
<= DR_LAST_REGNUM
)
1550 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword
,
1552 store_typed_floating (to
, type
, val
);
1556 ("sh_register_convert_to_virtual called with non DR register number");
1560 sh_sh4_register_convert_to_raw (struct type
*type
, int regnum
,
1561 const void *from
, void *to
)
1563 if (regnum
>= DR0_REGNUM
&& regnum
<= DR_LAST_REGNUM
)
1565 DOUBLEST val
= extract_typed_floating (from
, type
);
1566 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword
,
1570 error ("sh_register_convert_to_raw called with non DR register number");
1573 /* For vectors of 4 floating point registers. */
1575 fv_reg_base_num (int fv_regnum
)
1579 fp_regnum
= FP0_REGNUM
+ (fv_regnum
- FV0_REGNUM
) * 4;
1583 /* For double precision floating point registers, i.e 2 fp regs.*/
1585 dr_reg_base_num (int dr_regnum
)
1589 fp_regnum
= FP0_REGNUM
+ (dr_regnum
- DR0_REGNUM
) * 2;
1594 sh_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1595 int reg_nr
, void *buffer
)
1597 int base_regnum
, portion
;
1598 char temp_buffer
[MAX_REGISTER_SIZE
];
1600 if (reg_nr
>= DR0_REGNUM
&& reg_nr
<= DR_LAST_REGNUM
)
1602 base_regnum
= dr_reg_base_num (reg_nr
);
1604 /* Build the value in the provided buffer. */
1605 /* Read the real regs for which this one is an alias. */
1606 for (portion
= 0; portion
< 2; portion
++)
1607 regcache_raw_read (regcache
, base_regnum
+ portion
,
1609 + register_size (gdbarch
,
1610 base_regnum
) * portion
));
1611 /* We must pay attention to the endiannes. */
1612 sh_sh4_register_convert_to_virtual (reg_nr
,
1613 gdbarch_register_type (gdbarch
,
1615 temp_buffer
, buffer
);
1617 else if (reg_nr
>= FV0_REGNUM
&& reg_nr
<= FV_LAST_REGNUM
)
1619 base_regnum
= fv_reg_base_num (reg_nr
);
1621 /* Read the real regs for which this one is an alias. */
1622 for (portion
= 0; portion
< 4; portion
++)
1623 regcache_raw_read (regcache
, base_regnum
+ portion
,
1625 + register_size (gdbarch
,
1626 base_regnum
) * portion
));
1631 sh_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1632 int reg_nr
, const void *buffer
)
1634 int base_regnum
, portion
;
1635 char temp_buffer
[MAX_REGISTER_SIZE
];
1637 if (reg_nr
>= DR0_REGNUM
&& reg_nr
<= DR_LAST_REGNUM
)
1639 base_regnum
= dr_reg_base_num (reg_nr
);
1641 /* We must pay attention to the endiannes. */
1642 sh_sh4_register_convert_to_raw (gdbarch_register_type (gdbarch
, reg_nr
),
1643 reg_nr
, buffer
, temp_buffer
);
1645 /* Write the real regs for which this one is an alias. */
1646 for (portion
= 0; portion
< 2; portion
++)
1647 regcache_raw_write (regcache
, base_regnum
+ portion
,
1649 + register_size (gdbarch
,
1650 base_regnum
) * portion
));
1652 else if (reg_nr
>= FV0_REGNUM
&& reg_nr
<= FV_LAST_REGNUM
)
1654 base_regnum
= fv_reg_base_num (reg_nr
);
1656 /* Write the real regs for which this one is an alias. */
1657 for (portion
= 0; portion
< 4; portion
++)
1658 regcache_raw_write (regcache
, base_regnum
+ portion
,
1660 + register_size (gdbarch
,
1661 base_regnum
) * portion
));
1665 /* Floating point vector of 4 float registers. */
1667 do_fv_register_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
1670 int first_fp_reg_num
= fv_reg_base_num (fv_regnum
);
1671 fprintf_filtered (file
, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
1672 fv_regnum
- FV0_REGNUM
,
1673 (int) read_register (first_fp_reg_num
),
1674 (int) read_register (first_fp_reg_num
+ 1),
1675 (int) read_register (first_fp_reg_num
+ 2),
1676 (int) read_register (first_fp_reg_num
+ 3));
1679 /* Double precision registers. */
1681 do_dr_register_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
1684 int first_fp_reg_num
= dr_reg_base_num (dr_regnum
);
1686 fprintf_filtered (file
, "dr%d\t0x%08x%08x\n",
1687 dr_regnum
- DR0_REGNUM
,
1688 (int) read_register (first_fp_reg_num
),
1689 (int) read_register (first_fp_reg_num
+ 1));
1693 sh_print_pseudo_register (struct gdbarch
*gdbarch
, struct ui_file
*file
,
1696 if (regnum
< NUM_REGS
|| regnum
>= NUM_REGS
+ NUM_PSEUDO_REGS
)
1697 internal_error (__FILE__
, __LINE__
,
1698 "Invalid pseudo register number %d\n", regnum
);
1699 else if (regnum
>= DR0_REGNUM
&& regnum
<= DR_LAST_REGNUM
)
1700 do_dr_register_info (gdbarch
, file
, regnum
);
1701 else if (regnum
>= FV0_REGNUM
&& regnum
<= FV_LAST_REGNUM
)
1702 do_fv_register_info (gdbarch
, file
, regnum
);
1706 sh_do_fp_register (struct gdbarch
*gdbarch
, struct ui_file
*file
, int regnum
)
1707 { /* do values for FP (float) regs */
1709 double flt
; /* double extracted from raw hex data */
1713 /* Allocate space for the float. */
1714 raw_buffer
= (char *) alloca (register_size (gdbarch
, FP0_REGNUM
));
1716 /* Get the data in raw format. */
1717 if (!frame_register_read (get_selected_frame (), regnum
, raw_buffer
))
1718 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
1720 /* Get the register as a number */
1721 flt
= unpack_double (builtin_type_float
, raw_buffer
, &inv
);
1723 /* Print the name and some spaces. */
1724 fputs_filtered (REGISTER_NAME (regnum
), file
);
1725 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum
)), file
);
1727 /* Print the value. */
1729 fprintf_filtered (file
, "<invalid float>");
1731 fprintf_filtered (file
, "%-10.9g", flt
);
1733 /* Print the fp register as hex. */
1734 fprintf_filtered (file
, "\t(raw 0x");
1735 for (j
= 0; j
< register_size (gdbarch
, regnum
); j
++)
1737 int idx
= (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
1739 : register_size (gdbarch
, regnum
) - 1 - j
);
1740 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[idx
]);
1742 fprintf_filtered (file
, ")");
1743 fprintf_filtered (file
, "\n");
1747 sh_do_register (struct gdbarch
*gdbarch
, struct ui_file
*file
, int regnum
)
1749 char raw_buffer
[MAX_REGISTER_SIZE
];
1751 fputs_filtered (REGISTER_NAME (regnum
), file
);
1752 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum
)), file
);
1754 /* Get the data in raw format. */
1755 if (!frame_register_read (get_selected_frame (), regnum
, raw_buffer
))
1756 fprintf_filtered (file
, "*value not available*\n");
1758 val_print (gdbarch_register_type (gdbarch
, regnum
), raw_buffer
, 0, 0,
1759 file
, 'x', 1, 0, Val_pretty_default
);
1760 fprintf_filtered (file
, "\t");
1761 val_print (gdbarch_register_type (gdbarch
, regnum
), raw_buffer
, 0, 0,
1762 file
, 0, 1, 0, Val_pretty_default
);
1763 fprintf_filtered (file
, "\n");
1767 sh_print_register (struct gdbarch
*gdbarch
, struct ui_file
*file
, int regnum
)
1769 if (regnum
< 0 || regnum
>= NUM_REGS
+ NUM_PSEUDO_REGS
)
1770 internal_error (__FILE__
, __LINE__
,
1771 "Invalid register number %d\n", regnum
);
1773 else if (regnum
>= 0 && regnum
< NUM_REGS
)
1775 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
1777 sh_do_fp_register (gdbarch
, file
, regnum
); /* FP regs */
1779 sh_do_register (gdbarch
, file
, regnum
); /* All other regs */
1782 else if (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
1784 sh_print_pseudo_register (gdbarch
, file
, regnum
);
1789 sh_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
1790 struct frame_info
*frame
, int regnum
, int fpregs
)
1792 if (regnum
!= -1) /* do one specified register */
1794 if (*(REGISTER_NAME (regnum
)) == '\0')
1795 error ("Not a valid register for the current processor type");
1797 sh_print_register (gdbarch
, file
, regnum
);
1800 /* do all (or most) registers */
1803 while (regnum
< NUM_REGS
)
1805 /* If the register name is empty, it is undefined for this
1806 processor, so don't display anything. */
1807 if (REGISTER_NAME (regnum
) == NULL
1808 || *(REGISTER_NAME (regnum
)) == '\0')
1814 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
1819 /* true for "INFO ALL-REGISTERS" command */
1820 sh_do_fp_register (gdbarch
, file
, regnum
); /* FP regs */
1824 regnum
+= (FP_LAST_REGNUM
- FP0_REGNUM
); /* skip FP regs */
1828 sh_do_register (gdbarch
, file
, regnum
); /* All other regs */
1834 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
1836 sh_print_pseudo_register (gdbarch
, file
, regnum
);
1842 #ifdef SVR4_SHARED_LIBS
1844 /* Fetch (and possibly build) an appropriate link_map_offsets structure
1845 for native i386 linux targets using the struct offsets defined in
1846 link.h (but without actual reference to that file).
1848 This makes it possible to access i386-linux shared libraries from
1849 a gdb that was not built on an i386-linux host (for cross debugging).
1852 struct link_map_offsets
*
1853 sh_linux_svr4_fetch_link_map_offsets (void)
1855 static struct link_map_offsets lmo
;
1856 static struct link_map_offsets
*lmp
= 0;
1862 lmo
.r_debug_size
= 8; /* 20 not actual size but all we need */
1864 lmo
.r_map_offset
= 4;
1867 lmo
.link_map_size
= 20; /* 552 not actual size but all we need */
1869 lmo
.l_addr_offset
= 0;
1870 lmo
.l_addr_size
= 4;
1872 lmo
.l_name_offset
= 4;
1873 lmo
.l_name_size
= 4;
1875 lmo
.l_next_offset
= 12;
1876 lmo
.l_next_size
= 4;
1878 lmo
.l_prev_offset
= 16;
1879 lmo
.l_prev_size
= 4;
1884 #endif /* SVR4_SHARED_LIBS */
1887 sh_dsp_register_sim_regno (int nr
)
1889 if (legacy_register_sim_regno (nr
) < 0)
1890 return legacy_register_sim_regno (nr
);
1891 if (nr
>= DSR_REGNUM
&& nr
<= Y1_REGNUM
)
1892 return nr
- DSR_REGNUM
+ SIM_SH_DSR_REGNUM
;
1893 if (nr
== MOD_REGNUM
)
1894 return SIM_SH_MOD_REGNUM
;
1895 if (nr
== RS_REGNUM
)
1896 return SIM_SH_RS_REGNUM
;
1897 if (nr
== RE_REGNUM
)
1898 return SIM_SH_RE_REGNUM
;
1899 if (nr
>= R0_BANK_REGNUM
&& nr
<= R7_BANK_REGNUM
)
1900 return nr
- R0_BANK_REGNUM
+ SIM_SH_R0_BANK_REGNUM
;
1904 static struct sh_frame_cache
*
1905 sh_alloc_frame_cache (void)
1907 struct sh_frame_cache
*cache
;
1910 cache
= FRAME_OBSTACK_ZALLOC (struct sh_frame_cache
);
1914 cache
->saved_sp
= 0;
1915 cache
->sp_offset
= 0;
1918 /* Frameless until proven otherwise. */
1921 /* Saved registers. We initialize these to -1 since zero is a valid
1922 offset (that's where fp is supposed to be stored). */
1923 for (i
= 0; i
< SH_NUM_REGS
; i
++)
1925 cache
->saved_regs
[i
] = -1;
1931 static struct sh_frame_cache
*
1932 sh_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1934 struct sh_frame_cache
*cache
;
1935 CORE_ADDR current_pc
;
1941 cache
= sh_alloc_frame_cache ();
1942 *this_cache
= cache
;
1944 /* In principle, for normal frames, fp holds the frame pointer,
1945 which holds the base address for the current stack frame.
1946 However, for functions that don't need it, the frame pointer is
1947 optional. For these "frameless" functions the frame pointer is
1948 actually the frame pointer of the calling frame. */
1949 cache
->base
= frame_unwind_register_unsigned (next_frame
, FP_REGNUM
);
1950 if (cache
->base
== 0)
1953 cache
->pc
= frame_func_unwind (next_frame
);
1954 current_pc
= frame_pc_unwind (next_frame
);
1956 sh_analyze_prologue (cache
->pc
, current_pc
, cache
);
1958 if (!cache
->uses_fp
)
1960 /* We didn't find a valid frame, which means that CACHE->base
1961 currently holds the frame pointer for our calling frame. If
1962 we're at the start of a function, or somewhere half-way its
1963 prologue, the function's frame probably hasn't been fully
1964 setup yet. Try to reconstruct the base address for the stack
1965 frame by looking at the stack pointer. For truly "frameless"
1966 functions this might work too. */
1967 cache
->base
= frame_unwind_register_unsigned (next_frame
, SP_REGNUM
);
1970 /* Now that we have the base address for the stack frame we can
1971 calculate the value of sp in the calling frame. */
1972 cache
->saved_sp
= cache
->base
+ cache
->sp_offset
;
1974 /* Adjust all the saved registers such that they contain addresses
1975 instead of offsets. */
1976 for (i
= 0; i
< SH_NUM_REGS
; i
++)
1977 if (cache
->saved_regs
[i
] != -1)
1978 cache
->saved_regs
[i
] = cache
->saved_sp
- cache
->saved_regs
[i
] - 4;
1984 sh_frame_prev_register (struct frame_info
*next_frame
, void **this_cache
,
1985 int regnum
, int *optimizedp
,
1986 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1987 int *realnump
, void *valuep
)
1989 struct sh_frame_cache
*cache
= sh_frame_cache (next_frame
, this_cache
);
1991 gdb_assert (regnum
>= 0);
1993 if (regnum
== SP_REGNUM
&& cache
->saved_sp
)
2001 /* Store the value. */
2002 store_unsigned_integer (valuep
, 4, cache
->saved_sp
);
2007 /* The PC of the previous frame is stored in the PR register of
2008 the current frame. Frob regnum so that we pull the value from
2009 the correct place. */
2010 if (regnum
== PC_REGNUM
)
2013 if (regnum
< SH_NUM_REGS
&& cache
->saved_regs
[regnum
] != -1)
2016 *lvalp
= lval_memory
;
2017 *addrp
= cache
->saved_regs
[regnum
];
2021 /* Read the value in from memory. */
2022 read_memory (*addrp
, valuep
,
2023 register_size (current_gdbarch
, regnum
));
2028 frame_register_unwind (next_frame
, regnum
,
2029 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
2033 sh_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2034 struct frame_id
*this_id
)
2036 struct sh_frame_cache
*cache
= sh_frame_cache (next_frame
, this_cache
);
2038 /* This marks the outermost frame. */
2039 if (cache
->base
== 0)
2042 *this_id
= frame_id_build (cache
->saved_sp
, cache
->pc
);
2045 static const struct frame_unwind sh_frame_unwind
= {
2048 sh_frame_prev_register
2051 static const struct frame_unwind
*
2052 sh_frame_sniffer (struct frame_info
*next_frame
)
2054 return &sh_frame_unwind
;
2058 sh_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2060 return frame_unwind_register_unsigned (next_frame
, SP_REGNUM
);
2064 sh_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2066 return frame_unwind_register_unsigned (next_frame
, PC_REGNUM
);
2069 static struct frame_id
2070 sh_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2072 return frame_id_build (sh_unwind_sp (gdbarch
, next_frame
),
2073 frame_pc_unwind (next_frame
));
2077 sh_frame_base_address (struct frame_info
*next_frame
, void **this_cache
)
2079 struct sh_frame_cache
*cache
= sh_frame_cache (next_frame
, this_cache
);
2084 static const struct frame_base sh_frame_base
= {
2086 sh_frame_base_address
,
2087 sh_frame_base_address
,
2088 sh_frame_base_address
2091 /* The epilogue is defined here as the area at the end of a function,
2092 either on the `ret' instruction itself or after an instruction which
2093 destroys the function's stack frame. */
2095 sh_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2097 CORE_ADDR func_addr
= 0, func_end
= 0;
2099 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
2102 /* The sh epilogue is max. 14 bytes long. Give another 14 bytes
2103 for a nop and some fixed data (e.g. big offsets) which are
2104 unfortunately also treated as part of the function (which
2105 means, they are below func_end. */
2106 CORE_ADDR addr
= func_end
- 28;
2107 if (addr
< func_addr
+ 4)
2108 addr
= func_addr
+ 4;
2112 /* First search forward until hitting an rts. */
2113 while (addr
< func_end
2114 && !IS_RTS (read_memory_unsigned_integer (addr
, 2)))
2116 if (addr
>= func_end
)
2119 /* At this point we should find a mov.l @r15+,r14 instruction,
2120 either before or after the rts. If not, then the function has
2121 probably no "normal" epilogue and we bail out here. */
2122 inst
= read_memory_unsigned_integer (addr
- 2, 2);
2123 if (IS_RESTORE_FP (read_memory_unsigned_integer (addr
- 2, 2)))
2125 else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr
+ 2, 2)))
2128 /* Step over possible lds.l @r15+,pr. */
2129 inst
= read_memory_unsigned_integer (addr
- 2, 2);
2133 inst
= read_memory_unsigned_integer (addr
- 2, 2);
2136 /* Step over possible mov r14,r15. */
2137 if (IS_MOV_FP_SP (inst
))
2140 inst
= read_memory_unsigned_integer (addr
- 2, 2);
2143 /* Now check for FP adjustments, using add #imm,r14 or add rX, r14
2145 while (addr
> func_addr
+ 4
2146 && (IS_ADD_REG_TO_FP (inst
) || IS_ADD_IMM_FP (inst
)))
2149 inst
= read_memory_unsigned_integer (addr
- 2, 2);
2158 static gdbarch_init_ftype sh_gdbarch_init
;
2160 static struct gdbarch
*
2161 sh_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2163 struct gdbarch
*gdbarch
;
2165 sh_show_regs
= sh_generic_show_regs
;
2166 switch (info
.bfd_arch_info
->mach
)
2169 sh_show_regs
= sh2e_show_regs
;
2171 case bfd_mach_sh_dsp
:
2172 sh_show_regs
= sh_dsp_show_regs
;
2176 sh_show_regs
= sh3_show_regs
;
2180 sh_show_regs
= sh3e_show_regs
;
2183 case bfd_mach_sh3_dsp
:
2184 case bfd_mach_sh4al_dsp
:
2185 sh_show_regs
= sh3_dsp_show_regs
;
2190 sh_show_regs
= sh4_show_regs
;
2193 case bfd_mach_sh4_nofpu
:
2194 case bfd_mach_sh4a_nofpu
:
2195 sh_show_regs
= sh4_nofpu_show_regs
;
2199 sh_show_regs
= sh64_show_regs
;
2200 /* SH5 is handled entirely in sh64-tdep.c */
2201 return sh64_gdbarch_init (info
, arches
);
2204 /* If there is already a candidate, use it. */
2205 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2207 return arches
->gdbarch
;
2209 /* None found, create a new architecture from the information
2211 gdbarch
= gdbarch_alloc (&info
, NULL
);
2213 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
2214 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2215 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2216 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2217 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2218 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2219 set_gdbarch_long_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2220 set_gdbarch_ptr_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2222 set_gdbarch_num_regs (gdbarch
, SH_NUM_REGS
);
2223 set_gdbarch_sp_regnum (gdbarch
, 15);
2224 set_gdbarch_pc_regnum (gdbarch
, 16);
2225 set_gdbarch_fp0_regnum (gdbarch
, -1);
2226 set_gdbarch_num_pseudo_regs (gdbarch
, 0);
2228 set_gdbarch_register_type (gdbarch
, sh_default_register_type
);
2230 set_gdbarch_print_registers_info (gdbarch
, sh_print_registers_info
);
2232 set_gdbarch_breakpoint_from_pc (gdbarch
, sh_breakpoint_from_pc
);
2233 set_gdbarch_use_struct_convention (gdbarch
, sh_use_struct_convention
);
2235 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_sh
);
2236 set_gdbarch_register_sim_regno (gdbarch
, legacy_register_sim_regno
);
2238 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
2240 set_gdbarch_store_return_value (gdbarch
, sh_default_store_return_value
);
2241 set_gdbarch_extract_return_value (gdbarch
, sh_default_extract_return_value
);
2242 set_gdbarch_extract_struct_value_address (gdbarch
,
2243 sh_extract_struct_value_address
);
2245 set_gdbarch_skip_prologue (gdbarch
, sh_skip_prologue
);
2246 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2247 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
2248 set_gdbarch_function_start_offset (gdbarch
, 0);
2250 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_nofpu
);
2252 set_gdbarch_frame_args_skip (gdbarch
, 0);
2253 set_gdbarch_frameless_function_invocation (gdbarch
,
2254 frameless_look_for_prologue
);
2255 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
2257 set_gdbarch_frame_align (gdbarch
, sh_frame_align
);
2258 set_gdbarch_unwind_sp (gdbarch
, sh_unwind_sp
);
2259 set_gdbarch_unwind_pc (gdbarch
, sh_unwind_pc
);
2260 set_gdbarch_unwind_dummy_id (gdbarch
, sh_unwind_dummy_id
);
2261 frame_base_set_default (gdbarch
, &sh_frame_base
);
2263 set_gdbarch_in_function_epilogue_p (gdbarch
, sh_in_function_epilogue_p
);
2265 switch (info
.bfd_arch_info
->mach
)
2268 set_gdbarch_register_name (gdbarch
, sh_sh_register_name
);
2272 set_gdbarch_register_name (gdbarch
, sh_sh_register_name
);
2276 /* doubles on sh2e and sh3e are actually 4 byte. */
2277 set_gdbarch_double_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2279 set_gdbarch_register_name (gdbarch
, sh_sh2e_register_name
);
2280 set_gdbarch_register_type (gdbarch
, sh_sh3e_register_type
);
2281 set_gdbarch_fp0_regnum (gdbarch
, 25);
2282 set_gdbarch_store_return_value (gdbarch
, sh3e_sh4_store_return_value
);
2283 set_gdbarch_extract_return_value (gdbarch
,
2284 sh3e_sh4_extract_return_value
);
2285 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_fpu
);
2288 case bfd_mach_sh_dsp
:
2289 set_gdbarch_register_name (gdbarch
, sh_sh_dsp_register_name
);
2290 set_gdbarch_register_sim_regno (gdbarch
, sh_dsp_register_sim_regno
);
2294 set_gdbarch_register_name (gdbarch
, sh_sh3_register_name
);
2298 /* doubles on sh2e and sh3e are actually 4 byte. */
2299 set_gdbarch_double_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2301 set_gdbarch_register_name (gdbarch
, sh_sh3e_register_name
);
2302 set_gdbarch_register_type (gdbarch
, sh_sh3e_register_type
);
2303 set_gdbarch_fp0_regnum (gdbarch
, 25);
2304 set_gdbarch_store_return_value (gdbarch
, sh3e_sh4_store_return_value
);
2305 set_gdbarch_extract_return_value (gdbarch
,
2306 sh3e_sh4_extract_return_value
);
2307 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_fpu
);
2310 case bfd_mach_sh3_dsp
:
2311 set_gdbarch_register_name (gdbarch
, sh_sh3_dsp_register_name
);
2312 set_gdbarch_register_sim_regno (gdbarch
, sh_dsp_register_sim_regno
);
2317 set_gdbarch_register_name (gdbarch
, sh_sh4_register_name
);
2318 set_gdbarch_register_type (gdbarch
, sh_sh4_register_type
);
2319 set_gdbarch_fp0_regnum (gdbarch
, 25);
2320 set_gdbarch_num_pseudo_regs (gdbarch
, 12);
2321 set_gdbarch_pseudo_register_read (gdbarch
, sh_pseudo_register_read
);
2322 set_gdbarch_pseudo_register_write (gdbarch
, sh_pseudo_register_write
);
2323 set_gdbarch_store_return_value (gdbarch
, sh3e_sh4_store_return_value
);
2324 set_gdbarch_extract_return_value (gdbarch
,
2325 sh3e_sh4_extract_return_value
);
2326 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_fpu
);
2329 case bfd_mach_sh4_nofpu
:
2330 case bfd_mach_sh4a_nofpu
:
2331 set_gdbarch_register_name (gdbarch
, sh_sh4_nofpu_register_name
);
2334 case bfd_mach_sh4al_dsp
:
2335 set_gdbarch_register_name (gdbarch
, sh_sh4al_dsp_register_name
);
2336 set_gdbarch_register_sim_regno (gdbarch
, sh_dsp_register_sim_regno
);
2340 set_gdbarch_register_name (gdbarch
, sh_generic_register_name
);
2344 /* Hook in ABI-specific overrides, if they have been registered. */
2345 gdbarch_init_osabi (info
, gdbarch
);
2347 frame_unwind_append_sniffer (gdbarch
, dwarf2_frame_sniffer
);
2348 frame_unwind_append_sniffer (gdbarch
, sh_frame_sniffer
);
2353 extern initialize_file_ftype _initialize_sh_tdep
; /* -Wmissing-prototypes */
2356 _initialize_sh_tdep (void)
2358 struct cmd_list_element
*c
;
2360 gdbarch_register (bfd_arch_sh
, sh_gdbarch_init
, NULL
);
2362 add_com ("regs", class_vars
, sh_show_regs_command
, "Print all registers");