1 /* Target-dependent code for Hitachi Super-H, for GDB.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
3 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 Contributed by Steve Chamberlain
37 #include "inferior.h" /* for BEFORE_TEXT_END etc. */
38 #include "gdb_string.h"
39 #include "arch-utils.h"
40 #include "floatformat.h"
45 #include "solib-svr4.h"
49 /* registers numbers shared with the simulator */
50 #include "gdb/sim-sh.h"
52 void (*sh_show_regs
) (void);
53 CORE_ADDR (*skip_prologue_hard_way
) (CORE_ADDR
);
54 void (*do_pseudo_register
) (int);
56 #define SH_DEFAULT_NUM_REGS 59
58 /* Define other aspects of the stack frame.
59 we keep a copy of the worked out return pc lying around, since it
60 is a useful bit of info */
62 struct frame_extra_info
70 sh_generic_register_name (int reg_nr
)
72 static char *register_names
[] =
74 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
75 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
76 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
78 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
79 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
81 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
82 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
86 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
88 return register_names
[reg_nr
];
92 sh_sh_register_name (int reg_nr
)
94 static char *register_names
[] =
96 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
97 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
98 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
100 "", "", "", "", "", "", "", "",
101 "", "", "", "", "", "", "", "",
103 "", "", "", "", "", "", "", "",
104 "", "", "", "", "", "", "", "",
108 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
110 return register_names
[reg_nr
];
114 sh_sh3_register_name (int reg_nr
)
116 static char *register_names
[] =
118 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
119 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
120 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
122 "", "", "", "", "", "", "", "",
123 "", "", "", "", "", "", "", "",
125 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
126 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
130 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
132 return register_names
[reg_nr
];
136 sh_sh3e_register_name (int reg_nr
)
138 static char *register_names
[] =
140 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
141 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
142 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
144 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
145 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
147 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
148 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
152 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
154 return register_names
[reg_nr
];
158 sh_sh_dsp_register_name (int reg_nr
)
160 static char *register_names
[] =
162 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
163 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
164 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
166 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
167 "y0", "y1", "", "", "", "", "", "mod",
169 "rs", "re", "", "", "", "", "", "",
170 "", "", "", "", "", "", "", "",
174 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
176 return register_names
[reg_nr
];
180 sh_sh3_dsp_register_name (int reg_nr
)
182 static char *register_names
[] =
184 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
185 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
186 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
188 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
189 "y0", "y1", "", "", "", "", "", "mod",
191 "rs", "re", "", "", "", "", "", "",
192 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b"
193 "", "", "", "", "", "", "", "",
197 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
199 return register_names
[reg_nr
];
203 sh_sh4_register_name (int reg_nr
)
205 static char *register_names
[] =
207 /* general registers 0-15 */
208 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
209 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
211 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
214 /* floating point registers 25 - 40 */
215 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
216 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
220 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
222 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
223 /* double precision (pseudo) 59 - 66 */
224 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
225 /* vectors (pseudo) 67 - 70 */
226 "fv0", "fv4", "fv8", "fv12",
227 /* FIXME: missing XF 71 - 86 */
228 /* FIXME: missing XD 87 - 94 */
232 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
234 return register_names
[reg_nr
];
238 sh_sh64_register_name (int reg_nr
)
240 static char *register_names
[] =
242 /* SH MEDIA MODE (ISA 32) */
243 /* general registers (64-bit) 0-63 */
244 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
245 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
246 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
247 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
248 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
249 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
250 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
251 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
256 /* status reg., saved status reg., saved pc reg. (64-bit) 65-67 */
259 /* target registers (64-bit) 68-75*/
260 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7",
262 /* floating point state control register (32-bit) 76 */
265 /* single precision floating point registers (32-bit) 77-140*/
266 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
267 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
268 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
269 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31",
270 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39",
271 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47",
272 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55",
273 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63",
275 /* double precision registers (pseudo) 141-172 */
276 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
277 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30",
278 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46",
279 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62",
281 /* floating point pairs (pseudo) 173-204*/
282 "fp0", "fp2", "fp4", "fp6", "fp8", "fp10", "fp12", "fp14",
283 "fp16", "fp18", "fp20", "fp22", "fp24", "fp26", "fp28", "fp30",
284 "fp32", "fp34", "fp36", "fp38", "fp40", "fp42", "fp44", "fp46",
285 "fp48", "fp50", "fp52", "fp54", "fp56", "fp58", "fp60", "fp62",
287 /* floating point vectors (4 floating point regs) (pseudo) 205-220*/
288 "fv0", "fv4", "fv8", "fv12", "fv16", "fv20", "fv24", "fv28",
289 "fv32", "fv36", "fv40", "fv44", "fv48", "fv52", "fv56", "fv60",
291 /* SH COMPACT MODE (ISA 16) (all pseudo) 221-272*/
292 "r0_c", "r1_c", "r2_c", "r3_c", "r4_c", "r5_c", "r6_c", "r7_c",
293 "r8_c", "r9_c", "r10_c", "r11_c", "r12_c", "r13_c", "r14_c", "r15_c",
295 "gbr_c", "mach_c", "macl_c", "pr_c", "t_c",
297 "fr0_c", "fr1_c", "fr2_c", "fr3_c", "fr4_c", "fr5_c", "fr6_c", "fr7_c",
298 "fr8_c", "fr9_c", "fr10_c", "fr11_c", "fr12_c", "fr13_c", "fr14_c", "fr15_c",
299 "dr0_c", "dr2_c", "dr4_c", "dr6_c", "dr8_c", "dr10_c", "dr12_c", "dr14_c",
300 "fv0_c", "fv4_c", "fv8_c", "fv12_c",
301 /* FIXME!!!! XF0 XF15, XD0 XD14 ?????*/
306 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
308 return register_names
[reg_nr
];
311 #define NUM_PSEUDO_REGS_SH_MEDIA 80
312 #define NUM_PSEUDO_REGS_SH_COMPACT 51
314 static const unsigned char *
315 sh_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
317 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
318 static unsigned char breakpoint
[] = {0xc3, 0xc3};
320 *lenptr
= sizeof (breakpoint
);
324 /* Macros and functions for setting and testing a bit in a minimal
325 symbol that marks it as 32-bit function. The MSB of the minimal
326 symbol's "info" field is used for this purpose. This field is
327 already being used to store the symbol size, so the assumption is
328 that the symbol size cannot exceed 2^31.
330 ELF_MAKE_MSYMBOL_SPECIAL
331 tests whether an ELF symbol is "special", i.e. refers
332 to a 32-bit function, and sets a "special" bit in a
333 minimal symbol to mark it as a 32-bit function
334 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol
335 MSYMBOL_SIZE returns the size of the minimal symbol, i.e.
336 the "info" field with the "special" bit masked out */
338 #define MSYMBOL_IS_SPECIAL(msym) \
339 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
342 sh64_elf_make_msymbol_special (asymbol
*sym
, struct minimal_symbol
*msym
)
347 if (((elf_symbol_type
*)(sym
))->internal_elf_sym
.st_other
== STO_SH5_ISA32
)
349 MSYMBOL_INFO (msym
) = (char *) (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
350 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
354 /* ISA32 (shmedia) function addresses are odd (bit 0 is set). Here
355 are some macros to test, set, or clear bit 0 of addresses. */
356 #define IS_ISA32_ADDR(addr) ((addr) & 1)
357 #define MAKE_ISA32_ADDR(addr) ((addr) | 1)
358 #define UNMAKE_ISA32_ADDR(addr) ((addr) & ~1)
361 pc_is_isa32 (bfd_vma memaddr
)
363 struct minimal_symbol
*sym
;
365 /* If bit 0 of the address is set, assume this is a
366 ISA32 (shmedia) address. */
367 if (IS_ISA32_ADDR (memaddr
))
370 /* A flag indicating that this is a ISA32 function is stored by elfread.c in
371 the high bit of the info field. Use this to decide if the function is
373 sym
= lookup_minimal_symbol_by_pc (memaddr
);
375 return MSYMBOL_IS_SPECIAL (sym
);
380 static const unsigned char *
381 sh_sh64_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
383 /* The BRK instruction for shmedia is
384 01101111 11110101 11111111 11110000
385 which translates in big endian mode to 0x6f, 0xf5, 0xff, 0xf0
386 and in little endian mode to 0xf0, 0xff, 0xf5, 0x6f */
388 /* The BRK instruction for shcompact is
390 which translates in big endian mode to 0x0, 0x3b
391 and in little endian mode to 0x3b, 0x0*/
393 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
395 if (pc_is_isa32 (*pcptr
))
397 static unsigned char big_breakpoint_media
[] = {0x6f, 0xf5, 0xff, 0xf0};
398 *pcptr
= UNMAKE_ISA32_ADDR (*pcptr
);
399 *lenptr
= sizeof (big_breakpoint_media
);
400 return big_breakpoint_media
;
404 static unsigned char big_breakpoint_compact
[] = {0x0, 0x3b};
405 *lenptr
= sizeof (big_breakpoint_compact
);
406 return big_breakpoint_compact
;
411 if (pc_is_isa32 (*pcptr
))
413 static unsigned char little_breakpoint_media
[] = {0xf0, 0xff, 0xf5, 0x6f};
414 *pcptr
= UNMAKE_ISA32_ADDR (*pcptr
);
415 *lenptr
= sizeof (little_breakpoint_media
);
416 return little_breakpoint_media
;
420 static unsigned char little_breakpoint_compact
[] = {0x3b, 0x0};
421 *lenptr
= sizeof (little_breakpoint_compact
);
422 return little_breakpoint_compact
;
427 /* Prologue looks like
428 [mov.l <regs>,@-r15]...
433 Actually it can be more complicated than this. For instance, with
451 /* PTABS/L Rn, TRa 0110101111110001nnnnnnl00aaa0000
452 with l=1 and n = 18 0110101111110001010010100aaa0000 */
453 #define IS_PTABSL_R18(x) (((x) & 0xffffff8f) == 0x6bf14a00)
455 /* STS.L PR,@-r0 0100000000100010
456 r0-4-->r0, PR-->(r0) */
457 #define IS_STS_R0(x) ((x) == 0x4022)
459 /* STS PR, Rm 0000mmmm00101010
461 #define IS_STS_PR(x) (((x) & 0xf0ff) == 0x2a)
463 /* MOV.L Rm,@(disp,r15) 00011111mmmmdddd
465 #define IS_MOV_TO_R15(x) (((x) & 0xff00) == 0x1f00)
467 /* MOV.L R14,@(disp,r15) 000111111110dddd
468 R14-->(dispx4+r15) */
469 #define IS_MOV_R14(x) (((x) & 0xfff0) == 0x1fe0)
471 /* ST.Q R14, disp, R18 101011001110dddddddddd0100100000
472 R18-->(dispx8+R14) */
473 #define IS_STQ_R18_R14(x) (((x) & 0xfff003ff) == 0xace00120)
475 /* ST.Q R15, disp, R18 101011001111dddddddddd0100100000
476 R18-->(dispx8+R15) */
477 #define IS_STQ_R18_R15(x) (((x) & 0xfff003ff) == 0xacf00120)
479 /* ST.L R15, disp, R18 101010001111dddddddddd0100100000
480 R18-->(dispx4+R15) */
481 #define IS_STL_R18_R15(x) (((x) & 0xfff003ff) == 0xa8f00120)
483 /* ST.Q R15, disp, R14 1010 1100 1111 dddd dddd dd00 1110 0000
484 R14-->(dispx8+R15) */
485 #define IS_STQ_R14_R15(x) (((x) & 0xfff003ff) == 0xacf000e0)
487 /* ST.L R15, disp, R14 1010 1000 1111 dddd dddd dd00 1110 0000
488 R14-->(dispx4+R15) */
489 #define IS_STL_R14_R15(x) (((x) & 0xfff003ff) == 0xa8f000e0)
491 /* ADDI.L R15,imm,R15 1101 0100 1111 ssss ssss ss00 1111 0000
493 #define IS_ADDIL_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd4f000f0)
495 /* ADDI R15,imm,R15 1101 0000 1111 ssss ssss ss00 1111 0000
497 #define IS_ADDI_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd0f000f0)
499 /* ADD.L R15,R63,R14 0000 0000 1111 1000 1111 1100 1110 0000
501 #define IS_ADDL_SP_FP_MEDIA(x) ((x) == 0x00f8fce0)
503 /* ADD R15,R63,R14 0000 0000 1111 1001 1111 1100 1110 0000
505 #define IS_ADD_SP_FP_MEDIA(x) ((x) == 0x00f9fce0)
507 #define IS_MOV_SP_FP_MEDIA(x) (IS_ADDL_SP_FP_MEDIA(x) || IS_ADD_SP_FP_MEDIA(x))
509 /* MOV #imm, R0 1110 0000 ssss ssss
511 #define IS_MOV_R0(x) (((x) & 0xff00) == 0xe000)
513 /* MOV.L @(disp,PC), R0 1101 0000 iiii iiii */
514 #define IS_MOVL_R0(x) (((x) & 0xff00) == 0xd000)
516 /* ADD r15,r0 0011 0000 1111 1100
518 #define IS_ADD_SP_R0(x) ((x) == 0x30fc)
520 /* MOV.L R14 @-R0 0010 0000 1110 0110
521 R14-->(R0-4), R0-4-->R0 */
522 #define IS_MOV_R14_R0(x) ((x) == 0x20e6)
524 /* ADD Rm,R63,Rn Rm+R63-->Rn 0000 00mm mmmm 1001 1111 11nn nnnn 0000
525 where Rm is one of r2-r9 which are the argument registers. */
526 /* FIXME: Recognize the float and double register moves too! */
527 #define IS_MEDIA_IND_ARG_MOV(x) \
528 ((((x) & 0xfc0ffc0f) == 0x0009fc00) && (((x) & 0x03f00000) >= 0x00200000 && ((x) & 0x03f00000) <= 0x00900000))
530 /* ST.Q Rn,0,Rm Rm-->Rn+0 1010 11nn nnnn 0000 0000 00mm mmmm 0000
531 or ST.L Rn,0,Rm Rm-->Rn+0 1010 10nn nnnn 0000 0000 00mm mmmm 0000
532 where Rm is one of r2-r9 which are the argument registers. */
533 #define IS_MEDIA_ARG_MOV(x) \
534 (((((x) & 0xfc0ffc0f) == 0xac000000) || (((x) & 0xfc0ffc0f) == 0xa8000000)) \
535 && (((x) & 0x000003f0) >= 0x00000020 && ((x) & 0x000003f0) <= 0x00000090))
537 /* ST.B R14,0,Rn Rn-->(R14+0) 1010 0000 1110 0000 0000 00nn nnnn 0000*/
538 /* ST.W R14,0,Rn Rn-->(R14+0) 1010 0100 1110 0000 0000 00nn nnnn 0000*/
539 /* ST.L R14,0,Rn Rn-->(R14+0) 1010 1000 1110 0000 0000 00nn nnnn 0000*/
540 /* FST.S R14,0,FRn Rn-->(R14+0) 1011 0100 1110 0000 0000 00nn nnnn 0000*/
541 /* FST.D R14,0,DRn Rn-->(R14+0) 1011 1100 1110 0000 0000 00nn nnnn 0000*/
542 #define IS_MEDIA_MOV_TO_R14(x) \
543 ((((x) & 0xfffffc0f) == 0xa0e00000) \
544 || (((x) & 0xfffffc0f) == 0xa4e00000) \
545 || (((x) & 0xfffffc0f) == 0xa8e00000) \
546 || (((x) & 0xfffffc0f) == 0xb4e00000) \
547 || (((x) & 0xfffffc0f) == 0xbce00000))
549 /* MOV Rm, Rn Rm-->Rn 0110 nnnn mmmm 0011
551 #define IS_COMPACT_IND_ARG_MOV(x) \
552 ((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0020) && (((x) & 0x00f0) <= 0x0090))
554 /* compact direct arg move!
555 MOV.L Rn, @r14 0010 1110 mmmm 0010 */
556 #define IS_COMPACT_ARG_MOV(x) \
557 (((((x) & 0xff0f) == 0x2e02) && (((x) & 0x00f0) >= 0x0020) && ((x) & 0x00f0) <= 0x0090))
559 /* MOV.B Rm, @R14 0010 1110 mmmm 0000
560 MOV.W Rm, @R14 0010 1110 mmmm 0001 */
561 #define IS_COMPACT_MOV_TO_R14(x) \
562 ((((x) & 0xff0f) == 0x2e00) || (((x) & 0xff0f) == 0x2e01))
564 #define IS_JSR_R0(x) ((x) == 0x400b)
565 #define IS_NOP(x) ((x) == 0x0009)
568 /* STS.L PR,@-r15 0100111100100010
569 r15-4-->r15, PR-->(r15) */
570 #define IS_STS(x) ((x) == 0x4f22)
572 /* MOV.L Rm,@-r15 00101111mmmm0110
573 r15-4-->r15, Rm-->(R15) */
574 #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
576 #define GET_PUSHED_REG(x) (((x) >> 4) & 0xf)
578 /* MOV r15,r14 0110111011110011
580 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
582 /* ADD #imm,r15 01111111iiiiiiii
584 #define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00)
586 #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
587 #define IS_SHLL_R3(x) ((x) == 0x4300)
589 /* ADD r3,r15 0011111100111100
591 #define IS_ADD_R3SP(x) ((x) == 0x3f3c)
593 /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
594 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
595 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
596 #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b)
598 /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011
599 MOV.L Rm,@(disp,Rn) Rm-->(dispx4+Rn) 0001nnnnmmmmdddd
600 MOV.L Rm,@Rn Rm-->(Rn) 0010nnnnmmmm0010
601 where Rm is one of r4,r5,r6,r7 which are the argument registers. */
602 #define IS_ARG_MOV(x) \
603 (((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \
604 || ((((x) & 0xf000) == 0x1000) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \
605 || ((((x) & 0xf00f) == 0x2002) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)))
607 /* MOV.L Rm,@(disp,r14) 00011110mmmmdddd
608 Rm-->(dispx4+r14) where Rm is one of r4,r5,r6,r7 */
609 #define IS_MOV_TO_R14(x) \
610 ((((x) & 0xff00) == 0x1e) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070))
612 #define FPSCR_SZ (1 << 20)
614 /* Skip any prologue before the guts of a function */
616 /* Skip the prologue using the debug information. If this fails we'll
617 fall back on the 'guess' method below. */
619 after_prologue (CORE_ADDR pc
)
621 struct symtab_and_line sal
;
622 CORE_ADDR func_addr
, func_end
;
624 /* If we can not find the symbol in the partial symbol table, then
625 there is no hope we can determine the function's start address
627 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
630 /* Get the line associated with FUNC_ADDR. */
631 sal
= find_pc_line (func_addr
, 0);
633 /* There are only two cases to consider. First, the end of the source line
634 is within the function bounds. In that case we return the end of the
635 source line. Second is the end of the source line extends beyond the
636 bounds of the current function. We need to use the slow code to
637 examine instructions in that case. */
638 if (sal
.end
< func_end
)
644 /* Here we look at each instruction in the function, and try to guess
645 where the prologue ends. Unfortunately this is not always
648 sh_skip_prologue_hard_way (CORE_ADDR start_pc
)
656 for (here
= start_pc
, end
= start_pc
+ (2 * 28); here
< end
;)
658 int w
= read_memory_integer (here
, 2);
660 if (IS_FMOV (w
) || IS_PUSH (w
) || IS_STS (w
) || IS_MOV_R3 (w
)
661 || IS_ADD_R3SP (w
) || IS_ADD_SP (w
) || IS_SHLL_R3 (w
)
662 || IS_ARG_MOV (w
) || IS_MOV_TO_R14 (w
))
666 else if (IS_MOV_SP_FP (w
))
672 /* Don't bail out yet, if we are before the copy of sp. */
681 look_for_args_moves (CORE_ADDR start_pc
, int media_mode
)
685 int insn_size
= (media_mode
? 4 : 2);
687 for (here
= start_pc
, end
= start_pc
+ (insn_size
* 28); here
< end
;)
691 w
= read_memory_integer (UNMAKE_ISA32_ADDR (here
), insn_size
);
693 if (IS_MEDIA_IND_ARG_MOV (w
))
695 /* This must be followed by a store to r14, so the argument
696 is where the debug info says it is. This can happen after
697 the SP has been saved, unfortunately. */
699 int next_insn
= read_memory_integer (UNMAKE_ISA32_ADDR (here
),
702 if (IS_MEDIA_MOV_TO_R14 (next_insn
))
705 else if (IS_MEDIA_ARG_MOV (w
))
707 /* These instructions store directly the argument in r14. */
715 w
= read_memory_integer (here
, insn_size
);
718 if (IS_COMPACT_IND_ARG_MOV (w
))
720 /* This must be followed by a store to r14, so the argument
721 is where the debug info says it is. This can happen after
722 the SP has been saved, unfortunately. */
724 int next_insn
= 0xffff & read_memory_integer (here
, insn_size
);
726 if (IS_COMPACT_MOV_TO_R14 (next_insn
))
729 else if (IS_COMPACT_ARG_MOV (w
))
731 /* These instructions store directly the argument in r14. */
734 else if (IS_MOVL_R0 (w
))
736 /* There is a function that gcc calls to get the arguments
737 passed correctly to the function. Only after this
738 function call the arguments will be found at the place
739 where they are supposed to be. This happens in case the
740 argument has to be stored into a 64-bit register (for
741 instance doubles, long longs). SHcompact doesn't have
742 access to the full 64-bits, so we store the register in
743 stack slot and store the address of the stack slot in
744 the register, then do a call through a wrapper that
745 loads the memory value into the register. A SHcompact
746 callee calls an argument decoder
747 (GCC_shcompact_incoming_args) that stores the 64-bit
748 value in a stack slot and stores the address of the
749 stack slot in the register. GCC thinks the argument is
750 just passed by transparent reference, but this is only
751 true after the argument decoder is called. Such a call
752 needs to be considered part of the prologue. */
754 /* This must be followed by a JSR @r0 instruction and by
755 a NOP instruction. After these, the prologue is over! */
757 int next_insn
= 0xffff & read_memory_integer (here
, insn_size
);
759 if (IS_JSR_R0 (next_insn
))
761 next_insn
= 0xffff & read_memory_integer (here
, insn_size
);
764 if (IS_NOP (next_insn
))
777 sh64_skip_prologue_hard_way (CORE_ADDR start_pc
)
787 if (pc_is_isa32 (start_pc
) == 0)
793 for (here
= start_pc
, end
= start_pc
+ (insn_size
* 28); here
< end
;)
798 int w
= read_memory_integer (UNMAKE_ISA32_ADDR (here
), insn_size
);
800 if (IS_STQ_R18_R14 (w
) || IS_STQ_R18_R15 (w
) || IS_STQ_R14_R15 (w
)
801 || IS_STL_R14_R15 (w
) || IS_STL_R18_R15 (w
)
802 || IS_ADDIL_SP_MEDIA (w
) || IS_ADDI_SP_MEDIA (w
) || IS_PTABSL_R18 (w
))
806 else if (IS_MOV_SP_FP (w
) || IS_MOV_SP_FP_MEDIA(w
))
814 /* Don't bail out yet, we may have arguments stored in
815 registers here, according to the debug info, so that
816 gdb can print the frames correctly. */
817 start_pc
= look_for_args_moves (here
- insn_size
, media_mode
);
823 int w
= 0xffff & read_memory_integer (here
, insn_size
);
826 if (IS_STS_R0 (w
) || IS_STS_PR (w
)
827 || IS_MOV_TO_R15 (w
) || IS_MOV_R14 (w
)
828 || IS_MOV_R0 (w
) || IS_ADD_SP_R0 (w
) || IS_MOV_R14_R0 (w
))
832 else if (IS_MOV_SP_FP (w
))
840 /* Don't bail out yet, we may have arguments stored in
841 registers here, according to the debug info, so that
842 gdb can print the frames correctly. */
843 start_pc
= look_for_args_moves (here
- insn_size
, media_mode
);
853 sh_skip_prologue (CORE_ADDR pc
)
855 CORE_ADDR post_prologue_pc
;
857 /* See if we can determine the end of the prologue via the symbol table.
858 If so, then return either PC, or the PC after the prologue, whichever
860 post_prologue_pc
= after_prologue (pc
);
862 /* If after_prologue returned a useful address, then use it. Else
863 fall back on the instruction skipping code. */
864 if (post_prologue_pc
!= 0)
865 return max (pc
, post_prologue_pc
);
867 return (skip_prologue_hard_way (pc
));
870 /* Immediately after a function call, return the saved pc.
871 Can't always go through the frames for this because on some machines
872 the new frame is not set up until the new function executes
875 The return address is the value saved in the PR register + 4 */
877 sh_saved_pc_after_call (struct frame_info
*frame
)
879 return (ADDR_BITS_REMOVE (read_register (gdbarch_tdep (current_gdbarch
)->PR_REGNUM
)));
882 /* Should call_function allocate stack space for a struct return? */
884 sh_use_struct_convention (int gcc_p
, struct type
*type
)
886 return (TYPE_LENGTH (type
) > 1);
890 sh64_use_struct_convention (int gcc_p
, struct type
*type
)
892 return (TYPE_LENGTH (type
) > 8);
895 /* Store the address of the place in which to copy the structure the
896 subroutine will return. This is called from call_function.
898 We store structs through a pointer passed in R2 */
900 sh_store_struct_return (CORE_ADDR addr
, CORE_ADDR sp
)
902 write_register (STRUCT_RETURN_REGNUM
, (addr
));
905 /* Disassemble an instruction. */
907 gdb_print_insn_sh (bfd_vma memaddr
, disassemble_info
*info
)
909 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
910 return print_insn_sh (memaddr
, info
);
912 return print_insn_shl (memaddr
, info
);
915 /* Disassemble an instruction. */
917 gdb_print_insn_sh64 (bfd_vma memaddr
, disassemble_info
*info
)
919 if (pc_is_isa32 (memaddr
))
921 /* Round down the instruction address to the appropriate boundary
922 before disassembling it. */
923 return print_insn_sh64x_media (UNMAKE_ISA32_ADDR (memaddr
), info
);
927 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
928 return print_insn_sh (memaddr
, info
);
930 return print_insn_shl (memaddr
, info
);
934 /* Given a GDB frame, determine the address of the calling function's frame.
935 This will be used to create a new GDB frame struct, and then
936 INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
938 For us, the frame address is its stack pointer value, so we look up
939 the function prologue to determine the caller's sp value, and return it. */
941 sh_frame_chain (struct frame_info
*frame
)
943 if (PC_IN_CALL_DUMMY (frame
->pc
, frame
->frame
, frame
->frame
))
944 return frame
->frame
; /* dummy frame same as caller's frame */
945 if (frame
->pc
&& !inside_entry_file (frame
->pc
))
946 return read_memory_integer (FRAME_FP (frame
) + frame
->extra_info
->f_offset
, 4);
951 /* Given a register number RN as it appears in an assembly
952 instruction, find the corresponding register number in the GDB
955 translate_insn_rn (int rn
, int media_mode
)
957 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
959 /* FIXME: this assumes that the number rn is for a not pseudo
965 /* These registers don't have a corresponding compact one. */
966 /* FIXME: This is probably not enough. */
968 if ((rn
>= 16 && rn
<= 63) || (rn
>= 93 && rn
<= 140))
971 if (rn
>= 0 && rn
<= tdep
->R0_C_REGNUM
)
972 return tdep
->R0_C_REGNUM
+ rn
;
979 sh64_frame_chain (struct frame_info
*frame
)
981 if (PC_IN_CALL_DUMMY (frame
->pc
, frame
->frame
, frame
->frame
))
982 return frame
->frame
; /* dummy frame same as caller's frame */
983 if (frame
->pc
&& !inside_entry_file (frame
->pc
))
985 int media_mode
= pc_is_isa32 (frame
->pc
);
987 if (gdbarch_tdep (current_gdbarch
)->sh_abi
== SH_ABI_32
)
990 size
= REGISTER_RAW_SIZE (translate_insn_rn (FP_REGNUM
, media_mode
));
991 return read_memory_integer (FRAME_FP (frame
) + frame
->extra_info
->f_offset
, size
);
997 /* Find REGNUM on the stack. Otherwise, it's in an active register. One thing
998 we might want to do here is to check REGNUM against the clobber mask, and
999 somehow flag it as invalid if it isn't saved on the stack somewhere. This
1000 would provide a graceful failure mode when trying to get the value of
1001 caller-saves registers for an inner frame. */
1003 sh_find_callers_reg (struct frame_info
*fi
, int regnum
)
1005 for (; fi
; fi
= fi
->next
)
1006 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
1007 /* When the caller requests PR from the dummy frame, we return PC because
1008 that's where the previous routine appears to have done a call from. */
1009 return generic_read_register_dummy (fi
->pc
, fi
->frame
, regnum
);
1012 FRAME_INIT_SAVED_REGS (fi
);
1015 if (fi
->saved_regs
[regnum
] != 0)
1016 return read_memory_integer (fi
->saved_regs
[regnum
],
1017 REGISTER_RAW_SIZE (regnum
));
1019 return read_register (regnum
);
1023 sh64_get_saved_pr (struct frame_info
*fi
, int pr_regnum
)
1027 for (; fi
; fi
= fi
->next
)
1028 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
1029 /* When the caller requests PR from the dummy frame, we return PC because
1030 that's where the previous routine appears to have done a call from. */
1031 return generic_read_register_dummy (fi
->pc
, fi
->frame
, pr_regnum
);
1034 FRAME_INIT_SAVED_REGS (fi
);
1038 media_mode
= pc_is_isa32 (fi
->pc
);
1040 if (fi
->saved_regs
[pr_regnum
] != 0)
1042 int gdb_reg_num
= translate_insn_rn (pr_regnum
, media_mode
);
1043 int size
= ((gdbarch_tdep (current_gdbarch
)->sh_abi
== SH_ABI_32
)
1045 : REGISTER_RAW_SIZE (gdb_reg_num
));
1046 return read_memory_integer (fi
->saved_regs
[pr_regnum
], size
);
1049 return read_register (pr_regnum
);
1052 /* Put here the code to store, into a struct frame_saved_regs, the
1053 addresses of the saved registers of frame described by FRAME_INFO.
1054 This includes special registers such as pc and fp saved in special
1055 ways in the stack frame. sp is even more special: the address we
1056 return for it IS the sp for the next frame. */
1058 sh_nofp_frame_init_saved_regs (struct frame_info
*fi
)
1060 int *where
= (int *) alloca ((NUM_REGS
+ NUM_PSEUDO_REGS
) * sizeof(int));
1068 char *dummy_regs
= generic_find_dummy_frame (fi
->pc
, fi
->frame
);
1070 if (fi
->saved_regs
== NULL
)
1071 frame_saved_regs_zalloc (fi
);
1073 memset (fi
->saved_regs
, 0, SIZEOF_FRAME_SAVED_REGS
);
1077 /* DANGER! This is ONLY going to work if the char buffer format of
1078 the saved registers is byte-for-byte identical to the
1079 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
1080 memcpy (fi
->saved_regs
, dummy_regs
, sizeof (fi
->saved_regs
));
1084 fi
->extra_info
->leaf_function
= 1;
1085 fi
->extra_info
->f_offset
= 0;
1087 for (rn
= 0; rn
< NUM_REGS
+ NUM_PSEUDO_REGS
; rn
++)
1092 /* Loop around examining the prologue insns until we find something
1093 that does not appear to be part of the prologue. But give up
1094 after 20 of them, since we're getting silly then. */
1096 pc
= get_pc_function_start (fi
->pc
);
1103 for (opc
= pc
+ (2 * 28); pc
< opc
; pc
+= 2)
1105 insn
= read_memory_integer (pc
, 2);
1106 /* See where the registers will be saved to */
1109 rn
= GET_PUSHED_REG (insn
);
1113 else if (IS_STS (insn
))
1115 where
[gdbarch_tdep (current_gdbarch
)->PR_REGNUM
] = depth
;
1116 /* If we're storing the pr then this isn't a leaf */
1117 fi
->extra_info
->leaf_function
= 0;
1120 else if (IS_MOV_R3 (insn
))
1122 r3_val
= ((insn
& 0xff) ^ 0x80) - 0x80;
1124 else if (IS_SHLL_R3 (insn
))
1128 else if (IS_ADD_R3SP (insn
))
1132 else if (IS_ADD_SP (insn
))
1134 depth
-= ((insn
& 0xff) ^ 0x80) - 0x80;
1136 else if (IS_MOV_SP_FP (insn
))
1138 #if 0 /* This used to just stop when it found an instruction that
1139 was not considered part of the prologue. Now, we just
1140 keep going looking for likely instructions. */
1146 /* Now we know how deep things are, we can work out their addresses */
1148 for (rn
= 0; rn
< NUM_REGS
+ NUM_PSEUDO_REGS
; rn
++)
1152 if (rn
== FP_REGNUM
)
1155 fi
->saved_regs
[rn
] = fi
->frame
- where
[rn
] + depth
- 4;
1159 fi
->saved_regs
[rn
] = 0;
1165 fi
->saved_regs
[SP_REGNUM
] = read_memory_integer (fi
->saved_regs
[FP_REGNUM
], 4);
1169 fi
->saved_regs
[SP_REGNUM
] = fi
->frame
- 4;
1172 fi
->extra_info
->f_offset
= depth
- where
[FP_REGNUM
] - 4;
1173 /* Work out the return pc - either from the saved pr or the pr
1177 /* For vectors of 4 floating point registers. */
1179 fv_reg_base_num (int fv_regnum
)
1183 fp_regnum
= FP0_REGNUM
+
1184 (fv_regnum
- gdbarch_tdep (current_gdbarch
)->FV0_REGNUM
) * 4;
1188 /* For double precision floating point registers, i.e 2 fp regs.*/
1190 dr_reg_base_num (int dr_regnum
)
1194 fp_regnum
= FP0_REGNUM
+
1195 (dr_regnum
- gdbarch_tdep (current_gdbarch
)->DR0_REGNUM
) * 2;
1199 /* For pairs of floating point registers */
1201 fpp_reg_base_num (int fpp_regnum
)
1205 fp_regnum
= FP0_REGNUM
+
1206 (fpp_regnum
- gdbarch_tdep (current_gdbarch
)->FPP0_REGNUM
) * 2;
1211 is_media_pseudo (int rn
)
1213 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1215 return (rn
>= tdep
->DR0_REGNUM
1216 && rn
<= tdep
->FV_LAST_REGNUM
);
1220 sh64_get_gdb_regnum (int gcc_regnum
, CORE_ADDR pc
)
1222 return translate_insn_rn (gcc_regnum
, pc_is_isa32 (pc
));
1226 sh64_media_reg_base_num (int reg_nr
)
1228 int base_regnum
= -1;
1229 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1231 if (reg_nr
>= tdep
->DR0_REGNUM
1232 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
1233 base_regnum
= dr_reg_base_num (reg_nr
);
1235 else if (reg_nr
>= tdep
->FPP0_REGNUM
1236 && reg_nr
<= tdep
->FPP_LAST_REGNUM
)
1237 base_regnum
= fpp_reg_base_num (reg_nr
);
1239 else if (reg_nr
>= tdep
->FV0_REGNUM
1240 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
1241 base_regnum
= fv_reg_base_num (reg_nr
);
1248 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
1249 GDB_REGNUM BASE_REGNUM
1309 sh64_compact_reg_base_num (int reg_nr
)
1311 int base_regnum
= -1;
1312 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1314 /* general register N maps to general register N */
1315 if (reg_nr
>= tdep
->R0_C_REGNUM
1316 && reg_nr
<= tdep
->R_LAST_C_REGNUM
)
1317 base_regnum
= reg_nr
- tdep
->R0_C_REGNUM
;
1319 /* floating point register N maps to floating point register N */
1320 else if (reg_nr
>= tdep
->FP0_C_REGNUM
1321 && reg_nr
<= tdep
->FP_LAST_C_REGNUM
)
1322 base_regnum
= reg_nr
- tdep
->FP0_C_REGNUM
+ FP0_REGNUM
;
1324 /* double prec register N maps to base regnum for double prec register N */
1325 else if (reg_nr
>= tdep
->DR0_C_REGNUM
1326 && reg_nr
<= tdep
->DR_LAST_C_REGNUM
)
1327 base_regnum
= dr_reg_base_num (tdep
->DR0_REGNUM
1328 + reg_nr
- tdep
->DR0_C_REGNUM
);
1330 /* vector N maps to base regnum for vector register N */
1331 else if (reg_nr
>= tdep
->FV0_C_REGNUM
1332 && reg_nr
<= tdep
->FV_LAST_C_REGNUM
)
1333 base_regnum
= fv_reg_base_num (tdep
->FV0_REGNUM
1334 + reg_nr
- tdep
->FV0_C_REGNUM
);
1336 else if (reg_nr
== tdep
->PC_C_REGNUM
)
1337 base_regnum
= PC_REGNUM
;
1339 else if (reg_nr
== tdep
->GBR_C_REGNUM
)
1342 else if (reg_nr
== tdep
->MACH_C_REGNUM
1343 || reg_nr
== tdep
->MACL_C_REGNUM
)
1346 else if (reg_nr
== tdep
->PR_C_REGNUM
)
1349 else if (reg_nr
== tdep
->T_C_REGNUM
)
1352 else if (reg_nr
== tdep
->FPSCR_C_REGNUM
)
1353 base_regnum
= tdep
->FPSCR_REGNUM
; /*???? this register is a mess. */
1355 else if (reg_nr
== tdep
->FPUL_C_REGNUM
)
1356 base_regnum
= FP0_REGNUM
+ 32;
1361 /* Given a register number RN (according to the gdb scheme) , return
1362 its corresponding architectural register. In media mode, only a
1363 subset of the registers is pseudo registers. For compact mode, all
1364 the registers are pseudo. */
1366 translate_rn_to_arch_reg_num (int rn
, int media_mode
)
1371 if (!is_media_pseudo (rn
))
1374 return sh64_media_reg_base_num (rn
);
1377 /* All compact registers are pseudo. */
1378 return sh64_compact_reg_base_num (rn
);
1382 sign_extend (int value
, int bits
)
1384 value
= value
& ((1 << bits
) - 1);
1385 return (value
& (1 << (bits
- 1))
1386 ? value
| (~((1 << bits
) - 1))
1391 sh64_nofp_frame_init_saved_regs (struct frame_info
*fi
)
1393 int *where
= (int *) alloca ((NUM_REGS
+ NUM_PSEUDO_REGS
) * sizeof (int));
1405 int gdb_register_number
;
1406 int register_number
;
1407 char *dummy_regs
= generic_find_dummy_frame (fi
->pc
, fi
->frame
);
1408 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1410 if (fi
->saved_regs
== NULL
)
1411 frame_saved_regs_zalloc (fi
);
1413 memset (fi
->saved_regs
, 0, SIZEOF_FRAME_SAVED_REGS
);
1417 /* DANGER! This is ONLY going to work if the char buffer format of
1418 the saved registers is byte-for-byte identical to the
1419 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
1420 memcpy (fi
->saved_regs
, dummy_regs
, sizeof (fi
->saved_regs
));
1424 fi
->extra_info
->leaf_function
= 1;
1425 fi
->extra_info
->f_offset
= 0;
1427 for (rn
= 0; rn
< NUM_REGS
+ NUM_PSEUDO_REGS
; rn
++)
1432 /* Loop around examining the prologue insns until we find something
1433 that does not appear to be part of the prologue. But give up
1434 after 20 of them, since we're getting silly then. */
1436 pc
= get_pc_function_start (fi
->pc
);
1443 if (pc_is_isa32 (pc
))
1454 /* The frame pointer register is general register 14 in shmedia and
1455 shcompact modes. In sh compact it is a pseudo register. Same goes
1456 for the stack pointer register, which is register 15. */
1457 fp_regnum
= translate_insn_rn (FP_REGNUM
, media_mode
);
1458 sp_regnum
= translate_insn_rn (SP_REGNUM
, media_mode
);
1460 for (opc
= pc
+ (insn_size
* 28); pc
< opc
; pc
+= insn_size
)
1462 insn
= read_memory_integer (media_mode
? UNMAKE_ISA32_ADDR (pc
) : pc
,
1465 if (media_mode
== 0)
1467 if (IS_STS_PR (insn
))
1469 int next_insn
= read_memory_integer (pc
+ insn_size
, insn_size
);
1470 if (IS_MOV_TO_R15 (next_insn
))
1472 int reg_nr
= tdep
->PR_C_REGNUM
;
1474 where
[reg_nr
] = depth
- ((((next_insn
& 0xf) ^ 0x8) - 0x8) << 2);
1475 fi
->extra_info
->leaf_function
= 0;
1479 else if (IS_MOV_R14 (insn
))
1481 where
[fp_regnum
] = depth
- ((((insn
& 0xf) ^ 0x8) - 0x8) << 2);
1484 else if (IS_MOV_R0 (insn
))
1486 /* Put in R0 the offset from SP at which to store some
1487 registers. We are interested in this value, because it
1488 will tell us where the given registers are stored within
1490 r0_val
= ((insn
& 0xff) ^ 0x80) - 0x80;
1492 else if (IS_ADD_SP_R0 (insn
))
1494 /* This instruction still prepares r0, but we don't care.
1495 We already have the offset in r0_val. */
1497 else if (IS_STS_R0 (insn
))
1499 /* Store PR at r0_val-4 from SP. Decrement r0 by 4*/
1500 int reg_nr
= tdep
->PR_C_REGNUM
;
1501 where
[reg_nr
] = depth
- (r0_val
- 4);
1503 fi
->extra_info
->leaf_function
= 0;
1505 else if (IS_MOV_R14_R0 (insn
))
1507 /* Store R14 at r0_val-4 from SP. Decrement r0 by 4 */
1508 where
[fp_regnum
] = depth
- (r0_val
- 4);
1512 else if (IS_ADD_SP (insn
))
1514 depth
-= ((insn
& 0xff) ^ 0x80) - 0x80;
1516 else if (IS_MOV_SP_FP (insn
))
1521 if (IS_ADDIL_SP_MEDIA (insn
)
1522 || IS_ADDI_SP_MEDIA (insn
))
1524 depth
-= sign_extend ((((insn
& 0xffc00) ^ 0x80000) - 0x80000) >> 10, 9);
1527 else if (IS_STQ_R18_R15 (insn
))
1529 where
[tdep
->PR_REGNUM
] =
1530 depth
- (sign_extend ((insn
& 0xffc00) >> 10, 9) << 3);
1531 fi
->extra_info
->leaf_function
= 0;
1534 else if (IS_STL_R18_R15 (insn
))
1536 where
[tdep
->PR_REGNUM
] =
1537 depth
- (sign_extend ((insn
& 0xffc00) >> 10, 9) << 2);
1538 fi
->extra_info
->leaf_function
= 0;
1541 else if (IS_STQ_R14_R15 (insn
))
1543 where
[fp_regnum
] = depth
- (sign_extend ((insn
& 0xffc00) >> 10, 9) << 3);
1546 else if (IS_STL_R14_R15 (insn
))
1548 where
[fp_regnum
] = depth
- (sign_extend ((insn
& 0xffc00) >> 10, 9) << 2);
1551 else if (IS_MOV_SP_FP_MEDIA (insn
))
1556 /* Now we know how deep things are, we can work out their addresses. */
1557 for (rn
= 0; rn
< NUM_REGS
+ NUM_PSEUDO_REGS
; rn
++)
1559 register_number
= translate_rn_to_arch_reg_num (rn
, media_mode
);
1563 if (rn
== fp_regnum
)
1566 /* Watch out! saved_regs is only for the real registers, and
1567 doesn't include space for the pseudo registers. */
1568 fi
->saved_regs
[register_number
]= fi
->frame
- where
[rn
] + depth
;
1572 fi
->saved_regs
[register_number
] = 0;
1577 /* SP_REGNUM is 15. For shmedia 15 is the real register. For
1578 shcompact 15 is the arch register corresponding to the pseudo
1579 register r15 which still is the SP register. */
1580 /* The place on the stack where fp is stored contains the sp of
1582 /* Again, saved_registers contains only space for the real registers,
1583 so we store in FP_REGNUM position. */
1585 if (tdep
->sh_abi
== SH_ABI_32
)
1588 size
= REGISTER_RAW_SIZE (fp_regnum
);
1589 fi
->saved_regs
[sp_regnum
] = read_memory_integer (fi
->saved_regs
[fp_regnum
], size
);
1592 fi
->saved_regs
[sp_regnum
] = fi
->frame
;
1594 fi
->extra_info
->f_offset
= depth
- where
[fp_regnum
];
1598 sh_fp_frame_init_saved_regs (struct frame_info
*fi
)
1600 int *where
= (int *) alloca ((NUM_REGS
+ NUM_PSEUDO_REGS
) * sizeof (int));
1608 char *dummy_regs
= generic_find_dummy_frame (fi
->pc
, fi
->frame
);
1609 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1611 if (fi
->saved_regs
== NULL
)
1612 frame_saved_regs_zalloc (fi
);
1614 memset (fi
->saved_regs
, 0, SIZEOF_FRAME_SAVED_REGS
);
1618 /* DANGER! This is ONLY going to work if the char buffer format of
1619 the saved registers is byte-for-byte identical to the
1620 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
1621 memcpy (fi
->saved_regs
, dummy_regs
, sizeof (fi
->saved_regs
));
1625 fi
->extra_info
->leaf_function
= 1;
1626 fi
->extra_info
->f_offset
= 0;
1628 for (rn
= 0; rn
< NUM_REGS
+ NUM_PSEUDO_REGS
; rn
++)
1633 /* Loop around examining the prologue insns until we find something
1634 that does not appear to be part of the prologue. But give up
1635 after 20 of them, since we're getting silly then. */
1637 pc
= get_pc_function_start (fi
->pc
);
1644 for (opc
= pc
+ (2 * 28); pc
< opc
; pc
+= 2)
1646 insn
= read_memory_integer (pc
, 2);
1647 /* See where the registers will be saved to */
1650 rn
= GET_PUSHED_REG (insn
);
1654 else if (IS_STS (insn
))
1656 where
[tdep
->PR_REGNUM
] = depth
;
1657 /* If we're storing the pr then this isn't a leaf */
1658 fi
->extra_info
->leaf_function
= 0;
1661 else if (IS_MOV_R3 (insn
))
1663 r3_val
= ((insn
& 0xff) ^ 0x80) - 0x80;
1665 else if (IS_SHLL_R3 (insn
))
1669 else if (IS_ADD_R3SP (insn
))
1673 else if (IS_ADD_SP (insn
))
1675 depth
-= ((insn
& 0xff) ^ 0x80) - 0x80;
1677 else if (IS_FMOV (insn
))
1679 if (read_register (tdep
->FPSCR_REGNUM
) & FPSCR_SZ
)
1688 else if (IS_MOV_SP_FP (insn
))
1690 #if 0 /* This used to just stop when it found an instruction that
1691 was not considered part of the prologue. Now, we just
1692 keep going looking for likely instructions. */
1698 /* Now we know how deep things are, we can work out their addresses */
1700 for (rn
= 0; rn
< NUM_REGS
+ NUM_PSEUDO_REGS
; rn
++)
1704 if (rn
== FP_REGNUM
)
1707 fi
->saved_regs
[rn
] = fi
->frame
- where
[rn
] + depth
- 4;
1711 fi
->saved_regs
[rn
] = 0;
1717 fi
->saved_regs
[SP_REGNUM
] =
1718 read_memory_integer (fi
->saved_regs
[FP_REGNUM
], 4);
1722 fi
->saved_regs
[SP_REGNUM
] = fi
->frame
- 4;
1725 fi
->extra_info
->f_offset
= depth
- where
[FP_REGNUM
] - 4;
1726 /* Work out the return pc - either from the saved pr or the pr
1730 /* Initialize the extra info saved in a FRAME */
1732 sh_init_extra_frame_info (int fromleaf
, struct frame_info
*fi
)
1735 fi
->extra_info
= (struct frame_extra_info
*)
1736 frame_obstack_alloc (sizeof (struct frame_extra_info
));
1739 fi
->pc
= FRAME_SAVED_PC (fi
->next
);
1741 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
1743 /* We need to setup fi->frame here because run_stack_dummy gets it wrong
1744 by assuming it's always FP. */
1745 fi
->frame
= generic_read_register_dummy (fi
->pc
, fi
->frame
,
1747 fi
->extra_info
->return_pc
= generic_read_register_dummy (fi
->pc
,
1750 fi
->extra_info
->f_offset
= -(CALL_DUMMY_LENGTH
+ 4);
1751 fi
->extra_info
->leaf_function
= 0;
1756 FRAME_INIT_SAVED_REGS (fi
);
1757 fi
->extra_info
->return_pc
=
1758 sh_find_callers_reg (fi
, gdbarch_tdep (current_gdbarch
)->PR_REGNUM
);
1763 sh64_init_extra_frame_info (int fromleaf
, struct frame_info
*fi
)
1765 int media_mode
= pc_is_isa32 (fi
->pc
);
1767 fi
->extra_info
= (struct frame_extra_info
*)
1768 frame_obstack_alloc (sizeof (struct frame_extra_info
));
1771 fi
->pc
= FRAME_SAVED_PC (fi
->next
);
1773 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
1775 /* We need to setup fi->frame here because run_stack_dummy gets it wrong
1776 by assuming it's always FP. */
1777 fi
->frame
= generic_read_register_dummy (fi
->pc
, fi
->frame
,
1779 fi
->extra_info
->return_pc
=
1780 generic_read_register_dummy (fi
->pc
, fi
->frame
, PC_REGNUM
);
1781 fi
->extra_info
->f_offset
= -(CALL_DUMMY_LENGTH
+ 4);
1782 fi
->extra_info
->leaf_function
= 0;
1787 FRAME_INIT_SAVED_REGS (fi
);
1788 fi
->extra_info
->return_pc
=
1789 sh64_get_saved_pr (fi
, gdbarch_tdep (current_gdbarch
)->PR_REGNUM
);
1794 sh64_get_saved_register (char *raw_buffer
, int *optimized
, CORE_ADDR
*addrp
,
1795 struct frame_info
*frame
, int regnum
,
1796 enum lval_type
*lval
)
1799 int live_regnum
= regnum
;
1800 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1802 if (!target_has_registers
)
1803 error ("No registers.");
1805 /* Normal systems don't optimize out things with register numbers. */
1806 if (optimized
!= NULL
)
1809 if (addrp
) /* default assumption: not found in memory */
1813 memset (raw_buffer
, 0, sizeof (raw_buffer
));
1815 /* We must do this here, before the following while loop changes
1816 frame, and makes it NULL. If this is a media register number,
1817 but we are in compact mode, it will become the corresponding
1818 compact pseudo register. If there is no corresponding compact
1819 pseudo-register what do we do?*/
1820 media_mode
= pc_is_isa32 (frame
->pc
);
1821 live_regnum
= translate_insn_rn (regnum
, media_mode
);
1823 /* Note: since the current frame's registers could only have been
1824 saved by frames INTERIOR TO the current frame, we skip examining
1825 the current frame itself: otherwise, we would be getting the
1826 previous frame's registers which were saved by the current frame. */
1828 while (frame
&& ((frame
= frame
->next
) != NULL
))
1830 if (PC_IN_CALL_DUMMY (frame
->pc
, frame
->frame
, frame
->frame
))
1832 if (lval
) /* found it in a CALL_DUMMY frame */
1836 generic_find_dummy_frame (frame
->pc
, frame
->frame
) +
1837 REGISTER_BYTE (regnum
),
1838 REGISTER_RAW_SIZE (regnum
));
1842 FRAME_INIT_SAVED_REGS (frame
);
1843 if (frame
->saved_regs
!= NULL
1844 && frame
->saved_regs
[regnum
] != 0)
1846 if (lval
) /* found it saved on the stack */
1847 *lval
= lval_memory
;
1848 if (regnum
== SP_REGNUM
)
1850 if (raw_buffer
) /* SP register treated specially */
1851 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
),
1852 frame
->saved_regs
[regnum
]);
1855 { /* any other register */
1858 *addrp
= frame
->saved_regs
[regnum
];
1862 if (tdep
->sh_abi
== SH_ABI_32
1863 && (live_regnum
== FP_REGNUM
1864 || live_regnum
== tdep
->PR_REGNUM
))
1867 size
= REGISTER_RAW_SIZE (live_regnum
);
1868 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
1869 read_memory (frame
->saved_regs
[regnum
], raw_buffer
, size
);
1871 read_memory (frame
->saved_regs
[regnum
],
1873 + REGISTER_RAW_SIZE (live_regnum
)
1882 /* If we get thru the loop to this point, it means the register was
1883 not saved in any frame. Return the actual live-register value. */
1885 if (lval
) /* found it in a live register */
1886 *lval
= lval_register
;
1888 *addrp
= REGISTER_BYTE (live_regnum
);
1890 read_register_gen (live_regnum
, raw_buffer
);
1893 /* Extract from an array REGBUF containing the (raw) register state
1894 the address in which a function should return its structure value,
1895 as a CORE_ADDR (or an expression that can be used as one). */
1897 sh_extract_struct_value_address (char *regbuf
)
1899 return (extract_address ((regbuf
), REGISTER_RAW_SIZE (0)));
1903 sh64_extract_struct_value_address (char *regbuf
)
1905 return (extract_address ((regbuf
+ REGISTER_BYTE (STRUCT_RETURN_REGNUM
)),
1906 REGISTER_RAW_SIZE (STRUCT_RETURN_REGNUM
)));
1910 sh_frame_saved_pc (struct frame_info
*frame
)
1912 return ((frame
)->extra_info
->return_pc
);
1915 /* Discard from the stack the innermost frame,
1916 restoring all saved registers. */
1920 register struct frame_info
*frame
= get_current_frame ();
1921 register CORE_ADDR fp
;
1922 register int regnum
;
1924 if (PC_IN_CALL_DUMMY (frame
->pc
, frame
->frame
, frame
->frame
))
1925 generic_pop_dummy_frame ();
1928 fp
= FRAME_FP (frame
);
1929 FRAME_INIT_SAVED_REGS (frame
);
1931 /* Copy regs from where they were saved in the frame */
1932 for (regnum
= 0; regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
1933 if (frame
->saved_regs
[regnum
])
1934 write_register (regnum
,
1935 read_memory_integer (frame
->saved_regs
[regnum
], 4));
1937 write_register (PC_REGNUM
, frame
->extra_info
->return_pc
);
1938 write_register (SP_REGNUM
, fp
+ 4);
1940 flush_cached_frames ();
1943 /* Used in the 'return' command. */
1945 sh64_pop_frame (void)
1947 register struct frame_info
*frame
= get_current_frame ();
1948 register CORE_ADDR fp
;
1949 register int regnum
;
1950 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1952 int media_mode
= pc_is_isa32 (frame
->pc
);
1954 if (PC_IN_CALL_DUMMY (frame
->pc
, frame
->frame
, frame
->frame
))
1955 generic_pop_dummy_frame ();
1958 fp
= FRAME_FP (frame
);
1959 FRAME_INIT_SAVED_REGS (frame
);
1961 /* Copy regs from where they were saved in the frame */
1962 for (regnum
= 0; regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
1963 if (frame
->saved_regs
[regnum
])
1966 if (tdep
->sh_abi
== SH_ABI_32
1967 && (regnum
== FP_REGNUM
1968 || regnum
== tdep
->PR_REGNUM
))
1971 size
= REGISTER_RAW_SIZE (translate_insn_rn (regnum
,
1973 write_register (regnum
,
1974 read_memory_integer (frame
->saved_regs
[regnum
],
1978 write_register (PC_REGNUM
, frame
->extra_info
->return_pc
);
1979 write_register (SP_REGNUM
, fp
+ 8);
1981 flush_cached_frames ();
1984 /* Function: push_arguments
1985 Setup the function arguments for calling a function in the inferior.
1987 On the Hitachi SH architecture, there are four registers (R4 to R7)
1988 which are dedicated for passing function arguments. Up to the first
1989 four arguments (depending on size) may go into these registers.
1990 The rest go on the stack.
1992 Arguments that are smaller than 4 bytes will still take up a whole
1993 register or a whole 32-bit word on the stack, and will be
1994 right-justified in the register or the stack word. This includes
1995 chars, shorts, and small aggregate types.
1997 Arguments that are larger than 4 bytes may be split between two or
1998 more registers. If there are not enough registers free, an argument
1999 may be passed partly in a register (or registers), and partly on the
2000 stack. This includes doubles, long longs, and larger aggregates.
2001 As far as I know, there is no upper limit to the size of aggregates
2002 that will be passed in this way; in other words, the convention of
2003 passing a pointer to a large aggregate instead of a copy is not used.
2005 An exceptional case exists for struct arguments (and possibly other
2006 aggregates such as arrays) if the size is larger than 4 bytes but
2007 not a multiple of 4 bytes. In this case the argument is never split
2008 between the registers and the stack, but instead is copied in its
2009 entirety onto the stack, AND also copied into as many registers as
2010 there is room for. In other words, space in registers permitting,
2011 two copies of the same argument are passed in. As far as I can tell,
2012 only the one on the stack is used, although that may be a function
2013 of the level of compiler optimization. I suspect this is a compiler
2014 bug. Arguments of these odd sizes are left-justified within the
2015 word (as opposed to arguments smaller than 4 bytes, which are
2018 If the function is to return an aggregate type such as a struct, it
2019 is either returned in the normal return value register R0 (if its
2020 size is no greater than one byte), or else the caller must allocate
2021 space into which the callee will copy the return value (if the size
2022 is greater than one byte). In this case, a pointer to the return
2023 value location is passed into the callee in register R2, which does
2024 not displace any of the other arguments passed in via registers R4
2028 sh_push_arguments (int nargs
, struct value
**args
, CORE_ADDR sp
,
2029 int struct_return
, CORE_ADDR struct_addr
)
2031 int stack_offset
, stack_alloc
;
2039 int odd_sized_struct
;
2040 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2042 /* first force sp to a 4-byte alignment */
2045 /* The "struct return pointer" pseudo-argument has its own dedicated
2048 write_register (STRUCT_RETURN_REGNUM
, struct_addr
);
2050 /* Now make sure there's space on the stack */
2051 for (argnum
= 0, stack_alloc
= 0; argnum
< nargs
; argnum
++)
2052 stack_alloc
+= ((TYPE_LENGTH (VALUE_TYPE (args
[argnum
])) + 3) & ~3);
2053 sp
-= stack_alloc
; /* make room on stack for args */
2055 /* Now load as many as possible of the first arguments into
2056 registers, and push the rest onto the stack. There are 16 bytes
2057 in four registers available. Loop thru args from first to last. */
2059 argreg
= tdep
->ARG0_REGNUM
;
2060 for (argnum
= 0, stack_offset
= 0; argnum
< nargs
; argnum
++)
2062 type
= VALUE_TYPE (args
[argnum
]);
2063 len
= TYPE_LENGTH (type
);
2064 memset (valbuf
, 0, sizeof (valbuf
));
2067 /* value gets right-justified in the register or stack word */
2068 memcpy (valbuf
+ (4 - len
),
2069 (char *) VALUE_CONTENTS (args
[argnum
]), len
);
2073 val
= (char *) VALUE_CONTENTS (args
[argnum
]);
2075 if (len
> 4 && (len
& 3) != 0)
2076 odd_sized_struct
= 1; /* such structs go entirely on stack */
2078 odd_sized_struct
= 0;
2081 if (argreg
> tdep
->ARGLAST_REGNUM
2082 || odd_sized_struct
)
2084 /* must go on the stack */
2085 write_memory (sp
+ stack_offset
, val
, 4);
2088 /* NOTE WELL!!!!! This is not an "else if" clause!!!
2089 That's because some *&^%$ things get passed on the stack
2090 AND in the registers! */
2091 if (argreg
<= tdep
->ARGLAST_REGNUM
)
2093 /* there's room in a register */
2094 regval
= extract_address (val
, REGISTER_RAW_SIZE (argreg
));
2095 write_register (argreg
++, regval
);
2097 /* Store the value 4 bytes at a time. This means that things
2098 larger than 4 bytes may go partly in registers and partly
2100 len
-= REGISTER_RAW_SIZE (argreg
);
2101 val
+= REGISTER_RAW_SIZE (argreg
);
2107 /* R2-R9 for integer types and integer equivalent (char, pointers) and
2108 non-scalar (struct, union) elements (even if the elements are
2110 FR0-FR11 for single precision floating point (float)
2111 DR0-DR10 for double precision floating point (double)
2113 If a float is argument number 3 (for instance) and arguments number
2114 1,2, and 4 are integer, the mapping will be:
2115 arg1 -->R2, arg2 --> R3, arg3 -->FR0, arg4 --> R5. I.e. R4 is not used.
2117 If a float is argument number 10 (for instance) and arguments number
2118 1 through 10 are integer, the mapping will be:
2119 arg1->R2, arg2->R3, arg3->R4, arg4->R5, arg5->R6, arg6->R7, arg7->R8,
2120 arg8->R9, arg9->(0,SP)stack(8-byte aligned), arg10->FR0, arg11->stack(16,SP).
2121 I.e. there is hole in the stack.
2123 Different rules apply for variable arguments functions, and for functions
2124 for which the prototype is not known. */
2127 sh64_push_arguments (int nargs
, struct value
**args
, CORE_ADDR sp
,
2128 int struct_return
, CORE_ADDR struct_addr
)
2130 int stack_offset
, stack_alloc
;
2134 int float_arg_index
= 0;
2135 int double_arg_index
= 0;
2145 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2147 memset (fp_args
, 0, sizeof (fp_args
));
2149 /* first force sp to a 8-byte alignment */
2152 /* The "struct return pointer" pseudo-argument has its own dedicated
2156 write_register (STRUCT_RETURN_REGNUM
, struct_addr
);
2158 /* Now make sure there's space on the stack */
2159 for (argnum
= 0, stack_alloc
= 0; argnum
< nargs
; argnum
++)
2160 stack_alloc
+= ((TYPE_LENGTH (VALUE_TYPE (args
[argnum
])) + 7) & ~7);
2161 sp
-= stack_alloc
; /* make room on stack for args */
2163 /* Now load as many as possible of the first arguments into
2164 registers, and push the rest onto the stack. There are 64 bytes
2165 in eight registers available. Loop thru args from first to last. */
2167 int_argreg
= tdep
->ARG0_REGNUM
;
2168 float_argreg
= FP0_REGNUM
;
2169 double_argreg
= tdep
->DR0_REGNUM
;
2171 for (argnum
= 0, stack_offset
= 0; argnum
< nargs
; argnum
++)
2173 type
= VALUE_TYPE (args
[argnum
]);
2174 len
= TYPE_LENGTH (type
);
2175 memset (valbuf
, 0, sizeof (valbuf
));
2177 if (TYPE_CODE (type
) != TYPE_CODE_FLT
)
2179 argreg_size
= REGISTER_RAW_SIZE (int_argreg
);
2181 if (len
< argreg_size
)
2183 /* value gets right-justified in the register or stack word */
2184 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2185 memcpy (valbuf
+ argreg_size
- len
,
2186 (char *) VALUE_CONTENTS (args
[argnum
]), len
);
2188 memcpy (valbuf
, (char *) VALUE_CONTENTS (args
[argnum
]), len
);
2193 val
= (char *) VALUE_CONTENTS (args
[argnum
]);
2197 if (int_argreg
> tdep
->ARGLAST_REGNUM
)
2199 /* must go on the stack */
2200 write_memory (sp
+ stack_offset
, val
, argreg_size
);
2201 stack_offset
+= 8;/*argreg_size;*/
2203 /* NOTE WELL!!!!! This is not an "else if" clause!!!
2204 That's because some *&^%$ things get passed on the stack
2205 AND in the registers! */
2206 if (int_argreg
<= tdep
->ARGLAST_REGNUM
)
2208 /* there's room in a register */
2209 regval
= extract_address (val
, argreg_size
);
2210 write_register (int_argreg
, regval
);
2212 /* Store the value 8 bytes at a time. This means that
2213 things larger than 8 bytes may go partly in registers
2214 and partly on the stack. FIXME: argreg is incremented
2215 before we use its size. */
2223 val
= (char *) VALUE_CONTENTS (args
[argnum
]);
2226 /* Where is it going to be stored? */
2227 while (fp_args
[float_arg_index
])
2230 /* Now float_argreg points to the register where it
2231 should be stored. Are we still within the allowed
2233 if (float_arg_index
<= tdep
->FLOAT_ARGLAST_REGNUM
)
2235 /* Goes in FR0...FR11 */
2236 write_register_gen (FP0_REGNUM
+ float_arg_index
, val
);
2237 fp_args
[float_arg_index
] = 1;
2238 /* Skip the corresponding general argument register. */
2243 /* Store it as the integers, 8 bytes at the time, if
2244 necessary spilling on the stack. */
2249 /* Where is it going to be stored? */
2250 while (fp_args
[double_arg_index
])
2251 double_arg_index
+= 2;
2252 /* Now double_argreg points to the register
2253 where it should be stored.
2254 Are we still within the allowed register set? */
2255 if (double_arg_index
< tdep
->FLOAT_ARGLAST_REGNUM
)
2257 /* Goes in DR0...DR10 */
2258 /* The numbering of the DRi registers is consecutive,
2259 i.e. includes odd numbers. */
2260 int double_register_offset
= double_arg_index
/ 2;
2261 int regnum
= tdep
->DR0_REGNUM
+
2262 double_register_offset
;
2264 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
2266 memset (valbuf_tmp
, 0, sizeof (valbuf_tmp
));
2267 REGISTER_CONVERT_TO_VIRTUAL (regnum
,
2268 type
, val
, valbuf_tmp
);
2272 /* Note: must use write_register_gen here instead
2273 of regcache_write, because regcache_write works
2274 only for real registers, not pseudo.
2275 write_register_gen will call the gdbarch
2276 function to do register writes, and that will
2277 properly know how to deal with pseudoregs. */
2278 write_register_gen (regnum
, val
);
2279 fp_args
[double_arg_index
] = 1;
2280 fp_args
[double_arg_index
+ 1] = 1;
2281 /* Skip the corresponding general argument register. */
2286 /* Store it as the integers, 8 bytes at the time, if
2287 necessary spilling on the stack. */
2294 /* Function: push_return_address (pc)
2295 Set up the return address for the inferior function call.
2296 Needed for targets where we don't actually execute a JSR/BSR instruction */
2299 sh_push_return_address (CORE_ADDR pc
, CORE_ADDR sp
)
2301 write_register (gdbarch_tdep (current_gdbarch
)->PR_REGNUM
,
2302 CALL_DUMMY_ADDRESS ());
2306 /* Function: fix_call_dummy
2307 Poke the callee function's address into the destination part of
2308 the CALL_DUMMY. The address is actually stored in a data word
2309 following the actualy CALL_DUMMY instructions, which will load
2310 it into a register using PC-relative addressing. This function
2311 expects the CALL_DUMMY to look like this:
2322 sh_fix_call_dummy (char *dummy
, CORE_ADDR pc
, CORE_ADDR fun
, int nargs
,
2323 struct value
**args
, struct type
*type
, int gcc_p
)
2325 *(unsigned long *) (dummy
+ 8) = fun
;
2330 sh_coerce_float_to_double (struct type
*formal
, struct type
*actual
)
2335 /* Find a function's return value in the appropriate registers (in
2336 regbuf), and copy it into valbuf. Extract from an array REGBUF
2337 containing the (raw) register state a function return value of type
2338 TYPE, and copy that, in virtual format, into VALBUF. */
2340 sh_extract_return_value (struct type
*type
, char *regbuf
, char *valbuf
)
2342 int len
= TYPE_LENGTH (type
);
2343 int return_register
= R0_REGNUM
;
2348 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2349 offset
= REGISTER_BYTE (return_register
) + 4 - len
;
2351 offset
= REGISTER_BYTE (return_register
);
2352 memcpy (valbuf
, regbuf
+ offset
, len
);
2356 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2357 offset
= REGISTER_BYTE (return_register
) + 8 - len
;
2359 offset
= REGISTER_BYTE (return_register
);
2360 memcpy (valbuf
, regbuf
+ offset
, len
);
2363 error ("bad size for return value");
2367 sh3e_sh4_extract_return_value (struct type
*type
, char *regbuf
, char *valbuf
)
2369 int return_register
;
2371 int len
= TYPE_LENGTH (type
);
2373 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2374 return_register
= FP0_REGNUM
;
2376 return_register
= R0_REGNUM
;
2378 if (len
== 8 && TYPE_CODE (type
) == TYPE_CODE_FLT
)
2381 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
2382 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword
,
2383 (char *) regbuf
+ REGISTER_BYTE (return_register
),
2386 floatformat_to_doublest (&floatformat_ieee_double_big
,
2387 (char *) regbuf
+ REGISTER_BYTE (return_register
),
2389 store_floating (valbuf
, len
, val
);
2393 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2394 offset
= REGISTER_BYTE (return_register
) + 4 - len
;
2396 offset
= REGISTER_BYTE (return_register
);
2397 memcpy (valbuf
, regbuf
+ offset
, len
);
2401 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2402 offset
= REGISTER_BYTE (return_register
) + 8 - len
;
2404 offset
= REGISTER_BYTE (return_register
);
2405 memcpy (valbuf
, regbuf
+ offset
, len
);
2408 error ("bad size for return value");
2412 sh64_extract_return_value (struct type
*type
, char *regbuf
, char *valbuf
)
2415 int return_register
;
2416 int len
= TYPE_LENGTH (type
);
2417 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2419 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2423 /* Return value stored in FP0_REGNUM */
2424 return_register
= FP0_REGNUM
;
2425 offset
= REGISTER_BYTE (return_register
);
2426 memcpy (valbuf
, (char *) regbuf
+ offset
, len
);
2430 /* return value stored in DR0_REGNUM */
2433 return_register
= tdep
->DR0_REGNUM
;
2434 offset
= REGISTER_BYTE (return_register
);
2436 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
2437 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword
,
2438 (char *) regbuf
+ offset
, &val
);
2440 floatformat_to_doublest (&floatformat_ieee_double_big
,
2441 (char *) regbuf
+ offset
, &val
);
2442 store_floating (valbuf
, len
, val
);
2449 /* Result is in register 2. If smaller than 8 bytes, it is padded
2450 at the most significant end. */
2451 return_register
= tdep
->RETURN_REGNUM
;
2452 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2453 offset
= REGISTER_BYTE (return_register
) +
2454 REGISTER_RAW_SIZE (return_register
) - len
;
2456 offset
= REGISTER_BYTE (return_register
);
2457 memcpy (valbuf
, (char *) regbuf
+ offset
, len
);
2460 error ("bad size for return value");
2464 /* Write into appropriate registers a function return value
2465 of type TYPE, given in virtual format.
2466 If the architecture is sh4 or sh3e, store a function's return value
2467 in the R0 general register or in the FP0 floating point register,
2468 depending on the type of the return value. In all the other cases
2469 the result is stored in r0, left-justified. */
2471 sh_default_store_return_value (struct type
*type
, char *valbuf
)
2473 char buf
[32]; /* more than enough... */
2475 if (TYPE_LENGTH (type
) < REGISTER_RAW_SIZE (R0_REGNUM
))
2477 /* Add leading zeros to the value. */
2478 memset (buf
, 0, REGISTER_RAW_SIZE (R0_REGNUM
));
2479 memcpy (buf
+ REGISTER_RAW_SIZE (R0_REGNUM
) - TYPE_LENGTH (type
),
2480 valbuf
, TYPE_LENGTH (type
));
2481 write_register_bytes (REGISTER_BYTE (R0_REGNUM
), buf
,
2482 REGISTER_RAW_SIZE (R0_REGNUM
));
2485 write_register_bytes (REGISTER_BYTE (R0_REGNUM
), valbuf
,
2486 TYPE_LENGTH (type
));
2490 sh3e_sh4_store_return_value (struct type
*type
, char *valbuf
)
2492 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2493 write_register_bytes (REGISTER_BYTE (FP0_REGNUM
),
2494 valbuf
, TYPE_LENGTH (type
));
2496 sh_default_store_return_value (type
, valbuf
);
2500 sh64_store_return_value (struct type
*type
, char *valbuf
)
2502 char buf
[64]; /* more than enough... */
2503 int len
= TYPE_LENGTH (type
);
2505 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2509 /* Return value stored in FP0_REGNUM */
2510 write_register_gen (FP0_REGNUM
, valbuf
);
2514 /* return value stored in DR0_REGNUM */
2515 /* FIXME: Implement */
2520 int return_register
= gdbarch_tdep (current_gdbarch
)->RETURN_REGNUM
;
2523 if (len
<= REGISTER_RAW_SIZE (return_register
))
2525 /* Pad with zeros. */
2526 memset (buf
, 0, REGISTER_RAW_SIZE (return_register
));
2527 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
2528 offset
= 0; /*REGISTER_RAW_SIZE (return_register) - len;*/
2530 offset
= REGISTER_RAW_SIZE (return_register
) - len
;
2532 memcpy (buf
+ offset
, valbuf
, len
);
2533 write_register_gen (return_register
, buf
);
2536 write_register_gen (return_register
, valbuf
);
2540 /* Print the registers in a form similar to the E7000 */
2543 sh_generic_show_regs (void)
2545 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2547 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2548 paddr (read_register (PC_REGNUM
)),
2549 (long) read_register (tdep
->SR_REGNUM
),
2550 (long) read_register (tdep
->PR_REGNUM
),
2551 (long) read_register (MACH_REGNUM
),
2552 (long) read_register (MACL_REGNUM
));
2554 printf_filtered ("GBR=%08lx VBR=%08lx",
2555 (long) read_register (GBR_REGNUM
),
2556 (long) read_register (VBR_REGNUM
));
2558 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2559 (long) read_register (0),
2560 (long) read_register (1),
2561 (long) read_register (2),
2562 (long) read_register (3),
2563 (long) read_register (4),
2564 (long) read_register (5),
2565 (long) read_register (6),
2566 (long) read_register (7));
2567 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2568 (long) read_register (8),
2569 (long) read_register (9),
2570 (long) read_register (10),
2571 (long) read_register (11),
2572 (long) read_register (12),
2573 (long) read_register (13),
2574 (long) read_register (14),
2575 (long) read_register (15));
2579 sh3_show_regs (void)
2581 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2583 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2584 paddr (read_register (PC_REGNUM
)),
2585 (long) read_register (tdep
->SR_REGNUM
),
2586 (long) read_register (tdep
->PR_REGNUM
),
2587 (long) read_register (MACH_REGNUM
),
2588 (long) read_register (MACL_REGNUM
));
2590 printf_filtered ("GBR=%08lx VBR=%08lx",
2591 (long) read_register (GBR_REGNUM
),
2592 (long) read_register (VBR_REGNUM
));
2593 printf_filtered (" SSR=%08lx SPC=%08lx",
2594 (long) read_register (tdep
->SSR_REGNUM
),
2595 (long) read_register (tdep
->SPC_REGNUM
));
2597 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2598 (long) read_register (0),
2599 (long) read_register (1),
2600 (long) read_register (2),
2601 (long) read_register (3),
2602 (long) read_register (4),
2603 (long) read_register (5),
2604 (long) read_register (6),
2605 (long) read_register (7));
2606 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2607 (long) read_register (8),
2608 (long) read_register (9),
2609 (long) read_register (10),
2610 (long) read_register (11),
2611 (long) read_register (12),
2612 (long) read_register (13),
2613 (long) read_register (14),
2614 (long) read_register (15));
2619 sh3e_show_regs (void)
2621 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2623 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2624 paddr (read_register (PC_REGNUM
)),
2625 (long) read_register (tdep
->SR_REGNUM
),
2626 (long) read_register (tdep
->PR_REGNUM
),
2627 (long) read_register (MACH_REGNUM
),
2628 (long) read_register (MACL_REGNUM
));
2630 printf_filtered ("GBR=%08lx VBR=%08lx",
2631 (long) read_register (GBR_REGNUM
),
2632 (long) read_register (VBR_REGNUM
));
2633 printf_filtered (" SSR=%08lx SPC=%08lx",
2634 (long) read_register (tdep
->SSR_REGNUM
),
2635 (long) read_register (tdep
->SPC_REGNUM
));
2636 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
2637 (long) read_register (tdep
->FPUL_REGNUM
),
2638 (long) read_register (tdep
->FPSCR_REGNUM
));
2640 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2641 (long) read_register (0),
2642 (long) read_register (1),
2643 (long) read_register (2),
2644 (long) read_register (3),
2645 (long) read_register (4),
2646 (long) read_register (5),
2647 (long) read_register (6),
2648 (long) read_register (7));
2649 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2650 (long) read_register (8),
2651 (long) read_register (9),
2652 (long) read_register (10),
2653 (long) read_register (11),
2654 (long) read_register (12),
2655 (long) read_register (13),
2656 (long) read_register (14),
2657 (long) read_register (15));
2659 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2660 (long) read_register (FP0_REGNUM
+ 0),
2661 (long) read_register (FP0_REGNUM
+ 1),
2662 (long) read_register (FP0_REGNUM
+ 2),
2663 (long) read_register (FP0_REGNUM
+ 3),
2664 (long) read_register (FP0_REGNUM
+ 4),
2665 (long) read_register (FP0_REGNUM
+ 5),
2666 (long) read_register (FP0_REGNUM
+ 6),
2667 (long) read_register (FP0_REGNUM
+ 7));
2668 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2669 (long) read_register (FP0_REGNUM
+ 8),
2670 (long) read_register (FP0_REGNUM
+ 9),
2671 (long) read_register (FP0_REGNUM
+ 10),
2672 (long) read_register (FP0_REGNUM
+ 11),
2673 (long) read_register (FP0_REGNUM
+ 12),
2674 (long) read_register (FP0_REGNUM
+ 13),
2675 (long) read_register (FP0_REGNUM
+ 14),
2676 (long) read_register (FP0_REGNUM
+ 15));
2680 sh3_dsp_show_regs (void)
2682 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2684 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2685 paddr (read_register (PC_REGNUM
)),
2686 (long) read_register (tdep
->SR_REGNUM
),
2687 (long) read_register (tdep
->PR_REGNUM
),
2688 (long) read_register (MACH_REGNUM
),
2689 (long) read_register (MACL_REGNUM
));
2691 printf_filtered ("GBR=%08lx VBR=%08lx",
2692 (long) read_register (GBR_REGNUM
),
2693 (long) read_register (VBR_REGNUM
));
2695 printf_filtered (" SSR=%08lx SPC=%08lx",
2696 (long) read_register (tdep
->SSR_REGNUM
),
2697 (long) read_register (tdep
->SPC_REGNUM
));
2699 printf_filtered (" DSR=%08lx",
2700 (long) read_register (tdep
->DSR_REGNUM
));
2702 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2703 (long) read_register (0),
2704 (long) read_register (1),
2705 (long) read_register (2),
2706 (long) read_register (3),
2707 (long) read_register (4),
2708 (long) read_register (5),
2709 (long) read_register (6),
2710 (long) read_register (7));
2711 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2712 (long) read_register (8),
2713 (long) read_register (9),
2714 (long) read_register (10),
2715 (long) read_register (11),
2716 (long) read_register (12),
2717 (long) read_register (13),
2718 (long) read_register (14),
2719 (long) read_register (15));
2721 printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
2722 (long) read_register (tdep
->A0G_REGNUM
) & 0xff,
2723 (long) read_register (tdep
->A0_REGNUM
),
2724 (long) read_register (tdep
->M0_REGNUM
),
2725 (long) read_register (tdep
->X0_REGNUM
),
2726 (long) read_register (tdep
->Y0_REGNUM
),
2727 (long) read_register (tdep
->RS_REGNUM
),
2728 (long) read_register (tdep
->MOD_REGNUM
));
2729 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
2730 (long) read_register (tdep
->A1G_REGNUM
) & 0xff,
2731 (long) read_register (tdep
->A1_REGNUM
),
2732 (long) read_register (tdep
->M1_REGNUM
),
2733 (long) read_register (tdep
->X1_REGNUM
),
2734 (long) read_register (tdep
->Y1_REGNUM
),
2735 (long) read_register (tdep
->RE_REGNUM
));
2739 sh4_show_regs (void)
2741 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2743 int pr
= read_register (tdep
->FPSCR_REGNUM
) & 0x80000;
2744 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2745 paddr (read_register (PC_REGNUM
)),
2746 (long) read_register (tdep
->SR_REGNUM
),
2747 (long) read_register (tdep
->PR_REGNUM
),
2748 (long) read_register (MACH_REGNUM
),
2749 (long) read_register (MACL_REGNUM
));
2751 printf_filtered ("GBR=%08lx VBR=%08lx",
2752 (long) read_register (GBR_REGNUM
),
2753 (long) read_register (VBR_REGNUM
));
2754 printf_filtered (" SSR=%08lx SPC=%08lx",
2755 (long) read_register (tdep
->SSR_REGNUM
),
2756 (long) read_register (tdep
->SPC_REGNUM
));
2757 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
2758 (long) read_register (tdep
->FPUL_REGNUM
),
2759 (long) read_register (tdep
->FPSCR_REGNUM
));
2761 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2762 (long) read_register (0),
2763 (long) read_register (1),
2764 (long) read_register (2),
2765 (long) read_register (3),
2766 (long) read_register (4),
2767 (long) read_register (5),
2768 (long) read_register (6),
2769 (long) read_register (7));
2770 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2771 (long) read_register (8),
2772 (long) read_register (9),
2773 (long) read_register (10),
2774 (long) read_register (11),
2775 (long) read_register (12),
2776 (long) read_register (13),
2777 (long) read_register (14),
2778 (long) read_register (15));
2780 printf_filtered ((pr
2781 ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
2782 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2783 (long) read_register (FP0_REGNUM
+ 0),
2784 (long) read_register (FP0_REGNUM
+ 1),
2785 (long) read_register (FP0_REGNUM
+ 2),
2786 (long) read_register (FP0_REGNUM
+ 3),
2787 (long) read_register (FP0_REGNUM
+ 4),
2788 (long) read_register (FP0_REGNUM
+ 5),
2789 (long) read_register (FP0_REGNUM
+ 6),
2790 (long) read_register (FP0_REGNUM
+ 7));
2791 printf_filtered ((pr
2792 ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
2793 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2794 (long) read_register (FP0_REGNUM
+ 8),
2795 (long) read_register (FP0_REGNUM
+ 9),
2796 (long) read_register (FP0_REGNUM
+ 10),
2797 (long) read_register (FP0_REGNUM
+ 11),
2798 (long) read_register (FP0_REGNUM
+ 12),
2799 (long) read_register (FP0_REGNUM
+ 13),
2800 (long) read_register (FP0_REGNUM
+ 14),
2801 (long) read_register (FP0_REGNUM
+ 15));
2805 sh_dsp_show_regs (void)
2807 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2809 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2810 paddr (read_register (PC_REGNUM
)),
2811 (long) read_register (tdep
->SR_REGNUM
),
2812 (long) read_register (tdep
->PR_REGNUM
),
2813 (long) read_register (MACH_REGNUM
),
2814 (long) read_register (MACL_REGNUM
));
2816 printf_filtered ("GBR=%08lx VBR=%08lx",
2817 (long) read_register (GBR_REGNUM
),
2818 (long) read_register (VBR_REGNUM
));
2820 printf_filtered (" DSR=%08lx",
2821 (long) read_register (tdep
->DSR_REGNUM
));
2823 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2824 (long) read_register (0),
2825 (long) read_register (1),
2826 (long) read_register (2),
2827 (long) read_register (3),
2828 (long) read_register (4),
2829 (long) read_register (5),
2830 (long) read_register (6),
2831 (long) read_register (7));
2832 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2833 (long) read_register (8),
2834 (long) read_register (9),
2835 (long) read_register (10),
2836 (long) read_register (11),
2837 (long) read_register (12),
2838 (long) read_register (13),
2839 (long) read_register (14),
2840 (long) read_register (15));
2842 printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
2843 (long) read_register (tdep
->A0G_REGNUM
) & 0xff,
2844 (long) read_register (tdep
->A0_REGNUM
),
2845 (long) read_register (tdep
->M0_REGNUM
),
2846 (long) read_register (tdep
->X0_REGNUM
),
2847 (long) read_register (tdep
->Y0_REGNUM
),
2848 (long) read_register (tdep
->RS_REGNUM
),
2849 (long) read_register (tdep
->MOD_REGNUM
));
2850 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
2851 (long) read_register (tdep
->A1G_REGNUM
) & 0xff,
2852 (long) read_register (tdep
->A1_REGNUM
),
2853 (long) read_register (tdep
->M1_REGNUM
),
2854 (long) read_register (tdep
->X1_REGNUM
),
2855 (long) read_register (tdep
->Y1_REGNUM
),
2856 (long) read_register (tdep
->RE_REGNUM
));
2860 sh64_show_media_regs (void)
2863 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2865 printf_filtered ("PC=%s SR=%016llx \n",
2866 paddr (read_register (PC_REGNUM
)),
2867 (long long) read_register (tdep
->SR_REGNUM
));
2869 printf_filtered ("SSR=%016llx SPC=%016llx \n",
2870 (long long) read_register (tdep
->SSR_REGNUM
),
2871 (long long) read_register (tdep
->SPC_REGNUM
));
2872 printf_filtered ("FPSCR=%016lx\n ",
2873 (long) read_register (tdep
->FPSCR_REGNUM
));
2875 for (i
= 0; i
< 64; i
= i
+ 4)
2876 printf_filtered ("\nR%d-R%d %016llx %016llx %016llx %016llx\n",
2878 (long long) read_register (i
+ 0),
2879 (long long) read_register (i
+ 1),
2880 (long long) read_register (i
+ 2),
2881 (long long) read_register (i
+ 3));
2883 printf_filtered ("\n");
2885 for (i
= 0; i
< 64; i
= i
+ 8)
2886 printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2888 (long) read_register (FP0_REGNUM
+ i
+ 0),
2889 (long) read_register (FP0_REGNUM
+ i
+ 1),
2890 (long) read_register (FP0_REGNUM
+ i
+ 2),
2891 (long) read_register (FP0_REGNUM
+ i
+ 3),
2892 (long) read_register (FP0_REGNUM
+ i
+ 4),
2893 (long) read_register (FP0_REGNUM
+ i
+ 5),
2894 (long) read_register (FP0_REGNUM
+ i
+ 6),
2895 (long) read_register (FP0_REGNUM
+ i
+ 7));
2899 sh64_show_compact_regs (void)
2902 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2904 printf_filtered ("PC=%s \n",
2905 paddr (read_register (tdep
->PC_C_REGNUM
)));
2907 printf_filtered ("GBR=%08lx MACH=%08lx MACL=%08lx PR=%08lx T=%08lx\n",
2908 (long) read_register (tdep
->GBR_C_REGNUM
),
2909 (long) read_register (tdep
->MACH_C_REGNUM
),
2910 (long) read_register (tdep
->MACL_C_REGNUM
),
2911 (long) read_register (tdep
->PR_C_REGNUM
),
2912 (long) read_register (tdep
->T_C_REGNUM
));
2913 printf_filtered ("FPSCR=%08lx FPUL=%08lx\n",
2914 (long) read_register (tdep
->FPSCR_REGNUM
),
2915 (long) read_register (tdep
->FPUL_REGNUM
));
2917 for (i
= 0; i
< 16; i
= i
+ 4)
2918 printf_filtered ("\nR%d-R%d %08lx %08lx %08lx %08lx\n",
2920 (long) read_register (i
+ 0),
2921 (long) read_register (i
+ 1),
2922 (long) read_register (i
+ 2),
2923 (long) read_register (i
+ 3));
2925 printf_filtered ("\n");
2927 for (i
= 0; i
< 16; i
= i
+ 8)
2928 printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2930 (long) read_register (FP0_REGNUM
+ i
+ 0),
2931 (long) read_register (FP0_REGNUM
+ i
+ 1),
2932 (long) read_register (FP0_REGNUM
+ i
+ 2),
2933 (long) read_register (FP0_REGNUM
+ i
+ 3),
2934 (long) read_register (FP0_REGNUM
+ i
+ 4),
2935 (long) read_register (FP0_REGNUM
+ i
+ 5),
2936 (long) read_register (FP0_REGNUM
+ i
+ 6),
2937 (long) read_register (FP0_REGNUM
+ i
+ 7));
2940 /*FIXME!!! This only shows the registers for shmedia, excluding the
2941 pseudo registers. */
2943 sh64_show_regs (void)
2945 if (pc_is_isa32 (selected_frame
->pc
))
2946 sh64_show_media_regs ();
2948 sh64_show_compact_regs ();
2951 void sh_show_regs_command (char *args
, int from_tty
)
2957 /* Index within `registers' of the first byte of the space for
2960 sh_default_register_byte (int reg_nr
)
2962 return (reg_nr
* 4);
2966 sh_sh4_register_byte (int reg_nr
)
2968 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2970 if (reg_nr
>= tdep
->DR0_REGNUM
2971 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
2972 return (dr_reg_base_num (reg_nr
) * 4);
2973 else if (reg_nr
>= tdep
->FV0_REGNUM
2974 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
2975 return (fv_reg_base_num (reg_nr
) * 4);
2977 return (reg_nr
* 4);
2982 SH MEDIA MODE (ISA 32)
2983 general registers (64-bit) 0-63
2984 0 r0, r1, r2, r3, r4, r5, r6, r7,
2985 64 r8, r9, r10, r11, r12, r13, r14, r15,
2986 128 r16, r17, r18, r19, r20, r21, r22, r23,
2987 192 r24, r25, r26, r27, r28, r29, r30, r31,
2988 256 r32, r33, r34, r35, r36, r37, r38, r39,
2989 320 r40, r41, r42, r43, r44, r45, r46, r47,
2990 384 r48, r49, r50, r51, r52, r53, r54, r55,
2991 448 r56, r57, r58, r59, r60, r61, r62, r63,
2996 status reg., saved status reg., saved pc reg. (64-bit) 65-67
2999 target registers (64-bit) 68-75
3000 544 tr0, tr1, tr2, tr3, tr4, tr5, tr6, tr7,
3002 floating point state control register (32-bit) 76
3005 single precision floating point registers (32-bit) 77-140
3006 612 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
3007 644 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15,
3008 676 fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23,
3009 708 fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31,
3010 740 fr32, fr33, fr34, fr35, fr36, fr37, fr38, fr39,
3011 772 fr40, fr41, fr42, fr43, fr44, fr45, fr46, fr47,
3012 804 fr48, fr49, fr50, fr51, fr52, fr53, fr54, fr55,
3013 836 fr56, fr57, fr58, fr59, fr60, fr61, fr62, fr63,
3015 TOTAL SPACE FOR REGISTERS: 868 bytes
3017 From here on they are all pseudo registers: no memory allocated.
3018 REGISTER_BYTE returns the register byte for the base register.
3020 double precision registers (pseudo) 141-172
3021 dr0, dr2, dr4, dr6, dr8, dr10, dr12, dr14,
3022 dr16, dr18, dr20, dr22, dr24, dr26, dr28, dr30,
3023 dr32, dr34, dr36, dr38, dr40, dr42, dr44, dr46,
3024 dr48, dr50, dr52, dr54, dr56, dr58, dr60, dr62,
3026 floating point pairs (pseudo) 173-204
3027 fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14,
3028 fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30,
3029 fp32, fp34, fp36, fp38, fp40, fp42, fp44, fp46,
3030 fp48, fp50, fp52, fp54, fp56, fp58, fp60, fp62,
3032 floating point vectors (4 floating point regs) (pseudo) 205-220
3033 fv0, fv4, fv8, fv12, fv16, fv20, fv24, fv28,
3034 fv32, fv36, fv40, fv44, fv48, fv52, fv56, fv60,
3036 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
3037 r0_c, r1_c, r2_c, r3_c, r4_c, r5_c, r6_c, r7_c,
3038 r8_c, r9_c, r10_c, r11_c, r12_c, r13_c, r14_c, r15_c,
3040 gbr_c, mach_c, macl_c, pr_c, t_c,
3042 fr0_c, fr1_c, fr2_c, fr3_c, fr4_c, fr5_c, fr6_c, fr7_c,
3043 fr8_c, fr9_c, fr10_c, fr11_c, fr12_c, fr13_c, fr14_c, fr15_c
3044 dr0_c, dr2_c, dr4_c, dr6_c, dr8_c, dr10_c, dr12_c, dr14_c
3045 fv0_c, fv4_c, fv8_c, fv12_c
3049 sh_sh64_register_byte (int reg_nr
)
3051 int base_regnum
= -1;
3052 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3054 /* If it is a pseudo register, get the number of the first floating
3055 point register that is part of it. */
3056 if (reg_nr
>= tdep
->DR0_REGNUM
3057 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3058 base_regnum
= dr_reg_base_num (reg_nr
);
3060 else if (reg_nr
>= tdep
->FPP0_REGNUM
3061 && reg_nr
<= tdep
->FPP_LAST_REGNUM
)
3062 base_regnum
= fpp_reg_base_num (reg_nr
);
3064 else if (reg_nr
>= tdep
->FV0_REGNUM
3065 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3066 base_regnum
= fv_reg_base_num (reg_nr
);
3068 /* sh compact pseudo register. FPSCR is a pathological case, need to
3069 treat it as special. */
3070 else if ((reg_nr
>= tdep
->R0_C_REGNUM
3071 && reg_nr
<= tdep
->FV_LAST_C_REGNUM
)
3072 && reg_nr
!= tdep
->FPSCR_C_REGNUM
)
3073 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3075 /* Now return the offset in bytes within the register cache. */
3076 /* sh media pseudo register, i.e. any of DR, FFP, FV registers. */
3077 if (reg_nr
>= tdep
->DR0_REGNUM
3078 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3079 return (base_regnum
- FP0_REGNUM
+ 1) * 4
3080 + (tdep
->TR7_REGNUM
+ 1) * 8;
3082 /* sh compact pseudo register: general register */
3083 if ((reg_nr
>= tdep
->R0_C_REGNUM
3084 && reg_nr
<= tdep
->R_LAST_C_REGNUM
))
3085 return (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3086 ? base_regnum
* 8 + 4
3089 /* sh compact pseudo register: */
3090 if (reg_nr
== tdep
->PC_C_REGNUM
3091 || reg_nr
== tdep
->GBR_C_REGNUM
3092 || reg_nr
== tdep
->MACL_C_REGNUM
3093 || reg_nr
== tdep
->PR_C_REGNUM
)
3094 return (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3095 ? base_regnum
* 8 + 4
3098 if (reg_nr
== tdep
->MACH_C_REGNUM
)
3099 return base_regnum
* 8;
3101 if (reg_nr
== tdep
->T_C_REGNUM
)
3102 return base_regnum
* 8; /* FIXME??? how do we get bit 0? Do we have to? */
3104 /* sh compact pseudo register: floating point register */
3105 else if (reg_nr
>=tdep
->FP0_C_REGNUM
3106 && reg_nr
<= tdep
->FV_LAST_C_REGNUM
)
3107 return (base_regnum
- FP0_REGNUM
) * 4
3108 + (tdep
->TR7_REGNUM
+ 1) * 8 + 4;
3110 else if (reg_nr
== tdep
->FPSCR_C_REGNUM
)
3111 /* This is complicated, for now return the beginning of the
3112 architectural FPSCR register. */
3113 return (tdep
->TR7_REGNUM
+ 1) * 8;
3115 else if (reg_nr
== tdep
->FPUL_C_REGNUM
)
3116 return ((base_regnum
- FP0_REGNUM
) * 4 +
3117 (tdep
->TR7_REGNUM
+ 1) * 8 + 4);
3119 /* It is not a pseudo register. */
3120 /* It is a 64 bit register. */
3121 else if (reg_nr
<= tdep
->TR7_REGNUM
)
3124 /* It is a 32 bit register. */
3126 if (reg_nr
== tdep
->FPSCR_REGNUM
)
3127 return (tdep
->FPSCR_REGNUM
* 8);
3129 /* It is floating point 32-bit register */
3131 return ((tdep
->TR7_REGNUM
+ 1) * 8
3132 + (reg_nr
- FP0_REGNUM
+ 1) * 4);
3135 /* Number of bytes of storage in the actual machine representation for
3138 sh_default_register_raw_size (int reg_nr
)
3144 sh_sh4_register_raw_size (int reg_nr
)
3146 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3148 if (reg_nr
>= tdep
->DR0_REGNUM
3149 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3151 else if (reg_nr
>= tdep
->FV0_REGNUM
3152 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3159 sh_sh64_register_raw_size (int reg_nr
)
3161 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3163 if ((reg_nr
>= tdep
->DR0_REGNUM
3164 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3165 || (reg_nr
>= tdep
->FPP0_REGNUM
3166 && reg_nr
<= tdep
->FPP_LAST_REGNUM
)
3167 || (reg_nr
>= tdep
->DR0_C_REGNUM
3168 && reg_nr
<= tdep
->DR_LAST_C_REGNUM
)
3169 || (reg_nr
<= tdep
->TR7_REGNUM
))
3172 else if ((reg_nr
>= tdep
->FV0_REGNUM
3173 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3174 || (reg_nr
>= tdep
->FV0_C_REGNUM
3175 && reg_nr
<= tdep
->FV_LAST_C_REGNUM
))
3178 else /* this covers also the 32-bit SH compact registers. */
3182 /* Number of bytes of storage in the program's representation
3185 sh_register_virtual_size (int reg_nr
)
3192 sh_sh64_register_virtual_size (int reg_nr
)
3194 if (reg_nr
>= FP0_REGNUM
3195 && reg_nr
<= gdbarch_tdep (current_gdbarch
)->FP_LAST_REGNUM
)
3201 /* Return the GDB type object for the "standard" data type
3202 of data in register N. */
3203 static struct type
*
3204 sh_sh3e_register_virtual_type (int reg_nr
)
3206 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3208 if ((reg_nr
>= FP0_REGNUM
3209 && (reg_nr
<= tdep
->FP_LAST_REGNUM
))
3210 || (reg_nr
== tdep
->FPUL_REGNUM
))
3211 return builtin_type_float
;
3213 return builtin_type_int
;
3216 static struct type
*
3217 sh_sh4_build_float_register_type (int high
)
3221 temp
= create_range_type (NULL
, builtin_type_int
, 0, high
);
3222 return create_array_type (NULL
, builtin_type_float
, temp
);
3225 static struct type
*
3226 sh_sh4_register_virtual_type (int reg_nr
)
3228 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3230 if ((reg_nr
>= FP0_REGNUM
3231 && (reg_nr
<= tdep
->FP_LAST_REGNUM
))
3232 || (reg_nr
== tdep
->FPUL_REGNUM
))
3233 return builtin_type_float
;
3234 else if (reg_nr
>= tdep
->DR0_REGNUM
3235 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3236 return builtin_type_double
;
3237 else if (reg_nr
>= tdep
->FV0_REGNUM
3238 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3239 return sh_sh4_build_float_register_type (3);
3241 return builtin_type_int
;
3244 static struct type
*
3245 sh_sh64_register_virtual_type (int reg_nr
)
3247 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3249 if ((reg_nr
>= FP0_REGNUM
3250 && reg_nr
<= tdep
->FP_LAST_REGNUM
)
3251 || (reg_nr
>= tdep
->FP0_C_REGNUM
3252 && reg_nr
<= tdep
->FP_LAST_C_REGNUM
))
3253 return builtin_type_float
;
3254 else if ((reg_nr
>= tdep
->DR0_REGNUM
3255 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3256 || (reg_nr
>= tdep
->DR0_C_REGNUM
3257 && reg_nr
<= tdep
->DR_LAST_C_REGNUM
))
3258 return builtin_type_double
;
3259 else if (reg_nr
>= tdep
->FPP0_REGNUM
3260 && reg_nr
<= tdep
->FPP_LAST_REGNUM
)
3261 return sh_sh4_build_float_register_type (1);
3262 else if ((reg_nr
>= tdep
->FV0_REGNUM
3263 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3264 ||(reg_nr
>= tdep
->FV0_C_REGNUM
3265 && reg_nr
<= tdep
->FV_LAST_C_REGNUM
))
3266 return sh_sh4_build_float_register_type (3);
3267 else if (reg_nr
== tdep
->FPSCR_REGNUM
)
3268 return builtin_type_int
;
3269 else if (reg_nr
>= tdep
->R0_C_REGNUM
3270 && reg_nr
< tdep
->FP0_C_REGNUM
)
3271 return builtin_type_int
;
3273 return builtin_type_long_long
;
3276 static struct type
*
3277 sh_default_register_virtual_type (int reg_nr
)
3279 return builtin_type_int
;
3282 /* On the sh4, the DRi pseudo registers are problematic if the target
3283 is little endian. When the user writes one of those registers, for
3284 instance with 'ser var $dr0=1', we want the double to be stored
3286 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
3287 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
3289 This corresponds to little endian byte order & big endian word
3290 order. However if we let gdb write the register w/o conversion, it
3291 will write fr0 and fr1 this way:
3292 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
3293 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
3294 because it will consider fr0 and fr1 as a single LE stretch of memory.
3296 To achieve what we want we must force gdb to store things in
3297 floatformat_ieee_double_littlebyte_bigword (which is defined in
3298 include/floatformat.h and libiberty/floatformat.c.
3300 In case the target is big endian, there is no problem, the
3301 raw bytes will look like:
3302 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
3303 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
3305 The other pseudo registers (the FVs) also don't pose a problem
3306 because they are stored as 4 individual FP elements. */
3309 sh_sh4_register_convert_to_virtual (int regnum
, struct type
*type
,
3310 char *from
, char *to
)
3312 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3314 if (regnum
>= tdep
->DR0_REGNUM
3315 && regnum
<= tdep
->DR_LAST_REGNUM
)
3318 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword
, from
, &val
);
3319 store_floating (to
, TYPE_LENGTH (type
), val
);
3322 error ("sh_register_convert_to_virtual called with non DR register number");
3326 sh_sh64_register_convert_to_virtual (int regnum
, struct type
*type
,
3327 char *from
, char *to
)
3329 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3331 if (TARGET_BYTE_ORDER
!= BFD_ENDIAN_LITTLE
)
3333 /* It is a no-op. */
3334 memcpy (to
, from
, REGISTER_RAW_SIZE (regnum
));
3338 if ((regnum
>= tdep
->DR0_REGNUM
3339 && regnum
<= tdep
->DR_LAST_REGNUM
)
3340 || (regnum
>= tdep
->DR0_C_REGNUM
3341 && regnum
<= tdep
->DR_LAST_C_REGNUM
))
3344 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword
, from
, &val
);
3345 store_floating(to
, TYPE_LENGTH(type
), val
);
3348 error("sh_register_convert_to_virtual called with non DR register number");
3352 sh_sh4_register_convert_to_raw (struct type
*type
, int regnum
,
3353 char *from
, char *to
)
3355 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3357 if (regnum
>= tdep
->DR0_REGNUM
3358 && regnum
<= tdep
->DR_LAST_REGNUM
)
3360 DOUBLEST val
= extract_floating (from
, TYPE_LENGTH(type
));
3361 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword
, &val
, to
);
3364 error("sh_register_convert_to_raw called with non DR register number");
3368 sh_sh64_register_convert_to_raw (struct type
*type
, int regnum
,
3369 char *from
, char *to
)
3371 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3373 if (TARGET_BYTE_ORDER
!= BFD_ENDIAN_LITTLE
)
3375 /* It is a no-op. */
3376 memcpy (to
, from
, REGISTER_RAW_SIZE (regnum
));
3380 if ((regnum
>= tdep
->DR0_REGNUM
3381 && regnum
<= tdep
->DR_LAST_REGNUM
)
3382 || (regnum
>= tdep
->DR0_C_REGNUM
3383 && regnum
<= tdep
->DR_LAST_C_REGNUM
))
3385 DOUBLEST val
= extract_floating (from
, TYPE_LENGTH(type
));
3386 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword
, &val
, to
);
3389 error("sh_register_convert_to_raw called with non DR register number");
3393 sh_pseudo_register_read (int reg_nr
, char *buffer
)
3395 int base_regnum
, portion
;
3396 char *temp_buffer
= (char*) alloca (MAX_REGISTER_RAW_SIZE
);
3397 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3399 if (reg_nr
>= tdep
->DR0_REGNUM
3400 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3402 base_regnum
= dr_reg_base_num (reg_nr
);
3404 /* Build the value in the provided buffer. */
3405 /* Read the real regs for which this one is an alias. */
3406 for (portion
= 0; portion
< 2; portion
++)
3407 regcache_read (base_regnum
+ portion
,
3409 + REGISTER_RAW_SIZE (base_regnum
) * portion
);
3410 /* We must pay attention to the endiannes. */
3411 sh_sh4_register_convert_to_virtual (reg_nr
,
3412 REGISTER_VIRTUAL_TYPE (reg_nr
),
3413 temp_buffer
, buffer
);
3415 else if (reg_nr
>= tdep
->FV0_REGNUM
3416 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3418 base_regnum
= fv_reg_base_num (reg_nr
);
3420 /* Read the real regs for which this one is an alias. */
3421 for (portion
= 0; portion
< 4; portion
++)
3422 regcache_read (base_regnum
+ portion
,
3423 buffer
+ REGISTER_RAW_SIZE (base_regnum
) * portion
);
3428 sh4_register_read (struct gdbarch
*gdbarch
, int reg_nr
, char *buffer
)
3430 if (reg_nr
>= 0 && reg_nr
< gdbarch_tdep (current_gdbarch
)->DR0_REGNUM
)
3431 /* It is a regular register. */
3432 regcache_read (reg_nr
, buffer
);
3434 /* It is a pseudo register and we need to construct its value */
3435 sh_pseudo_register_read (reg_nr
, buffer
);
3439 sh64_pseudo_register_read (int reg_nr
, char *buffer
)
3444 char *temp_buffer
= (char*) alloca (MAX_REGISTER_RAW_SIZE
);
3445 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3447 if (reg_nr
>= tdep
->DR0_REGNUM
3448 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3450 base_regnum
= dr_reg_base_num (reg_nr
);
3452 /* Build the value in the provided buffer. */
3453 /* DR regs are double precision registers obtained by
3454 concatenating 2 single precision floating point registers. */
3455 for (portion
= 0; portion
< 2; portion
++)
3456 regcache_read (base_regnum
+ portion
,
3458 + REGISTER_RAW_SIZE (base_regnum
) * portion
);
3460 /* We must pay attention to the endiannes. */
3461 sh_sh64_register_convert_to_virtual (reg_nr
, REGISTER_VIRTUAL_TYPE (reg_nr
),
3462 temp_buffer
, buffer
);
3466 else if (reg_nr
>= tdep
->FPP0_REGNUM
3467 && reg_nr
<= tdep
->FPP_LAST_REGNUM
)
3469 base_regnum
= fpp_reg_base_num (reg_nr
);
3471 /* Build the value in the provided buffer. */
3472 /* FPP regs are pairs of single precision registers obtained by
3473 concatenating 2 single precision floating point registers. */
3474 for (portion
= 0; portion
< 2; portion
++)
3475 regcache_read (base_regnum
+ portion
,
3476 buffer
+ REGISTER_RAW_SIZE (base_regnum
) * portion
);
3479 else if (reg_nr
>= tdep
->FV0_REGNUM
3480 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3482 base_regnum
= fv_reg_base_num (reg_nr
);
3484 /* Build the value in the provided buffer. */
3485 /* FV regs are vectors of single precision registers obtained by
3486 concatenating 4 single precision floating point registers. */
3487 for (portion
= 0; portion
< 4; portion
++)
3488 regcache_read (base_regnum
+ portion
,
3489 buffer
+ REGISTER_RAW_SIZE (base_regnum
) * portion
);
3492 /* sh compact pseudo registers. 1-to-1 with a shmedia register */
3493 else if (reg_nr
>= tdep
->R0_C_REGNUM
3494 && reg_nr
<= tdep
->T_C_REGNUM
)
3496 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3498 /* Build the value in the provided buffer. */
3499 regcache_read (base_regnum
, temp_buffer
);
3500 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3502 memcpy (buffer
, temp_buffer
+ offset
, 4); /* get LOWER 32 bits only????*/
3505 else if (reg_nr
>= tdep
->FP0_C_REGNUM
3506 && reg_nr
<= tdep
->FP_LAST_C_REGNUM
)
3508 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3510 /* Build the value in the provided buffer. */
3511 /* Floating point registers map 1-1 to the media fp regs,
3512 they have the same size and endienness. */
3513 regcache_read (base_regnum
, buffer
);
3516 else if (reg_nr
>= tdep
->DR0_C_REGNUM
3517 && reg_nr
<= tdep
->DR_LAST_C_REGNUM
)
3519 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3521 /* DR_C regs are double precision registers obtained by
3522 concatenating 2 single precision floating point registers. */
3523 for (portion
= 0; portion
< 2; portion
++)
3524 regcache_read (base_regnum
+ portion
,
3526 + REGISTER_RAW_SIZE (base_regnum
) * portion
);
3528 /* We must pay attention to the endiannes. */
3529 sh_sh64_register_convert_to_virtual (reg_nr
, REGISTER_VIRTUAL_TYPE (reg_nr
),
3530 temp_buffer
, buffer
);
3533 else if (reg_nr
>= tdep
->FV0_C_REGNUM
3534 && reg_nr
<= tdep
->FV_LAST_C_REGNUM
)
3536 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3538 /* Build the value in the provided buffer. */
3539 /* FV_C regs are vectors of single precision registers obtained by
3540 concatenating 4 single precision floating point registers. */
3541 for (portion
= 0; portion
< 4; portion
++)
3542 regcache_read (base_regnum
+ portion
,
3543 buffer
+ REGISTER_RAW_SIZE (base_regnum
) * portion
);
3546 else if (reg_nr
== tdep
->FPSCR_C_REGNUM
)
3548 int fpscr_base_regnum
;
3550 unsigned int fpscr_value
;
3551 unsigned int sr_value
;
3552 unsigned int fpscr_c_value
;
3553 unsigned int fpscr_c_part1_value
;
3554 unsigned int fpscr_c_part2_value
;
3556 fpscr_base_regnum
= tdep
->FPSCR_REGNUM
;
3557 sr_base_regnum
= tdep
->SR_REGNUM
;
3559 /* Build the value in the provided buffer. */
3560 /* FPSCR_C is a very weird register that contains sparse bits
3561 from the FPSCR and the SR architectural registers.
3568 2-17 Bit 2-18 of FPSCR
3569 18-20 Bits 12,13,14 of SR
3573 /* Get FPSCR into a local buffer */
3574 regcache_read (fpscr_base_regnum
, temp_buffer
);
3575 /* Get value as an int. */
3576 fpscr_value
= extract_unsigned_integer (temp_buffer
, 4);
3577 /* Get SR into a local buffer */
3578 regcache_read (sr_base_regnum
, temp_buffer
);
3579 /* Get value as an int. */
3580 sr_value
= extract_unsigned_integer (temp_buffer
, 4);
3581 /* Build the new value. */
3582 fpscr_c_part1_value
= fpscr_value
& 0x3fffd;
3583 fpscr_c_part2_value
= (sr_value
& 0x7000) << 6;
3584 fpscr_c_value
= fpscr_c_part1_value
| fpscr_c_part2_value
;
3585 /* Store that in out buffer!!! */
3586 store_unsigned_integer (buffer
, 4, fpscr_c_value
);
3587 /* FIXME There is surely an endianness gotcha here. */
3590 else if (reg_nr
== tdep
->FPUL_C_REGNUM
)
3592 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3594 /* FPUL_C register is floating point register 32,
3595 same size, same endianness. */
3596 regcache_read (base_regnum
, buffer
);
3601 sh64_register_read (struct gdbarch
*gdbarch
, int reg_nr
, char *buffer
)
3604 if (reg_nr
>= 0 && reg_nr
< gdbarch_tdep (current_gdbarch
)->DR0_REGNUM
)
3605 /* It is a regular register. */
3606 regcache_read (reg_nr
, buffer
);
3608 /* It is a pseudo register and we need to construct its value */
3609 sh64_pseudo_register_read (reg_nr
, buffer
);
3613 sh_pseudo_register_write (int reg_nr
, char *buffer
)
3615 int base_regnum
, portion
;
3616 char *temp_buffer
= (char*) alloca (MAX_REGISTER_RAW_SIZE
);
3617 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3619 if (reg_nr
>= tdep
->DR0_REGNUM
3620 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3622 base_regnum
= dr_reg_base_num (reg_nr
);
3624 /* We must pay attention to the endiannes. */
3625 sh_sh4_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr
), reg_nr
,
3626 buffer
, temp_buffer
);
3628 /* Write the real regs for which this one is an alias. */
3629 for (portion
= 0; portion
< 2; portion
++)
3630 regcache_write (base_regnum
+ portion
,
3631 temp_buffer
+ REGISTER_RAW_SIZE (base_regnum
) * portion
);
3633 else if (reg_nr
>= tdep
->FV0_REGNUM
3634 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3636 base_regnum
= fv_reg_base_num (reg_nr
);
3638 /* Write the real regs for which this one is an alias. */
3639 for (portion
= 0; portion
< 4; portion
++)
3640 regcache_write (base_regnum
+ portion
,
3641 buffer
+ REGISTER_RAW_SIZE (base_regnum
) * portion
);
3646 sh4_register_write (struct gdbarch
*gdbarch
, int reg_nr
, char *buffer
)
3648 if (reg_nr
>= 0 && reg_nr
< gdbarch_tdep (current_gdbarch
)->DR0_REGNUM
)
3649 /* It is a regular register. */
3650 regcache_write (reg_nr
, buffer
);
3652 /* It is a pseudo register and we need to construct its value */
3653 sh_pseudo_register_write (reg_nr
, buffer
);
3657 sh64_pseudo_register_write (int reg_nr
, char *buffer
)
3659 int base_regnum
, portion
;
3661 char *temp_buffer
= (char*) alloca (MAX_REGISTER_RAW_SIZE
);
3662 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3664 if (reg_nr
>= tdep
->DR0_REGNUM
3665 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3667 base_regnum
= dr_reg_base_num (reg_nr
);
3668 /* We must pay attention to the endiannes. */
3669 sh_sh64_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr
), reg_nr
,
3670 buffer
, temp_buffer
);
3673 /* Write the real regs for which this one is an alias. */
3674 for (portion
= 0; portion
< 2; portion
++)
3675 regcache_write (base_regnum
+ portion
,
3676 temp_buffer
+ REGISTER_RAW_SIZE (base_regnum
) * portion
);
3679 else if (reg_nr
>= tdep
->FPP0_REGNUM
3680 && reg_nr
<= tdep
->FPP_LAST_REGNUM
)
3682 base_regnum
= fpp_reg_base_num (reg_nr
);
3684 /* Write the real regs for which this one is an alias. */
3685 for (portion
= 0; portion
< 2; portion
++)
3686 regcache_write (base_regnum
+ portion
,
3687 buffer
+ REGISTER_RAW_SIZE (base_regnum
) * portion
);
3690 else if (reg_nr
>= tdep
->FV0_REGNUM
3691 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3693 base_regnum
= fv_reg_base_num (reg_nr
);
3695 /* Write the real regs for which this one is an alias. */
3696 for (portion
= 0; portion
< 4; portion
++)
3697 regcache_write (base_regnum
+ portion
,
3698 buffer
+ REGISTER_RAW_SIZE (base_regnum
) * portion
);
3701 /* sh compact general pseudo registers. 1-to-1 with a shmedia
3702 register but only 4 bytes of it. */
3703 else if (reg_nr
>= tdep
->R0_C_REGNUM
3704 && reg_nr
<= tdep
->T_C_REGNUM
)
3706 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3707 /* reg_nr is 32 bit here, and base_regnum is 64 bits. */
3708 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3712 /* Let's read the value of the base register into a temporary
3713 buffer, so that overwriting the last four bytes with the new
3714 value of the pseudo will leave the upper 4 bytes unchanged. */
3715 regcache_read (base_regnum
, temp_buffer
);
3716 /* Write as an 8 byte quantity */
3717 memcpy (temp_buffer
+ offset
, buffer
, 4);
3718 regcache_write (base_regnum
, temp_buffer
);
3721 /* sh floating point compact pseudo registers. 1-to-1 with a shmedia
3722 registers. Both are 4 bytes. */
3723 else if (reg_nr
>= tdep
->FP0_C_REGNUM
3724 && reg_nr
<= tdep
->FP_LAST_C_REGNUM
)
3726 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3727 regcache_write (base_regnum
, buffer
);
3730 else if (reg_nr
>= tdep
->DR0_C_REGNUM
3731 && reg_nr
<= tdep
->DR_LAST_C_REGNUM
)
3733 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3734 for (portion
= 0; portion
< 2; portion
++)
3736 /* We must pay attention to the endiannes. */
3737 sh_sh64_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr
), reg_nr
,
3738 buffer
, temp_buffer
);
3740 regcache_write (base_regnum
+ portion
,
3741 temp_buffer
+ REGISTER_RAW_SIZE (base_regnum
) * portion
);
3745 else if (reg_nr
>= tdep
->FV0_C_REGNUM
3746 && reg_nr
<= tdep
->FV_LAST_C_REGNUM
)
3748 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3750 for (portion
= 0; portion
< 4; portion
++)
3752 regcache_write (base_regnum
+ portion
,
3753 buffer
+ REGISTER_RAW_SIZE (base_regnum
) * portion
);
3757 else if (reg_nr
== tdep
->FPSCR_C_REGNUM
)
3759 int fpscr_base_regnum
;
3761 unsigned int fpscr_value
;
3762 unsigned int sr_value
;
3763 unsigned int old_fpscr_value
;
3764 unsigned int old_sr_value
;
3765 unsigned int fpscr_c_value
;
3766 unsigned int fpscr_mask
;
3767 unsigned int sr_mask
;
3769 fpscr_base_regnum
= tdep
->FPSCR_REGNUM
;
3770 sr_base_regnum
= tdep
->SR_REGNUM
;
3772 /* FPSCR_C is a very weird register that contains sparse bits
3773 from the FPSCR and the SR architectural registers.
3780 2-17 Bit 2-18 of FPSCR
3781 18-20 Bits 12,13,14 of SR
3785 /* Get value as an int. */
3786 fpscr_c_value
= extract_unsigned_integer (buffer
, 4);
3788 /* Build the new values. */
3789 fpscr_mask
= 0x0003fffd;
3790 sr_mask
= 0x001c0000;
3792 fpscr_value
= fpscr_c_value
& fpscr_mask
;
3793 sr_value
= (fpscr_value
& sr_mask
) >> 6;
3795 regcache_read (fpscr_base_regnum
, temp_buffer
);
3796 old_fpscr_value
= extract_unsigned_integer (temp_buffer
, 4);
3797 old_fpscr_value
&= 0xfffc0002;
3798 fpscr_value
|= old_fpscr_value
;
3799 store_unsigned_integer (temp_buffer
, 4, fpscr_value
);
3800 regcache_write (fpscr_base_regnum
, temp_buffer
);
3802 regcache_read (sr_base_regnum
, temp_buffer
);
3803 old_sr_value
= extract_unsigned_integer (temp_buffer
, 4);
3804 old_sr_value
&= 0xffff8fff;
3805 sr_value
|= old_sr_value
;
3806 store_unsigned_integer (temp_buffer
, 4, sr_value
);
3807 regcache_write (sr_base_regnum
, temp_buffer
);
3810 else if (reg_nr
== tdep
->FPUL_C_REGNUM
)
3812 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3813 regcache_write (base_regnum
, buffer
);
3818 sh64_register_write (struct gdbarch
*gdbarch
, int reg_nr
, char *buffer
)
3820 if (reg_nr
>= 0 && reg_nr
< gdbarch_tdep (current_gdbarch
)->DR0_REGNUM
)
3821 /* It is a regular register. */
3822 regcache_write (reg_nr
, buffer
);
3824 /* It is a pseudo register and we need to construct its value */
3825 sh64_pseudo_register_write (reg_nr
, buffer
);
3828 /* Floating point vector of 4 float registers. */
3830 do_fv_register_info (int fv_regnum
)
3832 int first_fp_reg_num
= fv_reg_base_num (fv_regnum
);
3833 printf_filtered ("fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
3834 fv_regnum
- gdbarch_tdep (current_gdbarch
)->FV0_REGNUM
,
3835 (int) read_register (first_fp_reg_num
),
3836 (int) read_register (first_fp_reg_num
+ 1),
3837 (int) read_register (first_fp_reg_num
+ 2),
3838 (int) read_register (first_fp_reg_num
+ 3));
3841 /* Floating point vector of 4 float registers, compact mode. */
3843 do_fv_c_register_info (int fv_regnum
)
3845 int first_fp_reg_num
= sh64_compact_reg_base_num (fv_regnum
);
3846 printf_filtered ("fv%d_c\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
3847 fv_regnum
- gdbarch_tdep (current_gdbarch
)->FV0_C_REGNUM
,
3848 (int) read_register (first_fp_reg_num
),
3849 (int) read_register (first_fp_reg_num
+ 1),
3850 (int) read_register (first_fp_reg_num
+ 2),
3851 (int) read_register (first_fp_reg_num
+ 3));
3854 /* Pairs of single regs. The DR are instead double precision
3857 do_fpp_register_info (int fpp_regnum
)
3859 int first_fp_reg_num
= fpp_reg_base_num (fpp_regnum
);
3861 printf_filtered ("fpp%d\t0x%08x\t0x%08x\n",
3862 fpp_regnum
- gdbarch_tdep (current_gdbarch
)->FPP0_REGNUM
,
3863 (int) read_register (first_fp_reg_num
),
3864 (int) read_register (first_fp_reg_num
+ 1));
3867 /* Double precision registers. */
3869 do_dr_register_info (int dr_regnum
)
3871 int first_fp_reg_num
= dr_reg_base_num (dr_regnum
);
3873 printf_filtered ("dr%d\t0x%08x%08x\n",
3874 dr_regnum
- gdbarch_tdep (current_gdbarch
)->DR0_REGNUM
,
3875 (int) read_register (first_fp_reg_num
),
3876 (int) read_register (first_fp_reg_num
+ 1));
3879 /* Double precision registers, compact mode. */
3881 do_dr_c_register_info (int dr_regnum
)
3883 int first_fp_reg_num
= sh64_compact_reg_base_num (dr_regnum
);
3885 printf_filtered ("dr%d_c\t0x%08x%08x\n",
3886 dr_regnum
- gdbarch_tdep (current_gdbarch
)->DR0_C_REGNUM
,
3887 (int) read_register (first_fp_reg_num
),
3888 (int) read_register (first_fp_reg_num
+1));
3891 /* General register in compact mode. */
3893 do_r_c_register_info (int r_c_regnum
)
3895 int regnum
= sh64_compact_reg_base_num (r_c_regnum
);
3897 printf_filtered ("r%d_c\t0x%08x\n",
3898 r_c_regnum
- gdbarch_tdep (current_gdbarch
)->R0_C_REGNUM
,
3899 /*FIXME!!!*/ (int) read_register (regnum
));
3902 /* FIXME:!! THIS SHOULD TAKE CARE OF GETTING THE RIGHT PORTION OF THE
3903 shmedia REGISTERS. */
3904 /* Control registers, compact mode. */
3906 do_cr_c_register_info (int cr_c_regnum
)
3908 switch (cr_c_regnum
)
3910 case 237: printf_filtered ("pc_c\t0x%08x\n", (int) read_register (cr_c_regnum
));
3912 case 238: printf_filtered ("gbr_c\t0x%08x\n", (int) read_register (cr_c_regnum
));
3914 case 239: printf_filtered ("mach_c\t0x%08x\n", (int) read_register (cr_c_regnum
));
3916 case 240: printf_filtered ("macl_c\t0x%08x\n", (int) read_register (cr_c_regnum
));
3918 case 241: printf_filtered ("pr_c\t0x%08x\n", (int) read_register (cr_c_regnum
));
3920 case 242: printf_filtered ("t_c\t0x%08x\n", (int) read_register (cr_c_regnum
));
3922 case 243: printf_filtered ("fpscr_c\t0x%08x\n", (int) read_register (cr_c_regnum
));
3924 case 244: printf_filtered ("fpul_c\t0x%08x\n", (int)read_register (cr_c_regnum
));
3930 sh_do_pseudo_register (int regnum
)
3932 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3934 if (regnum
< NUM_REGS
|| regnum
>= NUM_REGS
+ NUM_PSEUDO_REGS
)
3935 internal_error (__FILE__
, __LINE__
,
3936 "Invalid pseudo register number %d\n", regnum
);
3937 else if (regnum
>= tdep
->DR0_REGNUM
3938 && regnum
< tdep
->DR_LAST_REGNUM
)
3939 do_dr_register_info (regnum
);
3940 else if (regnum
>= tdep
->FV0_REGNUM
3941 && regnum
<= tdep
->FV_LAST_REGNUM
)
3942 do_fv_register_info (regnum
);
3946 sh_do_fp_register (int regnum
)
3947 { /* do values for FP (float) regs */
3949 double flt
; /* double extracted from raw hex data */
3953 /* Allocate space for the float. */
3954 raw_buffer
= (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
3956 /* Get the data in raw format. */
3957 if (!frame_register_read (selected_frame
, regnum
, raw_buffer
))
3958 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
3960 /* Get the register as a number */
3961 flt
= unpack_double (builtin_type_float
, raw_buffer
, &inv
);
3963 /* Print the name and some spaces. */
3964 fputs_filtered (REGISTER_NAME (regnum
), gdb_stdout
);
3965 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum
)), gdb_stdout
);
3967 /* Print the value. */
3969 printf_filtered ("<invalid float>");
3971 printf_filtered ("%-10.9g", flt
);
3973 /* Print the fp register as hex. */
3974 printf_filtered ("\t(raw 0x");
3975 for (j
= 0; j
< REGISTER_RAW_SIZE (regnum
); j
++)
3977 register int idx
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? j
3978 : REGISTER_RAW_SIZE (regnum
) - 1 - j
;
3979 printf_filtered ("%02x", (unsigned char) raw_buffer
[idx
]);
3981 printf_filtered (")");
3982 printf_filtered ("\n");
3986 sh64_do_pseudo_register (int regnum
)
3988 /* All the sh64-compact mode registers are pseudo registers. */
3989 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3991 if (regnum
< NUM_REGS
3992 || regnum
>= NUM_REGS
+ NUM_PSEUDO_REGS_SH_MEDIA
+ NUM_PSEUDO_REGS_SH_COMPACT
)
3993 internal_error (__FILE__
, __LINE__
,
3994 "Invalid pseudo register number %d\n", regnum
);
3996 else if ((regnum
>= tdep
->DR0_REGNUM
3997 && regnum
<= tdep
->DR_LAST_REGNUM
))
3998 do_dr_register_info (regnum
);
4000 else if ((regnum
>= tdep
->DR0_C_REGNUM
4001 && regnum
<= tdep
->DR_LAST_C_REGNUM
))
4002 do_dr_c_register_info (regnum
);
4004 else if ((regnum
>= tdep
->FV0_REGNUM
4005 && regnum
<= tdep
->FV_LAST_REGNUM
))
4006 do_fv_register_info (regnum
);
4008 else if ((regnum
>= tdep
->FV0_C_REGNUM
4009 && regnum
<= tdep
->FV_LAST_C_REGNUM
))
4010 do_fv_c_register_info (regnum
);
4012 else if (regnum
>= tdep
->FPP0_REGNUM
4013 && regnum
<= tdep
->FPP_LAST_REGNUM
)
4014 do_fpp_register_info (regnum
);
4016 else if (regnum
>= tdep
->R0_C_REGNUM
4017 && regnum
<= tdep
->R_LAST_C_REGNUM
)
4018 do_r_c_register_info (regnum
); /* FIXME, this function will not print the right format */
4020 else if (regnum
>= tdep
->FP0_C_REGNUM
4021 && regnum
<= tdep
->FP_LAST_C_REGNUM
)
4022 sh_do_fp_register (regnum
); /* this should work also for pseudoregs */
4024 else if (regnum
>= tdep
->PC_C_REGNUM
4025 && regnum
<= tdep
->FPUL_C_REGNUM
)
4026 do_cr_c_register_info (regnum
);
4031 sh_do_register (int regnum
)
4033 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
4035 fputs_filtered (REGISTER_NAME (regnum
), gdb_stdout
);
4036 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum
)), gdb_stdout
);
4038 /* Get the data in raw format. */
4039 if (!frame_register_read (selected_frame
, regnum
, raw_buffer
))
4040 printf_filtered ("*value not available*\n");
4042 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0, 0,
4043 gdb_stdout
, 'x', 1, 0, Val_pretty_default
);
4044 printf_filtered ("\t");
4045 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0, 0,
4046 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
4047 printf_filtered ("\n");
4051 sh_print_register (int regnum
)
4053 if (regnum
< 0 || regnum
>= NUM_REGS
+ NUM_PSEUDO_REGS
)
4054 internal_error (__FILE__
, __LINE__
,
4055 "Invalid register number %d\n", regnum
);
4057 else if (regnum
>= 0 && regnum
< NUM_REGS
)
4059 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
4060 sh_do_fp_register (regnum
); /* FP regs */
4062 sh_do_register (regnum
); /* All other regs */
4065 else if (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
4066 do_pseudo_register (regnum
);
4070 sh_do_registers_info (int regnum
, int fpregs
)
4072 if (regnum
!= -1) /* do one specified register */
4074 if (*(REGISTER_NAME (regnum
)) == '\0')
4075 error ("Not a valid register for the current processor type");
4077 sh_print_register (regnum
);
4080 /* do all (or most) registers */
4083 while (regnum
< NUM_REGS
)
4085 /* If the register name is empty, it is undefined for this
4086 processor, so don't display anything. */
4087 if (REGISTER_NAME (regnum
) == NULL
4088 || *(REGISTER_NAME (regnum
)) == '\0')
4094 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
4098 /* true for "INFO ALL-REGISTERS" command */
4099 sh_do_fp_register (regnum
); /* FP regs */
4103 regnum
+= (gdbarch_tdep (current_gdbarch
)->FP_LAST_REGNUM
- FP0_REGNUM
); /* skip FP regs */
4107 sh_do_register (regnum
); /* All other regs */
4113 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
4115 do_pseudo_register (regnum
);
4122 sh_compact_do_registers_info (int regnum
, int fpregs
)
4124 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4125 if (regnum
!= -1) /* do one specified register */
4127 if (*(REGISTER_NAME (regnum
)) == '\0')
4128 error ("Not a valid register for the current processor type");
4130 if (regnum
>= 0 && regnum
< tdep
->R0_C_REGNUM
)
4131 error ("Not a valid register for the current processor mode.");
4133 sh_print_register (regnum
);
4136 /* do all compact registers */
4138 regnum
= tdep
->R0_C_REGNUM
;
4139 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
4141 do_pseudo_register (regnum
);
4148 sh64_do_registers_info (int regnum
, int fpregs
)
4150 if (pc_is_isa32 (selected_frame
->pc
))
4151 sh_do_registers_info (regnum
, fpregs
);
4153 sh_compact_do_registers_info (regnum
, fpregs
);
4156 #ifdef SVR4_SHARED_LIBS
4158 /* Fetch (and possibly build) an appropriate link_map_offsets structure
4159 for native i386 linux targets using the struct offsets defined in
4160 link.h (but without actual reference to that file).
4162 This makes it possible to access i386-linux shared libraries from
4163 a gdb that was not built on an i386-linux host (for cross debugging).
4166 struct link_map_offsets
*
4167 sh_linux_svr4_fetch_link_map_offsets (void)
4169 static struct link_map_offsets lmo
;
4170 static struct link_map_offsets
*lmp
= 0;
4176 lmo
.r_debug_size
= 8; /* 20 not actual size but all we need */
4178 lmo
.r_map_offset
= 4;
4181 lmo
.link_map_size
= 20; /* 552 not actual size but all we need */
4183 lmo
.l_addr_offset
= 0;
4184 lmo
.l_addr_size
= 4;
4186 lmo
.l_name_offset
= 4;
4187 lmo
.l_name_size
= 4;
4189 lmo
.l_next_offset
= 12;
4190 lmo
.l_next_size
= 4;
4192 lmo
.l_prev_offset
= 16;
4193 lmo
.l_prev_size
= 4;
4198 #endif /* SVR4_SHARED_LIBS */
4201 /* This table matches the indices assigned to enum sh_osabi. Keep
4203 static const char * const sh_osabi_names
[] =
4212 process_note_abi_tag_sections (bfd
*abfd
, asection
*sect
, void *obj
)
4214 enum sh_osabi
*os_ident_ptr
= obj
;
4216 unsigned int sectsize
;
4218 name
= bfd_get_section_name (abfd
, sect
);
4219 sectsize
= bfd_section_size (abfd
, sect
);
4221 if (strcmp (name
, ".note.ABI-tag") == 0 && sectsize
> 0)
4223 unsigned int name_length
, data_length
, note_type
;
4226 /* If the section is larger than this, it's probably not what we are
4231 note
= alloca (sectsize
);
4233 bfd_get_section_contents (abfd
, sect
, note
,
4234 (file_ptr
) 0, (bfd_size_type
) sectsize
);
4236 name_length
= bfd_h_get_32 (abfd
, note
);
4237 data_length
= bfd_h_get_32 (abfd
, note
+ 4);
4238 note_type
= bfd_h_get_32 (abfd
, note
+ 8);
4240 if (name_length
== 4 && data_length
== 16 && note_type
== NT_GNU_ABI_TAG
4241 && strcmp (note
+ 12, "GNU") == 0)
4243 int os_number
= bfd_h_get_32 (abfd
, note
+ 16);
4245 /* The case numbers are from abi-tags in glibc. */
4248 case GNU_ABI_TAG_LINUX
:
4249 *os_ident_ptr
= SH_OSABI_LINUX
;
4252 case GNU_ABI_TAG_HURD
:
4254 (__FILE__
, __LINE__
,
4255 "process_note_abi_sections: Hurd objects not supported");
4258 case GNU_ABI_TAG_SOLARIS
:
4260 (__FILE__
, __LINE__
,
4261 "process_note_abi_sections: Solaris objects not supported");
4266 (__FILE__
, __LINE__
,
4267 "process_note_abi_sections: unknown OS number %d",
4272 /* NetBSD uses a similar trick. */
4273 else if (strcmp (name
, ".note.netbsd.ident") == 0 && sectsize
> 0)
4275 unsigned int name_length
, desc_length
, note_type
;
4278 /* If the section is larger than this, it's probably not what we are
4283 note
= alloca (sectsize
);
4285 bfd_get_section_contents (abfd
, sect
, note
,
4286 (file_ptr
) 0, (bfd_size_type
) sectsize
);
4288 name_length
= bfd_h_get_32 (abfd
, note
);
4289 desc_length
= bfd_h_get_32 (abfd
, note
+ 4);
4290 note_type
= bfd_h_get_32 (abfd
, note
+ 8);
4292 if (name_length
== 7 && desc_length
== 4 && note_type
== NT_NETBSD_IDENT
4293 && strcmp (note
+ 12, "NetBSD") == 0)
4294 /* XXX Should we check the version here?
4295 Probably not necessary yet. */
4296 *os_ident_ptr
= SH_OSABI_NETBSD_ELF
;
4301 get_elfosabi (bfd
*abfd
)
4304 enum sh_osabi sh_osabi
= SH_OSABI_UNKNOWN
;
4306 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
4311 /* When elfosabi is 0 (ELFOSABI_NONE), this is supposed to indicate
4312 that we're on a SYSV system. However, some systems use note sections
4313 to record OS/ABI info, but leave e_ident[EI_OSABI] zero. So we
4314 have to check the note sections too. */
4315 bfd_map_over_sections (abfd
,
4316 process_note_abi_tag_sections
,
4320 case ELFOSABI_NETBSD
:
4321 sh_osabi
= SH_OSABI_NETBSD_ELF
;
4324 case ELFOSABI_LINUX
:
4325 sh_osabi
= SH_OSABI_LINUX
;
4332 struct sh_osabi_handler
4334 struct sh_osabi_handler
*next
;
4336 void (*init_osabi
)(struct gdbarch_info
, struct gdbarch
*);
4339 struct sh_osabi_handler
*sh_osabi_handler_list
= NULL
;
4342 sh_gdbarch_register_os_abi (enum sh_osabi abi
,
4343 void (*init_osabi
)(struct gdbarch_info
,
4346 struct sh_osabi_handler
**handler_p
;
4348 for (handler_p
= &sh_osabi_handler_list
; *handler_p
!= NULL
;
4349 handler_p
= &(*handler_p
)->next
)
4351 if ((*handler_p
)->abi
== abi
)
4354 (__FILE__
, __LINE__
,
4355 "sh_gdbarch_register_os_abi: A handler for this ABI variant "
4356 "(%d) has already been registered", (int) abi
);
4357 /* If user wants to continue, override previous definition. */
4358 (*handler_p
)->init_osabi
= init_osabi
;
4364 = (struct sh_osabi_handler
*) xmalloc (sizeof (struct sh_osabi_handler
));
4365 (*handler_p
)->next
= NULL
;
4366 (*handler_p
)->abi
= abi
;
4367 (*handler_p
)->init_osabi
= init_osabi
;
4370 static gdbarch_init_ftype sh_gdbarch_init
;
4372 static struct gdbarch
*
4373 sh_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
4375 static LONGEST sh_call_dummy_words
[] = {0};
4376 struct gdbarch
*gdbarch
;
4377 struct gdbarch_tdep
*tdep
;
4378 gdbarch_register_name_ftype
*sh_register_name
;
4379 gdbarch_store_return_value_ftype
*sh_store_return_value
;
4380 gdbarch_register_virtual_type_ftype
*sh_register_virtual_type
;
4381 enum sh_osabi sh_osabi
= SH_OSABI_UNKNOWN
;
4382 struct sh_osabi_handler
*osabi_handler
;
4384 /* Try to determine the ABI of the object we are loading. */
4386 if (info
.abfd
!= NULL
)
4388 switch (bfd_get_flavour (info
.abfd
))
4390 case bfd_target_elf_flavour
:
4391 sh_osabi
= get_elfosabi (info
.abfd
);
4395 /* Just leave it as "unkown". */
4400 /* Find a candidate among the list of pre-declared architectures. */
4401 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
4403 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
4405 /* Make sure the ABI selection matches. */
4406 tdep
= gdbarch_tdep (arches
->gdbarch
);
4407 if (tdep
&& tdep
->sh_osabi
== sh_osabi
)
4408 return arches
->gdbarch
;
4411 /* None found, create a new architecture from the information
4413 tdep
= XMALLOC (struct gdbarch_tdep
);
4414 gdbarch
= gdbarch_alloc (&info
, tdep
);
4416 tdep
->sh_osabi
= sh_osabi
;
4417 if (sh_osabi
< SH_OSABI_INVALID
)
4418 tdep
->osabi_name
= sh_osabi_names
[sh_osabi
];
4421 internal_error (__FILE__
, __LINE__
, "Invalid setting of sh_osabi %d",
4423 tdep
->osabi_name
= "<invalid>";
4426 /* Initialize the register numbers that are not common to all the
4427 variants to -1, if necessary thse will be overwritten in the case
4429 tdep
->FPUL_REGNUM
= -1;
4430 tdep
->FPSCR_REGNUM
= -1;
4431 tdep
->PR_REGNUM
= 17;
4432 tdep
->SR_REGNUM
= 22;
4433 tdep
->DSR_REGNUM
= -1;
4434 tdep
->FP_LAST_REGNUM
= -1;
4435 tdep
->A0G_REGNUM
= -1;
4436 tdep
->A0_REGNUM
= -1;
4437 tdep
->A1G_REGNUM
= -1;
4438 tdep
->A1_REGNUM
= -1;
4439 tdep
->M0_REGNUM
= -1;
4440 tdep
->M1_REGNUM
= -1;
4441 tdep
->X0_REGNUM
= -1;
4442 tdep
->X1_REGNUM
= -1;
4443 tdep
->Y0_REGNUM
= -1;
4444 tdep
->Y1_REGNUM
= -1;
4445 tdep
->MOD_REGNUM
= -1;
4446 tdep
->RS_REGNUM
= -1;
4447 tdep
->RE_REGNUM
= -1;
4448 tdep
->SSR_REGNUM
= -1;
4449 tdep
->SPC_REGNUM
= -1;
4450 tdep
->DR0_REGNUM
= -1;
4451 tdep
->DR_LAST_REGNUM
= -1;
4452 tdep
->FV0_REGNUM
= -1;
4453 tdep
->FV_LAST_REGNUM
= -1;
4454 tdep
->ARG0_REGNUM
= 4;
4455 tdep
->ARGLAST_REGNUM
= 7;
4456 tdep
->RETURN_REGNUM
= 0;
4457 tdep
->FLOAT_ARGLAST_REGNUM
= -1;
4459 tdep
->sh_abi
= SH_ABI_UNKNOWN
;
4461 set_gdbarch_fp0_regnum (gdbarch
, -1);
4462 set_gdbarch_num_pseudo_regs (gdbarch
, 0);
4463 set_gdbarch_max_register_raw_size (gdbarch
, 4);
4464 set_gdbarch_max_register_virtual_size (gdbarch
, 4);
4465 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
4466 set_gdbarch_ptr_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
4467 set_gdbarch_num_regs (gdbarch
, SH_DEFAULT_NUM_REGS
);
4468 set_gdbarch_sp_regnum (gdbarch
, 15);
4469 set_gdbarch_fp_regnum (gdbarch
, 14);
4470 set_gdbarch_pc_regnum (gdbarch
, 16);
4471 set_gdbarch_register_size (gdbarch
, 4);
4472 set_gdbarch_register_bytes (gdbarch
, SH_DEFAULT_NUM_REGS
* 4);
4473 set_gdbarch_do_registers_info (gdbarch
, sh_do_registers_info
);
4474 set_gdbarch_breakpoint_from_pc (gdbarch
, sh_breakpoint_from_pc
);
4475 set_gdbarch_frame_chain (gdbarch
, sh_frame_chain
);
4476 set_gdbarch_get_saved_register (gdbarch
, generic_get_saved_register
);
4477 set_gdbarch_init_extra_frame_info (gdbarch
, sh_init_extra_frame_info
);
4478 set_gdbarch_extract_return_value (gdbarch
, sh_extract_return_value
);
4479 set_gdbarch_push_arguments (gdbarch
, sh_push_arguments
);
4480 set_gdbarch_store_struct_return (gdbarch
, sh_store_struct_return
);
4481 set_gdbarch_use_struct_convention (gdbarch
, sh_use_struct_convention
);
4482 set_gdbarch_extract_struct_value_address (gdbarch
, sh_extract_struct_value_address
);
4483 set_gdbarch_pop_frame (gdbarch
, sh_pop_frame
);
4484 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_sh
);
4485 skip_prologue_hard_way
= sh_skip_prologue_hard_way
;
4486 do_pseudo_register
= sh_do_pseudo_register
;
4488 switch (info
.bfd_arch_info
->mach
)
4491 sh_register_name
= sh_sh_register_name
;
4492 sh_show_regs
= sh_generic_show_regs
;
4493 sh_store_return_value
= sh_default_store_return_value
;
4494 sh_register_virtual_type
= sh_default_register_virtual_type
;
4495 set_gdbarch_frame_init_saved_regs (gdbarch
, sh_nofp_frame_init_saved_regs
);
4496 set_gdbarch_register_raw_size (gdbarch
, sh_default_register_raw_size
);
4497 set_gdbarch_register_virtual_size (gdbarch
, sh_default_register_raw_size
);
4498 set_gdbarch_register_byte (gdbarch
, sh_default_register_byte
);
4501 sh_register_name
= sh_sh_register_name
;
4502 sh_show_regs
= sh_generic_show_regs
;
4503 sh_store_return_value
= sh_default_store_return_value
;
4504 sh_register_virtual_type
= sh_default_register_virtual_type
;
4505 set_gdbarch_frame_init_saved_regs (gdbarch
, sh_nofp_frame_init_saved_regs
);
4506 set_gdbarch_register_raw_size (gdbarch
, sh_default_register_raw_size
);
4507 set_gdbarch_register_virtual_size (gdbarch
, sh_default_register_raw_size
);
4508 set_gdbarch_register_byte (gdbarch
, sh_default_register_byte
);
4510 case bfd_mach_sh_dsp
:
4511 sh_register_name
= sh_sh_dsp_register_name
;
4512 sh_show_regs
= sh_dsp_show_regs
;
4513 sh_store_return_value
= sh_default_store_return_value
;
4514 sh_register_virtual_type
= sh_default_register_virtual_type
;
4515 set_gdbarch_frame_init_saved_regs (gdbarch
, sh_nofp_frame_init_saved_regs
);
4516 set_gdbarch_register_raw_size (gdbarch
, sh_default_register_raw_size
);
4517 set_gdbarch_register_virtual_size (gdbarch
, sh_default_register_raw_size
);
4518 set_gdbarch_register_byte (gdbarch
, sh_default_register_byte
);
4519 tdep
->DSR_REGNUM
= 24;
4520 tdep
->A0G_REGNUM
= 25;
4521 tdep
->A0_REGNUM
= 26;
4522 tdep
->A1G_REGNUM
= 27;
4523 tdep
->A1_REGNUM
= 28;
4524 tdep
->M0_REGNUM
= 29;
4525 tdep
->M1_REGNUM
= 30;
4526 tdep
->X0_REGNUM
= 31;
4527 tdep
->X1_REGNUM
= 32;
4528 tdep
->Y0_REGNUM
= 33;
4529 tdep
->Y1_REGNUM
= 34;
4530 tdep
->MOD_REGNUM
= 40;
4531 tdep
->RS_REGNUM
= 43;
4532 tdep
->RE_REGNUM
= 44;
4535 sh_register_name
= sh_sh3_register_name
;
4536 sh_show_regs
= sh3_show_regs
;
4537 sh_store_return_value
= sh_default_store_return_value
;
4538 sh_register_virtual_type
= sh_default_register_virtual_type
;
4539 set_gdbarch_frame_init_saved_regs (gdbarch
, sh_nofp_frame_init_saved_regs
);
4540 set_gdbarch_register_raw_size (gdbarch
, sh_default_register_raw_size
);
4541 set_gdbarch_register_virtual_size (gdbarch
, sh_default_register_raw_size
);
4542 set_gdbarch_register_byte (gdbarch
, sh_default_register_byte
);
4543 tdep
->SSR_REGNUM
= 41;
4544 tdep
->SPC_REGNUM
= 42;
4547 sh_register_name
= sh_sh3e_register_name
;
4548 sh_show_regs
= sh3e_show_regs
;
4549 sh_store_return_value
= sh3e_sh4_store_return_value
;
4550 sh_register_virtual_type
= sh_sh3e_register_virtual_type
;
4551 set_gdbarch_frame_init_saved_regs (gdbarch
, sh_fp_frame_init_saved_regs
);
4552 set_gdbarch_register_raw_size (gdbarch
, sh_default_register_raw_size
);
4553 set_gdbarch_register_virtual_size (gdbarch
, sh_default_register_raw_size
);
4554 set_gdbarch_register_byte (gdbarch
, sh_default_register_byte
);
4555 set_gdbarch_extract_return_value (gdbarch
, sh3e_sh4_extract_return_value
);
4556 set_gdbarch_fp0_regnum (gdbarch
, 25);
4557 tdep
->FPUL_REGNUM
= 23;
4558 tdep
->FPSCR_REGNUM
= 24;
4559 tdep
->FP_LAST_REGNUM
= 40;
4560 tdep
->SSR_REGNUM
= 41;
4561 tdep
->SPC_REGNUM
= 42;
4563 case bfd_mach_sh3_dsp
:
4564 sh_register_name
= sh_sh3_dsp_register_name
;
4565 sh_show_regs
= sh3_dsp_show_regs
;
4566 sh_store_return_value
= sh_default_store_return_value
;
4567 sh_register_virtual_type
= sh_default_register_virtual_type
;
4568 set_gdbarch_frame_init_saved_regs (gdbarch
, sh_nofp_frame_init_saved_regs
);
4569 set_gdbarch_register_raw_size (gdbarch
, sh_default_register_raw_size
);
4570 set_gdbarch_register_virtual_size (gdbarch
, sh_default_register_raw_size
);
4571 set_gdbarch_register_byte (gdbarch
, sh_default_register_byte
);
4572 tdep
->DSR_REGNUM
= 24;
4573 tdep
->A0G_REGNUM
= 25;
4574 tdep
->A0_REGNUM
= 26;
4575 tdep
->A1G_REGNUM
= 27;
4576 tdep
->A1_REGNUM
= 28;
4577 tdep
->M0_REGNUM
= 29;
4578 tdep
->M1_REGNUM
= 30;
4579 tdep
->X0_REGNUM
= 31;
4580 tdep
->X1_REGNUM
= 32;
4581 tdep
->Y0_REGNUM
= 33;
4582 tdep
->Y1_REGNUM
= 34;
4583 tdep
->MOD_REGNUM
= 40;
4584 tdep
->RS_REGNUM
= 43;
4585 tdep
->RE_REGNUM
= 44;
4586 tdep
->SSR_REGNUM
= 41;
4587 tdep
->SPC_REGNUM
= 42;
4590 sh_register_name
= sh_sh4_register_name
;
4591 sh_show_regs
= sh4_show_regs
;
4592 sh_store_return_value
= sh3e_sh4_store_return_value
;
4593 sh_register_virtual_type
= sh_sh4_register_virtual_type
;
4594 set_gdbarch_frame_init_saved_regs (gdbarch
, sh_fp_frame_init_saved_regs
);
4595 set_gdbarch_extract_return_value (gdbarch
, sh3e_sh4_extract_return_value
);
4596 set_gdbarch_fp0_regnum (gdbarch
, 25);
4597 set_gdbarch_register_raw_size (gdbarch
, sh_sh4_register_raw_size
);
4598 set_gdbarch_register_virtual_size (gdbarch
, sh_sh4_register_raw_size
);
4599 set_gdbarch_register_byte (gdbarch
, sh_sh4_register_byte
);
4600 set_gdbarch_num_pseudo_regs (gdbarch
, 12);
4601 set_gdbarch_max_register_raw_size (gdbarch
, 4 * 4);
4602 set_gdbarch_max_register_virtual_size (gdbarch
, 4 * 4);
4603 set_gdbarch_register_read (gdbarch
, sh4_register_read
);
4604 set_gdbarch_register_write (gdbarch
, sh4_register_write
);
4605 tdep
->FPUL_REGNUM
= 23;
4606 tdep
->FPSCR_REGNUM
= 24;
4607 tdep
->FP_LAST_REGNUM
= 40;
4608 tdep
->SSR_REGNUM
= 41;
4609 tdep
->SPC_REGNUM
= 42;
4610 tdep
->DR0_REGNUM
= 59;
4611 tdep
->DR_LAST_REGNUM
= 66;
4612 tdep
->FV0_REGNUM
= 67;
4613 tdep
->FV_LAST_REGNUM
= 70;
4616 tdep
->PR_REGNUM
= 18;
4617 tdep
->SR_REGNUM
= 65;
4618 tdep
->FPSCR_REGNUM
= SIM_SH64_FPCSR_REGNUM
;
4619 tdep
->FP_LAST_REGNUM
= SIM_SH64_FR0_REGNUM
+ SIM_SH64_NR_FP_REGS
- 1;
4620 tdep
->SSR_REGNUM
= SIM_SH64_SSR_REGNUM
;
4621 tdep
->SPC_REGNUM
= SIM_SH64_SPC_REGNUM
;
4622 tdep
->TR7_REGNUM
= SIM_SH64_TR0_REGNUM
+ 7;
4623 tdep
->FPP0_REGNUM
= 173;
4624 tdep
->FPP_LAST_REGNUM
= 204;
4625 tdep
->DR0_REGNUM
= 141;
4626 tdep
->DR_LAST_REGNUM
= 172;
4627 tdep
->FV0_REGNUM
= 205;
4628 tdep
->FV_LAST_REGNUM
= 220;
4629 tdep
->R0_C_REGNUM
= 221;
4630 tdep
->R_LAST_C_REGNUM
= 236;
4631 tdep
->PC_C_REGNUM
= 237;
4632 tdep
->GBR_C_REGNUM
= 238;
4633 tdep
->MACH_C_REGNUM
= 239;
4634 tdep
->MACL_C_REGNUM
= 240;
4635 tdep
->PR_C_REGNUM
= 241;
4636 tdep
->T_C_REGNUM
= 242;
4637 tdep
->FPSCR_C_REGNUM
= 243;
4638 tdep
->FPUL_C_REGNUM
= 244;
4639 tdep
->FP0_C_REGNUM
= 245;
4640 tdep
->FP_LAST_C_REGNUM
= 260;
4641 tdep
->DR0_C_REGNUM
= 261;
4642 tdep
->DR_LAST_C_REGNUM
= 268;
4643 tdep
->FV0_C_REGNUM
= 269;
4644 tdep
->FV_LAST_C_REGNUM
= 272;
4645 tdep
->ARG0_REGNUM
= 2;
4646 tdep
->ARGLAST_REGNUM
= 9;
4647 tdep
->RETURN_REGNUM
= 2;
4648 tdep
->FLOAT_ARGLAST_REGNUM
= 11;
4650 set_gdbarch_num_pseudo_regs (gdbarch
, NUM_PSEUDO_REGS_SH_MEDIA
+ NUM_PSEUDO_REGS_SH_COMPACT
);
4651 set_gdbarch_fp0_regnum (gdbarch
, SIM_SH64_FR0_REGNUM
);
4652 set_gdbarch_pc_regnum (gdbarch
, 64);
4654 /* Determine the ABI */
4655 if (bfd_get_arch_size (info
.abfd
) == 64)
4657 /* If the ABI is the 64-bit one, it can only be sh-media. */
4658 tdep
->sh_abi
= SH_ABI_64
;
4659 set_gdbarch_ptr_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
4660 set_gdbarch_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
4664 /* If the ABI is the 32-bit one it could be either media or
4666 tdep
->sh_abi
= SH_ABI_32
;
4667 set_gdbarch_ptr_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
4668 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
4671 /* the number of real registers is the same whether we are in
4672 ISA16(compact) or ISA32(media). */
4673 set_gdbarch_num_regs (gdbarch
, SIM_SH64_NR_REGS
);
4674 set_gdbarch_register_size (gdbarch
, 8); /*????*/
4675 set_gdbarch_register_bytes (gdbarch
,
4676 ((SIM_SH64_NR_FP_REGS
+ 1) * 4)
4677 + (SIM_SH64_NR_REGS
- SIM_SH64_NR_FP_REGS
-1) * 8);
4679 sh_register_name
= sh_sh64_register_name
;
4680 sh_show_regs
= sh64_show_regs
;
4681 sh_register_virtual_type
= sh_sh64_register_virtual_type
;
4682 sh_store_return_value
= sh64_store_return_value
;
4683 skip_prologue_hard_way
= sh64_skip_prologue_hard_way
;
4684 do_pseudo_register
= sh64_do_pseudo_register
;
4685 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_sh64
);
4686 set_gdbarch_register_raw_size (gdbarch
, sh_sh64_register_raw_size
);
4687 set_gdbarch_register_virtual_size (gdbarch
, sh_sh64_register_raw_size
);
4688 set_gdbarch_register_byte (gdbarch
, sh_sh64_register_byte
);
4689 /* This seems awfully wrong!*/
4690 /*set_gdbarch_max_register_raw_size (gdbarch, 8);*/
4691 /* should include the size of the pseudo regs. */
4692 set_gdbarch_max_register_raw_size (gdbarch
, 4 * 4);
4693 /* Or should that go in the virtual_size? */
4694 /*set_gdbarch_max_register_virtual_size (gdbarch, 8);*/
4695 set_gdbarch_max_register_virtual_size (gdbarch
, 4 * 4);
4696 set_gdbarch_register_read (gdbarch
, sh64_register_read
);
4697 set_gdbarch_register_write (gdbarch
, sh64_register_write
);
4699 set_gdbarch_do_registers_info (gdbarch
, sh64_do_registers_info
);
4700 set_gdbarch_frame_init_saved_regs (gdbarch
, sh64_nofp_frame_init_saved_regs
);
4701 set_gdbarch_breakpoint_from_pc (gdbarch
, sh_sh64_breakpoint_from_pc
);
4702 set_gdbarch_init_extra_frame_info (gdbarch
, sh64_init_extra_frame_info
);
4703 set_gdbarch_frame_chain (gdbarch
, sh64_frame_chain
);
4704 set_gdbarch_get_saved_register (gdbarch
, sh64_get_saved_register
);
4705 set_gdbarch_extract_return_value (gdbarch
, sh64_extract_return_value
);
4706 set_gdbarch_push_arguments (gdbarch
, sh64_push_arguments
);
4707 /*set_gdbarch_store_struct_return (gdbarch, sh64_store_struct_return);*/
4708 set_gdbarch_extract_struct_value_address (gdbarch
, sh64_extract_struct_value_address
);
4709 set_gdbarch_use_struct_convention (gdbarch
, sh64_use_struct_convention
);
4710 set_gdbarch_pop_frame (gdbarch
, sh64_pop_frame
);
4711 set_gdbarch_elf_make_msymbol_special (gdbarch
,
4712 sh64_elf_make_msymbol_special
);
4715 sh_register_name
= sh_generic_register_name
;
4716 sh_show_regs
= sh_generic_show_regs
;
4717 sh_store_return_value
= sh_default_store_return_value
;
4718 sh_register_virtual_type
= sh_default_register_virtual_type
;
4719 set_gdbarch_frame_init_saved_regs (gdbarch
, sh_nofp_frame_init_saved_regs
);
4720 set_gdbarch_register_raw_size (gdbarch
, sh_default_register_raw_size
);
4721 set_gdbarch_register_virtual_size (gdbarch
, sh_default_register_raw_size
);
4722 set_gdbarch_register_byte (gdbarch
, sh_default_register_byte
);
4726 set_gdbarch_read_pc (gdbarch
, generic_target_read_pc
);
4727 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
4728 set_gdbarch_read_fp (gdbarch
, generic_target_read_fp
);
4729 set_gdbarch_read_sp (gdbarch
, generic_target_read_sp
);
4730 set_gdbarch_write_sp (gdbarch
, generic_target_write_sp
);
4732 set_gdbarch_register_name (gdbarch
, sh_register_name
);
4733 set_gdbarch_register_virtual_type (gdbarch
, sh_register_virtual_type
);
4735 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
4736 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
4737 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
4738 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
4739 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
4740 set_gdbarch_long_double_bit (gdbarch
, 16 * TARGET_CHAR_BIT
);/*??should be 8?*/
4742 set_gdbarch_use_generic_dummy_frames (gdbarch
, 1);
4743 set_gdbarch_call_dummy_length (gdbarch
, 0);
4744 set_gdbarch_call_dummy_location (gdbarch
, AT_ENTRY_POINT
);
4745 set_gdbarch_call_dummy_address (gdbarch
, entry_point_address
);
4746 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1); /*???*/
4747 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
4748 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
4749 set_gdbarch_pc_in_call_dummy (gdbarch
, generic_pc_in_call_dummy
);
4750 set_gdbarch_call_dummy_words (gdbarch
, sh_call_dummy_words
);
4751 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (sh_call_dummy_words
));
4752 set_gdbarch_call_dummy_p (gdbarch
, 1);
4753 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 0);
4754 set_gdbarch_fix_call_dummy (gdbarch
, generic_fix_call_dummy
);
4755 set_gdbarch_coerce_float_to_double (gdbarch
,
4756 sh_coerce_float_to_double
);
4758 set_gdbarch_push_dummy_frame (gdbarch
, generic_push_dummy_frame
);
4759 set_gdbarch_push_return_address (gdbarch
, sh_push_return_address
);
4761 set_gdbarch_store_return_value (gdbarch
, sh_store_return_value
);
4762 set_gdbarch_skip_prologue (gdbarch
, sh_skip_prologue
);
4763 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
4764 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
4765 set_gdbarch_function_start_offset (gdbarch
, 0);
4767 set_gdbarch_frame_args_skip (gdbarch
, 0);
4768 set_gdbarch_frameless_function_invocation (gdbarch
, frameless_look_for_prologue
);
4769 set_gdbarch_frame_chain_valid (gdbarch
, generic_file_frame_chain_valid
);
4770 set_gdbarch_frame_saved_pc (gdbarch
, sh_frame_saved_pc
);
4771 set_gdbarch_frame_args_address (gdbarch
, default_frame_address
);
4772 set_gdbarch_frame_locals_address (gdbarch
, default_frame_address
);
4773 set_gdbarch_saved_pc_after_call (gdbarch
, sh_saved_pc_after_call
);
4774 set_gdbarch_frame_num_args (gdbarch
, frame_num_args_unknown
);
4775 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
4777 /* Hook in ABI-specific overrides, if they have been registered. If
4778 the ABI is unknown, this is probably an embedded target, so we
4779 should not warn about this situation. */
4780 if (sh_osabi
!= SH_OSABI_UNKNOWN
)
4782 for (osabi_handler
= sh_osabi_handler_list
; osabi_handler
!= NULL
;
4783 osabi_handler
= osabi_handler
->next
)
4784 if (osabi_handler
->abi
== sh_osabi
)
4788 osabi_handler
->init_osabi (info
, gdbarch
);
4791 /* We assume that if GDB_MULTI_ARCH is less than
4792 GDB_MULTI_ARCH_TM that an ABI variant can be supported by
4793 overriding definitions in this file. */
4794 if (GDB_MULTI_ARCH
> GDB_MULTI_ARCH_PARTIAL
)
4797 "A handler for the ABI variant \"%s\" is not built into this "
4798 "configuration of GDB. "
4799 "Attempting to continue with the default SuperH settings",
4800 sh_osabi_names
[sh_osabi
]);
4808 sh_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
4810 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4815 if (tdep
->osabi_name
!= NULL
)
4816 fprintf_unfiltered (file
, "sh_dump_tdep: OS ABI = %s\n", tdep
->osabi_name
);
4818 internal_error (__FILE__
, __LINE__
,
4819 "sh_dump_tdep: illegal setting of tdep->sh_osabi (%d)",
4820 (int) tdep
->sh_osabi
);
4824 _initialize_sh_tdep (void)
4826 struct cmd_list_element
*c
;
4828 gdbarch_register (bfd_arch_sh
, sh_gdbarch_init
, sh_dump_tdep
);
4830 add_com ("regs", class_vars
, sh_show_regs_command
, "Print all registers");