gdb/sh-tdep.c

   1 /* Target-dependent code for Hitachi Super-H, for GDB.
   2    Copyright 1993, 1994, 1995, 1996, 1997, 1998, 2000 Free Software
   3    Foundation, Inc.
   4
   5    This file is part of GDB.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 2 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program; if not, write to the Free Software
  19    Foundation, Inc., 59 Temple Place - Suite 330,
  20    Boston, MA 02111-1307, USA.  */
  21
  22 /*
  23    Contributed by Steve Chamberlain
  24    sac@cygnus.com
  25  */
  26
  27 #include "defs.h"
  28 #include "frame.h"
  29 #include "obstack.h"
  30 #include "symtab.h"
  31 #include "symfile.h"
  32 #include "gdbtypes.h"
  33 #include "gdbcmd.h"
  34 #include "gdbcore.h"
  35 #include "value.h"
  36 #include "dis-asm.h"
  37 #include "inferior.h"           /* for BEFORE_TEXT_END etc. */
  38 #include "gdb_string.h"
  39 #include "arch-utils.h"
  40
  41 /* A set of original names, to be used when restoring back to generic
  42    registers from a specific set.  */
  43 /* *INDENT-OFF* */
  44 static char *sh_generic_reg_names[] = {
  45   "r0",   "r1",   "r2",   "r3",   "r4",   "r5",   "r6",   "r7",
  46   "r8",   "r9",   "r10",  "r11",  "r12",  "r13",  "r14",  "r15",
  47   "pc",   "pr",   "gbr",  "vbr",  "mach", "macl", "sr",
  48   "fpul", "fpscr",
  49   "fr0",  "fr1",  "fr2",  "fr3",  "fr4",  "fr5",  "fr6",  "fr7",
  50   "fr8",  "fr9",  "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
  51   "ssr",  "spc",
  52   "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
  53   "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
  54 };
  55
  56 static char *sh_reg_names[] = {
  57   "r0",   "r1",   "r2",   "r3",   "r4",   "r5",   "r6",   "r7",
  58   "r8",   "r9",   "r10",  "r11",  "r12",  "r13",  "r14",  "r15",
  59   "pc",   "pr",   "gbr",  "vbr",  "mach", "macl", "sr",
  60   "",     "",
  61   "",     "",     "",     "",     "",     "",     "",     "",
  62   "",     "",     "",     "",     "",     "",     "",     "",
  63   "",     "",
  64   "",     "",     "",     "",     "",     "",     "",     "",
  65   "",     "",     "",     "",     "",     "",     "",     "",
  66 };
  67
  68 static char *sh3_reg_names[] = {
  69   "r0",   "r1",   "r2",   "r3",   "r4",   "r5",   "r6",   "r7",
  70   "r8",   "r9",   "r10",  "r11",  "r12",  "r13",  "r14",  "r15",
  71   "pc",   "pr",   "gbr",  "vbr",  "mach", "macl", "sr",
  72   "",     "",
  73   "",     "",     "",     "",     "",     "",     "",     "",
  74   "",     "",     "",     "",     "",     "",     "",     "",
  75   "ssr",  "spc",
  76   "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
  77   "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
  78 };
  79
  80 static char *sh3e_reg_names[] = {
  81   "r0",   "r1",   "r2",   "r3",   "r4",   "r5",   "r6",   "r7",
  82   "r8",   "r9",   "r10",  "r11",  "r12",  "r13",  "r14",  "r15",
  83   "pc",   "pr",   "gbr",  "vbr",  "mach", "macl", "sr",
  84   "fpul", "fpscr",
  85   "fr0",  "fr1",  "fr2",  "fr3",  "fr4",  "fr5",  "fr6",  "fr7",
  86   "fr8",  "fr9",  "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
  87   "ssr",  "spc",
  88   "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
  89   "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
  90 };
  91
  92 static char *sh_dsp_reg_names[] = {
  93   "r0",   "r1",   "r2",   "r3",   "r4",   "r5",   "r6",   "r7",
  94   "r8",   "r9",   "r10",  "r11",  "r12",  "r13",  "r14",  "r15",
  95   "pc",   "pr",   "gbr",  "vbr",  "mach", "macl", "sr",
  96   "",     "dsr",
  97   "a0g",  "a0",   "a1g",  "a1",   "m0",   "m1",   "x0",   "x1",
  98   "y0",   "y1",   "",     "",     "",     "",     "",     "mod",
  99   "",     "",
 100   "rs",   "re",   "",     "",     "",     "",     "",     "",
 101   "",     "",     "",     "",     "",     "",     "",     "",
 102 };
 103
 104 static char *sh3_dsp_reg_names[] = {
 105   "r0",   "r1",   "r2",   "r3",   "r4",   "r5",   "r6",   "r7",
 106   "r8",   "r9",   "r10",  "r11",  "r12",  "r13",  "r14",  "r15",
 107   "pc",   "pr",   "gbr",  "vbr",  "mach", "macl", "sr",
 108   "",     "dsr",
 109   "a0g",  "a0",   "a1g",  "a1",   "m0",   "m1",   "x0",   "x1",
 110   "y0",   "y1",   "",     "",     "",     "",     "",     "mod",
 111   "ssr",  "spc",
 112   "rs",   "re",   "",     "",     "",     "",     "",     "",
 113   "r0b",  "r1b",  "r2b",  "r3b",  "r4b",  "r5b",  "r6b",  "r7b",
 114 };
 115 /* *INDENT-ON* */
 116
 117 #ifdef _WIN32_WCE
 118 char **sh_register_names = sh3_reg_names;
 119 #else
 120 char **sh_register_names = sh_generic_reg_names;
 121 #endif
 122
 123 struct
 124   {
 125     char **regnames;
 126     int mach;
 127   }
 128 sh_processor_type_table[] =
 129 {
 130   {
 131     sh_reg_names, bfd_mach_sh
 132   }
 133   ,
 134   {
 135     sh_reg_names, bfd_mach_sh2
 136   }
 137   ,
 138   {
 139     sh_dsp_reg_names, bfd_mach_sh_dsp
 140   }
 141   ,
 142   {
 143     sh3_reg_names, bfd_mach_sh3
 144   }
 145   ,
 146   {
 147     sh3_dsp_reg_names, bfd_mach_sh3_dsp
 148   }
 149   ,
 150   {
 151     sh3e_reg_names, bfd_mach_sh3e
 152   }
 153   ,
 154   {
 155     NULL, 0
 156   }
 157 };
 158
 159 /* Prologue looks like
 160    [mov.l       <regs>,@-r15]...
 161    [sts.l       pr,@-r15]
 162    [mov.l       r14,@-r15]
 163    [mov         r15,r14]
 164  */
 165
 166 #define IS_STS(x)               ((x) == 0x4f22)
 167 #define IS_PUSH(x)              (((x) & 0xff0f) == 0x2f06)
 168 #define GET_PUSHED_REG(x)       (((x) >> 4) & 0xf)
 169 #define IS_MOV_SP_FP(x)         ((x) == 0x6ef3)
 170 #define IS_ADD_SP(x)            (((x) & 0xff00) == 0x7f00)
 171 #define IS_MOV_R3(x)            (((x) & 0xff00) == 0x1a00)
 172 #define IS_SHLL_R3(x)           ((x) == 0x4300)
 173 #define IS_ADD_R3SP(x)          ((x) == 0x3f3c)
 174 #define IS_FMOV(x)              (((x) & 0xf00f) == 0xf00b)
 175 #define FPSCR_SZ                (1 << 20)
 176
 177
 178 /* Should call_function allocate stack space for a struct return?  */
 179 int
 180 sh_use_struct_convention (gcc_p, type)
 181      int gcc_p;
 182      struct type *type;
 183 {
 184   return (TYPE_LENGTH (type) > 1);
 185 }
 186
 187
 188 /* Skip any prologue before the guts of a function */
 189
 190 CORE_ADDR
 191 sh_skip_prologue (start_pc)
 192      CORE_ADDR start_pc;
 193 {
 194   int w;
 195
 196   w = read_memory_integer (start_pc, 2);
 197   while (IS_STS (w)
 198          || IS_FMOV (w)
 199          || IS_PUSH (w)
 200          || IS_MOV_SP_FP (w)
 201          || IS_MOV_R3 (w)
 202          || IS_ADD_R3SP (w)
 203          || IS_ADD_SP (w)
 204          || IS_SHLL_R3 (w))
 205     {
 206       start_pc += 2;
 207       w = read_memory_integer (start_pc, 2);
 208     }
 209
 210   return start_pc;
 211 }
 212
 213 /* Disassemble an instruction.  */
 214
 215 int
 216 gdb_print_insn_sh (memaddr, info)
 217      bfd_vma memaddr;
 218      disassemble_info *info;
 219 {
 220   if (TARGET_BYTE_ORDER == BIG_ENDIAN)
 221     return print_insn_sh (memaddr, info);
 222   else
 223     return print_insn_shl (memaddr, info);
 224 }
 225
 226 /* Given a GDB frame, determine the address of the calling function's frame.
 227    This will be used to create a new GDB frame struct, and then
 228    INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
 229
 230    For us, the frame address is its stack pointer value, so we look up
 231    the function prologue to determine the caller's sp value, and return it.  */
 232
 233 CORE_ADDR
 234 sh_frame_chain (frame)
 235      struct frame_info *frame;
 236 {
 237   if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame))
 238     return frame->frame;        /* dummy frame same as caller's frame */
 239   if (!inside_entry_file (frame->pc))
 240     return read_memory_integer (FRAME_FP (frame) + frame->f_offset, 4);
 241   else
 242     return 0;
 243 }
 244
 245 /* Find REGNUM on the stack.  Otherwise, it's in an active register.  One thing
 246    we might want to do here is to check REGNUM against the clobber mask, and
 247    somehow flag it as invalid if it isn't saved on the stack somewhere.  This
 248    would provide a graceful failure mode when trying to get the value of
 249    caller-saves registers for an inner frame.  */
 250
 251 CORE_ADDR
 252 sh_find_callers_reg (fi, regnum)
 253      struct frame_info *fi;
 254      int regnum;
 255 {
 256   struct frame_saved_regs fsr;
 257
 258   for (; fi; fi = fi->next)
 259     if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
 260       /* When the caller requests PR from the dummy frame, we return PC because
 261          that's where the previous routine appears to have done a call from. */
 262       return generic_read_register_dummy (fi->pc, fi->frame, regnum);
 263     else
 264       {
 265         FRAME_FIND_SAVED_REGS (fi, fsr);
 266         if (fsr.regs[regnum] != 0)
 267           return read_memory_integer (fsr.regs[regnum],
 268                                       REGISTER_RAW_SIZE (regnum));
 269       }
 270   return read_register (regnum);
 271 }
 272
 273 /* Put here the code to store, into a struct frame_saved_regs, the
 274    addresses of the saved registers of frame described by FRAME_INFO.
 275    This includes special registers such as pc and fp saved in special
 276    ways in the stack frame.  sp is even more special: the address we
 277    return for it IS the sp for the next frame. */
 278
 279 void
 280 sh_frame_find_saved_regs (fi, fsr)
 281      struct frame_info *fi;
 282      struct frame_saved_regs *fsr;
 283 {
 284   int where[NUM_REGS];
 285   int rn;
 286   int have_fp = 0;
 287   int depth;
 288   int pc;
 289   int opc;
 290   int insn;
 291   int r3_val = 0;
 292   char *dummy_regs = generic_find_dummy_frame (fi->pc, fi->frame);
 293
 294   if (dummy_regs)
 295     {
 296       /* DANGER!  This is ONLY going to work if the char buffer format of
 297          the saved registers is byte-for-byte identical to the
 298          CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
 299       memcpy (&fsr->regs, dummy_regs, sizeof (fsr));
 300       return;
 301     }
 302
 303   opc = pc = get_pc_function_start (fi->pc);
 304
 305   insn = read_memory_integer (pc, 2);
 306
 307   fi->leaf_function = 1;
 308   fi->f_offset = 0;
 309
 310   for (rn = 0; rn < NUM_REGS; rn++)
 311     where[rn] = -1;
 312
 313   depth = 0;
 314
 315   /* Loop around examining the prologue insns until we find something
 316      that does not appear to be part of the prologue.  But give up
 317      after 20 of them, since we're getting silly then. */
 318
 319   while (pc < opc + 20 * 2)
 320     {
 321       /* See where the registers will be saved to */
 322       if (IS_PUSH (insn))
 323         {
 324           pc += 2;
 325           rn = GET_PUSHED_REG (insn);
 326           where[rn] = depth;
 327           insn = read_memory_integer (pc, 2);
 328           depth += 4;
 329         }
 330       else if (IS_STS (insn))
 331         {
 332           pc += 2;
 333           where[PR_REGNUM] = depth;
 334           insn = read_memory_integer (pc, 2);
 335           /* If we're storing the pr then this isn't a leaf */
 336           fi->leaf_function = 0;
 337           depth += 4;
 338         }
 339       else if (IS_MOV_R3 (insn))
 340         {
 341           r3_val = ((insn & 0xff) ^ 0x80) - 0x80;
 342           pc += 2;
 343           insn = read_memory_integer (pc, 2);
 344         }
 345       else if (IS_SHLL_R3 (insn))
 346         {
 347           r3_val <<= 1;
 348           pc += 2;
 349           insn = read_memory_integer (pc, 2);
 350         }
 351       else if (IS_ADD_R3SP (insn))
 352         {
 353           depth += -r3_val;
 354           pc += 2;
 355           insn = read_memory_integer (pc, 2);
 356         }
 357       else if (IS_ADD_SP (insn))
 358         {
 359           pc += 2;
 360           depth -= ((insn & 0xff) ^ 0x80) - 0x80;
 361           insn = read_memory_integer (pc, 2);
 362         }
 363       else if (IS_FMOV (insn))
 364         {
 365           pc += 2;
 366           insn = read_memory_integer (pc, 2);
 367           if (read_register (FPSCR_REGNUM) & FPSCR_SZ)
 368             {
 369               depth += 8;
 370             }
 371           else
 372             {
 373               depth += 4;
 374             }
 375         }
 376       else
 377         break;
 378     }
 379
 380   /* Now we know how deep things are, we can work out their addresses */
 381
 382   for (rn = 0; rn < NUM_REGS; rn++)
 383     {
 384       if (where[rn] >= 0)
 385         {
 386           if (rn == FP_REGNUM)
 387             have_fp = 1;
 388
 389           fsr->regs[rn] = fi->frame - where[rn] + depth - 4;
 390         }
 391       else
 392         {
 393           fsr->regs[rn] = 0;
 394         }
 395     }
 396
 397   if (have_fp)
 398     {
 399       fsr->regs[SP_REGNUM] = read_memory_integer (fsr->regs[FP_REGNUM], 4);
 400     }
 401   else
 402     {
 403       fsr->regs[SP_REGNUM] = fi->frame - 4;
 404     }
 405
 406   fi->f_offset = depth - where[FP_REGNUM] - 4;
 407   /* Work out the return pc - either from the saved pr or the pr
 408      value */
 409 }
 410
 411 /* initialize the extra info saved in a FRAME */
 412
 413 void
 414 sh_init_extra_frame_info (fromleaf, fi)
 415      int fromleaf;
 416      struct frame_info *fi;
 417 {
 418   struct frame_saved_regs fsr;
 419
 420   if (fi->next)
 421     fi->pc = FRAME_SAVED_PC (fi->next);
 422
 423   if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
 424     {
 425       /* We need to setup fi->frame here because run_stack_dummy gets it wrong
 426          by assuming it's always FP.  */
 427       fi->frame = generic_read_register_dummy (fi->pc, fi->frame,
 428                                                SP_REGNUM);
 429       fi->return_pc = generic_read_register_dummy (fi->pc, fi->frame,
 430                                                    PC_REGNUM);
 431       fi->f_offset = -(CALL_DUMMY_LENGTH + 4);
 432       fi->leaf_function = 0;
 433       return;
 434     }
 435   else
 436     {
 437       FRAME_FIND_SAVED_REGS (fi, fsr);
 438       fi->return_pc = sh_find_callers_reg (fi, PR_REGNUM);
 439     }
 440 }
 441
 442 /* Discard from the stack the innermost frame,
 443    restoring all saved registers.  */
 444
 445 void
 446 sh_pop_frame ()
 447 {
 448   register struct frame_info *frame = get_current_frame ();
 449   register CORE_ADDR fp;
 450   register int regnum;
 451   struct frame_saved_regs fsr;
 452
 453   if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame))
 454     generic_pop_dummy_frame ();
 455   else
 456     {
 457       fp = FRAME_FP (frame);
 458       get_frame_saved_regs (frame, &fsr);
 459
 460       /* Copy regs from where they were saved in the frame */
 461       for (regnum = 0; regnum < NUM_REGS; regnum++)
 462         if (fsr.regs[regnum])
 463           write_register (regnum, read_memory_integer (fsr.regs[regnum], 4));
 464
 465       write_register (PC_REGNUM, frame->return_pc);
 466       write_register (SP_REGNUM, fp + 4);
 467     }
 468   flush_cached_frames ();
 469 }
 470
 471 /* Function: push_arguments
 472    Setup the function arguments for calling a function in the inferior.
 473
 474    On the Hitachi SH architecture, there are four registers (R4 to R7)
 475    which are dedicated for passing function arguments.  Up to the first
 476    four arguments (depending on size) may go into these registers.
 477    The rest go on the stack.
 478
 479    Arguments that are smaller than 4 bytes will still take up a whole
 480    register or a whole 32-bit word on the stack, and will be
 481    right-justified in the register or the stack word.  This includes
 482    chars, shorts, and small aggregate types.
 483
 484    Arguments that are larger than 4 bytes may be split between two or
 485    more registers.  If there are not enough registers free, an argument
 486    may be passed partly in a register (or registers), and partly on the
 487    stack.  This includes doubles, long longs, and larger aggregates.
 488    As far as I know, there is no upper limit to the size of aggregates
 489    that will be passed in this way; in other words, the convention of
 490    passing a pointer to a large aggregate instead of a copy is not used.
 491
 492    An exceptional case exists for struct arguments (and possibly other
 493    aggregates such as arrays) if the size is larger than 4 bytes but
 494    not a multiple of 4 bytes.  In this case the argument is never split
 495    between the registers and the stack, but instead is copied in its
 496    entirety onto the stack, AND also copied into as many registers as
 497    there is room for.  In other words, space in registers permitting,
 498    two copies of the same argument are passed in.  As far as I can tell,
 499    only the one on the stack is used, although that may be a function
 500    of the level of compiler optimization.  I suspect this is a compiler
 501    bug.  Arguments of these odd sizes are left-justified within the
 502    word (as opposed to arguments smaller than 4 bytes, which are
 503    right-justified).
 504
 505
 506    If the function is to return an aggregate type such as a struct, it
 507    is either returned in the normal return value register R0 (if its
 508    size is no greater than one byte), or else the caller must allocate
 509    space into which the callee will copy the return value (if the size
 510    is greater than one byte).  In this case, a pointer to the return
 511    value location is passed into the callee in register R2, which does
 512    not displace any of the other arguments passed in via registers R4
 513    to R7.   */
 514
 515 CORE_ADDR
 516 sh_push_arguments (nargs, args, sp, struct_return, struct_addr)
 517      int nargs;
 518      value_ptr *args;
 519      CORE_ADDR sp;
 520      unsigned char struct_return;
 521      CORE_ADDR struct_addr;
 522 {
 523   int stack_offset, stack_alloc;
 524   int argreg;
 525   int argnum;
 526   struct type *type;
 527   CORE_ADDR regval;
 528   char *val;
 529   char valbuf[4];
 530   int len;
 531   int odd_sized_struct;
 532
 533   /* first force sp to a 4-byte alignment */
 534   sp = sp & ~3;
 535
 536   /* The "struct return pointer" pseudo-argument has its own dedicated
 537      register */
 538   if (struct_return)
 539     write_register (STRUCT_RETURN_REGNUM, struct_addr);
 540
 541   /* Now make sure there's space on the stack */
 542   for (argnum = 0, stack_alloc = 0;
 543        argnum < nargs; argnum++)
 544     stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 3) & ~3);
 545   sp -= stack_alloc;            /* make room on stack for args */
 546
 547
 548   /* Now load as many as possible of the first arguments into
 549      registers, and push the rest onto the stack.  There are 16 bytes
 550      in four registers available.  Loop thru args from first to last.  */
 551
 552   argreg = ARG0_REGNUM;
 553   for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
 554     {
 555       type = VALUE_TYPE (args[argnum]);
 556       len = TYPE_LENGTH (type);
 557       memset (valbuf, 0, sizeof (valbuf));
 558       if (len < 4)
 559         {                       /* value gets right-justified in the register or stack word */
 560           memcpy (valbuf + (4 - len),
 561                   (char *) VALUE_CONTENTS (args[argnum]), len);
 562           val = valbuf;
 563         }
 564       else
 565         val = (char *) VALUE_CONTENTS (args[argnum]);
 566
 567       if (len > 4 && (len & 3) != 0)
 568         odd_sized_struct = 1;   /* such structs go entirely on stack */
 569       else
 570         odd_sized_struct = 0;
 571       while (len > 0)
 572         {
 573           if (argreg > ARGLAST_REGNUM || odd_sized_struct)
 574             {                   /* must go on the stack */
 575               write_memory (sp + stack_offset, val, 4);
 576               stack_offset += 4;
 577             }
 578           /* NOTE WELL!!!!!  This is not an "else if" clause!!!
 579              That's because some *&^%$ things get passed on the stack
 580              AND in the registers!   */
 581           if (argreg <= ARGLAST_REGNUM)
 582             {                   /* there's room in a register */
 583               regval = extract_address (val, REGISTER_RAW_SIZE (argreg));
 584               write_register (argreg++, regval);
 585             }
 586           /* Store the value 4 bytes at a time.  This means that things
 587              larger than 4 bytes may go partly in registers and partly
 588              on the stack.  */
 589           len -= REGISTER_RAW_SIZE (argreg);
 590           val += REGISTER_RAW_SIZE (argreg);
 591         }
 592     }
 593   return sp;
 594 }
 595
 596 /* Function: push_return_address (pc)
 597    Set up the return address for the inferior function call.
 598    Needed for targets where we don't actually execute a JSR/BSR instruction */
 599
 600 CORE_ADDR
 601 sh_push_return_address (pc, sp)
 602      CORE_ADDR pc;
 603      CORE_ADDR sp;
 604 {
 605   write_register (PR_REGNUM, CALL_DUMMY_ADDRESS ());
 606   return sp;
 607 }
 608
 609 /* Function: fix_call_dummy
 610    Poke the callee function's address into the destination part of
 611    the CALL_DUMMY.  The address is actually stored in a data word
 612    following the actualy CALL_DUMMY instructions, which will load
 613    it into a register using PC-relative addressing.  This function
 614    expects the CALL_DUMMY to look like this:
 615
 616    mov.w @(2,PC), R8
 617    jsr   @R8
 618    nop
 619    trap
 620    <destination>
 621  */
 622
 623 #if 0
 624 void
 625 sh_fix_call_dummy (dummy, pc, fun, nargs, args, type, gcc_p)
 626      char *dummy;
 627      CORE_ADDR pc;
 628      CORE_ADDR fun;
 629      int nargs;
 630      value_ptr *args;
 631      struct type *type;
 632      int gcc_p;
 633 {
 634   *(unsigned long *) (dummy + 8) = fun;
 635 }
 636 #endif
 637
 638
 639 /* Modify the actual processor type. */
 640
 641 int
 642 sh_target_architecture_hook (ap)
 643      const bfd_arch_info_type *ap;
 644 {
 645   int i, j;
 646
 647   if (ap->arch != bfd_arch_sh)
 648     return 0;
 649
 650   for (i = 0; sh_processor_type_table[i].regnames != NULL; i++)
 651     {
 652       if (sh_processor_type_table[i].mach == ap->mach)
 653         {
 654           sh_register_names = sh_processor_type_table[i].regnames;
 655           return 1;
 656         }
 657     }
 658
 659   internal_error ("Architecture `%s' unreconized", ap->printable_name);
 660 }
 661
 662 /* Print the registers in a form similar to the E7000 */
 663
 664 static void
 665 sh_show_regs (args, from_tty)
 666      char *args;
 667      int from_tty;
 668 {
 669   int cpu;
 670   if (TARGET_ARCHITECTURE->arch == bfd_arch_sh)
 671     cpu = TARGET_ARCHITECTURE->mach;
 672   else
 673     cpu = 0;
 674
 675   printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
 676                    paddr (read_register (PC_REGNUM)),
 677                    (long) read_register (SR_REGNUM),
 678                    (long) read_register (PR_REGNUM),
 679                    (long) read_register (MACH_REGNUM),
 680                    (long) read_register (MACL_REGNUM));
 681
 682   printf_filtered ("GBR=%08lx VBR=%08lx",
 683                    (long) read_register (GBR_REGNUM),
 684                    (long) read_register (VBR_REGNUM));
 685   if (cpu == bfd_mach_sh3 || cpu == bfd_mach_sh3e || cpu == bfd_mach_sh3_dsp
 686       || cpu == bfd_mach_sh4)
 687     {
 688       printf_filtered (" SSR=%08lx SPC=%08lx",
 689                        (long) read_register (SSR_REGNUM),
 690                        (long) read_register (SPC_REGNUM));
 691       if (cpu == bfd_mach_sh3e || cpu == bfd_mach_sh4)
 692         {
 693           printf_filtered (" FPUL=%08lx FPSCR=%08lx",
 694                            (long) read_register (FPUL_REGNUM),
 695                            (long) read_register (FPSCR_REGNUM));
 696         }
 697     }
 698   if (cpu == bfd_mach_sh_dsp || cpu == bfd_mach_sh3_dsp)
 699     printf_filtered (" DSR=%08lx", (long) read_register (DSR_REGNUM));
 700
 701   printf_filtered ("\nR0-R7  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
 702                    (long) read_register (0),
 703                    (long) read_register (1),
 704                    (long) read_register (2),
 705                    (long) read_register (3),
 706                    (long) read_register (4),
 707                    (long) read_register (5),
 708                    (long) read_register (6),
 709                    (long) read_register (7));
 710   printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
 711                    (long) read_register (8),
 712                    (long) read_register (9),
 713                    (long) read_register (10),
 714                    (long) read_register (11),
 715                    (long) read_register (12),
 716                    (long) read_register (13),
 717                    (long) read_register (14),
 718                    (long) read_register (15));
 719   if (cpu == bfd_mach_sh3e || cpu == bfd_mach_sh4)
 720     {
 721       int pr = cpu == bfd_mach_sh4 && (read_register (FPSCR_REGNUM) & 0x80000);
 722
 723       printf_filtered ((pr
 724                         ? "DR0-DR6  %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
 725                         : "FP0-FP7  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
 726                        (long) read_register (FP0_REGNUM + 0),
 727                        (long) read_register (FP0_REGNUM + 1),
 728                        (long) read_register (FP0_REGNUM + 2),
 729                        (long) read_register (FP0_REGNUM + 3),
 730                        (long) read_register (FP0_REGNUM + 4),
 731                        (long) read_register (FP0_REGNUM + 5),
 732                        (long) read_register (FP0_REGNUM + 6),
 733                        (long) read_register (FP0_REGNUM + 7));
 734       printf_filtered ((pr
 735                         ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
 736                         : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
 737                        (long) read_register (FP0_REGNUM + 8),
 738                        (long) read_register (FP0_REGNUM + 9),
 739                        (long) read_register (FP0_REGNUM + 10),
 740                        (long) read_register (FP0_REGNUM + 11),
 741                        (long) read_register (FP0_REGNUM + 12),
 742                        (long) read_register (FP0_REGNUM + 13),
 743                        (long) read_register (FP0_REGNUM + 14),
 744                        (long) read_register (FP0_REGNUM + 15));
 745     }
 746   /* FIXME: sh4 has more registers */
 747   if (cpu == bfd_mach_sh_dsp || cpu == bfd_mach_sh3_dsp)
 748     {
 749       printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
 750                        (long) read_register (A0G_REGNUM) & 0xff,
 751                        (long) read_register (A0_REGNUM),
 752                        (long) read_register (M0_REGNUM),
 753                        (long) read_register (X0_REGNUM),
 754                        (long) read_register (Y0_REGNUM),
 755                        (long) read_register (RS_REGNUM),
 756                        (long) read_register (MOD_REGNUM));
 757       printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
 758                        (long) read_register (A1G_REGNUM) & 0xff,
 759                        (long) read_register (A1_REGNUM),
 760                        (long) read_register (M1_REGNUM),
 761                        (long) read_register (X1_REGNUM),
 762                        (long) read_register (Y1_REGNUM),
 763                        (long) read_register (RE_REGNUM));
 764     }
 765 }
 766
 767 /* Function: extract_return_value
 768    Find a function's return value in the appropriate registers (in regbuf),
 769    and copy it into valbuf.  */
 770
 771 void
 772 sh_extract_return_value (type, regbuf, valbuf)
 773      struct type *type;
 774      void *regbuf;
 775      void *valbuf;
 776 {
 777   int len = TYPE_LENGTH (type);
 778
 779   if (len <= 4)
 780     memcpy (valbuf, ((char *) regbuf) + 4 - len, len);
 781   else if (len <= 8)
 782     memcpy (valbuf, ((char *) regbuf) + 8 - len, len);
 783   else
 784     error ("bad size for return value");
 785 }
 786
 787 void
 788 _initialize_sh_tdep ()
 789 {
 790   struct cmd_list_element *c;
 791
 792   tm_print_insn = gdb_print_insn_sh;
 793
 794   target_architecture_hook = sh_target_architecture_hook;
 795
 796   add_com ("regs", class_vars, sh_show_regs, "Print all registers");
 797 }