1 /* Target-dependent code for Hitachi Super-H, for GDB.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
3 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 Contributed by Steve Chamberlain
37 #include "inferior.h" /* for BEFORE_TEXT_END etc. */
38 #include "gdb_string.h"
39 #include "arch-utils.h"
40 #include "floatformat.h"
47 #include "solib-svr4.h"
51 /* registers numbers shared with the simulator */
52 #include "gdb/sim-sh.h"
54 void (*sh_show_regs
) (void);
55 CORE_ADDR (*skip_prologue_hard_way
) (CORE_ADDR
);
56 void (*do_pseudo_register
) (int);
58 #define SH_DEFAULT_NUM_REGS 59
60 /* Define other aspects of the stack frame.
61 we keep a copy of the worked out return pc lying around, since it
62 is a useful bit of info */
64 struct frame_extra_info
72 sh_generic_register_name (int reg_nr
)
74 static char *register_names
[] =
76 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
77 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
78 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
80 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
81 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
83 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
84 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
88 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
90 return register_names
[reg_nr
];
94 sh_sh_register_name (int reg_nr
)
96 static char *register_names
[] =
98 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
99 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
100 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
102 "", "", "", "", "", "", "", "",
103 "", "", "", "", "", "", "", "",
105 "", "", "", "", "", "", "", "",
106 "", "", "", "", "", "", "", "",
110 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
112 return register_names
[reg_nr
];
116 sh_sh3_register_name (int reg_nr
)
118 static char *register_names
[] =
120 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
121 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
122 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
124 "", "", "", "", "", "", "", "",
125 "", "", "", "", "", "", "", "",
127 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
128 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
132 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
134 return register_names
[reg_nr
];
138 sh_sh3e_register_name (int reg_nr
)
140 static char *register_names
[] =
142 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
143 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
144 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
146 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
147 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
149 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
150 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
154 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
156 return register_names
[reg_nr
];
160 sh_sh_dsp_register_name (int reg_nr
)
162 static char *register_names
[] =
164 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
165 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
166 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
168 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
169 "y0", "y1", "", "", "", "", "", "mod",
171 "rs", "re", "", "", "", "", "", "",
172 "", "", "", "", "", "", "", "",
176 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
178 return register_names
[reg_nr
];
182 sh_sh3_dsp_register_name (int reg_nr
)
184 static char *register_names
[] =
186 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
187 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
188 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
190 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
191 "y0", "y1", "", "", "", "", "", "mod",
193 "rs", "re", "", "", "", "", "", "",
194 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b"
195 "", "", "", "", "", "", "", "",
199 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
201 return register_names
[reg_nr
];
205 sh_sh4_register_name (int reg_nr
)
207 static char *register_names
[] =
209 /* general registers 0-15 */
210 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
211 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
213 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
216 /* floating point registers 25 - 40 */
217 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
218 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
222 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
224 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
225 /* double precision (pseudo) 59 - 66 */
226 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
227 /* vectors (pseudo) 67 - 70 */
228 "fv0", "fv4", "fv8", "fv12",
229 /* FIXME: missing XF 71 - 86 */
230 /* FIXME: missing XD 87 - 94 */
234 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
236 return register_names
[reg_nr
];
240 sh_sh64_register_name (int reg_nr
)
242 static char *register_names
[] =
244 /* SH MEDIA MODE (ISA 32) */
245 /* general registers (64-bit) 0-63 */
246 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
247 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
248 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
249 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
250 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
251 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
252 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
253 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
258 /* status reg., saved status reg., saved pc reg. (64-bit) 65-67 */
261 /* target registers (64-bit) 68-75*/
262 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7",
264 /* floating point state control register (32-bit) 76 */
267 /* single precision floating point registers (32-bit) 77-140*/
268 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
269 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
270 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
271 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31",
272 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39",
273 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47",
274 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55",
275 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63",
277 /* double precision registers (pseudo) 141-172 */
278 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
279 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30",
280 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46",
281 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62",
283 /* floating point pairs (pseudo) 173-204*/
284 "fp0", "fp2", "fp4", "fp6", "fp8", "fp10", "fp12", "fp14",
285 "fp16", "fp18", "fp20", "fp22", "fp24", "fp26", "fp28", "fp30",
286 "fp32", "fp34", "fp36", "fp38", "fp40", "fp42", "fp44", "fp46",
287 "fp48", "fp50", "fp52", "fp54", "fp56", "fp58", "fp60", "fp62",
289 /* floating point vectors (4 floating point regs) (pseudo) 205-220*/
290 "fv0", "fv4", "fv8", "fv12", "fv16", "fv20", "fv24", "fv28",
291 "fv32", "fv36", "fv40", "fv44", "fv48", "fv52", "fv56", "fv60",
293 /* SH COMPACT MODE (ISA 16) (all pseudo) 221-272*/
294 "r0_c", "r1_c", "r2_c", "r3_c", "r4_c", "r5_c", "r6_c", "r7_c",
295 "r8_c", "r9_c", "r10_c", "r11_c", "r12_c", "r13_c", "r14_c", "r15_c",
297 "gbr_c", "mach_c", "macl_c", "pr_c", "t_c",
299 "fr0_c", "fr1_c", "fr2_c", "fr3_c", "fr4_c", "fr5_c", "fr6_c", "fr7_c",
300 "fr8_c", "fr9_c", "fr10_c", "fr11_c", "fr12_c", "fr13_c", "fr14_c", "fr15_c",
301 "dr0_c", "dr2_c", "dr4_c", "dr6_c", "dr8_c", "dr10_c", "dr12_c", "dr14_c",
302 "fv0_c", "fv4_c", "fv8_c", "fv12_c",
303 /* FIXME!!!! XF0 XF15, XD0 XD14 ?????*/
308 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
310 return register_names
[reg_nr
];
313 #define NUM_PSEUDO_REGS_SH_MEDIA 80
314 #define NUM_PSEUDO_REGS_SH_COMPACT 51
316 static const unsigned char *
317 sh_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
319 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
320 static unsigned char breakpoint
[] = {0xc3, 0xc3};
322 *lenptr
= sizeof (breakpoint
);
326 /* Macros and functions for setting and testing a bit in a minimal
327 symbol that marks it as 32-bit function. The MSB of the minimal
328 symbol's "info" field is used for this purpose. This field is
329 already being used to store the symbol size, so the assumption is
330 that the symbol size cannot exceed 2^31.
332 ELF_MAKE_MSYMBOL_SPECIAL
333 tests whether an ELF symbol is "special", i.e. refers
334 to a 32-bit function, and sets a "special" bit in a
335 minimal symbol to mark it as a 32-bit function
336 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol
337 MSYMBOL_SIZE returns the size of the minimal symbol, i.e.
338 the "info" field with the "special" bit masked out */
340 #define MSYMBOL_IS_SPECIAL(msym) \
341 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
344 sh64_elf_make_msymbol_special (asymbol
*sym
, struct minimal_symbol
*msym
)
349 if (((elf_symbol_type
*)(sym
))->internal_elf_sym
.st_other
== STO_SH5_ISA32
)
351 MSYMBOL_INFO (msym
) = (char *) (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
352 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
356 /* ISA32 (shmedia) function addresses are odd (bit 0 is set). Here
357 are some macros to test, set, or clear bit 0 of addresses. */
358 #define IS_ISA32_ADDR(addr) ((addr) & 1)
359 #define MAKE_ISA32_ADDR(addr) ((addr) | 1)
360 #define UNMAKE_ISA32_ADDR(addr) ((addr) & ~1)
363 pc_is_isa32 (bfd_vma memaddr
)
365 struct minimal_symbol
*sym
;
367 /* If bit 0 of the address is set, assume this is a
368 ISA32 (shmedia) address. */
369 if (IS_ISA32_ADDR (memaddr
))
372 /* A flag indicating that this is a ISA32 function is stored by elfread.c in
373 the high bit of the info field. Use this to decide if the function is
375 sym
= lookup_minimal_symbol_by_pc (memaddr
);
377 return MSYMBOL_IS_SPECIAL (sym
);
382 static const unsigned char *
383 sh_sh64_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
385 /* The BRK instruction for shmedia is
386 01101111 11110101 11111111 11110000
387 which translates in big endian mode to 0x6f, 0xf5, 0xff, 0xf0
388 and in little endian mode to 0xf0, 0xff, 0xf5, 0x6f */
390 /* The BRK instruction for shcompact is
392 which translates in big endian mode to 0x0, 0x3b
393 and in little endian mode to 0x3b, 0x0*/
395 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
397 if (pc_is_isa32 (*pcptr
))
399 static unsigned char big_breakpoint_media
[] = {0x6f, 0xf5, 0xff, 0xf0};
400 *pcptr
= UNMAKE_ISA32_ADDR (*pcptr
);
401 *lenptr
= sizeof (big_breakpoint_media
);
402 return big_breakpoint_media
;
406 static unsigned char big_breakpoint_compact
[] = {0x0, 0x3b};
407 *lenptr
= sizeof (big_breakpoint_compact
);
408 return big_breakpoint_compact
;
413 if (pc_is_isa32 (*pcptr
))
415 static unsigned char little_breakpoint_media
[] = {0xf0, 0xff, 0xf5, 0x6f};
416 *pcptr
= UNMAKE_ISA32_ADDR (*pcptr
);
417 *lenptr
= sizeof (little_breakpoint_media
);
418 return little_breakpoint_media
;
422 static unsigned char little_breakpoint_compact
[] = {0x3b, 0x0};
423 *lenptr
= sizeof (little_breakpoint_compact
);
424 return little_breakpoint_compact
;
429 /* Prologue looks like
430 [mov.l <regs>,@-r15]...
435 Actually it can be more complicated than this. For instance, with
453 /* PTABS/L Rn, TRa 0110101111110001nnnnnnl00aaa0000
454 with l=1 and n = 18 0110101111110001010010100aaa0000 */
455 #define IS_PTABSL_R18(x) (((x) & 0xffffff8f) == 0x6bf14a00)
457 /* STS.L PR,@-r0 0100000000100010
458 r0-4-->r0, PR-->(r0) */
459 #define IS_STS_R0(x) ((x) == 0x4022)
461 /* STS PR, Rm 0000mmmm00101010
463 #define IS_STS_PR(x) (((x) & 0xf0ff) == 0x2a)
465 /* MOV.L Rm,@(disp,r15) 00011111mmmmdddd
467 #define IS_MOV_TO_R15(x) (((x) & 0xff00) == 0x1f00)
469 /* MOV.L R14,@(disp,r15) 000111111110dddd
470 R14-->(dispx4+r15) */
471 #define IS_MOV_R14(x) (((x) & 0xfff0) == 0x1fe0)
473 /* ST.Q R14, disp, R18 101011001110dddddddddd0100100000
474 R18-->(dispx8+R14) */
475 #define IS_STQ_R18_R14(x) (((x) & 0xfff003ff) == 0xace00120)
477 /* ST.Q R15, disp, R18 101011001111dddddddddd0100100000
478 R18-->(dispx8+R15) */
479 #define IS_STQ_R18_R15(x) (((x) & 0xfff003ff) == 0xacf00120)
481 /* ST.L R15, disp, R18 101010001111dddddddddd0100100000
482 R18-->(dispx4+R15) */
483 #define IS_STL_R18_R15(x) (((x) & 0xfff003ff) == 0xa8f00120)
485 /* ST.Q R15, disp, R14 1010 1100 1111 dddd dddd dd00 1110 0000
486 R14-->(dispx8+R15) */
487 #define IS_STQ_R14_R15(x) (((x) & 0xfff003ff) == 0xacf000e0)
489 /* ST.L R15, disp, R14 1010 1000 1111 dddd dddd dd00 1110 0000
490 R14-->(dispx4+R15) */
491 #define IS_STL_R14_R15(x) (((x) & 0xfff003ff) == 0xa8f000e0)
493 /* ADDI.L R15,imm,R15 1101 0100 1111 ssss ssss ss00 1111 0000
495 #define IS_ADDIL_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd4f000f0)
497 /* ADDI R15,imm,R15 1101 0000 1111 ssss ssss ss00 1111 0000
499 #define IS_ADDI_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd0f000f0)
501 /* ADD.L R15,R63,R14 0000 0000 1111 1000 1111 1100 1110 0000
503 #define IS_ADDL_SP_FP_MEDIA(x) ((x) == 0x00f8fce0)
505 /* ADD R15,R63,R14 0000 0000 1111 1001 1111 1100 1110 0000
507 #define IS_ADD_SP_FP_MEDIA(x) ((x) == 0x00f9fce0)
509 #define IS_MOV_SP_FP_MEDIA(x) (IS_ADDL_SP_FP_MEDIA(x) || IS_ADD_SP_FP_MEDIA(x))
511 /* MOV #imm, R0 1110 0000 ssss ssss
513 #define IS_MOV_R0(x) (((x) & 0xff00) == 0xe000)
515 /* MOV.L @(disp,PC), R0 1101 0000 iiii iiii */
516 #define IS_MOVL_R0(x) (((x) & 0xff00) == 0xd000)
518 /* ADD r15,r0 0011 0000 1111 1100
520 #define IS_ADD_SP_R0(x) ((x) == 0x30fc)
522 /* MOV.L R14 @-R0 0010 0000 1110 0110
523 R14-->(R0-4), R0-4-->R0 */
524 #define IS_MOV_R14_R0(x) ((x) == 0x20e6)
526 /* ADD Rm,R63,Rn Rm+R63-->Rn 0000 00mm mmmm 1001 1111 11nn nnnn 0000
527 where Rm is one of r2-r9 which are the argument registers. */
528 /* FIXME: Recognize the float and double register moves too! */
529 #define IS_MEDIA_IND_ARG_MOV(x) \
530 ((((x) & 0xfc0ffc0f) == 0x0009fc00) && (((x) & 0x03f00000) >= 0x00200000 && ((x) & 0x03f00000) <= 0x00900000))
532 /* ST.Q Rn,0,Rm Rm-->Rn+0 1010 11nn nnnn 0000 0000 00mm mmmm 0000
533 or ST.L Rn,0,Rm Rm-->Rn+0 1010 10nn nnnn 0000 0000 00mm mmmm 0000
534 where Rm is one of r2-r9 which are the argument registers. */
535 #define IS_MEDIA_ARG_MOV(x) \
536 (((((x) & 0xfc0ffc0f) == 0xac000000) || (((x) & 0xfc0ffc0f) == 0xa8000000)) \
537 && (((x) & 0x000003f0) >= 0x00000020 && ((x) & 0x000003f0) <= 0x00000090))
539 /* ST.B R14,0,Rn Rn-->(R14+0) 1010 0000 1110 0000 0000 00nn nnnn 0000*/
540 /* ST.W R14,0,Rn Rn-->(R14+0) 1010 0100 1110 0000 0000 00nn nnnn 0000*/
541 /* ST.L R14,0,Rn Rn-->(R14+0) 1010 1000 1110 0000 0000 00nn nnnn 0000*/
542 /* FST.S R14,0,FRn Rn-->(R14+0) 1011 0100 1110 0000 0000 00nn nnnn 0000*/
543 /* FST.D R14,0,DRn Rn-->(R14+0) 1011 1100 1110 0000 0000 00nn nnnn 0000*/
544 #define IS_MEDIA_MOV_TO_R14(x) \
545 ((((x) & 0xfffffc0f) == 0xa0e00000) \
546 || (((x) & 0xfffffc0f) == 0xa4e00000) \
547 || (((x) & 0xfffffc0f) == 0xa8e00000) \
548 || (((x) & 0xfffffc0f) == 0xb4e00000) \
549 || (((x) & 0xfffffc0f) == 0xbce00000))
551 /* MOV Rm, Rn Rm-->Rn 0110 nnnn mmmm 0011
553 #define IS_COMPACT_IND_ARG_MOV(x) \
554 ((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0020) && (((x) & 0x00f0) <= 0x0090))
556 /* compact direct arg move!
557 MOV.L Rn, @r14 0010 1110 mmmm 0010 */
558 #define IS_COMPACT_ARG_MOV(x) \
559 (((((x) & 0xff0f) == 0x2e02) && (((x) & 0x00f0) >= 0x0020) && ((x) & 0x00f0) <= 0x0090))
561 /* MOV.B Rm, @R14 0010 1110 mmmm 0000
562 MOV.W Rm, @R14 0010 1110 mmmm 0001 */
563 #define IS_COMPACT_MOV_TO_R14(x) \
564 ((((x) & 0xff0f) == 0x2e00) || (((x) & 0xff0f) == 0x2e01))
566 #define IS_JSR_R0(x) ((x) == 0x400b)
567 #define IS_NOP(x) ((x) == 0x0009)
570 /* STS.L PR,@-r15 0100111100100010
571 r15-4-->r15, PR-->(r15) */
572 #define IS_STS(x) ((x) == 0x4f22)
574 /* MOV.L Rm,@-r15 00101111mmmm0110
575 r15-4-->r15, Rm-->(R15) */
576 #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
578 #define GET_PUSHED_REG(x) (((x) >> 4) & 0xf)
580 /* MOV r15,r14 0110111011110011
582 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
584 /* ADD #imm,r15 01111111iiiiiiii
586 #define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00)
588 #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
589 #define IS_SHLL_R3(x) ((x) == 0x4300)
591 /* ADD r3,r15 0011111100111100
593 #define IS_ADD_R3SP(x) ((x) == 0x3f3c)
595 /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
596 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
597 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
598 #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b)
600 /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011
601 MOV.L Rm,@(disp,Rn) Rm-->(dispx4+Rn) 0001nnnnmmmmdddd
602 MOV.L Rm,@Rn Rm-->(Rn) 0010nnnnmmmm0010
603 where Rm is one of r4,r5,r6,r7 which are the argument registers. */
604 #define IS_ARG_MOV(x) \
605 (((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \
606 || ((((x) & 0xf000) == 0x1000) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \
607 || ((((x) & 0xf00f) == 0x2002) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)))
609 /* MOV.L Rm,@(disp,r14) 00011110mmmmdddd
610 Rm-->(dispx4+r14) where Rm is one of r4,r5,r6,r7 */
611 #define IS_MOV_TO_R14(x) \
612 ((((x) & 0xff00) == 0x1e) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070))
614 #define FPSCR_SZ (1 << 20)
616 /* Skip any prologue before the guts of a function */
618 /* Skip the prologue using the debug information. If this fails we'll
619 fall back on the 'guess' method below. */
621 after_prologue (CORE_ADDR pc
)
623 struct symtab_and_line sal
;
624 CORE_ADDR func_addr
, func_end
;
626 /* If we can not find the symbol in the partial symbol table, then
627 there is no hope we can determine the function's start address
629 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
632 /* Get the line associated with FUNC_ADDR. */
633 sal
= find_pc_line (func_addr
, 0);
635 /* There are only two cases to consider. First, the end of the source line
636 is within the function bounds. In that case we return the end of the
637 source line. Second is the end of the source line extends beyond the
638 bounds of the current function. We need to use the slow code to
639 examine instructions in that case. */
640 if (sal
.end
< func_end
)
646 /* Here we look at each instruction in the function, and try to guess
647 where the prologue ends. Unfortunately this is not always
650 sh_skip_prologue_hard_way (CORE_ADDR start_pc
)
658 for (here
= start_pc
, end
= start_pc
+ (2 * 28); here
< end
;)
660 int w
= read_memory_integer (here
, 2);
662 if (IS_FMOV (w
) || IS_PUSH (w
) || IS_STS (w
) || IS_MOV_R3 (w
)
663 || IS_ADD_R3SP (w
) || IS_ADD_SP (w
) || IS_SHLL_R3 (w
)
664 || IS_ARG_MOV (w
) || IS_MOV_TO_R14 (w
))
668 else if (IS_MOV_SP_FP (w
))
674 /* Don't bail out yet, if we are before the copy of sp. */
683 look_for_args_moves (CORE_ADDR start_pc
, int media_mode
)
687 int insn_size
= (media_mode
? 4 : 2);
689 for (here
= start_pc
, end
= start_pc
+ (insn_size
* 28); here
< end
;)
693 w
= read_memory_integer (UNMAKE_ISA32_ADDR (here
), insn_size
);
695 if (IS_MEDIA_IND_ARG_MOV (w
))
697 /* This must be followed by a store to r14, so the argument
698 is where the debug info says it is. This can happen after
699 the SP has been saved, unfortunately. */
701 int next_insn
= read_memory_integer (UNMAKE_ISA32_ADDR (here
),
704 if (IS_MEDIA_MOV_TO_R14 (next_insn
))
707 else if (IS_MEDIA_ARG_MOV (w
))
709 /* These instructions store directly the argument in r14. */
717 w
= read_memory_integer (here
, insn_size
);
720 if (IS_COMPACT_IND_ARG_MOV (w
))
722 /* This must be followed by a store to r14, so the argument
723 is where the debug info says it is. This can happen after
724 the SP has been saved, unfortunately. */
726 int next_insn
= 0xffff & read_memory_integer (here
, insn_size
);
728 if (IS_COMPACT_MOV_TO_R14 (next_insn
))
731 else if (IS_COMPACT_ARG_MOV (w
))
733 /* These instructions store directly the argument in r14. */
736 else if (IS_MOVL_R0 (w
))
738 /* There is a function that gcc calls to get the arguments
739 passed correctly to the function. Only after this
740 function call the arguments will be found at the place
741 where they are supposed to be. This happens in case the
742 argument has to be stored into a 64-bit register (for
743 instance doubles, long longs). SHcompact doesn't have
744 access to the full 64-bits, so we store the register in
745 stack slot and store the address of the stack slot in
746 the register, then do a call through a wrapper that
747 loads the memory value into the register. A SHcompact
748 callee calls an argument decoder
749 (GCC_shcompact_incoming_args) that stores the 64-bit
750 value in a stack slot and stores the address of the
751 stack slot in the register. GCC thinks the argument is
752 just passed by transparent reference, but this is only
753 true after the argument decoder is called. Such a call
754 needs to be considered part of the prologue. */
756 /* This must be followed by a JSR @r0 instruction and by
757 a NOP instruction. After these, the prologue is over! */
759 int next_insn
= 0xffff & read_memory_integer (here
, insn_size
);
761 if (IS_JSR_R0 (next_insn
))
763 next_insn
= 0xffff & read_memory_integer (here
, insn_size
);
766 if (IS_NOP (next_insn
))
779 sh64_skip_prologue_hard_way (CORE_ADDR start_pc
)
789 if (pc_is_isa32 (start_pc
) == 0)
795 for (here
= start_pc
, end
= start_pc
+ (insn_size
* 28); here
< end
;)
800 int w
= read_memory_integer (UNMAKE_ISA32_ADDR (here
), insn_size
);
802 if (IS_STQ_R18_R14 (w
) || IS_STQ_R18_R15 (w
) || IS_STQ_R14_R15 (w
)
803 || IS_STL_R14_R15 (w
) || IS_STL_R18_R15 (w
)
804 || IS_ADDIL_SP_MEDIA (w
) || IS_ADDI_SP_MEDIA (w
) || IS_PTABSL_R18 (w
))
808 else if (IS_MOV_SP_FP (w
) || IS_MOV_SP_FP_MEDIA(w
))
816 /* Don't bail out yet, we may have arguments stored in
817 registers here, according to the debug info, so that
818 gdb can print the frames correctly. */
819 start_pc
= look_for_args_moves (here
- insn_size
, media_mode
);
825 int w
= 0xffff & read_memory_integer (here
, insn_size
);
828 if (IS_STS_R0 (w
) || IS_STS_PR (w
)
829 || IS_MOV_TO_R15 (w
) || IS_MOV_R14 (w
)
830 || IS_MOV_R0 (w
) || IS_ADD_SP_R0 (w
) || IS_MOV_R14_R0 (w
))
834 else if (IS_MOV_SP_FP (w
))
842 /* Don't bail out yet, we may have arguments stored in
843 registers here, according to the debug info, so that
844 gdb can print the frames correctly. */
845 start_pc
= look_for_args_moves (here
- insn_size
, media_mode
);
855 sh_skip_prologue (CORE_ADDR pc
)
857 CORE_ADDR post_prologue_pc
;
859 /* See if we can determine the end of the prologue via the symbol table.
860 If so, then return either PC, or the PC after the prologue, whichever
862 post_prologue_pc
= after_prologue (pc
);
864 /* If after_prologue returned a useful address, then use it. Else
865 fall back on the instruction skipping code. */
866 if (post_prologue_pc
!= 0)
867 return max (pc
, post_prologue_pc
);
869 return (skip_prologue_hard_way (pc
));
872 /* Immediately after a function call, return the saved pc.
873 Can't always go through the frames for this because on some machines
874 the new frame is not set up until the new function executes
877 The return address is the value saved in the PR register + 4 */
879 sh_saved_pc_after_call (struct frame_info
*frame
)
881 return (ADDR_BITS_REMOVE (read_register (gdbarch_tdep (current_gdbarch
)->PR_REGNUM
)));
884 /* Should call_function allocate stack space for a struct return? */
886 sh_use_struct_convention (int gcc_p
, struct type
*type
)
888 return (TYPE_LENGTH (type
) > 1);
892 sh64_use_struct_convention (int gcc_p
, struct type
*type
)
894 return (TYPE_LENGTH (type
) > 8);
897 /* Store the address of the place in which to copy the structure the
898 subroutine will return. This is called from call_function.
900 We store structs through a pointer passed in R2 */
902 sh_store_struct_return (CORE_ADDR addr
, CORE_ADDR sp
)
904 write_register (STRUCT_RETURN_REGNUM
, (addr
));
907 /* Disassemble an instruction. */
909 gdb_print_insn_sh (bfd_vma memaddr
, disassemble_info
*info
)
911 info
->endian
= TARGET_BYTE_ORDER
;
912 return print_insn_sh (memaddr
, info
);
915 /* Given a GDB frame, determine the address of the calling function's frame.
916 This will be used to create a new GDB frame struct, and then
917 INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
919 For us, the frame address is its stack pointer value, so we look up
920 the function prologue to determine the caller's sp value, and return it. */
922 sh_frame_chain (struct frame_info
*frame
)
924 if (PC_IN_CALL_DUMMY (frame
->pc
, frame
->frame
, frame
->frame
))
925 return frame
->frame
; /* dummy frame same as caller's frame */
926 if (frame
->pc
&& !inside_entry_file (frame
->pc
))
927 return read_memory_integer (FRAME_FP (frame
) + frame
->extra_info
->f_offset
, 4);
932 /* Given a register number RN as it appears in an assembly
933 instruction, find the corresponding register number in the GDB
936 translate_insn_rn (int rn
, int media_mode
)
938 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
940 /* FIXME: this assumes that the number rn is for a not pseudo
946 /* These registers don't have a corresponding compact one. */
947 /* FIXME: This is probably not enough. */
949 if ((rn
>= 16 && rn
<= 63) || (rn
>= 93 && rn
<= 140))
952 if (rn
>= 0 && rn
<= tdep
->R0_C_REGNUM
)
953 return tdep
->R0_C_REGNUM
+ rn
;
960 sh64_frame_chain (struct frame_info
*frame
)
962 if (PC_IN_CALL_DUMMY (frame
->pc
, frame
->frame
, frame
->frame
))
963 return frame
->frame
; /* dummy frame same as caller's frame */
964 if (frame
->pc
&& !inside_entry_file (frame
->pc
))
966 int media_mode
= pc_is_isa32 (frame
->pc
);
968 if (gdbarch_tdep (current_gdbarch
)->sh_abi
== SH_ABI_32
)
971 size
= REGISTER_RAW_SIZE (translate_insn_rn (FP_REGNUM
, media_mode
));
972 return read_memory_integer (FRAME_FP (frame
) + frame
->extra_info
->f_offset
, size
);
978 /* Find REGNUM on the stack. Otherwise, it's in an active register. One thing
979 we might want to do here is to check REGNUM against the clobber mask, and
980 somehow flag it as invalid if it isn't saved on the stack somewhere. This
981 would provide a graceful failure mode when trying to get the value of
982 caller-saves registers for an inner frame. */
984 sh_find_callers_reg (struct frame_info
*fi
, int regnum
)
986 for (; fi
; fi
= fi
->next
)
987 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
988 /* When the caller requests PR from the dummy frame, we return PC because
989 that's where the previous routine appears to have done a call from. */
990 return generic_read_register_dummy (fi
->pc
, fi
->frame
, regnum
);
993 FRAME_INIT_SAVED_REGS (fi
);
996 if (fi
->saved_regs
[regnum
] != 0)
997 return read_memory_integer (fi
->saved_regs
[regnum
],
998 REGISTER_RAW_SIZE (regnum
));
1000 return read_register (regnum
);
1004 sh64_get_saved_pr (struct frame_info
*fi
, int pr_regnum
)
1008 for (; fi
; fi
= fi
->next
)
1009 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
1010 /* When the caller requests PR from the dummy frame, we return PC because
1011 that's where the previous routine appears to have done a call from. */
1012 return generic_read_register_dummy (fi
->pc
, fi
->frame
, pr_regnum
);
1015 FRAME_INIT_SAVED_REGS (fi
);
1019 media_mode
= pc_is_isa32 (fi
->pc
);
1021 if (fi
->saved_regs
[pr_regnum
] != 0)
1023 int gdb_reg_num
= translate_insn_rn (pr_regnum
, media_mode
);
1024 int size
= ((gdbarch_tdep (current_gdbarch
)->sh_abi
== SH_ABI_32
)
1026 : REGISTER_RAW_SIZE (gdb_reg_num
));
1027 return read_memory_integer (fi
->saved_regs
[pr_regnum
], size
);
1030 return read_register (pr_regnum
);
1033 /* Put here the code to store, into a struct frame_saved_regs, the
1034 addresses of the saved registers of frame described by FRAME_INFO.
1035 This includes special registers such as pc and fp saved in special
1036 ways in the stack frame. sp is even more special: the address we
1037 return for it IS the sp for the next frame. */
1039 sh_nofp_frame_init_saved_regs (struct frame_info
*fi
)
1041 int *where
= (int *) alloca ((NUM_REGS
+ NUM_PSEUDO_REGS
) * sizeof(int));
1049 char *dummy_regs
= deprecated_generic_find_dummy_frame (fi
->pc
, fi
->frame
);
1051 if (fi
->saved_regs
== NULL
)
1052 frame_saved_regs_zalloc (fi
);
1054 memset (fi
->saved_regs
, 0, SIZEOF_FRAME_SAVED_REGS
);
1058 /* DANGER! This is ONLY going to work if the char buffer format of
1059 the saved registers is byte-for-byte identical to the
1060 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
1061 memcpy (fi
->saved_regs
, dummy_regs
, sizeof (fi
->saved_regs
));
1065 fi
->extra_info
->leaf_function
= 1;
1066 fi
->extra_info
->f_offset
= 0;
1068 for (rn
= 0; rn
< NUM_REGS
+ NUM_PSEUDO_REGS
; rn
++)
1073 /* Loop around examining the prologue insns until we find something
1074 that does not appear to be part of the prologue. But give up
1075 after 20 of them, since we're getting silly then. */
1077 pc
= get_pc_function_start (fi
->pc
);
1084 for (opc
= pc
+ (2 * 28); pc
< opc
; pc
+= 2)
1086 insn
= read_memory_integer (pc
, 2);
1087 /* See where the registers will be saved to */
1090 rn
= GET_PUSHED_REG (insn
);
1094 else if (IS_STS (insn
))
1096 where
[gdbarch_tdep (current_gdbarch
)->PR_REGNUM
] = depth
;
1097 /* If we're storing the pr then this isn't a leaf */
1098 fi
->extra_info
->leaf_function
= 0;
1101 else if (IS_MOV_R3 (insn
))
1103 r3_val
= ((insn
& 0xff) ^ 0x80) - 0x80;
1105 else if (IS_SHLL_R3 (insn
))
1109 else if (IS_ADD_R3SP (insn
))
1113 else if (IS_ADD_SP (insn
))
1115 depth
-= ((insn
& 0xff) ^ 0x80) - 0x80;
1117 else if (IS_MOV_SP_FP (insn
))
1119 #if 0 /* This used to just stop when it found an instruction that
1120 was not considered part of the prologue. Now, we just
1121 keep going looking for likely instructions. */
1127 /* Now we know how deep things are, we can work out their addresses */
1129 for (rn
= 0; rn
< NUM_REGS
+ NUM_PSEUDO_REGS
; rn
++)
1133 if (rn
== FP_REGNUM
)
1136 fi
->saved_regs
[rn
] = fi
->frame
- where
[rn
] + depth
- 4;
1140 fi
->saved_regs
[rn
] = 0;
1146 fi
->saved_regs
[SP_REGNUM
] = read_memory_integer (fi
->saved_regs
[FP_REGNUM
], 4);
1150 fi
->saved_regs
[SP_REGNUM
] = fi
->frame
- 4;
1153 fi
->extra_info
->f_offset
= depth
- where
[FP_REGNUM
] - 4;
1154 /* Work out the return pc - either from the saved pr or the pr
1158 /* For vectors of 4 floating point registers. */
1160 fv_reg_base_num (int fv_regnum
)
1164 fp_regnum
= FP0_REGNUM
+
1165 (fv_regnum
- gdbarch_tdep (current_gdbarch
)->FV0_REGNUM
) * 4;
1169 /* For double precision floating point registers, i.e 2 fp regs.*/
1171 dr_reg_base_num (int dr_regnum
)
1175 fp_regnum
= FP0_REGNUM
+
1176 (dr_regnum
- gdbarch_tdep (current_gdbarch
)->DR0_REGNUM
) * 2;
1180 /* For pairs of floating point registers */
1182 fpp_reg_base_num (int fpp_regnum
)
1186 fp_regnum
= FP0_REGNUM
+
1187 (fpp_regnum
- gdbarch_tdep (current_gdbarch
)->FPP0_REGNUM
) * 2;
1192 is_media_pseudo (int rn
)
1194 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1196 return (rn
>= tdep
->DR0_REGNUM
1197 && rn
<= tdep
->FV_LAST_REGNUM
);
1201 sh64_get_gdb_regnum (int gcc_regnum
, CORE_ADDR pc
)
1203 return translate_insn_rn (gcc_regnum
, pc_is_isa32 (pc
));
1207 sh64_media_reg_base_num (int reg_nr
)
1209 int base_regnum
= -1;
1210 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1212 if (reg_nr
>= tdep
->DR0_REGNUM
1213 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
1214 base_regnum
= dr_reg_base_num (reg_nr
);
1216 else if (reg_nr
>= tdep
->FPP0_REGNUM
1217 && reg_nr
<= tdep
->FPP_LAST_REGNUM
)
1218 base_regnum
= fpp_reg_base_num (reg_nr
);
1220 else if (reg_nr
>= tdep
->FV0_REGNUM
1221 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
1222 base_regnum
= fv_reg_base_num (reg_nr
);
1229 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
1230 GDB_REGNUM BASE_REGNUM
1290 sh64_compact_reg_base_num (int reg_nr
)
1292 int base_regnum
= -1;
1293 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1295 /* general register N maps to general register N */
1296 if (reg_nr
>= tdep
->R0_C_REGNUM
1297 && reg_nr
<= tdep
->R_LAST_C_REGNUM
)
1298 base_regnum
= reg_nr
- tdep
->R0_C_REGNUM
;
1300 /* floating point register N maps to floating point register N */
1301 else if (reg_nr
>= tdep
->FP0_C_REGNUM
1302 && reg_nr
<= tdep
->FP_LAST_C_REGNUM
)
1303 base_regnum
= reg_nr
- tdep
->FP0_C_REGNUM
+ FP0_REGNUM
;
1305 /* double prec register N maps to base regnum for double prec register N */
1306 else if (reg_nr
>= tdep
->DR0_C_REGNUM
1307 && reg_nr
<= tdep
->DR_LAST_C_REGNUM
)
1308 base_regnum
= dr_reg_base_num (tdep
->DR0_REGNUM
1309 + reg_nr
- tdep
->DR0_C_REGNUM
);
1311 /* vector N maps to base regnum for vector register N */
1312 else if (reg_nr
>= tdep
->FV0_C_REGNUM
1313 && reg_nr
<= tdep
->FV_LAST_C_REGNUM
)
1314 base_regnum
= fv_reg_base_num (tdep
->FV0_REGNUM
1315 + reg_nr
- tdep
->FV0_C_REGNUM
);
1317 else if (reg_nr
== tdep
->PC_C_REGNUM
)
1318 base_regnum
= PC_REGNUM
;
1320 else if (reg_nr
== tdep
->GBR_C_REGNUM
)
1323 else if (reg_nr
== tdep
->MACH_C_REGNUM
1324 || reg_nr
== tdep
->MACL_C_REGNUM
)
1327 else if (reg_nr
== tdep
->PR_C_REGNUM
)
1330 else if (reg_nr
== tdep
->T_C_REGNUM
)
1333 else if (reg_nr
== tdep
->FPSCR_C_REGNUM
)
1334 base_regnum
= tdep
->FPSCR_REGNUM
; /*???? this register is a mess. */
1336 else if (reg_nr
== tdep
->FPUL_C_REGNUM
)
1337 base_regnum
= FP0_REGNUM
+ 32;
1342 /* Given a register number RN (according to the gdb scheme) , return
1343 its corresponding architectural register. In media mode, only a
1344 subset of the registers is pseudo registers. For compact mode, all
1345 the registers are pseudo. */
1347 translate_rn_to_arch_reg_num (int rn
, int media_mode
)
1352 if (!is_media_pseudo (rn
))
1355 return sh64_media_reg_base_num (rn
);
1358 /* All compact registers are pseudo. */
1359 return sh64_compact_reg_base_num (rn
);
1363 sign_extend (int value
, int bits
)
1365 value
= value
& ((1 << bits
) - 1);
1366 return (value
& (1 << (bits
- 1))
1367 ? value
| (~((1 << bits
) - 1))
1372 sh64_nofp_frame_init_saved_regs (struct frame_info
*fi
)
1374 int *where
= (int *) alloca ((NUM_REGS
+ NUM_PSEUDO_REGS
) * sizeof (int));
1386 int gdb_register_number
;
1387 int register_number
;
1388 char *dummy_regs
= deprecated_generic_find_dummy_frame (fi
->pc
, fi
->frame
);
1389 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1391 if (fi
->saved_regs
== NULL
)
1392 frame_saved_regs_zalloc (fi
);
1394 memset (fi
->saved_regs
, 0, SIZEOF_FRAME_SAVED_REGS
);
1398 /* DANGER! This is ONLY going to work if the char buffer format of
1399 the saved registers is byte-for-byte identical to the
1400 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
1401 memcpy (fi
->saved_regs
, dummy_regs
, sizeof (fi
->saved_regs
));
1405 fi
->extra_info
->leaf_function
= 1;
1406 fi
->extra_info
->f_offset
= 0;
1408 for (rn
= 0; rn
< NUM_REGS
+ NUM_PSEUDO_REGS
; rn
++)
1413 /* Loop around examining the prologue insns until we find something
1414 that does not appear to be part of the prologue. But give up
1415 after 20 of them, since we're getting silly then. */
1417 pc
= get_pc_function_start (fi
->pc
);
1424 if (pc_is_isa32 (pc
))
1435 /* The frame pointer register is general register 14 in shmedia and
1436 shcompact modes. In sh compact it is a pseudo register. Same goes
1437 for the stack pointer register, which is register 15. */
1438 fp_regnum
= translate_insn_rn (FP_REGNUM
, media_mode
);
1439 sp_regnum
= translate_insn_rn (SP_REGNUM
, media_mode
);
1441 for (opc
= pc
+ (insn_size
* 28); pc
< opc
; pc
+= insn_size
)
1443 insn
= read_memory_integer (media_mode
? UNMAKE_ISA32_ADDR (pc
) : pc
,
1446 if (media_mode
== 0)
1448 if (IS_STS_PR (insn
))
1450 int next_insn
= read_memory_integer (pc
+ insn_size
, insn_size
);
1451 if (IS_MOV_TO_R15 (next_insn
))
1453 int reg_nr
= tdep
->PR_C_REGNUM
;
1455 where
[reg_nr
] = depth
- ((((next_insn
& 0xf) ^ 0x8) - 0x8) << 2);
1456 fi
->extra_info
->leaf_function
= 0;
1460 else if (IS_MOV_R14 (insn
))
1462 where
[fp_regnum
] = depth
- ((((insn
& 0xf) ^ 0x8) - 0x8) << 2);
1465 else if (IS_MOV_R0 (insn
))
1467 /* Put in R0 the offset from SP at which to store some
1468 registers. We are interested in this value, because it
1469 will tell us where the given registers are stored within
1471 r0_val
= ((insn
& 0xff) ^ 0x80) - 0x80;
1473 else if (IS_ADD_SP_R0 (insn
))
1475 /* This instruction still prepares r0, but we don't care.
1476 We already have the offset in r0_val. */
1478 else if (IS_STS_R0 (insn
))
1480 /* Store PR at r0_val-4 from SP. Decrement r0 by 4*/
1481 int reg_nr
= tdep
->PR_C_REGNUM
;
1482 where
[reg_nr
] = depth
- (r0_val
- 4);
1484 fi
->extra_info
->leaf_function
= 0;
1486 else if (IS_MOV_R14_R0 (insn
))
1488 /* Store R14 at r0_val-4 from SP. Decrement r0 by 4 */
1489 where
[fp_regnum
] = depth
- (r0_val
- 4);
1493 else if (IS_ADD_SP (insn
))
1495 depth
-= ((insn
& 0xff) ^ 0x80) - 0x80;
1497 else if (IS_MOV_SP_FP (insn
))
1502 if (IS_ADDIL_SP_MEDIA (insn
)
1503 || IS_ADDI_SP_MEDIA (insn
))
1505 depth
-= sign_extend ((((insn
& 0xffc00) ^ 0x80000) - 0x80000) >> 10, 9);
1508 else if (IS_STQ_R18_R15 (insn
))
1510 where
[tdep
->PR_REGNUM
] =
1511 depth
- (sign_extend ((insn
& 0xffc00) >> 10, 9) << 3);
1512 fi
->extra_info
->leaf_function
= 0;
1515 else if (IS_STL_R18_R15 (insn
))
1517 where
[tdep
->PR_REGNUM
] =
1518 depth
- (sign_extend ((insn
& 0xffc00) >> 10, 9) << 2);
1519 fi
->extra_info
->leaf_function
= 0;
1522 else if (IS_STQ_R14_R15 (insn
))
1524 where
[fp_regnum
] = depth
- (sign_extend ((insn
& 0xffc00) >> 10, 9) << 3);
1527 else if (IS_STL_R14_R15 (insn
))
1529 where
[fp_regnum
] = depth
- (sign_extend ((insn
& 0xffc00) >> 10, 9) << 2);
1532 else if (IS_MOV_SP_FP_MEDIA (insn
))
1537 /* Now we know how deep things are, we can work out their addresses. */
1538 for (rn
= 0; rn
< NUM_REGS
+ NUM_PSEUDO_REGS
; rn
++)
1540 register_number
= translate_rn_to_arch_reg_num (rn
, media_mode
);
1544 if (rn
== fp_regnum
)
1547 /* Watch out! saved_regs is only for the real registers, and
1548 doesn't include space for the pseudo registers. */
1549 fi
->saved_regs
[register_number
]= fi
->frame
- where
[rn
] + depth
;
1553 fi
->saved_regs
[register_number
] = 0;
1558 /* SP_REGNUM is 15. For shmedia 15 is the real register. For
1559 shcompact 15 is the arch register corresponding to the pseudo
1560 register r15 which still is the SP register. */
1561 /* The place on the stack where fp is stored contains the sp of
1563 /* Again, saved_registers contains only space for the real registers,
1564 so we store in FP_REGNUM position. */
1566 if (tdep
->sh_abi
== SH_ABI_32
)
1569 size
= REGISTER_RAW_SIZE (fp_regnum
);
1570 fi
->saved_regs
[sp_regnum
] = read_memory_integer (fi
->saved_regs
[fp_regnum
], size
);
1573 fi
->saved_regs
[sp_regnum
] = fi
->frame
;
1575 fi
->extra_info
->f_offset
= depth
- where
[fp_regnum
];
1579 sh_fp_frame_init_saved_regs (struct frame_info
*fi
)
1581 int *where
= (int *) alloca ((NUM_REGS
+ NUM_PSEUDO_REGS
) * sizeof (int));
1589 char *dummy_regs
= deprecated_generic_find_dummy_frame (fi
->pc
, fi
->frame
);
1590 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1592 if (fi
->saved_regs
== NULL
)
1593 frame_saved_regs_zalloc (fi
);
1595 memset (fi
->saved_regs
, 0, SIZEOF_FRAME_SAVED_REGS
);
1599 /* DANGER! This is ONLY going to work if the char buffer format of
1600 the saved registers is byte-for-byte identical to the
1601 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
1602 memcpy (fi
->saved_regs
, dummy_regs
, sizeof (fi
->saved_regs
));
1606 fi
->extra_info
->leaf_function
= 1;
1607 fi
->extra_info
->f_offset
= 0;
1609 for (rn
= 0; rn
< NUM_REGS
+ NUM_PSEUDO_REGS
; rn
++)
1614 /* Loop around examining the prologue insns until we find something
1615 that does not appear to be part of the prologue. But give up
1616 after 20 of them, since we're getting silly then. */
1618 pc
= get_pc_function_start (fi
->pc
);
1625 for (opc
= pc
+ (2 * 28); pc
< opc
; pc
+= 2)
1627 insn
= read_memory_integer (pc
, 2);
1628 /* See where the registers will be saved to */
1631 rn
= GET_PUSHED_REG (insn
);
1635 else if (IS_STS (insn
))
1637 where
[tdep
->PR_REGNUM
] = depth
;
1638 /* If we're storing the pr then this isn't a leaf */
1639 fi
->extra_info
->leaf_function
= 0;
1642 else if (IS_MOV_R3 (insn
))
1644 r3_val
= ((insn
& 0xff) ^ 0x80) - 0x80;
1646 else if (IS_SHLL_R3 (insn
))
1650 else if (IS_ADD_R3SP (insn
))
1654 else if (IS_ADD_SP (insn
))
1656 depth
-= ((insn
& 0xff) ^ 0x80) - 0x80;
1658 else if (IS_FMOV (insn
))
1660 if (read_register (tdep
->FPSCR_REGNUM
) & FPSCR_SZ
)
1669 else if (IS_MOV_SP_FP (insn
))
1671 #if 0 /* This used to just stop when it found an instruction that
1672 was not considered part of the prologue. Now, we just
1673 keep going looking for likely instructions. */
1679 /* Now we know how deep things are, we can work out their addresses */
1681 for (rn
= 0; rn
< NUM_REGS
+ NUM_PSEUDO_REGS
; rn
++)
1685 if (rn
== FP_REGNUM
)
1688 fi
->saved_regs
[rn
] = fi
->frame
- where
[rn
] + depth
- 4;
1692 fi
->saved_regs
[rn
] = 0;
1698 fi
->saved_regs
[SP_REGNUM
] =
1699 read_memory_integer (fi
->saved_regs
[FP_REGNUM
], 4);
1703 fi
->saved_regs
[SP_REGNUM
] = fi
->frame
- 4;
1706 fi
->extra_info
->f_offset
= depth
- where
[FP_REGNUM
] - 4;
1707 /* Work out the return pc - either from the saved pr or the pr
1711 /* Initialize the extra info saved in a FRAME */
1713 sh_init_extra_frame_info (int fromleaf
, struct frame_info
*fi
)
1716 fi
->extra_info
= (struct frame_extra_info
*)
1717 frame_obstack_alloc (sizeof (struct frame_extra_info
));
1720 fi
->pc
= FRAME_SAVED_PC (fi
->next
);
1722 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
1724 /* We need to setup fi->frame here because run_stack_dummy gets it wrong
1725 by assuming it's always FP. */
1726 fi
->frame
= generic_read_register_dummy (fi
->pc
, fi
->frame
,
1728 fi
->extra_info
->return_pc
= generic_read_register_dummy (fi
->pc
,
1731 fi
->extra_info
->f_offset
= -(CALL_DUMMY_LENGTH
+ 4);
1732 fi
->extra_info
->leaf_function
= 0;
1737 FRAME_INIT_SAVED_REGS (fi
);
1738 fi
->extra_info
->return_pc
=
1739 sh_find_callers_reg (fi
, gdbarch_tdep (current_gdbarch
)->PR_REGNUM
);
1744 sh64_init_extra_frame_info (int fromleaf
, struct frame_info
*fi
)
1746 int media_mode
= pc_is_isa32 (fi
->pc
);
1748 fi
->extra_info
= (struct frame_extra_info
*)
1749 frame_obstack_alloc (sizeof (struct frame_extra_info
));
1752 fi
->pc
= FRAME_SAVED_PC (fi
->next
);
1754 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
1756 /* We need to setup fi->frame here because run_stack_dummy gets it wrong
1757 by assuming it's always FP. */
1758 fi
->frame
= generic_read_register_dummy (fi
->pc
, fi
->frame
,
1760 fi
->extra_info
->return_pc
=
1761 generic_read_register_dummy (fi
->pc
, fi
->frame
, PC_REGNUM
);
1762 fi
->extra_info
->f_offset
= -(CALL_DUMMY_LENGTH
+ 4);
1763 fi
->extra_info
->leaf_function
= 0;
1768 FRAME_INIT_SAVED_REGS (fi
);
1769 fi
->extra_info
->return_pc
=
1770 sh64_get_saved_pr (fi
, gdbarch_tdep (current_gdbarch
)->PR_REGNUM
);
1775 sh64_get_saved_register (char *raw_buffer
, int *optimized
, CORE_ADDR
*addrp
,
1776 struct frame_info
*frame
, int regnum
,
1777 enum lval_type
*lval
)
1780 int live_regnum
= regnum
;
1781 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1783 if (!target_has_registers
)
1784 error ("No registers.");
1786 /* Normal systems don't optimize out things with register numbers. */
1787 if (optimized
!= NULL
)
1790 if (addrp
) /* default assumption: not found in memory */
1794 memset (raw_buffer
, 0, sizeof (raw_buffer
));
1796 /* We must do this here, before the following while loop changes
1797 frame, and makes it NULL. If this is a media register number,
1798 but we are in compact mode, it will become the corresponding
1799 compact pseudo register. If there is no corresponding compact
1800 pseudo-register what do we do?*/
1801 media_mode
= pc_is_isa32 (frame
->pc
);
1802 live_regnum
= translate_insn_rn (regnum
, media_mode
);
1804 /* Note: since the current frame's registers could only have been
1805 saved by frames INTERIOR TO the current frame, we skip examining
1806 the current frame itself: otherwise, we would be getting the
1807 previous frame's registers which were saved by the current frame. */
1809 while (frame
&& ((frame
= frame
->next
) != NULL
))
1811 if (PC_IN_CALL_DUMMY (frame
->pc
, frame
->frame
, frame
->frame
))
1813 if (lval
) /* found it in a CALL_DUMMY frame */
1817 (deprecated_generic_find_dummy_frame (frame
->pc
, frame
->frame
)
1818 + REGISTER_BYTE (regnum
)),
1819 REGISTER_RAW_SIZE (regnum
));
1823 FRAME_INIT_SAVED_REGS (frame
);
1824 if (frame
->saved_regs
!= NULL
1825 && frame
->saved_regs
[regnum
] != 0)
1827 if (lval
) /* found it saved on the stack */
1828 *lval
= lval_memory
;
1829 if (regnum
== SP_REGNUM
)
1831 if (raw_buffer
) /* SP register treated specially */
1832 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
),
1833 frame
->saved_regs
[regnum
]);
1836 { /* any other register */
1839 *addrp
= frame
->saved_regs
[regnum
];
1843 if (tdep
->sh_abi
== SH_ABI_32
1844 && (live_regnum
== FP_REGNUM
1845 || live_regnum
== tdep
->PR_REGNUM
))
1848 size
= REGISTER_RAW_SIZE (live_regnum
);
1849 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
1850 read_memory (frame
->saved_regs
[regnum
], raw_buffer
, size
);
1852 read_memory (frame
->saved_regs
[regnum
],
1854 + REGISTER_RAW_SIZE (live_regnum
)
1863 /* If we get thru the loop to this point, it means the register was
1864 not saved in any frame. Return the actual live-register value. */
1866 if (lval
) /* found it in a live register */
1867 *lval
= lval_register
;
1869 *addrp
= REGISTER_BYTE (live_regnum
);
1871 read_register_gen (live_regnum
, raw_buffer
);
1874 /* Extract from an array REGBUF containing the (raw) register state
1875 the address in which a function should return its structure value,
1876 as a CORE_ADDR (or an expression that can be used as one). */
1878 sh_extract_struct_value_address (char *regbuf
)
1880 return (extract_address ((regbuf
), REGISTER_RAW_SIZE (0)));
1884 sh64_extract_struct_value_address (char *regbuf
)
1886 return (extract_address ((regbuf
+ REGISTER_BYTE (STRUCT_RETURN_REGNUM
)),
1887 REGISTER_RAW_SIZE (STRUCT_RETURN_REGNUM
)));
1891 sh_frame_saved_pc (struct frame_info
*frame
)
1893 return ((frame
)->extra_info
->return_pc
);
1896 /* Discard from the stack the innermost frame,
1897 restoring all saved registers. */
1901 register struct frame_info
*frame
= get_current_frame ();
1902 register CORE_ADDR fp
;
1903 register int regnum
;
1905 if (PC_IN_CALL_DUMMY (frame
->pc
, frame
->frame
, frame
->frame
))
1906 generic_pop_dummy_frame ();
1909 fp
= FRAME_FP (frame
);
1910 FRAME_INIT_SAVED_REGS (frame
);
1912 /* Copy regs from where they were saved in the frame */
1913 for (regnum
= 0; regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
1914 if (frame
->saved_regs
[regnum
])
1915 write_register (regnum
,
1916 read_memory_integer (frame
->saved_regs
[regnum
], 4));
1918 write_register (PC_REGNUM
, frame
->extra_info
->return_pc
);
1919 write_register (SP_REGNUM
, fp
+ 4);
1921 flush_cached_frames ();
1924 /* Used in the 'return' command. */
1926 sh64_pop_frame (void)
1928 register struct frame_info
*frame
= get_current_frame ();
1929 register CORE_ADDR fp
;
1930 register int regnum
;
1931 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1933 int media_mode
= pc_is_isa32 (frame
->pc
);
1935 if (PC_IN_CALL_DUMMY (frame
->pc
, frame
->frame
, frame
->frame
))
1936 generic_pop_dummy_frame ();
1939 fp
= FRAME_FP (frame
);
1940 FRAME_INIT_SAVED_REGS (frame
);
1942 /* Copy regs from where they were saved in the frame */
1943 for (regnum
= 0; regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
1944 if (frame
->saved_regs
[regnum
])
1947 if (tdep
->sh_abi
== SH_ABI_32
1948 && (regnum
== FP_REGNUM
1949 || regnum
== tdep
->PR_REGNUM
))
1952 size
= REGISTER_RAW_SIZE (translate_insn_rn (regnum
,
1954 write_register (regnum
,
1955 read_memory_integer (frame
->saved_regs
[regnum
],
1959 write_register (PC_REGNUM
, frame
->extra_info
->return_pc
);
1960 write_register (SP_REGNUM
, fp
+ 8);
1962 flush_cached_frames ();
1965 /* Function: push_arguments
1966 Setup the function arguments for calling a function in the inferior.
1968 On the Hitachi SH architecture, there are four registers (R4 to R7)
1969 which are dedicated for passing function arguments. Up to the first
1970 four arguments (depending on size) may go into these registers.
1971 The rest go on the stack.
1973 Arguments that are smaller than 4 bytes will still take up a whole
1974 register or a whole 32-bit word on the stack, and will be
1975 right-justified in the register or the stack word. This includes
1976 chars, shorts, and small aggregate types.
1978 Arguments that are larger than 4 bytes may be split between two or
1979 more registers. If there are not enough registers free, an argument
1980 may be passed partly in a register (or registers), and partly on the
1981 stack. This includes doubles, long longs, and larger aggregates.
1982 As far as I know, there is no upper limit to the size of aggregates
1983 that will be passed in this way; in other words, the convention of
1984 passing a pointer to a large aggregate instead of a copy is not used.
1986 An exceptional case exists for struct arguments (and possibly other
1987 aggregates such as arrays) if the size is larger than 4 bytes but
1988 not a multiple of 4 bytes. In this case the argument is never split
1989 between the registers and the stack, but instead is copied in its
1990 entirety onto the stack, AND also copied into as many registers as
1991 there is room for. In other words, space in registers permitting,
1992 two copies of the same argument are passed in. As far as I can tell,
1993 only the one on the stack is used, although that may be a function
1994 of the level of compiler optimization. I suspect this is a compiler
1995 bug. Arguments of these odd sizes are left-justified within the
1996 word (as opposed to arguments smaller than 4 bytes, which are
1999 If the function is to return an aggregate type such as a struct, it
2000 is either returned in the normal return value register R0 (if its
2001 size is no greater than one byte), or else the caller must allocate
2002 space into which the callee will copy the return value (if the size
2003 is greater than one byte). In this case, a pointer to the return
2004 value location is passed into the callee in register R2, which does
2005 not displace any of the other arguments passed in via registers R4
2009 sh_push_arguments (int nargs
, struct value
**args
, CORE_ADDR sp
,
2010 int struct_return
, CORE_ADDR struct_addr
)
2012 int stack_offset
, stack_alloc
;
2020 int odd_sized_struct
;
2021 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2023 /* first force sp to a 4-byte alignment */
2026 /* The "struct return pointer" pseudo-argument has its own dedicated
2029 write_register (STRUCT_RETURN_REGNUM
, struct_addr
);
2031 /* Now make sure there's space on the stack */
2032 for (argnum
= 0, stack_alloc
= 0; argnum
< nargs
; argnum
++)
2033 stack_alloc
+= ((TYPE_LENGTH (VALUE_TYPE (args
[argnum
])) + 3) & ~3);
2034 sp
-= stack_alloc
; /* make room on stack for args */
2036 /* Now load as many as possible of the first arguments into
2037 registers, and push the rest onto the stack. There are 16 bytes
2038 in four registers available. Loop thru args from first to last. */
2040 argreg
= tdep
->ARG0_REGNUM
;
2041 for (argnum
= 0, stack_offset
= 0; argnum
< nargs
; argnum
++)
2043 type
= VALUE_TYPE (args
[argnum
]);
2044 len
= TYPE_LENGTH (type
);
2045 memset (valbuf
, 0, sizeof (valbuf
));
2048 /* value gets right-justified in the register or stack word */
2049 memcpy (valbuf
+ (4 - len
),
2050 (char *) VALUE_CONTENTS (args
[argnum
]), len
);
2054 val
= (char *) VALUE_CONTENTS (args
[argnum
]);
2056 if (len
> 4 && (len
& 3) != 0)
2057 odd_sized_struct
= 1; /* such structs go entirely on stack */
2059 odd_sized_struct
= 0;
2062 if (argreg
> tdep
->ARGLAST_REGNUM
2063 || odd_sized_struct
)
2065 /* must go on the stack */
2066 write_memory (sp
+ stack_offset
, val
, 4);
2069 /* NOTE WELL!!!!! This is not an "else if" clause!!!
2070 That's because some *&^%$ things get passed on the stack
2071 AND in the registers! */
2072 if (argreg
<= tdep
->ARGLAST_REGNUM
)
2074 /* there's room in a register */
2075 regval
= extract_address (val
, REGISTER_RAW_SIZE (argreg
));
2076 write_register (argreg
++, regval
);
2078 /* Store the value 4 bytes at a time. This means that things
2079 larger than 4 bytes may go partly in registers and partly
2081 len
-= REGISTER_RAW_SIZE (argreg
);
2082 val
+= REGISTER_RAW_SIZE (argreg
);
2088 /* R2-R9 for integer types and integer equivalent (char, pointers) and
2089 non-scalar (struct, union) elements (even if the elements are
2091 FR0-FR11 for single precision floating point (float)
2092 DR0-DR10 for double precision floating point (double)
2094 If a float is argument number 3 (for instance) and arguments number
2095 1,2, and 4 are integer, the mapping will be:
2096 arg1 -->R2, arg2 --> R3, arg3 -->FR0, arg4 --> R5. I.e. R4 is not used.
2098 If a float is argument number 10 (for instance) and arguments number
2099 1 through 10 are integer, the mapping will be:
2100 arg1->R2, arg2->R3, arg3->R4, arg4->R5, arg5->R6, arg6->R7, arg7->R8,
2101 arg8->R9, arg9->(0,SP)stack(8-byte aligned), arg10->FR0, arg11->stack(16,SP).
2102 I.e. there is hole in the stack.
2104 Different rules apply for variable arguments functions, and for functions
2105 for which the prototype is not known. */
2108 sh64_push_arguments (int nargs
, struct value
**args
, CORE_ADDR sp
,
2109 int struct_return
, CORE_ADDR struct_addr
)
2111 int stack_offset
, stack_alloc
;
2115 int float_arg_index
= 0;
2116 int double_arg_index
= 0;
2126 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2128 memset (fp_args
, 0, sizeof (fp_args
));
2130 /* first force sp to a 8-byte alignment */
2133 /* The "struct return pointer" pseudo-argument has its own dedicated
2137 write_register (STRUCT_RETURN_REGNUM
, struct_addr
);
2139 /* Now make sure there's space on the stack */
2140 for (argnum
= 0, stack_alloc
= 0; argnum
< nargs
; argnum
++)
2141 stack_alloc
+= ((TYPE_LENGTH (VALUE_TYPE (args
[argnum
])) + 7) & ~7);
2142 sp
-= stack_alloc
; /* make room on stack for args */
2144 /* Now load as many as possible of the first arguments into
2145 registers, and push the rest onto the stack. There are 64 bytes
2146 in eight registers available. Loop thru args from first to last. */
2148 int_argreg
= tdep
->ARG0_REGNUM
;
2149 float_argreg
= FP0_REGNUM
;
2150 double_argreg
= tdep
->DR0_REGNUM
;
2152 for (argnum
= 0, stack_offset
= 0; argnum
< nargs
; argnum
++)
2154 type
= VALUE_TYPE (args
[argnum
]);
2155 len
= TYPE_LENGTH (type
);
2156 memset (valbuf
, 0, sizeof (valbuf
));
2158 if (TYPE_CODE (type
) != TYPE_CODE_FLT
)
2160 argreg_size
= REGISTER_RAW_SIZE (int_argreg
);
2162 if (len
< argreg_size
)
2164 /* value gets right-justified in the register or stack word */
2165 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2166 memcpy (valbuf
+ argreg_size
- len
,
2167 (char *) VALUE_CONTENTS (args
[argnum
]), len
);
2169 memcpy (valbuf
, (char *) VALUE_CONTENTS (args
[argnum
]), len
);
2174 val
= (char *) VALUE_CONTENTS (args
[argnum
]);
2178 if (int_argreg
> tdep
->ARGLAST_REGNUM
)
2180 /* must go on the stack */
2181 write_memory (sp
+ stack_offset
, val
, argreg_size
);
2182 stack_offset
+= 8;/*argreg_size;*/
2184 /* NOTE WELL!!!!! This is not an "else if" clause!!!
2185 That's because some *&^%$ things get passed on the stack
2186 AND in the registers! */
2187 if (int_argreg
<= tdep
->ARGLAST_REGNUM
)
2189 /* there's room in a register */
2190 regval
= extract_address (val
, argreg_size
);
2191 write_register (int_argreg
, regval
);
2193 /* Store the value 8 bytes at a time. This means that
2194 things larger than 8 bytes may go partly in registers
2195 and partly on the stack. FIXME: argreg is incremented
2196 before we use its size. */
2204 val
= (char *) VALUE_CONTENTS (args
[argnum
]);
2207 /* Where is it going to be stored? */
2208 while (fp_args
[float_arg_index
])
2211 /* Now float_argreg points to the register where it
2212 should be stored. Are we still within the allowed
2214 if (float_arg_index
<= tdep
->FLOAT_ARGLAST_REGNUM
)
2216 /* Goes in FR0...FR11 */
2217 write_register_gen (FP0_REGNUM
+ float_arg_index
, val
);
2218 fp_args
[float_arg_index
] = 1;
2219 /* Skip the corresponding general argument register. */
2224 /* Store it as the integers, 8 bytes at the time, if
2225 necessary spilling on the stack. */
2230 /* Where is it going to be stored? */
2231 while (fp_args
[double_arg_index
])
2232 double_arg_index
+= 2;
2233 /* Now double_argreg points to the register
2234 where it should be stored.
2235 Are we still within the allowed register set? */
2236 if (double_arg_index
< tdep
->FLOAT_ARGLAST_REGNUM
)
2238 /* Goes in DR0...DR10 */
2239 /* The numbering of the DRi registers is consecutive,
2240 i.e. includes odd numbers. */
2241 int double_register_offset
= double_arg_index
/ 2;
2242 int regnum
= tdep
->DR0_REGNUM
+
2243 double_register_offset
;
2245 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
2247 memset (valbuf_tmp
, 0, sizeof (valbuf_tmp
));
2248 REGISTER_CONVERT_TO_VIRTUAL (regnum
,
2249 type
, val
, valbuf_tmp
);
2253 /* Note: must use write_register_gen here instead
2254 of regcache_write, because regcache_write works
2255 only for real registers, not pseudo.
2256 write_register_gen will call the gdbarch
2257 function to do register writes, and that will
2258 properly know how to deal with pseudoregs. */
2259 write_register_gen (regnum
, val
);
2260 fp_args
[double_arg_index
] = 1;
2261 fp_args
[double_arg_index
+ 1] = 1;
2262 /* Skip the corresponding general argument register. */
2267 /* Store it as the integers, 8 bytes at the time, if
2268 necessary spilling on the stack. */
2275 /* Function: push_return_address (pc)
2276 Set up the return address for the inferior function call.
2277 Needed for targets where we don't actually execute a JSR/BSR instruction */
2280 sh_push_return_address (CORE_ADDR pc
, CORE_ADDR sp
)
2282 write_register (gdbarch_tdep (current_gdbarch
)->PR_REGNUM
,
2283 CALL_DUMMY_ADDRESS ());
2287 /* Function: fix_call_dummy
2288 Poke the callee function's address into the destination part of
2289 the CALL_DUMMY. The address is actually stored in a data word
2290 following the actualy CALL_DUMMY instructions, which will load
2291 it into a register using PC-relative addressing. This function
2292 expects the CALL_DUMMY to look like this:
2303 sh_fix_call_dummy (char *dummy
, CORE_ADDR pc
, CORE_ADDR fun
, int nargs
,
2304 struct value
**args
, struct type
*type
, int gcc_p
)
2306 *(unsigned long *) (dummy
+ 8) = fun
;
2311 sh_coerce_float_to_double (struct type
*formal
, struct type
*actual
)
2316 /* Find a function's return value in the appropriate registers (in
2317 regbuf), and copy it into valbuf. Extract from an array REGBUF
2318 containing the (raw) register state a function return value of type
2319 TYPE, and copy that, in virtual format, into VALBUF. */
2321 sh_extract_return_value (struct type
*type
, char *regbuf
, char *valbuf
)
2323 int len
= TYPE_LENGTH (type
);
2324 int return_register
= R0_REGNUM
;
2329 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2330 offset
= REGISTER_BYTE (return_register
) + 4 - len
;
2332 offset
= REGISTER_BYTE (return_register
);
2333 memcpy (valbuf
, regbuf
+ offset
, len
);
2337 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2338 offset
= REGISTER_BYTE (return_register
) + 8 - len
;
2340 offset
= REGISTER_BYTE (return_register
);
2341 memcpy (valbuf
, regbuf
+ offset
, len
);
2344 error ("bad size for return value");
2348 sh3e_sh4_extract_return_value (struct type
*type
, char *regbuf
, char *valbuf
)
2350 int return_register
;
2352 int len
= TYPE_LENGTH (type
);
2354 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2355 return_register
= FP0_REGNUM
;
2357 return_register
= R0_REGNUM
;
2359 if (len
== 8 && TYPE_CODE (type
) == TYPE_CODE_FLT
)
2362 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
2363 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword
,
2364 (char *) regbuf
+ REGISTER_BYTE (return_register
),
2367 floatformat_to_doublest (&floatformat_ieee_double_big
,
2368 (char *) regbuf
+ REGISTER_BYTE (return_register
),
2370 store_floating (valbuf
, len
, val
);
2374 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2375 offset
= REGISTER_BYTE (return_register
) + 4 - len
;
2377 offset
= REGISTER_BYTE (return_register
);
2378 memcpy (valbuf
, regbuf
+ offset
, len
);
2382 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2383 offset
= REGISTER_BYTE (return_register
) + 8 - len
;
2385 offset
= REGISTER_BYTE (return_register
);
2386 memcpy (valbuf
, regbuf
+ offset
, len
);
2389 error ("bad size for return value");
2393 sh64_extract_return_value (struct type
*type
, char *regbuf
, char *valbuf
)
2396 int return_register
;
2397 int len
= TYPE_LENGTH (type
);
2398 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2400 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2404 /* Return value stored in FP0_REGNUM */
2405 return_register
= FP0_REGNUM
;
2406 offset
= REGISTER_BYTE (return_register
);
2407 memcpy (valbuf
, (char *) regbuf
+ offset
, len
);
2411 /* return value stored in DR0_REGNUM */
2414 return_register
= tdep
->DR0_REGNUM
;
2415 offset
= REGISTER_BYTE (return_register
);
2417 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
2418 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword
,
2419 (char *) regbuf
+ offset
, &val
);
2421 floatformat_to_doublest (&floatformat_ieee_double_big
,
2422 (char *) regbuf
+ offset
, &val
);
2423 store_floating (valbuf
, len
, val
);
2430 /* Result is in register 2. If smaller than 8 bytes, it is padded
2431 at the most significant end. */
2432 return_register
= tdep
->RETURN_REGNUM
;
2433 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2434 offset
= REGISTER_BYTE (return_register
) +
2435 REGISTER_RAW_SIZE (return_register
) - len
;
2437 offset
= REGISTER_BYTE (return_register
);
2438 memcpy (valbuf
, (char *) regbuf
+ offset
, len
);
2441 error ("bad size for return value");
2445 /* Write into appropriate registers a function return value
2446 of type TYPE, given in virtual format.
2447 If the architecture is sh4 or sh3e, store a function's return value
2448 in the R0 general register or in the FP0 floating point register,
2449 depending on the type of the return value. In all the other cases
2450 the result is stored in r0, left-justified. */
2452 sh_default_store_return_value (struct type
*type
, char *valbuf
)
2454 char buf
[32]; /* more than enough... */
2456 if (TYPE_LENGTH (type
) < REGISTER_RAW_SIZE (R0_REGNUM
))
2458 /* Add leading zeros to the value. */
2459 memset (buf
, 0, REGISTER_RAW_SIZE (R0_REGNUM
));
2460 memcpy (buf
+ REGISTER_RAW_SIZE (R0_REGNUM
) - TYPE_LENGTH (type
),
2461 valbuf
, TYPE_LENGTH (type
));
2462 write_register_bytes (REGISTER_BYTE (R0_REGNUM
), buf
,
2463 REGISTER_RAW_SIZE (R0_REGNUM
));
2466 write_register_bytes (REGISTER_BYTE (R0_REGNUM
), valbuf
,
2467 TYPE_LENGTH (type
));
2471 sh3e_sh4_store_return_value (struct type
*type
, char *valbuf
)
2473 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2474 write_register_bytes (REGISTER_BYTE (FP0_REGNUM
),
2475 valbuf
, TYPE_LENGTH (type
));
2477 sh_default_store_return_value (type
, valbuf
);
2481 sh64_store_return_value (struct type
*type
, char *valbuf
)
2483 char buf
[64]; /* more than enough... */
2484 int len
= TYPE_LENGTH (type
);
2486 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2490 /* Return value stored in FP0_REGNUM */
2491 write_register_gen (FP0_REGNUM
, valbuf
);
2495 /* return value stored in DR0_REGNUM */
2496 /* FIXME: Implement */
2501 int return_register
= gdbarch_tdep (current_gdbarch
)->RETURN_REGNUM
;
2504 if (len
<= REGISTER_RAW_SIZE (return_register
))
2506 /* Pad with zeros. */
2507 memset (buf
, 0, REGISTER_RAW_SIZE (return_register
));
2508 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
2509 offset
= 0; /*REGISTER_RAW_SIZE (return_register) - len;*/
2511 offset
= REGISTER_RAW_SIZE (return_register
) - len
;
2513 memcpy (buf
+ offset
, valbuf
, len
);
2514 write_register_gen (return_register
, buf
);
2517 write_register_gen (return_register
, valbuf
);
2521 /* Print the registers in a form similar to the E7000 */
2524 sh_generic_show_regs (void)
2526 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2528 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2529 paddr (read_register (PC_REGNUM
)),
2530 (long) read_register (tdep
->SR_REGNUM
),
2531 (long) read_register (tdep
->PR_REGNUM
),
2532 (long) read_register (MACH_REGNUM
),
2533 (long) read_register (MACL_REGNUM
));
2535 printf_filtered ("GBR=%08lx VBR=%08lx",
2536 (long) read_register (GBR_REGNUM
),
2537 (long) read_register (VBR_REGNUM
));
2539 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2540 (long) read_register (0),
2541 (long) read_register (1),
2542 (long) read_register (2),
2543 (long) read_register (3),
2544 (long) read_register (4),
2545 (long) read_register (5),
2546 (long) read_register (6),
2547 (long) read_register (7));
2548 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2549 (long) read_register (8),
2550 (long) read_register (9),
2551 (long) read_register (10),
2552 (long) read_register (11),
2553 (long) read_register (12),
2554 (long) read_register (13),
2555 (long) read_register (14),
2556 (long) read_register (15));
2560 sh3_show_regs (void)
2562 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2564 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2565 paddr (read_register (PC_REGNUM
)),
2566 (long) read_register (tdep
->SR_REGNUM
),
2567 (long) read_register (tdep
->PR_REGNUM
),
2568 (long) read_register (MACH_REGNUM
),
2569 (long) read_register (MACL_REGNUM
));
2571 printf_filtered ("GBR=%08lx VBR=%08lx",
2572 (long) read_register (GBR_REGNUM
),
2573 (long) read_register (VBR_REGNUM
));
2574 printf_filtered (" SSR=%08lx SPC=%08lx",
2575 (long) read_register (tdep
->SSR_REGNUM
),
2576 (long) read_register (tdep
->SPC_REGNUM
));
2578 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2579 (long) read_register (0),
2580 (long) read_register (1),
2581 (long) read_register (2),
2582 (long) read_register (3),
2583 (long) read_register (4),
2584 (long) read_register (5),
2585 (long) read_register (6),
2586 (long) read_register (7));
2587 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2588 (long) read_register (8),
2589 (long) read_register (9),
2590 (long) read_register (10),
2591 (long) read_register (11),
2592 (long) read_register (12),
2593 (long) read_register (13),
2594 (long) read_register (14),
2595 (long) read_register (15));
2600 sh3e_show_regs (void)
2602 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2604 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2605 paddr (read_register (PC_REGNUM
)),
2606 (long) read_register (tdep
->SR_REGNUM
),
2607 (long) read_register (tdep
->PR_REGNUM
),
2608 (long) read_register (MACH_REGNUM
),
2609 (long) read_register (MACL_REGNUM
));
2611 printf_filtered ("GBR=%08lx VBR=%08lx",
2612 (long) read_register (GBR_REGNUM
),
2613 (long) read_register (VBR_REGNUM
));
2614 printf_filtered (" SSR=%08lx SPC=%08lx",
2615 (long) read_register (tdep
->SSR_REGNUM
),
2616 (long) read_register (tdep
->SPC_REGNUM
));
2617 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
2618 (long) read_register (tdep
->FPUL_REGNUM
),
2619 (long) read_register (tdep
->FPSCR_REGNUM
));
2621 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2622 (long) read_register (0),
2623 (long) read_register (1),
2624 (long) read_register (2),
2625 (long) read_register (3),
2626 (long) read_register (4),
2627 (long) read_register (5),
2628 (long) read_register (6),
2629 (long) read_register (7));
2630 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2631 (long) read_register (8),
2632 (long) read_register (9),
2633 (long) read_register (10),
2634 (long) read_register (11),
2635 (long) read_register (12),
2636 (long) read_register (13),
2637 (long) read_register (14),
2638 (long) read_register (15));
2640 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2641 (long) read_register (FP0_REGNUM
+ 0),
2642 (long) read_register (FP0_REGNUM
+ 1),
2643 (long) read_register (FP0_REGNUM
+ 2),
2644 (long) read_register (FP0_REGNUM
+ 3),
2645 (long) read_register (FP0_REGNUM
+ 4),
2646 (long) read_register (FP0_REGNUM
+ 5),
2647 (long) read_register (FP0_REGNUM
+ 6),
2648 (long) read_register (FP0_REGNUM
+ 7));
2649 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2650 (long) read_register (FP0_REGNUM
+ 8),
2651 (long) read_register (FP0_REGNUM
+ 9),
2652 (long) read_register (FP0_REGNUM
+ 10),
2653 (long) read_register (FP0_REGNUM
+ 11),
2654 (long) read_register (FP0_REGNUM
+ 12),
2655 (long) read_register (FP0_REGNUM
+ 13),
2656 (long) read_register (FP0_REGNUM
+ 14),
2657 (long) read_register (FP0_REGNUM
+ 15));
2661 sh3_dsp_show_regs (void)
2663 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2665 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2666 paddr (read_register (PC_REGNUM
)),
2667 (long) read_register (tdep
->SR_REGNUM
),
2668 (long) read_register (tdep
->PR_REGNUM
),
2669 (long) read_register (MACH_REGNUM
),
2670 (long) read_register (MACL_REGNUM
));
2672 printf_filtered ("GBR=%08lx VBR=%08lx",
2673 (long) read_register (GBR_REGNUM
),
2674 (long) read_register (VBR_REGNUM
));
2676 printf_filtered (" SSR=%08lx SPC=%08lx",
2677 (long) read_register (tdep
->SSR_REGNUM
),
2678 (long) read_register (tdep
->SPC_REGNUM
));
2680 printf_filtered (" DSR=%08lx",
2681 (long) read_register (tdep
->DSR_REGNUM
));
2683 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2684 (long) read_register (0),
2685 (long) read_register (1),
2686 (long) read_register (2),
2687 (long) read_register (3),
2688 (long) read_register (4),
2689 (long) read_register (5),
2690 (long) read_register (6),
2691 (long) read_register (7));
2692 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2693 (long) read_register (8),
2694 (long) read_register (9),
2695 (long) read_register (10),
2696 (long) read_register (11),
2697 (long) read_register (12),
2698 (long) read_register (13),
2699 (long) read_register (14),
2700 (long) read_register (15));
2702 printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
2703 (long) read_register (tdep
->A0G_REGNUM
) & 0xff,
2704 (long) read_register (tdep
->A0_REGNUM
),
2705 (long) read_register (tdep
->M0_REGNUM
),
2706 (long) read_register (tdep
->X0_REGNUM
),
2707 (long) read_register (tdep
->Y0_REGNUM
),
2708 (long) read_register (tdep
->RS_REGNUM
),
2709 (long) read_register (tdep
->MOD_REGNUM
));
2710 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
2711 (long) read_register (tdep
->A1G_REGNUM
) & 0xff,
2712 (long) read_register (tdep
->A1_REGNUM
),
2713 (long) read_register (tdep
->M1_REGNUM
),
2714 (long) read_register (tdep
->X1_REGNUM
),
2715 (long) read_register (tdep
->Y1_REGNUM
),
2716 (long) read_register (tdep
->RE_REGNUM
));
2720 sh4_show_regs (void)
2722 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2724 int pr
= read_register (tdep
->FPSCR_REGNUM
) & 0x80000;
2725 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2726 paddr (read_register (PC_REGNUM
)),
2727 (long) read_register (tdep
->SR_REGNUM
),
2728 (long) read_register (tdep
->PR_REGNUM
),
2729 (long) read_register (MACH_REGNUM
),
2730 (long) read_register (MACL_REGNUM
));
2732 printf_filtered ("GBR=%08lx VBR=%08lx",
2733 (long) read_register (GBR_REGNUM
),
2734 (long) read_register (VBR_REGNUM
));
2735 printf_filtered (" SSR=%08lx SPC=%08lx",
2736 (long) read_register (tdep
->SSR_REGNUM
),
2737 (long) read_register (tdep
->SPC_REGNUM
));
2738 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
2739 (long) read_register (tdep
->FPUL_REGNUM
),
2740 (long) read_register (tdep
->FPSCR_REGNUM
));
2742 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2743 (long) read_register (0),
2744 (long) read_register (1),
2745 (long) read_register (2),
2746 (long) read_register (3),
2747 (long) read_register (4),
2748 (long) read_register (5),
2749 (long) read_register (6),
2750 (long) read_register (7));
2751 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2752 (long) read_register (8),
2753 (long) read_register (9),
2754 (long) read_register (10),
2755 (long) read_register (11),
2756 (long) read_register (12),
2757 (long) read_register (13),
2758 (long) read_register (14),
2759 (long) read_register (15));
2761 printf_filtered ((pr
2762 ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
2763 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2764 (long) read_register (FP0_REGNUM
+ 0),
2765 (long) read_register (FP0_REGNUM
+ 1),
2766 (long) read_register (FP0_REGNUM
+ 2),
2767 (long) read_register (FP0_REGNUM
+ 3),
2768 (long) read_register (FP0_REGNUM
+ 4),
2769 (long) read_register (FP0_REGNUM
+ 5),
2770 (long) read_register (FP0_REGNUM
+ 6),
2771 (long) read_register (FP0_REGNUM
+ 7));
2772 printf_filtered ((pr
2773 ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
2774 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2775 (long) read_register (FP0_REGNUM
+ 8),
2776 (long) read_register (FP0_REGNUM
+ 9),
2777 (long) read_register (FP0_REGNUM
+ 10),
2778 (long) read_register (FP0_REGNUM
+ 11),
2779 (long) read_register (FP0_REGNUM
+ 12),
2780 (long) read_register (FP0_REGNUM
+ 13),
2781 (long) read_register (FP0_REGNUM
+ 14),
2782 (long) read_register (FP0_REGNUM
+ 15));
2786 sh_dsp_show_regs (void)
2788 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2790 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2791 paddr (read_register (PC_REGNUM
)),
2792 (long) read_register (tdep
->SR_REGNUM
),
2793 (long) read_register (tdep
->PR_REGNUM
),
2794 (long) read_register (MACH_REGNUM
),
2795 (long) read_register (MACL_REGNUM
));
2797 printf_filtered ("GBR=%08lx VBR=%08lx",
2798 (long) read_register (GBR_REGNUM
),
2799 (long) read_register (VBR_REGNUM
));
2801 printf_filtered (" DSR=%08lx",
2802 (long) read_register (tdep
->DSR_REGNUM
));
2804 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2805 (long) read_register (0),
2806 (long) read_register (1),
2807 (long) read_register (2),
2808 (long) read_register (3),
2809 (long) read_register (4),
2810 (long) read_register (5),
2811 (long) read_register (6),
2812 (long) read_register (7));
2813 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2814 (long) read_register (8),
2815 (long) read_register (9),
2816 (long) read_register (10),
2817 (long) read_register (11),
2818 (long) read_register (12),
2819 (long) read_register (13),
2820 (long) read_register (14),
2821 (long) read_register (15));
2823 printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
2824 (long) read_register (tdep
->A0G_REGNUM
) & 0xff,
2825 (long) read_register (tdep
->A0_REGNUM
),
2826 (long) read_register (tdep
->M0_REGNUM
),
2827 (long) read_register (tdep
->X0_REGNUM
),
2828 (long) read_register (tdep
->Y0_REGNUM
),
2829 (long) read_register (tdep
->RS_REGNUM
),
2830 (long) read_register (tdep
->MOD_REGNUM
));
2831 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
2832 (long) read_register (tdep
->A1G_REGNUM
) & 0xff,
2833 (long) read_register (tdep
->A1_REGNUM
),
2834 (long) read_register (tdep
->M1_REGNUM
),
2835 (long) read_register (tdep
->X1_REGNUM
),
2836 (long) read_register (tdep
->Y1_REGNUM
),
2837 (long) read_register (tdep
->RE_REGNUM
));
2841 sh64_show_media_regs (void)
2844 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2846 printf_filtered ("PC=%s SR=%016llx \n",
2847 paddr (read_register (PC_REGNUM
)),
2848 (long long) read_register (tdep
->SR_REGNUM
));
2850 printf_filtered ("SSR=%016llx SPC=%016llx \n",
2851 (long long) read_register (tdep
->SSR_REGNUM
),
2852 (long long) read_register (tdep
->SPC_REGNUM
));
2853 printf_filtered ("FPSCR=%016lx\n ",
2854 (long) read_register (tdep
->FPSCR_REGNUM
));
2856 for (i
= 0; i
< 64; i
= i
+ 4)
2857 printf_filtered ("\nR%d-R%d %016llx %016llx %016llx %016llx\n",
2859 (long long) read_register (i
+ 0),
2860 (long long) read_register (i
+ 1),
2861 (long long) read_register (i
+ 2),
2862 (long long) read_register (i
+ 3));
2864 printf_filtered ("\n");
2866 for (i
= 0; i
< 64; i
= i
+ 8)
2867 printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2869 (long) read_register (FP0_REGNUM
+ i
+ 0),
2870 (long) read_register (FP0_REGNUM
+ i
+ 1),
2871 (long) read_register (FP0_REGNUM
+ i
+ 2),
2872 (long) read_register (FP0_REGNUM
+ i
+ 3),
2873 (long) read_register (FP0_REGNUM
+ i
+ 4),
2874 (long) read_register (FP0_REGNUM
+ i
+ 5),
2875 (long) read_register (FP0_REGNUM
+ i
+ 6),
2876 (long) read_register (FP0_REGNUM
+ i
+ 7));
2880 sh64_show_compact_regs (void)
2883 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2885 printf_filtered ("PC=%s \n",
2886 paddr (read_register (tdep
->PC_C_REGNUM
)));
2888 printf_filtered ("GBR=%08lx MACH=%08lx MACL=%08lx PR=%08lx T=%08lx\n",
2889 (long) read_register (tdep
->GBR_C_REGNUM
),
2890 (long) read_register (tdep
->MACH_C_REGNUM
),
2891 (long) read_register (tdep
->MACL_C_REGNUM
),
2892 (long) read_register (tdep
->PR_C_REGNUM
),
2893 (long) read_register (tdep
->T_C_REGNUM
));
2894 printf_filtered ("FPSCR=%08lx FPUL=%08lx\n",
2895 (long) read_register (tdep
->FPSCR_REGNUM
),
2896 (long) read_register (tdep
->FPUL_REGNUM
));
2898 for (i
= 0; i
< 16; i
= i
+ 4)
2899 printf_filtered ("\nR%d-R%d %08lx %08lx %08lx %08lx\n",
2901 (long) read_register (i
+ 0),
2902 (long) read_register (i
+ 1),
2903 (long) read_register (i
+ 2),
2904 (long) read_register (i
+ 3));
2906 printf_filtered ("\n");
2908 for (i
= 0; i
< 16; i
= i
+ 8)
2909 printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2911 (long) read_register (FP0_REGNUM
+ i
+ 0),
2912 (long) read_register (FP0_REGNUM
+ i
+ 1),
2913 (long) read_register (FP0_REGNUM
+ i
+ 2),
2914 (long) read_register (FP0_REGNUM
+ i
+ 3),
2915 (long) read_register (FP0_REGNUM
+ i
+ 4),
2916 (long) read_register (FP0_REGNUM
+ i
+ 5),
2917 (long) read_register (FP0_REGNUM
+ i
+ 6),
2918 (long) read_register (FP0_REGNUM
+ i
+ 7));
2921 /*FIXME!!! This only shows the registers for shmedia, excluding the
2922 pseudo registers. */
2924 sh64_show_regs (void)
2926 if (pc_is_isa32 (selected_frame
->pc
))
2927 sh64_show_media_regs ();
2929 sh64_show_compact_regs ();
2932 void sh_show_regs_command (char *args
, int from_tty
)
2938 /* Index within `registers' of the first byte of the space for
2941 sh_default_register_byte (int reg_nr
)
2943 return (reg_nr
* 4);
2947 sh_sh4_register_byte (int reg_nr
)
2949 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2951 if (reg_nr
>= tdep
->DR0_REGNUM
2952 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
2953 return (dr_reg_base_num (reg_nr
) * 4);
2954 else if (reg_nr
>= tdep
->FV0_REGNUM
2955 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
2956 return (fv_reg_base_num (reg_nr
) * 4);
2958 return (reg_nr
* 4);
2963 SH MEDIA MODE (ISA 32)
2964 general registers (64-bit) 0-63
2965 0 r0, r1, r2, r3, r4, r5, r6, r7,
2966 64 r8, r9, r10, r11, r12, r13, r14, r15,
2967 128 r16, r17, r18, r19, r20, r21, r22, r23,
2968 192 r24, r25, r26, r27, r28, r29, r30, r31,
2969 256 r32, r33, r34, r35, r36, r37, r38, r39,
2970 320 r40, r41, r42, r43, r44, r45, r46, r47,
2971 384 r48, r49, r50, r51, r52, r53, r54, r55,
2972 448 r56, r57, r58, r59, r60, r61, r62, r63,
2977 status reg., saved status reg., saved pc reg. (64-bit) 65-67
2980 target registers (64-bit) 68-75
2981 544 tr0, tr1, tr2, tr3, tr4, tr5, tr6, tr7,
2983 floating point state control register (32-bit) 76
2986 single precision floating point registers (32-bit) 77-140
2987 612 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
2988 644 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15,
2989 676 fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23,
2990 708 fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31,
2991 740 fr32, fr33, fr34, fr35, fr36, fr37, fr38, fr39,
2992 772 fr40, fr41, fr42, fr43, fr44, fr45, fr46, fr47,
2993 804 fr48, fr49, fr50, fr51, fr52, fr53, fr54, fr55,
2994 836 fr56, fr57, fr58, fr59, fr60, fr61, fr62, fr63,
2996 TOTAL SPACE FOR REGISTERS: 868 bytes
2998 From here on they are all pseudo registers: no memory allocated.
2999 REGISTER_BYTE returns the register byte for the base register.
3001 double precision registers (pseudo) 141-172
3002 dr0, dr2, dr4, dr6, dr8, dr10, dr12, dr14,
3003 dr16, dr18, dr20, dr22, dr24, dr26, dr28, dr30,
3004 dr32, dr34, dr36, dr38, dr40, dr42, dr44, dr46,
3005 dr48, dr50, dr52, dr54, dr56, dr58, dr60, dr62,
3007 floating point pairs (pseudo) 173-204
3008 fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14,
3009 fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30,
3010 fp32, fp34, fp36, fp38, fp40, fp42, fp44, fp46,
3011 fp48, fp50, fp52, fp54, fp56, fp58, fp60, fp62,
3013 floating point vectors (4 floating point regs) (pseudo) 205-220
3014 fv0, fv4, fv8, fv12, fv16, fv20, fv24, fv28,
3015 fv32, fv36, fv40, fv44, fv48, fv52, fv56, fv60,
3017 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
3018 r0_c, r1_c, r2_c, r3_c, r4_c, r5_c, r6_c, r7_c,
3019 r8_c, r9_c, r10_c, r11_c, r12_c, r13_c, r14_c, r15_c,
3021 gbr_c, mach_c, macl_c, pr_c, t_c,
3023 fr0_c, fr1_c, fr2_c, fr3_c, fr4_c, fr5_c, fr6_c, fr7_c,
3024 fr8_c, fr9_c, fr10_c, fr11_c, fr12_c, fr13_c, fr14_c, fr15_c
3025 dr0_c, dr2_c, dr4_c, dr6_c, dr8_c, dr10_c, dr12_c, dr14_c
3026 fv0_c, fv4_c, fv8_c, fv12_c
3030 sh_sh64_register_byte (int reg_nr
)
3032 int base_regnum
= -1;
3033 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3035 /* If it is a pseudo register, get the number of the first floating
3036 point register that is part of it. */
3037 if (reg_nr
>= tdep
->DR0_REGNUM
3038 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3039 base_regnum
= dr_reg_base_num (reg_nr
);
3041 else if (reg_nr
>= tdep
->FPP0_REGNUM
3042 && reg_nr
<= tdep
->FPP_LAST_REGNUM
)
3043 base_regnum
= fpp_reg_base_num (reg_nr
);
3045 else if (reg_nr
>= tdep
->FV0_REGNUM
3046 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3047 base_regnum
= fv_reg_base_num (reg_nr
);
3049 /* sh compact pseudo register. FPSCR is a pathological case, need to
3050 treat it as special. */
3051 else if ((reg_nr
>= tdep
->R0_C_REGNUM
3052 && reg_nr
<= tdep
->FV_LAST_C_REGNUM
)
3053 && reg_nr
!= tdep
->FPSCR_C_REGNUM
)
3054 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3056 /* Now return the offset in bytes within the register cache. */
3057 /* sh media pseudo register, i.e. any of DR, FFP, FV registers. */
3058 if (reg_nr
>= tdep
->DR0_REGNUM
3059 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3060 return (base_regnum
- FP0_REGNUM
+ 1) * 4
3061 + (tdep
->TR7_REGNUM
+ 1) * 8;
3063 /* sh compact pseudo register: general register */
3064 if ((reg_nr
>= tdep
->R0_C_REGNUM
3065 && reg_nr
<= tdep
->R_LAST_C_REGNUM
))
3066 return (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3067 ? base_regnum
* 8 + 4
3070 /* sh compact pseudo register: */
3071 if (reg_nr
== tdep
->PC_C_REGNUM
3072 || reg_nr
== tdep
->GBR_C_REGNUM
3073 || reg_nr
== tdep
->MACL_C_REGNUM
3074 || reg_nr
== tdep
->PR_C_REGNUM
)
3075 return (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3076 ? base_regnum
* 8 + 4
3079 if (reg_nr
== tdep
->MACH_C_REGNUM
)
3080 return base_regnum
* 8;
3082 if (reg_nr
== tdep
->T_C_REGNUM
)
3083 return base_regnum
* 8; /* FIXME??? how do we get bit 0? Do we have to? */
3085 /* sh compact pseudo register: floating point register */
3086 else if (reg_nr
>=tdep
->FP0_C_REGNUM
3087 && reg_nr
<= tdep
->FV_LAST_C_REGNUM
)
3088 return (base_regnum
- FP0_REGNUM
) * 4
3089 + (tdep
->TR7_REGNUM
+ 1) * 8 + 4;
3091 else if (reg_nr
== tdep
->FPSCR_C_REGNUM
)
3092 /* This is complicated, for now return the beginning of the
3093 architectural FPSCR register. */
3094 return (tdep
->TR7_REGNUM
+ 1) * 8;
3096 else if (reg_nr
== tdep
->FPUL_C_REGNUM
)
3097 return ((base_regnum
- FP0_REGNUM
) * 4 +
3098 (tdep
->TR7_REGNUM
+ 1) * 8 + 4);
3100 /* It is not a pseudo register. */
3101 /* It is a 64 bit register. */
3102 else if (reg_nr
<= tdep
->TR7_REGNUM
)
3105 /* It is a 32 bit register. */
3107 if (reg_nr
== tdep
->FPSCR_REGNUM
)
3108 return (tdep
->FPSCR_REGNUM
* 8);
3110 /* It is floating point 32-bit register */
3112 return ((tdep
->TR7_REGNUM
+ 1) * 8
3113 + (reg_nr
- FP0_REGNUM
+ 1) * 4);
3116 /* Number of bytes of storage in the actual machine representation for
3119 sh_default_register_raw_size (int reg_nr
)
3125 sh_sh4_register_raw_size (int reg_nr
)
3127 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3129 if (reg_nr
>= tdep
->DR0_REGNUM
3130 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3132 else if (reg_nr
>= tdep
->FV0_REGNUM
3133 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3140 sh_sh64_register_raw_size (int reg_nr
)
3142 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3144 if ((reg_nr
>= tdep
->DR0_REGNUM
3145 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3146 || (reg_nr
>= tdep
->FPP0_REGNUM
3147 && reg_nr
<= tdep
->FPP_LAST_REGNUM
)
3148 || (reg_nr
>= tdep
->DR0_C_REGNUM
3149 && reg_nr
<= tdep
->DR_LAST_C_REGNUM
)
3150 || (reg_nr
<= tdep
->TR7_REGNUM
))
3153 else if ((reg_nr
>= tdep
->FV0_REGNUM
3154 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3155 || (reg_nr
>= tdep
->FV0_C_REGNUM
3156 && reg_nr
<= tdep
->FV_LAST_C_REGNUM
))
3159 else /* this covers also the 32-bit SH compact registers. */
3163 /* Number of bytes of storage in the program's representation
3166 sh_register_virtual_size (int reg_nr
)
3173 sh_sh64_register_virtual_size (int reg_nr
)
3175 if (reg_nr
>= FP0_REGNUM
3176 && reg_nr
<= gdbarch_tdep (current_gdbarch
)->FP_LAST_REGNUM
)
3182 /* Return the GDB type object for the "standard" data type
3183 of data in register N. */
3184 static struct type
*
3185 sh_sh3e_register_virtual_type (int reg_nr
)
3187 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3189 if ((reg_nr
>= FP0_REGNUM
3190 && (reg_nr
<= tdep
->FP_LAST_REGNUM
))
3191 || (reg_nr
== tdep
->FPUL_REGNUM
))
3192 return builtin_type_float
;
3194 return builtin_type_int
;
3197 static struct type
*
3198 sh_sh4_build_float_register_type (int high
)
3202 temp
= create_range_type (NULL
, builtin_type_int
, 0, high
);
3203 return create_array_type (NULL
, builtin_type_float
, temp
);
3206 static struct type
*
3207 sh_sh4_register_virtual_type (int reg_nr
)
3209 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3211 if ((reg_nr
>= FP0_REGNUM
3212 && (reg_nr
<= tdep
->FP_LAST_REGNUM
))
3213 || (reg_nr
== tdep
->FPUL_REGNUM
))
3214 return builtin_type_float
;
3215 else if (reg_nr
>= tdep
->DR0_REGNUM
3216 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3217 return builtin_type_double
;
3218 else if (reg_nr
>= tdep
->FV0_REGNUM
3219 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3220 return sh_sh4_build_float_register_type (3);
3222 return builtin_type_int
;
3225 static struct type
*
3226 sh_sh64_register_virtual_type (int reg_nr
)
3228 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3230 if ((reg_nr
>= FP0_REGNUM
3231 && reg_nr
<= tdep
->FP_LAST_REGNUM
)
3232 || (reg_nr
>= tdep
->FP0_C_REGNUM
3233 && reg_nr
<= tdep
->FP_LAST_C_REGNUM
))
3234 return builtin_type_float
;
3235 else if ((reg_nr
>= tdep
->DR0_REGNUM
3236 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3237 || (reg_nr
>= tdep
->DR0_C_REGNUM
3238 && reg_nr
<= tdep
->DR_LAST_C_REGNUM
))
3239 return builtin_type_double
;
3240 else if (reg_nr
>= tdep
->FPP0_REGNUM
3241 && reg_nr
<= tdep
->FPP_LAST_REGNUM
)
3242 return sh_sh4_build_float_register_type (1);
3243 else if ((reg_nr
>= tdep
->FV0_REGNUM
3244 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3245 ||(reg_nr
>= tdep
->FV0_C_REGNUM
3246 && reg_nr
<= tdep
->FV_LAST_C_REGNUM
))
3247 return sh_sh4_build_float_register_type (3);
3248 else if (reg_nr
== tdep
->FPSCR_REGNUM
)
3249 return builtin_type_int
;
3250 else if (reg_nr
>= tdep
->R0_C_REGNUM
3251 && reg_nr
< tdep
->FP0_C_REGNUM
)
3252 return builtin_type_int
;
3254 return builtin_type_long_long
;
3257 static struct type
*
3258 sh_default_register_virtual_type (int reg_nr
)
3260 return builtin_type_int
;
3263 /* On the sh4, the DRi pseudo registers are problematic if the target
3264 is little endian. When the user writes one of those registers, for
3265 instance with 'ser var $dr0=1', we want the double to be stored
3267 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
3268 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
3270 This corresponds to little endian byte order & big endian word
3271 order. However if we let gdb write the register w/o conversion, it
3272 will write fr0 and fr1 this way:
3273 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
3274 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
3275 because it will consider fr0 and fr1 as a single LE stretch of memory.
3277 To achieve what we want we must force gdb to store things in
3278 floatformat_ieee_double_littlebyte_bigword (which is defined in
3279 include/floatformat.h and libiberty/floatformat.c.
3281 In case the target is big endian, there is no problem, the
3282 raw bytes will look like:
3283 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
3284 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
3286 The other pseudo registers (the FVs) also don't pose a problem
3287 because they are stored as 4 individual FP elements. */
3290 sh_sh4_register_convert_to_virtual (int regnum
, struct type
*type
,
3291 char *from
, char *to
)
3293 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3295 if (regnum
>= tdep
->DR0_REGNUM
3296 && regnum
<= tdep
->DR_LAST_REGNUM
)
3299 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword
, from
, &val
);
3300 store_floating (to
, TYPE_LENGTH (type
), val
);
3303 error ("sh_register_convert_to_virtual called with non DR register number");
3307 sh_sh64_register_convert_to_virtual (int regnum
, struct type
*type
,
3308 char *from
, char *to
)
3310 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3312 if (TARGET_BYTE_ORDER
!= BFD_ENDIAN_LITTLE
)
3314 /* It is a no-op. */
3315 memcpy (to
, from
, REGISTER_RAW_SIZE (regnum
));
3319 if ((regnum
>= tdep
->DR0_REGNUM
3320 && regnum
<= tdep
->DR_LAST_REGNUM
)
3321 || (regnum
>= tdep
->DR0_C_REGNUM
3322 && regnum
<= tdep
->DR_LAST_C_REGNUM
))
3325 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword
, from
, &val
);
3326 store_floating(to
, TYPE_LENGTH(type
), val
);
3329 error("sh_register_convert_to_virtual called with non DR register number");
3333 sh_sh4_register_convert_to_raw (struct type
*type
, int regnum
,
3334 char *from
, char *to
)
3336 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3338 if (regnum
>= tdep
->DR0_REGNUM
3339 && regnum
<= tdep
->DR_LAST_REGNUM
)
3341 DOUBLEST val
= extract_floating (from
, TYPE_LENGTH(type
));
3342 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword
, &val
, to
);
3345 error("sh_register_convert_to_raw called with non DR register number");
3349 sh_sh64_register_convert_to_raw (struct type
*type
, int regnum
,
3350 char *from
, char *to
)
3352 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3354 if (TARGET_BYTE_ORDER
!= BFD_ENDIAN_LITTLE
)
3356 /* It is a no-op. */
3357 memcpy (to
, from
, REGISTER_RAW_SIZE (regnum
));
3361 if ((regnum
>= tdep
->DR0_REGNUM
3362 && regnum
<= tdep
->DR_LAST_REGNUM
)
3363 || (regnum
>= tdep
->DR0_C_REGNUM
3364 && regnum
<= tdep
->DR_LAST_C_REGNUM
))
3366 DOUBLEST val
= extract_floating (from
, TYPE_LENGTH(type
));
3367 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword
, &val
, to
);
3370 error("sh_register_convert_to_raw called with non DR register number");
3374 sh_pseudo_register_read (int reg_nr
, char *buffer
)
3376 int base_regnum
, portion
;
3377 char *temp_buffer
= (char*) alloca (MAX_REGISTER_RAW_SIZE
);
3378 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3380 if (reg_nr
>= tdep
->DR0_REGNUM
3381 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3383 base_regnum
= dr_reg_base_num (reg_nr
);
3385 /* Build the value in the provided buffer. */
3386 /* Read the real regs for which this one is an alias. */
3387 for (portion
= 0; portion
< 2; portion
++)
3388 regcache_read (current_regcache
, base_regnum
+ portion
,
3390 + REGISTER_RAW_SIZE (base_regnum
) * portion
));
3391 /* We must pay attention to the endiannes. */
3392 sh_sh4_register_convert_to_virtual (reg_nr
,
3393 REGISTER_VIRTUAL_TYPE (reg_nr
),
3394 temp_buffer
, buffer
);
3396 else if (reg_nr
>= tdep
->FV0_REGNUM
3397 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3399 base_regnum
= fv_reg_base_num (reg_nr
);
3401 /* Read the real regs for which this one is an alias. */
3402 for (portion
= 0; portion
< 4; portion
++)
3403 regcache_read (current_regcache
, base_regnum
+ portion
,
3404 buffer
+ REGISTER_RAW_SIZE (base_regnum
) * portion
);
3409 sh4_register_read (struct gdbarch
*gdbarch
, int reg_nr
, char *buffer
)
3411 if (reg_nr
>= 0 && reg_nr
< gdbarch_tdep (current_gdbarch
)->DR0_REGNUM
)
3412 /* It is a regular register. */
3413 regcache_read (current_regcache
, reg_nr
, buffer
);
3415 /* It is a pseudo register and we need to construct its value */
3416 sh_pseudo_register_read (reg_nr
, buffer
);
3420 sh64_pseudo_register_read (int reg_nr
, char *buffer
)
3425 char *temp_buffer
= (char*) alloca (MAX_REGISTER_RAW_SIZE
);
3426 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3428 if (reg_nr
>= tdep
->DR0_REGNUM
3429 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3431 base_regnum
= dr_reg_base_num (reg_nr
);
3433 /* Build the value in the provided buffer. */
3434 /* DR regs are double precision registers obtained by
3435 concatenating 2 single precision floating point registers. */
3436 for (portion
= 0; portion
< 2; portion
++)
3437 regcache_read (current_regcache
, base_regnum
+ portion
,
3439 + REGISTER_RAW_SIZE (base_regnum
) * portion
));
3441 /* We must pay attention to the endiannes. */
3442 sh_sh64_register_convert_to_virtual (reg_nr
, REGISTER_VIRTUAL_TYPE (reg_nr
),
3443 temp_buffer
, buffer
);
3447 else if (reg_nr
>= tdep
->FPP0_REGNUM
3448 && reg_nr
<= tdep
->FPP_LAST_REGNUM
)
3450 base_regnum
= fpp_reg_base_num (reg_nr
);
3452 /* Build the value in the provided buffer. */
3453 /* FPP regs are pairs of single precision registers obtained by
3454 concatenating 2 single precision floating point registers. */
3455 for (portion
= 0; portion
< 2; portion
++)
3456 regcache_read (current_regcache
, base_regnum
+ portion
,
3457 buffer
+ REGISTER_RAW_SIZE (base_regnum
) * portion
);
3460 else if (reg_nr
>= tdep
->FV0_REGNUM
3461 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3463 base_regnum
= fv_reg_base_num (reg_nr
);
3465 /* Build the value in the provided buffer. */
3466 /* FV regs are vectors of single precision registers obtained by
3467 concatenating 4 single precision floating point registers. */
3468 for (portion
= 0; portion
< 4; portion
++)
3469 regcache_read (current_regcache
, base_regnum
+ portion
,
3470 buffer
+ REGISTER_RAW_SIZE (base_regnum
) * portion
);
3473 /* sh compact pseudo registers. 1-to-1 with a shmedia register */
3474 else if (reg_nr
>= tdep
->R0_C_REGNUM
3475 && reg_nr
<= tdep
->T_C_REGNUM
)
3477 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3479 /* Build the value in the provided buffer. */
3480 regcache_read (current_regcache
, base_regnum
, temp_buffer
);
3481 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3483 memcpy (buffer
, temp_buffer
+ offset
, 4); /* get LOWER 32 bits only????*/
3486 else if (reg_nr
>= tdep
->FP0_C_REGNUM
3487 && reg_nr
<= tdep
->FP_LAST_C_REGNUM
)
3489 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3491 /* Build the value in the provided buffer. */
3492 /* Floating point registers map 1-1 to the media fp regs,
3493 they have the same size and endienness. */
3494 regcache_read (current_regcache
, base_regnum
, buffer
);
3497 else if (reg_nr
>= tdep
->DR0_C_REGNUM
3498 && reg_nr
<= tdep
->DR_LAST_C_REGNUM
)
3500 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3502 /* DR_C regs are double precision registers obtained by
3503 concatenating 2 single precision floating point registers. */
3504 for (portion
= 0; portion
< 2; portion
++)
3505 regcache_read (current_regcache
, base_regnum
+ portion
,
3507 + REGISTER_RAW_SIZE (base_regnum
) * portion
));
3509 /* We must pay attention to the endiannes. */
3510 sh_sh64_register_convert_to_virtual (reg_nr
, REGISTER_VIRTUAL_TYPE (reg_nr
),
3511 temp_buffer
, buffer
);
3514 else if (reg_nr
>= tdep
->FV0_C_REGNUM
3515 && reg_nr
<= tdep
->FV_LAST_C_REGNUM
)
3517 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3519 /* Build the value in the provided buffer. */
3520 /* FV_C regs are vectors of single precision registers obtained by
3521 concatenating 4 single precision floating point registers. */
3522 for (portion
= 0; portion
< 4; portion
++)
3523 regcache_read (current_regcache
, base_regnum
+ portion
,
3524 buffer
+ REGISTER_RAW_SIZE (base_regnum
) * portion
);
3527 else if (reg_nr
== tdep
->FPSCR_C_REGNUM
)
3529 int fpscr_base_regnum
;
3531 unsigned int fpscr_value
;
3532 unsigned int sr_value
;
3533 unsigned int fpscr_c_value
;
3534 unsigned int fpscr_c_part1_value
;
3535 unsigned int fpscr_c_part2_value
;
3537 fpscr_base_regnum
= tdep
->FPSCR_REGNUM
;
3538 sr_base_regnum
= tdep
->SR_REGNUM
;
3540 /* Build the value in the provided buffer. */
3541 /* FPSCR_C is a very weird register that contains sparse bits
3542 from the FPSCR and the SR architectural registers.
3549 2-17 Bit 2-18 of FPSCR
3550 18-20 Bits 12,13,14 of SR
3554 /* Get FPSCR into a local buffer */
3555 regcache_read (current_regcache
, fpscr_base_regnum
, temp_buffer
);
3556 /* Get value as an int. */
3557 fpscr_value
= extract_unsigned_integer (temp_buffer
, 4);
3558 /* Get SR into a local buffer */
3559 regcache_read (current_regcache
, sr_base_regnum
, temp_buffer
);
3560 /* Get value as an int. */
3561 sr_value
= extract_unsigned_integer (temp_buffer
, 4);
3562 /* Build the new value. */
3563 fpscr_c_part1_value
= fpscr_value
& 0x3fffd;
3564 fpscr_c_part2_value
= (sr_value
& 0x7000) << 6;
3565 fpscr_c_value
= fpscr_c_part1_value
| fpscr_c_part2_value
;
3566 /* Store that in out buffer!!! */
3567 store_unsigned_integer (buffer
, 4, fpscr_c_value
);
3568 /* FIXME There is surely an endianness gotcha here. */
3571 else if (reg_nr
== tdep
->FPUL_C_REGNUM
)
3573 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3575 /* FPUL_C register is floating point register 32,
3576 same size, same endianness. */
3577 regcache_read (current_regcache
, base_regnum
, buffer
);
3582 sh64_register_read (struct gdbarch
*gdbarch
, int reg_nr
, char *buffer
)
3585 if (reg_nr
>= 0 && reg_nr
< gdbarch_tdep (current_gdbarch
)->DR0_REGNUM
)
3586 /* It is a regular register. */
3587 regcache_read (current_regcache
, reg_nr
, buffer
);
3589 /* It is a pseudo register and we need to construct its value */
3590 sh64_pseudo_register_read (reg_nr
, buffer
);
3594 sh_pseudo_register_write (int reg_nr
, char *buffer
)
3596 int base_regnum
, portion
;
3597 char *temp_buffer
= (char*) alloca (MAX_REGISTER_RAW_SIZE
);
3598 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3600 if (reg_nr
>= tdep
->DR0_REGNUM
3601 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3603 base_regnum
= dr_reg_base_num (reg_nr
);
3605 /* We must pay attention to the endiannes. */
3606 sh_sh4_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr
), reg_nr
,
3607 buffer
, temp_buffer
);
3609 /* Write the real regs for which this one is an alias. */
3610 for (portion
= 0; portion
< 2; portion
++)
3611 regcache_write (current_regcache
, base_regnum
+ portion
,
3613 + REGISTER_RAW_SIZE (base_regnum
) * portion
));
3615 else if (reg_nr
>= tdep
->FV0_REGNUM
3616 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3618 base_regnum
= fv_reg_base_num (reg_nr
);
3620 /* Write the real regs for which this one is an alias. */
3621 for (portion
= 0; portion
< 4; portion
++)
3622 regcache_write (current_regcache
, base_regnum
+ portion
,
3623 buffer
+ REGISTER_RAW_SIZE (base_regnum
) * portion
);
3628 sh4_register_write (struct gdbarch
*gdbarch
, int reg_nr
, char *buffer
)
3630 if (reg_nr
>= 0 && reg_nr
< gdbarch_tdep (current_gdbarch
)->DR0_REGNUM
)
3631 /* It is a regular register. */
3632 regcache_write (current_regcache
, reg_nr
, buffer
);
3634 /* It is a pseudo register and we need to construct its value */
3635 sh_pseudo_register_write (reg_nr
, buffer
);
3639 sh64_pseudo_register_write (int reg_nr
, char *buffer
)
3641 int base_regnum
, portion
;
3643 char *temp_buffer
= (char*) alloca (MAX_REGISTER_RAW_SIZE
);
3644 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3646 if (reg_nr
>= tdep
->DR0_REGNUM
3647 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3649 base_regnum
= dr_reg_base_num (reg_nr
);
3650 /* We must pay attention to the endiannes. */
3651 sh_sh64_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr
), reg_nr
,
3652 buffer
, temp_buffer
);
3655 /* Write the real regs for which this one is an alias. */
3656 for (portion
= 0; portion
< 2; portion
++)
3657 regcache_write (current_regcache
, base_regnum
+ portion
,
3659 + REGISTER_RAW_SIZE (base_regnum
) * portion
));
3662 else if (reg_nr
>= tdep
->FPP0_REGNUM
3663 && reg_nr
<= tdep
->FPP_LAST_REGNUM
)
3665 base_regnum
= fpp_reg_base_num (reg_nr
);
3667 /* Write the real regs for which this one is an alias. */
3668 for (portion
= 0; portion
< 2; portion
++)
3669 regcache_write (current_regcache
, base_regnum
+ portion
,
3670 buffer
+ REGISTER_RAW_SIZE (base_regnum
) * portion
);
3673 else if (reg_nr
>= tdep
->FV0_REGNUM
3674 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3676 base_regnum
= fv_reg_base_num (reg_nr
);
3678 /* Write the real regs for which this one is an alias. */
3679 for (portion
= 0; portion
< 4; portion
++)
3680 regcache_write (current_regcache
, base_regnum
+ portion
,
3681 buffer
+ REGISTER_RAW_SIZE (base_regnum
) * portion
);
3684 /* sh compact general pseudo registers. 1-to-1 with a shmedia
3685 register but only 4 bytes of it. */
3686 else if (reg_nr
>= tdep
->R0_C_REGNUM
3687 && reg_nr
<= tdep
->T_C_REGNUM
)
3689 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3690 /* reg_nr is 32 bit here, and base_regnum is 64 bits. */
3691 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3695 /* Let's read the value of the base register into a temporary
3696 buffer, so that overwriting the last four bytes with the new
3697 value of the pseudo will leave the upper 4 bytes unchanged. */
3698 regcache_read (current_regcache
, base_regnum
, temp_buffer
);
3699 /* Write as an 8 byte quantity */
3700 memcpy (temp_buffer
+ offset
, buffer
, 4);
3701 regcache_write (current_regcache
, base_regnum
, temp_buffer
);
3704 /* sh floating point compact pseudo registers. 1-to-1 with a shmedia
3705 registers. Both are 4 bytes. */
3706 else if (reg_nr
>= tdep
->FP0_C_REGNUM
3707 && reg_nr
<= tdep
->FP_LAST_C_REGNUM
)
3709 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3710 regcache_write (current_regcache
, base_regnum
, buffer
);
3713 else if (reg_nr
>= tdep
->DR0_C_REGNUM
3714 && reg_nr
<= tdep
->DR_LAST_C_REGNUM
)
3716 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3717 for (portion
= 0; portion
< 2; portion
++)
3719 /* We must pay attention to the endiannes. */
3720 sh_sh64_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr
), reg_nr
,
3721 buffer
, temp_buffer
);
3723 regcache_write (current_regcache
, base_regnum
+ portion
,
3725 + REGISTER_RAW_SIZE (base_regnum
) * portion
));
3729 else if (reg_nr
>= tdep
->FV0_C_REGNUM
3730 && reg_nr
<= tdep
->FV_LAST_C_REGNUM
)
3732 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3734 for (portion
= 0; portion
< 4; portion
++)
3736 regcache_write (current_regcache
, base_regnum
+ portion
,
3737 buffer
+ REGISTER_RAW_SIZE (base_regnum
) * portion
);
3741 else if (reg_nr
== tdep
->FPSCR_C_REGNUM
)
3743 int fpscr_base_regnum
;
3745 unsigned int fpscr_value
;
3746 unsigned int sr_value
;
3747 unsigned int old_fpscr_value
;
3748 unsigned int old_sr_value
;
3749 unsigned int fpscr_c_value
;
3750 unsigned int fpscr_mask
;
3751 unsigned int sr_mask
;
3753 fpscr_base_regnum
= tdep
->FPSCR_REGNUM
;
3754 sr_base_regnum
= tdep
->SR_REGNUM
;
3756 /* FPSCR_C is a very weird register that contains sparse bits
3757 from the FPSCR and the SR architectural registers.
3764 2-17 Bit 2-18 of FPSCR
3765 18-20 Bits 12,13,14 of SR
3769 /* Get value as an int. */
3770 fpscr_c_value
= extract_unsigned_integer (buffer
, 4);
3772 /* Build the new values. */
3773 fpscr_mask
= 0x0003fffd;
3774 sr_mask
= 0x001c0000;
3776 fpscr_value
= fpscr_c_value
& fpscr_mask
;
3777 sr_value
= (fpscr_value
& sr_mask
) >> 6;
3779 regcache_read (current_regcache
, fpscr_base_regnum
, temp_buffer
);
3780 old_fpscr_value
= extract_unsigned_integer (temp_buffer
, 4);
3781 old_fpscr_value
&= 0xfffc0002;
3782 fpscr_value
|= old_fpscr_value
;
3783 store_unsigned_integer (temp_buffer
, 4, fpscr_value
);
3784 regcache_write (current_regcache
, fpscr_base_regnum
, temp_buffer
);
3786 regcache_read (current_regcache
, sr_base_regnum
, temp_buffer
);
3787 old_sr_value
= extract_unsigned_integer (temp_buffer
, 4);
3788 old_sr_value
&= 0xffff8fff;
3789 sr_value
|= old_sr_value
;
3790 store_unsigned_integer (temp_buffer
, 4, sr_value
);
3791 regcache_write (current_regcache
, sr_base_regnum
, temp_buffer
);
3794 else if (reg_nr
== tdep
->FPUL_C_REGNUM
)
3796 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3797 regcache_write (current_regcache
, base_regnum
, buffer
);
3802 sh64_register_write (struct gdbarch
*gdbarch
, int reg_nr
, char *buffer
)
3804 if (reg_nr
>= 0 && reg_nr
< gdbarch_tdep (current_gdbarch
)->DR0_REGNUM
)
3805 /* It is a regular register. */
3806 regcache_write (current_regcache
, reg_nr
, buffer
);
3808 /* It is a pseudo register and we need to construct its value */
3809 sh64_pseudo_register_write (reg_nr
, buffer
);
3812 /* Floating point vector of 4 float registers. */
3814 do_fv_register_info (int fv_regnum
)
3816 int first_fp_reg_num
= fv_reg_base_num (fv_regnum
);
3817 printf_filtered ("fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
3818 fv_regnum
- gdbarch_tdep (current_gdbarch
)->FV0_REGNUM
,
3819 (int) read_register (first_fp_reg_num
),
3820 (int) read_register (first_fp_reg_num
+ 1),
3821 (int) read_register (first_fp_reg_num
+ 2),
3822 (int) read_register (first_fp_reg_num
+ 3));
3825 /* Floating point vector of 4 float registers, compact mode. */
3827 do_fv_c_register_info (int fv_regnum
)
3829 int first_fp_reg_num
= sh64_compact_reg_base_num (fv_regnum
);
3830 printf_filtered ("fv%d_c\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
3831 fv_regnum
- gdbarch_tdep (current_gdbarch
)->FV0_C_REGNUM
,
3832 (int) read_register (first_fp_reg_num
),
3833 (int) read_register (first_fp_reg_num
+ 1),
3834 (int) read_register (first_fp_reg_num
+ 2),
3835 (int) read_register (first_fp_reg_num
+ 3));
3838 /* Pairs of single regs. The DR are instead double precision
3841 do_fpp_register_info (int fpp_regnum
)
3843 int first_fp_reg_num
= fpp_reg_base_num (fpp_regnum
);
3845 printf_filtered ("fpp%d\t0x%08x\t0x%08x\n",
3846 fpp_regnum
- gdbarch_tdep (current_gdbarch
)->FPP0_REGNUM
,
3847 (int) read_register (first_fp_reg_num
),
3848 (int) read_register (first_fp_reg_num
+ 1));
3851 /* Double precision registers. */
3853 do_dr_register_info (int dr_regnum
)
3855 int first_fp_reg_num
= dr_reg_base_num (dr_regnum
);
3857 printf_filtered ("dr%d\t0x%08x%08x\n",
3858 dr_regnum
- gdbarch_tdep (current_gdbarch
)->DR0_REGNUM
,
3859 (int) read_register (first_fp_reg_num
),
3860 (int) read_register (first_fp_reg_num
+ 1));
3863 /* Double precision registers, compact mode. */
3865 do_dr_c_register_info (int dr_regnum
)
3867 int first_fp_reg_num
= sh64_compact_reg_base_num (dr_regnum
);
3869 printf_filtered ("dr%d_c\t0x%08x%08x\n",
3870 dr_regnum
- gdbarch_tdep (current_gdbarch
)->DR0_C_REGNUM
,
3871 (int) read_register (first_fp_reg_num
),
3872 (int) read_register (first_fp_reg_num
+1));
3875 /* General register in compact mode. */
3877 do_r_c_register_info (int r_c_regnum
)
3879 int regnum
= sh64_compact_reg_base_num (r_c_regnum
);
3881 printf_filtered ("r%d_c\t0x%08x\n",
3882 r_c_regnum
- gdbarch_tdep (current_gdbarch
)->R0_C_REGNUM
,
3883 /*FIXME!!!*/ (int) read_register (regnum
));
3886 /* FIXME:!! THIS SHOULD TAKE CARE OF GETTING THE RIGHT PORTION OF THE
3887 shmedia REGISTERS. */
3888 /* Control registers, compact mode. */
3890 do_cr_c_register_info (int cr_c_regnum
)
3892 switch (cr_c_regnum
)
3894 case 237: printf_filtered ("pc_c\t0x%08x\n", (int) read_register (cr_c_regnum
));
3896 case 238: printf_filtered ("gbr_c\t0x%08x\n", (int) read_register (cr_c_regnum
));
3898 case 239: printf_filtered ("mach_c\t0x%08x\n", (int) read_register (cr_c_regnum
));
3900 case 240: printf_filtered ("macl_c\t0x%08x\n", (int) read_register (cr_c_regnum
));
3902 case 241: printf_filtered ("pr_c\t0x%08x\n", (int) read_register (cr_c_regnum
));
3904 case 242: printf_filtered ("t_c\t0x%08x\n", (int) read_register (cr_c_regnum
));
3906 case 243: printf_filtered ("fpscr_c\t0x%08x\n", (int) read_register (cr_c_regnum
));
3908 case 244: printf_filtered ("fpul_c\t0x%08x\n", (int)read_register (cr_c_regnum
));
3914 sh_do_pseudo_register (int regnum
)
3916 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3918 if (regnum
< NUM_REGS
|| regnum
>= NUM_REGS
+ NUM_PSEUDO_REGS
)
3919 internal_error (__FILE__
, __LINE__
,
3920 "Invalid pseudo register number %d\n", regnum
);
3921 else if (regnum
>= tdep
->DR0_REGNUM
3922 && regnum
< tdep
->DR_LAST_REGNUM
)
3923 do_dr_register_info (regnum
);
3924 else if (regnum
>= tdep
->FV0_REGNUM
3925 && regnum
<= tdep
->FV_LAST_REGNUM
)
3926 do_fv_register_info (regnum
);
3930 sh_do_fp_register (int regnum
)
3931 { /* do values for FP (float) regs */
3933 double flt
; /* double extracted from raw hex data */
3937 /* Allocate space for the float. */
3938 raw_buffer
= (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
3940 /* Get the data in raw format. */
3941 if (!frame_register_read (selected_frame
, regnum
, raw_buffer
))
3942 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
3944 /* Get the register as a number */
3945 flt
= unpack_double (builtin_type_float
, raw_buffer
, &inv
);
3947 /* Print the name and some spaces. */
3948 fputs_filtered (REGISTER_NAME (regnum
), gdb_stdout
);
3949 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum
)), gdb_stdout
);
3951 /* Print the value. */
3953 printf_filtered ("<invalid float>");
3955 printf_filtered ("%-10.9g", flt
);
3957 /* Print the fp register as hex. */
3958 printf_filtered ("\t(raw 0x");
3959 for (j
= 0; j
< REGISTER_RAW_SIZE (regnum
); j
++)
3961 register int idx
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? j
3962 : REGISTER_RAW_SIZE (regnum
) - 1 - j
;
3963 printf_filtered ("%02x", (unsigned char) raw_buffer
[idx
]);
3965 printf_filtered (")");
3966 printf_filtered ("\n");
3970 sh64_do_pseudo_register (int regnum
)
3972 /* All the sh64-compact mode registers are pseudo registers. */
3973 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3975 if (regnum
< NUM_REGS
3976 || regnum
>= NUM_REGS
+ NUM_PSEUDO_REGS_SH_MEDIA
+ NUM_PSEUDO_REGS_SH_COMPACT
)
3977 internal_error (__FILE__
, __LINE__
,
3978 "Invalid pseudo register number %d\n", regnum
);
3980 else if ((regnum
>= tdep
->DR0_REGNUM
3981 && regnum
<= tdep
->DR_LAST_REGNUM
))
3982 do_dr_register_info (regnum
);
3984 else if ((regnum
>= tdep
->DR0_C_REGNUM
3985 && regnum
<= tdep
->DR_LAST_C_REGNUM
))
3986 do_dr_c_register_info (regnum
);
3988 else if ((regnum
>= tdep
->FV0_REGNUM
3989 && regnum
<= tdep
->FV_LAST_REGNUM
))
3990 do_fv_register_info (regnum
);
3992 else if ((regnum
>= tdep
->FV0_C_REGNUM
3993 && regnum
<= tdep
->FV_LAST_C_REGNUM
))
3994 do_fv_c_register_info (regnum
);
3996 else if (regnum
>= tdep
->FPP0_REGNUM
3997 && regnum
<= tdep
->FPP_LAST_REGNUM
)
3998 do_fpp_register_info (regnum
);
4000 else if (regnum
>= tdep
->R0_C_REGNUM
4001 && regnum
<= tdep
->R_LAST_C_REGNUM
)
4002 do_r_c_register_info (regnum
); /* FIXME, this function will not print the right format */
4004 else if (regnum
>= tdep
->FP0_C_REGNUM
4005 && regnum
<= tdep
->FP_LAST_C_REGNUM
)
4006 sh_do_fp_register (regnum
); /* this should work also for pseudoregs */
4008 else if (regnum
>= tdep
->PC_C_REGNUM
4009 && regnum
<= tdep
->FPUL_C_REGNUM
)
4010 do_cr_c_register_info (regnum
);
4015 sh_do_register (int regnum
)
4017 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
4019 fputs_filtered (REGISTER_NAME (regnum
), gdb_stdout
);
4020 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum
)), gdb_stdout
);
4022 /* Get the data in raw format. */
4023 if (!frame_register_read (selected_frame
, regnum
, raw_buffer
))
4024 printf_filtered ("*value not available*\n");
4026 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0, 0,
4027 gdb_stdout
, 'x', 1, 0, Val_pretty_default
);
4028 printf_filtered ("\t");
4029 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0, 0,
4030 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
4031 printf_filtered ("\n");
4035 sh_print_register (int regnum
)
4037 if (regnum
< 0 || regnum
>= NUM_REGS
+ NUM_PSEUDO_REGS
)
4038 internal_error (__FILE__
, __LINE__
,
4039 "Invalid register number %d\n", regnum
);
4041 else if (regnum
>= 0 && regnum
< NUM_REGS
)
4043 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
4044 sh_do_fp_register (regnum
); /* FP regs */
4046 sh_do_register (regnum
); /* All other regs */
4049 else if (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
4050 do_pseudo_register (regnum
);
4054 sh_do_registers_info (int regnum
, int fpregs
)
4056 if (regnum
!= -1) /* do one specified register */
4058 if (*(REGISTER_NAME (regnum
)) == '\0')
4059 error ("Not a valid register for the current processor type");
4061 sh_print_register (regnum
);
4064 /* do all (or most) registers */
4067 while (regnum
< NUM_REGS
)
4069 /* If the register name is empty, it is undefined for this
4070 processor, so don't display anything. */
4071 if (REGISTER_NAME (regnum
) == NULL
4072 || *(REGISTER_NAME (regnum
)) == '\0')
4078 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
4082 /* true for "INFO ALL-REGISTERS" command */
4083 sh_do_fp_register (regnum
); /* FP regs */
4087 regnum
+= (gdbarch_tdep (current_gdbarch
)->FP_LAST_REGNUM
- FP0_REGNUM
); /* skip FP regs */
4091 sh_do_register (regnum
); /* All other regs */
4097 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
4099 do_pseudo_register (regnum
);
4106 sh_compact_do_registers_info (int regnum
, int fpregs
)
4108 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4109 if (regnum
!= -1) /* do one specified register */
4111 if (*(REGISTER_NAME (regnum
)) == '\0')
4112 error ("Not a valid register for the current processor type");
4114 if (regnum
>= 0 && regnum
< tdep
->R0_C_REGNUM
)
4115 error ("Not a valid register for the current processor mode.");
4117 sh_print_register (regnum
);
4120 /* do all compact registers */
4122 regnum
= tdep
->R0_C_REGNUM
;
4123 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
4125 do_pseudo_register (regnum
);
4132 sh64_do_registers_info (int regnum
, int fpregs
)
4134 if (pc_is_isa32 (selected_frame
->pc
))
4135 sh_do_registers_info (regnum
, fpregs
);
4137 sh_compact_do_registers_info (regnum
, fpregs
);
4140 #ifdef SVR4_SHARED_LIBS
4142 /* Fetch (and possibly build) an appropriate link_map_offsets structure
4143 for native i386 linux targets using the struct offsets defined in
4144 link.h (but without actual reference to that file).
4146 This makes it possible to access i386-linux shared libraries from
4147 a gdb that was not built on an i386-linux host (for cross debugging).
4150 struct link_map_offsets
*
4151 sh_linux_svr4_fetch_link_map_offsets (void)
4153 static struct link_map_offsets lmo
;
4154 static struct link_map_offsets
*lmp
= 0;
4160 lmo
.r_debug_size
= 8; /* 20 not actual size but all we need */
4162 lmo
.r_map_offset
= 4;
4165 lmo
.link_map_size
= 20; /* 552 not actual size but all we need */
4167 lmo
.l_addr_offset
= 0;
4168 lmo
.l_addr_size
= 4;
4170 lmo
.l_name_offset
= 4;
4171 lmo
.l_name_size
= 4;
4173 lmo
.l_next_offset
= 12;
4174 lmo
.l_next_size
= 4;
4176 lmo
.l_prev_offset
= 16;
4177 lmo
.l_prev_size
= 4;
4182 #endif /* SVR4_SHARED_LIBS */
4185 static gdbarch_init_ftype sh_gdbarch_init
;
4187 static struct gdbarch
*
4188 sh_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
4190 static LONGEST sh_call_dummy_words
[] = {0};
4191 struct gdbarch
*gdbarch
;
4192 struct gdbarch_tdep
*tdep
;
4193 gdbarch_register_name_ftype
*sh_register_name
;
4194 gdbarch_store_return_value_ftype
*sh_store_return_value
;
4195 gdbarch_register_virtual_type_ftype
*sh_register_virtual_type
;
4196 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
4198 /* Try to determine the ABI of the object we are loading. */
4200 if (info
.abfd
!= NULL
)
4202 osabi
= gdbarch_lookup_osabi (info
.abfd
);
4203 /* If we get "unknown" back, just leave it that way. */
4206 /* Find a candidate among the list of pre-declared architectures. */
4207 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
4209 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
4211 /* Make sure the ABI selection matches. */
4212 tdep
= gdbarch_tdep (arches
->gdbarch
);
4213 if (tdep
&& tdep
->osabi
== osabi
)
4214 return arches
->gdbarch
;
4217 /* None found, create a new architecture from the information
4219 tdep
= XMALLOC (struct gdbarch_tdep
);
4220 gdbarch
= gdbarch_alloc (&info
, tdep
);
4222 tdep
->osabi
= osabi
;
4224 /* Initialize the register numbers that are not common to all the
4225 variants to -1, if necessary thse will be overwritten in the case
4227 tdep
->FPUL_REGNUM
= -1;
4228 tdep
->FPSCR_REGNUM
= -1;
4229 tdep
->PR_REGNUM
= 17;
4230 tdep
->SR_REGNUM
= 22;
4231 tdep
->DSR_REGNUM
= -1;
4232 tdep
->FP_LAST_REGNUM
= -1;
4233 tdep
->A0G_REGNUM
= -1;
4234 tdep
->A0_REGNUM
= -1;
4235 tdep
->A1G_REGNUM
= -1;
4236 tdep
->A1_REGNUM
= -1;
4237 tdep
->M0_REGNUM
= -1;
4238 tdep
->M1_REGNUM
= -1;
4239 tdep
->X0_REGNUM
= -1;
4240 tdep
->X1_REGNUM
= -1;
4241 tdep
->Y0_REGNUM
= -1;
4242 tdep
->Y1_REGNUM
= -1;
4243 tdep
->MOD_REGNUM
= -1;
4244 tdep
->RS_REGNUM
= -1;
4245 tdep
->RE_REGNUM
= -1;
4246 tdep
->SSR_REGNUM
= -1;
4247 tdep
->SPC_REGNUM
= -1;
4248 tdep
->DR0_REGNUM
= -1;
4249 tdep
->DR_LAST_REGNUM
= -1;
4250 tdep
->FV0_REGNUM
= -1;
4251 tdep
->FV_LAST_REGNUM
= -1;
4252 tdep
->ARG0_REGNUM
= 4;
4253 tdep
->ARGLAST_REGNUM
= 7;
4254 tdep
->RETURN_REGNUM
= 0;
4255 tdep
->FLOAT_ARGLAST_REGNUM
= -1;
4257 tdep
->sh_abi
= SH_ABI_UNKNOWN
;
4259 set_gdbarch_fp0_regnum (gdbarch
, -1);
4260 set_gdbarch_num_pseudo_regs (gdbarch
, 0);
4261 set_gdbarch_max_register_raw_size (gdbarch
, 4);
4262 set_gdbarch_max_register_virtual_size (gdbarch
, 4);
4263 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
4264 set_gdbarch_ptr_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
4265 set_gdbarch_num_regs (gdbarch
, SH_DEFAULT_NUM_REGS
);
4266 set_gdbarch_sp_regnum (gdbarch
, 15);
4267 set_gdbarch_fp_regnum (gdbarch
, 14);
4268 set_gdbarch_pc_regnum (gdbarch
, 16);
4269 set_gdbarch_register_size (gdbarch
, 4);
4270 set_gdbarch_register_bytes (gdbarch
, SH_DEFAULT_NUM_REGS
* 4);
4271 set_gdbarch_do_registers_info (gdbarch
, sh_do_registers_info
);
4272 set_gdbarch_breakpoint_from_pc (gdbarch
, sh_breakpoint_from_pc
);
4273 set_gdbarch_frame_chain (gdbarch
, sh_frame_chain
);
4274 set_gdbarch_get_saved_register (gdbarch
, generic_get_saved_register
);
4275 set_gdbarch_init_extra_frame_info (gdbarch
, sh_init_extra_frame_info
);
4276 set_gdbarch_deprecated_extract_return_value (gdbarch
, sh_extract_return_value
);
4277 set_gdbarch_push_arguments (gdbarch
, sh_push_arguments
);
4278 set_gdbarch_store_struct_return (gdbarch
, sh_store_struct_return
);
4279 set_gdbarch_use_struct_convention (gdbarch
, sh_use_struct_convention
);
4280 set_gdbarch_deprecated_extract_struct_value_address (gdbarch
, sh_extract_struct_value_address
);
4281 set_gdbarch_pop_frame (gdbarch
, sh_pop_frame
);
4282 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_sh
);
4283 skip_prologue_hard_way
= sh_skip_prologue_hard_way
;
4284 do_pseudo_register
= sh_do_pseudo_register
;
4286 switch (info
.bfd_arch_info
->mach
)
4289 sh_register_name
= sh_sh_register_name
;
4290 sh_show_regs
= sh_generic_show_regs
;
4291 sh_store_return_value
= sh_default_store_return_value
;
4292 sh_register_virtual_type
= sh_default_register_virtual_type
;
4293 set_gdbarch_frame_init_saved_regs (gdbarch
, sh_nofp_frame_init_saved_regs
);
4294 set_gdbarch_register_raw_size (gdbarch
, sh_default_register_raw_size
);
4295 set_gdbarch_register_virtual_size (gdbarch
, sh_default_register_raw_size
);
4296 set_gdbarch_register_byte (gdbarch
, sh_default_register_byte
);
4299 sh_register_name
= sh_sh_register_name
;
4300 sh_show_regs
= sh_generic_show_regs
;
4301 sh_store_return_value
= sh_default_store_return_value
;
4302 sh_register_virtual_type
= sh_default_register_virtual_type
;
4303 set_gdbarch_frame_init_saved_regs (gdbarch
, sh_nofp_frame_init_saved_regs
);
4304 set_gdbarch_register_raw_size (gdbarch
, sh_default_register_raw_size
);
4305 set_gdbarch_register_virtual_size (gdbarch
, sh_default_register_raw_size
);
4306 set_gdbarch_register_byte (gdbarch
, sh_default_register_byte
);
4308 case bfd_mach_sh_dsp
:
4309 sh_register_name
= sh_sh_dsp_register_name
;
4310 sh_show_regs
= sh_dsp_show_regs
;
4311 sh_store_return_value
= sh_default_store_return_value
;
4312 sh_register_virtual_type
= sh_default_register_virtual_type
;
4313 set_gdbarch_frame_init_saved_regs (gdbarch
, sh_nofp_frame_init_saved_regs
);
4314 set_gdbarch_register_raw_size (gdbarch
, sh_default_register_raw_size
);
4315 set_gdbarch_register_virtual_size (gdbarch
, sh_default_register_raw_size
);
4316 set_gdbarch_register_byte (gdbarch
, sh_default_register_byte
);
4317 tdep
->DSR_REGNUM
= 24;
4318 tdep
->A0G_REGNUM
= 25;
4319 tdep
->A0_REGNUM
= 26;
4320 tdep
->A1G_REGNUM
= 27;
4321 tdep
->A1_REGNUM
= 28;
4322 tdep
->M0_REGNUM
= 29;
4323 tdep
->M1_REGNUM
= 30;
4324 tdep
->X0_REGNUM
= 31;
4325 tdep
->X1_REGNUM
= 32;
4326 tdep
->Y0_REGNUM
= 33;
4327 tdep
->Y1_REGNUM
= 34;
4328 tdep
->MOD_REGNUM
= 40;
4329 tdep
->RS_REGNUM
= 43;
4330 tdep
->RE_REGNUM
= 44;
4333 sh_register_name
= sh_sh3_register_name
;
4334 sh_show_regs
= sh3_show_regs
;
4335 sh_store_return_value
= sh_default_store_return_value
;
4336 sh_register_virtual_type
= sh_default_register_virtual_type
;
4337 set_gdbarch_frame_init_saved_regs (gdbarch
, sh_nofp_frame_init_saved_regs
);
4338 set_gdbarch_register_raw_size (gdbarch
, sh_default_register_raw_size
);
4339 set_gdbarch_register_virtual_size (gdbarch
, sh_default_register_raw_size
);
4340 set_gdbarch_register_byte (gdbarch
, sh_default_register_byte
);
4341 tdep
->SSR_REGNUM
= 41;
4342 tdep
->SPC_REGNUM
= 42;
4345 sh_register_name
= sh_sh3e_register_name
;
4346 sh_show_regs
= sh3e_show_regs
;
4347 sh_store_return_value
= sh3e_sh4_store_return_value
;
4348 sh_register_virtual_type
= sh_sh3e_register_virtual_type
;
4349 set_gdbarch_frame_init_saved_regs (gdbarch
, sh_fp_frame_init_saved_regs
);
4350 set_gdbarch_register_raw_size (gdbarch
, sh_default_register_raw_size
);
4351 set_gdbarch_register_virtual_size (gdbarch
, sh_default_register_raw_size
);
4352 set_gdbarch_register_byte (gdbarch
, sh_default_register_byte
);
4353 set_gdbarch_deprecated_extract_return_value (gdbarch
, sh3e_sh4_extract_return_value
);
4354 set_gdbarch_fp0_regnum (gdbarch
, 25);
4355 tdep
->FPUL_REGNUM
= 23;
4356 tdep
->FPSCR_REGNUM
= 24;
4357 tdep
->FP_LAST_REGNUM
= 40;
4358 tdep
->SSR_REGNUM
= 41;
4359 tdep
->SPC_REGNUM
= 42;
4361 case bfd_mach_sh3_dsp
:
4362 sh_register_name
= sh_sh3_dsp_register_name
;
4363 sh_show_regs
= sh3_dsp_show_regs
;
4364 sh_store_return_value
= sh_default_store_return_value
;
4365 sh_register_virtual_type
= sh_default_register_virtual_type
;
4366 set_gdbarch_frame_init_saved_regs (gdbarch
, sh_nofp_frame_init_saved_regs
);
4367 set_gdbarch_register_raw_size (gdbarch
, sh_default_register_raw_size
);
4368 set_gdbarch_register_virtual_size (gdbarch
, sh_default_register_raw_size
);
4369 set_gdbarch_register_byte (gdbarch
, sh_default_register_byte
);
4370 tdep
->DSR_REGNUM
= 24;
4371 tdep
->A0G_REGNUM
= 25;
4372 tdep
->A0_REGNUM
= 26;
4373 tdep
->A1G_REGNUM
= 27;
4374 tdep
->A1_REGNUM
= 28;
4375 tdep
->M0_REGNUM
= 29;
4376 tdep
->M1_REGNUM
= 30;
4377 tdep
->X0_REGNUM
= 31;
4378 tdep
->X1_REGNUM
= 32;
4379 tdep
->Y0_REGNUM
= 33;
4380 tdep
->Y1_REGNUM
= 34;
4381 tdep
->MOD_REGNUM
= 40;
4382 tdep
->RS_REGNUM
= 43;
4383 tdep
->RE_REGNUM
= 44;
4384 tdep
->SSR_REGNUM
= 41;
4385 tdep
->SPC_REGNUM
= 42;
4388 sh_register_name
= sh_sh4_register_name
;
4389 sh_show_regs
= sh4_show_regs
;
4390 sh_store_return_value
= sh3e_sh4_store_return_value
;
4391 sh_register_virtual_type
= sh_sh4_register_virtual_type
;
4392 set_gdbarch_frame_init_saved_regs (gdbarch
, sh_fp_frame_init_saved_regs
);
4393 set_gdbarch_deprecated_extract_return_value (gdbarch
, sh3e_sh4_extract_return_value
);
4394 set_gdbarch_fp0_regnum (gdbarch
, 25);
4395 set_gdbarch_register_raw_size (gdbarch
, sh_sh4_register_raw_size
);
4396 set_gdbarch_register_virtual_size (gdbarch
, sh_sh4_register_raw_size
);
4397 set_gdbarch_register_byte (gdbarch
, sh_sh4_register_byte
);
4398 set_gdbarch_num_pseudo_regs (gdbarch
, 12);
4399 set_gdbarch_max_register_raw_size (gdbarch
, 4 * 4);
4400 set_gdbarch_max_register_virtual_size (gdbarch
, 4 * 4);
4401 set_gdbarch_register_read (gdbarch
, sh4_register_read
);
4402 set_gdbarch_register_write (gdbarch
, sh4_register_write
);
4403 tdep
->FPUL_REGNUM
= 23;
4404 tdep
->FPSCR_REGNUM
= 24;
4405 tdep
->FP_LAST_REGNUM
= 40;
4406 tdep
->SSR_REGNUM
= 41;
4407 tdep
->SPC_REGNUM
= 42;
4408 tdep
->DR0_REGNUM
= 59;
4409 tdep
->DR_LAST_REGNUM
= 66;
4410 tdep
->FV0_REGNUM
= 67;
4411 tdep
->FV_LAST_REGNUM
= 70;
4414 tdep
->PR_REGNUM
= 18;
4415 tdep
->SR_REGNUM
= 65;
4416 tdep
->FPSCR_REGNUM
= SIM_SH64_FPCSR_REGNUM
;
4417 tdep
->FP_LAST_REGNUM
= SIM_SH64_FR0_REGNUM
+ SIM_SH64_NR_FP_REGS
- 1;
4418 tdep
->SSR_REGNUM
= SIM_SH64_SSR_REGNUM
;
4419 tdep
->SPC_REGNUM
= SIM_SH64_SPC_REGNUM
;
4420 tdep
->TR7_REGNUM
= SIM_SH64_TR0_REGNUM
+ 7;
4421 tdep
->FPP0_REGNUM
= 173;
4422 tdep
->FPP_LAST_REGNUM
= 204;
4423 tdep
->DR0_REGNUM
= 141;
4424 tdep
->DR_LAST_REGNUM
= 172;
4425 tdep
->FV0_REGNUM
= 205;
4426 tdep
->FV_LAST_REGNUM
= 220;
4427 tdep
->R0_C_REGNUM
= 221;
4428 tdep
->R_LAST_C_REGNUM
= 236;
4429 tdep
->PC_C_REGNUM
= 237;
4430 tdep
->GBR_C_REGNUM
= 238;
4431 tdep
->MACH_C_REGNUM
= 239;
4432 tdep
->MACL_C_REGNUM
= 240;
4433 tdep
->PR_C_REGNUM
= 241;
4434 tdep
->T_C_REGNUM
= 242;
4435 tdep
->FPSCR_C_REGNUM
= 243;
4436 tdep
->FPUL_C_REGNUM
= 244;
4437 tdep
->FP0_C_REGNUM
= 245;
4438 tdep
->FP_LAST_C_REGNUM
= 260;
4439 tdep
->DR0_C_REGNUM
= 261;
4440 tdep
->DR_LAST_C_REGNUM
= 268;
4441 tdep
->FV0_C_REGNUM
= 269;
4442 tdep
->FV_LAST_C_REGNUM
= 272;
4443 tdep
->ARG0_REGNUM
= 2;
4444 tdep
->ARGLAST_REGNUM
= 9;
4445 tdep
->RETURN_REGNUM
= 2;
4446 tdep
->FLOAT_ARGLAST_REGNUM
= 11;
4448 set_gdbarch_num_pseudo_regs (gdbarch
, NUM_PSEUDO_REGS_SH_MEDIA
+ NUM_PSEUDO_REGS_SH_COMPACT
);
4449 set_gdbarch_fp0_regnum (gdbarch
, SIM_SH64_FR0_REGNUM
);
4450 set_gdbarch_pc_regnum (gdbarch
, 64);
4452 /* Determine the ABI */
4453 if (bfd_get_arch_size (info
.abfd
) == 64)
4455 /* If the ABI is the 64-bit one, it can only be sh-media. */
4456 tdep
->sh_abi
= SH_ABI_64
;
4457 set_gdbarch_ptr_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
4458 set_gdbarch_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
4462 /* If the ABI is the 32-bit one it could be either media or
4464 tdep
->sh_abi
= SH_ABI_32
;
4465 set_gdbarch_ptr_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
4466 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
4469 /* the number of real registers is the same whether we are in
4470 ISA16(compact) or ISA32(media). */
4471 set_gdbarch_num_regs (gdbarch
, SIM_SH64_NR_REGS
);
4472 set_gdbarch_register_size (gdbarch
, 8); /*????*/
4473 set_gdbarch_register_bytes (gdbarch
,
4474 ((SIM_SH64_NR_FP_REGS
+ 1) * 4)
4475 + (SIM_SH64_NR_REGS
- SIM_SH64_NR_FP_REGS
-1) * 8);
4477 sh_register_name
= sh_sh64_register_name
;
4478 sh_show_regs
= sh64_show_regs
;
4479 sh_register_virtual_type
= sh_sh64_register_virtual_type
;
4480 sh_store_return_value
= sh64_store_return_value
;
4481 skip_prologue_hard_way
= sh64_skip_prologue_hard_way
;
4482 do_pseudo_register
= sh64_do_pseudo_register
;
4483 set_gdbarch_register_raw_size (gdbarch
, sh_sh64_register_raw_size
);
4484 set_gdbarch_register_virtual_size (gdbarch
, sh_sh64_register_raw_size
);
4485 set_gdbarch_register_byte (gdbarch
, sh_sh64_register_byte
);
4486 /* This seems awfully wrong!*/
4487 /*set_gdbarch_max_register_raw_size (gdbarch, 8);*/
4488 /* should include the size of the pseudo regs. */
4489 set_gdbarch_max_register_raw_size (gdbarch
, 4 * 4);
4490 /* Or should that go in the virtual_size? */
4491 /*set_gdbarch_max_register_virtual_size (gdbarch, 8);*/
4492 set_gdbarch_max_register_virtual_size (gdbarch
, 4 * 4);
4493 set_gdbarch_register_read (gdbarch
, sh64_register_read
);
4494 set_gdbarch_register_write (gdbarch
, sh64_register_write
);
4496 set_gdbarch_do_registers_info (gdbarch
, sh64_do_registers_info
);
4497 set_gdbarch_frame_init_saved_regs (gdbarch
, sh64_nofp_frame_init_saved_regs
);
4498 set_gdbarch_breakpoint_from_pc (gdbarch
, sh_sh64_breakpoint_from_pc
);
4499 set_gdbarch_init_extra_frame_info (gdbarch
, sh64_init_extra_frame_info
);
4500 set_gdbarch_frame_chain (gdbarch
, sh64_frame_chain
);
4501 set_gdbarch_get_saved_register (gdbarch
, sh64_get_saved_register
);
4502 set_gdbarch_deprecated_extract_return_value (gdbarch
, sh64_extract_return_value
);
4503 set_gdbarch_push_arguments (gdbarch
, sh64_push_arguments
);
4504 /*set_gdbarch_store_struct_return (gdbarch, sh64_store_struct_return);*/
4505 set_gdbarch_deprecated_extract_struct_value_address (gdbarch
, sh64_extract_struct_value_address
);
4506 set_gdbarch_use_struct_convention (gdbarch
, sh64_use_struct_convention
);
4507 set_gdbarch_pop_frame (gdbarch
, sh64_pop_frame
);
4508 set_gdbarch_elf_make_msymbol_special (gdbarch
,
4509 sh64_elf_make_msymbol_special
);
4512 sh_register_name
= sh_generic_register_name
;
4513 sh_show_regs
= sh_generic_show_regs
;
4514 sh_store_return_value
= sh_default_store_return_value
;
4515 sh_register_virtual_type
= sh_default_register_virtual_type
;
4516 set_gdbarch_frame_init_saved_regs (gdbarch
, sh_nofp_frame_init_saved_regs
);
4517 set_gdbarch_register_raw_size (gdbarch
, sh_default_register_raw_size
);
4518 set_gdbarch_register_virtual_size (gdbarch
, sh_default_register_raw_size
);
4519 set_gdbarch_register_byte (gdbarch
, sh_default_register_byte
);
4523 set_gdbarch_read_pc (gdbarch
, generic_target_read_pc
);
4524 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
4525 set_gdbarch_read_fp (gdbarch
, generic_target_read_fp
);
4526 set_gdbarch_read_sp (gdbarch
, generic_target_read_sp
);
4527 set_gdbarch_write_sp (gdbarch
, generic_target_write_sp
);
4529 set_gdbarch_register_name (gdbarch
, sh_register_name
);
4530 set_gdbarch_register_virtual_type (gdbarch
, sh_register_virtual_type
);
4532 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
4533 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
4534 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
4535 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
4536 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
4537 set_gdbarch_long_double_bit (gdbarch
, 16 * TARGET_CHAR_BIT
);/*??should be 8?*/
4539 set_gdbarch_use_generic_dummy_frames (gdbarch
, 1);
4540 set_gdbarch_call_dummy_length (gdbarch
, 0);
4541 set_gdbarch_call_dummy_location (gdbarch
, AT_ENTRY_POINT
);
4542 set_gdbarch_call_dummy_address (gdbarch
, entry_point_address
);
4543 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1); /*???*/
4544 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
4545 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
4546 set_gdbarch_pc_in_call_dummy (gdbarch
, generic_pc_in_call_dummy
);
4547 set_gdbarch_call_dummy_words (gdbarch
, sh_call_dummy_words
);
4548 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (sh_call_dummy_words
));
4549 set_gdbarch_call_dummy_p (gdbarch
, 1);
4550 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 0);
4551 set_gdbarch_fix_call_dummy (gdbarch
, generic_fix_call_dummy
);
4552 set_gdbarch_coerce_float_to_double (gdbarch
,
4553 sh_coerce_float_to_double
);
4555 set_gdbarch_push_dummy_frame (gdbarch
, generic_push_dummy_frame
);
4556 set_gdbarch_push_return_address (gdbarch
, sh_push_return_address
);
4558 set_gdbarch_store_return_value (gdbarch
, sh_store_return_value
);
4559 set_gdbarch_skip_prologue (gdbarch
, sh_skip_prologue
);
4560 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
4561 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
4562 set_gdbarch_function_start_offset (gdbarch
, 0);
4564 set_gdbarch_frame_args_skip (gdbarch
, 0);
4565 set_gdbarch_frameless_function_invocation (gdbarch
, frameless_look_for_prologue
);
4566 set_gdbarch_frame_chain_valid (gdbarch
, generic_file_frame_chain_valid
);
4567 set_gdbarch_frame_saved_pc (gdbarch
, sh_frame_saved_pc
);
4568 set_gdbarch_frame_args_address (gdbarch
, default_frame_address
);
4569 set_gdbarch_frame_locals_address (gdbarch
, default_frame_address
);
4570 set_gdbarch_saved_pc_after_call (gdbarch
, sh_saved_pc_after_call
);
4571 set_gdbarch_frame_num_args (gdbarch
, frame_num_args_unknown
);
4572 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
4574 /* Hook in ABI-specific overrides, if they have been registered.
4576 FIXME: if the ABI is unknown, this is probably an embedded target,
4577 so we should not warn about this situation. */
4578 gdbarch_init_osabi (info
, gdbarch
, osabi
);
4584 sh_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
4586 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4591 fprintf_unfiltered (file
, "sh_dump_tdep: OS ABI = %s\n",
4592 gdbarch_osabi_name (tdep
->osabi
));
4596 _initialize_sh_tdep (void)
4598 struct cmd_list_element
*c
;
4600 gdbarch_register (bfd_arch_sh
, sh_gdbarch_init
, sh_dump_tdep
);
4602 add_com ("regs", class_vars
, sh_show_regs_command
, "Print all registers");