1 /* Target-dependent code for Renesas Super-H, for GDB.
3 Copyright (C) 1993-2005, 2007-2012 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20 /* Contributed by Steve Chamberlain
25 #include "frame-base.h"
26 #include "frame-unwind.h"
27 #include "dwarf2-frame.h"
35 #include "gdb_string.h"
36 #include "gdb_assert.h"
37 #include "arch-utils.h"
38 #include "floatformat.h"
42 #include "reggroups.h"
49 #include "solib-svr4.h"
54 /* registers numbers shared with the simulator. */
55 #include "gdb/sim-sh.h"
57 /* List of "set sh ..." and "show sh ..." commands. */
58 static struct cmd_list_element
*setshcmdlist
= NULL
;
59 static struct cmd_list_element
*showshcmdlist
= NULL
;
61 static const char sh_cc_gcc
[] = "gcc";
62 static const char sh_cc_renesas
[] = "renesas";
63 static const char *const sh_cc_enum
[] = {
69 static const char *sh_active_calling_convention
= sh_cc_gcc
;
71 static void (*sh_show_regs
) (struct frame_info
*);
73 #define SH_NUM_REGS 67
82 /* Flag showing that a frame has been created in the prologue code. */
85 /* Saved registers. */
86 CORE_ADDR saved_regs
[SH_NUM_REGS
];
91 sh_is_renesas_calling_convention (struct type
*func_type
)
97 func_type
= check_typedef (func_type
);
99 if (TYPE_CODE (func_type
) == TYPE_CODE_PTR
)
100 func_type
= check_typedef (TYPE_TARGET_TYPE (func_type
));
102 if (TYPE_CODE (func_type
) == TYPE_CODE_FUNC
103 && TYPE_CALLING_CONVENTION (func_type
) == DW_CC_GNU_renesas_sh
)
107 if (sh_active_calling_convention
== sh_cc_renesas
)
114 sh_sh_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
116 static char *register_names
[] = {
117 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
118 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
119 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
121 "", "", "", "", "", "", "", "",
122 "", "", "", "", "", "", "", "",
124 "", "", "", "", "", "", "", "",
125 "", "", "", "", "", "", "", "",
126 "", "", "", "", "", "", "", "",
130 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
132 return register_names
[reg_nr
];
136 sh_sh3_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
138 static char *register_names
[] = {
139 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
140 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
141 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
143 "", "", "", "", "", "", "", "",
144 "", "", "", "", "", "", "", "",
146 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
147 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
148 "", "", "", "", "", "", "", "",
152 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
154 return register_names
[reg_nr
];
158 sh_sh3e_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
160 static char *register_names
[] = {
161 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
162 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
163 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
165 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
166 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
168 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
169 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
170 "", "", "", "", "", "", "", "",
174 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
176 return register_names
[reg_nr
];
180 sh_sh2e_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
182 static char *register_names
[] = {
183 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
184 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
185 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
187 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
188 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
190 "", "", "", "", "", "", "", "",
191 "", "", "", "", "", "", "", "",
192 "", "", "", "", "", "", "", "",
196 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
198 return register_names
[reg_nr
];
202 sh_sh2a_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
204 static char *register_names
[] = {
205 /* general registers 0-15 */
206 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
207 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
209 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
212 /* floating point registers 25 - 40 */
213 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
214 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
217 /* 43 - 62. Banked registers. The bank number used is determined by
218 the bank register (63). */
219 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
220 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
221 "machb", "ivnb", "prb", "gbrb", "maclb",
222 /* 63: register bank number, not a real register but used to
223 communicate the register bank currently get/set. This register
224 is hidden to the user, who manipulates it using the pseudo
225 register called "bank" (67). See below. */
228 "ibcr", "ibnr", "tbr",
229 /* 67: register bank number, the user visible pseudo register. */
231 /* double precision (pseudo) 68 - 75 */
232 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
236 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
238 return register_names
[reg_nr
];
242 sh_sh2a_nofpu_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
244 static char *register_names
[] = {
245 /* general registers 0-15 */
246 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
247 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
249 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
252 /* floating point registers 25 - 40 */
253 "", "", "", "", "", "", "", "",
254 "", "", "", "", "", "", "", "",
257 /* 43 - 62. Banked registers. The bank number used is determined by
258 the bank register (63). */
259 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
260 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
261 "machb", "ivnb", "prb", "gbrb", "maclb",
262 /* 63: register bank number, not a real register but used to
263 communicate the register bank currently get/set. This register
264 is hidden to the user, who manipulates it using the pseudo
265 register called "bank" (67). See below. */
268 "ibcr", "ibnr", "tbr",
269 /* 67: register bank number, the user visible pseudo register. */
271 /* double precision (pseudo) 68 - 75 */
272 "", "", "", "", "", "", "", "",
276 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
278 return register_names
[reg_nr
];
282 sh_sh_dsp_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
284 static char *register_names
[] = {
285 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
286 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
287 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
289 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
290 "y0", "y1", "", "", "", "", "", "mod",
292 "rs", "re", "", "", "", "", "", "",
293 "", "", "", "", "", "", "", "",
294 "", "", "", "", "", "", "", "",
298 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
300 return register_names
[reg_nr
];
304 sh_sh3_dsp_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
306 static char *register_names
[] = {
307 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
308 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
309 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
311 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
312 "y0", "y1", "", "", "", "", "", "mod",
314 "rs", "re", "", "", "", "", "", "",
315 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
316 "", "", "", "", "", "", "", "",
317 "", "", "", "", "", "", "", "",
321 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
323 return register_names
[reg_nr
];
327 sh_sh4_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
329 static char *register_names
[] = {
330 /* general registers 0-15 */
331 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
332 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
334 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
337 /* floating point registers 25 - 40 */
338 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
339 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
343 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
345 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
346 "", "", "", "", "", "", "", "",
347 /* pseudo bank register. */
349 /* double precision (pseudo) 59 - 66 */
350 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
351 /* vectors (pseudo) 67 - 70 */
352 "fv0", "fv4", "fv8", "fv12",
353 /* FIXME: missing XF 71 - 86 */
354 /* FIXME: missing XD 87 - 94 */
358 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
360 return register_names
[reg_nr
];
364 sh_sh4_nofpu_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
366 static char *register_names
[] = {
367 /* general registers 0-15 */
368 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
369 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
371 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
374 /* floating point registers 25 - 40 -- not for nofpu target */
375 "", "", "", "", "", "", "", "",
376 "", "", "", "", "", "", "", "",
380 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
382 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
383 "", "", "", "", "", "", "", "",
384 /* pseudo bank register. */
386 /* double precision (pseudo) 59 - 66 -- not for nofpu target */
387 "", "", "", "", "", "", "", "",
388 /* vectors (pseudo) 67 - 70 -- not for nofpu target */
393 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
395 return register_names
[reg_nr
];
399 sh_sh4al_dsp_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
401 static char *register_names
[] = {
402 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
403 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
404 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
406 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
407 "y0", "y1", "", "", "", "", "", "mod",
409 "rs", "re", "", "", "", "", "", "",
410 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
411 "", "", "", "", "", "", "", "",
412 "", "", "", "", "", "", "", "",
416 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
418 return register_names
[reg_nr
];
421 static const unsigned char *
422 sh_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
, int *lenptr
)
424 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes. */
425 static unsigned char breakpoint
[] = { 0xc3, 0xc3 };
427 /* For remote stub targets, trapa #20 is used. */
428 if (strcmp (target_shortname
, "remote") == 0)
430 static unsigned char big_remote_breakpoint
[] = { 0xc3, 0x20 };
431 static unsigned char little_remote_breakpoint
[] = { 0x20, 0xc3 };
433 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
435 *lenptr
= sizeof (big_remote_breakpoint
);
436 return big_remote_breakpoint
;
440 *lenptr
= sizeof (little_remote_breakpoint
);
441 return little_remote_breakpoint
;
445 *lenptr
= sizeof (breakpoint
);
449 /* Prologue looks like
453 sub <room_for_loca_vars>,r15
456 Actually it can be more complicated than this but that's it, basically. */
458 #define GET_SOURCE_REG(x) (((x) >> 4) & 0xf)
459 #define GET_TARGET_REG(x) (((x) >> 8) & 0xf)
461 /* JSR @Rm 0100mmmm00001011 */
462 #define IS_JSR(x) (((x) & 0xf0ff) == 0x400b)
464 /* STS.L PR,@-r15 0100111100100010
465 r15-4-->r15, PR-->(r15) */
466 #define IS_STS(x) ((x) == 0x4f22)
468 /* STS.L MACL,@-r15 0100111100010010
469 r15-4-->r15, MACL-->(r15) */
470 #define IS_MACL_STS(x) ((x) == 0x4f12)
472 /* MOV.L Rm,@-r15 00101111mmmm0110
473 r15-4-->r15, Rm-->(R15) */
474 #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
476 /* MOV r15,r14 0110111011110011
478 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
480 /* ADD #imm,r15 01111111iiiiiiii
482 #define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00)
484 #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
485 #define IS_SHLL_R3(x) ((x) == 0x4300)
487 /* ADD r3,r15 0011111100111100
489 #define IS_ADD_R3SP(x) ((x) == 0x3f3c)
491 /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
492 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
493 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
494 /* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to
495 make this entirely clear. */
496 /* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */
497 #define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b)
499 /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */
500 #define IS_MOV_ARG_TO_REG(x) \
501 (((x) & 0xf00f) == 0x6003 && \
502 ((x) & 0x00f0) >= 0x0040 && \
503 ((x) & 0x00f0) <= 0x0070)
504 /* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */
505 #define IS_MOV_ARG_TO_IND_R14(x) \
506 (((x) & 0xff0f) == 0x2e02 && \
507 ((x) & 0x00f0) >= 0x0040 && \
508 ((x) & 0x00f0) <= 0x0070)
509 /* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */
510 #define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \
511 (((x) & 0xff00) == 0x1e00 && \
512 ((x) & 0x00f0) >= 0x0040 && \
513 ((x) & 0x00f0) <= 0x0070)
515 /* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */
516 #define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000)
517 /* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */
518 #define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000)
519 /* MOVI20 #imm20,Rn 0000nnnniiii0000 */
520 #define IS_MOVI20(x) (((x) & 0xf00f) == 0x0000)
521 /* SUB Rn,R15 00111111nnnn1000 */
522 #define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08)
524 #define FPSCR_SZ (1 << 20)
526 /* The following instructions are used for epilogue testing. */
527 #define IS_RESTORE_FP(x) ((x) == 0x6ef6)
528 #define IS_RTS(x) ((x) == 0x000b)
529 #define IS_LDS(x) ((x) == 0x4f26)
530 #define IS_MACL_LDS(x) ((x) == 0x4f16)
531 #define IS_MOV_FP_SP(x) ((x) == 0x6fe3)
532 #define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c)
533 #define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00)
536 sh_analyze_prologue (struct gdbarch
*gdbarch
,
537 CORE_ADDR pc
, CORE_ADDR current_pc
,
538 struct sh_frame_cache
*cache
, ULONGEST fpscr
)
540 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
546 int reg
, sav_reg
= -1;
548 if (pc
>= current_pc
)
552 for (opc
= pc
+ (2 * 28); pc
< opc
; pc
+= 2)
554 inst
= read_memory_unsigned_integer (pc
, 2, byte_order
);
555 /* See where the registers will be saved to. */
558 cache
->saved_regs
[GET_SOURCE_REG (inst
)] = cache
->sp_offset
;
559 cache
->sp_offset
+= 4;
561 else if (IS_STS (inst
))
563 cache
->saved_regs
[PR_REGNUM
] = cache
->sp_offset
;
564 cache
->sp_offset
+= 4;
566 else if (IS_MACL_STS (inst
))
568 cache
->saved_regs
[MACL_REGNUM
] = cache
->sp_offset
;
569 cache
->sp_offset
+= 4;
571 else if (IS_MOV_R3 (inst
))
573 r3_val
= ((inst
& 0xff) ^ 0x80) - 0x80;
575 else if (IS_SHLL_R3 (inst
))
579 else if (IS_ADD_R3SP (inst
))
581 cache
->sp_offset
+= -r3_val
;
583 else if (IS_ADD_IMM_SP (inst
))
585 offset
= ((inst
& 0xff) ^ 0x80) - 0x80;
586 cache
->sp_offset
-= offset
;
588 else if (IS_MOVW_PCREL_TO_REG (inst
))
592 reg
= GET_TARGET_REG (inst
);
596 offset
= (inst
& 0xff) << 1;
598 read_memory_integer ((pc
+ 4) + offset
, 2, byte_order
);
602 else if (IS_MOVL_PCREL_TO_REG (inst
))
606 reg
= GET_TARGET_REG (inst
);
610 offset
= (inst
& 0xff) << 2;
612 read_memory_integer (((pc
& 0xfffffffc) + 4) + offset
,
617 else if (IS_MOVI20 (inst
))
621 reg
= GET_TARGET_REG (inst
);
625 sav_offset
= GET_SOURCE_REG (inst
) << 16;
626 /* MOVI20 is a 32 bit instruction! */
629 |= read_memory_unsigned_integer (pc
, 2, byte_order
);
630 /* Now sav_offset contains an unsigned 20 bit value.
631 It must still get sign extended. */
632 if (sav_offset
& 0x00080000)
633 sav_offset
|= 0xfff00000;
637 else if (IS_SUB_REG_FROM_SP (inst
))
639 reg
= GET_SOURCE_REG (inst
);
640 if (sav_reg
> 0 && reg
== sav_reg
)
644 cache
->sp_offset
+= sav_offset
;
646 else if (IS_FPUSH (inst
))
648 if (fpscr
& FPSCR_SZ
)
650 cache
->sp_offset
+= 8;
654 cache
->sp_offset
+= 4;
657 else if (IS_MOV_SP_FP (inst
))
660 /* At this point, only allow argument register moves to other
661 registers or argument register moves to @(X,fp) which are
662 moving the register arguments onto the stack area allocated
663 by a former add somenumber to SP call. Don't allow moving
664 to an fp indirect address above fp + cache->sp_offset. */
666 for (opc
= pc
+ 12; pc
< opc
; pc
+= 2)
668 inst
= read_memory_integer (pc
, 2, byte_order
);
669 if (IS_MOV_ARG_TO_IND_R14 (inst
))
671 reg
= GET_SOURCE_REG (inst
);
672 if (cache
->sp_offset
> 0)
673 cache
->saved_regs
[reg
] = cache
->sp_offset
;
675 else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst
))
677 reg
= GET_SOURCE_REG (inst
);
678 offset
= (inst
& 0xf) * 4;
679 if (cache
->sp_offset
> offset
)
680 cache
->saved_regs
[reg
] = cache
->sp_offset
- offset
;
682 else if (IS_MOV_ARG_TO_REG (inst
))
689 else if (IS_JSR (inst
))
691 /* We have found a jsr that has been scheduled into the prologue.
692 If we continue the scan and return a pc someplace after this,
693 then setting a breakpoint on this function will cause it to
694 appear to be called after the function it is calling via the
695 jsr, which will be very confusing. Most likely the next
696 instruction is going to be IS_MOV_SP_FP in the delay slot. If
697 so, note that before returning the current pc. */
698 inst
= read_memory_integer (pc
+ 2, 2, byte_order
);
699 if (IS_MOV_SP_FP (inst
))
703 #if 0 /* This used to just stop when it found an instruction
704 that was not considered part of the prologue. Now,
705 we just keep going looking for likely
715 /* Skip any prologue before the guts of a function. */
717 sh_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
719 CORE_ADDR post_prologue_pc
, func_addr
;
720 struct sh_frame_cache cache
;
722 /* See if we can determine the end of the prologue via the symbol table.
723 If so, then return either PC, or the PC after the prologue, whichever
725 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
727 post_prologue_pc
= skip_prologue_using_sal (gdbarch
, func_addr
);
728 if (post_prologue_pc
!= 0)
729 return max (pc
, post_prologue_pc
);
732 /* Can't determine prologue from the symbol table, need to examine
735 cache
.sp_offset
= -4;
736 post_prologue_pc
= sh_analyze_prologue (gdbarch
, pc
, (CORE_ADDR
) -1, &cache
, 0);
738 pc
= post_prologue_pc
;
745 Aggregate types not bigger than 8 bytes that have the same size and
746 alignment as one of the integer scalar types are returned in the
747 same registers as the integer type they match.
749 For example, a 2-byte aligned structure with size 2 bytes has the
750 same size and alignment as a short int, and will be returned in R0.
751 A 4-byte aligned structure with size 8 bytes has the same size and
752 alignment as a long long int, and will be returned in R0 and R1.
754 When an aggregate type is returned in R0 and R1, R0 contains the
755 first four bytes of the aggregate, and R1 contains the
756 remainder. If the size of the aggregate type is not a multiple of 4
757 bytes, the aggregate is tail-padded up to a multiple of 4
758 bytes. The value of the padding is undefined. For little-endian
759 targets the padding will appear at the most significant end of the
760 last element, for big-endian targets the padding appears at the
761 least significant end of the last element.
763 All other aggregate types are returned by address. The caller
764 function passes the address of an area large enough to hold the
765 aggregate value in R2. The called function stores the result in
768 To reiterate, structs smaller than 8 bytes could also be returned
769 in memory, if they don't pass the "same size and alignment as an
774 struct s { char c[3]; } wibble;
775 struct s foo(void) { return wibble; }
777 the return value from foo() will be in memory, not
778 in R0, because there is no 3-byte integer type.
782 struct s { char c[2]; } wibble;
783 struct s foo(void) { return wibble; }
785 because a struct containing two chars has alignment 1, that matches
786 type char, but size 2, that matches type short. There's no integer
787 type that has alignment 1 and size 2, so the struct is returned in
791 sh_use_struct_convention (int renesas_abi
, struct type
*type
)
793 int len
= TYPE_LENGTH (type
);
794 int nelem
= TYPE_NFIELDS (type
);
796 /* The Renesas ABI returns aggregate types always on stack. */
797 if (renesas_abi
&& (TYPE_CODE (type
) == TYPE_CODE_STRUCT
798 || TYPE_CODE (type
) == TYPE_CODE_UNION
))
801 /* Non-power of 2 length types and types bigger than 8 bytes (which don't
802 fit in two registers anyway) use struct convention. */
803 if (len
!= 1 && len
!= 2 && len
!= 4 && len
!= 8)
806 /* Scalar types and aggregate types with exactly one field are aligned
807 by definition. They are returned in registers. */
811 /* If the first field in the aggregate has the same length as the entire
812 aggregate type, the type is returned in registers. */
813 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, 0)) == len
)
816 /* If the size of the aggregate is 8 bytes and the first field is
817 of size 4 bytes its alignment is equal to long long's alignment,
818 so it's returned in registers. */
819 if (len
== 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type
, 0)) == 4)
822 /* Otherwise use struct convention. */
827 sh_use_struct_convention_nofpu (int renesas_abi
, struct type
*type
)
829 /* The Renesas ABI returns long longs/doubles etc. always on stack. */
830 if (renesas_abi
&& TYPE_NFIELDS (type
) == 0 && TYPE_LENGTH (type
) >= 8)
832 return sh_use_struct_convention (renesas_abi
, type
);
836 sh_frame_align (struct gdbarch
*ignore
, CORE_ADDR sp
)
841 /* Function: push_dummy_call (formerly push_arguments)
842 Setup the function arguments for calling a function in the inferior.
844 On the Renesas SH architecture, there are four registers (R4 to R7)
845 which are dedicated for passing function arguments. Up to the first
846 four arguments (depending on size) may go into these registers.
847 The rest go on the stack.
849 MVS: Except on SH variants that have floating point registers.
850 In that case, float and double arguments are passed in the same
851 manner, but using FP registers instead of GP registers.
853 Arguments that are smaller than 4 bytes will still take up a whole
854 register or a whole 32-bit word on the stack, and will be
855 right-justified in the register or the stack word. This includes
856 chars, shorts, and small aggregate types.
858 Arguments that are larger than 4 bytes may be split between two or
859 more registers. If there are not enough registers free, an argument
860 may be passed partly in a register (or registers), and partly on the
861 stack. This includes doubles, long longs, and larger aggregates.
862 As far as I know, there is no upper limit to the size of aggregates
863 that will be passed in this way; in other words, the convention of
864 passing a pointer to a large aggregate instead of a copy is not used.
866 MVS: The above appears to be true for the SH variants that do not
867 have an FPU, however those that have an FPU appear to copy the
868 aggregate argument onto the stack (and not place it in registers)
869 if it is larger than 16 bytes (four GP registers).
871 An exceptional case exists for struct arguments (and possibly other
872 aggregates such as arrays) if the size is larger than 4 bytes but
873 not a multiple of 4 bytes. In this case the argument is never split
874 between the registers and the stack, but instead is copied in its
875 entirety onto the stack, AND also copied into as many registers as
876 there is room for. In other words, space in registers permitting,
877 two copies of the same argument are passed in. As far as I can tell,
878 only the one on the stack is used, although that may be a function
879 of the level of compiler optimization. I suspect this is a compiler
880 bug. Arguments of these odd sizes are left-justified within the
881 word (as opposed to arguments smaller than 4 bytes, which are
884 If the function is to return an aggregate type such as a struct, it
885 is either returned in the normal return value register R0 (if its
886 size is no greater than one byte), or else the caller must allocate
887 space into which the callee will copy the return value (if the size
888 is greater than one byte). In this case, a pointer to the return
889 value location is passed into the callee in register R2, which does
890 not displace any of the other arguments passed in via registers R4
893 /* Helper function to justify value in register according to endianess. */
895 sh_justify_value_in_reg (struct gdbarch
*gdbarch
, struct value
*val
, int len
)
897 static char valbuf
[4];
899 memset (valbuf
, 0, sizeof (valbuf
));
902 /* value gets right-justified in the register or stack word. */
903 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
904 memcpy (valbuf
+ (4 - len
), (char *) value_contents (val
), len
);
906 memcpy (valbuf
, (char *) value_contents (val
), len
);
909 return (char *) value_contents (val
);
912 /* Helper function to eval number of bytes to allocate on stack. */
914 sh_stack_allocsize (int nargs
, struct value
**args
)
918 stack_alloc
+= ((TYPE_LENGTH (value_type (args
[nargs
])) + 3) & ~3);
922 /* Helper functions for getting the float arguments right. Registers usage
923 depends on the ABI and the endianess. The comments should enlighten how
924 it's intended to work. */
926 /* This array stores which of the float arg registers are already in use. */
927 static int flt_argreg_array
[FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
+ 1];
929 /* This function just resets the above array to "no reg used so far". */
931 sh_init_flt_argreg (void)
933 memset (flt_argreg_array
, 0, sizeof flt_argreg_array
);
936 /* This function returns the next register to use for float arg passing.
937 It returns either a valid value between FLOAT_ARG0_REGNUM and
938 FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns
939 FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available.
941 Note that register number 0 in flt_argreg_array corresponds with the
942 real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is
943 29) the parity of the register number is preserved, which is important
944 for the double register passing test (see the "argreg & 1" test below). */
946 sh_next_flt_argreg (struct gdbarch
*gdbarch
, int len
, struct type
*func_type
)
950 /* First search for the next free register. */
951 for (argreg
= 0; argreg
<= FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
;
953 if (!flt_argreg_array
[argreg
])
956 /* No register left? */
957 if (argreg
> FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
)
958 return FLOAT_ARGLAST_REGNUM
+ 1;
962 /* Doubles are always starting in a even register number. */
965 /* In gcc ABI, the skipped register is lost for further argument
966 passing now. Not so in Renesas ABI. */
967 if (!sh_is_renesas_calling_convention (func_type
))
968 flt_argreg_array
[argreg
] = 1;
972 /* No register left? */
973 if (argreg
> FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
)
974 return FLOAT_ARGLAST_REGNUM
+ 1;
976 /* Also mark the next register as used. */
977 flt_argreg_array
[argreg
+ 1] = 1;
979 else if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
980 && !sh_is_renesas_calling_convention (func_type
))
982 /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */
983 if (!flt_argreg_array
[argreg
+ 1])
986 flt_argreg_array
[argreg
] = 1;
987 return FLOAT_ARG0_REGNUM
+ argreg
;
990 /* Helper function which figures out, if a type is treated like a float type.
992 The FPU ABIs have a special way how to treat types as float types.
993 Structures with exactly one member, which is of type float or double, are
994 treated exactly as the base types float or double:
1004 are handled the same way as just
1010 As a result, arguments of these struct types are pushed into floating point
1011 registers exactly as floats or doubles, using the same decision algorithm.
1013 The same is valid if these types are used as function return types. The
1014 above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1
1015 or even using struct convention as it is for other structs. */
1018 sh_treat_as_flt_p (struct type
*type
)
1020 int len
= TYPE_LENGTH (type
);
1022 /* Ordinary float types are obviously treated as float. */
1023 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1025 /* Otherwise non-struct types are not treated as float. */
1026 if (TYPE_CODE (type
) != TYPE_CODE_STRUCT
)
1028 /* Otherwise structs with more than one memeber are not treated as float. */
1029 if (TYPE_NFIELDS (type
) != 1)
1031 /* Otherwise if the type of that member is float, the whole type is
1032 treated as float. */
1033 if (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0)) == TYPE_CODE_FLT
)
1035 /* Otherwise it's not treated as float. */
1040 sh_push_dummy_call_fpu (struct gdbarch
*gdbarch
,
1041 struct value
*function
,
1042 struct regcache
*regcache
,
1043 CORE_ADDR bp_addr
, int nargs
,
1044 struct value
**args
,
1045 CORE_ADDR sp
, int struct_return
,
1046 CORE_ADDR struct_addr
)
1048 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1049 int stack_offset
= 0;
1050 int argreg
= ARG0_REGNUM
;
1053 struct type
*func_type
= value_type (function
);
1057 int len
, reg_size
= 0;
1058 int pass_on_stack
= 0;
1060 int last_reg_arg
= INT_MAX
;
1062 /* The Renesas ABI expects all varargs arguments, plus the last
1063 non-vararg argument to be on the stack, no matter how many
1064 registers have been used so far. */
1065 if (sh_is_renesas_calling_convention (func_type
)
1066 && TYPE_VARARGS (func_type
))
1067 last_reg_arg
= TYPE_NFIELDS (func_type
) - 2;
1069 /* First force sp to a 4-byte alignment. */
1070 sp
= sh_frame_align (gdbarch
, sp
);
1072 /* Make room on stack for args. */
1073 sp
-= sh_stack_allocsize (nargs
, args
);
1075 /* Initialize float argument mechanism. */
1076 sh_init_flt_argreg ();
1078 /* Now load as many as possible of the first arguments into
1079 registers, and push the rest onto the stack. There are 16 bytes
1080 in four registers available. Loop thru args from first to last. */
1081 for (argnum
= 0; argnum
< nargs
; argnum
++)
1083 type
= value_type (args
[argnum
]);
1084 len
= TYPE_LENGTH (type
);
1085 val
= sh_justify_value_in_reg (gdbarch
, args
[argnum
], len
);
1087 /* Some decisions have to be made how various types are handled.
1088 This also differs in different ABIs. */
1091 /* Find out the next register to use for a floating point value. */
1092 treat_as_flt
= sh_treat_as_flt_p (type
);
1094 flt_argreg
= sh_next_flt_argreg (gdbarch
, len
, func_type
);
1095 /* In Renesas ABI, long longs and aggregate types are always passed
1097 else if (sh_is_renesas_calling_convention (func_type
)
1098 && ((TYPE_CODE (type
) == TYPE_CODE_INT
&& len
== 8)
1099 || TYPE_CODE (type
) == TYPE_CODE_STRUCT
1100 || TYPE_CODE (type
) == TYPE_CODE_UNION
))
1102 /* In contrast to non-FPU CPUs, arguments are never split between
1103 registers and stack. If an argument doesn't fit in the remaining
1104 registers it's always pushed entirely on the stack. */
1105 else if (len
> ((ARGLAST_REGNUM
- argreg
+ 1) * 4))
1110 if ((treat_as_flt
&& flt_argreg
> FLOAT_ARGLAST_REGNUM
)
1111 || (!treat_as_flt
&& (argreg
> ARGLAST_REGNUM
1113 || argnum
> last_reg_arg
)
1115 /* The data goes entirely on the stack, 4-byte aligned. */
1116 reg_size
= (len
+ 3) & ~3;
1117 write_memory (sp
+ stack_offset
, val
, reg_size
);
1118 stack_offset
+= reg_size
;
1120 else if (treat_as_flt
&& flt_argreg
<= FLOAT_ARGLAST_REGNUM
)
1122 /* Argument goes in a float argument register. */
1123 reg_size
= register_size (gdbarch
, flt_argreg
);
1124 regval
= extract_unsigned_integer (val
, reg_size
, byte_order
);
1125 /* In little endian mode, float types taking two registers
1126 (doubles on sh4, long doubles on sh2e, sh3e and sh4) must
1127 be stored swapped in the argument registers. The below
1128 code first writes the first 32 bits in the next but one
1129 register, increments the val and len values accordingly
1130 and then proceeds as normal by writing the second 32 bits
1131 into the next register. */
1132 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
1133 && TYPE_LENGTH (type
) == 2 * reg_size
)
1135 regcache_cooked_write_unsigned (regcache
, flt_argreg
+ 1,
1139 regval
= extract_unsigned_integer (val
, reg_size
,
1142 regcache_cooked_write_unsigned (regcache
, flt_argreg
++, regval
);
1144 else if (!treat_as_flt
&& argreg
<= ARGLAST_REGNUM
)
1146 /* there's room in a register */
1147 reg_size
= register_size (gdbarch
, argreg
);
1148 regval
= extract_unsigned_integer (val
, reg_size
, byte_order
);
1149 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
1151 /* Store the value one register at a time or in one step on
1160 if (sh_is_renesas_calling_convention (func_type
))
1161 /* If the function uses the Renesas ABI, subtract another 4 bytes from
1162 the stack and store the struct return address there. */
1163 write_memory_unsigned_integer (sp
-= 4, 4, byte_order
, struct_addr
);
1165 /* Using the gcc ABI, the "struct return pointer" pseudo-argument has
1166 its own dedicated register. */
1167 regcache_cooked_write_unsigned (regcache
,
1168 STRUCT_RETURN_REGNUM
, struct_addr
);
1171 /* Store return address. */
1172 regcache_cooked_write_unsigned (regcache
, PR_REGNUM
, bp_addr
);
1174 /* Update stack pointer. */
1175 regcache_cooked_write_unsigned (regcache
,
1176 gdbarch_sp_regnum (gdbarch
), sp
);
1182 sh_push_dummy_call_nofpu (struct gdbarch
*gdbarch
,
1183 struct value
*function
,
1184 struct regcache
*regcache
,
1186 int nargs
, struct value
**args
,
1187 CORE_ADDR sp
, int struct_return
,
1188 CORE_ADDR struct_addr
)
1190 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1191 int stack_offset
= 0;
1192 int argreg
= ARG0_REGNUM
;
1194 struct type
*func_type
= value_type (function
);
1198 int len
, reg_size
= 0;
1199 int pass_on_stack
= 0;
1200 int last_reg_arg
= INT_MAX
;
1202 /* The Renesas ABI expects all varargs arguments, plus the last
1203 non-vararg argument to be on the stack, no matter how many
1204 registers have been used so far. */
1205 if (sh_is_renesas_calling_convention (func_type
)
1206 && TYPE_VARARGS (func_type
))
1207 last_reg_arg
= TYPE_NFIELDS (func_type
) - 2;
1209 /* First force sp to a 4-byte alignment. */
1210 sp
= sh_frame_align (gdbarch
, sp
);
1212 /* Make room on stack for args. */
1213 sp
-= sh_stack_allocsize (nargs
, args
);
1215 /* Now load as many as possible of the first arguments into
1216 registers, and push the rest onto the stack. There are 16 bytes
1217 in four registers available. Loop thru args from first to last. */
1218 for (argnum
= 0; argnum
< nargs
; argnum
++)
1220 type
= value_type (args
[argnum
]);
1221 len
= TYPE_LENGTH (type
);
1222 val
= sh_justify_value_in_reg (gdbarch
, args
[argnum
], len
);
1224 /* Some decisions have to be made how various types are handled.
1225 This also differs in different ABIs. */
1227 /* Renesas ABI pushes doubles and long longs entirely on stack.
1228 Same goes for aggregate types. */
1229 if (sh_is_renesas_calling_convention (func_type
)
1230 && ((TYPE_CODE (type
) == TYPE_CODE_INT
&& len
>= 8)
1231 || (TYPE_CODE (type
) == TYPE_CODE_FLT
&& len
>= 8)
1232 || TYPE_CODE (type
) == TYPE_CODE_STRUCT
1233 || TYPE_CODE (type
) == TYPE_CODE_UNION
))
1237 if (argreg
> ARGLAST_REGNUM
|| pass_on_stack
1238 || argnum
> last_reg_arg
)
1240 /* The remainder of the data goes entirely on the stack,
1242 reg_size
= (len
+ 3) & ~3;
1243 write_memory (sp
+ stack_offset
, val
, reg_size
);
1244 stack_offset
+= reg_size
;
1246 else if (argreg
<= ARGLAST_REGNUM
)
1248 /* There's room in a register. */
1249 reg_size
= register_size (gdbarch
, argreg
);
1250 regval
= extract_unsigned_integer (val
, reg_size
, byte_order
);
1251 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
1253 /* Store the value reg_size bytes at a time. This means that things
1254 larger than reg_size bytes may go partly in registers and partly
1263 if (sh_is_renesas_calling_convention (func_type
))
1264 /* If the function uses the Renesas ABI, subtract another 4 bytes from
1265 the stack and store the struct return address there. */
1266 write_memory_unsigned_integer (sp
-= 4, 4, byte_order
, struct_addr
);
1268 /* Using the gcc ABI, the "struct return pointer" pseudo-argument has
1269 its own dedicated register. */
1270 regcache_cooked_write_unsigned (regcache
,
1271 STRUCT_RETURN_REGNUM
, struct_addr
);
1274 /* Store return address. */
1275 regcache_cooked_write_unsigned (regcache
, PR_REGNUM
, bp_addr
);
1277 /* Update stack pointer. */
1278 regcache_cooked_write_unsigned (regcache
,
1279 gdbarch_sp_regnum (gdbarch
), sp
);
1284 /* Find a function's return value in the appropriate registers (in
1285 regbuf), and copy it into valbuf. Extract from an array REGBUF
1286 containing the (raw) register state a function return value of type
1287 TYPE, and copy that, in virtual format, into VALBUF. */
1289 sh_extract_return_value_nofpu (struct type
*type
, struct regcache
*regcache
,
1292 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1293 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1294 int len
= TYPE_LENGTH (type
);
1295 int return_register
= R0_REGNUM
;
1302 regcache_cooked_read_unsigned (regcache
, R0_REGNUM
, &c
);
1303 store_unsigned_integer (valbuf
, len
, byte_order
, c
);
1307 int i
, regnum
= R0_REGNUM
;
1308 for (i
= 0; i
< len
; i
+= 4)
1309 regcache_raw_read (regcache
, regnum
++, (char *) valbuf
+ i
);
1312 error (_("bad size for return value"));
1316 sh_extract_return_value_fpu (struct type
*type
, struct regcache
*regcache
,
1319 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1320 if (sh_treat_as_flt_p (type
))
1322 int len
= TYPE_LENGTH (type
);
1323 int i
, regnum
= gdbarch_fp0_regnum (gdbarch
);
1324 for (i
= 0; i
< len
; i
+= 4)
1325 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
1326 regcache_raw_read (regcache
, regnum
++,
1327 (char *) valbuf
+ len
- 4 - i
);
1329 regcache_raw_read (regcache
, regnum
++, (char *) valbuf
+ i
);
1332 sh_extract_return_value_nofpu (type
, regcache
, valbuf
);
1335 /* Write into appropriate registers a function return value
1336 of type TYPE, given in virtual format.
1337 If the architecture is sh4 or sh3e, store a function's return value
1338 in the R0 general register or in the FP0 floating point register,
1339 depending on the type of the return value. In all the other cases
1340 the result is stored in r0, left-justified. */
1342 sh_store_return_value_nofpu (struct type
*type
, struct regcache
*regcache
,
1345 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1346 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1348 int len
= TYPE_LENGTH (type
);
1352 val
= extract_unsigned_integer (valbuf
, len
, byte_order
);
1353 regcache_cooked_write_unsigned (regcache
, R0_REGNUM
, val
);
1357 int i
, regnum
= R0_REGNUM
;
1358 for (i
= 0; i
< len
; i
+= 4)
1359 regcache_raw_write (regcache
, regnum
++, (char *) valbuf
+ i
);
1364 sh_store_return_value_fpu (struct type
*type
, struct regcache
*regcache
,
1367 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1368 if (sh_treat_as_flt_p (type
))
1370 int len
= TYPE_LENGTH (type
);
1371 int i
, regnum
= gdbarch_fp0_regnum (gdbarch
);
1372 for (i
= 0; i
< len
; i
+= 4)
1373 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
1374 regcache_raw_write (regcache
, regnum
++,
1375 (char *) valbuf
+ len
- 4 - i
);
1377 regcache_raw_write (regcache
, regnum
++, (char *) valbuf
+ i
);
1380 sh_store_return_value_nofpu (type
, regcache
, valbuf
);
1383 static enum return_value_convention
1384 sh_return_value_nofpu (struct gdbarch
*gdbarch
, struct type
*func_type
,
1385 struct type
*type
, struct regcache
*regcache
,
1386 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1388 if (sh_use_struct_convention_nofpu (
1389 sh_is_renesas_calling_convention (func_type
), type
))
1390 return RETURN_VALUE_STRUCT_CONVENTION
;
1392 sh_store_return_value_nofpu (type
, regcache
, writebuf
);
1394 sh_extract_return_value_nofpu (type
, regcache
, readbuf
);
1395 return RETURN_VALUE_REGISTER_CONVENTION
;
1398 static enum return_value_convention
1399 sh_return_value_fpu (struct gdbarch
*gdbarch
, struct type
*func_type
,
1400 struct type
*type
, struct regcache
*regcache
,
1401 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1403 if (sh_use_struct_convention (
1404 sh_is_renesas_calling_convention (func_type
), type
))
1405 return RETURN_VALUE_STRUCT_CONVENTION
;
1407 sh_store_return_value_fpu (type
, regcache
, writebuf
);
1409 sh_extract_return_value_fpu (type
, regcache
, readbuf
);
1410 return RETURN_VALUE_REGISTER_CONVENTION
;
1413 /* Print the registers in a form similar to the E7000. */
1416 sh_generic_show_regs (struct frame_info
*frame
)
1419 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1420 phex (get_frame_register_unsigned (frame
,
1422 (get_frame_arch (frame
))), 4),
1423 (long) get_frame_register_unsigned (frame
, SR_REGNUM
),
1424 (long) get_frame_register_unsigned (frame
, PR_REGNUM
),
1425 (long) get_frame_register_unsigned (frame
, MACH_REGNUM
));
1428 (" GBR %08lx VBR %08lx MACL %08lx\n",
1429 (long) get_frame_register_unsigned (frame
, GBR_REGNUM
),
1430 (long) get_frame_register_unsigned (frame
, VBR_REGNUM
),
1431 (long) get_frame_register_unsigned (frame
, MACL_REGNUM
));
1434 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1435 (long) get_frame_register_unsigned (frame
, 0),
1436 (long) get_frame_register_unsigned (frame
, 1),
1437 (long) get_frame_register_unsigned (frame
, 2),
1438 (long) get_frame_register_unsigned (frame
, 3),
1439 (long) get_frame_register_unsigned (frame
, 4),
1440 (long) get_frame_register_unsigned (frame
, 5),
1441 (long) get_frame_register_unsigned (frame
, 6),
1442 (long) get_frame_register_unsigned (frame
, 7));
1444 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1445 (long) get_frame_register_unsigned (frame
, 8),
1446 (long) get_frame_register_unsigned (frame
, 9),
1447 (long) get_frame_register_unsigned (frame
, 10),
1448 (long) get_frame_register_unsigned (frame
, 11),
1449 (long) get_frame_register_unsigned (frame
, 12),
1450 (long) get_frame_register_unsigned (frame
, 13),
1451 (long) get_frame_register_unsigned (frame
, 14),
1452 (long) get_frame_register_unsigned (frame
, 15));
1456 sh3_show_regs (struct frame_info
*frame
)
1459 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1460 phex (get_frame_register_unsigned (frame
,
1462 (get_frame_arch (frame
))), 4),
1463 (long) get_frame_register_unsigned (frame
, SR_REGNUM
),
1464 (long) get_frame_register_unsigned (frame
, PR_REGNUM
),
1465 (long) get_frame_register_unsigned (frame
, MACH_REGNUM
));
1468 (" GBR %08lx VBR %08lx MACL %08lx\n",
1469 (long) get_frame_register_unsigned (frame
, GBR_REGNUM
),
1470 (long) get_frame_register_unsigned (frame
, VBR_REGNUM
),
1471 (long) get_frame_register_unsigned (frame
, MACL_REGNUM
));
1473 (" SSR %08lx SPC %08lx\n",
1474 (long) get_frame_register_unsigned (frame
, SSR_REGNUM
),
1475 (long) get_frame_register_unsigned (frame
, SPC_REGNUM
));
1478 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1479 (long) get_frame_register_unsigned (frame
, 0),
1480 (long) get_frame_register_unsigned (frame
, 1),
1481 (long) get_frame_register_unsigned (frame
, 2),
1482 (long) get_frame_register_unsigned (frame
, 3),
1483 (long) get_frame_register_unsigned (frame
, 4),
1484 (long) get_frame_register_unsigned (frame
, 5),
1485 (long) get_frame_register_unsigned (frame
, 6),
1486 (long) get_frame_register_unsigned (frame
, 7));
1488 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1489 (long) get_frame_register_unsigned (frame
, 8),
1490 (long) get_frame_register_unsigned (frame
, 9),
1491 (long) get_frame_register_unsigned (frame
, 10),
1492 (long) get_frame_register_unsigned (frame
, 11),
1493 (long) get_frame_register_unsigned (frame
, 12),
1494 (long) get_frame_register_unsigned (frame
, 13),
1495 (long) get_frame_register_unsigned (frame
, 14),
1496 (long) get_frame_register_unsigned (frame
, 15));
1500 sh2e_show_regs (struct frame_info
*frame
)
1502 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1504 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1505 phex (get_frame_register_unsigned (frame
,
1506 gdbarch_pc_regnum (gdbarch
)), 4),
1507 (long) get_frame_register_unsigned (frame
, SR_REGNUM
),
1508 (long) get_frame_register_unsigned (frame
, PR_REGNUM
),
1509 (long) get_frame_register_unsigned (frame
, MACH_REGNUM
));
1512 (" GBR %08lx VBR %08lx MACL %08lx\n",
1513 (long) get_frame_register_unsigned (frame
, GBR_REGNUM
),
1514 (long) get_frame_register_unsigned (frame
, VBR_REGNUM
),
1515 (long) get_frame_register_unsigned (frame
, MACL_REGNUM
));
1517 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1518 (long) get_frame_register_unsigned (frame
, SSR_REGNUM
),
1519 (long) get_frame_register_unsigned (frame
, SPC_REGNUM
),
1520 (long) get_frame_register_unsigned (frame
, FPUL_REGNUM
),
1521 (long) get_frame_register_unsigned (frame
, FPSCR_REGNUM
));
1524 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1525 (long) get_frame_register_unsigned (frame
, 0),
1526 (long) get_frame_register_unsigned (frame
, 1),
1527 (long) get_frame_register_unsigned (frame
, 2),
1528 (long) get_frame_register_unsigned (frame
, 3),
1529 (long) get_frame_register_unsigned (frame
, 4),
1530 (long) get_frame_register_unsigned (frame
, 5),
1531 (long) get_frame_register_unsigned (frame
, 6),
1532 (long) get_frame_register_unsigned (frame
, 7));
1534 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1535 (long) get_frame_register_unsigned (frame
, 8),
1536 (long) get_frame_register_unsigned (frame
, 9),
1537 (long) get_frame_register_unsigned (frame
, 10),
1538 (long) get_frame_register_unsigned (frame
, 11),
1539 (long) get_frame_register_unsigned (frame
, 12),
1540 (long) get_frame_register_unsigned (frame
, 13),
1541 (long) get_frame_register_unsigned (frame
, 14),
1542 (long) get_frame_register_unsigned (frame
, 15));
1545 ("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1546 (long) get_frame_register_unsigned
1547 (frame
, gdbarch_fp0_regnum (gdbarch
) + 0),
1548 (long) get_frame_register_unsigned
1549 (frame
, gdbarch_fp0_regnum (gdbarch
) + 1),
1550 (long) get_frame_register_unsigned
1551 (frame
, gdbarch_fp0_regnum (gdbarch
) + 2),
1552 (long) get_frame_register_unsigned
1553 (frame
, gdbarch_fp0_regnum (gdbarch
) + 3),
1554 (long) get_frame_register_unsigned
1555 (frame
, gdbarch_fp0_regnum (gdbarch
) + 4),
1556 (long) get_frame_register_unsigned
1557 (frame
, gdbarch_fp0_regnum (gdbarch
) + 5),
1558 (long) get_frame_register_unsigned
1559 (frame
, gdbarch_fp0_regnum (gdbarch
) + 6),
1560 (long) get_frame_register_unsigned
1561 (frame
, gdbarch_fp0_regnum (gdbarch
) + 7));
1563 ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1564 (long) get_frame_register_unsigned
1565 (frame
, gdbarch_fp0_regnum (gdbarch
) + 8),
1566 (long) get_frame_register_unsigned
1567 (frame
, gdbarch_fp0_regnum (gdbarch
) + 9),
1568 (long) get_frame_register_unsigned
1569 (frame
, gdbarch_fp0_regnum (gdbarch
) + 10),
1570 (long) get_frame_register_unsigned
1571 (frame
, gdbarch_fp0_regnum (gdbarch
) + 11),
1572 (long) get_frame_register_unsigned
1573 (frame
, gdbarch_fp0_regnum (gdbarch
) + 12),
1574 (long) get_frame_register_unsigned
1575 (frame
, gdbarch_fp0_regnum (gdbarch
) + 13),
1576 (long) get_frame_register_unsigned
1577 (frame
, gdbarch_fp0_regnum (gdbarch
) + 14),
1578 (long) get_frame_register_unsigned
1579 (frame
, gdbarch_fp0_regnum (gdbarch
) + 15));
1583 sh2a_show_regs (struct frame_info
*frame
)
1585 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1586 int pr
= get_frame_register_unsigned (frame
, FPSCR_REGNUM
) & 0x80000;
1589 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1590 phex (get_frame_register_unsigned (frame
,
1591 gdbarch_pc_regnum (gdbarch
)), 4),
1592 (long) get_frame_register_unsigned (frame
, SR_REGNUM
),
1593 (long) get_frame_register_unsigned (frame
, PR_REGNUM
),
1594 (long) get_frame_register_unsigned (frame
, MACH_REGNUM
));
1597 (" GBR %08lx VBR %08lx TBR %08lx MACL %08lx\n",
1598 (long) get_frame_register_unsigned (frame
, GBR_REGNUM
),
1599 (long) get_frame_register_unsigned (frame
, VBR_REGNUM
),
1600 (long) get_frame_register_unsigned (frame
, TBR_REGNUM
),
1601 (long) get_frame_register_unsigned (frame
, MACL_REGNUM
));
1603 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1604 (long) get_frame_register_unsigned (frame
, SSR_REGNUM
),
1605 (long) get_frame_register_unsigned (frame
, SPC_REGNUM
),
1606 (long) get_frame_register_unsigned (frame
, FPUL_REGNUM
),
1607 (long) get_frame_register_unsigned (frame
, FPSCR_REGNUM
));
1610 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1611 (long) get_frame_register_unsigned (frame
, 0),
1612 (long) get_frame_register_unsigned (frame
, 1),
1613 (long) get_frame_register_unsigned (frame
, 2),
1614 (long) get_frame_register_unsigned (frame
, 3),
1615 (long) get_frame_register_unsigned (frame
, 4),
1616 (long) get_frame_register_unsigned (frame
, 5),
1617 (long) get_frame_register_unsigned (frame
, 6),
1618 (long) get_frame_register_unsigned (frame
, 7));
1620 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1621 (long) get_frame_register_unsigned (frame
, 8),
1622 (long) get_frame_register_unsigned (frame
, 9),
1623 (long) get_frame_register_unsigned (frame
, 10),
1624 (long) get_frame_register_unsigned (frame
, 11),
1625 (long) get_frame_register_unsigned (frame
, 12),
1626 (long) get_frame_register_unsigned (frame
, 13),
1627 (long) get_frame_register_unsigned (frame
, 14),
1628 (long) get_frame_register_unsigned (frame
, 15));
1631 (pr
? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1632 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1633 (long) get_frame_register_unsigned
1634 (frame
, gdbarch_fp0_regnum (gdbarch
) + 0),
1635 (long) get_frame_register_unsigned
1636 (frame
, gdbarch_fp0_regnum (gdbarch
) + 1),
1637 (long) get_frame_register_unsigned
1638 (frame
, gdbarch_fp0_regnum (gdbarch
) + 2),
1639 (long) get_frame_register_unsigned
1640 (frame
, gdbarch_fp0_regnum (gdbarch
) + 3),
1641 (long) get_frame_register_unsigned
1642 (frame
, gdbarch_fp0_regnum (gdbarch
) + 4),
1643 (long) get_frame_register_unsigned
1644 (frame
, gdbarch_fp0_regnum (gdbarch
) + 5),
1645 (long) get_frame_register_unsigned
1646 (frame
, gdbarch_fp0_regnum (gdbarch
) + 6),
1647 (long) get_frame_register_unsigned
1648 (frame
, gdbarch_fp0_regnum (gdbarch
) + 7));
1650 (pr
? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1651 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1652 (long) get_frame_register_unsigned
1653 (frame
, gdbarch_fp0_regnum (gdbarch
) + 8),
1654 (long) get_frame_register_unsigned
1655 (frame
, gdbarch_fp0_regnum (gdbarch
) + 9),
1656 (long) get_frame_register_unsigned
1657 (frame
, gdbarch_fp0_regnum (gdbarch
) + 10),
1658 (long) get_frame_register_unsigned
1659 (frame
, gdbarch_fp0_regnum (gdbarch
) + 11),
1660 (long) get_frame_register_unsigned
1661 (frame
, gdbarch_fp0_regnum (gdbarch
) + 12),
1662 (long) get_frame_register_unsigned
1663 (frame
, gdbarch_fp0_regnum (gdbarch
) + 13),
1664 (long) get_frame_register_unsigned
1665 (frame
, gdbarch_fp0_regnum (gdbarch
) + 14),
1666 (long) get_frame_register_unsigned
1667 (frame
, gdbarch_fp0_regnum (gdbarch
) + 15));
1669 ("BANK=%-3d\n", (int) get_frame_register_unsigned (frame
, BANK_REGNUM
));
1671 ("R0b-R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1672 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 0),
1673 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 1),
1674 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 2),
1675 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 3),
1676 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 4),
1677 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 5),
1678 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 6),
1679 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 7));
1681 ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1682 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 8),
1683 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 9),
1684 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 10),
1685 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 11),
1686 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 12),
1687 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 13),
1688 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 14));
1690 ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n",
1691 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 15),
1692 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 16),
1693 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 17),
1694 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 18),
1695 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 19));
1699 sh2a_nofpu_show_regs (struct frame_info
*frame
)
1701 int pr
= get_frame_register_unsigned (frame
, FPSCR_REGNUM
) & 0x80000;
1704 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1705 phex (get_frame_register_unsigned (frame
,
1707 (get_frame_arch (frame
))), 4),
1708 (long) get_frame_register_unsigned (frame
, SR_REGNUM
),
1709 (long) get_frame_register_unsigned (frame
, PR_REGNUM
),
1710 (long) get_frame_register_unsigned (frame
, MACH_REGNUM
));
1713 (" GBR %08lx VBR %08lx TBR %08lx MACL %08lx\n",
1714 (long) get_frame_register_unsigned (frame
, GBR_REGNUM
),
1715 (long) get_frame_register_unsigned (frame
, VBR_REGNUM
),
1716 (long) get_frame_register_unsigned (frame
, TBR_REGNUM
),
1717 (long) get_frame_register_unsigned (frame
, MACL_REGNUM
));
1719 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1720 (long) get_frame_register_unsigned (frame
, SSR_REGNUM
),
1721 (long) get_frame_register_unsigned (frame
, SPC_REGNUM
),
1722 (long) get_frame_register_unsigned (frame
, FPUL_REGNUM
),
1723 (long) get_frame_register_unsigned (frame
, FPSCR_REGNUM
));
1726 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1727 (long) get_frame_register_unsigned (frame
, 0),
1728 (long) get_frame_register_unsigned (frame
, 1),
1729 (long) get_frame_register_unsigned (frame
, 2),
1730 (long) get_frame_register_unsigned (frame
, 3),
1731 (long) get_frame_register_unsigned (frame
, 4),
1732 (long) get_frame_register_unsigned (frame
, 5),
1733 (long) get_frame_register_unsigned (frame
, 6),
1734 (long) get_frame_register_unsigned (frame
, 7));
1736 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1737 (long) get_frame_register_unsigned (frame
, 8),
1738 (long) get_frame_register_unsigned (frame
, 9),
1739 (long) get_frame_register_unsigned (frame
, 10),
1740 (long) get_frame_register_unsigned (frame
, 11),
1741 (long) get_frame_register_unsigned (frame
, 12),
1742 (long) get_frame_register_unsigned (frame
, 13),
1743 (long) get_frame_register_unsigned (frame
, 14),
1744 (long) get_frame_register_unsigned (frame
, 15));
1747 ("BANK=%-3d\n", (int) get_frame_register_unsigned (frame
, BANK_REGNUM
));
1749 ("R0b-R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1750 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 0),
1751 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 1),
1752 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 2),
1753 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 3),
1754 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 4),
1755 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 5),
1756 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 6),
1757 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 7));
1759 ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1760 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 8),
1761 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 9),
1762 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 10),
1763 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 11),
1764 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 12),
1765 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 13),
1766 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 14));
1768 ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n",
1769 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 15),
1770 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 16),
1771 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 17),
1772 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 18),
1773 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 19));
1777 sh3e_show_regs (struct frame_info
*frame
)
1779 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1781 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1782 phex (get_frame_register_unsigned (frame
,
1783 gdbarch_pc_regnum (gdbarch
)), 4),
1784 (long) get_frame_register_unsigned (frame
, SR_REGNUM
),
1785 (long) get_frame_register_unsigned (frame
, PR_REGNUM
),
1786 (long) get_frame_register_unsigned (frame
, MACH_REGNUM
));
1789 (" GBR %08lx VBR %08lx MACL %08lx\n",
1790 (long) get_frame_register_unsigned (frame
, GBR_REGNUM
),
1791 (long) get_frame_register_unsigned (frame
, VBR_REGNUM
),
1792 (long) get_frame_register_unsigned (frame
, MACL_REGNUM
));
1794 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1795 (long) get_frame_register_unsigned (frame
, SSR_REGNUM
),
1796 (long) get_frame_register_unsigned (frame
, SPC_REGNUM
),
1797 (long) get_frame_register_unsigned (frame
, FPUL_REGNUM
),
1798 (long) get_frame_register_unsigned (frame
, FPSCR_REGNUM
));
1801 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1802 (long) get_frame_register_unsigned (frame
, 0),
1803 (long) get_frame_register_unsigned (frame
, 1),
1804 (long) get_frame_register_unsigned (frame
, 2),
1805 (long) get_frame_register_unsigned (frame
, 3),
1806 (long) get_frame_register_unsigned (frame
, 4),
1807 (long) get_frame_register_unsigned (frame
, 5),
1808 (long) get_frame_register_unsigned (frame
, 6),
1809 (long) get_frame_register_unsigned (frame
, 7));
1811 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1812 (long) get_frame_register_unsigned (frame
, 8),
1813 (long) get_frame_register_unsigned (frame
, 9),
1814 (long) get_frame_register_unsigned (frame
, 10),
1815 (long) get_frame_register_unsigned (frame
, 11),
1816 (long) get_frame_register_unsigned (frame
, 12),
1817 (long) get_frame_register_unsigned (frame
, 13),
1818 (long) get_frame_register_unsigned (frame
, 14),
1819 (long) get_frame_register_unsigned (frame
, 15));
1822 ("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1823 (long) get_frame_register_unsigned
1824 (frame
, gdbarch_fp0_regnum (gdbarch
) + 0),
1825 (long) get_frame_register_unsigned
1826 (frame
, gdbarch_fp0_regnum (gdbarch
) + 1),
1827 (long) get_frame_register_unsigned
1828 (frame
, gdbarch_fp0_regnum (gdbarch
) + 2),
1829 (long) get_frame_register_unsigned
1830 (frame
, gdbarch_fp0_regnum (gdbarch
) + 3),
1831 (long) get_frame_register_unsigned
1832 (frame
, gdbarch_fp0_regnum (gdbarch
) + 4),
1833 (long) get_frame_register_unsigned
1834 (frame
, gdbarch_fp0_regnum (gdbarch
) + 5),
1835 (long) get_frame_register_unsigned
1836 (frame
, gdbarch_fp0_regnum (gdbarch
) + 6),
1837 (long) get_frame_register_unsigned
1838 (frame
, gdbarch_fp0_regnum (gdbarch
) + 7));
1840 ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1841 (long) get_frame_register_unsigned
1842 (frame
, gdbarch_fp0_regnum (gdbarch
) + 8),
1843 (long) get_frame_register_unsigned
1844 (frame
, gdbarch_fp0_regnum (gdbarch
) + 9),
1845 (long) get_frame_register_unsigned
1846 (frame
, gdbarch_fp0_regnum (gdbarch
) + 10),
1847 (long) get_frame_register_unsigned
1848 (frame
, gdbarch_fp0_regnum (gdbarch
) + 11),
1849 (long) get_frame_register_unsigned
1850 (frame
, gdbarch_fp0_regnum (gdbarch
) + 12),
1851 (long) get_frame_register_unsigned
1852 (frame
, gdbarch_fp0_regnum (gdbarch
) + 13),
1853 (long) get_frame_register_unsigned
1854 (frame
, gdbarch_fp0_regnum (gdbarch
) + 14),
1855 (long) get_frame_register_unsigned
1856 (frame
, gdbarch_fp0_regnum (gdbarch
) + 15));
1860 sh3_dsp_show_regs (struct frame_info
*frame
)
1863 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1864 phex (get_frame_register_unsigned (frame
,
1866 (get_frame_arch (frame
))), 4),
1867 (long) get_frame_register_unsigned (frame
, SR_REGNUM
),
1868 (long) get_frame_register_unsigned (frame
, PR_REGNUM
),
1869 (long) get_frame_register_unsigned (frame
, MACH_REGNUM
));
1872 (" GBR %08lx VBR %08lx MACL %08lx\n",
1873 (long) get_frame_register_unsigned (frame
, GBR_REGNUM
),
1874 (long) get_frame_register_unsigned (frame
, VBR_REGNUM
),
1875 (long) get_frame_register_unsigned (frame
, MACL_REGNUM
));
1878 (" SSR %08lx SPC %08lx DSR %08lx\n",
1879 (long) get_frame_register_unsigned (frame
, SSR_REGNUM
),
1880 (long) get_frame_register_unsigned (frame
, SPC_REGNUM
),
1881 (long) get_frame_register_unsigned (frame
, DSR_REGNUM
));
1884 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1885 (long) get_frame_register_unsigned (frame
, 0),
1886 (long) get_frame_register_unsigned (frame
, 1),
1887 (long) get_frame_register_unsigned (frame
, 2),
1888 (long) get_frame_register_unsigned (frame
, 3),
1889 (long) get_frame_register_unsigned (frame
, 4),
1890 (long) get_frame_register_unsigned (frame
, 5),
1891 (long) get_frame_register_unsigned (frame
, 6),
1892 (long) get_frame_register_unsigned (frame
, 7));
1894 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1895 (long) get_frame_register_unsigned (frame
, 8),
1896 (long) get_frame_register_unsigned (frame
, 9),
1897 (long) get_frame_register_unsigned (frame
, 10),
1898 (long) get_frame_register_unsigned (frame
, 11),
1899 (long) get_frame_register_unsigned (frame
, 12),
1900 (long) get_frame_register_unsigned (frame
, 13),
1901 (long) get_frame_register_unsigned (frame
, 14),
1902 (long) get_frame_register_unsigned (frame
, 15));
1905 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1906 (long) get_frame_register_unsigned (frame
, A0G_REGNUM
) & 0xff,
1907 (long) get_frame_register_unsigned (frame
, A0_REGNUM
),
1908 (long) get_frame_register_unsigned (frame
, M0_REGNUM
),
1909 (long) get_frame_register_unsigned (frame
, X0_REGNUM
),
1910 (long) get_frame_register_unsigned (frame
, Y0_REGNUM
),
1911 (long) get_frame_register_unsigned (frame
, RS_REGNUM
),
1912 (long) get_frame_register_unsigned (frame
, MOD_REGNUM
));
1914 ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1915 (long) get_frame_register_unsigned (frame
, A1G_REGNUM
) & 0xff,
1916 (long) get_frame_register_unsigned (frame
, A1_REGNUM
),
1917 (long) get_frame_register_unsigned (frame
, M1_REGNUM
),
1918 (long) get_frame_register_unsigned (frame
, X1_REGNUM
),
1919 (long) get_frame_register_unsigned (frame
, Y1_REGNUM
),
1920 (long) get_frame_register_unsigned (frame
, RE_REGNUM
));
1924 sh4_show_regs (struct frame_info
*frame
)
1926 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1927 int pr
= get_frame_register_unsigned (frame
, FPSCR_REGNUM
) & 0x80000;
1930 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1931 phex (get_frame_register_unsigned (frame
,
1932 gdbarch_pc_regnum (gdbarch
)), 4),
1933 (long) get_frame_register_unsigned (frame
, SR_REGNUM
),
1934 (long) get_frame_register_unsigned (frame
, PR_REGNUM
),
1935 (long) get_frame_register_unsigned (frame
, MACH_REGNUM
));
1938 (" GBR %08lx VBR %08lx MACL %08lx\n",
1939 (long) get_frame_register_unsigned (frame
, GBR_REGNUM
),
1940 (long) get_frame_register_unsigned (frame
, VBR_REGNUM
),
1941 (long) get_frame_register_unsigned (frame
, MACL_REGNUM
));
1943 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1944 (long) get_frame_register_unsigned (frame
, SSR_REGNUM
),
1945 (long) get_frame_register_unsigned (frame
, SPC_REGNUM
),
1946 (long) get_frame_register_unsigned (frame
, FPUL_REGNUM
),
1947 (long) get_frame_register_unsigned (frame
, FPSCR_REGNUM
));
1950 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1951 (long) get_frame_register_unsigned (frame
, 0),
1952 (long) get_frame_register_unsigned (frame
, 1),
1953 (long) get_frame_register_unsigned (frame
, 2),
1954 (long) get_frame_register_unsigned (frame
, 3),
1955 (long) get_frame_register_unsigned (frame
, 4),
1956 (long) get_frame_register_unsigned (frame
, 5),
1957 (long) get_frame_register_unsigned (frame
, 6),
1958 (long) get_frame_register_unsigned (frame
, 7));
1960 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1961 (long) get_frame_register_unsigned (frame
, 8),
1962 (long) get_frame_register_unsigned (frame
, 9),
1963 (long) get_frame_register_unsigned (frame
, 10),
1964 (long) get_frame_register_unsigned (frame
, 11),
1965 (long) get_frame_register_unsigned (frame
, 12),
1966 (long) get_frame_register_unsigned (frame
, 13),
1967 (long) get_frame_register_unsigned (frame
, 14),
1968 (long) get_frame_register_unsigned (frame
, 15));
1971 (pr
? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1972 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1973 (long) get_frame_register_unsigned
1974 (frame
, gdbarch_fp0_regnum (gdbarch
) + 0),
1975 (long) get_frame_register_unsigned
1976 (frame
, gdbarch_fp0_regnum (gdbarch
) + 1),
1977 (long) get_frame_register_unsigned
1978 (frame
, gdbarch_fp0_regnum (gdbarch
) + 2),
1979 (long) get_frame_register_unsigned
1980 (frame
, gdbarch_fp0_regnum (gdbarch
) + 3),
1981 (long) get_frame_register_unsigned
1982 (frame
, gdbarch_fp0_regnum (gdbarch
) + 4),
1983 (long) get_frame_register_unsigned
1984 (frame
, gdbarch_fp0_regnum (gdbarch
) + 5),
1985 (long) get_frame_register_unsigned
1986 (frame
, gdbarch_fp0_regnum (gdbarch
) + 6),
1987 (long) get_frame_register_unsigned
1988 (frame
, gdbarch_fp0_regnum (gdbarch
) + 7));
1990 (pr
? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1991 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1992 (long) get_frame_register_unsigned
1993 (frame
, gdbarch_fp0_regnum (gdbarch
) + 8),
1994 (long) get_frame_register_unsigned
1995 (frame
, gdbarch_fp0_regnum (gdbarch
) + 9),
1996 (long) get_frame_register_unsigned
1997 (frame
, gdbarch_fp0_regnum (gdbarch
) + 10),
1998 (long) get_frame_register_unsigned
1999 (frame
, gdbarch_fp0_regnum (gdbarch
) + 11),
2000 (long) get_frame_register_unsigned
2001 (frame
, gdbarch_fp0_regnum (gdbarch
) + 12),
2002 (long) get_frame_register_unsigned
2003 (frame
, gdbarch_fp0_regnum (gdbarch
) + 13),
2004 (long) get_frame_register_unsigned
2005 (frame
, gdbarch_fp0_regnum (gdbarch
) + 14),
2006 (long) get_frame_register_unsigned
2007 (frame
, gdbarch_fp0_regnum (gdbarch
) + 15));
2011 sh4_nofpu_show_regs (struct frame_info
*frame
)
2014 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
2015 phex (get_frame_register_unsigned (frame
,
2017 (get_frame_arch (frame
))), 4),
2018 (long) get_frame_register_unsigned (frame
, SR_REGNUM
),
2019 (long) get_frame_register_unsigned (frame
, PR_REGNUM
),
2020 (long) get_frame_register_unsigned (frame
, MACH_REGNUM
));
2023 (" GBR %08lx VBR %08lx MACL %08lx\n",
2024 (long) get_frame_register_unsigned (frame
, GBR_REGNUM
),
2025 (long) get_frame_register_unsigned (frame
, VBR_REGNUM
),
2026 (long) get_frame_register_unsigned (frame
, MACL_REGNUM
));
2028 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
2029 (long) get_frame_register_unsigned (frame
, SSR_REGNUM
),
2030 (long) get_frame_register_unsigned (frame
, SPC_REGNUM
),
2031 (long) get_frame_register_unsigned (frame
, FPUL_REGNUM
),
2032 (long) get_frame_register_unsigned (frame
, FPSCR_REGNUM
));
2035 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2036 (long) get_frame_register_unsigned (frame
, 0),
2037 (long) get_frame_register_unsigned (frame
, 1),
2038 (long) get_frame_register_unsigned (frame
, 2),
2039 (long) get_frame_register_unsigned (frame
, 3),
2040 (long) get_frame_register_unsigned (frame
, 4),
2041 (long) get_frame_register_unsigned (frame
, 5),
2042 (long) get_frame_register_unsigned (frame
, 6),
2043 (long) get_frame_register_unsigned (frame
, 7));
2045 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2046 (long) get_frame_register_unsigned (frame
, 8),
2047 (long) get_frame_register_unsigned (frame
, 9),
2048 (long) get_frame_register_unsigned (frame
, 10),
2049 (long) get_frame_register_unsigned (frame
, 11),
2050 (long) get_frame_register_unsigned (frame
, 12),
2051 (long) get_frame_register_unsigned (frame
, 13),
2052 (long) get_frame_register_unsigned (frame
, 14),
2053 (long) get_frame_register_unsigned (frame
, 15));
2057 sh_dsp_show_regs (struct frame_info
*frame
)
2060 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
2061 phex (get_frame_register_unsigned (frame
,
2063 (get_frame_arch (frame
))), 4),
2064 (long) get_frame_register_unsigned (frame
, SR_REGNUM
),
2065 (long) get_frame_register_unsigned (frame
, PR_REGNUM
),
2066 (long) get_frame_register_unsigned (frame
, MACH_REGNUM
));
2069 (" GBR %08lx VBR %08lx DSR %08lx MACL %08lx\n",
2070 (long) get_frame_register_unsigned (frame
, GBR_REGNUM
),
2071 (long) get_frame_register_unsigned (frame
, VBR_REGNUM
),
2072 (long) get_frame_register_unsigned (frame
, DSR_REGNUM
),
2073 (long) get_frame_register_unsigned (frame
, MACL_REGNUM
));
2076 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2077 (long) get_frame_register_unsigned (frame
, 0),
2078 (long) get_frame_register_unsigned (frame
, 1),
2079 (long) get_frame_register_unsigned (frame
, 2),
2080 (long) get_frame_register_unsigned (frame
, 3),
2081 (long) get_frame_register_unsigned (frame
, 4),
2082 (long) get_frame_register_unsigned (frame
, 5),
2083 (long) get_frame_register_unsigned (frame
, 6),
2084 (long) get_frame_register_unsigned (frame
, 7));
2086 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2087 (long) get_frame_register_unsigned (frame
, 8),
2088 (long) get_frame_register_unsigned (frame
, 9),
2089 (long) get_frame_register_unsigned (frame
, 10),
2090 (long) get_frame_register_unsigned (frame
, 11),
2091 (long) get_frame_register_unsigned (frame
, 12),
2092 (long) get_frame_register_unsigned (frame
, 13),
2093 (long) get_frame_register_unsigned (frame
, 14),
2094 (long) get_frame_register_unsigned (frame
, 15));
2097 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
2098 (long) get_frame_register_unsigned (frame
, A0G_REGNUM
) & 0xff,
2099 (long) get_frame_register_unsigned (frame
, A0_REGNUM
),
2100 (long) get_frame_register_unsigned (frame
, M0_REGNUM
),
2101 (long) get_frame_register_unsigned (frame
, X0_REGNUM
),
2102 (long) get_frame_register_unsigned (frame
, Y0_REGNUM
),
2103 (long) get_frame_register_unsigned (frame
, RS_REGNUM
),
2104 (long) get_frame_register_unsigned (frame
, MOD_REGNUM
));
2105 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
2106 (long) get_frame_register_unsigned (frame
, A1G_REGNUM
) & 0xff,
2107 (long) get_frame_register_unsigned (frame
, A1_REGNUM
),
2108 (long) get_frame_register_unsigned (frame
, M1_REGNUM
),
2109 (long) get_frame_register_unsigned (frame
, X1_REGNUM
),
2110 (long) get_frame_register_unsigned (frame
, Y1_REGNUM
),
2111 (long) get_frame_register_unsigned (frame
, RE_REGNUM
));
2115 sh_show_regs_command (char *args
, int from_tty
)
2118 (*sh_show_regs
) (get_current_frame ());
2121 static struct type
*
2122 sh_sh2a_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
2124 if ((reg_nr
>= gdbarch_fp0_regnum (gdbarch
)
2125 && (reg_nr
<= FP_LAST_REGNUM
)) || (reg_nr
== FPUL_REGNUM
))
2126 return builtin_type (gdbarch
)->builtin_float
;
2127 else if (reg_nr
>= DR0_REGNUM
&& reg_nr
<= DR_LAST_REGNUM
)
2128 return builtin_type (gdbarch
)->builtin_double
;
2130 return builtin_type (gdbarch
)->builtin_int
;
2133 /* Return the GDB type object for the "standard" data type
2134 of data in register N. */
2135 static struct type
*
2136 sh_sh3e_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
2138 if ((reg_nr
>= gdbarch_fp0_regnum (gdbarch
)
2139 && (reg_nr
<= FP_LAST_REGNUM
)) || (reg_nr
== FPUL_REGNUM
))
2140 return builtin_type (gdbarch
)->builtin_float
;
2142 return builtin_type (gdbarch
)->builtin_int
;
2145 static struct type
*
2146 sh_sh4_build_float_register_type (struct gdbarch
*gdbarch
, int high
)
2148 return lookup_array_range_type (builtin_type (gdbarch
)->builtin_float
,
2152 static struct type
*
2153 sh_sh4_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
2155 if ((reg_nr
>= gdbarch_fp0_regnum (gdbarch
)
2156 && (reg_nr
<= FP_LAST_REGNUM
)) || (reg_nr
== FPUL_REGNUM
))
2157 return builtin_type (gdbarch
)->builtin_float
;
2158 else if (reg_nr
>= DR0_REGNUM
&& reg_nr
<= DR_LAST_REGNUM
)
2159 return builtin_type (gdbarch
)->builtin_double
;
2160 else if (reg_nr
>= FV0_REGNUM
&& reg_nr
<= FV_LAST_REGNUM
)
2161 return sh_sh4_build_float_register_type (gdbarch
, 3);
2163 return builtin_type (gdbarch
)->builtin_int
;
2166 static struct type
*
2167 sh_default_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
2169 return builtin_type (gdbarch
)->builtin_int
;
2172 /* Is a register in a reggroup?
2173 The default code in reggroup.c doesn't identify system registers, some
2174 float registers or any of the vector registers.
2175 TODO: sh2a and dsp registers. */
2177 sh_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2178 struct reggroup
*reggroup
)
2180 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
2181 || *gdbarch_register_name (gdbarch
, regnum
) == '\0')
2184 if (reggroup
== float_reggroup
2185 && (regnum
== FPUL_REGNUM
2186 || regnum
== FPSCR_REGNUM
))
2189 if (regnum
>= FV0_REGNUM
&& regnum
<= FV_LAST_REGNUM
)
2191 if (reggroup
== vector_reggroup
|| reggroup
== float_reggroup
)
2193 if (reggroup
== general_reggroup
)
2197 if (regnum
== VBR_REGNUM
2198 || regnum
== SR_REGNUM
2199 || regnum
== FPSCR_REGNUM
2200 || regnum
== SSR_REGNUM
2201 || regnum
== SPC_REGNUM
)
2203 if (reggroup
== system_reggroup
)
2205 if (reggroup
== general_reggroup
)
2209 /* The default code can cope with any other registers. */
2210 return default_register_reggroup_p (gdbarch
, regnum
, reggroup
);
2213 /* On the sh4, the DRi pseudo registers are problematic if the target
2214 is little endian. When the user writes one of those registers, for
2215 instance with 'ser var $dr0=1', we want the double to be stored
2217 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
2218 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2220 This corresponds to little endian byte order & big endian word
2221 order. However if we let gdb write the register w/o conversion, it
2222 will write fr0 and fr1 this way:
2223 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2224 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
2225 because it will consider fr0 and fr1 as a single LE stretch of memory.
2227 To achieve what we want we must force gdb to store things in
2228 floatformat_ieee_double_littlebyte_bigword (which is defined in
2229 include/floatformat.h and libiberty/floatformat.c.
2231 In case the target is big endian, there is no problem, the
2232 raw bytes will look like:
2233 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
2234 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2236 The other pseudo registers (the FVs) also don't pose a problem
2237 because they are stored as 4 individual FP elements. */
2240 sh_register_convert_to_virtual (int regnum
, struct type
*type
,
2241 char *from
, char *to
)
2243 if (regnum
>= DR0_REGNUM
&& regnum
<= DR_LAST_REGNUM
)
2246 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword
,
2248 store_typed_floating (to
, type
, val
);
2252 ("sh_register_convert_to_virtual called with non DR register number");
2256 sh_register_convert_to_raw (struct type
*type
, int regnum
,
2257 const void *from
, void *to
)
2259 if (regnum
>= DR0_REGNUM
&& regnum
<= DR_LAST_REGNUM
)
2261 DOUBLEST val
= extract_typed_floating (from
, type
);
2262 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword
,
2266 error (_("sh_register_convert_to_raw called with non DR register number"));
2269 /* For vectors of 4 floating point registers. */
2271 fv_reg_base_num (struct gdbarch
*gdbarch
, int fv_regnum
)
2275 fp_regnum
= gdbarch_fp0_regnum (gdbarch
)
2276 + (fv_regnum
- FV0_REGNUM
) * 4;
2280 /* For double precision floating point registers, i.e 2 fp regs. */
2282 dr_reg_base_num (struct gdbarch
*gdbarch
, int dr_regnum
)
2286 fp_regnum
= gdbarch_fp0_regnum (gdbarch
)
2287 + (dr_regnum
- DR0_REGNUM
) * 2;
2291 /* Concatenate PORTIONS contiguous raw registers starting at
2292 BASE_REGNUM into BUFFER. */
2294 static enum register_status
2295 pseudo_register_read_portions (struct gdbarch
*gdbarch
,
2296 struct regcache
*regcache
,
2298 int base_regnum
, gdb_byte
*buffer
)
2302 for (portion
= 0; portion
< portions
; portion
++)
2304 enum register_status status
;
2307 b
= buffer
+ register_size (gdbarch
, base_regnum
) * portion
;
2308 status
= regcache_raw_read (regcache
, base_regnum
+ portion
, b
);
2309 if (status
!= REG_VALID
)
2316 static enum register_status
2317 sh_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2318 int reg_nr
, gdb_byte
*buffer
)
2321 char temp_buffer
[MAX_REGISTER_SIZE
];
2322 enum register_status status
;
2324 if (reg_nr
== PSEUDO_BANK_REGNUM
)
2325 return regcache_raw_read (regcache
, BANK_REGNUM
, buffer
);
2326 else if (reg_nr
>= DR0_REGNUM
&& reg_nr
<= DR_LAST_REGNUM
)
2328 base_regnum
= dr_reg_base_num (gdbarch
, reg_nr
);
2330 /* Build the value in the provided buffer. */
2331 /* Read the real regs for which this one is an alias. */
2332 status
= pseudo_register_read_portions (gdbarch
, regcache
,
2333 2, base_regnum
, temp_buffer
);
2334 if (status
== REG_VALID
)
2336 /* We must pay attention to the endiannes. */
2337 sh_register_convert_to_virtual (reg_nr
,
2338 register_type (gdbarch
, reg_nr
),
2339 temp_buffer
, buffer
);
2343 else if (reg_nr
>= FV0_REGNUM
&& reg_nr
<= FV_LAST_REGNUM
)
2345 base_regnum
= fv_reg_base_num (gdbarch
, reg_nr
);
2347 /* Read the real regs for which this one is an alias. */
2348 return pseudo_register_read_portions (gdbarch
, regcache
,
2349 4, base_regnum
, buffer
);
2352 gdb_assert_not_reached ("invalid pseudo register number");
2356 sh_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2357 int reg_nr
, const gdb_byte
*buffer
)
2359 int base_regnum
, portion
;
2360 char temp_buffer
[MAX_REGISTER_SIZE
];
2362 if (reg_nr
== PSEUDO_BANK_REGNUM
)
2364 /* When the bank register is written to, the whole register bank
2365 is switched and all values in the bank registers must be read
2366 from the target/sim again. We're just invalidating the regcache
2367 so that a re-read happens next time it's necessary. */
2370 regcache_raw_write (regcache
, BANK_REGNUM
, buffer
);
2371 for (bregnum
= R0_BANK0_REGNUM
; bregnum
< MACLB_REGNUM
; ++bregnum
)
2372 regcache_invalidate (regcache
, bregnum
);
2374 else if (reg_nr
>= DR0_REGNUM
&& reg_nr
<= DR_LAST_REGNUM
)
2376 base_regnum
= dr_reg_base_num (gdbarch
, reg_nr
);
2378 /* We must pay attention to the endiannes. */
2379 sh_register_convert_to_raw (register_type (gdbarch
, reg_nr
),
2380 reg_nr
, buffer
, temp_buffer
);
2382 /* Write the real regs for which this one is an alias. */
2383 for (portion
= 0; portion
< 2; portion
++)
2384 regcache_raw_write (regcache
, base_regnum
+ portion
,
2386 + register_size (gdbarch
,
2387 base_regnum
) * portion
));
2389 else if (reg_nr
>= FV0_REGNUM
&& reg_nr
<= FV_LAST_REGNUM
)
2391 base_regnum
= fv_reg_base_num (gdbarch
, reg_nr
);
2393 /* Write the real regs for which this one is an alias. */
2394 for (portion
= 0; portion
< 4; portion
++)
2395 regcache_raw_write (regcache
, base_regnum
+ portion
,
2397 + register_size (gdbarch
,
2398 base_regnum
) * portion
));
2403 sh_dsp_register_sim_regno (struct gdbarch
*gdbarch
, int nr
)
2405 if (legacy_register_sim_regno (gdbarch
, nr
) < 0)
2406 return legacy_register_sim_regno (gdbarch
, nr
);
2407 if (nr
>= DSR_REGNUM
&& nr
<= Y1_REGNUM
)
2408 return nr
- DSR_REGNUM
+ SIM_SH_DSR_REGNUM
;
2409 if (nr
== MOD_REGNUM
)
2410 return SIM_SH_MOD_REGNUM
;
2411 if (nr
== RS_REGNUM
)
2412 return SIM_SH_RS_REGNUM
;
2413 if (nr
== RE_REGNUM
)
2414 return SIM_SH_RE_REGNUM
;
2415 if (nr
>= DSP_R0_BANK_REGNUM
&& nr
<= DSP_R7_BANK_REGNUM
)
2416 return nr
- DSP_R0_BANK_REGNUM
+ SIM_SH_R0_BANK_REGNUM
;
2421 sh_sh2a_register_sim_regno (struct gdbarch
*gdbarch
, int nr
)
2426 return SIM_SH_TBR_REGNUM
;
2428 return SIM_SH_IBNR_REGNUM
;
2430 return SIM_SH_IBCR_REGNUM
;
2432 return SIM_SH_BANK_REGNUM
;
2434 return SIM_SH_BANK_MACL_REGNUM
;
2436 return SIM_SH_BANK_GBR_REGNUM
;
2438 return SIM_SH_BANK_PR_REGNUM
;
2440 return SIM_SH_BANK_IVN_REGNUM
;
2442 return SIM_SH_BANK_MACH_REGNUM
;
2446 return legacy_register_sim_regno (gdbarch
, nr
);
2449 /* Set up the register unwinding such that call-clobbered registers are
2450 not displayed in frames >0 because the true value is not certain.
2451 The 'undefined' registers will show up as 'not available' unless the
2454 This function is currently set up for SH4 and compatible only. */
2457 sh_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
2458 struct dwarf2_frame_state_reg
*reg
,
2459 struct frame_info
*this_frame
)
2461 /* Mark the PC as the destination for the return address. */
2462 if (regnum
== gdbarch_pc_regnum (gdbarch
))
2463 reg
->how
= DWARF2_FRAME_REG_RA
;
2465 /* Mark the stack pointer as the call frame address. */
2466 else if (regnum
== gdbarch_sp_regnum (gdbarch
))
2467 reg
->how
= DWARF2_FRAME_REG_CFA
;
2469 /* The above was taken from the default init_reg in dwarf2-frame.c
2470 while the below is SH specific. */
2472 /* Caller save registers. */
2473 else if ((regnum
>= R0_REGNUM
&& regnum
<= R0_REGNUM
+7)
2474 || (regnum
>= FR0_REGNUM
&& regnum
<= FR0_REGNUM
+11)
2475 || (regnum
>= DR0_REGNUM
&& regnum
<= DR0_REGNUM
+5)
2476 || (regnum
>= FV0_REGNUM
&& regnum
<= FV0_REGNUM
+2)
2477 || (regnum
== MACH_REGNUM
)
2478 || (regnum
== MACL_REGNUM
)
2479 || (regnum
== FPUL_REGNUM
)
2480 || (regnum
== SR_REGNUM
))
2481 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
2483 /* Callee save registers. */
2484 else if ((regnum
>= R0_REGNUM
+8 && regnum
<= R0_REGNUM
+15)
2485 || (regnum
>= FR0_REGNUM
+12 && regnum
<= FR0_REGNUM
+15)
2486 || (regnum
>= DR0_REGNUM
+6 && regnum
<= DR0_REGNUM
+8)
2487 || (regnum
== FV0_REGNUM
+3))
2488 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
2490 /* Other registers. These are not in the ABI and may or may not
2491 mean anything in frames >0 so don't show them. */
2492 else if ((regnum
>= R0_BANK0_REGNUM
&& regnum
<= R0_BANK0_REGNUM
+15)
2493 || (regnum
== GBR_REGNUM
)
2494 || (regnum
== VBR_REGNUM
)
2495 || (regnum
== FPSCR_REGNUM
)
2496 || (regnum
== SSR_REGNUM
)
2497 || (regnum
== SPC_REGNUM
))
2498 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
2501 static struct sh_frame_cache
*
2502 sh_alloc_frame_cache (void)
2504 struct sh_frame_cache
*cache
;
2507 cache
= FRAME_OBSTACK_ZALLOC (struct sh_frame_cache
);
2511 cache
->saved_sp
= 0;
2512 cache
->sp_offset
= 0;
2515 /* Frameless until proven otherwise. */
2518 /* Saved registers. We initialize these to -1 since zero is a valid
2519 offset (that's where fp is supposed to be stored). */
2520 for (i
= 0; i
< SH_NUM_REGS
; i
++)
2522 cache
->saved_regs
[i
] = -1;
2528 static struct sh_frame_cache
*
2529 sh_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2531 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2532 struct sh_frame_cache
*cache
;
2533 CORE_ADDR current_pc
;
2539 cache
= sh_alloc_frame_cache ();
2540 *this_cache
= cache
;
2542 /* In principle, for normal frames, fp holds the frame pointer,
2543 which holds the base address for the current stack frame.
2544 However, for functions that don't need it, the frame pointer is
2545 optional. For these "frameless" functions the frame pointer is
2546 actually the frame pointer of the calling frame. */
2547 cache
->base
= get_frame_register_unsigned (this_frame
, FP_REGNUM
);
2548 if (cache
->base
== 0)
2551 cache
->pc
= get_frame_func (this_frame
);
2552 current_pc
= get_frame_pc (this_frame
);
2556 fpscr
= get_frame_register_unsigned (this_frame
, FPSCR_REGNUM
);
2557 sh_analyze_prologue (gdbarch
, cache
->pc
, current_pc
, cache
, fpscr
);
2560 if (!cache
->uses_fp
)
2562 /* We didn't find a valid frame, which means that CACHE->base
2563 currently holds the frame pointer for our calling frame. If
2564 we're at the start of a function, or somewhere half-way its
2565 prologue, the function's frame probably hasn't been fully
2566 setup yet. Try to reconstruct the base address for the stack
2567 frame by looking at the stack pointer. For truly "frameless"
2568 functions this might work too. */
2569 cache
->base
= get_frame_register_unsigned
2570 (this_frame
, gdbarch_sp_regnum (gdbarch
));
2573 /* Now that we have the base address for the stack frame we can
2574 calculate the value of sp in the calling frame. */
2575 cache
->saved_sp
= cache
->base
+ cache
->sp_offset
;
2577 /* Adjust all the saved registers such that they contain addresses
2578 instead of offsets. */
2579 for (i
= 0; i
< SH_NUM_REGS
; i
++)
2580 if (cache
->saved_regs
[i
] != -1)
2581 cache
->saved_regs
[i
] = cache
->saved_sp
- cache
->saved_regs
[i
] - 4;
2586 static struct value
*
2587 sh_frame_prev_register (struct frame_info
*this_frame
,
2588 void **this_cache
, int regnum
)
2590 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2591 struct sh_frame_cache
*cache
= sh_frame_cache (this_frame
, this_cache
);
2593 gdb_assert (regnum
>= 0);
2595 if (regnum
== gdbarch_sp_regnum (gdbarch
) && cache
->saved_sp
)
2596 return frame_unwind_got_constant (this_frame
, regnum
, cache
->saved_sp
);
2598 /* The PC of the previous frame is stored in the PR register of
2599 the current frame. Frob regnum so that we pull the value from
2600 the correct place. */
2601 if (regnum
== gdbarch_pc_regnum (gdbarch
))
2604 if (regnum
< SH_NUM_REGS
&& cache
->saved_regs
[regnum
] != -1)
2605 return frame_unwind_got_memory (this_frame
, regnum
,
2606 cache
->saved_regs
[regnum
]);
2608 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
2612 sh_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2613 struct frame_id
*this_id
)
2615 struct sh_frame_cache
*cache
= sh_frame_cache (this_frame
, this_cache
);
2617 /* This marks the outermost frame. */
2618 if (cache
->base
== 0)
2621 *this_id
= frame_id_build (cache
->saved_sp
, cache
->pc
);
2624 static const struct frame_unwind sh_frame_unwind
= {
2626 default_frame_unwind_stop_reason
,
2628 sh_frame_prev_register
,
2630 default_frame_sniffer
2634 sh_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2636 return frame_unwind_register_unsigned (next_frame
,
2637 gdbarch_sp_regnum (gdbarch
));
2641 sh_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2643 return frame_unwind_register_unsigned (next_frame
,
2644 gdbarch_pc_regnum (gdbarch
));
2647 static struct frame_id
2648 sh_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2650 CORE_ADDR sp
= get_frame_register_unsigned (this_frame
,
2651 gdbarch_sp_regnum (gdbarch
));
2652 return frame_id_build (sp
, get_frame_pc (this_frame
));
2656 sh_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2658 struct sh_frame_cache
*cache
= sh_frame_cache (this_frame
, this_cache
);
2663 static const struct frame_base sh_frame_base
= {
2665 sh_frame_base_address
,
2666 sh_frame_base_address
,
2667 sh_frame_base_address
2670 static struct sh_frame_cache
*
2671 sh_make_stub_cache (struct frame_info
*this_frame
)
2673 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2674 struct sh_frame_cache
*cache
;
2676 cache
= sh_alloc_frame_cache ();
2679 = get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
2685 sh_stub_this_id (struct frame_info
*this_frame
, void **this_cache
,
2686 struct frame_id
*this_id
)
2688 struct sh_frame_cache
*cache
;
2690 if (*this_cache
== NULL
)
2691 *this_cache
= sh_make_stub_cache (this_frame
);
2692 cache
= *this_cache
;
2694 *this_id
= frame_id_build (cache
->saved_sp
, get_frame_pc (this_frame
));
2698 sh_stub_unwind_sniffer (const struct frame_unwind
*self
,
2699 struct frame_info
*this_frame
,
2700 void **this_prologue_cache
)
2702 CORE_ADDR addr_in_block
;
2704 addr_in_block
= get_frame_address_in_block (this_frame
);
2705 if (in_plt_section (addr_in_block
, NULL
))
2711 static const struct frame_unwind sh_stub_unwind
=
2714 default_frame_unwind_stop_reason
,
2716 sh_frame_prev_register
,
2718 sh_stub_unwind_sniffer
2721 /* The epilogue is defined here as the area at the end of a function,
2722 either on the `ret' instruction itself or after an instruction which
2723 destroys the function's stack frame. */
2725 sh_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2727 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2728 CORE_ADDR func_addr
= 0, func_end
= 0;
2730 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
2733 /* The sh epilogue is max. 14 bytes long. Give another 14 bytes
2734 for a nop and some fixed data (e.g. big offsets) which are
2735 unfortunately also treated as part of the function (which
2736 means, they are below func_end. */
2737 CORE_ADDR addr
= func_end
- 28;
2738 if (addr
< func_addr
+ 4)
2739 addr
= func_addr
+ 4;
2743 /* First search forward until hitting an rts. */
2744 while (addr
< func_end
2745 && !IS_RTS (read_memory_unsigned_integer (addr
, 2, byte_order
)))
2747 if (addr
>= func_end
)
2750 /* At this point we should find a mov.l @r15+,r14 instruction,
2751 either before or after the rts. If not, then the function has
2752 probably no "normal" epilogue and we bail out here. */
2753 inst
= read_memory_unsigned_integer (addr
- 2, 2, byte_order
);
2754 if (IS_RESTORE_FP (read_memory_unsigned_integer (addr
- 2, 2,
2757 else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr
+ 2, 2,
2761 inst
= read_memory_unsigned_integer (addr
- 2, 2, byte_order
);
2763 /* Step over possible lds.l @r15+,macl. */
2764 if (IS_MACL_LDS (inst
))
2767 inst
= read_memory_unsigned_integer (addr
- 2, 2, byte_order
);
2770 /* Step over possible lds.l @r15+,pr. */
2774 inst
= read_memory_unsigned_integer (addr
- 2, 2, byte_order
);
2777 /* Step over possible mov r14,r15. */
2778 if (IS_MOV_FP_SP (inst
))
2781 inst
= read_memory_unsigned_integer (addr
- 2, 2, byte_order
);
2784 /* Now check for FP adjustments, using add #imm,r14 or add rX, r14
2786 while (addr
> func_addr
+ 4
2787 && (IS_ADD_REG_TO_FP (inst
) || IS_ADD_IMM_FP (inst
)))
2790 inst
= read_memory_unsigned_integer (addr
- 2, 2, byte_order
);
2793 /* On SH2a check if the previous instruction was perhaps a MOVI20.
2794 That's allowed for the epilogue. */
2795 if ((gdbarch_bfd_arch_info (gdbarch
)->mach
== bfd_mach_sh2a
2796 || gdbarch_bfd_arch_info (gdbarch
)->mach
== bfd_mach_sh2a_nofpu
)
2797 && addr
> func_addr
+ 6
2798 && IS_MOVI20 (read_memory_unsigned_integer (addr
- 4, 2,
2809 /* Supply register REGNUM from the buffer specified by REGS and LEN
2810 in the register set REGSET to register cache REGCACHE.
2811 REGTABLE specifies where each register can be found in REGS.
2812 If REGNUM is -1, do this for all registers in REGSET. */
2815 sh_corefile_supply_regset (const struct regset
*regset
,
2816 struct regcache
*regcache
,
2817 int regnum
, const void *regs
, size_t len
)
2819 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
2820 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2821 const struct sh_corefile_regmap
*regmap
= (regset
== &sh_corefile_gregset
2822 ? tdep
->core_gregmap
2823 : tdep
->core_fpregmap
);
2826 for (i
= 0; regmap
[i
].regnum
!= -1; i
++)
2828 if ((regnum
== -1 || regnum
== regmap
[i
].regnum
)
2829 && regmap
[i
].offset
+ 4 <= len
)
2830 regcache_raw_supply (regcache
, regmap
[i
].regnum
,
2831 (char *)regs
+ regmap
[i
].offset
);
2835 /* Collect register REGNUM in the register set REGSET from register cache
2836 REGCACHE into the buffer specified by REGS and LEN.
2837 REGTABLE specifies where each register can be found in REGS.
2838 If REGNUM is -1, do this for all registers in REGSET. */
2841 sh_corefile_collect_regset (const struct regset
*regset
,
2842 const struct regcache
*regcache
,
2843 int regnum
, void *regs
, size_t len
)
2845 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
2846 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2847 const struct sh_corefile_regmap
*regmap
= (regset
== &sh_corefile_gregset
2848 ? tdep
->core_gregmap
2849 : tdep
->core_fpregmap
);
2852 for (i
= 0; regmap
[i
].regnum
!= -1; i
++)
2854 if ((regnum
== -1 || regnum
== regmap
[i
].regnum
)
2855 && regmap
[i
].offset
+ 4 <= len
)
2856 regcache_raw_collect (regcache
, regmap
[i
].regnum
,
2857 (char *)regs
+ regmap
[i
].offset
);
2861 /* The following two regsets have the same contents, so it is tempting to
2862 unify them, but they are distiguished by their address, so don't. */
2864 struct regset sh_corefile_gregset
=
2867 sh_corefile_supply_regset
,
2868 sh_corefile_collect_regset
2871 static struct regset sh_corefile_fpregset
=
2874 sh_corefile_supply_regset
,
2875 sh_corefile_collect_regset
2878 static const struct regset
*
2879 sh_regset_from_core_section (struct gdbarch
*gdbarch
, const char *sect_name
,
2882 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2884 if (tdep
->core_gregmap
&& strcmp (sect_name
, ".reg") == 0)
2885 return &sh_corefile_gregset
;
2887 if (tdep
->core_fpregmap
&& strcmp (sect_name
, ".reg2") == 0)
2888 return &sh_corefile_fpregset
;
2894 static struct gdbarch
*
2895 sh_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2897 struct gdbarch
*gdbarch
;
2898 struct gdbarch_tdep
*tdep
;
2900 sh_show_regs
= sh_generic_show_regs
;
2901 switch (info
.bfd_arch_info
->mach
)
2904 sh_show_regs
= sh2e_show_regs
;
2907 sh_show_regs
= sh2a_show_regs
;
2909 case bfd_mach_sh2a_nofpu
:
2910 sh_show_regs
= sh2a_nofpu_show_regs
;
2912 case bfd_mach_sh_dsp
:
2913 sh_show_regs
= sh_dsp_show_regs
;
2917 case bfd_mach_sh3_nommu
:
2918 case bfd_mach_sh2a_nofpu_or_sh3_nommu
:
2919 sh_show_regs
= sh3_show_regs
;
2923 case bfd_mach_sh2a_or_sh3e
:
2924 sh_show_regs
= sh3e_show_regs
;
2927 case bfd_mach_sh3_dsp
:
2928 case bfd_mach_sh4al_dsp
:
2929 sh_show_regs
= sh3_dsp_show_regs
;
2934 case bfd_mach_sh2a_or_sh4
:
2935 sh_show_regs
= sh4_show_regs
;
2938 case bfd_mach_sh4_nofpu
:
2939 case bfd_mach_sh4_nommu_nofpu
:
2940 case bfd_mach_sh4a_nofpu
:
2941 case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu
:
2942 sh_show_regs
= sh4_nofpu_show_regs
;
2946 sh_show_regs
= sh64_show_regs
;
2947 /* SH5 is handled entirely in sh64-tdep.c. */
2948 return sh64_gdbarch_init (info
, arches
);
2951 /* If there is already a candidate, use it. */
2952 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2954 return arches
->gdbarch
;
2956 /* None found, create a new architecture from the information
2958 tdep
= XZALLOC (struct gdbarch_tdep
);
2959 gdbarch
= gdbarch_alloc (&info
, tdep
);
2961 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
2962 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2963 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2964 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2965 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2966 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2967 set_gdbarch_long_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2968 set_gdbarch_ptr_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2970 set_gdbarch_num_regs (gdbarch
, SH_NUM_REGS
);
2971 set_gdbarch_sp_regnum (gdbarch
, 15);
2972 set_gdbarch_pc_regnum (gdbarch
, 16);
2973 set_gdbarch_fp0_regnum (gdbarch
, -1);
2974 set_gdbarch_num_pseudo_regs (gdbarch
, 0);
2976 set_gdbarch_register_type (gdbarch
, sh_default_register_type
);
2977 set_gdbarch_register_reggroup_p (gdbarch
, sh_register_reggroup_p
);
2979 set_gdbarch_breakpoint_from_pc (gdbarch
, sh_breakpoint_from_pc
);
2981 set_gdbarch_print_insn (gdbarch
, print_insn_sh
);
2982 set_gdbarch_register_sim_regno (gdbarch
, legacy_register_sim_regno
);
2984 set_gdbarch_return_value (gdbarch
, sh_return_value_nofpu
);
2986 set_gdbarch_skip_prologue (gdbarch
, sh_skip_prologue
);
2987 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2989 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_nofpu
);
2991 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
2993 set_gdbarch_frame_align (gdbarch
, sh_frame_align
);
2994 set_gdbarch_unwind_sp (gdbarch
, sh_unwind_sp
);
2995 set_gdbarch_unwind_pc (gdbarch
, sh_unwind_pc
);
2996 set_gdbarch_dummy_id (gdbarch
, sh_dummy_id
);
2997 frame_base_set_default (gdbarch
, &sh_frame_base
);
2999 set_gdbarch_in_function_epilogue_p (gdbarch
, sh_in_function_epilogue_p
);
3001 dwarf2_frame_set_init_reg (gdbarch
, sh_dwarf2_frame_init_reg
);
3003 set_gdbarch_regset_from_core_section (gdbarch
, sh_regset_from_core_section
);
3005 switch (info
.bfd_arch_info
->mach
)
3008 set_gdbarch_register_name (gdbarch
, sh_sh_register_name
);
3012 set_gdbarch_register_name (gdbarch
, sh_sh_register_name
);
3016 /* doubles on sh2e and sh3e are actually 4 byte. */
3017 set_gdbarch_double_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
3019 set_gdbarch_register_name (gdbarch
, sh_sh2e_register_name
);
3020 set_gdbarch_register_type (gdbarch
, sh_sh3e_register_type
);
3021 set_gdbarch_fp0_regnum (gdbarch
, 25);
3022 set_gdbarch_return_value (gdbarch
, sh_return_value_fpu
);
3023 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_fpu
);
3027 set_gdbarch_register_name (gdbarch
, sh_sh2a_register_name
);
3028 set_gdbarch_register_type (gdbarch
, sh_sh2a_register_type
);
3029 set_gdbarch_register_sim_regno (gdbarch
, sh_sh2a_register_sim_regno
);
3031 set_gdbarch_fp0_regnum (gdbarch
, 25);
3032 set_gdbarch_num_pseudo_regs (gdbarch
, 9);
3033 set_gdbarch_pseudo_register_read (gdbarch
, sh_pseudo_register_read
);
3034 set_gdbarch_pseudo_register_write (gdbarch
, sh_pseudo_register_write
);
3035 set_gdbarch_return_value (gdbarch
, sh_return_value_fpu
);
3036 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_fpu
);
3039 case bfd_mach_sh2a_nofpu
:
3040 set_gdbarch_register_name (gdbarch
, sh_sh2a_nofpu_register_name
);
3041 set_gdbarch_register_sim_regno (gdbarch
, sh_sh2a_register_sim_regno
);
3043 set_gdbarch_num_pseudo_regs (gdbarch
, 1);
3044 set_gdbarch_pseudo_register_read (gdbarch
, sh_pseudo_register_read
);
3045 set_gdbarch_pseudo_register_write (gdbarch
, sh_pseudo_register_write
);
3048 case bfd_mach_sh_dsp
:
3049 set_gdbarch_register_name (gdbarch
, sh_sh_dsp_register_name
);
3050 set_gdbarch_register_sim_regno (gdbarch
, sh_dsp_register_sim_regno
);
3054 case bfd_mach_sh3_nommu
:
3055 case bfd_mach_sh2a_nofpu_or_sh3_nommu
:
3056 set_gdbarch_register_name (gdbarch
, sh_sh3_register_name
);
3060 case bfd_mach_sh2a_or_sh3e
:
3061 /* doubles on sh2e and sh3e are actually 4 byte. */
3062 set_gdbarch_double_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
3064 set_gdbarch_register_name (gdbarch
, sh_sh3e_register_name
);
3065 set_gdbarch_register_type (gdbarch
, sh_sh3e_register_type
);
3066 set_gdbarch_fp0_regnum (gdbarch
, 25);
3067 set_gdbarch_return_value (gdbarch
, sh_return_value_fpu
);
3068 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_fpu
);
3071 case bfd_mach_sh3_dsp
:
3072 set_gdbarch_register_name (gdbarch
, sh_sh3_dsp_register_name
);
3073 set_gdbarch_register_sim_regno (gdbarch
, sh_dsp_register_sim_regno
);
3078 case bfd_mach_sh2a_or_sh4
:
3079 set_gdbarch_register_name (gdbarch
, sh_sh4_register_name
);
3080 set_gdbarch_register_type (gdbarch
, sh_sh4_register_type
);
3081 set_gdbarch_fp0_regnum (gdbarch
, 25);
3082 set_gdbarch_num_pseudo_regs (gdbarch
, 13);
3083 set_gdbarch_pseudo_register_read (gdbarch
, sh_pseudo_register_read
);
3084 set_gdbarch_pseudo_register_write (gdbarch
, sh_pseudo_register_write
);
3085 set_gdbarch_return_value (gdbarch
, sh_return_value_fpu
);
3086 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_fpu
);
3089 case bfd_mach_sh4_nofpu
:
3090 case bfd_mach_sh4a_nofpu
:
3091 case bfd_mach_sh4_nommu_nofpu
:
3092 case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu
:
3093 set_gdbarch_register_name (gdbarch
, sh_sh4_nofpu_register_name
);
3096 case bfd_mach_sh4al_dsp
:
3097 set_gdbarch_register_name (gdbarch
, sh_sh4al_dsp_register_name
);
3098 set_gdbarch_register_sim_regno (gdbarch
, sh_dsp_register_sim_regno
);
3102 set_gdbarch_register_name (gdbarch
, sh_sh_register_name
);
3106 /* Hook in ABI-specific overrides, if they have been registered. */
3107 gdbarch_init_osabi (info
, gdbarch
);
3109 dwarf2_append_unwinders (gdbarch
);
3110 frame_unwind_append_unwinder (gdbarch
, &sh_stub_unwind
);
3111 frame_unwind_append_unwinder (gdbarch
, &sh_frame_unwind
);
3117 show_sh_command (char *args
, int from_tty
)
3119 help_list (showshcmdlist
, "show sh ", all_commands
, gdb_stdout
);
3123 set_sh_command (char *args
, int from_tty
)
3126 ("\"set sh\" must be followed by an appropriate subcommand.\n");
3127 help_list (setshcmdlist
, "set sh ", all_commands
, gdb_stdout
);
3130 extern initialize_file_ftype _initialize_sh_tdep
; /* -Wmissing-prototypes */
3133 _initialize_sh_tdep (void)
3135 struct cmd_list_element
*c
;
3137 gdbarch_register (bfd_arch_sh
, sh_gdbarch_init
, NULL
);
3139 add_com ("regs", class_vars
, sh_show_regs_command
, _("Print all registers"));
3141 add_prefix_cmd ("sh", no_class
, set_sh_command
, "SH specific commands.",
3142 &setshcmdlist
, "set sh ", 0, &setlist
);
3143 add_prefix_cmd ("sh", no_class
, show_sh_command
, "SH specific commands.",
3144 &showshcmdlist
, "show sh ", 0, &showlist
);
3146 add_setshow_enum_cmd ("calling-convention", class_vars
, sh_cc_enum
,
3147 &sh_active_calling_convention
,
3148 _("Set calling convention used when calling target "
3149 "functions from GDB."),
3150 _("Show calling convention used when calling target "
3151 "functions from GDB."),
3152 _("gcc - Use GCC calling convention (default).\n"
3153 "renesas - Enforce Renesas calling convention."),
3155 &setshcmdlist
, &showshcmdlist
);