1 /* Target-dependent code for Renesas Super-H, for GDB.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 Contributed by Steve Chamberlain
29 #include "frame-base.h"
30 #include "frame-unwind.h"
31 #include "dwarf2-frame.h"
40 #include "gdb_string.h"
41 #include "gdb_assert.h"
42 #include "arch-utils.h"
43 #include "floatformat.h"
51 #include "solib-svr4.h"
55 /* registers numbers shared with the simulator */
56 #include "gdb/sim-sh.h"
58 static void (*sh_show_regs
) (void);
60 #define SH_NUM_REGS 59
69 /* Flag showing that a frame has been created in the prologue code. */
72 /* Saved registers. */
73 CORE_ADDR saved_regs
[SH_NUM_REGS
];
78 sh_generic_register_name (int reg_nr
)
80 static char *register_names
[] = {
81 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
82 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
83 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
85 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
86 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
88 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
89 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
93 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
95 return register_names
[reg_nr
];
99 sh_sh_register_name (int reg_nr
)
101 static char *register_names
[] = {
102 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
103 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
104 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
106 "", "", "", "", "", "", "", "",
107 "", "", "", "", "", "", "", "",
109 "", "", "", "", "", "", "", "",
110 "", "", "", "", "", "", "", "",
114 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
116 return register_names
[reg_nr
];
120 sh_sh3_register_name (int reg_nr
)
122 static char *register_names
[] = {
123 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
124 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
125 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
127 "", "", "", "", "", "", "", "",
128 "", "", "", "", "", "", "", "",
130 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
131 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
135 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
137 return register_names
[reg_nr
];
141 sh_sh3e_register_name (int reg_nr
)
143 static char *register_names
[] = {
144 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
145 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
146 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
148 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
149 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
151 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
152 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
156 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
158 return register_names
[reg_nr
];
162 sh_sh2e_register_name (int reg_nr
)
164 static char *register_names
[] = {
165 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
166 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
167 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
169 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
170 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
172 "", "", "", "", "", "", "", "",
173 "", "", "", "", "", "", "", "",
177 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
179 return register_names
[reg_nr
];
183 sh_sh_dsp_register_name (int reg_nr
)
185 static char *register_names
[] = {
186 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
187 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
188 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
190 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
191 "y0", "y1", "", "", "", "", "", "mod",
193 "rs", "re", "", "", "", "", "", "",
194 "", "", "", "", "", "", "", "",
198 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
200 return register_names
[reg_nr
];
204 sh_sh3_dsp_register_name (int reg_nr
)
206 static char *register_names
[] = {
207 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
208 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
209 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
211 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
212 "y0", "y1", "", "", "", "", "", "mod",
214 "rs", "re", "", "", "", "", "", "",
215 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b"
216 "", "", "", "", "", "", "", "",
220 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
222 return register_names
[reg_nr
];
226 sh_sh4_register_name (int reg_nr
)
228 static char *register_names
[] = {
229 /* general registers 0-15 */
230 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
231 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
233 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
236 /* floating point registers 25 - 40 */
237 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
238 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
242 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
244 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
245 /* double precision (pseudo) 59 - 66 */
246 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
247 /* vectors (pseudo) 67 - 70 */
248 "fv0", "fv4", "fv8", "fv12",
249 /* FIXME: missing XF 71 - 86 */
250 /* FIXME: missing XD 87 - 94 */
254 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
256 return register_names
[reg_nr
];
259 static const unsigned char *
260 sh_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
262 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
263 static unsigned char breakpoint
[] = { 0xc3, 0xc3 };
265 *lenptr
= sizeof (breakpoint
);
269 /* Prologue looks like
273 sub <room_for_loca_vars>,r15
276 Actually it can be more complicated than this but that's it, basically.
279 #define GET_SOURCE_REG(x) (((x) >> 4) & 0xf)
280 #define GET_TARGET_REG(x) (((x) >> 8) & 0xf)
282 /* STS.L PR,@-r15 0100111100100010
283 r15-4-->r15, PR-->(r15) */
284 #define IS_STS(x) ((x) == 0x4f22)
286 /* MOV.L Rm,@-r15 00101111mmmm0110
287 r15-4-->r15, Rm-->(R15) */
288 #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
290 /* MOV r15,r14 0110111011110011
292 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
294 /* ADD #imm,r15 01111111iiiiiiii
296 #define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00)
298 #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
299 #define IS_SHLL_R3(x) ((x) == 0x4300)
301 /* ADD r3,r15 0011111100111100
303 #define IS_ADD_R3SP(x) ((x) == 0x3f3c)
305 /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
306 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
307 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
308 /* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to
309 make this entirely clear. */
310 /* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */
311 #define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b)
313 /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */
314 #define IS_MOV_ARG_TO_REG(x) \
315 (((x) & 0xf00f) == 0x6003 && \
316 ((x) & 0x00f0) >= 0x0040 && \
317 ((x) & 0x00f0) <= 0x0070)
318 /* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */
319 #define IS_MOV_ARG_TO_IND_R14(x) \
320 (((x) & 0xff0f) == 0x2e02 && \
321 ((x) & 0x00f0) >= 0x0040 && \
322 ((x) & 0x00f0) <= 0x0070)
323 /* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */
324 #define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \
325 (((x) & 0xff00) == 0x1e00 && \
326 ((x) & 0x00f0) >= 0x0040 && \
327 ((x) & 0x00f0) <= 0x0070)
329 /* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */
330 #define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000)
331 /* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */
332 #define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000)
333 /* SUB Rn,R15 00111111nnnn1000 */
334 #define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08)
336 #define FPSCR_SZ (1 << 20)
338 /* The following instructions are used for epilogue testing. */
339 #define IS_RESTORE_FP(x) ((x) == 0x6ef6)
340 #define IS_RTS(x) ((x) == 0x000b)
341 #define IS_LDS(x) ((x) == 0x4f26)
342 #define IS_MOV_FP_SP(x) ((x) == 0x6fe3)
343 #define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c)
344 #define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00)
346 /* Disassemble an instruction. */
348 gdb_print_insn_sh (bfd_vma memaddr
, disassemble_info
* info
)
350 info
->endian
= TARGET_BYTE_ORDER
;
351 return print_insn_sh (memaddr
, info
);
355 sh_analyze_prologue (CORE_ADDR pc
, CORE_ADDR current_pc
,
356 struct sh_frame_cache
*cache
)
363 int reg
, sav_reg
= -1;
365 if (pc
>= current_pc
)
369 for (opc
= pc
+ (2 * 28); pc
< opc
; pc
+= 2)
371 inst
= read_memory_unsigned_integer (pc
, 2);
372 /* See where the registers will be saved to */
375 cache
->saved_regs
[GET_SOURCE_REG (inst
)] = cache
->sp_offset
;
376 cache
->sp_offset
+= 4;
378 else if (IS_STS (inst
))
380 cache
->saved_regs
[PR_REGNUM
] = cache
->sp_offset
;
381 cache
->sp_offset
+= 4;
383 else if (IS_MOV_R3 (inst
))
385 r3_val
= ((inst
& 0xff) ^ 0x80) - 0x80;
387 else if (IS_SHLL_R3 (inst
))
391 else if (IS_ADD_R3SP (inst
))
393 cache
->sp_offset
+= -r3_val
;
395 else if (IS_ADD_IMM_SP (inst
))
397 offset
= ((inst
& 0xff) ^ 0x80) - 0x80;
398 cache
->sp_offset
-= offset
;
400 else if (IS_MOVW_PCREL_TO_REG (inst
))
404 reg
= GET_TARGET_REG (inst
);
408 offset
= (((inst
& 0xff) ^ 0x80) - 0x80) << 1;
410 read_memory_integer (((pc
+ 4) & ~3) + offset
, 2);
414 else if (IS_MOVL_PCREL_TO_REG (inst
))
418 reg
= (inst
& 0x0f00) >> 8;
422 offset
= (((inst
& 0xff) ^ 0x80) - 0x80) << 1;
424 read_memory_integer (((pc
+ 4) & ~3) + offset
, 4);
428 else if (IS_SUB_REG_FROM_SP (inst
))
430 reg
= GET_SOURCE_REG (inst
);
431 if (sav_reg
> 0 && reg
== sav_reg
)
435 cache
->sp_offset
+= sav_offset
;
437 else if (IS_FPUSH (inst
))
439 if (read_register (FPSCR_REGNUM
) & FPSCR_SZ
)
441 cache
->sp_offset
+= 8;
445 cache
->sp_offset
+= 4;
448 else if (IS_MOV_SP_FP (inst
))
452 /* At this point, only allow argument register moves to other
453 registers or argument register moves to @(X,fp) which are
454 moving the register arguments onto the stack area allocated
455 by a former add somenumber to SP call. Don't allow moving
456 to an fp indirect address above fp + cache->sp_offset. */
458 for (opc
= pc
+ 12; pc
< opc
; pc
+= 2)
460 inst
= read_memory_integer (pc
, 2);
461 if (IS_MOV_ARG_TO_IND_R14 (inst
))
463 reg
= GET_SOURCE_REG (inst
);
464 if (cache
->sp_offset
> 0)
465 cache
->saved_regs
[reg
] = cache
->sp_offset
;
467 else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst
))
469 reg
= GET_SOURCE_REG (inst
);
470 offset
= (inst
& 0xf) * 4;
471 if (cache
->sp_offset
> offset
)
472 cache
->saved_regs
[reg
] = cache
->sp_offset
- offset
;
474 else if (IS_MOV_ARG_TO_REG (inst
))
481 #if 0 /* This used to just stop when it found an instruction that
482 was not considered part of the prologue. Now, we just
483 keep going looking for likely instructions. */
492 /* Skip any prologue before the guts of a function */
494 /* Skip the prologue using the debug information. If this fails we'll
495 fall back on the 'guess' method below. */
497 after_prologue (CORE_ADDR pc
)
499 struct symtab_and_line sal
;
500 CORE_ADDR func_addr
, func_end
;
502 /* If we can not find the symbol in the partial symbol table, then
503 there is no hope we can determine the function's start address
505 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
508 /* Get the line associated with FUNC_ADDR. */
509 sal
= find_pc_line (func_addr
, 0);
511 /* There are only two cases to consider. First, the end of the source line
512 is within the function bounds. In that case we return the end of the
513 source line. Second is the end of the source line extends beyond the
514 bounds of the current function. We need to use the slow code to
515 examine instructions in that case. */
516 if (sal
.end
< func_end
)
523 sh_skip_prologue (CORE_ADDR start_pc
)
526 struct sh_frame_cache cache
;
528 /* See if we can determine the end of the prologue via the symbol table.
529 If so, then return either PC, or the PC after the prologue, whichever
531 pc
= after_prologue (start_pc
);
533 /* If after_prologue returned a useful address, then use it. Else
534 fall back on the instruction skipping code. */
536 return max (pc
, start_pc
);
538 cache
.sp_offset
= -4;
539 pc
= sh_analyze_prologue (start_pc
, (CORE_ADDR
) -1, &cache
);
548 Aggregate types not bigger than 8 bytes that have the same size and
549 alignment as one of the integer scalar types are returned in the
550 same registers as the integer type they match.
552 For example, a 2-byte aligned structure with size 2 bytes has the
553 same size and alignment as a short int, and will be returned in R0.
554 A 4-byte aligned structure with size 8 bytes has the same size and
555 alignment as a long long int, and will be returned in R0 and R1.
557 When an aggregate type is returned in R0 and R1, R0 contains the
558 first four bytes of the aggregate, and R1 contains the
559 remainder. If the size of the aggregate type is not a multiple of 4
560 bytes, the aggregate is tail-padded up to a multiple of 4
561 bytes. The value of the padding is undefined. For little-endian
562 targets the padding will appear at the most significant end of the
563 last element, for big-endian targets the padding appears at the
564 least significant end of the last element.
566 All other aggregate types are returned by address. The caller
567 function passes the address of an area large enough to hold the
568 aggregate value in R2. The called function stores the result in
571 To reiterate, structs smaller than 8 bytes could also be returned
572 in memory, if they don't pass the "same size and alignment as an
577 struct s { char c[3]; } wibble;
578 struct s foo(void) { return wibble; }
580 the return value from foo() will be in memory, not
581 in R0, because there is no 3-byte integer type.
585 struct s { char c[2]; } wibble;
586 struct s foo(void) { return wibble; }
588 because a struct containing two chars has alignment 1, that matches
589 type char, but size 2, that matches type short. There's no integer
590 type that has alignment 1 and size 2, so the struct is returned in
596 sh_use_struct_convention (int gcc_p
, struct type
*type
)
598 int len
= TYPE_LENGTH (type
);
599 int nelem
= TYPE_NFIELDS (type
);
601 /* Non-power of 2 length types and types bigger than 8 bytes (which don't
602 fit in two registers anyway) use struct convention. */
603 if (len
!= 1 && len
!= 2 && len
!= 4 && len
!= 8)
606 /* Scalar types and aggregate types with exactly one field are aligned
607 by definition. They are returned in registers. */
611 /* If the first field in the aggregate has the same length as the entire
612 aggregate type, the type is returned in registers. */
613 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, 0)) == len
)
616 /* If the size of the aggregate is 8 bytes and the first field is
617 of size 4 bytes its alignment is equal to long long's alignment,
618 so it's returned in registers. */
619 if (len
== 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type
, 0)) == 4)
622 /* Otherwise use struct convention. */
626 /* Extract from an array REGBUF containing the (raw) register state
627 the address in which a function should return its structure value,
628 as a CORE_ADDR (or an expression that can be used as one). */
630 sh_extract_struct_value_address (struct regcache
*regcache
)
634 regcache_cooked_read_unsigned (regcache
, STRUCT_RETURN_REGNUM
, &addr
);
639 sh_frame_align (struct gdbarch
*ignore
, CORE_ADDR sp
)
644 /* Function: push_dummy_call (formerly push_arguments)
645 Setup the function arguments for calling a function in the inferior.
647 On the Renesas SH architecture, there are four registers (R4 to R7)
648 which are dedicated for passing function arguments. Up to the first
649 four arguments (depending on size) may go into these registers.
650 The rest go on the stack.
652 MVS: Except on SH variants that have floating point registers.
653 In that case, float and double arguments are passed in the same
654 manner, but using FP registers instead of GP registers.
656 Arguments that are smaller than 4 bytes will still take up a whole
657 register or a whole 32-bit word on the stack, and will be
658 right-justified in the register or the stack word. This includes
659 chars, shorts, and small aggregate types.
661 Arguments that are larger than 4 bytes may be split between two or
662 more registers. If there are not enough registers free, an argument
663 may be passed partly in a register (or registers), and partly on the
664 stack. This includes doubles, long longs, and larger aggregates.
665 As far as I know, there is no upper limit to the size of aggregates
666 that will be passed in this way; in other words, the convention of
667 passing a pointer to a large aggregate instead of a copy is not used.
669 MVS: The above appears to be true for the SH variants that do not
670 have an FPU, however those that have an FPU appear to copy the
671 aggregate argument onto the stack (and not place it in registers)
672 if it is larger than 16 bytes (four GP registers).
674 An exceptional case exists for struct arguments (and possibly other
675 aggregates such as arrays) if the size is larger than 4 bytes but
676 not a multiple of 4 bytes. In this case the argument is never split
677 between the registers and the stack, but instead is copied in its
678 entirety onto the stack, AND also copied into as many registers as
679 there is room for. In other words, space in registers permitting,
680 two copies of the same argument are passed in. As far as I can tell,
681 only the one on the stack is used, although that may be a function
682 of the level of compiler optimization. I suspect this is a compiler
683 bug. Arguments of these odd sizes are left-justified within the
684 word (as opposed to arguments smaller than 4 bytes, which are
687 If the function is to return an aggregate type such as a struct, it
688 is either returned in the normal return value register R0 (if its
689 size is no greater than one byte), or else the caller must allocate
690 space into which the callee will copy the return value (if the size
691 is greater than one byte). In this case, a pointer to the return
692 value location is passed into the callee in register R2, which does
693 not displace any of the other arguments passed in via registers R4
696 /* Helper function to justify value in register according to endianess. */
698 sh_justify_value_in_reg (struct value
*val
, int len
)
700 static char valbuf
[4];
702 memset (valbuf
, 0, sizeof (valbuf
));
705 /* value gets right-justified in the register or stack word */
706 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
707 memcpy (valbuf
+ (4 - len
), (char *) VALUE_CONTENTS (val
), len
);
709 memcpy (valbuf
, (char *) VALUE_CONTENTS (val
), len
);
712 return (char *) VALUE_CONTENTS (val
);
715 /* Helper function to eval number of bytes to allocate on stack. */
717 sh_stack_allocsize (int nargs
, struct value
**args
)
721 stack_alloc
+= ((TYPE_LENGTH (VALUE_TYPE (args
[nargs
])) + 3) & ~3);
725 /* Helper functions for getting the float arguments right. Registers usage
726 depends on the ABI and the endianess. The comments should enlighten how
727 it's intended to work. */
729 /* This array stores which of the float arg registers are already in use. */
730 static int flt_argreg_array
[FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
+ 1];
732 /* This function just resets the above array to "no reg used so far". */
734 sh_init_flt_argreg (void)
736 memset (flt_argreg_array
, 0, sizeof flt_argreg_array
);
739 /* This function returns the next register to use for float arg passing.
740 It returns either a valid value between FLOAT_ARG0_REGNUM and
741 FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns
742 FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available.
744 Note that register number 0 in flt_argreg_array corresponds with the
745 real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is
746 29) the parity of the register number is preserved, which is important
747 for the double register passing test (see the "argreg & 1" test below). */
749 sh_next_flt_argreg (int len
)
753 /* First search for the next free register. */
754 for (argreg
= 0; argreg
<= FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
;
756 if (!flt_argreg_array
[argreg
])
759 /* No register left? */
760 if (argreg
> FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
)
761 return FLOAT_ARGLAST_REGNUM
+ 1;
765 /* Doubles are always starting in a even register number. */
768 flt_argreg_array
[argreg
] = 1;
772 /* No register left? */
773 if (argreg
> FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
)
774 return FLOAT_ARGLAST_REGNUM
+ 1;
776 /* Also mark the next register as used. */
777 flt_argreg_array
[argreg
+ 1] = 1;
779 else if (TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
781 /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */
782 if (!flt_argreg_array
[argreg
+ 1])
785 flt_argreg_array
[argreg
] = 1;
786 return FLOAT_ARG0_REGNUM
+ argreg
;
789 /* Helper function which figures out, if a type is treated like a float type.
791 The FPU ABIs have a special way how to treat types as float types.
792 Structures with exactly one member, which is of type float or double, are
793 treated exactly as the base types float or double:
803 are handled the same way as just
809 As a result, arguments of these struct types are pushed into floating point
810 registers exactly as floats or doubles, using the same decision algorithm.
812 The same is valid if these types are used as function return types. The
813 above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1
814 or even using struct convention as it is for other structs. */
817 sh_treat_as_flt_p (struct type
*type
)
819 int len
= TYPE_LENGTH (type
);
821 /* Ordinary float types are obviously treated as float. */
822 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
824 /* Otherwise non-struct types are not treated as float. */
825 if (TYPE_CODE (type
) != TYPE_CODE_STRUCT
)
827 /* Otherwise structs with more than one memeber are not treated as float. */
828 if (TYPE_NFIELDS (type
) != 1)
830 /* Otherwise if the type of that member is float, the whole type is
832 if (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0)) == TYPE_CODE_FLT
)
834 /* Otherwise it's not treated as float. */
839 sh_push_dummy_call_fpu (struct gdbarch
*gdbarch
,
841 struct regcache
*regcache
,
842 CORE_ADDR bp_addr
, int nargs
,
844 CORE_ADDR sp
, int struct_return
,
845 CORE_ADDR struct_addr
)
847 int stack_offset
= 0;
848 int argreg
= ARG0_REGNUM
;
854 int len
, reg_size
= 0;
855 int pass_on_stack
= 0;
858 /* first force sp to a 4-byte alignment */
859 sp
= sh_frame_align (gdbarch
, sp
);
862 regcache_cooked_write_unsigned (regcache
,
863 STRUCT_RETURN_REGNUM
, struct_addr
);
865 /* make room on stack for args */
866 sp
-= sh_stack_allocsize (nargs
, args
);
868 /* Initialize float argument mechanism. */
869 sh_init_flt_argreg ();
871 /* Now load as many as possible of the first arguments into
872 registers, and push the rest onto the stack. There are 16 bytes
873 in four registers available. Loop thru args from first to last. */
874 for (argnum
= 0; argnum
< nargs
; argnum
++)
876 type
= VALUE_TYPE (args
[argnum
]);
877 len
= TYPE_LENGTH (type
);
878 val
= sh_justify_value_in_reg (args
[argnum
], len
);
880 /* Some decisions have to be made how various types are handled.
881 This also differs in different ABIs. */
884 /* Find out the next register to use for a floating point value. */
885 treat_as_flt
= sh_treat_as_flt_p (type
);
887 flt_argreg
= sh_next_flt_argreg (len
);
888 /* In contrast to non-FPU CPUs, arguments are never split between
889 registers and stack. If an argument doesn't fit in the remaining
890 registers it's always pushed entirely on the stack. */
891 else if (len
> ((ARGLAST_REGNUM
- argreg
+ 1) * 4))
896 if ((treat_as_flt
&& flt_argreg
> FLOAT_ARGLAST_REGNUM
)
897 || (!treat_as_flt
&& (argreg
> ARGLAST_REGNUM
900 /* The data goes entirely on the stack, 4-byte aligned. */
901 reg_size
= (len
+ 3) & ~3;
902 write_memory (sp
+ stack_offset
, val
, reg_size
);
903 stack_offset
+= reg_size
;
905 else if (treat_as_flt
&& flt_argreg
<= FLOAT_ARGLAST_REGNUM
)
907 /* Argument goes in a float argument register. */
908 reg_size
= register_size (gdbarch
, flt_argreg
);
909 regval
= extract_unsigned_integer (val
, reg_size
);
910 /* In little endian mode, float types taking two registers
911 (doubles on sh4, long doubles on sh2e, sh3e and sh4) must
912 be stored swapped in the argument registers. The below
913 code first writes the first 32 bits in the next but one
914 register, increments the val and len values accordingly
915 and then proceeds as normal by writing the second 32 bits
916 into the next register. */
917 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
918 && TYPE_LENGTH (type
) == 2 * reg_size
)
920 regcache_cooked_write_unsigned (regcache
, flt_argreg
+ 1,
924 regval
= extract_unsigned_integer (val
, reg_size
);
926 regcache_cooked_write_unsigned (regcache
, flt_argreg
++, regval
);
928 else if (!treat_as_flt
&& argreg
<= ARGLAST_REGNUM
)
930 /* there's room in a register */
931 reg_size
= register_size (gdbarch
, argreg
);
932 regval
= extract_unsigned_integer (val
, reg_size
);
933 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
935 /* Store the value one register at a time or in one step on stack. */
941 /* Store return address. */
942 regcache_cooked_write_unsigned (regcache
, PR_REGNUM
, bp_addr
);
944 /* Update stack pointer. */
945 regcache_cooked_write_unsigned (regcache
, SP_REGNUM
, sp
);
951 sh_push_dummy_call_nofpu (struct gdbarch
*gdbarch
,
953 struct regcache
*regcache
,
955 int nargs
, struct value
**args
,
956 CORE_ADDR sp
, int struct_return
,
957 CORE_ADDR struct_addr
)
959 int stack_offset
= 0;
960 int argreg
= ARG0_REGNUM
;
967 /* first force sp to a 4-byte alignment */
968 sp
= sh_frame_align (gdbarch
, sp
);
971 regcache_cooked_write_unsigned (regcache
,
972 STRUCT_RETURN_REGNUM
, struct_addr
);
974 /* make room on stack for args */
975 sp
-= sh_stack_allocsize (nargs
, args
);
977 /* Now load as many as possible of the first arguments into
978 registers, and push the rest onto the stack. There are 16 bytes
979 in four registers available. Loop thru args from first to last. */
980 for (argnum
= 0; argnum
< nargs
; argnum
++)
982 type
= VALUE_TYPE (args
[argnum
]);
983 len
= TYPE_LENGTH (type
);
984 val
= sh_justify_value_in_reg (args
[argnum
], len
);
988 if (argreg
> ARGLAST_REGNUM
)
990 /* The remainder of the data goes entirely on the stack,
992 reg_size
= (len
+ 3) & ~3;
993 write_memory (sp
+ stack_offset
, val
, reg_size
);
994 stack_offset
+= reg_size
;
996 else if (argreg
<= ARGLAST_REGNUM
)
998 /* there's room in a register */
999 reg_size
= register_size (gdbarch
, argreg
);
1000 regval
= extract_unsigned_integer (val
, reg_size
);
1001 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
1003 /* Store the value reg_size bytes at a time. This means that things
1004 larger than reg_size bytes may go partly in registers and partly
1011 /* Store return address. */
1012 regcache_cooked_write_unsigned (regcache
, PR_REGNUM
, bp_addr
);
1014 /* Update stack pointer. */
1015 regcache_cooked_write_unsigned (regcache
, SP_REGNUM
, sp
);
1020 /* Find a function's return value in the appropriate registers (in
1021 regbuf), and copy it into valbuf. Extract from an array REGBUF
1022 containing the (raw) register state a function return value of type
1023 TYPE, and copy that, in virtual format, into VALBUF. */
1025 sh_default_extract_return_value (struct type
*type
, struct regcache
*regcache
,
1028 int len
= TYPE_LENGTH (type
);
1029 int return_register
= R0_REGNUM
;
1036 regcache_cooked_read_unsigned (regcache
, R0_REGNUM
, &c
);
1037 store_unsigned_integer (valbuf
, len
, c
);
1041 int i
, regnum
= R0_REGNUM
;
1042 for (i
= 0; i
< len
; i
+= 4)
1043 regcache_raw_read (regcache
, regnum
++, (char *) valbuf
+ i
);
1046 error ("bad size for return value");
1050 sh3e_sh4_extract_return_value (struct type
*type
, struct regcache
*regcache
,
1053 if (sh_treat_as_flt_p (type
))
1055 int len
= TYPE_LENGTH (type
);
1056 int i
, regnum
= FP0_REGNUM
;
1057 for (i
= 0; i
< len
; i
+= 4)
1058 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
1059 regcache_raw_read (regcache
, regnum
++, (char *) valbuf
+ len
- 4 - i
);
1061 regcache_raw_read (regcache
, regnum
++, (char *) valbuf
+ i
);
1064 sh_default_extract_return_value (type
, regcache
, valbuf
);
1067 /* Write into appropriate registers a function return value
1068 of type TYPE, given in virtual format.
1069 If the architecture is sh4 or sh3e, store a function's return value
1070 in the R0 general register or in the FP0 floating point register,
1071 depending on the type of the return value. In all the other cases
1072 the result is stored in r0, left-justified. */
1074 sh_default_store_return_value (struct type
*type
, struct regcache
*regcache
,
1078 int len
= TYPE_LENGTH (type
);
1082 val
= extract_unsigned_integer (valbuf
, len
);
1083 regcache_cooked_write_unsigned (regcache
, R0_REGNUM
, val
);
1087 int i
, regnum
= R0_REGNUM
;
1088 for (i
= 0; i
< len
; i
+= 4)
1089 regcache_raw_write (regcache
, regnum
++, (char *) valbuf
+ i
);
1094 sh3e_sh4_store_return_value (struct type
*type
, struct regcache
*regcache
,
1097 if (sh_treat_as_flt_p (type
))
1099 int len
= TYPE_LENGTH (type
);
1100 int i
, regnum
= FP0_REGNUM
;
1101 for (i
= 0; i
< len
; i
+= 4)
1102 regcache_raw_write (regcache
, regnum
++, (char *) valbuf
+ i
);
1105 sh_default_store_return_value (type
, regcache
, valbuf
);
1108 /* Print the registers in a form similar to the E7000 */
1111 sh_generic_show_regs (void)
1113 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1114 paddr (read_register (PC_REGNUM
)),
1115 (long) read_register (SR_REGNUM
),
1116 (long) read_register (PR_REGNUM
),
1117 (long) read_register (MACH_REGNUM
),
1118 (long) read_register (MACL_REGNUM
));
1120 printf_filtered ("GBR=%08lx VBR=%08lx",
1121 (long) read_register (GBR_REGNUM
),
1122 (long) read_register (VBR_REGNUM
));
1125 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1126 (long) read_register (0), (long) read_register (1),
1127 (long) read_register (2), (long) read_register (3),
1128 (long) read_register (4), (long) read_register (5),
1129 (long) read_register (6), (long) read_register (7));
1130 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1131 (long) read_register (8), (long) read_register (9),
1132 (long) read_register (10), (long) read_register (11),
1133 (long) read_register (12), (long) read_register (13),
1134 (long) read_register (14), (long) read_register (15));
1138 sh3_show_regs (void)
1140 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1141 paddr (read_register (PC_REGNUM
)),
1142 (long) read_register (SR_REGNUM
),
1143 (long) read_register (PR_REGNUM
),
1144 (long) read_register (MACH_REGNUM
),
1145 (long) read_register (MACL_REGNUM
));
1147 printf_filtered ("GBR=%08lx VBR=%08lx",
1148 (long) read_register (GBR_REGNUM
),
1149 (long) read_register (VBR_REGNUM
));
1150 printf_filtered (" SSR=%08lx SPC=%08lx",
1151 (long) read_register (SSR_REGNUM
),
1152 (long) read_register (SPC_REGNUM
));
1155 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1156 (long) read_register (0), (long) read_register (1),
1157 (long) read_register (2), (long) read_register (3),
1158 (long) read_register (4), (long) read_register (5),
1159 (long) read_register (6), (long) read_register (7));
1160 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1161 (long) read_register (8), (long) read_register (9),
1162 (long) read_register (10), (long) read_register (11),
1163 (long) read_register (12), (long) read_register (13),
1164 (long) read_register (14), (long) read_register (15));
1169 sh2e_show_regs (void)
1171 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1172 paddr (read_register (PC_REGNUM
)),
1173 (long) read_register (SR_REGNUM
),
1174 (long) read_register (PR_REGNUM
),
1175 (long) read_register (MACH_REGNUM
),
1176 (long) read_register (MACL_REGNUM
));
1178 printf_filtered ("GBR=%08lx VBR=%08lx",
1179 (long) read_register (GBR_REGNUM
),
1180 (long) read_register (VBR_REGNUM
));
1181 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1182 (long) read_register (FPUL_REGNUM
),
1183 (long) read_register (FPSCR_REGNUM
));
1186 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1187 (long) read_register (0), (long) read_register (1),
1188 (long) read_register (2), (long) read_register (3),
1189 (long) read_register (4), (long) read_register (5),
1190 (long) read_register (6), (long) read_register (7));
1191 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1192 (long) read_register (8), (long) read_register (9),
1193 (long) read_register (10), (long) read_register (11),
1194 (long) read_register (12), (long) read_register (13),
1195 (long) read_register (14), (long) read_register (15));
1197 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM
+ 0), (long) read_register (FP0_REGNUM
+ 1), (long) read_register (FP0_REGNUM
+ 2), (long) read_register (FP0_REGNUM
+ 3), (long) read_register (FP0_REGNUM
+ 4), (long) read_register (FP0_REGNUM
+ 5), (long) read_register (FP0_REGNUM
+ 6), (long) read_register (FP0_REGNUM
+ 7));
1198 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM
+ 8), (long) read_register (FP0_REGNUM
+ 9), (long) read_register (FP0_REGNUM
+ 10), (long) read_register (FP0_REGNUM
+ 11), (long) read_register (FP0_REGNUM
+ 12), (long) read_register (FP0_REGNUM
+ 13), (long) read_register (FP0_REGNUM
+ 14), (long) read_register (FP0_REGNUM
+ 15));
1202 sh3e_show_regs (void)
1204 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1205 paddr (read_register (PC_REGNUM
)),
1206 (long) read_register (SR_REGNUM
),
1207 (long) read_register (PR_REGNUM
),
1208 (long) read_register (MACH_REGNUM
),
1209 (long) read_register (MACL_REGNUM
));
1211 printf_filtered ("GBR=%08lx VBR=%08lx",
1212 (long) read_register (GBR_REGNUM
),
1213 (long) read_register (VBR_REGNUM
));
1214 printf_filtered (" SSR=%08lx SPC=%08lx",
1215 (long) read_register (SSR_REGNUM
),
1216 (long) read_register (SPC_REGNUM
));
1217 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1218 (long) read_register (FPUL_REGNUM
),
1219 (long) read_register (FPSCR_REGNUM
));
1222 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1223 (long) read_register (0), (long) read_register (1),
1224 (long) read_register (2), (long) read_register (3),
1225 (long) read_register (4), (long) read_register (5),
1226 (long) read_register (6), (long) read_register (7));
1227 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1228 (long) read_register (8), (long) read_register (9),
1229 (long) read_register (10), (long) read_register (11),
1230 (long) read_register (12), (long) read_register (13),
1231 (long) read_register (14), (long) read_register (15));
1233 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM
+ 0), (long) read_register (FP0_REGNUM
+ 1), (long) read_register (FP0_REGNUM
+ 2), (long) read_register (FP0_REGNUM
+ 3), (long) read_register (FP0_REGNUM
+ 4), (long) read_register (FP0_REGNUM
+ 5), (long) read_register (FP0_REGNUM
+ 6), (long) read_register (FP0_REGNUM
+ 7));
1234 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM
+ 8), (long) read_register (FP0_REGNUM
+ 9), (long) read_register (FP0_REGNUM
+ 10), (long) read_register (FP0_REGNUM
+ 11), (long) read_register (FP0_REGNUM
+ 12), (long) read_register (FP0_REGNUM
+ 13), (long) read_register (FP0_REGNUM
+ 14), (long) read_register (FP0_REGNUM
+ 15));
1238 sh3_dsp_show_regs (void)
1240 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1241 paddr (read_register (PC_REGNUM
)),
1242 (long) read_register (SR_REGNUM
),
1243 (long) read_register (PR_REGNUM
),
1244 (long) read_register (MACH_REGNUM
),
1245 (long) read_register (MACL_REGNUM
));
1247 printf_filtered ("GBR=%08lx VBR=%08lx",
1248 (long) read_register (GBR_REGNUM
),
1249 (long) read_register (VBR_REGNUM
));
1251 printf_filtered (" SSR=%08lx SPC=%08lx",
1252 (long) read_register (SSR_REGNUM
),
1253 (long) read_register (SPC_REGNUM
));
1255 printf_filtered (" DSR=%08lx", (long) read_register (DSR_REGNUM
));
1258 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1259 (long) read_register (0), (long) read_register (1),
1260 (long) read_register (2), (long) read_register (3),
1261 (long) read_register (4), (long) read_register (5),
1262 (long) read_register (6), (long) read_register (7));
1263 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1264 (long) read_register (8), (long) read_register (9),
1265 (long) read_register (10), (long) read_register (11),
1266 (long) read_register (12), (long) read_register (13),
1267 (long) read_register (14), (long) read_register (15));
1270 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1271 (long) read_register (A0G_REGNUM
) & 0xff,
1272 (long) read_register (A0_REGNUM
), (long) read_register (M0_REGNUM
),
1273 (long) read_register (X0_REGNUM
), (long) read_register (Y0_REGNUM
),
1274 (long) read_register (RS_REGNUM
), (long) read_register (MOD_REGNUM
));
1275 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1276 (long) read_register (A1G_REGNUM
) & 0xff,
1277 (long) read_register (A1_REGNUM
),
1278 (long) read_register (M1_REGNUM
),
1279 (long) read_register (X1_REGNUM
),
1280 (long) read_register (Y1_REGNUM
),
1281 (long) read_register (RE_REGNUM
));
1285 sh4_show_regs (void)
1287 int pr
= read_register (FPSCR_REGNUM
) & 0x80000;
1288 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1289 paddr (read_register (PC_REGNUM
)),
1290 (long) read_register (SR_REGNUM
),
1291 (long) read_register (PR_REGNUM
),
1292 (long) read_register (MACH_REGNUM
),
1293 (long) read_register (MACL_REGNUM
));
1295 printf_filtered ("GBR=%08lx VBR=%08lx",
1296 (long) read_register (GBR_REGNUM
),
1297 (long) read_register (VBR_REGNUM
));
1298 printf_filtered (" SSR=%08lx SPC=%08lx",
1299 (long) read_register (SSR_REGNUM
),
1300 (long) read_register (SPC_REGNUM
));
1301 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1302 (long) read_register (FPUL_REGNUM
),
1303 (long) read_register (FPSCR_REGNUM
));
1306 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1307 (long) read_register (0), (long) read_register (1),
1308 (long) read_register (2), (long) read_register (3),
1309 (long) read_register (4), (long) read_register (5),
1310 (long) read_register (6), (long) read_register (7));
1311 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1312 (long) read_register (8), (long) read_register (9),
1313 (long) read_register (10), (long) read_register (11),
1314 (long) read_register (12), (long) read_register (13),
1315 (long) read_register (14), (long) read_register (15));
1317 printf_filtered ((pr
1318 ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1320 "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1321 (long) read_register (FP0_REGNUM
+ 0),
1322 (long) read_register (FP0_REGNUM
+ 1),
1323 (long) read_register (FP0_REGNUM
+ 2),
1324 (long) read_register (FP0_REGNUM
+ 3),
1325 (long) read_register (FP0_REGNUM
+ 4),
1326 (long) read_register (FP0_REGNUM
+ 5),
1327 (long) read_register (FP0_REGNUM
+ 6),
1328 (long) read_register (FP0_REGNUM
+ 7));
1329 printf_filtered ((pr
?
1330 "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" :
1331 "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1332 (long) read_register (FP0_REGNUM
+ 8),
1333 (long) read_register (FP0_REGNUM
+ 9),
1334 (long) read_register (FP0_REGNUM
+ 10),
1335 (long) read_register (FP0_REGNUM
+ 11),
1336 (long) read_register (FP0_REGNUM
+ 12),
1337 (long) read_register (FP0_REGNUM
+ 13),
1338 (long) read_register (FP0_REGNUM
+ 14),
1339 (long) read_register (FP0_REGNUM
+ 15));
1343 sh_dsp_show_regs (void)
1345 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1346 paddr (read_register (PC_REGNUM
)),
1347 (long) read_register (SR_REGNUM
),
1348 (long) read_register (PR_REGNUM
),
1349 (long) read_register (MACH_REGNUM
),
1350 (long) read_register (MACL_REGNUM
));
1352 printf_filtered ("GBR=%08lx VBR=%08lx",
1353 (long) read_register (GBR_REGNUM
),
1354 (long) read_register (VBR_REGNUM
));
1356 printf_filtered (" DSR=%08lx", (long) read_register (DSR_REGNUM
));
1359 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1360 (long) read_register (0), (long) read_register (1),
1361 (long) read_register (2), (long) read_register (3),
1362 (long) read_register (4), (long) read_register (5),
1363 (long) read_register (6), (long) read_register (7));
1364 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1365 (long) read_register (8), (long) read_register (9),
1366 (long) read_register (10), (long) read_register (11),
1367 (long) read_register (12), (long) read_register (13),
1368 (long) read_register (14), (long) read_register (15));
1371 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1372 (long) read_register (A0G_REGNUM
) & 0xff,
1373 (long) read_register (A0_REGNUM
), (long) read_register (M0_REGNUM
),
1374 (long) read_register (X0_REGNUM
), (long) read_register (Y0_REGNUM
),
1375 (long) read_register (RS_REGNUM
), (long) read_register (MOD_REGNUM
));
1376 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1377 (long) read_register (A1G_REGNUM
) & 0xff,
1378 (long) read_register (A1_REGNUM
),
1379 (long) read_register (M1_REGNUM
),
1380 (long) read_register (X1_REGNUM
),
1381 (long) read_register (Y1_REGNUM
),
1382 (long) read_register (RE_REGNUM
));
1386 sh_show_regs_command (char *args
, int from_tty
)
1392 /* Return the GDB type object for the "standard" data type
1393 of data in register N. */
1394 static struct type
*
1395 sh_sh3e_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
1397 if ((reg_nr
>= FP0_REGNUM
1398 && (reg_nr
<= FP_LAST_REGNUM
)) || (reg_nr
== FPUL_REGNUM
))
1399 return builtin_type_float
;
1401 return builtin_type_int
;
1404 static struct type
*
1405 sh_sh4_build_float_register_type (int high
)
1409 temp
= create_range_type (NULL
, builtin_type_int
, 0, high
);
1410 return create_array_type (NULL
, builtin_type_float
, temp
);
1413 static struct type
*
1414 sh_sh4_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
1416 if ((reg_nr
>= FP0_REGNUM
1417 && (reg_nr
<= FP_LAST_REGNUM
)) || (reg_nr
== FPUL_REGNUM
))
1418 return builtin_type_float
;
1419 else if (reg_nr
>= DR0_REGNUM
&& reg_nr
<= DR_LAST_REGNUM
)
1420 return builtin_type_double
;
1421 else if (reg_nr
>= FV0_REGNUM
&& reg_nr
<= FV_LAST_REGNUM
)
1422 return sh_sh4_build_float_register_type (3);
1424 return builtin_type_int
;
1427 static struct type
*
1428 sh_default_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
1430 return builtin_type_int
;
1433 /* On the sh4, the DRi pseudo registers are problematic if the target
1434 is little endian. When the user writes one of those registers, for
1435 instance with 'ser var $dr0=1', we want the double to be stored
1437 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1438 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1440 This corresponds to little endian byte order & big endian word
1441 order. However if we let gdb write the register w/o conversion, it
1442 will write fr0 and fr1 this way:
1443 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1444 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1445 because it will consider fr0 and fr1 as a single LE stretch of memory.
1447 To achieve what we want we must force gdb to store things in
1448 floatformat_ieee_double_littlebyte_bigword (which is defined in
1449 include/floatformat.h and libiberty/floatformat.c.
1451 In case the target is big endian, there is no problem, the
1452 raw bytes will look like:
1453 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
1454 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1456 The other pseudo registers (the FVs) also don't pose a problem
1457 because they are stored as 4 individual FP elements. */
1460 sh_sh4_register_convert_to_virtual (int regnum
, struct type
*type
,
1461 char *from
, char *to
)
1463 if (regnum
>= DR0_REGNUM
&& regnum
<= DR_LAST_REGNUM
)
1466 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword
,
1468 store_typed_floating (to
, type
, val
);
1472 ("sh_register_convert_to_virtual called with non DR register number");
1476 sh_sh4_register_convert_to_raw (struct type
*type
, int regnum
,
1477 const void *from
, void *to
)
1479 if (regnum
>= DR0_REGNUM
&& regnum
<= DR_LAST_REGNUM
)
1481 DOUBLEST val
= extract_typed_floating (from
, type
);
1482 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword
,
1486 error ("sh_register_convert_to_raw called with non DR register number");
1489 /* For vectors of 4 floating point registers. */
1491 fv_reg_base_num (int fv_regnum
)
1495 fp_regnum
= FP0_REGNUM
+ (fv_regnum
- FV0_REGNUM
) * 4;
1499 /* For double precision floating point registers, i.e 2 fp regs.*/
1501 dr_reg_base_num (int dr_regnum
)
1505 fp_regnum
= FP0_REGNUM
+ (dr_regnum
- DR0_REGNUM
) * 2;
1510 sh_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1511 int reg_nr
, void *buffer
)
1513 int base_regnum
, portion
;
1514 char temp_buffer
[MAX_REGISTER_SIZE
];
1516 if (reg_nr
>= DR0_REGNUM
&& reg_nr
<= DR_LAST_REGNUM
)
1518 base_regnum
= dr_reg_base_num (reg_nr
);
1520 /* Build the value in the provided buffer. */
1521 /* Read the real regs for which this one is an alias. */
1522 for (portion
= 0; portion
< 2; portion
++)
1523 regcache_raw_read (regcache
, base_regnum
+ portion
,
1525 + register_size (gdbarch
,
1526 base_regnum
) * portion
));
1527 /* We must pay attention to the endiannes. */
1528 sh_sh4_register_convert_to_virtual (reg_nr
,
1529 gdbarch_register_type (gdbarch
,
1531 temp_buffer
, buffer
);
1533 else if (reg_nr
>= FV0_REGNUM
&& reg_nr
<= FV_LAST_REGNUM
)
1535 base_regnum
= fv_reg_base_num (reg_nr
);
1537 /* Read the real regs for which this one is an alias. */
1538 for (portion
= 0; portion
< 4; portion
++)
1539 regcache_raw_read (regcache
, base_regnum
+ portion
,
1541 + register_size (gdbarch
,
1542 base_regnum
) * portion
));
1547 sh_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1548 int reg_nr
, const void *buffer
)
1550 int base_regnum
, portion
;
1551 char temp_buffer
[MAX_REGISTER_SIZE
];
1553 if (reg_nr
>= DR0_REGNUM
&& reg_nr
<= DR_LAST_REGNUM
)
1555 base_regnum
= dr_reg_base_num (reg_nr
);
1557 /* We must pay attention to the endiannes. */
1558 sh_sh4_register_convert_to_raw (gdbarch_register_type (gdbarch
, reg_nr
),
1559 reg_nr
, buffer
, temp_buffer
);
1561 /* Write the real regs for which this one is an alias. */
1562 for (portion
= 0; portion
< 2; portion
++)
1563 regcache_raw_write (regcache
, base_regnum
+ portion
,
1565 + register_size (gdbarch
,
1566 base_regnum
) * portion
));
1568 else if (reg_nr
>= FV0_REGNUM
&& reg_nr
<= FV_LAST_REGNUM
)
1570 base_regnum
= fv_reg_base_num (reg_nr
);
1572 /* Write the real regs for which this one is an alias. */
1573 for (portion
= 0; portion
< 4; portion
++)
1574 regcache_raw_write (regcache
, base_regnum
+ portion
,
1576 + register_size (gdbarch
,
1577 base_regnum
) * portion
));
1581 /* Floating point vector of 4 float registers. */
1583 do_fv_register_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
1586 int first_fp_reg_num
= fv_reg_base_num (fv_regnum
);
1587 fprintf_filtered (file
, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
1588 fv_regnum
- FV0_REGNUM
,
1589 (int) read_register (first_fp_reg_num
),
1590 (int) read_register (first_fp_reg_num
+ 1),
1591 (int) read_register (first_fp_reg_num
+ 2),
1592 (int) read_register (first_fp_reg_num
+ 3));
1595 /* Double precision registers. */
1597 do_dr_register_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
1600 int first_fp_reg_num
= dr_reg_base_num (dr_regnum
);
1602 fprintf_filtered (file
, "dr%d\t0x%08x%08x\n",
1603 dr_regnum
- DR0_REGNUM
,
1604 (int) read_register (first_fp_reg_num
),
1605 (int) read_register (first_fp_reg_num
+ 1));
1609 sh_print_pseudo_register (struct gdbarch
*gdbarch
, struct ui_file
*file
,
1612 if (regnum
< NUM_REGS
|| regnum
>= NUM_REGS
+ NUM_PSEUDO_REGS
)
1613 internal_error (__FILE__
, __LINE__
,
1614 "Invalid pseudo register number %d\n", regnum
);
1615 else if (regnum
>= DR0_REGNUM
&& regnum
<= DR_LAST_REGNUM
)
1616 do_dr_register_info (gdbarch
, file
, regnum
);
1617 else if (regnum
>= FV0_REGNUM
&& regnum
<= FV_LAST_REGNUM
)
1618 do_fv_register_info (gdbarch
, file
, regnum
);
1622 sh_do_fp_register (struct gdbarch
*gdbarch
, struct ui_file
*file
, int regnum
)
1623 { /* do values for FP (float) regs */
1625 double flt
; /* double extracted from raw hex data */
1629 /* Allocate space for the float. */
1630 raw_buffer
= (char *) alloca (register_size (gdbarch
, FP0_REGNUM
));
1632 /* Get the data in raw format. */
1633 if (!frame_register_read (get_selected_frame (), regnum
, raw_buffer
))
1634 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
1636 /* Get the register as a number */
1637 flt
= unpack_double (builtin_type_float
, raw_buffer
, &inv
);
1639 /* Print the name and some spaces. */
1640 fputs_filtered (REGISTER_NAME (regnum
), file
);
1641 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum
)), file
);
1643 /* Print the value. */
1645 fprintf_filtered (file
, "<invalid float>");
1647 fprintf_filtered (file
, "%-10.9g", flt
);
1649 /* Print the fp register as hex. */
1650 fprintf_filtered (file
, "\t(raw 0x");
1651 for (j
= 0; j
< register_size (gdbarch
, regnum
); j
++)
1653 int idx
= (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
1655 : register_size (gdbarch
, regnum
) - 1 - j
);
1656 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[idx
]);
1658 fprintf_filtered (file
, ")");
1659 fprintf_filtered (file
, "\n");
1663 sh_do_register (struct gdbarch
*gdbarch
, struct ui_file
*file
, int regnum
)
1665 char raw_buffer
[MAX_REGISTER_SIZE
];
1667 fputs_filtered (REGISTER_NAME (regnum
), file
);
1668 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum
)), file
);
1670 /* Get the data in raw format. */
1671 if (!frame_register_read (get_selected_frame (), regnum
, raw_buffer
))
1672 fprintf_filtered (file
, "*value not available*\n");
1674 val_print (gdbarch_register_type (gdbarch
, regnum
), raw_buffer
, 0, 0,
1675 file
, 'x', 1, 0, Val_pretty_default
);
1676 fprintf_filtered (file
, "\t");
1677 val_print (gdbarch_register_type (gdbarch
, regnum
), raw_buffer
, 0, 0,
1678 file
, 0, 1, 0, Val_pretty_default
);
1679 fprintf_filtered (file
, "\n");
1683 sh_print_register (struct gdbarch
*gdbarch
, struct ui_file
*file
, int regnum
)
1685 if (regnum
< 0 || regnum
>= NUM_REGS
+ NUM_PSEUDO_REGS
)
1686 internal_error (__FILE__
, __LINE__
,
1687 "Invalid register number %d\n", regnum
);
1689 else if (regnum
>= 0 && regnum
< NUM_REGS
)
1691 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
1693 sh_do_fp_register (gdbarch
, file
, regnum
); /* FP regs */
1695 sh_do_register (gdbarch
, file
, regnum
); /* All other regs */
1698 else if (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
1700 sh_print_pseudo_register (gdbarch
, file
, regnum
);
1705 sh_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
1706 struct frame_info
*frame
, int regnum
, int fpregs
)
1708 if (regnum
!= -1) /* do one specified register */
1710 if (*(REGISTER_NAME (regnum
)) == '\0')
1711 error ("Not a valid register for the current processor type");
1713 sh_print_register (gdbarch
, file
, regnum
);
1716 /* do all (or most) registers */
1719 while (regnum
< NUM_REGS
)
1721 /* If the register name is empty, it is undefined for this
1722 processor, so don't display anything. */
1723 if (REGISTER_NAME (regnum
) == NULL
1724 || *(REGISTER_NAME (regnum
)) == '\0')
1730 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
1735 /* true for "INFO ALL-REGISTERS" command */
1736 sh_do_fp_register (gdbarch
, file
, regnum
); /* FP regs */
1740 regnum
+= (FP_LAST_REGNUM
- FP0_REGNUM
); /* skip FP regs */
1744 sh_do_register (gdbarch
, file
, regnum
); /* All other regs */
1750 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
1752 sh_print_pseudo_register (gdbarch
, file
, regnum
);
1758 #ifdef SVR4_SHARED_LIBS
1760 /* Fetch (and possibly build) an appropriate link_map_offsets structure
1761 for native i386 linux targets using the struct offsets defined in
1762 link.h (but without actual reference to that file).
1764 This makes it possible to access i386-linux shared libraries from
1765 a gdb that was not built on an i386-linux host (for cross debugging).
1768 struct link_map_offsets
*
1769 sh_linux_svr4_fetch_link_map_offsets (void)
1771 static struct link_map_offsets lmo
;
1772 static struct link_map_offsets
*lmp
= 0;
1778 lmo
.r_debug_size
= 8; /* 20 not actual size but all we need */
1780 lmo
.r_map_offset
= 4;
1783 lmo
.link_map_size
= 20; /* 552 not actual size but all we need */
1785 lmo
.l_addr_offset
= 0;
1786 lmo
.l_addr_size
= 4;
1788 lmo
.l_name_offset
= 4;
1789 lmo
.l_name_size
= 4;
1791 lmo
.l_next_offset
= 12;
1792 lmo
.l_next_size
= 4;
1794 lmo
.l_prev_offset
= 16;
1795 lmo
.l_prev_size
= 4;
1800 #endif /* SVR4_SHARED_LIBS */
1803 sh_dsp_register_sim_regno (int nr
)
1805 if (legacy_register_sim_regno (nr
) < 0)
1806 return legacy_register_sim_regno (nr
);
1807 if (nr
>= DSR_REGNUM
&& nr
<= Y1_REGNUM
)
1808 return nr
- DSR_REGNUM
+ SIM_SH_DSR_REGNUM
;
1809 if (nr
== MOD_REGNUM
)
1810 return SIM_SH_MOD_REGNUM
;
1811 if (nr
== RS_REGNUM
)
1812 return SIM_SH_RS_REGNUM
;
1813 if (nr
== RE_REGNUM
)
1814 return SIM_SH_RE_REGNUM
;
1815 if (nr
>= R0_BANK_REGNUM
&& nr
<= R7_BANK_REGNUM
)
1816 return nr
- R0_BANK_REGNUM
+ SIM_SH_R0_BANK_REGNUM
;
1820 static struct sh_frame_cache
*
1821 sh_alloc_frame_cache (void)
1823 struct sh_frame_cache
*cache
;
1826 cache
= FRAME_OBSTACK_ZALLOC (struct sh_frame_cache
);
1830 cache
->saved_sp
= 0;
1831 cache
->sp_offset
= 0;
1834 /* Frameless until proven otherwise. */
1837 /* Saved registers. We initialize these to -1 since zero is a valid
1838 offset (that's where fp is supposed to be stored). */
1839 for (i
= 0; i
< SH_NUM_REGS
; i
++)
1841 cache
->saved_regs
[i
] = -1;
1847 static struct sh_frame_cache
*
1848 sh_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1850 struct sh_frame_cache
*cache
;
1851 CORE_ADDR current_pc
;
1857 cache
= sh_alloc_frame_cache ();
1858 *this_cache
= cache
;
1860 /* In principle, for normal frames, fp holds the frame pointer,
1861 which holds the base address for the current stack frame.
1862 However, for functions that don't need it, the frame pointer is
1863 optional. For these "frameless" functions the frame pointer is
1864 actually the frame pointer of the calling frame. */
1865 cache
->base
= frame_unwind_register_unsigned (next_frame
, FP_REGNUM
);
1866 if (cache
->base
== 0)
1869 cache
->pc
= frame_func_unwind (next_frame
);
1870 current_pc
= frame_pc_unwind (next_frame
);
1872 sh_analyze_prologue (cache
->pc
, current_pc
, cache
);
1874 if (!cache
->uses_fp
)
1876 /* We didn't find a valid frame, which means that CACHE->base
1877 currently holds the frame pointer for our calling frame. If
1878 we're at the start of a function, or somewhere half-way its
1879 prologue, the function's frame probably hasn't been fully
1880 setup yet. Try to reconstruct the base address for the stack
1881 frame by looking at the stack pointer. For truly "frameless"
1882 functions this might work too. */
1883 cache
->base
= frame_unwind_register_unsigned (next_frame
, SP_REGNUM
);
1886 /* Now that we have the base address for the stack frame we can
1887 calculate the value of sp in the calling frame. */
1888 cache
->saved_sp
= cache
->base
+ cache
->sp_offset
;
1890 /* Adjust all the saved registers such that they contain addresses
1891 instead of offsets. */
1892 for (i
= 0; i
< SH_NUM_REGS
; i
++)
1893 if (cache
->saved_regs
[i
] != -1)
1894 cache
->saved_regs
[i
] = cache
->saved_sp
- cache
->saved_regs
[i
] - 4;
1900 sh_frame_prev_register (struct frame_info
*next_frame
, void **this_cache
,
1901 int regnum
, int *optimizedp
,
1902 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1903 int *realnump
, void *valuep
)
1905 struct sh_frame_cache
*cache
= sh_frame_cache (next_frame
, this_cache
);
1907 gdb_assert (regnum
>= 0);
1909 if (regnum
== SP_REGNUM
&& cache
->saved_sp
)
1917 /* Store the value. */
1918 store_unsigned_integer (valuep
, 4, cache
->saved_sp
);
1923 /* The PC of the previous frame is stored in the PR register of
1924 the current frame. Frob regnum so that we pull the value from
1925 the correct place. */
1926 if (regnum
== PC_REGNUM
)
1929 if (regnum
< SH_NUM_REGS
&& cache
->saved_regs
[regnum
] != -1)
1932 *lvalp
= lval_memory
;
1933 *addrp
= cache
->saved_regs
[regnum
];
1937 /* Read the value in from memory. */
1938 read_memory (*addrp
, valuep
,
1939 register_size (current_gdbarch
, regnum
));
1944 frame_register_unwind (next_frame
, regnum
,
1945 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1949 sh_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1950 struct frame_id
*this_id
)
1952 struct sh_frame_cache
*cache
= sh_frame_cache (next_frame
, this_cache
);
1954 /* This marks the outermost frame. */
1955 if (cache
->base
== 0)
1958 *this_id
= frame_id_build (cache
->saved_sp
, cache
->pc
);
1961 static const struct frame_unwind sh_frame_unwind
= {
1964 sh_frame_prev_register
1967 static const struct frame_unwind
*
1968 sh_frame_sniffer (struct frame_info
*next_frame
)
1970 return &sh_frame_unwind
;
1974 sh_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1976 return frame_unwind_register_unsigned (next_frame
, SP_REGNUM
);
1980 sh_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1982 return frame_unwind_register_unsigned (next_frame
, PC_REGNUM
);
1985 static struct frame_id
1986 sh_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1988 return frame_id_build (sh_unwind_sp (gdbarch
, next_frame
),
1989 frame_pc_unwind (next_frame
));
1993 sh_frame_base_address (struct frame_info
*next_frame
, void **this_cache
)
1995 struct sh_frame_cache
*cache
= sh_frame_cache (next_frame
, this_cache
);
2000 static const struct frame_base sh_frame_base
= {
2002 sh_frame_base_address
,
2003 sh_frame_base_address
,
2004 sh_frame_base_address
2007 /* The epilogue is defined here as the area at the end of a function,
2008 either on the `ret' instruction itself or after an instruction which
2009 destroys the function's stack frame. */
2011 sh_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2013 CORE_ADDR func_addr
= 0, func_end
= 0;
2015 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
2018 /* The sh epilogue is max. 14 bytes long. Give another 14 bytes
2019 for a nop and some fixed data (e.g. big offsets) which are
2020 unfortunately also treated as part of the function (which
2021 means, they are below func_end. */
2022 CORE_ADDR addr
= func_end
- 28;
2023 if (addr
< func_addr
+ 4)
2024 addr
= func_addr
+ 4;
2028 /* First search forward until hitting an rts. */
2029 while (addr
< func_end
2030 && !IS_RTS (read_memory_unsigned_integer (addr
, 2)))
2032 if (addr
>= func_end
)
2035 /* At this point we should find a mov.l @r15+,r14 instruction,
2036 either before or after the rts. If not, then the function has
2037 probably no "normal" epilogue and we bail out here. */
2038 inst
= read_memory_unsigned_integer (addr
- 2, 2);
2039 if (IS_RESTORE_FP (read_memory_unsigned_integer (addr
- 2, 2)))
2041 else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr
+ 2, 2)))
2044 /* Step over possible lds.l @r15+,pr. */
2045 inst
= read_memory_unsigned_integer (addr
- 2, 2);
2049 inst
= read_memory_unsigned_integer (addr
- 2, 2);
2052 /* Step over possible mov r14,r15. */
2053 if (IS_MOV_FP_SP (inst
))
2056 inst
= read_memory_unsigned_integer (addr
- 2, 2);
2059 /* Now check for FP adjustments, using add #imm,r14 or add rX, r14
2061 while (addr
> func_addr
+ 4
2062 && (IS_ADD_REG_TO_FP (inst
) || IS_ADD_IMM_FP (inst
)))
2065 inst
= read_memory_unsigned_integer (addr
- 2, 2);
2074 static gdbarch_init_ftype sh_gdbarch_init
;
2076 static struct gdbarch
*
2077 sh_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2079 struct gdbarch
*gdbarch
;
2081 sh_show_regs
= sh_generic_show_regs
;
2082 switch (info
.bfd_arch_info
->mach
)
2085 sh_show_regs
= sh2e_show_regs
;
2087 case bfd_mach_sh_dsp
:
2088 sh_show_regs
= sh_dsp_show_regs
;
2092 sh_show_regs
= sh3_show_regs
;
2096 sh_show_regs
= sh3e_show_regs
;
2099 case bfd_mach_sh3_dsp
:
2100 sh_show_regs
= sh3_dsp_show_regs
;
2104 sh_show_regs
= sh4_show_regs
;
2108 sh_show_regs
= sh64_show_regs
;
2109 /* SH5 is handled entirely in sh64-tdep.c */
2110 return sh64_gdbarch_init (info
, arches
);
2113 /* If there is already a candidate, use it. */
2114 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2116 return arches
->gdbarch
;
2118 /* None found, create a new architecture from the information
2120 gdbarch
= gdbarch_alloc (&info
, NULL
);
2122 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
2123 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2124 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2125 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2126 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2127 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2128 set_gdbarch_long_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2129 set_gdbarch_ptr_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2131 set_gdbarch_num_regs (gdbarch
, SH_NUM_REGS
);
2132 set_gdbarch_sp_regnum (gdbarch
, 15);
2133 set_gdbarch_pc_regnum (gdbarch
, 16);
2134 set_gdbarch_fp0_regnum (gdbarch
, -1);
2135 set_gdbarch_num_pseudo_regs (gdbarch
, 0);
2137 set_gdbarch_register_type (gdbarch
, sh_default_register_type
);
2139 set_gdbarch_print_registers_info (gdbarch
, sh_print_registers_info
);
2141 set_gdbarch_breakpoint_from_pc (gdbarch
, sh_breakpoint_from_pc
);
2142 set_gdbarch_use_struct_convention (gdbarch
, sh_use_struct_convention
);
2144 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_sh
);
2145 set_gdbarch_register_sim_regno (gdbarch
, legacy_register_sim_regno
);
2147 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
2149 set_gdbarch_store_return_value (gdbarch
, sh_default_store_return_value
);
2150 set_gdbarch_extract_return_value (gdbarch
, sh_default_extract_return_value
);
2151 set_gdbarch_extract_struct_value_address (gdbarch
,
2152 sh_extract_struct_value_address
);
2154 set_gdbarch_skip_prologue (gdbarch
, sh_skip_prologue
);
2155 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2156 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
2157 set_gdbarch_function_start_offset (gdbarch
, 0);
2159 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_nofpu
);
2161 set_gdbarch_frame_args_skip (gdbarch
, 0);
2162 set_gdbarch_frameless_function_invocation (gdbarch
,
2163 frameless_look_for_prologue
);
2164 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
2166 set_gdbarch_frame_align (gdbarch
, sh_frame_align
);
2167 set_gdbarch_unwind_sp (gdbarch
, sh_unwind_sp
);
2168 set_gdbarch_unwind_pc (gdbarch
, sh_unwind_pc
);
2169 set_gdbarch_unwind_dummy_id (gdbarch
, sh_unwind_dummy_id
);
2170 frame_base_set_default (gdbarch
, &sh_frame_base
);
2172 set_gdbarch_in_function_epilogue_p (gdbarch
, sh_in_function_epilogue_p
);
2174 switch (info
.bfd_arch_info
->mach
)
2177 set_gdbarch_register_name (gdbarch
, sh_sh_register_name
);
2181 set_gdbarch_register_name (gdbarch
, sh_sh_register_name
);
2185 /* doubles on sh2e and sh3e are actually 4 byte. */
2186 set_gdbarch_double_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2188 set_gdbarch_register_name (gdbarch
, sh_sh2e_register_name
);
2189 set_gdbarch_register_type (gdbarch
, sh_sh3e_register_type
);
2190 set_gdbarch_fp0_regnum (gdbarch
, 25);
2191 set_gdbarch_store_return_value (gdbarch
, sh3e_sh4_store_return_value
);
2192 set_gdbarch_extract_return_value (gdbarch
,
2193 sh3e_sh4_extract_return_value
);
2194 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_fpu
);
2197 case bfd_mach_sh_dsp
:
2198 set_gdbarch_register_name (gdbarch
, sh_sh_dsp_register_name
);
2199 set_gdbarch_register_sim_regno (gdbarch
, sh_dsp_register_sim_regno
);
2203 set_gdbarch_register_name (gdbarch
, sh_sh3_register_name
);
2207 /* doubles on sh2e and sh3e are actually 4 byte. */
2208 set_gdbarch_double_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2210 set_gdbarch_register_name (gdbarch
, sh_sh3e_register_name
);
2211 set_gdbarch_register_type (gdbarch
, sh_sh3e_register_type
);
2212 set_gdbarch_fp0_regnum (gdbarch
, 25);
2213 set_gdbarch_store_return_value (gdbarch
, sh3e_sh4_store_return_value
);
2214 set_gdbarch_extract_return_value (gdbarch
,
2215 sh3e_sh4_extract_return_value
);
2216 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_fpu
);
2219 case bfd_mach_sh3_dsp
:
2220 set_gdbarch_register_name (gdbarch
, sh_sh3_dsp_register_name
);
2221 set_gdbarch_register_sim_regno (gdbarch
, sh_dsp_register_sim_regno
);
2225 set_gdbarch_register_name (gdbarch
, sh_sh4_register_name
);
2226 set_gdbarch_register_type (gdbarch
, sh_sh4_register_type
);
2227 set_gdbarch_fp0_regnum (gdbarch
, 25);
2228 set_gdbarch_num_pseudo_regs (gdbarch
, 12);
2229 set_gdbarch_pseudo_register_read (gdbarch
, sh_pseudo_register_read
);
2230 set_gdbarch_pseudo_register_write (gdbarch
, sh_pseudo_register_write
);
2231 set_gdbarch_store_return_value (gdbarch
, sh3e_sh4_store_return_value
);
2232 set_gdbarch_extract_return_value (gdbarch
,
2233 sh3e_sh4_extract_return_value
);
2234 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_fpu
);
2238 set_gdbarch_register_name (gdbarch
, sh_generic_register_name
);
2242 /* Hook in ABI-specific overrides, if they have been registered. */
2243 gdbarch_init_osabi (info
, gdbarch
);
2245 frame_unwind_append_sniffer (gdbarch
, dwarf2_frame_sniffer
);
2246 frame_unwind_append_sniffer (gdbarch
, sh_frame_sniffer
);
2251 extern initialize_file_ftype _initialize_sh_tdep
; /* -Wmissing-prototypes */
2254 _initialize_sh_tdep (void)
2256 struct cmd_list_element
*c
;
2258 gdbarch_register (bfd_arch_sh
, sh_gdbarch_init
, NULL
);
2260 add_com ("regs", class_vars
, sh_show_regs_command
, "Print all registers");