projects / deliverable / binutils-gdb.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
2003-10-09 Andrew Cagney <cagney@redhat.com>
[deliverable/binutils-gdb.git] / gdb / sh-tdep.c
1 /* Target-dependent code for Hitachi Super-H, for GDB.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22 /*
23 Contributed by Steve Chamberlain
24 sac@cygnus.com
25 */
26
27 #include "defs.h"
28 #include "frame.h"
29 #include "frame-base.h"
30 #include "frame-unwind.h"
31 #include "dwarf2-frame.h"
32 #include "symtab.h"
33 #include "symfile.h"
34 #include "gdbtypes.h"
35 #include "gdbcmd.h"
36 #include "gdbcore.h"
37 #include "value.h"
38 #include "dis-asm.h"
39 #include "inferior.h"
40 #include "gdb_string.h"
41 #include "gdb_assert.h"
42 #include "arch-utils.h"
43 #include "floatformat.h"
44 #include "regcache.h"
45 #include "doublest.h"
46 #include "osabi.h"
47
48 #include "sh-tdep.h"
49
50 #include "elf-bfd.h"
51 #include "solib-svr4.h"
52
53 /* sh flags */
54 #include "elf/sh.h"
55 /* registers numbers shared with the simulator */
56 #include "gdb/sim-sh.h"
57
58 static void (*sh_show_regs) (void);
59
60 #define SH_NUM_REGS 59
61
62 struct sh_frame_cache
63 {
64 /* Base address. */
65 CORE_ADDR base;
66 LONGEST sp_offset;
67 CORE_ADDR pc;
68
69 /* Flag showing that a frame has been created in the prologue code. */
70 int uses_fp;
71
72 /* Saved registers. */
73 CORE_ADDR saved_regs[SH_NUM_REGS];
74 CORE_ADDR saved_sp;
75 };
76
77 static const char *
78 sh_generic_register_name (int reg_nr)
79 {
80 static char *register_names[] = {
81 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
82 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
83 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
84 "fpul", "fpscr",
85 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
86 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
87 "ssr", "spc",
88 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
89 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
90 };
91 if (reg_nr < 0)
92 return NULL;
93 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
94 return NULL;
95 return register_names[reg_nr];
96 }
97
98 static const char *
99 sh_sh_register_name (int reg_nr)
100 {
101 static char *register_names[] = {
102 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
103 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
104 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
105 "", "",
106 "", "", "", "", "", "", "", "",
107 "", "", "", "", "", "", "", "",
108 "", "",
109 "", "", "", "", "", "", "", "",
110 "", "", "", "", "", "", "", "",
111 };
112 if (reg_nr < 0)
113 return NULL;
114 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
115 return NULL;
116 return register_names[reg_nr];
117 }
118
119 static const char *
120 sh_sh3_register_name (int reg_nr)
121 {
122 static char *register_names[] = {
123 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
124 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
125 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
126 "", "",
127 "", "", "", "", "", "", "", "",
128 "", "", "", "", "", "", "", "",
129 "ssr", "spc",
130 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
131 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
132 };
133 if (reg_nr < 0)
134 return NULL;
135 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
136 return NULL;
137 return register_names[reg_nr];
138 }
139
140 static const char *
141 sh_sh3e_register_name (int reg_nr)
142 {
143 static char *register_names[] = {
144 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
145 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
146 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
147 "fpul", "fpscr",
148 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
149 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
150 "ssr", "spc",
151 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
152 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
153 };
154 if (reg_nr < 0)
155 return NULL;
156 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
157 return NULL;
158 return register_names[reg_nr];
159 }
160
161 static const char *
162 sh_sh2e_register_name (int reg_nr)
163 {
164 static char *register_names[] = {
165 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
166 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
167 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
168 "fpul", "fpscr",
169 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
170 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
171 "", "",
172 "", "", "", "", "", "", "", "",
173 "", "", "", "", "", "", "", "",
174 };
175 if (reg_nr < 0)
176 return NULL;
177 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
178 return NULL;
179 return register_names[reg_nr];
180 }
181
182 static const char *
183 sh_sh_dsp_register_name (int reg_nr)
184 {
185 static char *register_names[] = {
186 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
187 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
188 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
189 "", "dsr",
190 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
191 "y0", "y1", "", "", "", "", "", "mod",
192 "", "",
193 "rs", "re", "", "", "", "", "", "",
194 "", "", "", "", "", "", "", "",
195 };
196 if (reg_nr < 0)
197 return NULL;
198 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
199 return NULL;
200 return register_names[reg_nr];
201 }
202
203 static const char *
204 sh_sh3_dsp_register_name (int reg_nr)
205 {
206 static char *register_names[] = {
207 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
208 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
209 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
210 "", "dsr",
211 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
212 "y0", "y1", "", "", "", "", "", "mod",
213 "ssr", "spc",
214 "rs", "re", "", "", "", "", "", "",
215 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b"
216 "", "", "", "", "", "", "", "",
217 };
218 if (reg_nr < 0)
219 return NULL;
220 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
221 return NULL;
222 return register_names[reg_nr];
223 }
224
225 static const char *
226 sh_sh4_register_name (int reg_nr)
227 {
228 static char *register_names[] = {
229 /* general registers 0-15 */
230 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
231 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
232 /* 16 - 22 */
233 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
234 /* 23, 24 */
235 "fpul", "fpscr",
236 /* floating point registers 25 - 40 */
237 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
238 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
239 /* 41, 42 */
240 "ssr", "spc",
241 /* bank 0 43 - 50 */
242 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
243 /* bank 1 51 - 58 */
244 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
245 /* double precision (pseudo) 59 - 66 */
246 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
247 /* vectors (pseudo) 67 - 70 */
248 "fv0", "fv4", "fv8", "fv12",
249 /* FIXME: missing XF 71 - 86 */
250 /* FIXME: missing XD 87 - 94 */
251 };
252 if (reg_nr < 0)
253 return NULL;
254 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
255 return NULL;
256 return register_names[reg_nr];
257 }
258
259 static const unsigned char *
260 sh_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
261 {
262 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
263 static unsigned char breakpoint[] = { 0xc3, 0xc3 };
264
265 *lenptr = sizeof (breakpoint);
266 return breakpoint;
267 }
268
269 /* Prologue looks like
270 mov.l r14,@-r15
271 sts.l pr,@-r15
272 mov.l <regs>,@-r15
273 sub <room_for_loca_vars>,r15
274 mov r15,r14
275
276 Actually it can be more complicated than this but that's it, basically.
277 */
278
279 #define GET_SOURCE_REG(x) (((x) >> 4) & 0xf)
280 #define GET_TARGET_REG(x) (((x) >> 8) & 0xf)
281
282 /* STS.L PR,@-r15 0100111100100010
283 r15-4-->r15, PR-->(r15) */
284 #define IS_STS(x) ((x) == 0x4f22)
285
286 /* MOV.L Rm,@-r15 00101111mmmm0110
287 r15-4-->r15, Rm-->(R15) */
288 #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
289
290 /* MOV r15,r14 0110111011110011
291 r15-->r14 */
292 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
293
294 /* ADD #imm,r15 01111111iiiiiiii
295 r15+imm-->r15 */
296 #define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00)
297
298 #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
299 #define IS_SHLL_R3(x) ((x) == 0x4300)
300
301 /* ADD r3,r15 0011111100111100
302 r15+r3-->r15 */
303 #define IS_ADD_R3SP(x) ((x) == 0x3f3c)
304
305 /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
306 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
307 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
308 /* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to
309 make this entirely clear. */
310 /* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */
311 #define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b)
312
313 /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */
314 #define IS_MOV_ARG_TO_REG(x) \
315 (((x) & 0xf00f) == 0x6003 && \
316 ((x) & 0x00f0) >= 0x0040 && \
317 ((x) & 0x00f0) <= 0x0070)
318 /* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */
319 #define IS_MOV_ARG_TO_IND_R14(x) \
320 (((x) & 0xff0f) == 0x2e02 && \
321 ((x) & 0x00f0) >= 0x0040 && \
322 ((x) & 0x00f0) <= 0x0070)
323 /* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */
324 #define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \
325 (((x) & 0xff00) == 0x1e00 && \
326 ((x) & 0x00f0) >= 0x0040 && \
327 ((x) & 0x00f0) <= 0x0070)
328
329 /* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */
330 #define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000)
331 /* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */
332 #define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000)
333 /* SUB Rn,R15 00111111nnnn1000 */
334 #define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08)
335
336 #define FPSCR_SZ (1 << 20)
337
338 /* The following instructions are used for epilogue testing. */
339 #define IS_RESTORE_FP(x) ((x) == 0x6ef6)
340 #define IS_RTS(x) ((x) == 0x000b)
341 #define IS_LDS(x) ((x) == 0x4f26)
342 #define IS_MOV_FP_SP(x) ((x) == 0x6fe3)
343 #define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c)
344 #define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00)
345
346 /* Disassemble an instruction. */
347 static int
348 gdb_print_insn_sh (bfd_vma memaddr, disassemble_info * info)
349 {
350 info->endian = TARGET_BYTE_ORDER;
351 return print_insn_sh (memaddr, info);
352 }
353
354 static CORE_ADDR
355 sh_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc,
356 struct sh_frame_cache *cache)
357 {
358 ULONGEST inst;
359 CORE_ADDR opc;
360 int offset;
361 int sav_offset = 0;
362 int r3_val = 0;
363 int reg, sav_reg = -1;
364
365 if (pc >= current_pc)
366 return current_pc;
367
368 cache->uses_fp = 0;
369 for (opc = pc + (2 * 28); pc < opc; pc += 2)
370 {
371 inst = read_memory_unsigned_integer (pc, 2);
372 /* See where the registers will be saved to */
373 if (IS_PUSH (inst))
374 {
375 cache->saved_regs[GET_SOURCE_REG (inst)] = cache->sp_offset;
376 cache->sp_offset += 4;
377 }
378 else if (IS_STS (inst))
379 {
380 cache->saved_regs[PR_REGNUM] = cache->sp_offset;
381 cache->sp_offset += 4;
382 }
383 else if (IS_MOV_R3 (inst))
384 {
385 r3_val = ((inst & 0xff) ^ 0x80) - 0x80;
386 }
387 else if (IS_SHLL_R3 (inst))
388 {
389 r3_val <<= 1;
390 }
391 else if (IS_ADD_R3SP (inst))
392 {
393 cache->sp_offset += -r3_val;
394 }
395 else if (IS_ADD_IMM_SP (inst))
396 {
397 offset = ((inst & 0xff) ^ 0x80) - 0x80;
398 cache->sp_offset -= offset;
399 }
400 else if (IS_MOVW_PCREL_TO_REG (inst))
401 {
402 if (sav_reg < 0)
403 {
404 reg = GET_TARGET_REG (inst);
405 if (reg < 14)
406 {
407 sav_reg = reg;
408 offset = (((inst & 0xff) ^ 0x80) - 0x80) << 1;
409 sav_offset =
410 read_memory_integer (((pc + 4) & ~3) + offset, 2);
411 }
412 }
413 }
414 else if (IS_MOVL_PCREL_TO_REG (inst))
415 {
416 if (sav_reg < 0)
417 {
418 reg = (inst & 0x0f00) >> 8;
419 if (reg < 14)
420 {
421 sav_reg = reg;
422 offset = (((inst & 0xff) ^ 0x80) - 0x80) << 1;
423 sav_offset =
424 read_memory_integer (((pc + 4) & ~3) + offset, 4);
425 }
426 }
427 }
428 else if (IS_SUB_REG_FROM_SP (inst))
429 {
430 reg = GET_SOURCE_REG (inst);
431 if (sav_reg > 0 && reg == sav_reg)
432 {
433 sav_reg = -1;
434 }
435 cache->sp_offset += sav_offset;
436 }
437 else if (IS_FPUSH (inst))
438 {
439 if (read_register (FPSCR_REGNUM) & FPSCR_SZ)
440 {
441 cache->sp_offset += 8;
442 }
443 else
444 {
445 cache->sp_offset += 4;
446 }
447 }
448 else if (IS_MOV_SP_FP (inst))
449 {
450 if (!cache->uses_fp)
451 cache->uses_fp = 1;
452 /* At this point, only allow argument register moves to other
453 registers or argument register moves to @(X,fp) which are
454 moving the register arguments onto the stack area allocated
455 by a former add somenumber to SP call. Don't allow moving
456 to an fp indirect address above fp + cache->sp_offset. */
457 pc += 2;
458 for (opc = pc + 12; pc < opc; pc += 2)
459 {
460 inst = read_memory_integer (pc, 2);
461 if (IS_MOV_ARG_TO_IND_R14 (inst))
462 {
463 reg = GET_SOURCE_REG (inst);
464 if (cache->sp_offset > 0)
465 cache->saved_regs[reg] = cache->sp_offset;
466 }
467 else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst))
468 {
469 reg = GET_SOURCE_REG (inst);
470 offset = (inst & 0xf) * 4;
471 if (cache->sp_offset > offset)
472 cache->saved_regs[reg] = cache->sp_offset - offset;
473 }
474 else if (IS_MOV_ARG_TO_REG (inst))
475 continue;
476 else
477 break;
478 }
479 break;
480 }
481 #if 0 /* This used to just stop when it found an instruction that
482 was not considered part of the prologue. Now, we just
483 keep going looking for likely instructions. */
484 else
485 break;
486 #endif
487 }
488
489 return pc;
490 }
491
492 /* Skip any prologue before the guts of a function */
493
494 /* Skip the prologue using the debug information. If this fails we'll
495 fall back on the 'guess' method below. */
496 static CORE_ADDR
497 after_prologue (CORE_ADDR pc)
498 {
499 struct symtab_and_line sal;
500 CORE_ADDR func_addr, func_end;
501
502 /* If we can not find the symbol in the partial symbol table, then
503 there is no hope we can determine the function's start address
504 with this code. */
505 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
506 return 0;
507
508 /* Get the line associated with FUNC_ADDR. */
509 sal = find_pc_line (func_addr, 0);
510
511 /* There are only two cases to consider. First, the end of the source line
512 is within the function bounds. In that case we return the end of the
513 source line. Second is the end of the source line extends beyond the
514 bounds of the current function. We need to use the slow code to
515 examine instructions in that case. */
516 if (sal.end < func_end)
517 return sal.end;
518 else
519 return 0;
520 }
521
522 static CORE_ADDR
523 sh_skip_prologue (CORE_ADDR start_pc)
524 {
525 CORE_ADDR pc;
526 struct sh_frame_cache cache;
527
528 /* See if we can determine the end of the prologue via the symbol table.
529 If so, then return either PC, or the PC after the prologue, whichever
530 is greater. */
531 pc = after_prologue (start_pc);
532
533 /* If after_prologue returned a useful address, then use it. Else
534 fall back on the instruction skipping code. */
535 if (pc)
536 return max (pc, start_pc);
537
538 cache.sp_offset = -4;
539 pc = sh_analyze_prologue (start_pc, (CORE_ADDR) -1, &cache);
540 if (!cache.uses_fp)
541 return start_pc;
542
543 return pc;
544 }
545
546 /* Should call_function allocate stack space for a struct return?
547
548 The ABI says:
549
550 Aggregate types not bigger than 8 bytes that have the same size and
551 alignment as one of the integer scalar types are returned in the
552 same registers as the integer type they match.
553
554 For example, a 2-byte aligned structure with size 2 bytes has the
555 same size and alignment as a short int, and will be returned in R0.
556 A 4-byte aligned structure with size 8 bytes has the same size and
557 alignment as a long long int, and will be returned in R0 and R1.
558
559 When an aggregate type is returned in R0 and R1, R0 contains the
560 first four bytes of the aggregate, and R1 contains the
561 remainder. If the size of the aggregate type is not a multiple of 4
562 bytes, the aggregate is tail-padded up to a multiple of 4
563 bytes. The value of the padding is undefined. For little-endian
564 targets the padding will appear at the most significant end of the
565 last element, for big-endian targets the padding appears at the
566 least significant end of the last element.
567
568 All other aggregate types are returned by address. The caller
569 function passes the address of an area large enough to hold the
570 aggregate value in R2. The called function stores the result in
571 this location."
572
573 To reiterate, structs smaller than 8 bytes could also be returned
574 in memory, if they don't pass the "same size and alignment as an
575 integer type" rule.
576
577 For example, in
578
579 struct s { char c[3]; } wibble;
580 struct s foo(void) { return wibble; }
581
582 the return value from foo() will be in memory, not
583 in R0, because there is no 3-byte integer type.
584
585 */
586
587 static int
588 sh_use_struct_convention (int gcc_p, struct type *type)
589 {
590 int len = TYPE_LENGTH (type);
591 int nelem = TYPE_NFIELDS (type);
592 return ((len != 1 && len != 2 && len != 4 && len != 8) || nelem != 1) &&
593 (len != 8 || TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) != 4);
594 }
595
596 /* Extract from an array REGBUF containing the (raw) register state
597 the address in which a function should return its structure value,
598 as a CORE_ADDR (or an expression that can be used as one). */
599 static CORE_ADDR
600 sh_extract_struct_value_address (struct regcache *regcache)
601 {
602 ULONGEST addr;
603
604 regcache_cooked_read_unsigned (regcache, STRUCT_RETURN_REGNUM, &addr);
605 return addr;
606 }
607
608 static CORE_ADDR
609 sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
610 {
611 return sp & ~3;
612 }
613
614 /* Function: push_dummy_call (formerly push_arguments)
615 Setup the function arguments for calling a function in the inferior.
616
617 On the Hitachi SH architecture, there are four registers (R4 to R7)
618 which are dedicated for passing function arguments. Up to the first
619 four arguments (depending on size) may go into these registers.
620 The rest go on the stack.
621
622 MVS: Except on SH variants that have floating point registers.
623 In that case, float and double arguments are passed in the same
624 manner, but using FP registers instead of GP registers.
625
626 Arguments that are smaller than 4 bytes will still take up a whole
627 register or a whole 32-bit word on the stack, and will be
628 right-justified in the register or the stack word. This includes
629 chars, shorts, and small aggregate types.
630
631 Arguments that are larger than 4 bytes may be split between two or
632 more registers. If there are not enough registers free, an argument
633 may be passed partly in a register (or registers), and partly on the
634 stack. This includes doubles, long longs, and larger aggregates.
635 As far as I know, there is no upper limit to the size of aggregates
636 that will be passed in this way; in other words, the convention of
637 passing a pointer to a large aggregate instead of a copy is not used.
638
639 MVS: The above appears to be true for the SH variants that do not
640 have an FPU, however those that have an FPU appear to copy the
641 aggregate argument onto the stack (and not place it in registers)
642 if it is larger than 16 bytes (four GP registers).
643
644 An exceptional case exists for struct arguments (and possibly other
645 aggregates such as arrays) if the size is larger than 4 bytes but
646 not a multiple of 4 bytes. In this case the argument is never split
647 between the registers and the stack, but instead is copied in its
648 entirety onto the stack, AND also copied into as many registers as
649 there is room for. In other words, space in registers permitting,
650 two copies of the same argument are passed in. As far as I can tell,
651 only the one on the stack is used, although that may be a function
652 of the level of compiler optimization. I suspect this is a compiler
653 bug. Arguments of these odd sizes are left-justified within the
654 word (as opposed to arguments smaller than 4 bytes, which are
655 right-justified).
656
657 If the function is to return an aggregate type such as a struct, it
658 is either returned in the normal return value register R0 (if its
659 size is no greater than one byte), or else the caller must allocate
660 space into which the callee will copy the return value (if the size
661 is greater than one byte). In this case, a pointer to the return
662 value location is passed into the callee in register R2, which does
663 not displace any of the other arguments passed in via registers R4
664 to R7. */
665
666 /* Helper function to justify value in register according to endianess. */
667 static char *
668 sh_justify_value_in_reg (struct value *val, int len)
669 {
670 static char valbuf[4];
671
672 memset (valbuf, 0, sizeof (valbuf));
673 if (len < 4)
674 {
675 /* value gets right-justified in the register or stack word */
676 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
677 memcpy (valbuf + (4 - len), (char *) VALUE_CONTENTS (val), len);
678 else
679 memcpy (valbuf, (char *) VALUE_CONTENTS (val), len);
680 return valbuf;
681 }
682 return (char *) VALUE_CONTENTS (val);
683 }
684
685 /* Helper function to eval number of bytes to allocate on stack. */
686 static CORE_ADDR
687 sh_stack_allocsize (int nargs, struct value **args)
688 {
689 int stack_alloc = 0;
690 while (nargs-- > 0)
691 stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[nargs])) + 3) & ~3);
692 return stack_alloc;
693 }
694
695 /* Helper functions for getting the float arguments right. Registers usage
696 depends on the ABI and the endianess. The comments should enlighten how
697 it's intended to work. */
698
699 /* This array stores which of the float arg registers are already in use. */
700 static int flt_argreg_array[FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM + 1];
701
702 /* This function just resets the above array to "no reg used so far". */
703 static void
704 sh_init_flt_argreg (void)
705 {
706 memset (flt_argreg_array, 0, sizeof flt_argreg_array);
707 }
708
709 /* This function returns the next register to use for float arg passing.
710 It returns either a valid value between FLOAT_ARG0_REGNUM and
711 FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns
712 FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available.
713
714 Note that register number 0 in flt_argreg_array corresponds with the
715 real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is
716 29) the parity of the register number is preserved, which is important
717 for the double register passing test (see the "argreg & 1" test below). */
718 static int
719 sh_next_flt_argreg (int len)
720 {
721 int argreg;
722
723 /* First search for the next free register. */
724 for (argreg = 0; argreg <= FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM;
725 ++argreg)
726 if (!flt_argreg_array[argreg])
727 break;
728
729 /* No register left? */
730 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
731 return FLOAT_ARGLAST_REGNUM + 1;
732
733 if (len == 8)
734 {
735 /* Doubles are always starting in a even register number. */
736 if (argreg & 1)
737 {
738 flt_argreg_array[argreg] = 1;
739
740 ++argreg;
741
742 /* No register left? */
743 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
744 return FLOAT_ARGLAST_REGNUM + 1;
745 }
746 /* Also mark the next register as used. */
747 flt_argreg_array[argreg + 1] = 1;
748 }
749 else if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
750 {
751 /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */
752 if (!flt_argreg_array[argreg + 1])
753 ++argreg;
754 }
755 flt_argreg_array[argreg] = 1;
756 return FLOAT_ARG0_REGNUM + argreg;
757 }
758
759 static CORE_ADDR
760 sh_push_dummy_call_fpu (struct gdbarch *gdbarch,
761 CORE_ADDR func_addr,
762 struct regcache *regcache,
763 CORE_ADDR bp_addr, int nargs,
764 struct value **args,
765 CORE_ADDR sp, int struct_return,
766 CORE_ADDR struct_addr)
767 {
768 int stack_offset = 0;
769 int argreg = ARG0_REGNUM;
770 int flt_argreg = 0;
771 int argnum;
772 struct type *type;
773 CORE_ADDR regval;
774 char *val;
775 int len, reg_size = 0;
776 int pass_on_stack;
777
778 /* first force sp to a 4-byte alignment */
779 sp = sh_frame_align (gdbarch, sp);
780
781 if (struct_return)
782 regcache_cooked_write_unsigned (regcache,
783 STRUCT_RETURN_REGNUM, struct_addr);
784
785 /* make room on stack for args */
786 sp -= sh_stack_allocsize (nargs, args);
787
788 /* Initialize float argument mechanism. */
789 sh_init_flt_argreg ();
790
791 /* Now load as many as possible of the first arguments into
792 registers, and push the rest onto the stack. There are 16 bytes
793 in four registers available. Loop thru args from first to last. */
794 for (argnum = 0; argnum < nargs; argnum++)
795 {
796 type = VALUE_TYPE (args[argnum]);
797 len = TYPE_LENGTH (type);
798 val = sh_justify_value_in_reg (args[argnum], len);
799
800 /* Some decisions have to be made how various types are handled.
801 This also differs in different ABIs. */
802 pass_on_stack = 0;
803 if (len > 16)
804 pass_on_stack = 1; /* Types bigger than 16 bytes are passed on stack. */
805
806 /* Find out the next register to use for a floating point value. */
807 if (TYPE_CODE (type) == TYPE_CODE_FLT)
808 flt_argreg = sh_next_flt_argreg (len);
809
810 while (len > 0)
811 {
812 if ((TYPE_CODE (type) == TYPE_CODE_FLT
813 && flt_argreg > FLOAT_ARGLAST_REGNUM)
814 || argreg > ARGLAST_REGNUM || pass_on_stack)
815 {
816 /* The remainder of the data goes entirely on the stack,
817 4-byte aligned. */
818 reg_size = (len + 3) & ~3;
819 write_memory (sp + stack_offset, val, reg_size);
820 stack_offset += reg_size;
821 }
822 else if (TYPE_CODE (type) == TYPE_CODE_FLT
823 && flt_argreg <= FLOAT_ARGLAST_REGNUM)
824 {
825 /* Argument goes in a float argument register. */
826 reg_size = register_size (gdbarch, flt_argreg);
827 regval = extract_unsigned_integer (val, reg_size);
828 regcache_cooked_write_unsigned (regcache, flt_argreg++, regval);
829 }
830 else if (argreg <= ARGLAST_REGNUM)
831 {
832 /* there's room in a register */
833 reg_size = register_size (gdbarch, argreg);
834 regval = extract_unsigned_integer (val, reg_size);
835 regcache_cooked_write_unsigned (regcache, argreg++, regval);
836 }
837 /* Store the value reg_size bytes at a time. This means that things
838 larger than reg_size bytes may go partly in registers and partly
839 on the stack. */
840 len -= reg_size;
841 val += reg_size;
842 }
843 }
844
845 /* Store return address. */
846 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
847
848 /* Update stack pointer. */
849 regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp);
850
851 return sp;
852 }
853
854 static CORE_ADDR
855 sh_push_dummy_call_nofpu (struct gdbarch *gdbarch,
856 CORE_ADDR func_addr,
857 struct regcache *regcache,
858 CORE_ADDR bp_addr,
859 int nargs, struct value **args,
860 CORE_ADDR sp, int struct_return,
861 CORE_ADDR struct_addr)
862 {
863 int stack_offset = 0;
864 int argreg = ARG0_REGNUM;
865 int argnum;
866 struct type *type;
867 CORE_ADDR regval;
868 char *val;
869 int len, reg_size;
870
871 /* first force sp to a 4-byte alignment */
872 sp = sh_frame_align (gdbarch, sp);
873
874 if (struct_return)
875 regcache_cooked_write_unsigned (regcache,
876 STRUCT_RETURN_REGNUM, struct_addr);
877
878 /* make room on stack for args */
879 sp -= sh_stack_allocsize (nargs, args);
880
881 /* Now load as many as possible of the first arguments into
882 registers, and push the rest onto the stack. There are 16 bytes
883 in four registers available. Loop thru args from first to last. */
884 for (argnum = 0; argnum < nargs; argnum++)
885 {
886 type = VALUE_TYPE (args[argnum]);
887 len = TYPE_LENGTH (type);
888 val = sh_justify_value_in_reg (args[argnum], len);
889
890 while (len > 0)
891 {
892 if (argreg > ARGLAST_REGNUM)
893 {
894 /* The remainder of the data goes entirely on the stack,
895 4-byte aligned. */
896 reg_size = (len + 3) & ~3;
897 write_memory (sp + stack_offset, val, reg_size);
898 stack_offset += reg_size;
899 }
900 else if (argreg <= ARGLAST_REGNUM)
901 {
902 /* there's room in a register */
903 reg_size = register_size (gdbarch, argreg);
904 regval = extract_unsigned_integer (val, reg_size);
905 regcache_cooked_write_unsigned (regcache, argreg++, regval);
906 }
907 /* Store the value reg_size bytes at a time. This means that things
908 larger than reg_size bytes may go partly in registers and partly
909 on the stack. */
910 len -= reg_size;
911 val += reg_size;
912 }
913 }
914
915 /* Store return address. */
916 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
917
918 /* Update stack pointer. */
919 regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp);
920
921 return sp;
922 }
923
924 /* Find a function's return value in the appropriate registers (in
925 regbuf), and copy it into valbuf. Extract from an array REGBUF
926 containing the (raw) register state a function return value of type
927 TYPE, and copy that, in virtual format, into VALBUF. */
928 static void
929 sh_default_extract_return_value (struct type *type, struct regcache *regcache,
930 void *valbuf)
931 {
932 int len = TYPE_LENGTH (type);
933 int return_register = R0_REGNUM;
934 int offset;
935
936 if (len <= 4)
937 {
938 ULONGEST c;
939
940 regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c);
941 store_unsigned_integer (valbuf, len, c);
942 }
943 else if (len == 8)
944 {
945 int i, regnum = R0_REGNUM;
946 for (i = 0; i < len; i += 4)
947 regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
948 }
949 else
950 error ("bad size for return value");
951 }
952
953 static void
954 sh3e_sh4_extract_return_value (struct type *type, struct regcache *regcache,
955 void *valbuf)
956 {
957 if (TYPE_CODE (type) == TYPE_CODE_FLT)
958 {
959 int len = TYPE_LENGTH (type);
960 int i, regnum = FP0_REGNUM;
961 for (i = 0; i < len; i += 4)
962 regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
963 }
964 else
965 sh_default_extract_return_value (type, regcache, valbuf);
966 }
967
968 /* Write into appropriate registers a function return value
969 of type TYPE, given in virtual format.
970 If the architecture is sh4 or sh3e, store a function's return value
971 in the R0 general register or in the FP0 floating point register,
972 depending on the type of the return value. In all the other cases
973 the result is stored in r0, left-justified. */
974 static void
975 sh_default_store_return_value (struct type *type, struct regcache *regcache,
976 const void *valbuf)
977 {
978 ULONGEST val;
979 int len = TYPE_LENGTH (type);
980
981 if (len <= 4)
982 {
983 val = extract_unsigned_integer (valbuf, len);
984 regcache_cooked_write_unsigned (regcache, R0_REGNUM, val);
985 }
986 else
987 {
988 int i, regnum = R0_REGNUM;
989 for (i = 0; i < len; i += 4)
990 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
991 }
992 }
993
994 static void
995 sh3e_sh4_store_return_value (struct type *type, struct regcache *regcache,
996 const void *valbuf)
997 {
998 if (TYPE_CODE (type) == TYPE_CODE_FLT)
999 {
1000 int len = TYPE_LENGTH (type);
1001 int i, regnum = FP0_REGNUM;
1002 for (i = 0; i < len; i += 4)
1003 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
1004 }
1005 else
1006 sh_default_store_return_value (type, regcache, valbuf);
1007 }
1008
1009 /* Print the registers in a form similar to the E7000 */
1010
1011 static void
1012 sh_generic_show_regs (void)
1013 {
1014 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1015 paddr (read_register (PC_REGNUM)),
1016 (long) read_register (SR_REGNUM),
1017 (long) read_register (PR_REGNUM),
1018 (long) read_register (MACH_REGNUM),
1019 (long) read_register (MACL_REGNUM));
1020
1021 printf_filtered ("GBR=%08lx VBR=%08lx",
1022 (long) read_register (GBR_REGNUM),
1023 (long) read_register (VBR_REGNUM));
1024
1025 printf_filtered
1026 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1027 (long) read_register (0), (long) read_register (1),
1028 (long) read_register (2), (long) read_register (3),
1029 (long) read_register (4), (long) read_register (5),
1030 (long) read_register (6), (long) read_register (7));
1031 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1032 (long) read_register (8), (long) read_register (9),
1033 (long) read_register (10), (long) read_register (11),
1034 (long) read_register (12), (long) read_register (13),
1035 (long) read_register (14), (long) read_register (15));
1036 }
1037
1038 static void
1039 sh3_show_regs (void)
1040 {
1041 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1042 paddr (read_register (PC_REGNUM)),
1043 (long) read_register (SR_REGNUM),
1044 (long) read_register (PR_REGNUM),
1045 (long) read_register (MACH_REGNUM),
1046 (long) read_register (MACL_REGNUM));
1047
1048 printf_filtered ("GBR=%08lx VBR=%08lx",
1049 (long) read_register (GBR_REGNUM),
1050 (long) read_register (VBR_REGNUM));
1051 printf_filtered (" SSR=%08lx SPC=%08lx",
1052 (long) read_register (SSR_REGNUM),
1053 (long) read_register (SPC_REGNUM));
1054
1055 printf_filtered
1056 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1057 (long) read_register (0), (long) read_register (1),
1058 (long) read_register (2), (long) read_register (3),
1059 (long) read_register (4), (long) read_register (5),
1060 (long) read_register (6), (long) read_register (7));
1061 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1062 (long) read_register (8), (long) read_register (9),
1063 (long) read_register (10), (long) read_register (11),
1064 (long) read_register (12), (long) read_register (13),
1065 (long) read_register (14), (long) read_register (15));
1066 }
1067
1068
1069 static void
1070 sh2e_show_regs (void)
1071 {
1072 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1073 paddr (read_register (PC_REGNUM)),
1074 (long) read_register (SR_REGNUM),
1075 (long) read_register (PR_REGNUM),
1076 (long) read_register (MACH_REGNUM),
1077 (long) read_register (MACL_REGNUM));
1078
1079 printf_filtered ("GBR=%08lx VBR=%08lx",
1080 (long) read_register (GBR_REGNUM),
1081 (long) read_register (VBR_REGNUM));
1082 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1083 (long) read_register (FPUL_REGNUM),
1084 (long) read_register (FPSCR_REGNUM));
1085
1086 printf_filtered
1087 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1088 (long) read_register (0), (long) read_register (1),
1089 (long) read_register (2), (long) read_register (3),
1090 (long) read_register (4), (long) read_register (5),
1091 (long) read_register (6), (long) read_register (7));
1092 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1093 (long) read_register (8), (long) read_register (9),
1094 (long) read_register (10), (long) read_register (11),
1095 (long) read_register (12), (long) read_register (13),
1096 (long) read_register (14), (long) read_register (15));
1097
1098 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 0), (long) read_register (FP0_REGNUM + 1), (long) read_register (FP0_REGNUM + 2), (long) read_register (FP0_REGNUM + 3), (long) read_register (FP0_REGNUM + 4), (long) read_register (FP0_REGNUM + 5), (long) read_register (FP0_REGNUM + 6), (long) read_register (FP0_REGNUM + 7));
1099 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 8), (long) read_register (FP0_REGNUM + 9), (long) read_register (FP0_REGNUM + 10), (long) read_register (FP0_REGNUM + 11), (long) read_register (FP0_REGNUM + 12), (long) read_register (FP0_REGNUM + 13), (long) read_register (FP0_REGNUM + 14), (long) read_register (FP0_REGNUM + 15));
1100 }
1101
1102 static void
1103 sh3e_show_regs (void)
1104 {
1105 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1106 paddr (read_register (PC_REGNUM)),
1107 (long) read_register (SR_REGNUM),
1108 (long) read_register (PR_REGNUM),
1109 (long) read_register (MACH_REGNUM),
1110 (long) read_register (MACL_REGNUM));
1111
1112 printf_filtered ("GBR=%08lx VBR=%08lx",
1113 (long) read_register (GBR_REGNUM),
1114 (long) read_register (VBR_REGNUM));
1115 printf_filtered (" SSR=%08lx SPC=%08lx",
1116 (long) read_register (SSR_REGNUM),
1117 (long) read_register (SPC_REGNUM));
1118 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1119 (long) read_register (FPUL_REGNUM),
1120 (long) read_register (FPSCR_REGNUM));
1121
1122 printf_filtered
1123 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1124 (long) read_register (0), (long) read_register (1),
1125 (long) read_register (2), (long) read_register (3),
1126 (long) read_register (4), (long) read_register (5),
1127 (long) read_register (6), (long) read_register (7));
1128 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1129 (long) read_register (8), (long) read_register (9),
1130 (long) read_register (10), (long) read_register (11),
1131 (long) read_register (12), (long) read_register (13),
1132 (long) read_register (14), (long) read_register (15));
1133
1134 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 0), (long) read_register (FP0_REGNUM + 1), (long) read_register (FP0_REGNUM + 2), (long) read_register (FP0_REGNUM + 3), (long) read_register (FP0_REGNUM + 4), (long) read_register (FP0_REGNUM + 5), (long) read_register (FP0_REGNUM + 6), (long) read_register (FP0_REGNUM + 7));
1135 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 8), (long) read_register (FP0_REGNUM + 9), (long) read_register (FP0_REGNUM + 10), (long) read_register (FP0_REGNUM + 11), (long) read_register (FP0_REGNUM + 12), (long) read_register (FP0_REGNUM + 13), (long) read_register (FP0_REGNUM + 14), (long) read_register (FP0_REGNUM + 15));
1136 }
1137
1138 static void
1139 sh3_dsp_show_regs (void)
1140 {
1141 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1142 paddr (read_register (PC_REGNUM)),
1143 (long) read_register (SR_REGNUM),
1144 (long) read_register (PR_REGNUM),
1145 (long) read_register (MACH_REGNUM),
1146 (long) read_register (MACL_REGNUM));
1147
1148 printf_filtered ("GBR=%08lx VBR=%08lx",
1149 (long) read_register (GBR_REGNUM),
1150 (long) read_register (VBR_REGNUM));
1151
1152 printf_filtered (" SSR=%08lx SPC=%08lx",
1153 (long) read_register (SSR_REGNUM),
1154 (long) read_register (SPC_REGNUM));
1155
1156 printf_filtered (" DSR=%08lx", (long) read_register (DSR_REGNUM));
1157
1158 printf_filtered
1159 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1160 (long) read_register (0), (long) read_register (1),
1161 (long) read_register (2), (long) read_register (3),
1162 (long) read_register (4), (long) read_register (5),
1163 (long) read_register (6), (long) read_register (7));
1164 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1165 (long) read_register (8), (long) read_register (9),
1166 (long) read_register (10), (long) read_register (11),
1167 (long) read_register (12), (long) read_register (13),
1168 (long) read_register (14), (long) read_register (15));
1169
1170 printf_filtered
1171 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1172 (long) read_register (A0G_REGNUM) & 0xff,
1173 (long) read_register (A0_REGNUM), (long) read_register (M0_REGNUM),
1174 (long) read_register (X0_REGNUM), (long) read_register (Y0_REGNUM),
1175 (long) read_register (RS_REGNUM), (long) read_register (MOD_REGNUM));
1176 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1177 (long) read_register (A1G_REGNUM) & 0xff,
1178 (long) read_register (A1_REGNUM),
1179 (long) read_register (M1_REGNUM),
1180 (long) read_register (X1_REGNUM),
1181 (long) read_register (Y1_REGNUM),
1182 (long) read_register (RE_REGNUM));
1183 }
1184
1185 static void
1186 sh4_show_regs (void)
1187 {
1188 int pr = read_register (FPSCR_REGNUM) & 0x80000;
1189 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1190 paddr (read_register (PC_REGNUM)),
1191 (long) read_register (SR_REGNUM),
1192 (long) read_register (PR_REGNUM),
1193 (long) read_register (MACH_REGNUM),
1194 (long) read_register (MACL_REGNUM));
1195
1196 printf_filtered ("GBR=%08lx VBR=%08lx",
1197 (long) read_register (GBR_REGNUM),
1198 (long) read_register (VBR_REGNUM));
1199 printf_filtered (" SSR=%08lx SPC=%08lx",
1200 (long) read_register (SSR_REGNUM),
1201 (long) read_register (SPC_REGNUM));
1202 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1203 (long) read_register (FPUL_REGNUM),
1204 (long) read_register (FPSCR_REGNUM));
1205
1206 printf_filtered
1207 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1208 (long) read_register (0), (long) read_register (1),
1209 (long) read_register (2), (long) read_register (3),
1210 (long) read_register (4), (long) read_register (5),
1211 (long) read_register (6), (long) read_register (7));
1212 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1213 (long) read_register (8), (long) read_register (9),
1214 (long) read_register (10), (long) read_register (11),
1215 (long) read_register (12), (long) read_register (13),
1216 (long) read_register (14), (long) read_register (15));
1217
1218 printf_filtered ((pr
1219 ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1220 :
1221 "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1222 (long) read_register (FP0_REGNUM + 0),
1223 (long) read_register (FP0_REGNUM + 1),
1224 (long) read_register (FP0_REGNUM + 2),
1225 (long) read_register (FP0_REGNUM + 3),
1226 (long) read_register (FP0_REGNUM + 4),
1227 (long) read_register (FP0_REGNUM + 5),
1228 (long) read_register (FP0_REGNUM + 6),
1229 (long) read_register (FP0_REGNUM + 7));
1230 printf_filtered ((pr ?
1231 "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" :
1232 "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1233 (long) read_register (FP0_REGNUM + 8),
1234 (long) read_register (FP0_REGNUM + 9),
1235 (long) read_register (FP0_REGNUM + 10),
1236 (long) read_register (FP0_REGNUM + 11),
1237 (long) read_register (FP0_REGNUM + 12),
1238 (long) read_register (FP0_REGNUM + 13),
1239 (long) read_register (FP0_REGNUM + 14),
1240 (long) read_register (FP0_REGNUM + 15));
1241 }
1242
1243 static void
1244 sh_dsp_show_regs (void)
1245 {
1246 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1247 paddr (read_register (PC_REGNUM)),
1248 (long) read_register (SR_REGNUM),
1249 (long) read_register (PR_REGNUM),
1250 (long) read_register (MACH_REGNUM),
1251 (long) read_register (MACL_REGNUM));
1252
1253 printf_filtered ("GBR=%08lx VBR=%08lx",
1254 (long) read_register (GBR_REGNUM),
1255 (long) read_register (VBR_REGNUM));
1256
1257 printf_filtered (" DSR=%08lx", (long) read_register (DSR_REGNUM));
1258
1259 printf_filtered
1260 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1261 (long) read_register (0), (long) read_register (1),
1262 (long) read_register (2), (long) read_register (3),
1263 (long) read_register (4), (long) read_register (5),
1264 (long) read_register (6), (long) read_register (7));
1265 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1266 (long) read_register (8), (long) read_register (9),
1267 (long) read_register (10), (long) read_register (11),
1268 (long) read_register (12), (long) read_register (13),
1269 (long) read_register (14), (long) read_register (15));
1270
1271 printf_filtered
1272 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1273 (long) read_register (A0G_REGNUM) & 0xff,
1274 (long) read_register (A0_REGNUM), (long) read_register (M0_REGNUM),
1275 (long) read_register (X0_REGNUM), (long) read_register (Y0_REGNUM),
1276 (long) read_register (RS_REGNUM), (long) read_register (MOD_REGNUM));
1277 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1278 (long) read_register (A1G_REGNUM) & 0xff,
1279 (long) read_register (A1_REGNUM),
1280 (long) read_register (M1_REGNUM),
1281 (long) read_register (X1_REGNUM),
1282 (long) read_register (Y1_REGNUM),
1283 (long) read_register (RE_REGNUM));
1284 }
1285
1286 static void
1287 sh_show_regs_command (char *args, int from_tty)
1288 {
1289 if (sh_show_regs)
1290 (*sh_show_regs) ();
1291 }
1292
1293 /* Return the GDB type object for the "standard" data type
1294 of data in register N. */
1295 static struct type *
1296 sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr)
1297 {
1298 if ((reg_nr >= FP0_REGNUM
1299 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
1300 return builtin_type_float;
1301 else
1302 return builtin_type_int;
1303 }
1304
1305 static struct type *
1306 sh_sh4_build_float_register_type (int high)
1307 {
1308 struct type *temp;
1309
1310 temp = create_range_type (NULL, builtin_type_int, 0, high);
1311 return create_array_type (NULL, builtin_type_float, temp);
1312 }
1313
1314 static struct type *
1315 sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr)
1316 {
1317 if ((reg_nr >= FP0_REGNUM
1318 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
1319 return builtin_type_float;
1320 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
1321 return builtin_type_double;
1322 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
1323 return sh_sh4_build_float_register_type (3);
1324 else
1325 return builtin_type_int;
1326 }
1327
1328 static struct type *
1329 sh_default_register_type (struct gdbarch *gdbarch, int reg_nr)
1330 {
1331 return builtin_type_int;
1332 }
1333
1334 /* On the sh4, the DRi pseudo registers are problematic if the target
1335 is little endian. When the user writes one of those registers, for
1336 instance with 'ser var $dr0=1', we want the double to be stored
1337 like this:
1338 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1339 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1340
1341 This corresponds to little endian byte order & big endian word
1342 order. However if we let gdb write the register w/o conversion, it
1343 will write fr0 and fr1 this way:
1344 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1345 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1346 because it will consider fr0 and fr1 as a single LE stretch of memory.
1347
1348 To achieve what we want we must force gdb to store things in
1349 floatformat_ieee_double_littlebyte_bigword (which is defined in
1350 include/floatformat.h and libiberty/floatformat.c.
1351
1352 In case the target is big endian, there is no problem, the
1353 raw bytes will look like:
1354 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
1355 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1356
1357 The other pseudo registers (the FVs) also don't pose a problem
1358 because they are stored as 4 individual FP elements. */
1359
1360 static void
1361 sh_sh4_register_convert_to_virtual (int regnum, struct type *type,
1362 char *from, char *to)
1363 {
1364 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
1365 {
1366 DOUBLEST val;
1367 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
1368 from, &val);
1369 store_typed_floating (to, type, val);
1370 }
1371 else
1372 error
1373 ("sh_register_convert_to_virtual called with non DR register number");
1374 }
1375
1376 static void
1377 sh_sh4_register_convert_to_raw (struct type *type, int regnum,
1378 const void *from, void *to)
1379 {
1380 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
1381 {
1382 DOUBLEST val = extract_typed_floating (from, type);
1383 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword,
1384 &val, to);
1385 }
1386 else
1387 error ("sh_register_convert_to_raw called with non DR register number");
1388 }
1389
1390 /* For vectors of 4 floating point registers. */
1391 static int
1392 fv_reg_base_num (int fv_regnum)
1393 {
1394 int fp_regnum;
1395
1396 fp_regnum = FP0_REGNUM + (fv_regnum - FV0_REGNUM) * 4;
1397 return fp_regnum;
1398 }
1399
1400 /* For double precision floating point registers, i.e 2 fp regs.*/
1401 static int
1402 dr_reg_base_num (int dr_regnum)
1403 {
1404 int fp_regnum;
1405
1406 fp_regnum = FP0_REGNUM + (dr_regnum - DR0_REGNUM) * 2;
1407 return fp_regnum;
1408 }
1409
1410 static void
1411 sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
1412 int reg_nr, void *buffer)
1413 {
1414 int base_regnum, portion;
1415 char temp_buffer[MAX_REGISTER_SIZE];
1416
1417 if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
1418 {
1419 base_regnum = dr_reg_base_num (reg_nr);
1420
1421 /* Build the value in the provided buffer. */
1422 /* Read the real regs for which this one is an alias. */
1423 for (portion = 0; portion < 2; portion++)
1424 regcache_raw_read (regcache, base_regnum + portion,
1425 (temp_buffer
1426 + register_size (gdbarch,
1427 base_regnum) * portion));
1428 /* We must pay attention to the endiannes. */
1429 sh_sh4_register_convert_to_virtual (reg_nr,
1430 gdbarch_register_type (gdbarch,
1431 reg_nr),
1432 temp_buffer, buffer);
1433 }
1434 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
1435 {
1436 base_regnum = fv_reg_base_num (reg_nr);
1437
1438 /* Read the real regs for which this one is an alias. */
1439 for (portion = 0; portion < 4; portion++)
1440 regcache_raw_read (regcache, base_regnum + portion,
1441 ((char *) buffer
1442 + register_size (gdbarch,
1443 base_regnum) * portion));
1444 }
1445 }
1446
1447 static void
1448 sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
1449 int reg_nr, const void *buffer)
1450 {
1451 int base_regnum, portion;
1452 char temp_buffer[MAX_REGISTER_SIZE];
1453
1454 if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
1455 {
1456 base_regnum = dr_reg_base_num (reg_nr);
1457
1458 /* We must pay attention to the endiannes. */
1459 sh_sh4_register_convert_to_raw (gdbarch_register_type (gdbarch, reg_nr),
1460 reg_nr, buffer, temp_buffer);
1461
1462 /* Write the real regs for which this one is an alias. */
1463 for (portion = 0; portion < 2; portion++)
1464 regcache_raw_write (regcache, base_regnum + portion,
1465 (temp_buffer
1466 + register_size (gdbarch,
1467 base_regnum) * portion));
1468 }
1469 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
1470 {
1471 base_regnum = fv_reg_base_num (reg_nr);
1472
1473 /* Write the real regs for which this one is an alias. */
1474 for (portion = 0; portion < 4; portion++)
1475 regcache_raw_write (regcache, base_regnum + portion,
1476 ((char *) buffer
1477 + register_size (gdbarch,
1478 base_regnum) * portion));
1479 }
1480 }
1481
1482 /* Floating point vector of 4 float registers. */
1483 static void
1484 do_fv_register_info (struct gdbarch *gdbarch, struct ui_file *file,
1485 int fv_regnum)
1486 {
1487 int first_fp_reg_num = fv_reg_base_num (fv_regnum);
1488 fprintf_filtered (file, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
1489 fv_regnum - FV0_REGNUM,
1490 (int) read_register (first_fp_reg_num),
1491 (int) read_register (first_fp_reg_num + 1),
1492 (int) read_register (first_fp_reg_num + 2),
1493 (int) read_register (first_fp_reg_num + 3));
1494 }
1495
1496 /* Double precision registers. */
1497 static void
1498 do_dr_register_info (struct gdbarch *gdbarch, struct ui_file *file,
1499 int dr_regnum)
1500 {
1501 int first_fp_reg_num = dr_reg_base_num (dr_regnum);
1502
1503 fprintf_filtered (file, "dr%d\t0x%08x%08x\n",
1504 dr_regnum - DR0_REGNUM,
1505 (int) read_register (first_fp_reg_num),
1506 (int) read_register (first_fp_reg_num + 1));
1507 }
1508
1509 static void
1510 sh_print_pseudo_register (struct gdbarch *gdbarch, struct ui_file *file,
1511 int regnum)
1512 {
1513 if (regnum < NUM_REGS || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
1514 internal_error (__FILE__, __LINE__,
1515 "Invalid pseudo register number %d\n", regnum);
1516 else if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
1517 do_dr_register_info (gdbarch, file, regnum);
1518 else if (regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM)
1519 do_fv_register_info (gdbarch, file, regnum);
1520 }
1521
1522 static void
1523 sh_do_fp_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
1524 { /* do values for FP (float) regs */
1525 char *raw_buffer;
1526 double flt; /* double extracted from raw hex data */
1527 int inv;
1528 int j;
1529
1530 /* Allocate space for the float. */
1531 raw_buffer = (char *) alloca (register_size (gdbarch, FP0_REGNUM));
1532
1533 /* Get the data in raw format. */
1534 if (!frame_register_read (get_selected_frame (), regnum, raw_buffer))
1535 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
1536
1537 /* Get the register as a number */
1538 flt = unpack_double (builtin_type_float, raw_buffer, &inv);
1539
1540 /* Print the name and some spaces. */
1541 fputs_filtered (REGISTER_NAME (regnum), file);
1542 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
1543
1544 /* Print the value. */
1545 if (inv)
1546 fprintf_filtered (file, "<invalid float>");
1547 else
1548 fprintf_filtered (file, "%-10.9g", flt);
1549
1550 /* Print the fp register as hex. */
1551 fprintf_filtered (file, "\t(raw 0x");
1552 for (j = 0; j < register_size (gdbarch, regnum); j++)
1553 {
1554 int idx = (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
1555 ? j
1556 : register_size (gdbarch, regnum) - 1 - j);
1557 fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[idx]);
1558 }
1559 fprintf_filtered (file, ")");
1560 fprintf_filtered (file, "\n");
1561 }
1562
1563 static void
1564 sh_do_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
1565 {
1566 char raw_buffer[MAX_REGISTER_SIZE];
1567
1568 fputs_filtered (REGISTER_NAME (regnum), file);
1569 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
1570
1571 /* Get the data in raw format. */
1572 if (!frame_register_read (get_selected_frame (), regnum, raw_buffer))
1573 fprintf_filtered (file, "*value not available*\n");
1574
1575 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
1576 file, 'x', 1, 0, Val_pretty_default);
1577 fprintf_filtered (file, "\t");
1578 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
1579 file, 0, 1, 0, Val_pretty_default);
1580 fprintf_filtered (file, "\n");
1581 }
1582
1583 static void
1584 sh_print_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
1585 {
1586 if (regnum < 0 || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
1587 internal_error (__FILE__, __LINE__,
1588 "Invalid register number %d\n", regnum);
1589
1590 else if (regnum >= 0 && regnum < NUM_REGS)
1591 {
1592 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) ==
1593 TYPE_CODE_FLT)
1594 sh_do_fp_register (gdbarch, file, regnum); /* FP regs */
1595 else
1596 sh_do_register (gdbarch, file, regnum); /* All other regs */
1597 }
1598
1599 else if (regnum < NUM_REGS + NUM_PSEUDO_REGS)
1600 {
1601 sh_print_pseudo_register (gdbarch, file, regnum);
1602 }
1603 }
1604
1605 static void
1606 sh_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
1607 struct frame_info *frame, int regnum, int fpregs)
1608 {
1609 if (regnum != -1) /* do one specified register */
1610 {
1611 if (*(REGISTER_NAME (regnum)) == '\0')
1612 error ("Not a valid register for the current processor type");
1613
1614 sh_print_register (gdbarch, file, regnum);
1615 }
1616 else
1617 /* do all (or most) registers */
1618 {
1619 regnum = 0;
1620 while (regnum < NUM_REGS)
1621 {
1622 /* If the register name is empty, it is undefined for this
1623 processor, so don't display anything. */
1624 if (REGISTER_NAME (regnum) == NULL
1625 || *(REGISTER_NAME (regnum)) == '\0')
1626 {
1627 regnum++;
1628 continue;
1629 }
1630
1631 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) ==
1632 TYPE_CODE_FLT)
1633 {
1634 if (fpregs)
1635 {
1636 /* true for "INFO ALL-REGISTERS" command */
1637 sh_do_fp_register (gdbarch, file, regnum); /* FP regs */
1638 regnum++;
1639 }
1640 else
1641 regnum += (FP_LAST_REGNUM - FP0_REGNUM); /* skip FP regs */
1642 }
1643 else
1644 {
1645 sh_do_register (gdbarch, file, regnum); /* All other regs */
1646 regnum++;
1647 }
1648 }
1649
1650 if (fpregs)
1651 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
1652 {
1653 sh_print_pseudo_register (gdbarch, file, regnum);
1654 regnum++;
1655 }
1656 }
1657 }
1658
1659 #ifdef SVR4_SHARED_LIBS
1660
1661 /* Fetch (and possibly build) an appropriate link_map_offsets structure
1662 for native i386 linux targets using the struct offsets defined in
1663 link.h (but without actual reference to that file).
1664
1665 This makes it possible to access i386-linux shared libraries from
1666 a gdb that was not built on an i386-linux host (for cross debugging).
1667 */
1668
1669 struct link_map_offsets *
1670 sh_linux_svr4_fetch_link_map_offsets (void)
1671 {
1672 static struct link_map_offsets lmo;
1673 static struct link_map_offsets *lmp = 0;
1674
1675 if (lmp == 0)
1676 {
1677 lmp = &lmo;
1678
1679 lmo.r_debug_size = 8; /* 20 not actual size but all we need */
1680
1681 lmo.r_map_offset = 4;
1682 lmo.r_map_size = 4;
1683
1684 lmo.link_map_size = 20; /* 552 not actual size but all we need */
1685
1686 lmo.l_addr_offset = 0;
1687 lmo.l_addr_size = 4;
1688
1689 lmo.l_name_offset = 4;
1690 lmo.l_name_size = 4;
1691
1692 lmo.l_next_offset = 12;
1693 lmo.l_next_size = 4;
1694
1695 lmo.l_prev_offset = 16;
1696 lmo.l_prev_size = 4;
1697 }
1698
1699 return lmp;
1700 }
1701 #endif /* SVR4_SHARED_LIBS */
1702
1703 static int
1704 sh_dsp_register_sim_regno (int nr)
1705 {
1706 if (legacy_register_sim_regno (nr) < 0)
1707 return legacy_register_sim_regno (nr);
1708 if (nr >= DSR_REGNUM && nr <= Y1_REGNUM)
1709 return nr - DSR_REGNUM + SIM_SH_DSR_REGNUM;
1710 if (nr == MOD_REGNUM)
1711 return SIM_SH_MOD_REGNUM;
1712 if (nr == RS_REGNUM)
1713 return SIM_SH_RS_REGNUM;
1714 if (nr == RE_REGNUM)
1715 return SIM_SH_RE_REGNUM;
1716 if (nr >= R0_BANK_REGNUM && nr <= R7_BANK_REGNUM)
1717 return nr - R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM;
1718 return nr;
1719 }
1720
1721 static struct sh_frame_cache *
1722 sh_alloc_frame_cache (void)
1723 {
1724 struct sh_frame_cache *cache;
1725 int i;
1726
1727 cache = FRAME_OBSTACK_ZALLOC (struct sh_frame_cache);
1728
1729 /* Base address. */
1730 cache->base = 0;
1731 cache->saved_sp = 0;
1732 cache->sp_offset = 0;
1733 cache->pc = 0;
1734
1735 /* Frameless until proven otherwise. */
1736 cache->uses_fp = 0;
1737
1738 /* Saved registers. We initialize these to -1 since zero is a valid
1739 offset (that's where fp is supposed to be stored). */
1740 for (i = 0; i < SH_NUM_REGS; i++)
1741 {
1742 cache->saved_regs[i] = -1;
1743 }
1744
1745 return cache;
1746 }
1747
1748 static struct sh_frame_cache *
1749 sh_frame_cache (struct frame_info *next_frame, void **this_cache)
1750 {
1751 struct sh_frame_cache *cache;
1752 CORE_ADDR current_pc;
1753 int i;
1754
1755 if (*this_cache)
1756 return *this_cache;
1757
1758 cache = sh_alloc_frame_cache ();
1759 *this_cache = cache;
1760
1761 /* In principle, for normal frames, fp holds the frame pointer,
1762 which holds the base address for the current stack frame.
1763 However, for functions that don't need it, the frame pointer is
1764 optional. For these "frameless" functions the frame pointer is
1765 actually the frame pointer of the calling frame. */
1766 cache->base = frame_unwind_register_unsigned (next_frame, FP_REGNUM);
1767 if (cache->base == 0)
1768 return cache;
1769
1770 cache->pc = frame_func_unwind (next_frame);
1771 current_pc = frame_pc_unwind (next_frame);
1772 if (cache->pc != 0)
1773 sh_analyze_prologue (cache->pc, current_pc, cache);
1774
1775 if (!cache->uses_fp)
1776 {
1777 /* We didn't find a valid frame, which means that CACHE->base
1778 currently holds the frame pointer for our calling frame. If
1779 we're at the start of a function, or somewhere half-way its
1780 prologue, the function's frame probably hasn't been fully
1781 setup yet. Try to reconstruct the base address for the stack
1782 frame by looking at the stack pointer. For truly "frameless"
1783 functions this might work too. */
1784 cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
1785 }
1786
1787 /* Now that we have the base address for the stack frame we can
1788 calculate the value of sp in the calling frame. */
1789 cache->saved_sp = cache->base + cache->sp_offset;
1790
1791 /* Adjust all the saved registers such that they contain addresses
1792 instead of offsets. */
1793 for (i = 0; i < SH_NUM_REGS; i++)
1794 if (cache->saved_regs[i] != -1)
1795 cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i] - 4;
1796
1797 return cache;
1798 }
1799
1800 static void
1801 sh_frame_prev_register (struct frame_info *next_frame, void **this_cache,
1802 int regnum, int *optimizedp,
1803 enum lval_type *lvalp, CORE_ADDR *addrp,
1804 int *realnump, void *valuep)
1805 {
1806 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
1807
1808 gdb_assert (regnum >= 0);
1809
1810 if (regnum == SP_REGNUM && cache->saved_sp)
1811 {
1812 *optimizedp = 0;
1813 *lvalp = not_lval;
1814 *addrp = 0;
1815 *realnump = -1;
1816 if (valuep)
1817 {
1818 /* Store the value. */
1819 store_unsigned_integer (valuep, 4, cache->saved_sp);
1820 }
1821 return;
1822 }
1823
1824 /* The PC of the previous frame is stored in the PR register of
1825 the current frame. Frob regnum so that we pull the value from
1826 the correct place. */
1827 if (regnum == PC_REGNUM)
1828 regnum = PR_REGNUM;
1829
1830 if (regnum < SH_NUM_REGS && cache->saved_regs[regnum] != -1)
1831 {
1832 *optimizedp = 0;
1833 *lvalp = lval_memory;
1834 *addrp = cache->saved_regs[regnum];
1835 *realnump = -1;
1836 if (valuep)
1837 {
1838 /* Read the value in from memory. */
1839 read_memory (*addrp, valuep,
1840 register_size (current_gdbarch, regnum));
1841 }
1842 return;
1843 }
1844
1845 frame_register_unwind (next_frame, regnum,
1846 optimizedp, lvalp, addrp, realnump, valuep);
1847 }
1848
1849 static void
1850 sh_frame_this_id (struct frame_info *next_frame, void **this_cache,
1851 struct frame_id *this_id)
1852 {
1853 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
1854
1855 /* This marks the outermost frame. */
1856 if (cache->base == 0)
1857 return;
1858
1859 *this_id = frame_id_build (cache->saved_sp, cache->pc);
1860 }
1861
1862 static const struct frame_unwind sh_frame_unwind = {
1863 NORMAL_FRAME,
1864 sh_frame_this_id,
1865 sh_frame_prev_register
1866 };
1867
1868 static const struct frame_unwind *
1869 sh_frame_sniffer (struct frame_info *next_frame)
1870 {
1871 return &sh_frame_unwind;
1872 }
1873
1874 static CORE_ADDR
1875 sh_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1876 {
1877 return frame_unwind_register_unsigned (next_frame, SP_REGNUM);
1878 }
1879
1880 static CORE_ADDR
1881 sh_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1882 {
1883 return frame_unwind_register_unsigned (next_frame, PC_REGNUM);
1884 }
1885
1886 static struct frame_id
1887 sh_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
1888 {
1889 return frame_id_build (sh_unwind_sp (gdbarch, next_frame),
1890 frame_pc_unwind (next_frame));
1891 }
1892
1893 static CORE_ADDR
1894 sh_frame_base_address (struct frame_info *next_frame, void **this_cache)
1895 {
1896 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
1897
1898 return cache->base;
1899 }
1900
1901 static const struct frame_base sh_frame_base = {
1902 &sh_frame_unwind,
1903 sh_frame_base_address,
1904 sh_frame_base_address,
1905 sh_frame_base_address
1906 };
1907
1908 /* The epilogue is defined here as the area at the end of a function,
1909 either on the `ret' instruction itself or after an instruction which
1910 destroys the function's stack frame. */
1911 static int
1912 sh_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
1913 {
1914 CORE_ADDR func_addr = 0, func_end = 0;
1915
1916 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
1917 {
1918 ULONGEST inst;
1919 /* The sh epilogue is max. 14 bytes long. Give another 14 bytes
1920 for a nop and some fixed data (e.g. big offsets) which are
1921 unfortunately also treated as part of the function (which
1922 means, they are below func_end. */
1923 CORE_ADDR addr = func_end - 28;
1924 if (addr < func_addr + 4)
1925 addr = func_addr + 4;
1926 if (pc < addr)
1927 return 0;
1928
1929 /* First search forward until hitting an rts. */
1930 while (addr < func_end
1931 && !IS_RTS (read_memory_unsigned_integer (addr, 2)))
1932 addr += 2;
1933 if (addr >= func_end)
1934 return 0;
1935
1936 /* At this point we should find a mov.l @r15+,r14 instruction,
1937 either before or after the rts. If not, then the function has
1938 probably no "normal" epilogue and we bail out here. */
1939 inst = read_memory_unsigned_integer (addr - 2, 2);
1940 if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2)))
1941 addr -= 2;
1942 else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2)))
1943 return 0;
1944
1945 /* Step over possible lds.l @r15+,pr. */
1946 inst = read_memory_unsigned_integer (addr - 2, 2);
1947 if (IS_LDS (inst))
1948 {
1949 addr -= 2;
1950 inst = read_memory_unsigned_integer (addr - 2, 2);
1951 }
1952
1953 /* Step over possible mov r14,r15. */
1954 if (IS_MOV_FP_SP (inst))
1955 {
1956 addr -= 2;
1957 inst = read_memory_unsigned_integer (addr - 2, 2);
1958 }
1959
1960 /* Now check for FP adjustments, using add #imm,r14 or add rX, r14
1961 instructions. */
1962 while (addr > func_addr + 4
1963 && (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst)))
1964 {
1965 addr -= 2;
1966 inst = read_memory_unsigned_integer (addr - 2, 2);
1967 }
1968
1969 if (pc >= addr)
1970 return 1;
1971 }
1972 return 0;
1973 }
1974
1975 static gdbarch_init_ftype sh_gdbarch_init;
1976
1977 static struct gdbarch *
1978 sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1979 {
1980 struct gdbarch *gdbarch;
1981
1982 sh_show_regs = sh_generic_show_regs;
1983 switch (info.bfd_arch_info->mach)
1984 {
1985 case bfd_mach_sh2e:
1986 sh_show_regs = sh2e_show_regs;
1987 break;
1988 case bfd_mach_sh_dsp:
1989 sh_show_regs = sh_dsp_show_regs;
1990 break;
1991
1992 case bfd_mach_sh3:
1993 sh_show_regs = sh3_show_regs;
1994 break;
1995
1996 case bfd_mach_sh3e:
1997 sh_show_regs = sh3e_show_regs;
1998 break;
1999
2000 case bfd_mach_sh3_dsp:
2001 sh_show_regs = sh3_dsp_show_regs;
2002 break;
2003
2004 case bfd_mach_sh4:
2005 sh_show_regs = sh4_show_regs;
2006 break;
2007
2008 case bfd_mach_sh5:
2009 sh_show_regs = sh64_show_regs;
2010 /* SH5 is handled entirely in sh64-tdep.c */
2011 return sh64_gdbarch_init (info, arches);
2012 }
2013
2014 /* If there is already a candidate, use it. */
2015 arches = gdbarch_list_lookup_by_info (arches, &info);
2016 if (arches != NULL)
2017 return arches->gdbarch;
2018
2019 /* None found, create a new architecture from the information
2020 provided. */
2021 gdbarch = gdbarch_alloc (&info, NULL);
2022
2023 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2024 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2025 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2026 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2027 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2028 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2029 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2030 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2031
2032 set_gdbarch_num_regs (gdbarch, SH_NUM_REGS);
2033 set_gdbarch_sp_regnum (gdbarch, 15);
2034 set_gdbarch_pc_regnum (gdbarch, 16);
2035 set_gdbarch_fp0_regnum (gdbarch, -1);
2036 set_gdbarch_num_pseudo_regs (gdbarch, 0);
2037
2038 set_gdbarch_register_type (gdbarch, sh_default_register_type);
2039
2040 set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info);
2041
2042 set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);
2043 set_gdbarch_use_struct_convention (gdbarch, sh_use_struct_convention);
2044
2045 set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh);
2046 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
2047
2048 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
2049
2050 set_gdbarch_store_return_value (gdbarch, sh_default_store_return_value);
2051 set_gdbarch_extract_return_value (gdbarch, sh_default_extract_return_value);
2052 set_gdbarch_extract_struct_value_address (gdbarch,
2053 sh_extract_struct_value_address);
2054
2055 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
2056 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2057 set_gdbarch_decr_pc_after_break (gdbarch, 0);
2058 set_gdbarch_function_start_offset (gdbarch, 0);
2059
2060 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu);
2061
2062 set_gdbarch_frame_args_skip (gdbarch, 0);
2063 set_gdbarch_frameless_function_invocation (gdbarch,
2064 frameless_look_for_prologue);
2065 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2066
2067 set_gdbarch_frame_align (gdbarch, sh_frame_align);
2068 set_gdbarch_unwind_sp (gdbarch, sh_unwind_sp);
2069 set_gdbarch_unwind_pc (gdbarch, sh_unwind_pc);
2070 set_gdbarch_unwind_dummy_id (gdbarch, sh_unwind_dummy_id);
2071 frame_base_set_default (gdbarch, &sh_frame_base);
2072
2073 set_gdbarch_in_function_epilogue_p (gdbarch, sh_in_function_epilogue_p);
2074
2075 switch (info.bfd_arch_info->mach)
2076 {
2077 case bfd_mach_sh:
2078 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2079 break;
2080
2081 case bfd_mach_sh2:
2082 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2083 break;
2084
2085 case bfd_mach_sh2e:
2086 /* doubles on sh2e and sh3e are actually 4 byte. */
2087 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2088
2089 set_gdbarch_register_name (gdbarch, sh_sh2e_register_name);
2090 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2091 set_gdbarch_fp0_regnum (gdbarch, 25);
2092 set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
2093 set_gdbarch_extract_return_value (gdbarch,
2094 sh3e_sh4_extract_return_value);
2095 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2096 break;
2097
2098 case bfd_mach_sh_dsp:
2099 set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name);
2100 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2101 break;
2102
2103 case bfd_mach_sh3:
2104 set_gdbarch_register_name (gdbarch, sh_sh3_register_name);
2105 break;
2106
2107 case bfd_mach_sh3e:
2108 /* doubles on sh2e and sh3e are actually 4 byte. */
2109 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2110
2111 set_gdbarch_register_name (gdbarch, sh_sh3e_register_name);
2112 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2113 set_gdbarch_fp0_regnum (gdbarch, 25);
2114 set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
2115 set_gdbarch_extract_return_value (gdbarch,
2116 sh3e_sh4_extract_return_value);
2117 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2118 break;
2119
2120 case bfd_mach_sh3_dsp:
2121 set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name);
2122 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2123 break;
2124
2125 case bfd_mach_sh4:
2126 set_gdbarch_register_name (gdbarch, sh_sh4_register_name);
2127 set_gdbarch_register_type (gdbarch, sh_sh4_register_type);
2128 set_gdbarch_fp0_regnum (gdbarch, 25);
2129 set_gdbarch_num_pseudo_regs (gdbarch, 12);
2130 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2131 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
2132 set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
2133 set_gdbarch_extract_return_value (gdbarch,
2134 sh3e_sh4_extract_return_value);
2135 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2136 break;
2137
2138 default:
2139 set_gdbarch_register_name (gdbarch, sh_generic_register_name);
2140 break;
2141 }
2142
2143 /* Hook in ABI-specific overrides, if they have been registered. */
2144 gdbarch_init_osabi (info, gdbarch);
2145
2146 frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer);
2147 frame_unwind_append_sniffer (gdbarch, sh_frame_sniffer);
2148
2149 return gdbarch;
2150 }
2151
2152 extern initialize_file_ftype _initialize_sh_tdep; /* -Wmissing-prototypes */
2153
2154 void
2155 _initialize_sh_tdep (void)
2156 {
2157 struct cmd_list_element *c;
2158
2159 gdbarch_register (bfd_arch_sh, sh_gdbarch_init, NULL);
2160
2161 add_com ("regs", class_vars, sh_show_regs_command, "Print all registers");
2162 }
GDB Binutils - Deliverables
This page took 0.077802 seconds and 5 git commands to generate.