gdb/sh-tdep.c

   1 /* Target-dependent code for Renesas Super-H, for GDB.
   2    Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
   3    Free Software Foundation, Inc.
   4
   5    This file is part of GDB.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 2 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program; if not, write to the Free Software
  19    Foundation, Inc., 59 Temple Place - Suite 330,
  20    Boston, MA 02111-1307, USA.  */
  21
  22 /*
  23    Contributed by Steve Chamberlain
  24    sac@cygnus.com
  25  */
  26
  27 #include "defs.h"
  28 #include "frame.h"
  29 #include "frame-base.h"
  30 #include "frame-unwind.h"
  31 #include "dwarf2-frame.h"
  32 #include "symtab.h"
  33 #include "symfile.h"
  34 #include "gdbtypes.h"
  35 #include "gdbcmd.h"
  36 #include "gdbcore.h"
  37 #include "value.h"
  38 #include "dis-asm.h"
  39 #include "inferior.h"
  40 #include "gdb_string.h"
  41 #include "gdb_assert.h"
  42 #include "arch-utils.h"
  43 #include "floatformat.h"
  44 #include "regcache.h"
  45 #include "doublest.h"
  46 #include "osabi.h"
  47
  48 #include "sh-tdep.h"
  49
  50 #include "elf-bfd.h"
  51 #include "solib-svr4.h"
  52
  53 /* sh flags */
  54 #include "elf/sh.h"
  55 /* registers numbers shared with the simulator */
  56 #include "gdb/sim-sh.h"
  57
  58 static void (*sh_show_regs) (void);
  59
  60 #define SH_NUM_REGS 59
  61
  62 struct sh_frame_cache
  63 {
  64   /* Base address.  */
  65   CORE_ADDR base;
  66   LONGEST sp_offset;
  67   CORE_ADDR pc;
  68
  69   /* Flag showing that a frame has been created in the prologue code. */
  70   int uses_fp;
  71
  72   /* Saved registers.  */
  73   CORE_ADDR saved_regs[SH_NUM_REGS];
  74   CORE_ADDR saved_sp;
  75 };
  76
  77 static const char *
  78 sh_generic_register_name (int reg_nr)
  79 {
  80   static char *register_names[] = {
  81     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
  82     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
  83     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
  84     "fpul", "fpscr",
  85     "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
  86     "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
  87     "ssr", "spc",
  88     "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
  89     "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
  90   };
  91   if (reg_nr < 0)
  92     return NULL;
  93   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
  94     return NULL;
  95   return register_names[reg_nr];
  96 }
  97
  98 static const char *
  99 sh_sh_register_name (int reg_nr)
 100 {
 101   static char *register_names[] = {
 102     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 103     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 104     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
 105     "", "",
 106     "", "", "", "", "", "", "", "",
 107     "", "", "", "", "", "", "", "",
 108     "", "",
 109     "", "", "", "", "", "", "", "",
 110     "", "", "", "", "", "", "", "",
 111   };
 112   if (reg_nr < 0)
 113     return NULL;
 114   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
 115     return NULL;
 116   return register_names[reg_nr];
 117 }
 118
 119 static const char *
 120 sh_sh3_register_name (int reg_nr)
 121 {
 122   static char *register_names[] = {
 123     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 124     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 125     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
 126     "", "",
 127     "", "", "", "", "", "", "", "",
 128     "", "", "", "", "", "", "", "",
 129     "ssr", "spc",
 130     "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
 131     "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
 132   };
 133   if (reg_nr < 0)
 134     return NULL;
 135   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
 136     return NULL;
 137   return register_names[reg_nr];
 138 }
 139
 140 static const char *
 141 sh_sh3e_register_name (int reg_nr)
 142 {
 143   static char *register_names[] = {
 144     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 145     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 146     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
 147     "fpul", "fpscr",
 148     "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
 149     "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
 150     "ssr", "spc",
 151     "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
 152     "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
 153   };
 154   if (reg_nr < 0)
 155     return NULL;
 156   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
 157     return NULL;
 158   return register_names[reg_nr];
 159 }
 160
 161 static const char *
 162 sh_sh2e_register_name (int reg_nr)
 163 {
 164   static char *register_names[] = {
 165     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 166     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 167     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
 168     "fpul", "fpscr",
 169     "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
 170     "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
 171     "", "",
 172     "", "", "", "", "", "", "", "",
 173     "", "", "", "", "", "", "", "",
 174   };
 175   if (reg_nr < 0)
 176     return NULL;
 177   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
 178     return NULL;
 179   return register_names[reg_nr];
 180 }
 181
 182 static const char *
 183 sh_sh_dsp_register_name (int reg_nr)
 184 {
 185   static char *register_names[] = {
 186     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 187     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 188     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
 189     "", "dsr",
 190     "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
 191     "y0", "y1", "", "", "", "", "", "mod",
 192     "", "",
 193     "rs", "re", "", "", "", "", "", "",
 194     "", "", "", "", "", "", "", "",
 195   };
 196   if (reg_nr < 0)
 197     return NULL;
 198   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
 199     return NULL;
 200   return register_names[reg_nr];
 201 }
 202
 203 static const char *
 204 sh_sh3_dsp_register_name (int reg_nr)
 205 {
 206   static char *register_names[] = {
 207     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 208     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 209     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
 210     "", "dsr",
 211     "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
 212     "y0", "y1", "", "", "", "", "", "mod",
 213     "ssr", "spc",
 214     "rs", "re", "", "", "", "", "", "",
 215     "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b"
 216       "", "", "", "", "", "", "", "",
 217   };
 218   if (reg_nr < 0)
 219     return NULL;
 220   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
 221     return NULL;
 222   return register_names[reg_nr];
 223 }
 224
 225 static const char *
 226 sh_sh4_register_name (int reg_nr)
 227 {
 228   static char *register_names[] = {
 229     /* general registers 0-15 */
 230     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 231     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 232     /* 16 - 22 */
 233     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
 234     /* 23, 24 */
 235     "fpul", "fpscr",
 236     /* floating point registers 25 - 40 */
 237     "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
 238     "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
 239     /* 41, 42 */
 240     "ssr", "spc",
 241     /* bank 0 43 - 50 */
 242     "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
 243     /* bank 1 51 - 58 */
 244     "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
 245     /* double precision (pseudo) 59 - 66 */
 246     "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
 247     /* vectors (pseudo) 67 - 70 */
 248     "fv0", "fv4", "fv8", "fv12",
 249     /* FIXME: missing XF 71 - 86 */
 250     /* FIXME: missing XD 87 - 94 */
 251   };
 252   if (reg_nr < 0)
 253     return NULL;
 254   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
 255     return NULL;
 256   return register_names[reg_nr];
 257 }
 258
 259 static const unsigned char *
 260 sh_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
 261 {
 262   /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
 263   static unsigned char breakpoint[] = { 0xc3, 0xc3 };
 264
 265   *lenptr = sizeof (breakpoint);
 266   return breakpoint;
 267 }
 268
 269 /* Prologue looks like
 270    mov.l        r14,@-r15
 271    sts.l        pr,@-r15
 272    mov.l        <regs>,@-r15
 273    sub          <room_for_loca_vars>,r15
 274    mov          r15,r14
 275
 276    Actually it can be more complicated than this but that's it, basically.
 277  */
 278
 279 #define GET_SOURCE_REG(x)       (((x) >> 4) & 0xf)
 280 #define GET_TARGET_REG(x)       (((x) >> 8) & 0xf)
 281
 282 /* STS.L PR,@-r15  0100111100100010
 283    r15-4-->r15, PR-->(r15) */
 284 #define IS_STS(x)               ((x) == 0x4f22)
 285
 286 /* MOV.L Rm,@-r15  00101111mmmm0110
 287    r15-4-->r15, Rm-->(R15) */
 288 #define IS_PUSH(x)              (((x) & 0xff0f) == 0x2f06)
 289
 290 /* MOV r15,r14     0110111011110011
 291    r15-->r14  */
 292 #define IS_MOV_SP_FP(x)         ((x) == 0x6ef3)
 293
 294 /* ADD #imm,r15    01111111iiiiiiii
 295    r15+imm-->r15 */
 296 #define IS_ADD_IMM_SP(x)        (((x) & 0xff00) == 0x7f00)
 297
 298 #define IS_MOV_R3(x)            (((x) & 0xff00) == 0x1a00)
 299 #define IS_SHLL_R3(x)           ((x) == 0x4300)
 300
 301 /* ADD r3,r15      0011111100111100
 302    r15+r3-->r15 */
 303 #define IS_ADD_R3SP(x)          ((x) == 0x3f3c)
 304
 305 /* FMOV.S FRm,@-Rn  Rn-4-->Rn, FRm-->(Rn)     1111nnnnmmmm1011
 306    FMOV DRm,@-Rn    Rn-8-->Rn, DRm-->(Rn)     1111nnnnmmm01011
 307    FMOV XDm,@-Rn    Rn-8-->Rn, XDm-->(Rn)     1111nnnnmmm11011 */
 308 /* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to
 309                    make this entirely clear. */
 310 /* #define IS_FMOV(x)           (((x) & 0xf00f) == 0xf00b) */
 311 #define IS_FPUSH(x)             (((x) & 0xff0f) == 0xff0b)
 312
 313 /* MOV Rm,Rn          Rm-->Rn        0110nnnnmmmm0011  4 <= m <= 7 */
 314 #define IS_MOV_ARG_TO_REG(x) \
 315         (((x) & 0xf00f) == 0x6003 && \
 316          ((x) & 0x00f0) >= 0x0040 && \
 317          ((x) & 0x00f0) <= 0x0070)
 318 /* MOV.L Rm,@Rn               0010nnnnmmmm0010  n = 14, 4 <= m <= 7 */
 319 #define IS_MOV_ARG_TO_IND_R14(x) \
 320         (((x) & 0xff0f) == 0x2e02 && \
 321          ((x) & 0x00f0) >= 0x0040 && \
 322          ((x) & 0x00f0) <= 0x0070)
 323 /* MOV.L Rm,@(disp*4,Rn)      00011110mmmmdddd  n = 14, 4 <= m <= 7 */
 324 #define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \
 325         (((x) & 0xff00) == 0x1e00 && \
 326          ((x) & 0x00f0) >= 0x0040 && \
 327          ((x) & 0x00f0) <= 0x0070)
 328
 329 /* MOV.W @(disp*2,PC),Rn      1001nnnndddddddd */
 330 #define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000)
 331 /* MOV.L @(disp*4,PC),Rn      1101nnnndddddddd */
 332 #define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000)
 333 /* SUB Rn,R15                 00111111nnnn1000 */
 334 #define IS_SUB_REG_FROM_SP(x)   (((x) & 0xff0f) == 0x3f08)
 335
 336 #define FPSCR_SZ                (1 << 20)
 337
 338 /* The following instructions are used for epilogue testing. */
 339 #define IS_RESTORE_FP(x)        ((x) == 0x6ef6)
 340 #define IS_RTS(x)               ((x) == 0x000b)
 341 #define IS_LDS(x)               ((x) == 0x4f26)
 342 #define IS_MOV_FP_SP(x)         ((x) == 0x6fe3)
 343 #define IS_ADD_REG_TO_FP(x)     (((x) & 0xff0f) == 0x3e0c)
 344 #define IS_ADD_IMM_FP(x)        (((x) & 0xff00) == 0x7e00)
 345
 346 /* Disassemble an instruction.  */
 347 static int
 348 gdb_print_insn_sh (bfd_vma memaddr, disassemble_info * info)
 349 {
 350   info->endian = TARGET_BYTE_ORDER;
 351   return print_insn_sh (memaddr, info);
 352 }
 353
 354 static CORE_ADDR
 355 sh_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc,
 356                      struct sh_frame_cache *cache)
 357 {
 358   ULONGEST inst;
 359   CORE_ADDR opc;
 360   int offset;
 361   int sav_offset = 0;
 362   int r3_val = 0;
 363   int reg, sav_reg = -1;
 364
 365   if (pc >= current_pc)
 366     return current_pc;
 367
 368   cache->uses_fp = 0;
 369   for (opc = pc + (2 * 28); pc < opc; pc += 2)
 370     {
 371       inst = read_memory_unsigned_integer (pc, 2);
 372       /* See where the registers will be saved to */
 373       if (IS_PUSH (inst))
 374         {
 375           cache->saved_regs[GET_SOURCE_REG (inst)] = cache->sp_offset;
 376           cache->sp_offset += 4;
 377         }
 378       else if (IS_STS (inst))
 379         {
 380           cache->saved_regs[PR_REGNUM] = cache->sp_offset;
 381           cache->sp_offset += 4;
 382         }
 383       else if (IS_MOV_R3 (inst))
 384         {
 385           r3_val = ((inst & 0xff) ^ 0x80) - 0x80;
 386         }
 387       else if (IS_SHLL_R3 (inst))
 388         {
 389           r3_val <<= 1;
 390         }
 391       else if (IS_ADD_R3SP (inst))
 392         {
 393           cache->sp_offset += -r3_val;
 394         }
 395       else if (IS_ADD_IMM_SP (inst))
 396         {
 397           offset = ((inst & 0xff) ^ 0x80) - 0x80;
 398           cache->sp_offset -= offset;
 399         }
 400       else if (IS_MOVW_PCREL_TO_REG (inst))
 401         {
 402           if (sav_reg < 0)
 403             {
 404               reg = GET_TARGET_REG (inst);
 405               if (reg < 14)
 406                 {
 407                   sav_reg = reg;
 408                   offset = (((inst & 0xff) ^ 0x80) - 0x80) << 1;
 409                   sav_offset =
 410                     read_memory_integer (((pc + 4) & ~3) + offset, 2);
 411                 }
 412             }
 413         }
 414       else if (IS_MOVL_PCREL_TO_REG (inst))
 415         {
 416           if (sav_reg < 0)
 417             {
 418               reg = (inst & 0x0f00) >> 8;
 419               if (reg < 14)
 420                 {
 421                   sav_reg = reg;
 422                   offset = (((inst & 0xff) ^ 0x80) - 0x80) << 1;
 423                   sav_offset =
 424                     read_memory_integer (((pc + 4) & ~3) + offset, 4);
 425                 }
 426             }
 427         }
 428       else if (IS_SUB_REG_FROM_SP (inst))
 429         {
 430           reg = GET_SOURCE_REG (inst);
 431           if (sav_reg > 0 && reg == sav_reg)
 432             {
 433               sav_reg = -1;
 434             }
 435           cache->sp_offset += sav_offset;
 436         }
 437       else if (IS_FPUSH (inst))
 438         {
 439           if (read_register (FPSCR_REGNUM) & FPSCR_SZ)
 440             {
 441               cache->sp_offset += 8;
 442             }
 443           else
 444             {
 445               cache->sp_offset += 4;
 446             }
 447         }
 448       else if (IS_MOV_SP_FP (inst))
 449         {
 450           if (!cache->uses_fp)
 451             cache->uses_fp = 1;
 452           /* At this point, only allow argument register moves to other
 453              registers or argument register moves to @(X,fp) which are
 454              moving the register arguments onto the stack area allocated
 455              by a former add somenumber to SP call.  Don't allow moving
 456              to an fp indirect address above fp + cache->sp_offset. */
 457           pc += 2;
 458           for (opc = pc + 12; pc < opc; pc += 2)
 459             {
 460               inst = read_memory_integer (pc, 2);
 461               if (IS_MOV_ARG_TO_IND_R14 (inst))
 462                 {
 463                   reg = GET_SOURCE_REG (inst);
 464                   if (cache->sp_offset > 0)
 465                     cache->saved_regs[reg] = cache->sp_offset;
 466                 }
 467               else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst))
 468                 {
 469                   reg = GET_SOURCE_REG (inst);
 470                   offset = (inst & 0xf) * 4;
 471                   if (cache->sp_offset > offset)
 472                     cache->saved_regs[reg] = cache->sp_offset - offset;
 473                 }
 474               else if (IS_MOV_ARG_TO_REG (inst))
 475                 continue;
 476               else
 477                 break;
 478             }
 479           break;
 480         }
 481 #if 0                           /* This used to just stop when it found an instruction that
 482                                    was not considered part of the prologue.  Now, we just
 483                                    keep going looking for likely instructions. */
 484       else
 485         break;
 486 #endif
 487     }
 488
 489   return pc;
 490 }
 491
 492 /* Skip any prologue before the guts of a function */
 493
 494 /* Skip the prologue using the debug information. If this fails we'll
 495    fall back on the 'guess' method below. */
 496 static CORE_ADDR
 497 after_prologue (CORE_ADDR pc)
 498 {
 499   struct symtab_and_line sal;
 500   CORE_ADDR func_addr, func_end;
 501
 502   /* If we can not find the symbol in the partial symbol table, then
 503      there is no hope we can determine the function's start address
 504      with this code.  */
 505   if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
 506     return 0;
 507
 508   /* Get the line associated with FUNC_ADDR.  */
 509   sal = find_pc_line (func_addr, 0);
 510
 511   /* There are only two cases to consider.  First, the end of the source line
 512      is within the function bounds.  In that case we return the end of the
 513      source line.  Second is the end of the source line extends beyond the
 514      bounds of the current function.  We need to use the slow code to
 515      examine instructions in that case.  */
 516   if (sal.end < func_end)
 517     return sal.end;
 518   else
 519     return 0;
 520 }
 521
 522 static CORE_ADDR
 523 sh_skip_prologue (CORE_ADDR start_pc)
 524 {
 525   CORE_ADDR pc;
 526   struct sh_frame_cache cache;
 527
 528   /* See if we can determine the end of the prologue via the symbol table.
 529      If so, then return either PC, or the PC after the prologue, whichever
 530      is greater.  */
 531   pc = after_prologue (start_pc);
 532
 533   /* If after_prologue returned a useful address, then use it.  Else
 534      fall back on the instruction skipping code. */
 535   if (pc)
 536     return max (pc, start_pc);
 537
 538   cache.sp_offset = -4;
 539   pc = sh_analyze_prologue (start_pc, (CORE_ADDR) -1, &cache);
 540   if (!cache.uses_fp)
 541     return start_pc;
 542
 543   return pc;
 544 }
 545
 546 /* Should call_function allocate stack space for a struct return?
 547
 548    The ABI says:
 549
 550    Aggregate types not bigger than 8 bytes that have the same size and
 551    alignment as one of the integer scalar types are returned in the
 552    same registers as the integer type they match.
 553
 554    For example, a 2-byte aligned structure with size 2 bytes has the
 555    same size and alignment as a short int, and will be returned in R0.
 556    A 4-byte aligned structure with size 8 bytes has the same size and
 557    alignment as a long long int, and will be returned in R0 and R1.
 558
 559    When an aggregate type is returned in R0 and R1, R0 contains the
 560    first four bytes of the aggregate, and R1 contains the
 561    remainder. If the size of the aggregate type is not a multiple of 4
 562    bytes, the aggregate is tail-padded up to a multiple of 4
 563    bytes. The value of the padding is undefined. For little-endian
 564    targets the padding will appear at the most significant end of the
 565    last element, for big-endian targets the padding appears at the
 566    least significant end of the last element.
 567
 568    All other aggregate types are returned by address. The caller
 569    function passes the address of an area large enough to hold the
 570    aggregate value in R2. The called function stores the result in
 571    this location.
 572
 573    To reiterate, structs smaller than 8 bytes could also be returned
 574    in memory, if they don't pass the "same size and alignment as an
 575    integer type" rule.
 576
 577    For example, in
 578
 579    struct s { char c[3]; } wibble;
 580    struct s foo(void) {  return wibble; }
 581
 582    the return value from foo() will be in memory, not
 583    in R0, because there is no 3-byte integer type.
 584
 585    Similarly, in
 586
 587    struct s { char c[2]; } wibble;
 588    struct s foo(void) {  return wibble; }
 589
 590    because a struct containing two chars has alignment 1, that matches
 591    type char, but size 2, that matches type short.  There's no integer
 592    type that has alignment 1 and size 2, so the struct is returned in
 593    memory.
 594
 595 */
 596
 597 static int
 598 sh_use_struct_convention (int gcc_p, struct type *type)
 599 {
 600   int len = TYPE_LENGTH (type);
 601   int nelem = TYPE_NFIELDS (type);
 602
 603   /* Non-power of 2 length types and types bigger than 8 bytes (which don't
 604      fit in two registers anyway) use struct convention.  */
 605   if (len != 1 && len != 2 && len != 4 && len != 8)
 606     return 1;
 607
 608   /* Scalar types and aggregate types with exactly one field are aligned
 609      by definition.  They are returned in registers.  */
 610   if (nelem <= 1)
 611     return 0;
 612
 613   /* If the first field in the aggregate has the same length as the entire
 614      aggregate type, the type is returned in registers.  */
 615   if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == len)
 616     return 0;
 617
 618   /* If the size of the aggregate is 8 bytes and the first field is
 619      of size 4 bytes its alignment is equal to long long's alignment,
 620      so it's returned in registers.  */
 621   if (len == 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == 4)
 622     return 0;
 623
 624   /* Otherwise use struct convention.  */
 625   return 1;
 626 }
 627
 628 /* Extract from an array REGBUF containing the (raw) register state
 629    the address in which a function should return its structure value,
 630    as a CORE_ADDR (or an expression that can be used as one).  */
 631 static CORE_ADDR
 632 sh_extract_struct_value_address (struct regcache *regcache)
 633 {
 634   ULONGEST addr;
 635
 636   regcache_cooked_read_unsigned (regcache, STRUCT_RETURN_REGNUM, &addr);
 637   return addr;
 638 }
 639
 640 static CORE_ADDR
 641 sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
 642 {
 643   return sp & ~3;
 644 }
 645
 646 /* Function: push_dummy_call (formerly push_arguments)
 647    Setup the function arguments for calling a function in the inferior.
 648
 649    On the Renesas SH architecture, there are four registers (R4 to R7)
 650    which are dedicated for passing function arguments.  Up to the first
 651    four arguments (depending on size) may go into these registers.
 652    The rest go on the stack.
 653
 654    MVS: Except on SH variants that have floating point registers.
 655    In that case, float and double arguments are passed in the same
 656    manner, but using FP registers instead of GP registers.
 657
 658    Arguments that are smaller than 4 bytes will still take up a whole
 659    register or a whole 32-bit word on the stack, and will be
 660    right-justified in the register or the stack word.  This includes
 661    chars, shorts, and small aggregate types.
 662
 663    Arguments that are larger than 4 bytes may be split between two or
 664    more registers.  If there are not enough registers free, an argument
 665    may be passed partly in a register (or registers), and partly on the
 666    stack.  This includes doubles, long longs, and larger aggregates.
 667    As far as I know, there is no upper limit to the size of aggregates
 668    that will be passed in this way; in other words, the convention of
 669    passing a pointer to a large aggregate instead of a copy is not used.
 670
 671    MVS: The above appears to be true for the SH variants that do not
 672    have an FPU, however those that have an FPU appear to copy the
 673    aggregate argument onto the stack (and not place it in registers)
 674    if it is larger than 16 bytes (four GP registers).
 675
 676    An exceptional case exists for struct arguments (and possibly other
 677    aggregates such as arrays) if the size is larger than 4 bytes but
 678    not a multiple of 4 bytes.  In this case the argument is never split
 679    between the registers and the stack, but instead is copied in its
 680    entirety onto the stack, AND also copied into as many registers as
 681    there is room for.  In other words, space in registers permitting,
 682    two copies of the same argument are passed in.  As far as I can tell,
 683    only the one on the stack is used, although that may be a function
 684    of the level of compiler optimization.  I suspect this is a compiler
 685    bug.  Arguments of these odd sizes are left-justified within the
 686    word (as opposed to arguments smaller than 4 bytes, which are
 687    right-justified).
 688
 689    If the function is to return an aggregate type such as a struct, it
 690    is either returned in the normal return value register R0 (if its
 691    size is no greater than one byte), or else the caller must allocate
 692    space into which the callee will copy the return value (if the size
 693    is greater than one byte).  In this case, a pointer to the return
 694    value location is passed into the callee in register R2, which does
 695    not displace any of the other arguments passed in via registers R4
 696    to R7.   */
 697
 698 /* Helper function to justify value in register according to endianess. */
 699 static char *
 700 sh_justify_value_in_reg (struct value *val, int len)
 701 {
 702   static char valbuf[4];
 703
 704   memset (valbuf, 0, sizeof (valbuf));
 705   if (len < 4)
 706     {
 707       /* value gets right-justified in the register or stack word */
 708       if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
 709         memcpy (valbuf + (4 - len), (char *) VALUE_CONTENTS (val), len);
 710       else
 711         memcpy (valbuf, (char *) VALUE_CONTENTS (val), len);
 712       return valbuf;
 713     }
 714   return (char *) VALUE_CONTENTS (val);
 715 }
 716
 717 /* Helper function to eval number of bytes to allocate on stack. */
 718 static CORE_ADDR
 719 sh_stack_allocsize (int nargs, struct value **args)
 720 {
 721   int stack_alloc = 0;
 722   while (nargs-- > 0)
 723     stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[nargs])) + 3) & ~3);
 724   return stack_alloc;
 725 }
 726
 727 /* Helper functions for getting the float arguments right.  Registers usage
 728    depends on the ABI and the endianess.  The comments should enlighten how
 729    it's intended to work. */
 730
 731 /* This array stores which of the float arg registers are already in use. */
 732 static int flt_argreg_array[FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM + 1];
 733
 734 /* This function just resets the above array to "no reg used so far". */
 735 static void
 736 sh_init_flt_argreg (void)
 737 {
 738   memset (flt_argreg_array, 0, sizeof flt_argreg_array);
 739 }
 740
 741 /* This function returns the next register to use for float arg passing.
 742    It returns either a valid value between FLOAT_ARG0_REGNUM and
 743    FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns
 744    FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available.
 745
 746    Note that register number 0 in flt_argreg_array corresponds with the
 747    real float register fr4.  In contrast to FLOAT_ARG0_REGNUM (value is
 748    29) the parity of the register number is preserved, which is important
 749    for the double register passing test (see the "argreg & 1" test below). */
 750 static int
 751 sh_next_flt_argreg (int len)
 752 {
 753   int argreg;
 754
 755   /* First search for the next free register. */
 756   for (argreg = 0; argreg <= FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM;
 757        ++argreg)
 758     if (!flt_argreg_array[argreg])
 759       break;
 760
 761   /* No register left? */
 762   if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
 763     return FLOAT_ARGLAST_REGNUM + 1;
 764
 765   if (len == 8)
 766     {
 767       /* Doubles are always starting in a even register number. */
 768       if (argreg & 1)
 769         {
 770           flt_argreg_array[argreg] = 1;
 771
 772           ++argreg;
 773
 774           /* No register left? */
 775           if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
 776             return FLOAT_ARGLAST_REGNUM + 1;
 777         }
 778       /* Also mark the next register as used. */
 779       flt_argreg_array[argreg + 1] = 1;
 780     }
 781   else if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
 782     {
 783       /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */
 784       if (!flt_argreg_array[argreg + 1])
 785         ++argreg;
 786     }
 787   flt_argreg_array[argreg] = 1;
 788   return FLOAT_ARG0_REGNUM + argreg;
 789 }
 790
 791 static CORE_ADDR
 792 sh_push_dummy_call_fpu (struct gdbarch *gdbarch,
 793                         CORE_ADDR func_addr,
 794                         struct regcache *regcache,
 795                         CORE_ADDR bp_addr, int nargs,
 796                         struct value **args,
 797                         CORE_ADDR sp, int struct_return,
 798                         CORE_ADDR struct_addr)
 799 {
 800   int stack_offset = 0;
 801   int argreg = ARG0_REGNUM;
 802   int flt_argreg = 0;
 803   int argnum;
 804   struct type *type;
 805   CORE_ADDR regval;
 806   char *val;
 807   int len, reg_size = 0;
 808   int pass_on_stack;
 809
 810   /* first force sp to a 4-byte alignment */
 811   sp = sh_frame_align (gdbarch, sp);
 812
 813   if (struct_return)
 814     regcache_cooked_write_unsigned (regcache,
 815                                     STRUCT_RETURN_REGNUM, struct_addr);
 816
 817   /* make room on stack for args */
 818   sp -= sh_stack_allocsize (nargs, args);
 819
 820   /* Initialize float argument mechanism. */
 821   sh_init_flt_argreg ();
 822
 823   /* Now load as many as possible of the first arguments into
 824      registers, and push the rest onto the stack.  There are 16 bytes
 825      in four registers available.  Loop thru args from first to last.  */
 826   for (argnum = 0; argnum < nargs; argnum++)
 827     {
 828       type = VALUE_TYPE (args[argnum]);
 829       len = TYPE_LENGTH (type);
 830       val = sh_justify_value_in_reg (args[argnum], len);
 831
 832       /* Some decisions have to be made how various types are handled.
 833          This also differs in different ABIs. */
 834       pass_on_stack = 0;
 835       if (len > 16)
 836         pass_on_stack = 1;      /* Types bigger than 16 bytes are passed on stack. */
 837
 838       /* Find out the next register to use for a floating point value. */
 839       if (TYPE_CODE (type) == TYPE_CODE_FLT)
 840         flt_argreg = sh_next_flt_argreg (len);
 841
 842       while (len > 0)
 843         {
 844           if ((TYPE_CODE (type) == TYPE_CODE_FLT
 845                && flt_argreg > FLOAT_ARGLAST_REGNUM)
 846               || argreg > ARGLAST_REGNUM || pass_on_stack)
 847             {
 848               /* The remainder of the data goes entirely on the stack,
 849                  4-byte aligned. */
 850               reg_size = (len + 3) & ~3;
 851               write_memory (sp + stack_offset, val, reg_size);
 852               stack_offset += reg_size;
 853             }
 854           else if (TYPE_CODE (type) == TYPE_CODE_FLT
 855                    && flt_argreg <= FLOAT_ARGLAST_REGNUM)
 856             {
 857               /* Argument goes in a float argument register.  */
 858               reg_size = register_size (gdbarch, flt_argreg);
 859               regval = extract_unsigned_integer (val, reg_size);
 860               regcache_cooked_write_unsigned (regcache, flt_argreg++, regval);
 861             }
 862           else if (argreg <= ARGLAST_REGNUM)
 863             {
 864               /* there's room in a register */
 865               reg_size = register_size (gdbarch, argreg);
 866               regval = extract_unsigned_integer (val, reg_size);
 867               regcache_cooked_write_unsigned (regcache, argreg++, regval);
 868             }
 869           /* Store the value reg_size bytes at a time.  This means that things
 870              larger than reg_size bytes may go partly in registers and partly
 871              on the stack.  */
 872           len -= reg_size;
 873           val += reg_size;
 874         }
 875     }
 876
 877   /* Store return address. */
 878   regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
 879
 880   /* Update stack pointer.  */
 881   regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp);
 882
 883   return sp;
 884 }
 885
 886 static CORE_ADDR
 887 sh_push_dummy_call_nofpu (struct gdbarch *gdbarch,
 888                           CORE_ADDR func_addr,
 889                           struct regcache *regcache,
 890                           CORE_ADDR bp_addr,
 891                           int nargs, struct value **args,
 892                           CORE_ADDR sp, int struct_return,
 893                           CORE_ADDR struct_addr)
 894 {
 895   int stack_offset = 0;
 896   int argreg = ARG0_REGNUM;
 897   int argnum;
 898   struct type *type;
 899   CORE_ADDR regval;
 900   char *val;
 901   int len, reg_size;
 902
 903   /* first force sp to a 4-byte alignment */
 904   sp = sh_frame_align (gdbarch, sp);
 905
 906   if (struct_return)
 907     regcache_cooked_write_unsigned (regcache,
 908                                     STRUCT_RETURN_REGNUM, struct_addr);
 909
 910   /* make room on stack for args */
 911   sp -= sh_stack_allocsize (nargs, args);
 912
 913   /* Now load as many as possible of the first arguments into
 914      registers, and push the rest onto the stack.  There are 16 bytes
 915      in four registers available.  Loop thru args from first to last.  */
 916   for (argnum = 0; argnum < nargs; argnum++)
 917     {
 918       type = VALUE_TYPE (args[argnum]);
 919       len = TYPE_LENGTH (type);
 920       val = sh_justify_value_in_reg (args[argnum], len);
 921
 922       while (len > 0)
 923         {
 924           if (argreg > ARGLAST_REGNUM)
 925             {
 926               /* The remainder of the data goes entirely on the stack,
 927                  4-byte aligned. */
 928               reg_size = (len + 3) & ~3;
 929               write_memory (sp + stack_offset, val, reg_size);
 930               stack_offset += reg_size;
 931             }
 932           else if (argreg <= ARGLAST_REGNUM)
 933             {
 934               /* there's room in a register */
 935               reg_size = register_size (gdbarch, argreg);
 936               regval = extract_unsigned_integer (val, reg_size);
 937               regcache_cooked_write_unsigned (regcache, argreg++, regval);
 938             }
 939           /* Store the value reg_size bytes at a time.  This means that things
 940              larger than reg_size bytes may go partly in registers and partly
 941              on the stack.  */
 942           len -= reg_size;
 943           val += reg_size;
 944         }
 945     }
 946
 947   /* Store return address. */
 948   regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
 949
 950   /* Update stack pointer.  */
 951   regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp);
 952
 953   return sp;
 954 }
 955
 956 /* Find a function's return value in the appropriate registers (in
 957    regbuf), and copy it into valbuf.  Extract from an array REGBUF
 958    containing the (raw) register state a function return value of type
 959    TYPE, and copy that, in virtual format, into VALBUF.  */
 960 static void
 961 sh_default_extract_return_value (struct type *type, struct regcache *regcache,
 962                                  void *valbuf)
 963 {
 964   int len = TYPE_LENGTH (type);
 965   int return_register = R0_REGNUM;
 966   int offset;
 967
 968   if (len <= 4)
 969     {
 970       ULONGEST c;
 971
 972       regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c);
 973       store_unsigned_integer (valbuf, len, c);
 974     }
 975   else if (len == 8)
 976     {
 977       int i, regnum = R0_REGNUM;
 978       for (i = 0; i < len; i += 4)
 979         regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
 980     }
 981   else
 982     error ("bad size for return value");
 983 }
 984
 985 static void
 986 sh3e_sh4_extract_return_value (struct type *type, struct regcache *regcache,
 987                                void *valbuf)
 988 {
 989   if (TYPE_CODE (type) == TYPE_CODE_FLT)
 990     {
 991       int len = TYPE_LENGTH (type);
 992       int i, regnum = FP0_REGNUM;
 993       for (i = 0; i < len; i += 4)
 994         regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
 995     }
 996   else
 997     sh_default_extract_return_value (type, regcache, valbuf);
 998 }
 999
1000 /* Write into appropriate registers a function return value
1001    of type TYPE, given in virtual format.
1002    If the architecture is sh4 or sh3e, store a function's return value
1003    in the R0 general register or in the FP0 floating point register,
1004    depending on the type of the return value. In all the other cases
1005    the result is stored in r0, left-justified. */
1006 static void
1007 sh_default_store_return_value (struct type *type, struct regcache *regcache,
1008                                const void *valbuf)
1009 {
1010   ULONGEST val;
1011   int len = TYPE_LENGTH (type);
1012
1013   if (len <= 4)
1014     {
1015       val = extract_unsigned_integer (valbuf, len);
1016       regcache_cooked_write_unsigned (regcache, R0_REGNUM, val);
1017     }
1018   else
1019     {
1020       int i, regnum = R0_REGNUM;
1021       for (i = 0; i < len; i += 4)
1022         regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
1023     }
1024 }
1025
1026 static void
1027 sh3e_sh4_store_return_value (struct type *type, struct regcache *regcache,
1028                              const void *valbuf)
1029 {
1030   if (TYPE_CODE (type) == TYPE_CODE_FLT)
1031     {
1032       int len = TYPE_LENGTH (type);
1033       int i, regnum = FP0_REGNUM;
1034       for (i = 0; i < len; i += 4)
1035         regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
1036     }
1037   else
1038     sh_default_store_return_value (type, regcache, valbuf);
1039 }
1040
1041 /* Print the registers in a form similar to the E7000 */
1042
1043 static void
1044 sh_generic_show_regs (void)
1045 {
1046   printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1047                    paddr (read_register (PC_REGNUM)),
1048                    (long) read_register (SR_REGNUM),
1049                    (long) read_register (PR_REGNUM),
1050                    (long) read_register (MACH_REGNUM),
1051                    (long) read_register (MACL_REGNUM));
1052
1053   printf_filtered ("GBR=%08lx VBR=%08lx",
1054                    (long) read_register (GBR_REGNUM),
1055                    (long) read_register (VBR_REGNUM));
1056
1057   printf_filtered
1058     ("\nR0-R7  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1059      (long) read_register (0), (long) read_register (1),
1060      (long) read_register (2), (long) read_register (3),
1061      (long) read_register (4), (long) read_register (5),
1062      (long) read_register (6), (long) read_register (7));
1063   printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1064                    (long) read_register (8), (long) read_register (9),
1065                    (long) read_register (10), (long) read_register (11),
1066                    (long) read_register (12), (long) read_register (13),
1067                    (long) read_register (14), (long) read_register (15));
1068 }
1069
1070 static void
1071 sh3_show_regs (void)
1072 {
1073   printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1074                    paddr (read_register (PC_REGNUM)),
1075                    (long) read_register (SR_REGNUM),
1076                    (long) read_register (PR_REGNUM),
1077                    (long) read_register (MACH_REGNUM),
1078                    (long) read_register (MACL_REGNUM));
1079
1080   printf_filtered ("GBR=%08lx VBR=%08lx",
1081                    (long) read_register (GBR_REGNUM),
1082                    (long) read_register (VBR_REGNUM));
1083   printf_filtered (" SSR=%08lx SPC=%08lx",
1084                    (long) read_register (SSR_REGNUM),
1085                    (long) read_register (SPC_REGNUM));
1086
1087   printf_filtered
1088     ("\nR0-R7  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1089      (long) read_register (0), (long) read_register (1),
1090      (long) read_register (2), (long) read_register (3),
1091      (long) read_register (4), (long) read_register (5),
1092      (long) read_register (6), (long) read_register (7));
1093   printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1094                    (long) read_register (8), (long) read_register (9),
1095                    (long) read_register (10), (long) read_register (11),
1096                    (long) read_register (12), (long) read_register (13),
1097                    (long) read_register (14), (long) read_register (15));
1098 }
1099
1100
1101 static void
1102 sh2e_show_regs (void)
1103 {
1104   printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1105                    paddr (read_register (PC_REGNUM)),
1106                    (long) read_register (SR_REGNUM),
1107                    (long) read_register (PR_REGNUM),
1108                    (long) read_register (MACH_REGNUM),
1109                    (long) read_register (MACL_REGNUM));
1110
1111   printf_filtered ("GBR=%08lx VBR=%08lx",
1112                    (long) read_register (GBR_REGNUM),
1113                    (long) read_register (VBR_REGNUM));
1114   printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1115                    (long) read_register (FPUL_REGNUM),
1116                    (long) read_register (FPSCR_REGNUM));
1117
1118   printf_filtered
1119     ("\nR0-R7  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1120      (long) read_register (0), (long) read_register (1),
1121      (long) read_register (2), (long) read_register (3),
1122      (long) read_register (4), (long) read_register (5),
1123      (long) read_register (6), (long) read_register (7));
1124   printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1125                    (long) read_register (8), (long) read_register (9),
1126                    (long) read_register (10), (long) read_register (11),
1127                    (long) read_register (12), (long) read_register (13),
1128                    (long) read_register (14), (long) read_register (15));
1129
1130   printf_filtered (("FP0-FP7  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 0), (long) read_register (FP0_REGNUM + 1), (long) read_register (FP0_REGNUM + 2), (long) read_register (FP0_REGNUM + 3), (long) read_register (FP0_REGNUM + 4), (long) read_register (FP0_REGNUM + 5), (long) read_register (FP0_REGNUM + 6), (long) read_register (FP0_REGNUM + 7));
1131   printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 8), (long) read_register (FP0_REGNUM + 9), (long) read_register (FP0_REGNUM + 10), (long) read_register (FP0_REGNUM + 11), (long) read_register (FP0_REGNUM + 12), (long) read_register (FP0_REGNUM + 13), (long) read_register (FP0_REGNUM + 14), (long) read_register (FP0_REGNUM + 15));
1132 }
1133
1134 static void
1135 sh3e_show_regs (void)
1136 {
1137   printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1138                    paddr (read_register (PC_REGNUM)),
1139                    (long) read_register (SR_REGNUM),
1140                    (long) read_register (PR_REGNUM),
1141                    (long) read_register (MACH_REGNUM),
1142                    (long) read_register (MACL_REGNUM));
1143
1144   printf_filtered ("GBR=%08lx VBR=%08lx",
1145                    (long) read_register (GBR_REGNUM),
1146                    (long) read_register (VBR_REGNUM));
1147   printf_filtered (" SSR=%08lx SPC=%08lx",
1148                    (long) read_register (SSR_REGNUM),
1149                    (long) read_register (SPC_REGNUM));
1150   printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1151                    (long) read_register (FPUL_REGNUM),
1152                    (long) read_register (FPSCR_REGNUM));
1153
1154   printf_filtered
1155     ("\nR0-R7  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1156      (long) read_register (0), (long) read_register (1),
1157      (long) read_register (2), (long) read_register (3),
1158      (long) read_register (4), (long) read_register (5),
1159      (long) read_register (6), (long) read_register (7));
1160   printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1161                    (long) read_register (8), (long) read_register (9),
1162                    (long) read_register (10), (long) read_register (11),
1163                    (long) read_register (12), (long) read_register (13),
1164                    (long) read_register (14), (long) read_register (15));
1165
1166   printf_filtered (("FP0-FP7  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 0), (long) read_register (FP0_REGNUM + 1), (long) read_register (FP0_REGNUM + 2), (long) read_register (FP0_REGNUM + 3), (long) read_register (FP0_REGNUM + 4), (long) read_register (FP0_REGNUM + 5), (long) read_register (FP0_REGNUM + 6), (long) read_register (FP0_REGNUM + 7));
1167   printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 8), (long) read_register (FP0_REGNUM + 9), (long) read_register (FP0_REGNUM + 10), (long) read_register (FP0_REGNUM + 11), (long) read_register (FP0_REGNUM + 12), (long) read_register (FP0_REGNUM + 13), (long) read_register (FP0_REGNUM + 14), (long) read_register (FP0_REGNUM + 15));
1168 }
1169
1170 static void
1171 sh3_dsp_show_regs (void)
1172 {
1173   printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1174                    paddr (read_register (PC_REGNUM)),
1175                    (long) read_register (SR_REGNUM),
1176                    (long) read_register (PR_REGNUM),
1177                    (long) read_register (MACH_REGNUM),
1178                    (long) read_register (MACL_REGNUM));
1179
1180   printf_filtered ("GBR=%08lx VBR=%08lx",
1181                    (long) read_register (GBR_REGNUM),
1182                    (long) read_register (VBR_REGNUM));
1183
1184   printf_filtered (" SSR=%08lx SPC=%08lx",
1185                    (long) read_register (SSR_REGNUM),
1186                    (long) read_register (SPC_REGNUM));
1187
1188   printf_filtered (" DSR=%08lx", (long) read_register (DSR_REGNUM));
1189
1190   printf_filtered
1191     ("\nR0-R7  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1192      (long) read_register (0), (long) read_register (1),
1193      (long) read_register (2), (long) read_register (3),
1194      (long) read_register (4), (long) read_register (5),
1195      (long) read_register (6), (long) read_register (7));
1196   printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1197                    (long) read_register (8), (long) read_register (9),
1198                    (long) read_register (10), (long) read_register (11),
1199                    (long) read_register (12), (long) read_register (13),
1200                    (long) read_register (14), (long) read_register (15));
1201
1202   printf_filtered
1203     ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1204      (long) read_register (A0G_REGNUM) & 0xff,
1205      (long) read_register (A0_REGNUM), (long) read_register (M0_REGNUM),
1206      (long) read_register (X0_REGNUM), (long) read_register (Y0_REGNUM),
1207      (long) read_register (RS_REGNUM), (long) read_register (MOD_REGNUM));
1208   printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1209                    (long) read_register (A1G_REGNUM) & 0xff,
1210                    (long) read_register (A1_REGNUM),
1211                    (long) read_register (M1_REGNUM),
1212                    (long) read_register (X1_REGNUM),
1213                    (long) read_register (Y1_REGNUM),
1214                    (long) read_register (RE_REGNUM));
1215 }
1216
1217 static void
1218 sh4_show_regs (void)
1219 {
1220   int pr = read_register (FPSCR_REGNUM) & 0x80000;
1221   printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1222                    paddr (read_register (PC_REGNUM)),
1223                    (long) read_register (SR_REGNUM),
1224                    (long) read_register (PR_REGNUM),
1225                    (long) read_register (MACH_REGNUM),
1226                    (long) read_register (MACL_REGNUM));
1227
1228   printf_filtered ("GBR=%08lx VBR=%08lx",
1229                    (long) read_register (GBR_REGNUM),
1230                    (long) read_register (VBR_REGNUM));
1231   printf_filtered (" SSR=%08lx SPC=%08lx",
1232                    (long) read_register (SSR_REGNUM),
1233                    (long) read_register (SPC_REGNUM));
1234   printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1235                    (long) read_register (FPUL_REGNUM),
1236                    (long) read_register (FPSCR_REGNUM));
1237
1238   printf_filtered
1239     ("\nR0-R7  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1240      (long) read_register (0), (long) read_register (1),
1241      (long) read_register (2), (long) read_register (3),
1242      (long) read_register (4), (long) read_register (5),
1243      (long) read_register (6), (long) read_register (7));
1244   printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1245                    (long) read_register (8), (long) read_register (9),
1246                    (long) read_register (10), (long) read_register (11),
1247                    (long) read_register (12), (long) read_register (13),
1248                    (long) read_register (14), (long) read_register (15));
1249
1250   printf_filtered ((pr
1251                     ? "DR0-DR6  %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1252                     :
1253                     "FP0-FP7  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1254                    (long) read_register (FP0_REGNUM + 0),
1255                    (long) read_register (FP0_REGNUM + 1),
1256                    (long) read_register (FP0_REGNUM + 2),
1257                    (long) read_register (FP0_REGNUM + 3),
1258                    (long) read_register (FP0_REGNUM + 4),
1259                    (long) read_register (FP0_REGNUM + 5),
1260                    (long) read_register (FP0_REGNUM + 6),
1261                    (long) read_register (FP0_REGNUM + 7));
1262   printf_filtered ((pr ?
1263                     "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" :
1264                     "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1265                    (long) read_register (FP0_REGNUM + 8),
1266                    (long) read_register (FP0_REGNUM + 9),
1267                    (long) read_register (FP0_REGNUM + 10),
1268                    (long) read_register (FP0_REGNUM + 11),
1269                    (long) read_register (FP0_REGNUM + 12),
1270                    (long) read_register (FP0_REGNUM + 13),
1271                    (long) read_register (FP0_REGNUM + 14),
1272                    (long) read_register (FP0_REGNUM + 15));
1273 }
1274
1275 static void
1276 sh_dsp_show_regs (void)
1277 {
1278   printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1279                    paddr (read_register (PC_REGNUM)),
1280                    (long) read_register (SR_REGNUM),
1281                    (long) read_register (PR_REGNUM),
1282                    (long) read_register (MACH_REGNUM),
1283                    (long) read_register (MACL_REGNUM));
1284
1285   printf_filtered ("GBR=%08lx VBR=%08lx",
1286                    (long) read_register (GBR_REGNUM),
1287                    (long) read_register (VBR_REGNUM));
1288
1289   printf_filtered (" DSR=%08lx", (long) read_register (DSR_REGNUM));
1290
1291   printf_filtered
1292     ("\nR0-R7  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1293      (long) read_register (0), (long) read_register (1),
1294      (long) read_register (2), (long) read_register (3),
1295      (long) read_register (4), (long) read_register (5),
1296      (long) read_register (6), (long) read_register (7));
1297   printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1298                    (long) read_register (8), (long) read_register (9),
1299                    (long) read_register (10), (long) read_register (11),
1300                    (long) read_register (12), (long) read_register (13),
1301                    (long) read_register (14), (long) read_register (15));
1302
1303   printf_filtered
1304     ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1305      (long) read_register (A0G_REGNUM) & 0xff,
1306      (long) read_register (A0_REGNUM), (long) read_register (M0_REGNUM),
1307      (long) read_register (X0_REGNUM), (long) read_register (Y0_REGNUM),
1308      (long) read_register (RS_REGNUM), (long) read_register (MOD_REGNUM));
1309   printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1310                    (long) read_register (A1G_REGNUM) & 0xff,
1311                    (long) read_register (A1_REGNUM),
1312                    (long) read_register (M1_REGNUM),
1313                    (long) read_register (X1_REGNUM),
1314                    (long) read_register (Y1_REGNUM),
1315                    (long) read_register (RE_REGNUM));
1316 }
1317
1318 static void
1319 sh_show_regs_command (char *args, int from_tty)
1320 {
1321   if (sh_show_regs)
1322     (*sh_show_regs) ();
1323 }
1324
1325 /* Return the GDB type object for the "standard" data type
1326    of data in register N.  */
1327 static struct type *
1328 sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr)
1329 {
1330   if ((reg_nr >= FP0_REGNUM
1331        && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
1332     return builtin_type_float;
1333   else
1334     return builtin_type_int;
1335 }
1336
1337 static struct type *
1338 sh_sh4_build_float_register_type (int high)
1339 {
1340   struct type *temp;
1341
1342   temp = create_range_type (NULL, builtin_type_int, 0, high);
1343   return create_array_type (NULL, builtin_type_float, temp);
1344 }
1345
1346 static struct type *
1347 sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr)
1348 {
1349   if ((reg_nr >= FP0_REGNUM
1350        && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
1351     return builtin_type_float;
1352   else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
1353     return builtin_type_double;
1354   else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
1355     return sh_sh4_build_float_register_type (3);
1356   else
1357     return builtin_type_int;
1358 }
1359
1360 static struct type *
1361 sh_default_register_type (struct gdbarch *gdbarch, int reg_nr)
1362 {
1363   return builtin_type_int;
1364 }
1365
1366 /* On the sh4, the DRi pseudo registers are problematic if the target
1367    is little endian. When the user writes one of those registers, for
1368    instance with 'ser var $dr0=1', we want the double to be stored
1369    like this:
1370    fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1371    fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1372
1373    This corresponds to little endian byte order & big endian word
1374    order.  However if we let gdb write the register w/o conversion, it
1375    will write fr0 and fr1 this way:
1376    fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1377    fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1378    because it will consider fr0 and fr1 as a single LE stretch of memory.
1379
1380    To achieve what we want we must force gdb to store things in
1381    floatformat_ieee_double_littlebyte_bigword (which is defined in
1382    include/floatformat.h and libiberty/floatformat.c.
1383
1384    In case the target is big endian, there is no problem, the
1385    raw bytes will look like:
1386    fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
1387    fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1388
1389    The other pseudo registers (the FVs) also don't pose a problem
1390    because they are stored as 4 individual FP elements. */
1391
1392 static void
1393 sh_sh4_register_convert_to_virtual (int regnum, struct type *type,
1394                                     char *from, char *to)
1395 {
1396   if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
1397     {
1398       DOUBLEST val;
1399       floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
1400                                from, &val);
1401       store_typed_floating (to, type, val);
1402     }
1403   else
1404     error
1405       ("sh_register_convert_to_virtual called with non DR register number");
1406 }
1407
1408 static void
1409 sh_sh4_register_convert_to_raw (struct type *type, int regnum,
1410                                 const void *from, void *to)
1411 {
1412   if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
1413     {
1414       DOUBLEST val = extract_typed_floating (from, type);
1415       floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword,
1416                                  &val, to);
1417     }
1418   else
1419     error ("sh_register_convert_to_raw called with non DR register number");
1420 }
1421
1422 /* For vectors of 4 floating point registers. */
1423 static int
1424 fv_reg_base_num (int fv_regnum)
1425 {
1426   int fp_regnum;
1427
1428   fp_regnum = FP0_REGNUM + (fv_regnum - FV0_REGNUM) * 4;
1429   return fp_regnum;
1430 }
1431
1432 /* For double precision floating point registers, i.e 2 fp regs.*/
1433 static int
1434 dr_reg_base_num (int dr_regnum)
1435 {
1436   int fp_regnum;
1437
1438   fp_regnum = FP0_REGNUM + (dr_regnum - DR0_REGNUM) * 2;
1439   return fp_regnum;
1440 }
1441
1442 static void
1443 sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
1444                          int reg_nr, void *buffer)
1445 {
1446   int base_regnum, portion;
1447   char temp_buffer[MAX_REGISTER_SIZE];
1448
1449   if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
1450     {
1451       base_regnum = dr_reg_base_num (reg_nr);
1452
1453       /* Build the value in the provided buffer. */
1454       /* Read the real regs for which this one is an alias.  */
1455       for (portion = 0; portion < 2; portion++)
1456         regcache_raw_read (regcache, base_regnum + portion,
1457                            (temp_buffer
1458                             + register_size (gdbarch,
1459                                              base_regnum) * portion));
1460       /* We must pay attention to the endiannes. */
1461       sh_sh4_register_convert_to_virtual (reg_nr,
1462                                           gdbarch_register_type (gdbarch,
1463                                                                  reg_nr),
1464                                           temp_buffer, buffer);
1465     }
1466   else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
1467     {
1468       base_regnum = fv_reg_base_num (reg_nr);
1469
1470       /* Read the real regs for which this one is an alias.  */
1471       for (portion = 0; portion < 4; portion++)
1472         regcache_raw_read (regcache, base_regnum + portion,
1473                            ((char *) buffer
1474                             + register_size (gdbarch,
1475                                              base_regnum) * portion));
1476     }
1477 }
1478
1479 static void
1480 sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
1481                           int reg_nr, const void *buffer)
1482 {
1483   int base_regnum, portion;
1484   char temp_buffer[MAX_REGISTER_SIZE];
1485
1486   if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
1487     {
1488       base_regnum = dr_reg_base_num (reg_nr);
1489
1490       /* We must pay attention to the endiannes. */
1491       sh_sh4_register_convert_to_raw (gdbarch_register_type (gdbarch, reg_nr),
1492                                       reg_nr, buffer, temp_buffer);
1493
1494       /* Write the real regs for which this one is an alias.  */
1495       for (portion = 0; portion < 2; portion++)
1496         regcache_raw_write (regcache, base_regnum + portion,
1497                             (temp_buffer
1498                              + register_size (gdbarch,
1499                                               base_regnum) * portion));
1500     }
1501   else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
1502     {
1503       base_regnum = fv_reg_base_num (reg_nr);
1504
1505       /* Write the real regs for which this one is an alias.  */
1506       for (portion = 0; portion < 4; portion++)
1507         regcache_raw_write (regcache, base_regnum + portion,
1508                             ((char *) buffer
1509                              + register_size (gdbarch,
1510                                               base_regnum) * portion));
1511     }
1512 }
1513
1514 /* Floating point vector of 4 float registers. */
1515 static void
1516 do_fv_register_info (struct gdbarch *gdbarch, struct ui_file *file,
1517                      int fv_regnum)
1518 {
1519   int first_fp_reg_num = fv_reg_base_num (fv_regnum);
1520   fprintf_filtered (file, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
1521                     fv_regnum - FV0_REGNUM,
1522                     (int) read_register (first_fp_reg_num),
1523                     (int) read_register (first_fp_reg_num + 1),
1524                     (int) read_register (first_fp_reg_num + 2),
1525                     (int) read_register (first_fp_reg_num + 3));
1526 }
1527
1528 /* Double precision registers. */
1529 static void
1530 do_dr_register_info (struct gdbarch *gdbarch, struct ui_file *file,
1531                      int dr_regnum)
1532 {
1533   int first_fp_reg_num = dr_reg_base_num (dr_regnum);
1534
1535   fprintf_filtered (file, "dr%d\t0x%08x%08x\n",
1536                     dr_regnum - DR0_REGNUM,
1537                     (int) read_register (first_fp_reg_num),
1538                     (int) read_register (first_fp_reg_num + 1));
1539 }
1540
1541 static void
1542 sh_print_pseudo_register (struct gdbarch *gdbarch, struct ui_file *file,
1543                           int regnum)
1544 {
1545   if (regnum < NUM_REGS || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
1546     internal_error (__FILE__, __LINE__,
1547                     "Invalid pseudo register number %d\n", regnum);
1548   else if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
1549     do_dr_register_info (gdbarch, file, regnum);
1550   else if (regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM)
1551     do_fv_register_info (gdbarch, file, regnum);
1552 }
1553
1554 static void
1555 sh_do_fp_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
1556 {                               /* do values for FP (float) regs */
1557   char *raw_buffer;
1558   double flt;                   /* double extracted from raw hex data */
1559   int inv;
1560   int j;
1561
1562   /* Allocate space for the float. */
1563   raw_buffer = (char *) alloca (register_size (gdbarch, FP0_REGNUM));
1564
1565   /* Get the data in raw format.  */
1566   if (!frame_register_read (get_selected_frame (), regnum, raw_buffer))
1567     error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
1568
1569   /* Get the register as a number */
1570   flt = unpack_double (builtin_type_float, raw_buffer, &inv);
1571
1572   /* Print the name and some spaces. */
1573   fputs_filtered (REGISTER_NAME (regnum), file);
1574   print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
1575
1576   /* Print the value. */
1577   if (inv)
1578     fprintf_filtered (file, "<invalid float>");
1579   else
1580     fprintf_filtered (file, "%-10.9g", flt);
1581
1582   /* Print the fp register as hex. */
1583   fprintf_filtered (file, "\t(raw 0x");
1584   for (j = 0; j < register_size (gdbarch, regnum); j++)
1585     {
1586       int idx = (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
1587                  ? j
1588                  : register_size (gdbarch, regnum) - 1 - j);
1589       fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[idx]);
1590     }
1591   fprintf_filtered (file, ")");
1592   fprintf_filtered (file, "\n");
1593 }
1594
1595 static void
1596 sh_do_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
1597 {
1598   char raw_buffer[MAX_REGISTER_SIZE];
1599
1600   fputs_filtered (REGISTER_NAME (regnum), file);
1601   print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
1602
1603   /* Get the data in raw format.  */
1604   if (!frame_register_read (get_selected_frame (), regnum, raw_buffer))
1605     fprintf_filtered (file, "*value not available*\n");
1606
1607   val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
1608              file, 'x', 1, 0, Val_pretty_default);
1609   fprintf_filtered (file, "\t");
1610   val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
1611              file, 0, 1, 0, Val_pretty_default);
1612   fprintf_filtered (file, "\n");
1613 }
1614
1615 static void
1616 sh_print_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
1617 {
1618   if (regnum < 0 || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
1619     internal_error (__FILE__, __LINE__,
1620                     "Invalid register number %d\n", regnum);
1621
1622   else if (regnum >= 0 && regnum < NUM_REGS)
1623     {
1624       if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) ==
1625           TYPE_CODE_FLT)
1626         sh_do_fp_register (gdbarch, file, regnum);      /* FP regs */
1627       else
1628         sh_do_register (gdbarch, file, regnum); /* All other regs */
1629     }
1630
1631   else if (regnum < NUM_REGS + NUM_PSEUDO_REGS)
1632     {
1633       sh_print_pseudo_register (gdbarch, file, regnum);
1634     }
1635 }
1636
1637 static void
1638 sh_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
1639                          struct frame_info *frame, int regnum, int fpregs)
1640 {
1641   if (regnum != -1)             /* do one specified register */
1642     {
1643       if (*(REGISTER_NAME (regnum)) == '\0')
1644         error ("Not a valid register for the current processor type");
1645
1646       sh_print_register (gdbarch, file, regnum);
1647     }
1648   else
1649     /* do all (or most) registers */
1650     {
1651       regnum = 0;
1652       while (regnum < NUM_REGS)
1653         {
1654           /* If the register name is empty, it is undefined for this
1655              processor, so don't display anything.  */
1656           if (REGISTER_NAME (regnum) == NULL
1657               || *(REGISTER_NAME (regnum)) == '\0')
1658             {
1659               regnum++;
1660               continue;
1661             }
1662
1663           if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) ==
1664               TYPE_CODE_FLT)
1665             {
1666               if (fpregs)
1667                 {
1668                   /* true for "INFO ALL-REGISTERS" command */
1669                   sh_do_fp_register (gdbarch, file, regnum);    /* FP regs */
1670                   regnum++;
1671                 }
1672               else
1673                 regnum += (FP_LAST_REGNUM - FP0_REGNUM);        /* skip FP regs */
1674             }
1675           else
1676             {
1677               sh_do_register (gdbarch, file, regnum);   /* All other regs */
1678               regnum++;
1679             }
1680         }
1681
1682       if (fpregs)
1683         while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
1684           {
1685             sh_print_pseudo_register (gdbarch, file, regnum);
1686             regnum++;
1687           }
1688     }
1689 }
1690
1691 #ifdef SVR4_SHARED_LIBS
1692
1693 /* Fetch (and possibly build) an appropriate link_map_offsets structure
1694    for native i386 linux targets using the struct offsets defined in
1695    link.h (but without actual reference to that file).
1696
1697    This makes it possible to access i386-linux shared libraries from
1698    a gdb that was not built on an i386-linux host (for cross debugging).
1699    */
1700
1701 struct link_map_offsets *
1702 sh_linux_svr4_fetch_link_map_offsets (void)
1703 {
1704   static struct link_map_offsets lmo;
1705   static struct link_map_offsets *lmp = 0;
1706
1707   if (lmp == 0)
1708     {
1709       lmp = &lmo;
1710
1711       lmo.r_debug_size = 8;     /* 20 not actual size but all we need */
1712
1713       lmo.r_map_offset = 4;
1714       lmo.r_map_size = 4;
1715
1716       lmo.link_map_size = 20;   /* 552 not actual size but all we need */
1717
1718       lmo.l_addr_offset = 0;
1719       lmo.l_addr_size = 4;
1720
1721       lmo.l_name_offset = 4;
1722       lmo.l_name_size = 4;
1723
1724       lmo.l_next_offset = 12;
1725       lmo.l_next_size = 4;
1726
1727       lmo.l_prev_offset = 16;
1728       lmo.l_prev_size = 4;
1729     }
1730
1731   return lmp;
1732 }
1733 #endif /* SVR4_SHARED_LIBS */
1734
1735 static int
1736 sh_dsp_register_sim_regno (int nr)
1737 {
1738   if (legacy_register_sim_regno (nr) < 0)
1739     return legacy_register_sim_regno (nr);
1740   if (nr >= DSR_REGNUM && nr <= Y1_REGNUM)
1741     return nr - DSR_REGNUM + SIM_SH_DSR_REGNUM;
1742   if (nr == MOD_REGNUM)
1743     return SIM_SH_MOD_REGNUM;
1744   if (nr == RS_REGNUM)
1745     return SIM_SH_RS_REGNUM;
1746   if (nr == RE_REGNUM)
1747     return SIM_SH_RE_REGNUM;
1748   if (nr >= R0_BANK_REGNUM && nr <= R7_BANK_REGNUM)
1749     return nr - R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM;
1750   return nr;
1751 }
1752
1753 static struct sh_frame_cache *
1754 sh_alloc_frame_cache (void)
1755 {
1756   struct sh_frame_cache *cache;
1757   int i;
1758
1759   cache = FRAME_OBSTACK_ZALLOC (struct sh_frame_cache);
1760
1761   /* Base address.  */
1762   cache->base = 0;
1763   cache->saved_sp = 0;
1764   cache->sp_offset = 0;
1765   cache->pc = 0;
1766
1767   /* Frameless until proven otherwise.  */
1768   cache->uses_fp = 0;
1769
1770   /* Saved registers.  We initialize these to -1 since zero is a valid
1771      offset (that's where fp is supposed to be stored).  */
1772   for (i = 0; i < SH_NUM_REGS; i++)
1773     {
1774       cache->saved_regs[i] = -1;
1775     }
1776
1777   return cache;
1778 }
1779
1780 static struct sh_frame_cache *
1781 sh_frame_cache (struct frame_info *next_frame, void **this_cache)
1782 {
1783   struct sh_frame_cache *cache;
1784   CORE_ADDR current_pc;
1785   int i;
1786
1787   if (*this_cache)
1788     return *this_cache;
1789
1790   cache = sh_alloc_frame_cache ();
1791   *this_cache = cache;
1792
1793   /* In principle, for normal frames, fp holds the frame pointer,
1794      which holds the base address for the current stack frame.
1795      However, for functions that don't need it, the frame pointer is
1796      optional.  For these "frameless" functions the frame pointer is
1797      actually the frame pointer of the calling frame. */
1798   cache->base = frame_unwind_register_unsigned (next_frame, FP_REGNUM);
1799   if (cache->base == 0)
1800     return cache;
1801
1802   cache->pc = frame_func_unwind (next_frame);
1803   current_pc = frame_pc_unwind (next_frame);
1804   if (cache->pc != 0)
1805     sh_analyze_prologue (cache->pc, current_pc, cache);
1806
1807   if (!cache->uses_fp)
1808     {
1809       /* We didn't find a valid frame, which means that CACHE->base
1810          currently holds the frame pointer for our calling frame.  If
1811          we're at the start of a function, or somewhere half-way its
1812          prologue, the function's frame probably hasn't been fully
1813          setup yet.  Try to reconstruct the base address for the stack
1814          frame by looking at the stack pointer.  For truly "frameless"
1815          functions this might work too.  */
1816       cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
1817     }
1818
1819   /* Now that we have the base address for the stack frame we can
1820      calculate the value of sp in the calling frame.  */
1821   cache->saved_sp = cache->base + cache->sp_offset;
1822
1823   /* Adjust all the saved registers such that they contain addresses
1824      instead of offsets.  */
1825   for (i = 0; i < SH_NUM_REGS; i++)
1826     if (cache->saved_regs[i] != -1)
1827       cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i] - 4;
1828
1829   return cache;
1830 }
1831
1832 static void
1833 sh_frame_prev_register (struct frame_info *next_frame, void **this_cache,
1834                         int regnum, int *optimizedp,
1835                         enum lval_type *lvalp, CORE_ADDR *addrp,
1836                         int *realnump, void *valuep)
1837 {
1838   struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
1839
1840   gdb_assert (regnum >= 0);
1841
1842   if (regnum == SP_REGNUM && cache->saved_sp)
1843     {
1844       *optimizedp = 0;
1845       *lvalp = not_lval;
1846       *addrp = 0;
1847       *realnump = -1;
1848       if (valuep)
1849         {
1850           /* Store the value.  */
1851           store_unsigned_integer (valuep, 4, cache->saved_sp);
1852         }
1853       return;
1854     }
1855
1856   /* The PC of the previous frame is stored in the PR register of
1857      the current frame.  Frob regnum so that we pull the value from
1858      the correct place.  */
1859   if (regnum == PC_REGNUM)
1860     regnum = PR_REGNUM;
1861
1862   if (regnum < SH_NUM_REGS && cache->saved_regs[regnum] != -1)
1863     {
1864       *optimizedp = 0;
1865       *lvalp = lval_memory;
1866       *addrp = cache->saved_regs[regnum];
1867       *realnump = -1;
1868       if (valuep)
1869         {
1870           /* Read the value in from memory.  */
1871           read_memory (*addrp, valuep,
1872                        register_size (current_gdbarch, regnum));
1873         }
1874       return;
1875     }
1876
1877   frame_register_unwind (next_frame, regnum,
1878                          optimizedp, lvalp, addrp, realnump, valuep);
1879 }
1880
1881 static void
1882 sh_frame_this_id (struct frame_info *next_frame, void **this_cache,
1883                   struct frame_id *this_id)
1884 {
1885   struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
1886
1887   /* This marks the outermost frame.  */
1888   if (cache->base == 0)
1889     return;
1890
1891   *this_id = frame_id_build (cache->saved_sp, cache->pc);
1892 }
1893
1894 static const struct frame_unwind sh_frame_unwind = {
1895   NORMAL_FRAME,
1896   sh_frame_this_id,
1897   sh_frame_prev_register
1898 };
1899
1900 static const struct frame_unwind *
1901 sh_frame_sniffer (struct frame_info *next_frame)
1902 {
1903   return &sh_frame_unwind;
1904 }
1905
1906 static CORE_ADDR
1907 sh_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1908 {
1909   return frame_unwind_register_unsigned (next_frame, SP_REGNUM);
1910 }
1911
1912 static CORE_ADDR
1913 sh_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1914 {
1915   return frame_unwind_register_unsigned (next_frame, PC_REGNUM);
1916 }
1917
1918 static struct frame_id
1919 sh_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
1920 {
1921   return frame_id_build (sh_unwind_sp (gdbarch, next_frame),
1922                          frame_pc_unwind (next_frame));
1923 }
1924
1925 static CORE_ADDR
1926 sh_frame_base_address (struct frame_info *next_frame, void **this_cache)
1927 {
1928   struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
1929
1930   return cache->base;
1931 }
1932
1933 static const struct frame_base sh_frame_base = {
1934   &sh_frame_unwind,
1935   sh_frame_base_address,
1936   sh_frame_base_address,
1937   sh_frame_base_address
1938 };
1939
1940 /* The epilogue is defined here as the area at the end of a function,
1941    either on the `ret' instruction itself or after an instruction which
1942    destroys the function's stack frame. */
1943 static int
1944 sh_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
1945 {
1946   CORE_ADDR func_addr = 0, func_end = 0;
1947
1948   if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
1949     {
1950       ULONGEST inst;
1951       /* The sh epilogue is max. 14 bytes long.  Give another 14 bytes
1952          for a nop and some fixed data (e.g. big offsets) which are
1953          unfortunately also treated as part of the function (which
1954          means, they are below func_end. */
1955       CORE_ADDR addr = func_end - 28;
1956       if (addr < func_addr + 4)
1957         addr = func_addr + 4;
1958       if (pc < addr)
1959         return 0;
1960
1961       /* First search forward until hitting an rts. */
1962       while (addr < func_end
1963              && !IS_RTS (read_memory_unsigned_integer (addr, 2)))
1964         addr += 2;
1965       if (addr >= func_end)
1966         return 0;
1967
1968       /* At this point we should find a mov.l @r15+,r14 instruction,
1969          either before or after the rts.  If not, then the function has
1970          probably no "normal" epilogue and we bail out here. */
1971       inst = read_memory_unsigned_integer (addr - 2, 2);
1972       if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2)))
1973         addr -= 2;
1974       else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2)))
1975         return 0;
1976
1977       /* Step over possible lds.l @r15+,pr. */
1978       inst = read_memory_unsigned_integer (addr - 2, 2);
1979       if (IS_LDS (inst))
1980         {
1981           addr -= 2;
1982           inst = read_memory_unsigned_integer (addr - 2, 2);
1983         }
1984
1985       /* Step over possible mov r14,r15. */
1986       if (IS_MOV_FP_SP (inst))
1987         {
1988           addr -= 2;
1989           inst = read_memory_unsigned_integer (addr - 2, 2);
1990         }
1991
1992       /* Now check for FP adjustments, using add #imm,r14 or add rX, r14
1993          instructions. */
1994       while (addr > func_addr + 4
1995              && (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst)))
1996         {
1997           addr -= 2;
1998           inst = read_memory_unsigned_integer (addr - 2, 2);
1999         }
2000
2001       if (pc >= addr)
2002         return 1;
2003     }
2004   return 0;
2005 }
2006
2007 static gdbarch_init_ftype sh_gdbarch_init;
2008
2009 static struct gdbarch *
2010 sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2011 {
2012   struct gdbarch *gdbarch;
2013
2014   sh_show_regs = sh_generic_show_regs;
2015   switch (info.bfd_arch_info->mach)
2016     {
2017     case bfd_mach_sh2e:
2018       sh_show_regs = sh2e_show_regs;
2019       break;
2020     case bfd_mach_sh_dsp:
2021       sh_show_regs = sh_dsp_show_regs;
2022       break;
2023
2024     case bfd_mach_sh3:
2025       sh_show_regs = sh3_show_regs;
2026       break;
2027
2028     case bfd_mach_sh3e:
2029       sh_show_regs = sh3e_show_regs;
2030       break;
2031
2032     case bfd_mach_sh3_dsp:
2033       sh_show_regs = sh3_dsp_show_regs;
2034       break;
2035
2036     case bfd_mach_sh4:
2037       sh_show_regs = sh4_show_regs;
2038       break;
2039
2040     case bfd_mach_sh5:
2041       sh_show_regs = sh64_show_regs;
2042       /* SH5 is handled entirely in sh64-tdep.c */
2043       return sh64_gdbarch_init (info, arches);
2044     }
2045
2046   /* If there is already a candidate, use it.  */
2047   arches = gdbarch_list_lookup_by_info (arches, &info);
2048   if (arches != NULL)
2049     return arches->gdbarch;
2050
2051   /* None found, create a new architecture from the information
2052      provided. */
2053   gdbarch = gdbarch_alloc (&info, NULL);
2054
2055   set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2056   set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2057   set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2058   set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2059   set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2060   set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2061   set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2062   set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2063
2064   set_gdbarch_num_regs (gdbarch, SH_NUM_REGS);
2065   set_gdbarch_sp_regnum (gdbarch, 15);
2066   set_gdbarch_pc_regnum (gdbarch, 16);
2067   set_gdbarch_fp0_regnum (gdbarch, -1);
2068   set_gdbarch_num_pseudo_regs (gdbarch, 0);
2069
2070   set_gdbarch_register_type (gdbarch, sh_default_register_type);
2071
2072   set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info);
2073
2074   set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);
2075   set_gdbarch_use_struct_convention (gdbarch, sh_use_struct_convention);
2076
2077   set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh);
2078   set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
2079
2080   set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
2081
2082   set_gdbarch_store_return_value (gdbarch, sh_default_store_return_value);
2083   set_gdbarch_extract_return_value (gdbarch, sh_default_extract_return_value);
2084   set_gdbarch_extract_struct_value_address (gdbarch,
2085                                             sh_extract_struct_value_address);
2086
2087   set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
2088   set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2089   set_gdbarch_decr_pc_after_break (gdbarch, 0);
2090   set_gdbarch_function_start_offset (gdbarch, 0);
2091
2092   set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu);
2093
2094   set_gdbarch_frame_args_skip (gdbarch, 0);
2095   set_gdbarch_frameless_function_invocation (gdbarch,
2096                                              frameless_look_for_prologue);
2097   set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2098
2099   set_gdbarch_frame_align (gdbarch, sh_frame_align);
2100   set_gdbarch_unwind_sp (gdbarch, sh_unwind_sp);
2101   set_gdbarch_unwind_pc (gdbarch, sh_unwind_pc);
2102   set_gdbarch_unwind_dummy_id (gdbarch, sh_unwind_dummy_id);
2103   frame_base_set_default (gdbarch, &sh_frame_base);
2104
2105   set_gdbarch_in_function_epilogue_p (gdbarch, sh_in_function_epilogue_p);
2106
2107   switch (info.bfd_arch_info->mach)
2108     {
2109     case bfd_mach_sh:
2110       set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2111       break;
2112
2113     case bfd_mach_sh2:
2114       set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2115       break;
2116
2117     case bfd_mach_sh2e:
2118       /* doubles on sh2e and sh3e are actually 4 byte. */
2119       set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2120
2121       set_gdbarch_register_name (gdbarch, sh_sh2e_register_name);
2122       set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2123       set_gdbarch_fp0_regnum (gdbarch, 25);
2124       set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
2125       set_gdbarch_extract_return_value (gdbarch,
2126                                         sh3e_sh4_extract_return_value);
2127       set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2128       break;
2129
2130     case bfd_mach_sh_dsp:
2131       set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name);
2132       set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2133       break;
2134
2135     case bfd_mach_sh3:
2136       set_gdbarch_register_name (gdbarch, sh_sh3_register_name);
2137       break;
2138
2139     case bfd_mach_sh3e:
2140       /* doubles on sh2e and sh3e are actually 4 byte. */
2141       set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2142
2143       set_gdbarch_register_name (gdbarch, sh_sh3e_register_name);
2144       set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2145       set_gdbarch_fp0_regnum (gdbarch, 25);
2146       set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
2147       set_gdbarch_extract_return_value (gdbarch,
2148                                         sh3e_sh4_extract_return_value);
2149       set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2150       break;
2151
2152     case bfd_mach_sh3_dsp:
2153       set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name);
2154       set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2155       break;
2156
2157     case bfd_mach_sh4:
2158       set_gdbarch_register_name (gdbarch, sh_sh4_register_name);
2159       set_gdbarch_register_type (gdbarch, sh_sh4_register_type);
2160       set_gdbarch_fp0_regnum (gdbarch, 25);
2161       set_gdbarch_num_pseudo_regs (gdbarch, 12);
2162       set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2163       set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
2164       set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
2165       set_gdbarch_extract_return_value (gdbarch,
2166                                         sh3e_sh4_extract_return_value);
2167       set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2168       break;
2169
2170     default:
2171       set_gdbarch_register_name (gdbarch, sh_generic_register_name);
2172       break;
2173     }
2174
2175   /* Hook in ABI-specific overrides, if they have been registered.  */
2176   gdbarch_init_osabi (info, gdbarch);
2177
2178   frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer);
2179   frame_unwind_append_sniffer (gdbarch, sh_frame_sniffer);
2180
2181   return gdbarch;
2182 }
2183
2184 extern initialize_file_ftype _initialize_sh_tdep;       /* -Wmissing-prototypes */
2185
2186 void
2187 _initialize_sh_tdep (void)
2188 {
2189   struct cmd_list_element *c;
2190
2191   gdbarch_register (bfd_arch_sh, sh_gdbarch_init, NULL);
2192
2193   add_com ("regs", class_vars, sh_show_regs_command, "Print all registers");
2194 }