1 /* Target-dependent code for Renesas Super-H, for GDB.
3 Copyright (C) 1993-2005, 2007-2012 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20 /* Contributed by Steve Chamberlain
25 #include "frame-base.h"
26 #include "frame-unwind.h"
27 #include "dwarf2-frame.h"
35 #include "gdb_string.h"
36 #include "gdb_assert.h"
37 #include "arch-utils.h"
38 #include "floatformat.h"
42 #include "reggroups.h"
48 #include "solib-svr4.h"
53 /* registers numbers shared with the simulator. */
54 #include "gdb/sim-sh.h"
56 /* List of "set sh ..." and "show sh ..." commands. */
57 static struct cmd_list_element
*setshcmdlist
= NULL
;
58 static struct cmd_list_element
*showshcmdlist
= NULL
;
60 static const char sh_cc_gcc
[] = "gcc";
61 static const char sh_cc_renesas
[] = "renesas";
62 static const char *const sh_cc_enum
[] = {
68 static const char *sh_active_calling_convention
= sh_cc_gcc
;
70 static void (*sh_show_regs
) (struct frame_info
*);
72 #define SH_NUM_REGS 67
81 /* Flag showing that a frame has been created in the prologue code. */
84 /* Saved registers. */
85 CORE_ADDR saved_regs
[SH_NUM_REGS
];
90 sh_is_renesas_calling_convention (struct type
*func_type
)
96 func_type
= check_typedef (func_type
);
98 if (TYPE_CODE (func_type
) == TYPE_CODE_PTR
)
99 func_type
= check_typedef (TYPE_TARGET_TYPE (func_type
));
101 if (TYPE_CODE (func_type
) == TYPE_CODE_FUNC
102 && TYPE_CALLING_CONVENTION (func_type
) == DW_CC_GNU_renesas_sh
)
106 if (sh_active_calling_convention
== sh_cc_renesas
)
113 sh_sh_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
115 static char *register_names
[] = {
116 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
117 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
118 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
120 "", "", "", "", "", "", "", "",
121 "", "", "", "", "", "", "", "",
123 "", "", "", "", "", "", "", "",
124 "", "", "", "", "", "", "", "",
125 "", "", "", "", "", "", "", "",
129 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
131 return register_names
[reg_nr
];
135 sh_sh3_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
137 static char *register_names
[] = {
138 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
139 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
140 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
142 "", "", "", "", "", "", "", "",
143 "", "", "", "", "", "", "", "",
145 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
146 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
147 "", "", "", "", "", "", "", "",
151 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
153 return register_names
[reg_nr
];
157 sh_sh3e_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
159 static char *register_names
[] = {
160 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
161 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
162 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
164 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
165 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
167 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
168 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
169 "", "", "", "", "", "", "", "",
173 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
175 return register_names
[reg_nr
];
179 sh_sh2e_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
181 static char *register_names
[] = {
182 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
183 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
184 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
186 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
187 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
189 "", "", "", "", "", "", "", "",
190 "", "", "", "", "", "", "", "",
191 "", "", "", "", "", "", "", "",
195 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
197 return register_names
[reg_nr
];
201 sh_sh2a_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
203 static char *register_names
[] = {
204 /* general registers 0-15 */
205 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
206 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
208 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
211 /* floating point registers 25 - 40 */
212 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
213 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
216 /* 43 - 62. Banked registers. The bank number used is determined by
217 the bank register (63). */
218 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
219 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
220 "machb", "ivnb", "prb", "gbrb", "maclb",
221 /* 63: register bank number, not a real register but used to
222 communicate the register bank currently get/set. This register
223 is hidden to the user, who manipulates it using the pseudo
224 register called "bank" (67). See below. */
227 "ibcr", "ibnr", "tbr",
228 /* 67: register bank number, the user visible pseudo register. */
230 /* double precision (pseudo) 68 - 75 */
231 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
235 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
237 return register_names
[reg_nr
];
241 sh_sh2a_nofpu_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
243 static char *register_names
[] = {
244 /* general registers 0-15 */
245 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
246 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
248 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
251 /* floating point registers 25 - 40 */
252 "", "", "", "", "", "", "", "",
253 "", "", "", "", "", "", "", "",
256 /* 43 - 62. Banked registers. The bank number used is determined by
257 the bank register (63). */
258 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
259 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
260 "machb", "ivnb", "prb", "gbrb", "maclb",
261 /* 63: register bank number, not a real register but used to
262 communicate the register bank currently get/set. This register
263 is hidden to the user, who manipulates it using the pseudo
264 register called "bank" (67). See below. */
267 "ibcr", "ibnr", "tbr",
268 /* 67: register bank number, the user visible pseudo register. */
270 /* double precision (pseudo) 68 - 75 */
271 "", "", "", "", "", "", "", "",
275 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
277 return register_names
[reg_nr
];
281 sh_sh_dsp_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
283 static char *register_names
[] = {
284 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
285 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
286 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
288 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
289 "y0", "y1", "", "", "", "", "", "mod",
291 "rs", "re", "", "", "", "", "", "",
292 "", "", "", "", "", "", "", "",
293 "", "", "", "", "", "", "", "",
297 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
299 return register_names
[reg_nr
];
303 sh_sh3_dsp_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
305 static char *register_names
[] = {
306 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
307 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
308 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
310 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
311 "y0", "y1", "", "", "", "", "", "mod",
313 "rs", "re", "", "", "", "", "", "",
314 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
315 "", "", "", "", "", "", "", "",
316 "", "", "", "", "", "", "", "",
320 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
322 return register_names
[reg_nr
];
326 sh_sh4_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
328 static char *register_names
[] = {
329 /* general registers 0-15 */
330 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
331 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
333 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
336 /* floating point registers 25 - 40 */
337 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
338 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
342 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
344 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
345 "", "", "", "", "", "", "", "",
346 /* pseudo bank register. */
348 /* double precision (pseudo) 59 - 66 */
349 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
350 /* vectors (pseudo) 67 - 70 */
351 "fv0", "fv4", "fv8", "fv12",
352 /* FIXME: missing XF 71 - 86 */
353 /* FIXME: missing XD 87 - 94 */
357 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
359 return register_names
[reg_nr
];
363 sh_sh4_nofpu_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
365 static char *register_names
[] = {
366 /* general registers 0-15 */
367 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
368 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
370 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
373 /* floating point registers 25 - 40 -- not for nofpu target */
374 "", "", "", "", "", "", "", "",
375 "", "", "", "", "", "", "", "",
379 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
381 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
382 "", "", "", "", "", "", "", "",
383 /* pseudo bank register. */
385 /* double precision (pseudo) 59 - 66 -- not for nofpu target */
386 "", "", "", "", "", "", "", "",
387 /* vectors (pseudo) 67 - 70 -- not for nofpu target */
392 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
394 return register_names
[reg_nr
];
398 sh_sh4al_dsp_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
400 static char *register_names
[] = {
401 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
402 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
403 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
405 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
406 "y0", "y1", "", "", "", "", "", "mod",
408 "rs", "re", "", "", "", "", "", "",
409 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
410 "", "", "", "", "", "", "", "",
411 "", "", "", "", "", "", "", "",
415 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
417 return register_names
[reg_nr
];
420 static const unsigned char *
421 sh_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
, int *lenptr
)
423 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes. */
424 static unsigned char breakpoint
[] = { 0xc3, 0xc3 };
426 /* For remote stub targets, trapa #20 is used. */
427 if (strcmp (target_shortname
, "remote") == 0)
429 static unsigned char big_remote_breakpoint
[] = { 0xc3, 0x20 };
430 static unsigned char little_remote_breakpoint
[] = { 0x20, 0xc3 };
432 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
434 *lenptr
= sizeof (big_remote_breakpoint
);
435 return big_remote_breakpoint
;
439 *lenptr
= sizeof (little_remote_breakpoint
);
440 return little_remote_breakpoint
;
444 *lenptr
= sizeof (breakpoint
);
448 /* Prologue looks like
452 sub <room_for_loca_vars>,r15
455 Actually it can be more complicated than this but that's it, basically. */
457 #define GET_SOURCE_REG(x) (((x) >> 4) & 0xf)
458 #define GET_TARGET_REG(x) (((x) >> 8) & 0xf)
460 /* JSR @Rm 0100mmmm00001011 */
461 #define IS_JSR(x) (((x) & 0xf0ff) == 0x400b)
463 /* STS.L PR,@-r15 0100111100100010
464 r15-4-->r15, PR-->(r15) */
465 #define IS_STS(x) ((x) == 0x4f22)
467 /* STS.L MACL,@-r15 0100111100010010
468 r15-4-->r15, MACL-->(r15) */
469 #define IS_MACL_STS(x) ((x) == 0x4f12)
471 /* MOV.L Rm,@-r15 00101111mmmm0110
472 r15-4-->r15, Rm-->(R15) */
473 #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
475 /* MOV r15,r14 0110111011110011
477 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
479 /* ADD #imm,r15 01111111iiiiiiii
481 #define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00)
483 #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
484 #define IS_SHLL_R3(x) ((x) == 0x4300)
486 /* ADD r3,r15 0011111100111100
488 #define IS_ADD_R3SP(x) ((x) == 0x3f3c)
490 /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
491 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
492 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
493 /* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to
494 make this entirely clear. */
495 /* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */
496 #define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b)
498 /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */
499 #define IS_MOV_ARG_TO_REG(x) \
500 (((x) & 0xf00f) == 0x6003 && \
501 ((x) & 0x00f0) >= 0x0040 && \
502 ((x) & 0x00f0) <= 0x0070)
503 /* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */
504 #define IS_MOV_ARG_TO_IND_R14(x) \
505 (((x) & 0xff0f) == 0x2e02 && \
506 ((x) & 0x00f0) >= 0x0040 && \
507 ((x) & 0x00f0) <= 0x0070)
508 /* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */
509 #define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \
510 (((x) & 0xff00) == 0x1e00 && \
511 ((x) & 0x00f0) >= 0x0040 && \
512 ((x) & 0x00f0) <= 0x0070)
514 /* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */
515 #define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000)
516 /* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */
517 #define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000)
518 /* MOVI20 #imm20,Rn 0000nnnniiii0000 */
519 #define IS_MOVI20(x) (((x) & 0xf00f) == 0x0000)
520 /* SUB Rn,R15 00111111nnnn1000 */
521 #define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08)
523 #define FPSCR_SZ (1 << 20)
525 /* The following instructions are used for epilogue testing. */
526 #define IS_RESTORE_FP(x) ((x) == 0x6ef6)
527 #define IS_RTS(x) ((x) == 0x000b)
528 #define IS_LDS(x) ((x) == 0x4f26)
529 #define IS_MACL_LDS(x) ((x) == 0x4f16)
530 #define IS_MOV_FP_SP(x) ((x) == 0x6fe3)
531 #define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c)
532 #define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00)
535 sh_analyze_prologue (struct gdbarch
*gdbarch
,
536 CORE_ADDR pc
, CORE_ADDR current_pc
,
537 struct sh_frame_cache
*cache
, ULONGEST fpscr
)
539 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
545 int reg
, sav_reg
= -1;
547 if (pc
>= current_pc
)
551 for (opc
= pc
+ (2 * 28); pc
< opc
; pc
+= 2)
553 inst
= read_memory_unsigned_integer (pc
, 2, byte_order
);
554 /* See where the registers will be saved to. */
557 cache
->saved_regs
[GET_SOURCE_REG (inst
)] = cache
->sp_offset
;
558 cache
->sp_offset
+= 4;
560 else if (IS_STS (inst
))
562 cache
->saved_regs
[PR_REGNUM
] = cache
->sp_offset
;
563 cache
->sp_offset
+= 4;
565 else if (IS_MACL_STS (inst
))
567 cache
->saved_regs
[MACL_REGNUM
] = cache
->sp_offset
;
568 cache
->sp_offset
+= 4;
570 else if (IS_MOV_R3 (inst
))
572 r3_val
= ((inst
& 0xff) ^ 0x80) - 0x80;
574 else if (IS_SHLL_R3 (inst
))
578 else if (IS_ADD_R3SP (inst
))
580 cache
->sp_offset
+= -r3_val
;
582 else if (IS_ADD_IMM_SP (inst
))
584 offset
= ((inst
& 0xff) ^ 0x80) - 0x80;
585 cache
->sp_offset
-= offset
;
587 else if (IS_MOVW_PCREL_TO_REG (inst
))
591 reg
= GET_TARGET_REG (inst
);
595 offset
= (inst
& 0xff) << 1;
597 read_memory_integer ((pc
+ 4) + offset
, 2, byte_order
);
601 else if (IS_MOVL_PCREL_TO_REG (inst
))
605 reg
= GET_TARGET_REG (inst
);
609 offset
= (inst
& 0xff) << 2;
611 read_memory_integer (((pc
& 0xfffffffc) + 4) + offset
,
616 else if (IS_MOVI20 (inst
))
620 reg
= GET_TARGET_REG (inst
);
624 sav_offset
= GET_SOURCE_REG (inst
) << 16;
625 /* MOVI20 is a 32 bit instruction! */
628 |= read_memory_unsigned_integer (pc
, 2, byte_order
);
629 /* Now sav_offset contains an unsigned 20 bit value.
630 It must still get sign extended. */
631 if (sav_offset
& 0x00080000)
632 sav_offset
|= 0xfff00000;
636 else if (IS_SUB_REG_FROM_SP (inst
))
638 reg
= GET_SOURCE_REG (inst
);
639 if (sav_reg
> 0 && reg
== sav_reg
)
643 cache
->sp_offset
+= sav_offset
;
645 else if (IS_FPUSH (inst
))
647 if (fpscr
& FPSCR_SZ
)
649 cache
->sp_offset
+= 8;
653 cache
->sp_offset
+= 4;
656 else if (IS_MOV_SP_FP (inst
))
659 /* At this point, only allow argument register moves to other
660 registers or argument register moves to @(X,fp) which are
661 moving the register arguments onto the stack area allocated
662 by a former add somenumber to SP call. Don't allow moving
663 to an fp indirect address above fp + cache->sp_offset. */
665 for (opc
= pc
+ 12; pc
< opc
; pc
+= 2)
667 inst
= read_memory_integer (pc
, 2, byte_order
);
668 if (IS_MOV_ARG_TO_IND_R14 (inst
))
670 reg
= GET_SOURCE_REG (inst
);
671 if (cache
->sp_offset
> 0)
672 cache
->saved_regs
[reg
] = cache
->sp_offset
;
674 else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst
))
676 reg
= GET_SOURCE_REG (inst
);
677 offset
= (inst
& 0xf) * 4;
678 if (cache
->sp_offset
> offset
)
679 cache
->saved_regs
[reg
] = cache
->sp_offset
- offset
;
681 else if (IS_MOV_ARG_TO_REG (inst
))
688 else if (IS_JSR (inst
))
690 /* We have found a jsr that has been scheduled into the prologue.
691 If we continue the scan and return a pc someplace after this,
692 then setting a breakpoint on this function will cause it to
693 appear to be called after the function it is calling via the
694 jsr, which will be very confusing. Most likely the next
695 instruction is going to be IS_MOV_SP_FP in the delay slot. If
696 so, note that before returning the current pc. */
697 inst
= read_memory_integer (pc
+ 2, 2, byte_order
);
698 if (IS_MOV_SP_FP (inst
))
702 #if 0 /* This used to just stop when it found an instruction
703 that was not considered part of the prologue. Now,
704 we just keep going looking for likely
714 /* Skip any prologue before the guts of a function. */
716 /* Skip the prologue using the debug information. If this fails we'll
717 fall back on the 'guess' method below. */
719 after_prologue (CORE_ADDR pc
)
721 struct symtab_and_line sal
;
722 CORE_ADDR func_addr
, func_end
;
724 /* If we can not find the symbol in the partial symbol table, then
725 there is no hope we can determine the function's start address
727 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
730 /* Get the line associated with FUNC_ADDR. */
731 sal
= find_pc_line (func_addr
, 0);
733 /* There are only two cases to consider. First, the end of the source line
734 is within the function bounds. In that case we return the end of the
735 source line. Second is the end of the source line extends beyond the
736 bounds of the current function. We need to use the slow code to
737 examine instructions in that case. */
738 if (sal
.end
< func_end
)
745 sh_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
748 struct sh_frame_cache cache
;
750 /* See if we can determine the end of the prologue via the symbol table.
751 If so, then return either PC, or the PC after the prologue, whichever
753 pc
= after_prologue (start_pc
);
755 /* If after_prologue returned a useful address, then use it. Else
756 fall back on the instruction skipping code. */
758 return max (pc
, start_pc
);
760 cache
.sp_offset
= -4;
761 pc
= sh_analyze_prologue (gdbarch
, start_pc
, (CORE_ADDR
) -1, &cache
, 0);
770 Aggregate types not bigger than 8 bytes that have the same size and
771 alignment as one of the integer scalar types are returned in the
772 same registers as the integer type they match.
774 For example, a 2-byte aligned structure with size 2 bytes has the
775 same size and alignment as a short int, and will be returned in R0.
776 A 4-byte aligned structure with size 8 bytes has the same size and
777 alignment as a long long int, and will be returned in R0 and R1.
779 When an aggregate type is returned in R0 and R1, R0 contains the
780 first four bytes of the aggregate, and R1 contains the
781 remainder. If the size of the aggregate type is not a multiple of 4
782 bytes, the aggregate is tail-padded up to a multiple of 4
783 bytes. The value of the padding is undefined. For little-endian
784 targets the padding will appear at the most significant end of the
785 last element, for big-endian targets the padding appears at the
786 least significant end of the last element.
788 All other aggregate types are returned by address. The caller
789 function passes the address of an area large enough to hold the
790 aggregate value in R2. The called function stores the result in
793 To reiterate, structs smaller than 8 bytes could also be returned
794 in memory, if they don't pass the "same size and alignment as an
799 struct s { char c[3]; } wibble;
800 struct s foo(void) { return wibble; }
802 the return value from foo() will be in memory, not
803 in R0, because there is no 3-byte integer type.
807 struct s { char c[2]; } wibble;
808 struct s foo(void) { return wibble; }
810 because a struct containing two chars has alignment 1, that matches
811 type char, but size 2, that matches type short. There's no integer
812 type that has alignment 1 and size 2, so the struct is returned in
816 sh_use_struct_convention (int renesas_abi
, struct type
*type
)
818 int len
= TYPE_LENGTH (type
);
819 int nelem
= TYPE_NFIELDS (type
);
821 /* The Renesas ABI returns aggregate types always on stack. */
822 if (renesas_abi
&& (TYPE_CODE (type
) == TYPE_CODE_STRUCT
823 || TYPE_CODE (type
) == TYPE_CODE_UNION
))
826 /* Non-power of 2 length types and types bigger than 8 bytes (which don't
827 fit in two registers anyway) use struct convention. */
828 if (len
!= 1 && len
!= 2 && len
!= 4 && len
!= 8)
831 /* Scalar types and aggregate types with exactly one field are aligned
832 by definition. They are returned in registers. */
836 /* If the first field in the aggregate has the same length as the entire
837 aggregate type, the type is returned in registers. */
838 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, 0)) == len
)
841 /* If the size of the aggregate is 8 bytes and the first field is
842 of size 4 bytes its alignment is equal to long long's alignment,
843 so it's returned in registers. */
844 if (len
== 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type
, 0)) == 4)
847 /* Otherwise use struct convention. */
852 sh_use_struct_convention_nofpu (int renesas_abi
, struct type
*type
)
854 /* The Renesas ABI returns long longs/doubles etc. always on stack. */
855 if (renesas_abi
&& TYPE_NFIELDS (type
) == 0 && TYPE_LENGTH (type
) >= 8)
857 return sh_use_struct_convention (renesas_abi
, type
);
861 sh_frame_align (struct gdbarch
*ignore
, CORE_ADDR sp
)
866 /* Function: push_dummy_call (formerly push_arguments)
867 Setup the function arguments for calling a function in the inferior.
869 On the Renesas SH architecture, there are four registers (R4 to R7)
870 which are dedicated for passing function arguments. Up to the first
871 four arguments (depending on size) may go into these registers.
872 The rest go on the stack.
874 MVS: Except on SH variants that have floating point registers.
875 In that case, float and double arguments are passed in the same
876 manner, but using FP registers instead of GP registers.
878 Arguments that are smaller than 4 bytes will still take up a whole
879 register or a whole 32-bit word on the stack, and will be
880 right-justified in the register or the stack word. This includes
881 chars, shorts, and small aggregate types.
883 Arguments that are larger than 4 bytes may be split between two or
884 more registers. If there are not enough registers free, an argument
885 may be passed partly in a register (or registers), and partly on the
886 stack. This includes doubles, long longs, and larger aggregates.
887 As far as I know, there is no upper limit to the size of aggregates
888 that will be passed in this way; in other words, the convention of
889 passing a pointer to a large aggregate instead of a copy is not used.
891 MVS: The above appears to be true for the SH variants that do not
892 have an FPU, however those that have an FPU appear to copy the
893 aggregate argument onto the stack (and not place it in registers)
894 if it is larger than 16 bytes (four GP registers).
896 An exceptional case exists for struct arguments (and possibly other
897 aggregates such as arrays) if the size is larger than 4 bytes but
898 not a multiple of 4 bytes. In this case the argument is never split
899 between the registers and the stack, but instead is copied in its
900 entirety onto the stack, AND also copied into as many registers as
901 there is room for. In other words, space in registers permitting,
902 two copies of the same argument are passed in. As far as I can tell,
903 only the one on the stack is used, although that may be a function
904 of the level of compiler optimization. I suspect this is a compiler
905 bug. Arguments of these odd sizes are left-justified within the
906 word (as opposed to arguments smaller than 4 bytes, which are
909 If the function is to return an aggregate type such as a struct, it
910 is either returned in the normal return value register R0 (if its
911 size is no greater than one byte), or else the caller must allocate
912 space into which the callee will copy the return value (if the size
913 is greater than one byte). In this case, a pointer to the return
914 value location is passed into the callee in register R2, which does
915 not displace any of the other arguments passed in via registers R4
918 /* Helper function to justify value in register according to endianess. */
920 sh_justify_value_in_reg (struct gdbarch
*gdbarch
, struct value
*val
, int len
)
922 static char valbuf
[4];
924 memset (valbuf
, 0, sizeof (valbuf
));
927 /* value gets right-justified in the register or stack word. */
928 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
929 memcpy (valbuf
+ (4 - len
), (char *) value_contents (val
), len
);
931 memcpy (valbuf
, (char *) value_contents (val
), len
);
934 return (char *) value_contents (val
);
937 /* Helper function to eval number of bytes to allocate on stack. */
939 sh_stack_allocsize (int nargs
, struct value
**args
)
943 stack_alloc
+= ((TYPE_LENGTH (value_type (args
[nargs
])) + 3) & ~3);
947 /* Helper functions for getting the float arguments right. Registers usage
948 depends on the ABI and the endianess. The comments should enlighten how
949 it's intended to work. */
951 /* This array stores which of the float arg registers are already in use. */
952 static int flt_argreg_array
[FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
+ 1];
954 /* This function just resets the above array to "no reg used so far". */
956 sh_init_flt_argreg (void)
958 memset (flt_argreg_array
, 0, sizeof flt_argreg_array
);
961 /* This function returns the next register to use for float arg passing.
962 It returns either a valid value between FLOAT_ARG0_REGNUM and
963 FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns
964 FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available.
966 Note that register number 0 in flt_argreg_array corresponds with the
967 real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is
968 29) the parity of the register number is preserved, which is important
969 for the double register passing test (see the "argreg & 1" test below). */
971 sh_next_flt_argreg (struct gdbarch
*gdbarch
, int len
, struct type
*func_type
)
975 /* First search for the next free register. */
976 for (argreg
= 0; argreg
<= FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
;
978 if (!flt_argreg_array
[argreg
])
981 /* No register left? */
982 if (argreg
> FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
)
983 return FLOAT_ARGLAST_REGNUM
+ 1;
987 /* Doubles are always starting in a even register number. */
990 /* In gcc ABI, the skipped register is lost for further argument
991 passing now. Not so in Renesas ABI. */
992 if (!sh_is_renesas_calling_convention (func_type
))
993 flt_argreg_array
[argreg
] = 1;
997 /* No register left? */
998 if (argreg
> FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
)
999 return FLOAT_ARGLAST_REGNUM
+ 1;
1001 /* Also mark the next register as used. */
1002 flt_argreg_array
[argreg
+ 1] = 1;
1004 else if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
1005 && !sh_is_renesas_calling_convention (func_type
))
1007 /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */
1008 if (!flt_argreg_array
[argreg
+ 1])
1011 flt_argreg_array
[argreg
] = 1;
1012 return FLOAT_ARG0_REGNUM
+ argreg
;
1015 /* Helper function which figures out, if a type is treated like a float type.
1017 The FPU ABIs have a special way how to treat types as float types.
1018 Structures with exactly one member, which is of type float or double, are
1019 treated exactly as the base types float or double:
1029 are handled the same way as just
1035 As a result, arguments of these struct types are pushed into floating point
1036 registers exactly as floats or doubles, using the same decision algorithm.
1038 The same is valid if these types are used as function return types. The
1039 above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1
1040 or even using struct convention as it is for other structs. */
1043 sh_treat_as_flt_p (struct type
*type
)
1045 int len
= TYPE_LENGTH (type
);
1047 /* Ordinary float types are obviously treated as float. */
1048 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1050 /* Otherwise non-struct types are not treated as float. */
1051 if (TYPE_CODE (type
) != TYPE_CODE_STRUCT
)
1053 /* Otherwise structs with more than one memeber are not treated as float. */
1054 if (TYPE_NFIELDS (type
) != 1)
1056 /* Otherwise if the type of that member is float, the whole type is
1057 treated as float. */
1058 if (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0)) == TYPE_CODE_FLT
)
1060 /* Otherwise it's not treated as float. */
1065 sh_push_dummy_call_fpu (struct gdbarch
*gdbarch
,
1066 struct value
*function
,
1067 struct regcache
*regcache
,
1068 CORE_ADDR bp_addr
, int nargs
,
1069 struct value
**args
,
1070 CORE_ADDR sp
, int struct_return
,
1071 CORE_ADDR struct_addr
)
1073 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1074 int stack_offset
= 0;
1075 int argreg
= ARG0_REGNUM
;
1078 struct type
*func_type
= value_type (function
);
1082 int len
, reg_size
= 0;
1083 int pass_on_stack
= 0;
1085 int last_reg_arg
= INT_MAX
;
1087 /* The Renesas ABI expects all varargs arguments, plus the last
1088 non-vararg argument to be on the stack, no matter how many
1089 registers have been used so far. */
1090 if (sh_is_renesas_calling_convention (func_type
)
1091 && TYPE_VARARGS (func_type
))
1092 last_reg_arg
= TYPE_NFIELDS (func_type
) - 2;
1094 /* First force sp to a 4-byte alignment. */
1095 sp
= sh_frame_align (gdbarch
, sp
);
1097 /* Make room on stack for args. */
1098 sp
-= sh_stack_allocsize (nargs
, args
);
1100 /* Initialize float argument mechanism. */
1101 sh_init_flt_argreg ();
1103 /* Now load as many as possible of the first arguments into
1104 registers, and push the rest onto the stack. There are 16 bytes
1105 in four registers available. Loop thru args from first to last. */
1106 for (argnum
= 0; argnum
< nargs
; argnum
++)
1108 type
= value_type (args
[argnum
]);
1109 len
= TYPE_LENGTH (type
);
1110 val
= sh_justify_value_in_reg (gdbarch
, args
[argnum
], len
);
1112 /* Some decisions have to be made how various types are handled.
1113 This also differs in different ABIs. */
1116 /* Find out the next register to use for a floating point value. */
1117 treat_as_flt
= sh_treat_as_flt_p (type
);
1119 flt_argreg
= sh_next_flt_argreg (gdbarch
, len
, func_type
);
1120 /* In Renesas ABI, long longs and aggregate types are always passed
1122 else if (sh_is_renesas_calling_convention (func_type
)
1123 && ((TYPE_CODE (type
) == TYPE_CODE_INT
&& len
== 8)
1124 || TYPE_CODE (type
) == TYPE_CODE_STRUCT
1125 || TYPE_CODE (type
) == TYPE_CODE_UNION
))
1127 /* In contrast to non-FPU CPUs, arguments are never split between
1128 registers and stack. If an argument doesn't fit in the remaining
1129 registers it's always pushed entirely on the stack. */
1130 else if (len
> ((ARGLAST_REGNUM
- argreg
+ 1) * 4))
1135 if ((treat_as_flt
&& flt_argreg
> FLOAT_ARGLAST_REGNUM
)
1136 || (!treat_as_flt
&& (argreg
> ARGLAST_REGNUM
1138 || argnum
> last_reg_arg
)
1140 /* The data goes entirely on the stack, 4-byte aligned. */
1141 reg_size
= (len
+ 3) & ~3;
1142 write_memory (sp
+ stack_offset
, val
, reg_size
);
1143 stack_offset
+= reg_size
;
1145 else if (treat_as_flt
&& flt_argreg
<= FLOAT_ARGLAST_REGNUM
)
1147 /* Argument goes in a float argument register. */
1148 reg_size
= register_size (gdbarch
, flt_argreg
);
1149 regval
= extract_unsigned_integer (val
, reg_size
, byte_order
);
1150 /* In little endian mode, float types taking two registers
1151 (doubles on sh4, long doubles on sh2e, sh3e and sh4) must
1152 be stored swapped in the argument registers. The below
1153 code first writes the first 32 bits in the next but one
1154 register, increments the val and len values accordingly
1155 and then proceeds as normal by writing the second 32 bits
1156 into the next register. */
1157 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
1158 && TYPE_LENGTH (type
) == 2 * reg_size
)
1160 regcache_cooked_write_unsigned (regcache
, flt_argreg
+ 1,
1164 regval
= extract_unsigned_integer (val
, reg_size
,
1167 regcache_cooked_write_unsigned (regcache
, flt_argreg
++, regval
);
1169 else if (!treat_as_flt
&& argreg
<= ARGLAST_REGNUM
)
1171 /* there's room in a register */
1172 reg_size
= register_size (gdbarch
, argreg
);
1173 regval
= extract_unsigned_integer (val
, reg_size
, byte_order
);
1174 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
1176 /* Store the value one register at a time or in one step on
1185 if (sh_is_renesas_calling_convention (func_type
))
1186 /* If the function uses the Renesas ABI, subtract another 4 bytes from
1187 the stack and store the struct return address there. */
1188 write_memory_unsigned_integer (sp
-= 4, 4, byte_order
, struct_addr
);
1190 /* Using the gcc ABI, the "struct return pointer" pseudo-argument has
1191 its own dedicated register. */
1192 regcache_cooked_write_unsigned (regcache
,
1193 STRUCT_RETURN_REGNUM
, struct_addr
);
1196 /* Store return address. */
1197 regcache_cooked_write_unsigned (regcache
, PR_REGNUM
, bp_addr
);
1199 /* Update stack pointer. */
1200 regcache_cooked_write_unsigned (regcache
,
1201 gdbarch_sp_regnum (gdbarch
), sp
);
1207 sh_push_dummy_call_nofpu (struct gdbarch
*gdbarch
,
1208 struct value
*function
,
1209 struct regcache
*regcache
,
1211 int nargs
, struct value
**args
,
1212 CORE_ADDR sp
, int struct_return
,
1213 CORE_ADDR struct_addr
)
1215 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1216 int stack_offset
= 0;
1217 int argreg
= ARG0_REGNUM
;
1219 struct type
*func_type
= value_type (function
);
1223 int len
, reg_size
= 0;
1224 int pass_on_stack
= 0;
1225 int last_reg_arg
= INT_MAX
;
1227 /* The Renesas ABI expects all varargs arguments, plus the last
1228 non-vararg argument to be on the stack, no matter how many
1229 registers have been used so far. */
1230 if (sh_is_renesas_calling_convention (func_type
)
1231 && TYPE_VARARGS (func_type
))
1232 last_reg_arg
= TYPE_NFIELDS (func_type
) - 2;
1234 /* First force sp to a 4-byte alignment. */
1235 sp
= sh_frame_align (gdbarch
, sp
);
1237 /* Make room on stack for args. */
1238 sp
-= sh_stack_allocsize (nargs
, args
);
1240 /* Now load as many as possible of the first arguments into
1241 registers, and push the rest onto the stack. There are 16 bytes
1242 in four registers available. Loop thru args from first to last. */
1243 for (argnum
= 0; argnum
< nargs
; argnum
++)
1245 type
= value_type (args
[argnum
]);
1246 len
= TYPE_LENGTH (type
);
1247 val
= sh_justify_value_in_reg (gdbarch
, args
[argnum
], len
);
1249 /* Some decisions have to be made how various types are handled.
1250 This also differs in different ABIs. */
1252 /* Renesas ABI pushes doubles and long longs entirely on stack.
1253 Same goes for aggregate types. */
1254 if (sh_is_renesas_calling_convention (func_type
)
1255 && ((TYPE_CODE (type
) == TYPE_CODE_INT
&& len
>= 8)
1256 || (TYPE_CODE (type
) == TYPE_CODE_FLT
&& len
>= 8)
1257 || TYPE_CODE (type
) == TYPE_CODE_STRUCT
1258 || TYPE_CODE (type
) == TYPE_CODE_UNION
))
1262 if (argreg
> ARGLAST_REGNUM
|| pass_on_stack
1263 || argnum
> last_reg_arg
)
1265 /* The remainder of the data goes entirely on the stack,
1267 reg_size
= (len
+ 3) & ~3;
1268 write_memory (sp
+ stack_offset
, val
, reg_size
);
1269 stack_offset
+= reg_size
;
1271 else if (argreg
<= ARGLAST_REGNUM
)
1273 /* There's room in a register. */
1274 reg_size
= register_size (gdbarch
, argreg
);
1275 regval
= extract_unsigned_integer (val
, reg_size
, byte_order
);
1276 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
1278 /* Store the value reg_size bytes at a time. This means that things
1279 larger than reg_size bytes may go partly in registers and partly
1288 if (sh_is_renesas_calling_convention (func_type
))
1289 /* If the function uses the Renesas ABI, subtract another 4 bytes from
1290 the stack and store the struct return address there. */
1291 write_memory_unsigned_integer (sp
-= 4, 4, byte_order
, struct_addr
);
1293 /* Using the gcc ABI, the "struct return pointer" pseudo-argument has
1294 its own dedicated register. */
1295 regcache_cooked_write_unsigned (regcache
,
1296 STRUCT_RETURN_REGNUM
, struct_addr
);
1299 /* Store return address. */
1300 regcache_cooked_write_unsigned (regcache
, PR_REGNUM
, bp_addr
);
1302 /* Update stack pointer. */
1303 regcache_cooked_write_unsigned (regcache
,
1304 gdbarch_sp_regnum (gdbarch
), sp
);
1309 /* Find a function's return value in the appropriate registers (in
1310 regbuf), and copy it into valbuf. Extract from an array REGBUF
1311 containing the (raw) register state a function return value of type
1312 TYPE, and copy that, in virtual format, into VALBUF. */
1314 sh_extract_return_value_nofpu (struct type
*type
, struct regcache
*regcache
,
1317 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1318 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1319 int len
= TYPE_LENGTH (type
);
1320 int return_register
= R0_REGNUM
;
1327 regcache_cooked_read_unsigned (regcache
, R0_REGNUM
, &c
);
1328 store_unsigned_integer (valbuf
, len
, byte_order
, c
);
1332 int i
, regnum
= R0_REGNUM
;
1333 for (i
= 0; i
< len
; i
+= 4)
1334 regcache_raw_read (regcache
, regnum
++, (char *) valbuf
+ i
);
1337 error (_("bad size for return value"));
1341 sh_extract_return_value_fpu (struct type
*type
, struct regcache
*regcache
,
1344 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1345 if (sh_treat_as_flt_p (type
))
1347 int len
= TYPE_LENGTH (type
);
1348 int i
, regnum
= gdbarch_fp0_regnum (gdbarch
);
1349 for (i
= 0; i
< len
; i
+= 4)
1350 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
1351 regcache_raw_read (regcache
, regnum
++,
1352 (char *) valbuf
+ len
- 4 - i
);
1354 regcache_raw_read (regcache
, regnum
++, (char *) valbuf
+ i
);
1357 sh_extract_return_value_nofpu (type
, regcache
, valbuf
);
1360 /* Write into appropriate registers a function return value
1361 of type TYPE, given in virtual format.
1362 If the architecture is sh4 or sh3e, store a function's return value
1363 in the R0 general register or in the FP0 floating point register,
1364 depending on the type of the return value. In all the other cases
1365 the result is stored in r0, left-justified. */
1367 sh_store_return_value_nofpu (struct type
*type
, struct regcache
*regcache
,
1370 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1371 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1373 int len
= TYPE_LENGTH (type
);
1377 val
= extract_unsigned_integer (valbuf
, len
, byte_order
);
1378 regcache_cooked_write_unsigned (regcache
, R0_REGNUM
, val
);
1382 int i
, regnum
= R0_REGNUM
;
1383 for (i
= 0; i
< len
; i
+= 4)
1384 regcache_raw_write (regcache
, regnum
++, (char *) valbuf
+ i
);
1389 sh_store_return_value_fpu (struct type
*type
, struct regcache
*regcache
,
1392 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1393 if (sh_treat_as_flt_p (type
))
1395 int len
= TYPE_LENGTH (type
);
1396 int i
, regnum
= gdbarch_fp0_regnum (gdbarch
);
1397 for (i
= 0; i
< len
; i
+= 4)
1398 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
1399 regcache_raw_write (regcache
, regnum
++,
1400 (char *) valbuf
+ len
- 4 - i
);
1402 regcache_raw_write (regcache
, regnum
++, (char *) valbuf
+ i
);
1405 sh_store_return_value_nofpu (type
, regcache
, valbuf
);
1408 static enum return_value_convention
1409 sh_return_value_nofpu (struct gdbarch
*gdbarch
, struct type
*func_type
,
1410 struct type
*type
, struct regcache
*regcache
,
1411 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1413 if (sh_use_struct_convention_nofpu (
1414 sh_is_renesas_calling_convention (func_type
), type
))
1415 return RETURN_VALUE_STRUCT_CONVENTION
;
1417 sh_store_return_value_nofpu (type
, regcache
, writebuf
);
1419 sh_extract_return_value_nofpu (type
, regcache
, readbuf
);
1420 return RETURN_VALUE_REGISTER_CONVENTION
;
1423 static enum return_value_convention
1424 sh_return_value_fpu (struct gdbarch
*gdbarch
, struct type
*func_type
,
1425 struct type
*type
, struct regcache
*regcache
,
1426 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1428 if (sh_use_struct_convention (
1429 sh_is_renesas_calling_convention (func_type
), type
))
1430 return RETURN_VALUE_STRUCT_CONVENTION
;
1432 sh_store_return_value_fpu (type
, regcache
, writebuf
);
1434 sh_extract_return_value_fpu (type
, regcache
, readbuf
);
1435 return RETURN_VALUE_REGISTER_CONVENTION
;
1438 /* Print the registers in a form similar to the E7000. */
1441 sh_generic_show_regs (struct frame_info
*frame
)
1444 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1445 phex (get_frame_register_unsigned (frame
,
1447 (get_frame_arch (frame
))), 4),
1448 (long) get_frame_register_unsigned (frame
, SR_REGNUM
),
1449 (long) get_frame_register_unsigned (frame
, PR_REGNUM
),
1450 (long) get_frame_register_unsigned (frame
, MACH_REGNUM
));
1453 (" GBR %08lx VBR %08lx MACL %08lx\n",
1454 (long) get_frame_register_unsigned (frame
, GBR_REGNUM
),
1455 (long) get_frame_register_unsigned (frame
, VBR_REGNUM
),
1456 (long) get_frame_register_unsigned (frame
, MACL_REGNUM
));
1459 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1460 (long) get_frame_register_unsigned (frame
, 0),
1461 (long) get_frame_register_unsigned (frame
, 1),
1462 (long) get_frame_register_unsigned (frame
, 2),
1463 (long) get_frame_register_unsigned (frame
, 3),
1464 (long) get_frame_register_unsigned (frame
, 4),
1465 (long) get_frame_register_unsigned (frame
, 5),
1466 (long) get_frame_register_unsigned (frame
, 6),
1467 (long) get_frame_register_unsigned (frame
, 7));
1469 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1470 (long) get_frame_register_unsigned (frame
, 8),
1471 (long) get_frame_register_unsigned (frame
, 9),
1472 (long) get_frame_register_unsigned (frame
, 10),
1473 (long) get_frame_register_unsigned (frame
, 11),
1474 (long) get_frame_register_unsigned (frame
, 12),
1475 (long) get_frame_register_unsigned (frame
, 13),
1476 (long) get_frame_register_unsigned (frame
, 14),
1477 (long) get_frame_register_unsigned (frame
, 15));
1481 sh3_show_regs (struct frame_info
*frame
)
1484 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1485 phex (get_frame_register_unsigned (frame
,
1487 (get_frame_arch (frame
))), 4),
1488 (long) get_frame_register_unsigned (frame
, SR_REGNUM
),
1489 (long) get_frame_register_unsigned (frame
, PR_REGNUM
),
1490 (long) get_frame_register_unsigned (frame
, MACH_REGNUM
));
1493 (" GBR %08lx VBR %08lx MACL %08lx\n",
1494 (long) get_frame_register_unsigned (frame
, GBR_REGNUM
),
1495 (long) get_frame_register_unsigned (frame
, VBR_REGNUM
),
1496 (long) get_frame_register_unsigned (frame
, MACL_REGNUM
));
1498 (" SSR %08lx SPC %08lx\n",
1499 (long) get_frame_register_unsigned (frame
, SSR_REGNUM
),
1500 (long) get_frame_register_unsigned (frame
, SPC_REGNUM
));
1503 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1504 (long) get_frame_register_unsigned (frame
, 0),
1505 (long) get_frame_register_unsigned (frame
, 1),
1506 (long) get_frame_register_unsigned (frame
, 2),
1507 (long) get_frame_register_unsigned (frame
, 3),
1508 (long) get_frame_register_unsigned (frame
, 4),
1509 (long) get_frame_register_unsigned (frame
, 5),
1510 (long) get_frame_register_unsigned (frame
, 6),
1511 (long) get_frame_register_unsigned (frame
, 7));
1513 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1514 (long) get_frame_register_unsigned (frame
, 8),
1515 (long) get_frame_register_unsigned (frame
, 9),
1516 (long) get_frame_register_unsigned (frame
, 10),
1517 (long) get_frame_register_unsigned (frame
, 11),
1518 (long) get_frame_register_unsigned (frame
, 12),
1519 (long) get_frame_register_unsigned (frame
, 13),
1520 (long) get_frame_register_unsigned (frame
, 14),
1521 (long) get_frame_register_unsigned (frame
, 15));
1525 sh2e_show_regs (struct frame_info
*frame
)
1527 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1529 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1530 phex (get_frame_register_unsigned (frame
,
1531 gdbarch_pc_regnum (gdbarch
)), 4),
1532 (long) get_frame_register_unsigned (frame
, SR_REGNUM
),
1533 (long) get_frame_register_unsigned (frame
, PR_REGNUM
),
1534 (long) get_frame_register_unsigned (frame
, MACH_REGNUM
));
1537 (" GBR %08lx VBR %08lx MACL %08lx\n",
1538 (long) get_frame_register_unsigned (frame
, GBR_REGNUM
),
1539 (long) get_frame_register_unsigned (frame
, VBR_REGNUM
),
1540 (long) get_frame_register_unsigned (frame
, MACL_REGNUM
));
1542 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1543 (long) get_frame_register_unsigned (frame
, SSR_REGNUM
),
1544 (long) get_frame_register_unsigned (frame
, SPC_REGNUM
),
1545 (long) get_frame_register_unsigned (frame
, FPUL_REGNUM
),
1546 (long) get_frame_register_unsigned (frame
, FPSCR_REGNUM
));
1549 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1550 (long) get_frame_register_unsigned (frame
, 0),
1551 (long) get_frame_register_unsigned (frame
, 1),
1552 (long) get_frame_register_unsigned (frame
, 2),
1553 (long) get_frame_register_unsigned (frame
, 3),
1554 (long) get_frame_register_unsigned (frame
, 4),
1555 (long) get_frame_register_unsigned (frame
, 5),
1556 (long) get_frame_register_unsigned (frame
, 6),
1557 (long) get_frame_register_unsigned (frame
, 7));
1559 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1560 (long) get_frame_register_unsigned (frame
, 8),
1561 (long) get_frame_register_unsigned (frame
, 9),
1562 (long) get_frame_register_unsigned (frame
, 10),
1563 (long) get_frame_register_unsigned (frame
, 11),
1564 (long) get_frame_register_unsigned (frame
, 12),
1565 (long) get_frame_register_unsigned (frame
, 13),
1566 (long) get_frame_register_unsigned (frame
, 14),
1567 (long) get_frame_register_unsigned (frame
, 15));
1570 ("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1571 (long) get_frame_register_unsigned
1572 (frame
, gdbarch_fp0_regnum (gdbarch
) + 0),
1573 (long) get_frame_register_unsigned
1574 (frame
, gdbarch_fp0_regnum (gdbarch
) + 1),
1575 (long) get_frame_register_unsigned
1576 (frame
, gdbarch_fp0_regnum (gdbarch
) + 2),
1577 (long) get_frame_register_unsigned
1578 (frame
, gdbarch_fp0_regnum (gdbarch
) + 3),
1579 (long) get_frame_register_unsigned
1580 (frame
, gdbarch_fp0_regnum (gdbarch
) + 4),
1581 (long) get_frame_register_unsigned
1582 (frame
, gdbarch_fp0_regnum (gdbarch
) + 5),
1583 (long) get_frame_register_unsigned
1584 (frame
, gdbarch_fp0_regnum (gdbarch
) + 6),
1585 (long) get_frame_register_unsigned
1586 (frame
, gdbarch_fp0_regnum (gdbarch
) + 7));
1588 ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1589 (long) get_frame_register_unsigned
1590 (frame
, gdbarch_fp0_regnum (gdbarch
) + 8),
1591 (long) get_frame_register_unsigned
1592 (frame
, gdbarch_fp0_regnum (gdbarch
) + 9),
1593 (long) get_frame_register_unsigned
1594 (frame
, gdbarch_fp0_regnum (gdbarch
) + 10),
1595 (long) get_frame_register_unsigned
1596 (frame
, gdbarch_fp0_regnum (gdbarch
) + 11),
1597 (long) get_frame_register_unsigned
1598 (frame
, gdbarch_fp0_regnum (gdbarch
) + 12),
1599 (long) get_frame_register_unsigned
1600 (frame
, gdbarch_fp0_regnum (gdbarch
) + 13),
1601 (long) get_frame_register_unsigned
1602 (frame
, gdbarch_fp0_regnum (gdbarch
) + 14),
1603 (long) get_frame_register_unsigned
1604 (frame
, gdbarch_fp0_regnum (gdbarch
) + 15));
1608 sh2a_show_regs (struct frame_info
*frame
)
1610 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1611 int pr
= get_frame_register_unsigned (frame
, FPSCR_REGNUM
) & 0x80000;
1614 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1615 phex (get_frame_register_unsigned (frame
,
1616 gdbarch_pc_regnum (gdbarch
)), 4),
1617 (long) get_frame_register_unsigned (frame
, SR_REGNUM
),
1618 (long) get_frame_register_unsigned (frame
, PR_REGNUM
),
1619 (long) get_frame_register_unsigned (frame
, MACH_REGNUM
));
1622 (" GBR %08lx VBR %08lx TBR %08lx MACL %08lx\n",
1623 (long) get_frame_register_unsigned (frame
, GBR_REGNUM
),
1624 (long) get_frame_register_unsigned (frame
, VBR_REGNUM
),
1625 (long) get_frame_register_unsigned (frame
, TBR_REGNUM
),
1626 (long) get_frame_register_unsigned (frame
, MACL_REGNUM
));
1628 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1629 (long) get_frame_register_unsigned (frame
, SSR_REGNUM
),
1630 (long) get_frame_register_unsigned (frame
, SPC_REGNUM
),
1631 (long) get_frame_register_unsigned (frame
, FPUL_REGNUM
),
1632 (long) get_frame_register_unsigned (frame
, FPSCR_REGNUM
));
1635 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1636 (long) get_frame_register_unsigned (frame
, 0),
1637 (long) get_frame_register_unsigned (frame
, 1),
1638 (long) get_frame_register_unsigned (frame
, 2),
1639 (long) get_frame_register_unsigned (frame
, 3),
1640 (long) get_frame_register_unsigned (frame
, 4),
1641 (long) get_frame_register_unsigned (frame
, 5),
1642 (long) get_frame_register_unsigned (frame
, 6),
1643 (long) get_frame_register_unsigned (frame
, 7));
1645 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1646 (long) get_frame_register_unsigned (frame
, 8),
1647 (long) get_frame_register_unsigned (frame
, 9),
1648 (long) get_frame_register_unsigned (frame
, 10),
1649 (long) get_frame_register_unsigned (frame
, 11),
1650 (long) get_frame_register_unsigned (frame
, 12),
1651 (long) get_frame_register_unsigned (frame
, 13),
1652 (long) get_frame_register_unsigned (frame
, 14),
1653 (long) get_frame_register_unsigned (frame
, 15));
1656 (pr
? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1657 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1658 (long) get_frame_register_unsigned
1659 (frame
, gdbarch_fp0_regnum (gdbarch
) + 0),
1660 (long) get_frame_register_unsigned
1661 (frame
, gdbarch_fp0_regnum (gdbarch
) + 1),
1662 (long) get_frame_register_unsigned
1663 (frame
, gdbarch_fp0_regnum (gdbarch
) + 2),
1664 (long) get_frame_register_unsigned
1665 (frame
, gdbarch_fp0_regnum (gdbarch
) + 3),
1666 (long) get_frame_register_unsigned
1667 (frame
, gdbarch_fp0_regnum (gdbarch
) + 4),
1668 (long) get_frame_register_unsigned
1669 (frame
, gdbarch_fp0_regnum (gdbarch
) + 5),
1670 (long) get_frame_register_unsigned
1671 (frame
, gdbarch_fp0_regnum (gdbarch
) + 6),
1672 (long) get_frame_register_unsigned
1673 (frame
, gdbarch_fp0_regnum (gdbarch
) + 7));
1675 (pr
? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1676 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1677 (long) get_frame_register_unsigned
1678 (frame
, gdbarch_fp0_regnum (gdbarch
) + 8),
1679 (long) get_frame_register_unsigned
1680 (frame
, gdbarch_fp0_regnum (gdbarch
) + 9),
1681 (long) get_frame_register_unsigned
1682 (frame
, gdbarch_fp0_regnum (gdbarch
) + 10),
1683 (long) get_frame_register_unsigned
1684 (frame
, gdbarch_fp0_regnum (gdbarch
) + 11),
1685 (long) get_frame_register_unsigned
1686 (frame
, gdbarch_fp0_regnum (gdbarch
) + 12),
1687 (long) get_frame_register_unsigned
1688 (frame
, gdbarch_fp0_regnum (gdbarch
) + 13),
1689 (long) get_frame_register_unsigned
1690 (frame
, gdbarch_fp0_regnum (gdbarch
) + 14),
1691 (long) get_frame_register_unsigned
1692 (frame
, gdbarch_fp0_regnum (gdbarch
) + 15));
1694 ("BANK=%-3d\n", (int) get_frame_register_unsigned (frame
, BANK_REGNUM
));
1696 ("R0b-R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1697 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 0),
1698 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 1),
1699 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 2),
1700 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 3),
1701 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 4),
1702 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 5),
1703 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 6),
1704 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 7));
1706 ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1707 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 8),
1708 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 9),
1709 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 10),
1710 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 11),
1711 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 12),
1712 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 13),
1713 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 14));
1715 ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n",
1716 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 15),
1717 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 16),
1718 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 17),
1719 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 18),
1720 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 19));
1724 sh2a_nofpu_show_regs (struct frame_info
*frame
)
1726 int pr
= get_frame_register_unsigned (frame
, FPSCR_REGNUM
) & 0x80000;
1729 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1730 phex (get_frame_register_unsigned (frame
,
1732 (get_frame_arch (frame
))), 4),
1733 (long) get_frame_register_unsigned (frame
, SR_REGNUM
),
1734 (long) get_frame_register_unsigned (frame
, PR_REGNUM
),
1735 (long) get_frame_register_unsigned (frame
, MACH_REGNUM
));
1738 (" GBR %08lx VBR %08lx TBR %08lx MACL %08lx\n",
1739 (long) get_frame_register_unsigned (frame
, GBR_REGNUM
),
1740 (long) get_frame_register_unsigned (frame
, VBR_REGNUM
),
1741 (long) get_frame_register_unsigned (frame
, TBR_REGNUM
),
1742 (long) get_frame_register_unsigned (frame
, MACL_REGNUM
));
1744 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1745 (long) get_frame_register_unsigned (frame
, SSR_REGNUM
),
1746 (long) get_frame_register_unsigned (frame
, SPC_REGNUM
),
1747 (long) get_frame_register_unsigned (frame
, FPUL_REGNUM
),
1748 (long) get_frame_register_unsigned (frame
, FPSCR_REGNUM
));
1751 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1752 (long) get_frame_register_unsigned (frame
, 0),
1753 (long) get_frame_register_unsigned (frame
, 1),
1754 (long) get_frame_register_unsigned (frame
, 2),
1755 (long) get_frame_register_unsigned (frame
, 3),
1756 (long) get_frame_register_unsigned (frame
, 4),
1757 (long) get_frame_register_unsigned (frame
, 5),
1758 (long) get_frame_register_unsigned (frame
, 6),
1759 (long) get_frame_register_unsigned (frame
, 7));
1761 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1762 (long) get_frame_register_unsigned (frame
, 8),
1763 (long) get_frame_register_unsigned (frame
, 9),
1764 (long) get_frame_register_unsigned (frame
, 10),
1765 (long) get_frame_register_unsigned (frame
, 11),
1766 (long) get_frame_register_unsigned (frame
, 12),
1767 (long) get_frame_register_unsigned (frame
, 13),
1768 (long) get_frame_register_unsigned (frame
, 14),
1769 (long) get_frame_register_unsigned (frame
, 15));
1772 ("BANK=%-3d\n", (int) get_frame_register_unsigned (frame
, BANK_REGNUM
));
1774 ("R0b-R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1775 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 0),
1776 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 1),
1777 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 2),
1778 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 3),
1779 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 4),
1780 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 5),
1781 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 6),
1782 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 7));
1784 ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1785 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 8),
1786 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 9),
1787 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 10),
1788 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 11),
1789 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 12),
1790 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 13),
1791 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 14));
1793 ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n",
1794 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 15),
1795 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 16),
1796 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 17),
1797 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 18),
1798 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 19));
1802 sh3e_show_regs (struct frame_info
*frame
)
1804 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1806 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1807 phex (get_frame_register_unsigned (frame
,
1808 gdbarch_pc_regnum (gdbarch
)), 4),
1809 (long) get_frame_register_unsigned (frame
, SR_REGNUM
),
1810 (long) get_frame_register_unsigned (frame
, PR_REGNUM
),
1811 (long) get_frame_register_unsigned (frame
, MACH_REGNUM
));
1814 (" GBR %08lx VBR %08lx MACL %08lx\n",
1815 (long) get_frame_register_unsigned (frame
, GBR_REGNUM
),
1816 (long) get_frame_register_unsigned (frame
, VBR_REGNUM
),
1817 (long) get_frame_register_unsigned (frame
, MACL_REGNUM
));
1819 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1820 (long) get_frame_register_unsigned (frame
, SSR_REGNUM
),
1821 (long) get_frame_register_unsigned (frame
, SPC_REGNUM
),
1822 (long) get_frame_register_unsigned (frame
, FPUL_REGNUM
),
1823 (long) get_frame_register_unsigned (frame
, FPSCR_REGNUM
));
1826 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1827 (long) get_frame_register_unsigned (frame
, 0),
1828 (long) get_frame_register_unsigned (frame
, 1),
1829 (long) get_frame_register_unsigned (frame
, 2),
1830 (long) get_frame_register_unsigned (frame
, 3),
1831 (long) get_frame_register_unsigned (frame
, 4),
1832 (long) get_frame_register_unsigned (frame
, 5),
1833 (long) get_frame_register_unsigned (frame
, 6),
1834 (long) get_frame_register_unsigned (frame
, 7));
1836 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1837 (long) get_frame_register_unsigned (frame
, 8),
1838 (long) get_frame_register_unsigned (frame
, 9),
1839 (long) get_frame_register_unsigned (frame
, 10),
1840 (long) get_frame_register_unsigned (frame
, 11),
1841 (long) get_frame_register_unsigned (frame
, 12),
1842 (long) get_frame_register_unsigned (frame
, 13),
1843 (long) get_frame_register_unsigned (frame
, 14),
1844 (long) get_frame_register_unsigned (frame
, 15));
1847 ("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1848 (long) get_frame_register_unsigned
1849 (frame
, gdbarch_fp0_regnum (gdbarch
) + 0),
1850 (long) get_frame_register_unsigned
1851 (frame
, gdbarch_fp0_regnum (gdbarch
) + 1),
1852 (long) get_frame_register_unsigned
1853 (frame
, gdbarch_fp0_regnum (gdbarch
) + 2),
1854 (long) get_frame_register_unsigned
1855 (frame
, gdbarch_fp0_regnum (gdbarch
) + 3),
1856 (long) get_frame_register_unsigned
1857 (frame
, gdbarch_fp0_regnum (gdbarch
) + 4),
1858 (long) get_frame_register_unsigned
1859 (frame
, gdbarch_fp0_regnum (gdbarch
) + 5),
1860 (long) get_frame_register_unsigned
1861 (frame
, gdbarch_fp0_regnum (gdbarch
) + 6),
1862 (long) get_frame_register_unsigned
1863 (frame
, gdbarch_fp0_regnum (gdbarch
) + 7));
1865 ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1866 (long) get_frame_register_unsigned
1867 (frame
, gdbarch_fp0_regnum (gdbarch
) + 8),
1868 (long) get_frame_register_unsigned
1869 (frame
, gdbarch_fp0_regnum (gdbarch
) + 9),
1870 (long) get_frame_register_unsigned
1871 (frame
, gdbarch_fp0_regnum (gdbarch
) + 10),
1872 (long) get_frame_register_unsigned
1873 (frame
, gdbarch_fp0_regnum (gdbarch
) + 11),
1874 (long) get_frame_register_unsigned
1875 (frame
, gdbarch_fp0_regnum (gdbarch
) + 12),
1876 (long) get_frame_register_unsigned
1877 (frame
, gdbarch_fp0_regnum (gdbarch
) + 13),
1878 (long) get_frame_register_unsigned
1879 (frame
, gdbarch_fp0_regnum (gdbarch
) + 14),
1880 (long) get_frame_register_unsigned
1881 (frame
, gdbarch_fp0_regnum (gdbarch
) + 15));
1885 sh3_dsp_show_regs (struct frame_info
*frame
)
1888 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1889 phex (get_frame_register_unsigned (frame
,
1891 (get_frame_arch (frame
))), 4),
1892 (long) get_frame_register_unsigned (frame
, SR_REGNUM
),
1893 (long) get_frame_register_unsigned (frame
, PR_REGNUM
),
1894 (long) get_frame_register_unsigned (frame
, MACH_REGNUM
));
1897 (" GBR %08lx VBR %08lx MACL %08lx\n",
1898 (long) get_frame_register_unsigned (frame
, GBR_REGNUM
),
1899 (long) get_frame_register_unsigned (frame
, VBR_REGNUM
),
1900 (long) get_frame_register_unsigned (frame
, MACL_REGNUM
));
1903 (" SSR %08lx SPC %08lx DSR %08lx\n",
1904 (long) get_frame_register_unsigned (frame
, SSR_REGNUM
),
1905 (long) get_frame_register_unsigned (frame
, SPC_REGNUM
),
1906 (long) get_frame_register_unsigned (frame
, DSR_REGNUM
));
1909 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1910 (long) get_frame_register_unsigned (frame
, 0),
1911 (long) get_frame_register_unsigned (frame
, 1),
1912 (long) get_frame_register_unsigned (frame
, 2),
1913 (long) get_frame_register_unsigned (frame
, 3),
1914 (long) get_frame_register_unsigned (frame
, 4),
1915 (long) get_frame_register_unsigned (frame
, 5),
1916 (long) get_frame_register_unsigned (frame
, 6),
1917 (long) get_frame_register_unsigned (frame
, 7));
1919 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1920 (long) get_frame_register_unsigned (frame
, 8),
1921 (long) get_frame_register_unsigned (frame
, 9),
1922 (long) get_frame_register_unsigned (frame
, 10),
1923 (long) get_frame_register_unsigned (frame
, 11),
1924 (long) get_frame_register_unsigned (frame
, 12),
1925 (long) get_frame_register_unsigned (frame
, 13),
1926 (long) get_frame_register_unsigned (frame
, 14),
1927 (long) get_frame_register_unsigned (frame
, 15));
1930 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1931 (long) get_frame_register_unsigned (frame
, A0G_REGNUM
) & 0xff,
1932 (long) get_frame_register_unsigned (frame
, A0_REGNUM
),
1933 (long) get_frame_register_unsigned (frame
, M0_REGNUM
),
1934 (long) get_frame_register_unsigned (frame
, X0_REGNUM
),
1935 (long) get_frame_register_unsigned (frame
, Y0_REGNUM
),
1936 (long) get_frame_register_unsigned (frame
, RS_REGNUM
),
1937 (long) get_frame_register_unsigned (frame
, MOD_REGNUM
));
1939 ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1940 (long) get_frame_register_unsigned (frame
, A1G_REGNUM
) & 0xff,
1941 (long) get_frame_register_unsigned (frame
, A1_REGNUM
),
1942 (long) get_frame_register_unsigned (frame
, M1_REGNUM
),
1943 (long) get_frame_register_unsigned (frame
, X1_REGNUM
),
1944 (long) get_frame_register_unsigned (frame
, Y1_REGNUM
),
1945 (long) get_frame_register_unsigned (frame
, RE_REGNUM
));
1949 sh4_show_regs (struct frame_info
*frame
)
1951 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1952 int pr
= get_frame_register_unsigned (frame
, FPSCR_REGNUM
) & 0x80000;
1955 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1956 phex (get_frame_register_unsigned (frame
,
1957 gdbarch_pc_regnum (gdbarch
)), 4),
1958 (long) get_frame_register_unsigned (frame
, SR_REGNUM
),
1959 (long) get_frame_register_unsigned (frame
, PR_REGNUM
),
1960 (long) get_frame_register_unsigned (frame
, MACH_REGNUM
));
1963 (" GBR %08lx VBR %08lx MACL %08lx\n",
1964 (long) get_frame_register_unsigned (frame
, GBR_REGNUM
),
1965 (long) get_frame_register_unsigned (frame
, VBR_REGNUM
),
1966 (long) get_frame_register_unsigned (frame
, MACL_REGNUM
));
1968 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1969 (long) get_frame_register_unsigned (frame
, SSR_REGNUM
),
1970 (long) get_frame_register_unsigned (frame
, SPC_REGNUM
),
1971 (long) get_frame_register_unsigned (frame
, FPUL_REGNUM
),
1972 (long) get_frame_register_unsigned (frame
, FPSCR_REGNUM
));
1975 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1976 (long) get_frame_register_unsigned (frame
, 0),
1977 (long) get_frame_register_unsigned (frame
, 1),
1978 (long) get_frame_register_unsigned (frame
, 2),
1979 (long) get_frame_register_unsigned (frame
, 3),
1980 (long) get_frame_register_unsigned (frame
, 4),
1981 (long) get_frame_register_unsigned (frame
, 5),
1982 (long) get_frame_register_unsigned (frame
, 6),
1983 (long) get_frame_register_unsigned (frame
, 7));
1985 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1986 (long) get_frame_register_unsigned (frame
, 8),
1987 (long) get_frame_register_unsigned (frame
, 9),
1988 (long) get_frame_register_unsigned (frame
, 10),
1989 (long) get_frame_register_unsigned (frame
, 11),
1990 (long) get_frame_register_unsigned (frame
, 12),
1991 (long) get_frame_register_unsigned (frame
, 13),
1992 (long) get_frame_register_unsigned (frame
, 14),
1993 (long) get_frame_register_unsigned (frame
, 15));
1996 (pr
? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1997 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1998 (long) get_frame_register_unsigned
1999 (frame
, gdbarch_fp0_regnum (gdbarch
) + 0),
2000 (long) get_frame_register_unsigned
2001 (frame
, gdbarch_fp0_regnum (gdbarch
) + 1),
2002 (long) get_frame_register_unsigned
2003 (frame
, gdbarch_fp0_regnum (gdbarch
) + 2),
2004 (long) get_frame_register_unsigned
2005 (frame
, gdbarch_fp0_regnum (gdbarch
) + 3),
2006 (long) get_frame_register_unsigned
2007 (frame
, gdbarch_fp0_regnum (gdbarch
) + 4),
2008 (long) get_frame_register_unsigned
2009 (frame
, gdbarch_fp0_regnum (gdbarch
) + 5),
2010 (long) get_frame_register_unsigned
2011 (frame
, gdbarch_fp0_regnum (gdbarch
) + 6),
2012 (long) get_frame_register_unsigned
2013 (frame
, gdbarch_fp0_regnum (gdbarch
) + 7));
2015 (pr
? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
2016 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2017 (long) get_frame_register_unsigned
2018 (frame
, gdbarch_fp0_regnum (gdbarch
) + 8),
2019 (long) get_frame_register_unsigned
2020 (frame
, gdbarch_fp0_regnum (gdbarch
) + 9),
2021 (long) get_frame_register_unsigned
2022 (frame
, gdbarch_fp0_regnum (gdbarch
) + 10),
2023 (long) get_frame_register_unsigned
2024 (frame
, gdbarch_fp0_regnum (gdbarch
) + 11),
2025 (long) get_frame_register_unsigned
2026 (frame
, gdbarch_fp0_regnum (gdbarch
) + 12),
2027 (long) get_frame_register_unsigned
2028 (frame
, gdbarch_fp0_regnum (gdbarch
) + 13),
2029 (long) get_frame_register_unsigned
2030 (frame
, gdbarch_fp0_regnum (gdbarch
) + 14),
2031 (long) get_frame_register_unsigned
2032 (frame
, gdbarch_fp0_regnum (gdbarch
) + 15));
2036 sh4_nofpu_show_regs (struct frame_info
*frame
)
2039 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
2040 phex (get_frame_register_unsigned (frame
,
2042 (get_frame_arch (frame
))), 4),
2043 (long) get_frame_register_unsigned (frame
, SR_REGNUM
),
2044 (long) get_frame_register_unsigned (frame
, PR_REGNUM
),
2045 (long) get_frame_register_unsigned (frame
, MACH_REGNUM
));
2048 (" GBR %08lx VBR %08lx MACL %08lx\n",
2049 (long) get_frame_register_unsigned (frame
, GBR_REGNUM
),
2050 (long) get_frame_register_unsigned (frame
, VBR_REGNUM
),
2051 (long) get_frame_register_unsigned (frame
, MACL_REGNUM
));
2053 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
2054 (long) get_frame_register_unsigned (frame
, SSR_REGNUM
),
2055 (long) get_frame_register_unsigned (frame
, SPC_REGNUM
),
2056 (long) get_frame_register_unsigned (frame
, FPUL_REGNUM
),
2057 (long) get_frame_register_unsigned (frame
, FPSCR_REGNUM
));
2060 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2061 (long) get_frame_register_unsigned (frame
, 0),
2062 (long) get_frame_register_unsigned (frame
, 1),
2063 (long) get_frame_register_unsigned (frame
, 2),
2064 (long) get_frame_register_unsigned (frame
, 3),
2065 (long) get_frame_register_unsigned (frame
, 4),
2066 (long) get_frame_register_unsigned (frame
, 5),
2067 (long) get_frame_register_unsigned (frame
, 6),
2068 (long) get_frame_register_unsigned (frame
, 7));
2070 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2071 (long) get_frame_register_unsigned (frame
, 8),
2072 (long) get_frame_register_unsigned (frame
, 9),
2073 (long) get_frame_register_unsigned (frame
, 10),
2074 (long) get_frame_register_unsigned (frame
, 11),
2075 (long) get_frame_register_unsigned (frame
, 12),
2076 (long) get_frame_register_unsigned (frame
, 13),
2077 (long) get_frame_register_unsigned (frame
, 14),
2078 (long) get_frame_register_unsigned (frame
, 15));
2082 sh_dsp_show_regs (struct frame_info
*frame
)
2085 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
2086 phex (get_frame_register_unsigned (frame
,
2088 (get_frame_arch (frame
))), 4),
2089 (long) get_frame_register_unsigned (frame
, SR_REGNUM
),
2090 (long) get_frame_register_unsigned (frame
, PR_REGNUM
),
2091 (long) get_frame_register_unsigned (frame
, MACH_REGNUM
));
2094 (" GBR %08lx VBR %08lx DSR %08lx MACL %08lx\n",
2095 (long) get_frame_register_unsigned (frame
, GBR_REGNUM
),
2096 (long) get_frame_register_unsigned (frame
, VBR_REGNUM
),
2097 (long) get_frame_register_unsigned (frame
, DSR_REGNUM
),
2098 (long) get_frame_register_unsigned (frame
, MACL_REGNUM
));
2101 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2102 (long) get_frame_register_unsigned (frame
, 0),
2103 (long) get_frame_register_unsigned (frame
, 1),
2104 (long) get_frame_register_unsigned (frame
, 2),
2105 (long) get_frame_register_unsigned (frame
, 3),
2106 (long) get_frame_register_unsigned (frame
, 4),
2107 (long) get_frame_register_unsigned (frame
, 5),
2108 (long) get_frame_register_unsigned (frame
, 6),
2109 (long) get_frame_register_unsigned (frame
, 7));
2111 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2112 (long) get_frame_register_unsigned (frame
, 8),
2113 (long) get_frame_register_unsigned (frame
, 9),
2114 (long) get_frame_register_unsigned (frame
, 10),
2115 (long) get_frame_register_unsigned (frame
, 11),
2116 (long) get_frame_register_unsigned (frame
, 12),
2117 (long) get_frame_register_unsigned (frame
, 13),
2118 (long) get_frame_register_unsigned (frame
, 14),
2119 (long) get_frame_register_unsigned (frame
, 15));
2122 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
2123 (long) get_frame_register_unsigned (frame
, A0G_REGNUM
) & 0xff,
2124 (long) get_frame_register_unsigned (frame
, A0_REGNUM
),
2125 (long) get_frame_register_unsigned (frame
, M0_REGNUM
),
2126 (long) get_frame_register_unsigned (frame
, X0_REGNUM
),
2127 (long) get_frame_register_unsigned (frame
, Y0_REGNUM
),
2128 (long) get_frame_register_unsigned (frame
, RS_REGNUM
),
2129 (long) get_frame_register_unsigned (frame
, MOD_REGNUM
));
2130 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
2131 (long) get_frame_register_unsigned (frame
, A1G_REGNUM
) & 0xff,
2132 (long) get_frame_register_unsigned (frame
, A1_REGNUM
),
2133 (long) get_frame_register_unsigned (frame
, M1_REGNUM
),
2134 (long) get_frame_register_unsigned (frame
, X1_REGNUM
),
2135 (long) get_frame_register_unsigned (frame
, Y1_REGNUM
),
2136 (long) get_frame_register_unsigned (frame
, RE_REGNUM
));
2140 sh_show_regs_command (char *args
, int from_tty
)
2143 (*sh_show_regs
) (get_current_frame ());
2146 static struct type
*
2147 sh_sh2a_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
2149 if ((reg_nr
>= gdbarch_fp0_regnum (gdbarch
)
2150 && (reg_nr
<= FP_LAST_REGNUM
)) || (reg_nr
== FPUL_REGNUM
))
2151 return builtin_type (gdbarch
)->builtin_float
;
2152 else if (reg_nr
>= DR0_REGNUM
&& reg_nr
<= DR_LAST_REGNUM
)
2153 return builtin_type (gdbarch
)->builtin_double
;
2155 return builtin_type (gdbarch
)->builtin_int
;
2158 /* Return the GDB type object for the "standard" data type
2159 of data in register N. */
2160 static struct type
*
2161 sh_sh3e_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
2163 if ((reg_nr
>= gdbarch_fp0_regnum (gdbarch
)
2164 && (reg_nr
<= FP_LAST_REGNUM
)) || (reg_nr
== FPUL_REGNUM
))
2165 return builtin_type (gdbarch
)->builtin_float
;
2167 return builtin_type (gdbarch
)->builtin_int
;
2170 static struct type
*
2171 sh_sh4_build_float_register_type (struct gdbarch
*gdbarch
, int high
)
2173 return lookup_array_range_type (builtin_type (gdbarch
)->builtin_float
,
2177 static struct type
*
2178 sh_sh4_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
2180 if ((reg_nr
>= gdbarch_fp0_regnum (gdbarch
)
2181 && (reg_nr
<= FP_LAST_REGNUM
)) || (reg_nr
== FPUL_REGNUM
))
2182 return builtin_type (gdbarch
)->builtin_float
;
2183 else if (reg_nr
>= DR0_REGNUM
&& reg_nr
<= DR_LAST_REGNUM
)
2184 return builtin_type (gdbarch
)->builtin_double
;
2185 else if (reg_nr
>= FV0_REGNUM
&& reg_nr
<= FV_LAST_REGNUM
)
2186 return sh_sh4_build_float_register_type (gdbarch
, 3);
2188 return builtin_type (gdbarch
)->builtin_int
;
2191 static struct type
*
2192 sh_default_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
2194 return builtin_type (gdbarch
)->builtin_int
;
2197 /* Is a register in a reggroup?
2198 The default code in reggroup.c doesn't identify system registers, some
2199 float registers or any of the vector registers.
2200 TODO: sh2a and dsp registers. */
2202 sh_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2203 struct reggroup
*reggroup
)
2205 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
2206 || *gdbarch_register_name (gdbarch
, regnum
) == '\0')
2209 if (reggroup
== float_reggroup
2210 && (regnum
== FPUL_REGNUM
2211 || regnum
== FPSCR_REGNUM
))
2214 if (regnum
>= FV0_REGNUM
&& regnum
<= FV_LAST_REGNUM
)
2216 if (reggroup
== vector_reggroup
|| reggroup
== float_reggroup
)
2218 if (reggroup
== general_reggroup
)
2222 if (regnum
== VBR_REGNUM
2223 || regnum
== SR_REGNUM
2224 || regnum
== FPSCR_REGNUM
2225 || regnum
== SSR_REGNUM
2226 || regnum
== SPC_REGNUM
)
2228 if (reggroup
== system_reggroup
)
2230 if (reggroup
== general_reggroup
)
2234 /* The default code can cope with any other registers. */
2235 return default_register_reggroup_p (gdbarch
, regnum
, reggroup
);
2238 /* On the sh4, the DRi pseudo registers are problematic if the target
2239 is little endian. When the user writes one of those registers, for
2240 instance with 'ser var $dr0=1', we want the double to be stored
2242 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
2243 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2245 This corresponds to little endian byte order & big endian word
2246 order. However if we let gdb write the register w/o conversion, it
2247 will write fr0 and fr1 this way:
2248 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2249 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
2250 because it will consider fr0 and fr1 as a single LE stretch of memory.
2252 To achieve what we want we must force gdb to store things in
2253 floatformat_ieee_double_littlebyte_bigword (which is defined in
2254 include/floatformat.h and libiberty/floatformat.c.
2256 In case the target is big endian, there is no problem, the
2257 raw bytes will look like:
2258 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
2259 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2261 The other pseudo registers (the FVs) also don't pose a problem
2262 because they are stored as 4 individual FP elements. */
2265 sh_register_convert_to_virtual (int regnum
, struct type
*type
,
2266 char *from
, char *to
)
2268 if (regnum
>= DR0_REGNUM
&& regnum
<= DR_LAST_REGNUM
)
2271 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword
,
2273 store_typed_floating (to
, type
, val
);
2277 ("sh_register_convert_to_virtual called with non DR register number");
2281 sh_register_convert_to_raw (struct type
*type
, int regnum
,
2282 const void *from
, void *to
)
2284 if (regnum
>= DR0_REGNUM
&& regnum
<= DR_LAST_REGNUM
)
2286 DOUBLEST val
= extract_typed_floating (from
, type
);
2287 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword
,
2291 error (_("sh_register_convert_to_raw called with non DR register number"));
2294 /* For vectors of 4 floating point registers. */
2296 fv_reg_base_num (struct gdbarch
*gdbarch
, int fv_regnum
)
2300 fp_regnum
= gdbarch_fp0_regnum (gdbarch
)
2301 + (fv_regnum
- FV0_REGNUM
) * 4;
2305 /* For double precision floating point registers, i.e 2 fp regs. */
2307 dr_reg_base_num (struct gdbarch
*gdbarch
, int dr_regnum
)
2311 fp_regnum
= gdbarch_fp0_regnum (gdbarch
)
2312 + (dr_regnum
- DR0_REGNUM
) * 2;
2316 /* Concatenate PORTIONS contiguous raw registers starting at
2317 BASE_REGNUM into BUFFER. */
2319 static enum register_status
2320 pseudo_register_read_portions (struct gdbarch
*gdbarch
,
2321 struct regcache
*regcache
,
2323 int base_regnum
, gdb_byte
*buffer
)
2327 for (portion
= 0; portion
< portions
; portion
++)
2329 enum register_status status
;
2332 b
= buffer
+ register_size (gdbarch
, base_regnum
) * portion
;
2333 status
= regcache_raw_read (regcache
, base_regnum
+ portion
, b
);
2334 if (status
!= REG_VALID
)
2341 static enum register_status
2342 sh_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2343 int reg_nr
, gdb_byte
*buffer
)
2346 char temp_buffer
[MAX_REGISTER_SIZE
];
2347 enum register_status status
;
2349 if (reg_nr
== PSEUDO_BANK_REGNUM
)
2350 return regcache_raw_read (regcache
, BANK_REGNUM
, buffer
);
2351 else if (reg_nr
>= DR0_REGNUM
&& reg_nr
<= DR_LAST_REGNUM
)
2353 base_regnum
= dr_reg_base_num (gdbarch
, reg_nr
);
2355 /* Build the value in the provided buffer. */
2356 /* Read the real regs for which this one is an alias. */
2357 status
= pseudo_register_read_portions (gdbarch
, regcache
,
2358 2, base_regnum
, temp_buffer
);
2359 if (status
== REG_VALID
)
2361 /* We must pay attention to the endiannes. */
2362 sh_register_convert_to_virtual (reg_nr
,
2363 register_type (gdbarch
, reg_nr
),
2364 temp_buffer
, buffer
);
2368 else if (reg_nr
>= FV0_REGNUM
&& reg_nr
<= FV_LAST_REGNUM
)
2370 base_regnum
= fv_reg_base_num (gdbarch
, reg_nr
);
2372 /* Read the real regs for which this one is an alias. */
2373 return pseudo_register_read_portions (gdbarch
, regcache
,
2374 4, base_regnum
, buffer
);
2377 gdb_assert_not_reached ("invalid pseudo register number");
2381 sh_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2382 int reg_nr
, const gdb_byte
*buffer
)
2384 int base_regnum
, portion
;
2385 char temp_buffer
[MAX_REGISTER_SIZE
];
2387 if (reg_nr
== PSEUDO_BANK_REGNUM
)
2389 /* When the bank register is written to, the whole register bank
2390 is switched and all values in the bank registers must be read
2391 from the target/sim again. We're just invalidating the regcache
2392 so that a re-read happens next time it's necessary. */
2395 regcache_raw_write (regcache
, BANK_REGNUM
, buffer
);
2396 for (bregnum
= R0_BANK0_REGNUM
; bregnum
< MACLB_REGNUM
; ++bregnum
)
2397 regcache_invalidate (regcache
, bregnum
);
2399 else if (reg_nr
>= DR0_REGNUM
&& reg_nr
<= DR_LAST_REGNUM
)
2401 base_regnum
= dr_reg_base_num (gdbarch
, reg_nr
);
2403 /* We must pay attention to the endiannes. */
2404 sh_register_convert_to_raw (register_type (gdbarch
, reg_nr
),
2405 reg_nr
, buffer
, temp_buffer
);
2407 /* Write the real regs for which this one is an alias. */
2408 for (portion
= 0; portion
< 2; portion
++)
2409 regcache_raw_write (regcache
, base_regnum
+ portion
,
2411 + register_size (gdbarch
,
2412 base_regnum
) * portion
));
2414 else if (reg_nr
>= FV0_REGNUM
&& reg_nr
<= FV_LAST_REGNUM
)
2416 base_regnum
= fv_reg_base_num (gdbarch
, reg_nr
);
2418 /* Write the real regs for which this one is an alias. */
2419 for (portion
= 0; portion
< 4; portion
++)
2420 regcache_raw_write (regcache
, base_regnum
+ portion
,
2422 + register_size (gdbarch
,
2423 base_regnum
) * portion
));
2428 sh_dsp_register_sim_regno (struct gdbarch
*gdbarch
, int nr
)
2430 if (legacy_register_sim_regno (gdbarch
, nr
) < 0)
2431 return legacy_register_sim_regno (gdbarch
, nr
);
2432 if (nr
>= DSR_REGNUM
&& nr
<= Y1_REGNUM
)
2433 return nr
- DSR_REGNUM
+ SIM_SH_DSR_REGNUM
;
2434 if (nr
== MOD_REGNUM
)
2435 return SIM_SH_MOD_REGNUM
;
2436 if (nr
== RS_REGNUM
)
2437 return SIM_SH_RS_REGNUM
;
2438 if (nr
== RE_REGNUM
)
2439 return SIM_SH_RE_REGNUM
;
2440 if (nr
>= DSP_R0_BANK_REGNUM
&& nr
<= DSP_R7_BANK_REGNUM
)
2441 return nr
- DSP_R0_BANK_REGNUM
+ SIM_SH_R0_BANK_REGNUM
;
2446 sh_sh2a_register_sim_regno (struct gdbarch
*gdbarch
, int nr
)
2451 return SIM_SH_TBR_REGNUM
;
2453 return SIM_SH_IBNR_REGNUM
;
2455 return SIM_SH_IBCR_REGNUM
;
2457 return SIM_SH_BANK_REGNUM
;
2459 return SIM_SH_BANK_MACL_REGNUM
;
2461 return SIM_SH_BANK_GBR_REGNUM
;
2463 return SIM_SH_BANK_PR_REGNUM
;
2465 return SIM_SH_BANK_IVN_REGNUM
;
2467 return SIM_SH_BANK_MACH_REGNUM
;
2471 return legacy_register_sim_regno (gdbarch
, nr
);
2474 /* Set up the register unwinding such that call-clobbered registers are
2475 not displayed in frames >0 because the true value is not certain.
2476 The 'undefined' registers will show up as 'not available' unless the
2479 This function is currently set up for SH4 and compatible only. */
2482 sh_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
2483 struct dwarf2_frame_state_reg
*reg
,
2484 struct frame_info
*this_frame
)
2486 /* Mark the PC as the destination for the return address. */
2487 if (regnum
== gdbarch_pc_regnum (gdbarch
))
2488 reg
->how
= DWARF2_FRAME_REG_RA
;
2490 /* Mark the stack pointer as the call frame address. */
2491 else if (regnum
== gdbarch_sp_regnum (gdbarch
))
2492 reg
->how
= DWARF2_FRAME_REG_CFA
;
2494 /* The above was taken from the default init_reg in dwarf2-frame.c
2495 while the below is SH specific. */
2497 /* Caller save registers. */
2498 else if ((regnum
>= R0_REGNUM
&& regnum
<= R0_REGNUM
+7)
2499 || (regnum
>= FR0_REGNUM
&& regnum
<= FR0_REGNUM
+11)
2500 || (regnum
>= DR0_REGNUM
&& regnum
<= DR0_REGNUM
+5)
2501 || (regnum
>= FV0_REGNUM
&& regnum
<= FV0_REGNUM
+2)
2502 || (regnum
== MACH_REGNUM
)
2503 || (regnum
== MACL_REGNUM
)
2504 || (regnum
== FPUL_REGNUM
)
2505 || (regnum
== SR_REGNUM
))
2506 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
2508 /* Callee save registers. */
2509 else if ((regnum
>= R0_REGNUM
+8 && regnum
<= R0_REGNUM
+15)
2510 || (regnum
>= FR0_REGNUM
+12 && regnum
<= FR0_REGNUM
+15)
2511 || (regnum
>= DR0_REGNUM
+6 && regnum
<= DR0_REGNUM
+8)
2512 || (regnum
== FV0_REGNUM
+3))
2513 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
2515 /* Other registers. These are not in the ABI and may or may not
2516 mean anything in frames >0 so don't show them. */
2517 else if ((regnum
>= R0_BANK0_REGNUM
&& regnum
<= R0_BANK0_REGNUM
+15)
2518 || (regnum
== GBR_REGNUM
)
2519 || (regnum
== VBR_REGNUM
)
2520 || (regnum
== FPSCR_REGNUM
)
2521 || (regnum
== SSR_REGNUM
)
2522 || (regnum
== SPC_REGNUM
))
2523 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
2526 static struct sh_frame_cache
*
2527 sh_alloc_frame_cache (void)
2529 struct sh_frame_cache
*cache
;
2532 cache
= FRAME_OBSTACK_ZALLOC (struct sh_frame_cache
);
2536 cache
->saved_sp
= 0;
2537 cache
->sp_offset
= 0;
2540 /* Frameless until proven otherwise. */
2543 /* Saved registers. We initialize these to -1 since zero is a valid
2544 offset (that's where fp is supposed to be stored). */
2545 for (i
= 0; i
< SH_NUM_REGS
; i
++)
2547 cache
->saved_regs
[i
] = -1;
2553 static struct sh_frame_cache
*
2554 sh_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2556 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2557 struct sh_frame_cache
*cache
;
2558 CORE_ADDR current_pc
;
2564 cache
= sh_alloc_frame_cache ();
2565 *this_cache
= cache
;
2567 /* In principle, for normal frames, fp holds the frame pointer,
2568 which holds the base address for the current stack frame.
2569 However, for functions that don't need it, the frame pointer is
2570 optional. For these "frameless" functions the frame pointer is
2571 actually the frame pointer of the calling frame. */
2572 cache
->base
= get_frame_register_unsigned (this_frame
, FP_REGNUM
);
2573 if (cache
->base
== 0)
2576 cache
->pc
= get_frame_func (this_frame
);
2577 current_pc
= get_frame_pc (this_frame
);
2581 fpscr
= get_frame_register_unsigned (this_frame
, FPSCR_REGNUM
);
2582 sh_analyze_prologue (gdbarch
, cache
->pc
, current_pc
, cache
, fpscr
);
2585 if (!cache
->uses_fp
)
2587 /* We didn't find a valid frame, which means that CACHE->base
2588 currently holds the frame pointer for our calling frame. If
2589 we're at the start of a function, or somewhere half-way its
2590 prologue, the function's frame probably hasn't been fully
2591 setup yet. Try to reconstruct the base address for the stack
2592 frame by looking at the stack pointer. For truly "frameless"
2593 functions this might work too. */
2594 cache
->base
= get_frame_register_unsigned
2595 (this_frame
, gdbarch_sp_regnum (gdbarch
));
2598 /* Now that we have the base address for the stack frame we can
2599 calculate the value of sp in the calling frame. */
2600 cache
->saved_sp
= cache
->base
+ cache
->sp_offset
;
2602 /* Adjust all the saved registers such that they contain addresses
2603 instead of offsets. */
2604 for (i
= 0; i
< SH_NUM_REGS
; i
++)
2605 if (cache
->saved_regs
[i
] != -1)
2606 cache
->saved_regs
[i
] = cache
->saved_sp
- cache
->saved_regs
[i
] - 4;
2611 static struct value
*
2612 sh_frame_prev_register (struct frame_info
*this_frame
,
2613 void **this_cache
, int regnum
)
2615 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2616 struct sh_frame_cache
*cache
= sh_frame_cache (this_frame
, this_cache
);
2618 gdb_assert (regnum
>= 0);
2620 if (regnum
== gdbarch_sp_regnum (gdbarch
) && cache
->saved_sp
)
2621 return frame_unwind_got_constant (this_frame
, regnum
, cache
->saved_sp
);
2623 /* The PC of the previous frame is stored in the PR register of
2624 the current frame. Frob regnum so that we pull the value from
2625 the correct place. */
2626 if (regnum
== gdbarch_pc_regnum (gdbarch
))
2629 if (regnum
< SH_NUM_REGS
&& cache
->saved_regs
[regnum
] != -1)
2630 return frame_unwind_got_memory (this_frame
, regnum
,
2631 cache
->saved_regs
[regnum
]);
2633 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
2637 sh_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2638 struct frame_id
*this_id
)
2640 struct sh_frame_cache
*cache
= sh_frame_cache (this_frame
, this_cache
);
2642 /* This marks the outermost frame. */
2643 if (cache
->base
== 0)
2646 *this_id
= frame_id_build (cache
->saved_sp
, cache
->pc
);
2649 static const struct frame_unwind sh_frame_unwind
= {
2651 default_frame_unwind_stop_reason
,
2653 sh_frame_prev_register
,
2655 default_frame_sniffer
2659 sh_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2661 return frame_unwind_register_unsigned (next_frame
,
2662 gdbarch_sp_regnum (gdbarch
));
2666 sh_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2668 return frame_unwind_register_unsigned (next_frame
,
2669 gdbarch_pc_regnum (gdbarch
));
2672 static struct frame_id
2673 sh_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2675 CORE_ADDR sp
= get_frame_register_unsigned (this_frame
,
2676 gdbarch_sp_regnum (gdbarch
));
2677 return frame_id_build (sp
, get_frame_pc (this_frame
));
2681 sh_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2683 struct sh_frame_cache
*cache
= sh_frame_cache (this_frame
, this_cache
);
2688 static const struct frame_base sh_frame_base
= {
2690 sh_frame_base_address
,
2691 sh_frame_base_address
,
2692 sh_frame_base_address
2695 /* The epilogue is defined here as the area at the end of a function,
2696 either on the `ret' instruction itself or after an instruction which
2697 destroys the function's stack frame. */
2699 sh_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2701 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2702 CORE_ADDR func_addr
= 0, func_end
= 0;
2704 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
2707 /* The sh epilogue is max. 14 bytes long. Give another 14 bytes
2708 for a nop and some fixed data (e.g. big offsets) which are
2709 unfortunately also treated as part of the function (which
2710 means, they are below func_end. */
2711 CORE_ADDR addr
= func_end
- 28;
2712 if (addr
< func_addr
+ 4)
2713 addr
= func_addr
+ 4;
2717 /* First search forward until hitting an rts. */
2718 while (addr
< func_end
2719 && !IS_RTS (read_memory_unsigned_integer (addr
, 2, byte_order
)))
2721 if (addr
>= func_end
)
2724 /* At this point we should find a mov.l @r15+,r14 instruction,
2725 either before or after the rts. If not, then the function has
2726 probably no "normal" epilogue and we bail out here. */
2727 inst
= read_memory_unsigned_integer (addr
- 2, 2, byte_order
);
2728 if (IS_RESTORE_FP (read_memory_unsigned_integer (addr
- 2, 2,
2731 else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr
+ 2, 2,
2735 inst
= read_memory_unsigned_integer (addr
- 2, 2, byte_order
);
2737 /* Step over possible lds.l @r15+,macl. */
2738 if (IS_MACL_LDS (inst
))
2741 inst
= read_memory_unsigned_integer (addr
- 2, 2, byte_order
);
2744 /* Step over possible lds.l @r15+,pr. */
2748 inst
= read_memory_unsigned_integer (addr
- 2, 2, byte_order
);
2751 /* Step over possible mov r14,r15. */
2752 if (IS_MOV_FP_SP (inst
))
2755 inst
= read_memory_unsigned_integer (addr
- 2, 2, byte_order
);
2758 /* Now check for FP adjustments, using add #imm,r14 or add rX, r14
2760 while (addr
> func_addr
+ 4
2761 && (IS_ADD_REG_TO_FP (inst
) || IS_ADD_IMM_FP (inst
)))
2764 inst
= read_memory_unsigned_integer (addr
- 2, 2, byte_order
);
2767 /* On SH2a check if the previous instruction was perhaps a MOVI20.
2768 That's allowed for the epilogue. */
2769 if ((gdbarch_bfd_arch_info (gdbarch
)->mach
== bfd_mach_sh2a
2770 || gdbarch_bfd_arch_info (gdbarch
)->mach
== bfd_mach_sh2a_nofpu
)
2771 && addr
> func_addr
+ 6
2772 && IS_MOVI20 (read_memory_unsigned_integer (addr
- 4, 2,
2783 /* Supply register REGNUM from the buffer specified by REGS and LEN
2784 in the register set REGSET to register cache REGCACHE.
2785 REGTABLE specifies where each register can be found in REGS.
2786 If REGNUM is -1, do this for all registers in REGSET. */
2789 sh_corefile_supply_regset (const struct regset
*regset
,
2790 struct regcache
*regcache
,
2791 int regnum
, const void *regs
, size_t len
)
2793 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
2794 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2795 const struct sh_corefile_regmap
*regmap
= (regset
== &sh_corefile_gregset
2796 ? tdep
->core_gregmap
2797 : tdep
->core_fpregmap
);
2800 for (i
= 0; regmap
[i
].regnum
!= -1; i
++)
2802 if ((regnum
== -1 || regnum
== regmap
[i
].regnum
)
2803 && regmap
[i
].offset
+ 4 <= len
)
2804 regcache_raw_supply (regcache
, regmap
[i
].regnum
,
2805 (char *)regs
+ regmap
[i
].offset
);
2809 /* Collect register REGNUM in the register set REGSET from register cache
2810 REGCACHE into the buffer specified by REGS and LEN.
2811 REGTABLE specifies where each register can be found in REGS.
2812 If REGNUM is -1, do this for all registers in REGSET. */
2815 sh_corefile_collect_regset (const struct regset
*regset
,
2816 const struct regcache
*regcache
,
2817 int regnum
, void *regs
, size_t len
)
2819 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
2820 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2821 const struct sh_corefile_regmap
*regmap
= (regset
== &sh_corefile_gregset
2822 ? tdep
->core_gregmap
2823 : tdep
->core_fpregmap
);
2826 for (i
= 0; regmap
[i
].regnum
!= -1; i
++)
2828 if ((regnum
== -1 || regnum
== regmap
[i
].regnum
)
2829 && regmap
[i
].offset
+ 4 <= len
)
2830 regcache_raw_collect (regcache
, regmap
[i
].regnum
,
2831 (char *)regs
+ regmap
[i
].offset
);
2835 /* The following two regsets have the same contents, so it is tempting to
2836 unify them, but they are distiguished by their address, so don't. */
2838 struct regset sh_corefile_gregset
=
2841 sh_corefile_supply_regset
,
2842 sh_corefile_collect_regset
2845 static struct regset sh_corefile_fpregset
=
2848 sh_corefile_supply_regset
,
2849 sh_corefile_collect_regset
2852 static const struct regset
*
2853 sh_regset_from_core_section (struct gdbarch
*gdbarch
, const char *sect_name
,
2856 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2858 if (tdep
->core_gregmap
&& strcmp (sect_name
, ".reg") == 0)
2859 return &sh_corefile_gregset
;
2861 if (tdep
->core_fpregmap
&& strcmp (sect_name
, ".reg2") == 0)
2862 return &sh_corefile_fpregset
;
2868 static struct gdbarch
*
2869 sh_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2871 struct gdbarch
*gdbarch
;
2872 struct gdbarch_tdep
*tdep
;
2874 sh_show_regs
= sh_generic_show_regs
;
2875 switch (info
.bfd_arch_info
->mach
)
2878 sh_show_regs
= sh2e_show_regs
;
2881 sh_show_regs
= sh2a_show_regs
;
2883 case bfd_mach_sh2a_nofpu
:
2884 sh_show_regs
= sh2a_nofpu_show_regs
;
2886 case bfd_mach_sh_dsp
:
2887 sh_show_regs
= sh_dsp_show_regs
;
2891 case bfd_mach_sh3_nommu
:
2892 case bfd_mach_sh2a_nofpu_or_sh3_nommu
:
2893 sh_show_regs
= sh3_show_regs
;
2897 case bfd_mach_sh2a_or_sh3e
:
2898 sh_show_regs
= sh3e_show_regs
;
2901 case bfd_mach_sh3_dsp
:
2902 case bfd_mach_sh4al_dsp
:
2903 sh_show_regs
= sh3_dsp_show_regs
;
2908 case bfd_mach_sh2a_or_sh4
:
2909 sh_show_regs
= sh4_show_regs
;
2912 case bfd_mach_sh4_nofpu
:
2913 case bfd_mach_sh4_nommu_nofpu
:
2914 case bfd_mach_sh4a_nofpu
:
2915 case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu
:
2916 sh_show_regs
= sh4_nofpu_show_regs
;
2920 sh_show_regs
= sh64_show_regs
;
2921 /* SH5 is handled entirely in sh64-tdep.c. */
2922 return sh64_gdbarch_init (info
, arches
);
2925 /* If there is already a candidate, use it. */
2926 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2928 return arches
->gdbarch
;
2930 /* None found, create a new architecture from the information
2932 tdep
= XZALLOC (struct gdbarch_tdep
);
2933 gdbarch
= gdbarch_alloc (&info
, tdep
);
2935 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
2936 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2937 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2938 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2939 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2940 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2941 set_gdbarch_long_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2942 set_gdbarch_ptr_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2944 set_gdbarch_num_regs (gdbarch
, SH_NUM_REGS
);
2945 set_gdbarch_sp_regnum (gdbarch
, 15);
2946 set_gdbarch_pc_regnum (gdbarch
, 16);
2947 set_gdbarch_fp0_regnum (gdbarch
, -1);
2948 set_gdbarch_num_pseudo_regs (gdbarch
, 0);
2950 set_gdbarch_register_type (gdbarch
, sh_default_register_type
);
2951 set_gdbarch_register_reggroup_p (gdbarch
, sh_register_reggroup_p
);
2953 set_gdbarch_breakpoint_from_pc (gdbarch
, sh_breakpoint_from_pc
);
2955 set_gdbarch_print_insn (gdbarch
, print_insn_sh
);
2956 set_gdbarch_register_sim_regno (gdbarch
, legacy_register_sim_regno
);
2958 set_gdbarch_return_value (gdbarch
, sh_return_value_nofpu
);
2960 set_gdbarch_skip_prologue (gdbarch
, sh_skip_prologue
);
2961 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2963 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_nofpu
);
2965 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
2967 set_gdbarch_frame_align (gdbarch
, sh_frame_align
);
2968 set_gdbarch_unwind_sp (gdbarch
, sh_unwind_sp
);
2969 set_gdbarch_unwind_pc (gdbarch
, sh_unwind_pc
);
2970 set_gdbarch_dummy_id (gdbarch
, sh_dummy_id
);
2971 frame_base_set_default (gdbarch
, &sh_frame_base
);
2973 set_gdbarch_in_function_epilogue_p (gdbarch
, sh_in_function_epilogue_p
);
2975 dwarf2_frame_set_init_reg (gdbarch
, sh_dwarf2_frame_init_reg
);
2977 set_gdbarch_regset_from_core_section (gdbarch
, sh_regset_from_core_section
);
2979 switch (info
.bfd_arch_info
->mach
)
2982 set_gdbarch_register_name (gdbarch
, sh_sh_register_name
);
2986 set_gdbarch_register_name (gdbarch
, sh_sh_register_name
);
2990 /* doubles on sh2e and sh3e are actually 4 byte. */
2991 set_gdbarch_double_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2993 set_gdbarch_register_name (gdbarch
, sh_sh2e_register_name
);
2994 set_gdbarch_register_type (gdbarch
, sh_sh3e_register_type
);
2995 set_gdbarch_fp0_regnum (gdbarch
, 25);
2996 set_gdbarch_return_value (gdbarch
, sh_return_value_fpu
);
2997 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_fpu
);
3001 set_gdbarch_register_name (gdbarch
, sh_sh2a_register_name
);
3002 set_gdbarch_register_type (gdbarch
, sh_sh2a_register_type
);
3003 set_gdbarch_register_sim_regno (gdbarch
, sh_sh2a_register_sim_regno
);
3005 set_gdbarch_fp0_regnum (gdbarch
, 25);
3006 set_gdbarch_num_pseudo_regs (gdbarch
, 9);
3007 set_gdbarch_pseudo_register_read (gdbarch
, sh_pseudo_register_read
);
3008 set_gdbarch_pseudo_register_write (gdbarch
, sh_pseudo_register_write
);
3009 set_gdbarch_return_value (gdbarch
, sh_return_value_fpu
);
3010 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_fpu
);
3013 case bfd_mach_sh2a_nofpu
:
3014 set_gdbarch_register_name (gdbarch
, sh_sh2a_nofpu_register_name
);
3015 set_gdbarch_register_sim_regno (gdbarch
, sh_sh2a_register_sim_regno
);
3017 set_gdbarch_num_pseudo_regs (gdbarch
, 1);
3018 set_gdbarch_pseudo_register_read (gdbarch
, sh_pseudo_register_read
);
3019 set_gdbarch_pseudo_register_write (gdbarch
, sh_pseudo_register_write
);
3022 case bfd_mach_sh_dsp
:
3023 set_gdbarch_register_name (gdbarch
, sh_sh_dsp_register_name
);
3024 set_gdbarch_register_sim_regno (gdbarch
, sh_dsp_register_sim_regno
);
3028 case bfd_mach_sh3_nommu
:
3029 case bfd_mach_sh2a_nofpu_or_sh3_nommu
:
3030 set_gdbarch_register_name (gdbarch
, sh_sh3_register_name
);
3034 case bfd_mach_sh2a_or_sh3e
:
3035 /* doubles on sh2e and sh3e are actually 4 byte. */
3036 set_gdbarch_double_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
3038 set_gdbarch_register_name (gdbarch
, sh_sh3e_register_name
);
3039 set_gdbarch_register_type (gdbarch
, sh_sh3e_register_type
);
3040 set_gdbarch_fp0_regnum (gdbarch
, 25);
3041 set_gdbarch_return_value (gdbarch
, sh_return_value_fpu
);
3042 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_fpu
);
3045 case bfd_mach_sh3_dsp
:
3046 set_gdbarch_register_name (gdbarch
, sh_sh3_dsp_register_name
);
3047 set_gdbarch_register_sim_regno (gdbarch
, sh_dsp_register_sim_regno
);
3052 case bfd_mach_sh2a_or_sh4
:
3053 set_gdbarch_register_name (gdbarch
, sh_sh4_register_name
);
3054 set_gdbarch_register_type (gdbarch
, sh_sh4_register_type
);
3055 set_gdbarch_fp0_regnum (gdbarch
, 25);
3056 set_gdbarch_num_pseudo_regs (gdbarch
, 13);
3057 set_gdbarch_pseudo_register_read (gdbarch
, sh_pseudo_register_read
);
3058 set_gdbarch_pseudo_register_write (gdbarch
, sh_pseudo_register_write
);
3059 set_gdbarch_return_value (gdbarch
, sh_return_value_fpu
);
3060 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_fpu
);
3063 case bfd_mach_sh4_nofpu
:
3064 case bfd_mach_sh4a_nofpu
:
3065 case bfd_mach_sh4_nommu_nofpu
:
3066 case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu
:
3067 set_gdbarch_register_name (gdbarch
, sh_sh4_nofpu_register_name
);
3070 case bfd_mach_sh4al_dsp
:
3071 set_gdbarch_register_name (gdbarch
, sh_sh4al_dsp_register_name
);
3072 set_gdbarch_register_sim_regno (gdbarch
, sh_dsp_register_sim_regno
);
3076 set_gdbarch_register_name (gdbarch
, sh_sh_register_name
);
3080 /* Hook in ABI-specific overrides, if they have been registered. */
3081 gdbarch_init_osabi (info
, gdbarch
);
3083 dwarf2_append_unwinders (gdbarch
);
3084 frame_unwind_append_unwinder (gdbarch
, &sh_frame_unwind
);
3090 show_sh_command (char *args
, int from_tty
)
3092 help_list (showshcmdlist
, "show sh ", all_commands
, gdb_stdout
);
3096 set_sh_command (char *args
, int from_tty
)
3099 ("\"set sh\" must be followed by an appropriate subcommand.\n");
3100 help_list (setshcmdlist
, "set sh ", all_commands
, gdb_stdout
);
3103 extern initialize_file_ftype _initialize_sh_tdep
; /* -Wmissing-prototypes */
3106 _initialize_sh_tdep (void)
3108 struct cmd_list_element
*c
;
3110 gdbarch_register (bfd_arch_sh
, sh_gdbarch_init
, NULL
);
3112 add_com ("regs", class_vars
, sh_show_regs_command
, _("Print all registers"));
3114 add_prefix_cmd ("sh", no_class
, set_sh_command
, "SH specific commands.",
3115 &setshcmdlist
, "set sh ", 0, &setlist
);
3116 add_prefix_cmd ("sh", no_class
, show_sh_command
, "SH specific commands.",
3117 &showshcmdlist
, "show sh ", 0, &showlist
);
3119 add_setshow_enum_cmd ("calling-convention", class_vars
, sh_cc_enum
,
3120 &sh_active_calling_convention
,
3121 _("Set calling convention used when calling target "
3122 "functions from GDB."),
3123 _("Show calling convention used when calling target "
3124 "functions from GDB."),
3125 _("gcc - Use GCC calling convention (default).\n"
3126 "renesas - Enforce Renesas calling convention."),
3128 &setshcmdlist
, &showshcmdlist
);