1 /* Target-dependent code for Renesas Super-H, for GDB.
3 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
4 2003, 2004, 2005, 2007, 2008 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 Contributed by Steve Chamberlain
28 #include "frame-base.h"
29 #include "frame-unwind.h"
30 #include "dwarf2-frame.h"
38 #include "gdb_string.h"
39 #include "gdb_assert.h"
40 #include "arch-utils.h"
48 /* registers numbers shared with the simulator */
49 #include "gdb/sim-sh.h"
52 /* Information that is dependent on the processor variant. */
65 struct sh64_frame_cache
72 /* Flag showing that a frame has been created in the prologue code. */
77 /* Saved registers. */
78 CORE_ADDR saved_regs
[SIM_SH64_NR_REGS
];
82 /* Registers of SH5 */
86 DEFAULT_RETURN_REGNUM
= 2,
87 STRUCT_RETURN_REGNUM
= 2,
90 FLOAT_ARGLAST_REGNUM
= 11,
96 /* FPP stands for Floating Point Pair, to avoid confusion with
97 GDB's gdbarch_fp0_regnum, which is the number of the first Floating
98 point register. Unfortunately on the sh5, the floating point
99 registers are called FR, and the floating point pairs are called FP. */
101 FPP_LAST_REGNUM
= 204,
103 FV_LAST_REGNUM
= 220,
105 R_LAST_C_REGNUM
= 236,
112 FPSCR_C_REGNUM
= 243,
115 FP_LAST_C_REGNUM
= 260,
117 DR_LAST_C_REGNUM
= 268,
119 FV_LAST_C_REGNUM
= 272,
120 FPSCR_REGNUM
= SIM_SH64_FPCSR_REGNUM
,
121 SSR_REGNUM
= SIM_SH64_SSR_REGNUM
,
122 SPC_REGNUM
= SIM_SH64_SPC_REGNUM
,
123 TR7_REGNUM
= SIM_SH64_TR0_REGNUM
+ 7,
124 FP_LAST_REGNUM
= SIM_SH64_FR0_REGNUM
+ SIM_SH64_NR_FP_REGS
- 1
128 sh64_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
130 static char *register_names
[] =
132 /* SH MEDIA MODE (ISA 32) */
133 /* general registers (64-bit) 0-63 */
134 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
135 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
136 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
137 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
138 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
139 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
140 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
141 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
146 /* status reg., saved status reg., saved pc reg. (64-bit) 65-67 */
149 /* target registers (64-bit) 68-75*/
150 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7",
152 /* floating point state control register (32-bit) 76 */
155 /* single precision floating point registers (32-bit) 77-140*/
156 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
157 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
158 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
159 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31",
160 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39",
161 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47",
162 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55",
163 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63",
165 /* double precision registers (pseudo) 141-172 */
166 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
167 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30",
168 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46",
169 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62",
171 /* floating point pairs (pseudo) 173-204*/
172 "fp0", "fp2", "fp4", "fp6", "fp8", "fp10", "fp12", "fp14",
173 "fp16", "fp18", "fp20", "fp22", "fp24", "fp26", "fp28", "fp30",
174 "fp32", "fp34", "fp36", "fp38", "fp40", "fp42", "fp44", "fp46",
175 "fp48", "fp50", "fp52", "fp54", "fp56", "fp58", "fp60", "fp62",
177 /* floating point vectors (4 floating point regs) (pseudo) 205-220*/
178 "fv0", "fv4", "fv8", "fv12", "fv16", "fv20", "fv24", "fv28",
179 "fv32", "fv36", "fv40", "fv44", "fv48", "fv52", "fv56", "fv60",
181 /* SH COMPACT MODE (ISA 16) (all pseudo) 221-272*/
182 "r0_c", "r1_c", "r2_c", "r3_c", "r4_c", "r5_c", "r6_c", "r7_c",
183 "r8_c", "r9_c", "r10_c", "r11_c", "r12_c", "r13_c", "r14_c", "r15_c",
185 "gbr_c", "mach_c", "macl_c", "pr_c", "t_c",
187 "fr0_c", "fr1_c", "fr2_c", "fr3_c", "fr4_c", "fr5_c", "fr6_c", "fr7_c",
188 "fr8_c", "fr9_c", "fr10_c", "fr11_c", "fr12_c", "fr13_c", "fr14_c", "fr15_c",
189 "dr0_c", "dr2_c", "dr4_c", "dr6_c", "dr8_c", "dr10_c", "dr12_c", "dr14_c",
190 "fv0_c", "fv4_c", "fv8_c", "fv12_c",
191 /* FIXME!!!! XF0 XF15, XD0 XD14 ?????*/
196 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
198 return register_names
[reg_nr
];
201 #define NUM_PSEUDO_REGS_SH_MEDIA 80
202 #define NUM_PSEUDO_REGS_SH_COMPACT 51
204 /* Macros and functions for setting and testing a bit in a minimal
205 symbol that marks it as 32-bit function. The MSB of the minimal
206 symbol's "info" field is used for this purpose.
208 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
209 i.e. refers to a 32-bit function, and sets a "special" bit in a
210 minimal symbol to mark it as a 32-bit function
211 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
213 #define MSYMBOL_IS_SPECIAL(msym) \
214 MSYMBOL_TARGET_FLAG_1 (msym)
217 sh64_elf_make_msymbol_special (asymbol
*sym
, struct minimal_symbol
*msym
)
222 if (((elf_symbol_type
*)(sym
))->internal_elf_sym
.st_other
== STO_SH5_ISA32
)
224 MSYMBOL_TARGET_FLAG_1 (msym
) = 1;
225 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
229 /* ISA32 (shmedia) function addresses are odd (bit 0 is set). Here
230 are some macros to test, set, or clear bit 0 of addresses. */
231 #define IS_ISA32_ADDR(addr) ((addr) & 1)
232 #define MAKE_ISA32_ADDR(addr) ((addr) | 1)
233 #define UNMAKE_ISA32_ADDR(addr) ((addr) & ~1)
236 pc_is_isa32 (bfd_vma memaddr
)
238 struct minimal_symbol
*sym
;
240 /* If bit 0 of the address is set, assume this is a
241 ISA32 (shmedia) address. */
242 if (IS_ISA32_ADDR (memaddr
))
245 /* A flag indicating that this is a ISA32 function is stored by elfread.c in
246 the high bit of the info field. Use this to decide if the function is
248 sym
= lookup_minimal_symbol_by_pc (memaddr
);
250 return MSYMBOL_IS_SPECIAL (sym
);
255 static const unsigned char *
256 sh64_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
, int *lenptr
)
258 /* The BRK instruction for shmedia is
259 01101111 11110101 11111111 11110000
260 which translates in big endian mode to 0x6f, 0xf5, 0xff, 0xf0
261 and in little endian mode to 0xf0, 0xff, 0xf5, 0x6f */
263 /* The BRK instruction for shcompact is
265 which translates in big endian mode to 0x0, 0x3b
266 and in little endian mode to 0x3b, 0x0*/
268 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
270 if (pc_is_isa32 (*pcptr
))
272 static unsigned char big_breakpoint_media
[] = {0x6f, 0xf5, 0xff, 0xf0};
273 *pcptr
= UNMAKE_ISA32_ADDR (*pcptr
);
274 *lenptr
= sizeof (big_breakpoint_media
);
275 return big_breakpoint_media
;
279 static unsigned char big_breakpoint_compact
[] = {0x0, 0x3b};
280 *lenptr
= sizeof (big_breakpoint_compact
);
281 return big_breakpoint_compact
;
286 if (pc_is_isa32 (*pcptr
))
288 static unsigned char little_breakpoint_media
[] = {0xf0, 0xff, 0xf5, 0x6f};
289 *pcptr
= UNMAKE_ISA32_ADDR (*pcptr
);
290 *lenptr
= sizeof (little_breakpoint_media
);
291 return little_breakpoint_media
;
295 static unsigned char little_breakpoint_compact
[] = {0x3b, 0x0};
296 *lenptr
= sizeof (little_breakpoint_compact
);
297 return little_breakpoint_compact
;
302 /* Prologue looks like
303 [mov.l <regs>,@-r15]...
308 Actually it can be more complicated than this. For instance, with
326 /* PTABS/L Rn, TRa 0110101111110001nnnnnnl00aaa0000
327 with l=1 and n = 18 0110101111110001010010100aaa0000 */
328 #define IS_PTABSL_R18(x) (((x) & 0xffffff8f) == 0x6bf14a00)
330 /* STS.L PR,@-r0 0100000000100010
331 r0-4-->r0, PR-->(r0) */
332 #define IS_STS_R0(x) ((x) == 0x4022)
334 /* STS PR, Rm 0000mmmm00101010
336 #define IS_STS_PR(x) (((x) & 0xf0ff) == 0x2a)
338 /* MOV.L Rm,@(disp,r15) 00011111mmmmdddd
340 #define IS_MOV_TO_R15(x) (((x) & 0xff00) == 0x1f00)
342 /* MOV.L R14,@(disp,r15) 000111111110dddd
343 R14-->(dispx4+r15) */
344 #define IS_MOV_R14(x) (((x) & 0xfff0) == 0x1fe0)
346 /* ST.Q R14, disp, R18 101011001110dddddddddd0100100000
347 R18-->(dispx8+R14) */
348 #define IS_STQ_R18_R14(x) (((x) & 0xfff003ff) == 0xace00120)
350 /* ST.Q R15, disp, R18 101011001111dddddddddd0100100000
351 R18-->(dispx8+R15) */
352 #define IS_STQ_R18_R15(x) (((x) & 0xfff003ff) == 0xacf00120)
354 /* ST.L R15, disp, R18 101010001111dddddddddd0100100000
355 R18-->(dispx4+R15) */
356 #define IS_STL_R18_R15(x) (((x) & 0xfff003ff) == 0xa8f00120)
358 /* ST.Q R15, disp, R14 1010 1100 1111 dddd dddd dd00 1110 0000
359 R14-->(dispx8+R15) */
360 #define IS_STQ_R14_R15(x) (((x) & 0xfff003ff) == 0xacf000e0)
362 /* ST.L R15, disp, R14 1010 1000 1111 dddd dddd dd00 1110 0000
363 R14-->(dispx4+R15) */
364 #define IS_STL_R14_R15(x) (((x) & 0xfff003ff) == 0xa8f000e0)
366 /* ADDI.L R15,imm,R15 1101 0100 1111 ssss ssss ss00 1111 0000
368 #define IS_ADDIL_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd4f000f0)
370 /* ADDI R15,imm,R15 1101 0000 1111 ssss ssss ss00 1111 0000
372 #define IS_ADDI_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd0f000f0)
374 /* ADD.L R15,R63,R14 0000 0000 1111 1000 1111 1100 1110 0000
376 #define IS_ADDL_SP_FP_MEDIA(x) ((x) == 0x00f8fce0)
378 /* ADD R15,R63,R14 0000 0000 1111 1001 1111 1100 1110 0000
380 #define IS_ADD_SP_FP_MEDIA(x) ((x) == 0x00f9fce0)
382 #define IS_MOV_SP_FP_MEDIA(x) (IS_ADDL_SP_FP_MEDIA(x) || IS_ADD_SP_FP_MEDIA(x))
384 /* MOV #imm, R0 1110 0000 ssss ssss
386 #define IS_MOV_R0(x) (((x) & 0xff00) == 0xe000)
388 /* MOV.L @(disp,PC), R0 1101 0000 iiii iiii */
389 #define IS_MOVL_R0(x) (((x) & 0xff00) == 0xd000)
391 /* ADD r15,r0 0011 0000 1111 1100
393 #define IS_ADD_SP_R0(x) ((x) == 0x30fc)
395 /* MOV.L R14 @-R0 0010 0000 1110 0110
396 R14-->(R0-4), R0-4-->R0 */
397 #define IS_MOV_R14_R0(x) ((x) == 0x20e6)
399 /* ADD Rm,R63,Rn Rm+R63-->Rn 0000 00mm mmmm 1001 1111 11nn nnnn 0000
400 where Rm is one of r2-r9 which are the argument registers. */
401 /* FIXME: Recognize the float and double register moves too! */
402 #define IS_MEDIA_IND_ARG_MOV(x) \
403 ((((x) & 0xfc0ffc0f) == 0x0009fc00) && (((x) & 0x03f00000) >= 0x00200000 && ((x) & 0x03f00000) <= 0x00900000))
405 /* ST.Q Rn,0,Rm Rm-->Rn+0 1010 11nn nnnn 0000 0000 00mm mmmm 0000
406 or ST.L Rn,0,Rm Rm-->Rn+0 1010 10nn nnnn 0000 0000 00mm mmmm 0000
407 where Rm is one of r2-r9 which are the argument registers. */
408 #define IS_MEDIA_ARG_MOV(x) \
409 (((((x) & 0xfc0ffc0f) == 0xac000000) || (((x) & 0xfc0ffc0f) == 0xa8000000)) \
410 && (((x) & 0x000003f0) >= 0x00000020 && ((x) & 0x000003f0) <= 0x00000090))
412 /* ST.B R14,0,Rn Rn-->(R14+0) 1010 0000 1110 0000 0000 00nn nnnn 0000*/
413 /* ST.W R14,0,Rn Rn-->(R14+0) 1010 0100 1110 0000 0000 00nn nnnn 0000*/
414 /* ST.L R14,0,Rn Rn-->(R14+0) 1010 1000 1110 0000 0000 00nn nnnn 0000*/
415 /* FST.S R14,0,FRn Rn-->(R14+0) 1011 0100 1110 0000 0000 00nn nnnn 0000*/
416 /* FST.D R14,0,DRn Rn-->(R14+0) 1011 1100 1110 0000 0000 00nn nnnn 0000*/
417 #define IS_MEDIA_MOV_TO_R14(x) \
418 ((((x) & 0xfffffc0f) == 0xa0e00000) \
419 || (((x) & 0xfffffc0f) == 0xa4e00000) \
420 || (((x) & 0xfffffc0f) == 0xa8e00000) \
421 || (((x) & 0xfffffc0f) == 0xb4e00000) \
422 || (((x) & 0xfffffc0f) == 0xbce00000))
424 /* MOV Rm, Rn Rm-->Rn 0110 nnnn mmmm 0011
426 #define IS_COMPACT_IND_ARG_MOV(x) \
427 ((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0020) && (((x) & 0x00f0) <= 0x0090))
429 /* compact direct arg move!
430 MOV.L Rn, @r14 0010 1110 mmmm 0010 */
431 #define IS_COMPACT_ARG_MOV(x) \
432 (((((x) & 0xff0f) == 0x2e02) && (((x) & 0x00f0) >= 0x0020) && ((x) & 0x00f0) <= 0x0090))
434 /* MOV.B Rm, @R14 0010 1110 mmmm 0000
435 MOV.W Rm, @R14 0010 1110 mmmm 0001 */
436 #define IS_COMPACT_MOV_TO_R14(x) \
437 ((((x) & 0xff0f) == 0x2e00) || (((x) & 0xff0f) == 0x2e01))
439 #define IS_JSR_R0(x) ((x) == 0x400b)
440 #define IS_NOP(x) ((x) == 0x0009)
443 /* MOV r15,r14 0110111011110011
445 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
447 /* ADD #imm,r15 01111111iiiiiiii
449 #define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00)
451 /* Skip any prologue before the guts of a function */
453 /* Skip the prologue using the debug information. If this fails we'll
454 fall back on the 'guess' method below. */
456 after_prologue (CORE_ADDR pc
)
458 struct symtab_and_line sal
;
459 CORE_ADDR func_addr
, func_end
;
461 /* If we can not find the symbol in the partial symbol table, then
462 there is no hope we can determine the function's start address
464 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
468 /* Get the line associated with FUNC_ADDR. */
469 sal
= find_pc_line (func_addr
, 0);
471 /* There are only two cases to consider. First, the end of the source line
472 is within the function bounds. In that case we return the end of the
473 source line. Second is the end of the source line extends beyond the
474 bounds of the current function. We need to use the slow code to
475 examine instructions in that case. */
476 if (sal
.end
< func_end
)
483 look_for_args_moves (CORE_ADDR start_pc
, int media_mode
)
487 int insn_size
= (media_mode
? 4 : 2);
489 for (here
= start_pc
, end
= start_pc
+ (insn_size
* 28); here
< end
;)
493 w
= read_memory_integer (UNMAKE_ISA32_ADDR (here
), insn_size
);
495 if (IS_MEDIA_IND_ARG_MOV (w
))
497 /* This must be followed by a store to r14, so the argument
498 is where the debug info says it is. This can happen after
499 the SP has been saved, unfortunately. */
501 int next_insn
= read_memory_integer (UNMAKE_ISA32_ADDR (here
),
504 if (IS_MEDIA_MOV_TO_R14 (next_insn
))
507 else if (IS_MEDIA_ARG_MOV (w
))
509 /* These instructions store directly the argument in r14. */
517 w
= read_memory_integer (here
, insn_size
);
520 if (IS_COMPACT_IND_ARG_MOV (w
))
522 /* This must be followed by a store to r14, so the argument
523 is where the debug info says it is. This can happen after
524 the SP has been saved, unfortunately. */
526 int next_insn
= 0xffff & read_memory_integer (here
, insn_size
);
528 if (IS_COMPACT_MOV_TO_R14 (next_insn
))
531 else if (IS_COMPACT_ARG_MOV (w
))
533 /* These instructions store directly the argument in r14. */
536 else if (IS_MOVL_R0 (w
))
538 /* There is a function that gcc calls to get the arguments
539 passed correctly to the function. Only after this
540 function call the arguments will be found at the place
541 where they are supposed to be. This happens in case the
542 argument has to be stored into a 64-bit register (for
543 instance doubles, long longs). SHcompact doesn't have
544 access to the full 64-bits, so we store the register in
545 stack slot and store the address of the stack slot in
546 the register, then do a call through a wrapper that
547 loads the memory value into the register. A SHcompact
548 callee calls an argument decoder
549 (GCC_shcompact_incoming_args) that stores the 64-bit
550 value in a stack slot and stores the address of the
551 stack slot in the register. GCC thinks the argument is
552 just passed by transparent reference, but this is only
553 true after the argument decoder is called. Such a call
554 needs to be considered part of the prologue. */
556 /* This must be followed by a JSR @r0 instruction and by
557 a NOP instruction. After these, the prologue is over! */
559 int next_insn
= 0xffff & read_memory_integer (here
, insn_size
);
561 if (IS_JSR_R0 (next_insn
))
563 next_insn
= 0xffff & read_memory_integer (here
, insn_size
);
566 if (IS_NOP (next_insn
))
579 sh64_skip_prologue_hard_way (CORE_ADDR start_pc
)
589 if (pc_is_isa32 (start_pc
) == 0)
595 for (here
= start_pc
, end
= start_pc
+ (insn_size
* 28); here
< end
;)
600 int w
= read_memory_integer (UNMAKE_ISA32_ADDR (here
), insn_size
);
602 if (IS_STQ_R18_R14 (w
) || IS_STQ_R18_R15 (w
) || IS_STQ_R14_R15 (w
)
603 || IS_STL_R14_R15 (w
) || IS_STL_R18_R15 (w
)
604 || IS_ADDIL_SP_MEDIA (w
) || IS_ADDI_SP_MEDIA (w
) || IS_PTABSL_R18 (w
))
608 else if (IS_MOV_SP_FP (w
) || IS_MOV_SP_FP_MEDIA(w
))
616 /* Don't bail out yet, we may have arguments stored in
617 registers here, according to the debug info, so that
618 gdb can print the frames correctly. */
619 start_pc
= look_for_args_moves (here
- insn_size
, media_mode
);
625 int w
= 0xffff & read_memory_integer (here
, insn_size
);
628 if (IS_STS_R0 (w
) || IS_STS_PR (w
)
629 || IS_MOV_TO_R15 (w
) || IS_MOV_R14 (w
)
630 || IS_MOV_R0 (w
) || IS_ADD_SP_R0 (w
) || IS_MOV_R14_R0 (w
))
634 else if (IS_MOV_SP_FP (w
))
642 /* Don't bail out yet, we may have arguments stored in
643 registers here, according to the debug info, so that
644 gdb can print the frames correctly. */
645 start_pc
= look_for_args_moves (here
- insn_size
, media_mode
);
655 sh64_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
657 CORE_ADDR post_prologue_pc
;
659 /* See if we can determine the end of the prologue via the symbol table.
660 If so, then return either PC, or the PC after the prologue, whichever
662 post_prologue_pc
= after_prologue (pc
);
664 /* If after_prologue returned a useful address, then use it. Else
665 fall back on the instruction skipping code. */
666 if (post_prologue_pc
!= 0)
667 return max (pc
, post_prologue_pc
);
669 return sh64_skip_prologue_hard_way (pc
);
672 /* Should call_function allocate stack space for a struct return? */
674 sh64_use_struct_convention (struct type
*type
)
676 return (TYPE_LENGTH (type
) > 8);
679 /* For vectors of 4 floating point registers. */
681 sh64_fv_reg_base_num (struct gdbarch
*gdbarch
, int fv_regnum
)
685 fp_regnum
= gdbarch_fp0_regnum (gdbarch
) + (fv_regnum
- FV0_REGNUM
) * 4;
689 /* For double precision floating point registers, i.e 2 fp regs.*/
691 sh64_dr_reg_base_num (struct gdbarch
*gdbarch
, int dr_regnum
)
695 fp_regnum
= gdbarch_fp0_regnum (gdbarch
) + (dr_regnum
- DR0_REGNUM
) * 2;
699 /* For pairs of floating point registers */
701 sh64_fpp_reg_base_num (struct gdbarch
*gdbarch
, int fpp_regnum
)
705 fp_regnum
= gdbarch_fp0_regnum (gdbarch
) + (fpp_regnum
- FPP0_REGNUM
) * 2;
711 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
712 GDB_REGNUM BASE_REGNUM
772 sh64_compact_reg_base_num (struct gdbarch
*gdbarch
, int reg_nr
)
774 int base_regnum
= reg_nr
;
776 /* general register N maps to general register N */
777 if (reg_nr
>= R0_C_REGNUM
778 && reg_nr
<= R_LAST_C_REGNUM
)
779 base_regnum
= reg_nr
- R0_C_REGNUM
;
781 /* floating point register N maps to floating point register N */
782 else if (reg_nr
>= FP0_C_REGNUM
783 && reg_nr
<= FP_LAST_C_REGNUM
)
784 base_regnum
= reg_nr
- FP0_C_REGNUM
+ gdbarch_fp0_regnum (gdbarch
);
786 /* double prec register N maps to base regnum for double prec register N */
787 else if (reg_nr
>= DR0_C_REGNUM
788 && reg_nr
<= DR_LAST_C_REGNUM
)
789 base_regnum
= sh64_dr_reg_base_num (gdbarch
,
790 DR0_REGNUM
+ reg_nr
- DR0_C_REGNUM
);
792 /* vector N maps to base regnum for vector register N */
793 else if (reg_nr
>= FV0_C_REGNUM
794 && reg_nr
<= FV_LAST_C_REGNUM
)
795 base_regnum
= sh64_fv_reg_base_num (gdbarch
,
796 FV0_REGNUM
+ reg_nr
- FV0_C_REGNUM
);
798 else if (reg_nr
== PC_C_REGNUM
)
799 base_regnum
= gdbarch_pc_regnum (gdbarch
);
801 else if (reg_nr
== GBR_C_REGNUM
)
804 else if (reg_nr
== MACH_C_REGNUM
805 || reg_nr
== MACL_C_REGNUM
)
808 else if (reg_nr
== PR_C_REGNUM
)
809 base_regnum
= PR_REGNUM
;
811 else if (reg_nr
== T_C_REGNUM
)
814 else if (reg_nr
== FPSCR_C_REGNUM
)
815 base_regnum
= FPSCR_REGNUM
; /*???? this register is a mess. */
817 else if (reg_nr
== FPUL_C_REGNUM
)
818 base_regnum
= gdbarch_fp0_regnum (gdbarch
) + 32;
824 sign_extend (int value
, int bits
)
826 value
= value
& ((1 << bits
) - 1);
827 return (value
& (1 << (bits
- 1))
828 ? value
| (~((1 << bits
) - 1))
833 sh64_analyze_prologue (struct gdbarch
*gdbarch
,
834 struct sh64_frame_cache
*cache
,
836 CORE_ADDR current_pc
)
844 int gdb_register_number
;
846 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
848 cache
->sp_offset
= 0;
850 /* Loop around examining the prologue insns until we find something
851 that does not appear to be part of the prologue. But give up
852 after 20 of them, since we're getting silly then. */
856 if (cache
->media_mode
)
861 opc
= pc
+ (insn_size
* 28);
862 if (opc
> current_pc
)
864 for ( ; pc
<= opc
; pc
+= insn_size
)
866 insn
= read_memory_integer (cache
->media_mode
? UNMAKE_ISA32_ADDR (pc
)
870 if (!cache
->media_mode
)
872 if (IS_STS_PR (insn
))
874 int next_insn
= read_memory_integer (pc
+ insn_size
, insn_size
);
875 if (IS_MOV_TO_R15 (next_insn
))
877 cache
->saved_regs
[PR_REGNUM
] =
878 cache
->sp_offset
- ((((next_insn
& 0xf) ^ 0x8) - 0x8) << 2);
883 else if (IS_MOV_R14 (insn
))
884 cache
->saved_regs
[MEDIA_FP_REGNUM
] =
885 cache
->sp_offset
- ((((insn
& 0xf) ^ 0x8) - 0x8) << 2);
887 else if (IS_MOV_R0 (insn
))
889 /* Put in R0 the offset from SP at which to store some
890 registers. We are interested in this value, because it
891 will tell us where the given registers are stored within
893 r0_val
= ((insn
& 0xff) ^ 0x80) - 0x80;
896 else if (IS_ADD_SP_R0 (insn
))
898 /* This instruction still prepares r0, but we don't care.
899 We already have the offset in r0_val. */
902 else if (IS_STS_R0 (insn
))
904 /* Store PR at r0_val-4 from SP. Decrement r0 by 4*/
905 cache
->saved_regs
[PR_REGNUM
] = cache
->sp_offset
- (r0_val
- 4);
909 else if (IS_MOV_R14_R0 (insn
))
911 /* Store R14 at r0_val-4 from SP. Decrement r0 by 4 */
912 cache
->saved_regs
[MEDIA_FP_REGNUM
] = cache
->sp_offset
917 else if (IS_ADD_SP (insn
))
918 cache
->sp_offset
-= ((insn
& 0xff) ^ 0x80) - 0x80;
920 else if (IS_MOV_SP_FP (insn
))
925 if (IS_ADDIL_SP_MEDIA (insn
) || IS_ADDI_SP_MEDIA (insn
))
927 sign_extend ((((insn
& 0xffc00) ^ 0x80000) - 0x80000) >> 10, 9);
929 else if (IS_STQ_R18_R15 (insn
))
930 cache
->saved_regs
[PR_REGNUM
] =
931 cache
->sp_offset
- (sign_extend ((insn
& 0xffc00) >> 10, 9) << 3);
933 else if (IS_STL_R18_R15 (insn
))
934 cache
->saved_regs
[PR_REGNUM
] =
935 cache
->sp_offset
- (sign_extend ((insn
& 0xffc00) >> 10, 9) << 2);
937 else if (IS_STQ_R14_R15 (insn
))
938 cache
->saved_regs
[MEDIA_FP_REGNUM
] =
939 cache
->sp_offset
- (sign_extend ((insn
& 0xffc00) >> 10, 9) << 3);
941 else if (IS_STL_R14_R15 (insn
))
942 cache
->saved_regs
[MEDIA_FP_REGNUM
] =
943 cache
->sp_offset
- (sign_extend ((insn
& 0xffc00) >> 10, 9) << 2);
945 else if (IS_MOV_SP_FP_MEDIA (insn
))
950 if (cache
->saved_regs
[MEDIA_FP_REGNUM
] >= 0)
955 sh64_frame_align (struct gdbarch
*ignore
, CORE_ADDR sp
)
960 /* Function: push_dummy_call
961 Setup the function arguments for calling a function in the inferior.
963 On the Renesas SH architecture, there are four registers (R4 to R7)
964 which are dedicated for passing function arguments. Up to the first
965 four arguments (depending on size) may go into these registers.
966 The rest go on the stack.
968 Arguments that are smaller than 4 bytes will still take up a whole
969 register or a whole 32-bit word on the stack, and will be
970 right-justified in the register or the stack word. This includes
971 chars, shorts, and small aggregate types.
973 Arguments that are larger than 4 bytes may be split between two or
974 more registers. If there are not enough registers free, an argument
975 may be passed partly in a register (or registers), and partly on the
976 stack. This includes doubles, long longs, and larger aggregates.
977 As far as I know, there is no upper limit to the size of aggregates
978 that will be passed in this way; in other words, the convention of
979 passing a pointer to a large aggregate instead of a copy is not used.
981 An exceptional case exists for struct arguments (and possibly other
982 aggregates such as arrays) if the size is larger than 4 bytes but
983 not a multiple of 4 bytes. In this case the argument is never split
984 between the registers and the stack, but instead is copied in its
985 entirety onto the stack, AND also copied into as many registers as
986 there is room for. In other words, space in registers permitting,
987 two copies of the same argument are passed in. As far as I can tell,
988 only the one on the stack is used, although that may be a function
989 of the level of compiler optimization. I suspect this is a compiler
990 bug. Arguments of these odd sizes are left-justified within the
991 word (as opposed to arguments smaller than 4 bytes, which are
994 If the function is to return an aggregate type such as a struct, it
995 is either returned in the normal return value register R0 (if its
996 size is no greater than one byte), or else the caller must allocate
997 space into which the callee will copy the return value (if the size
998 is greater than one byte). In this case, a pointer to the return
999 value location is passed into the callee in register R2, which does
1000 not displace any of the other arguments passed in via registers R4
1003 /* R2-R9 for integer types and integer equivalent (char, pointers) and
1004 non-scalar (struct, union) elements (even if the elements are
1006 FR0-FR11 for single precision floating point (float)
1007 DR0-DR10 for double precision floating point (double)
1009 If a float is argument number 3 (for instance) and arguments number
1010 1,2, and 4 are integer, the mapping will be:
1011 arg1 -->R2, arg2 --> R3, arg3 -->FR0, arg4 --> R5. I.e. R4 is not used.
1013 If a float is argument number 10 (for instance) and arguments number
1014 1 through 10 are integer, the mapping will be:
1015 arg1->R2, arg2->R3, arg3->R4, arg4->R5, arg5->R6, arg6->R7, arg7->R8,
1016 arg8->R9, arg9->(0,SP)stack(8-byte aligned), arg10->FR0, arg11->stack(16,SP).
1017 I.e. there is hole in the stack.
1019 Different rules apply for variable arguments functions, and for functions
1020 for which the prototype is not known. */
1023 sh64_push_dummy_call (struct gdbarch
*gdbarch
,
1024 struct value
*function
,
1025 struct regcache
*regcache
,
1027 int nargs
, struct value
**args
,
1028 CORE_ADDR sp
, int struct_return
,
1029 CORE_ADDR struct_addr
)
1031 int stack_offset
, stack_alloc
;
1035 int float_arg_index
= 0;
1036 int double_arg_index
= 0;
1047 memset (fp_args
, 0, sizeof (fp_args
));
1049 /* first force sp to a 8-byte alignment */
1050 sp
= sh64_frame_align (gdbarch
, sp
);
1052 /* The "struct return pointer" pseudo-argument has its own dedicated
1056 regcache_cooked_write_unsigned (regcache
,
1057 STRUCT_RETURN_REGNUM
, struct_addr
);
1059 /* Now make sure there's space on the stack */
1060 for (argnum
= 0, stack_alloc
= 0; argnum
< nargs
; argnum
++)
1061 stack_alloc
+= ((TYPE_LENGTH (value_type (args
[argnum
])) + 7) & ~7);
1062 sp
-= stack_alloc
; /* make room on stack for args */
1064 /* Now load as many as possible of the first arguments into
1065 registers, and push the rest onto the stack. There are 64 bytes
1066 in eight registers available. Loop thru args from first to last. */
1068 int_argreg
= ARG0_REGNUM
;
1069 float_argreg
= gdbarch_fp0_regnum (gdbarch
);
1070 double_argreg
= DR0_REGNUM
;
1072 for (argnum
= 0, stack_offset
= 0; argnum
< nargs
; argnum
++)
1074 type
= value_type (args
[argnum
]);
1075 len
= TYPE_LENGTH (type
);
1076 memset (valbuf
, 0, sizeof (valbuf
));
1078 if (TYPE_CODE (type
) != TYPE_CODE_FLT
)
1080 argreg_size
= register_size (gdbarch
, int_argreg
);
1082 if (len
< argreg_size
)
1084 /* value gets right-justified in the register or stack word */
1085 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1086 memcpy (valbuf
+ argreg_size
- len
,
1087 (char *) value_contents (args
[argnum
]), len
);
1089 memcpy (valbuf
, (char *) value_contents (args
[argnum
]), len
);
1094 val
= (char *) value_contents (args
[argnum
]);
1098 if (int_argreg
> ARGLAST_REGNUM
)
1100 /* must go on the stack */
1101 write_memory (sp
+ stack_offset
, (const bfd_byte
*) val
,
1103 stack_offset
+= 8;/*argreg_size;*/
1105 /* NOTE WELL!!!!! This is not an "else if" clause!!!
1106 That's because some *&^%$ things get passed on the stack
1107 AND in the registers! */
1108 if (int_argreg
<= ARGLAST_REGNUM
)
1110 /* there's room in a register */
1111 regval
= extract_unsigned_integer (val
, argreg_size
);
1112 regcache_cooked_write_unsigned (regcache
, int_argreg
, regval
);
1114 /* Store the value 8 bytes at a time. This means that
1115 things larger than 8 bytes may go partly in registers
1116 and partly on the stack. FIXME: argreg is incremented
1117 before we use its size. */
1125 val
= (char *) value_contents (args
[argnum
]);
1128 /* Where is it going to be stored? */
1129 while (fp_args
[float_arg_index
])
1132 /* Now float_argreg points to the register where it
1133 should be stored. Are we still within the allowed
1135 if (float_arg_index
<= FLOAT_ARGLAST_REGNUM
)
1137 /* Goes in FR0...FR11 */
1138 regcache_cooked_write (regcache
,
1139 gdbarch_fp0_regnum (gdbarch
)
1142 fp_args
[float_arg_index
] = 1;
1143 /* Skip the corresponding general argument register. */
1148 /* Store it as the integers, 8 bytes at the time, if
1149 necessary spilling on the stack. */
1154 /* Where is it going to be stored? */
1155 while (fp_args
[double_arg_index
])
1156 double_arg_index
+= 2;
1157 /* Now double_argreg points to the register
1158 where it should be stored.
1159 Are we still within the allowed register set? */
1160 if (double_arg_index
< FLOAT_ARGLAST_REGNUM
)
1162 /* Goes in DR0...DR10 */
1163 /* The numbering of the DRi registers is consecutive,
1164 i.e. includes odd numbers. */
1165 int double_register_offset
= double_arg_index
/ 2;
1166 int regnum
= DR0_REGNUM
+ double_register_offset
;
1167 regcache_cooked_write (regcache
, regnum
, val
);
1168 fp_args
[double_arg_index
] = 1;
1169 fp_args
[double_arg_index
+ 1] = 1;
1170 /* Skip the corresponding general argument register. */
1175 /* Store it as the integers, 8 bytes at the time, if
1176 necessary spilling on the stack. */
1180 /* Store return address. */
1181 regcache_cooked_write_unsigned (regcache
, PR_REGNUM
, bp_addr
);
1183 /* Update stack pointer. */
1184 regcache_cooked_write_unsigned (regcache
,
1185 gdbarch_sp_regnum (gdbarch
), sp
);
1190 /* Find a function's return value in the appropriate registers (in
1191 regbuf), and copy it into valbuf. Extract from an array REGBUF
1192 containing the (raw) register state a function return value of type
1193 TYPE, and copy that, in virtual format, into VALBUF. */
1195 sh64_extract_return_value (struct type
*type
, struct regcache
*regcache
,
1198 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1199 int len
= TYPE_LENGTH (type
);
1201 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1205 /* Return value stored in gdbarch_fp0_regnum */
1206 regcache_raw_read (regcache
,
1207 gdbarch_fp0_regnum (gdbarch
), valbuf
);
1211 /* return value stored in DR0_REGNUM */
1215 regcache_cooked_read (regcache
, DR0_REGNUM
, buf
);
1217 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
1218 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword
,
1221 floatformat_to_doublest (&floatformat_ieee_double_big
,
1223 store_typed_floating (valbuf
, type
, val
);
1232 /* Result is in register 2. If smaller than 8 bytes, it is padded
1233 at the most significant end. */
1234 regcache_raw_read (regcache
, DEFAULT_RETURN_REGNUM
, buf
);
1236 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1237 offset
= register_size (gdbarch
, DEFAULT_RETURN_REGNUM
)
1241 memcpy (valbuf
, buf
+ offset
, len
);
1244 error ("bad size for return value");
1248 /* Write into appropriate registers a function return value
1249 of type TYPE, given in virtual format.
1250 If the architecture is sh4 or sh3e, store a function's return value
1251 in the R0 general register or in the FP0 floating point register,
1252 depending on the type of the return value. In all the other cases
1253 the result is stored in r0, left-justified. */
1256 sh64_store_return_value (struct type
*type
, struct regcache
*regcache
,
1259 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1260 char buf
[64]; /* more than enough... */
1261 int len
= TYPE_LENGTH (type
);
1263 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1265 int i
, regnum
= gdbarch_fp0_regnum (gdbarch
);
1266 for (i
= 0; i
< len
; i
+= 4)
1267 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
1268 regcache_raw_write (regcache
, regnum
++,
1269 (char *) valbuf
+ len
- 4 - i
);
1271 regcache_raw_write (regcache
, regnum
++, (char *) valbuf
+ i
);
1275 int return_register
= DEFAULT_RETURN_REGNUM
;
1278 if (len
<= register_size (gdbarch
, return_register
))
1280 /* Pad with zeros. */
1281 memset (buf
, 0, register_size (gdbarch
, return_register
));
1282 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
1283 offset
= 0; /*register_size (gdbarch,
1284 return_register) - len;*/
1286 offset
= register_size (gdbarch
, return_register
) - len
;
1288 memcpy (buf
+ offset
, valbuf
, len
);
1289 regcache_raw_write (regcache
, return_register
, buf
);
1292 regcache_raw_write (regcache
, return_register
, valbuf
);
1296 static enum return_value_convention
1297 sh64_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
1298 struct type
*type
, struct regcache
*regcache
,
1299 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1301 if (sh64_use_struct_convention (type
))
1302 return RETURN_VALUE_STRUCT_CONVENTION
;
1304 sh64_store_return_value (type
, regcache
, writebuf
);
1306 sh64_extract_return_value (type
, regcache
, readbuf
);
1307 return RETURN_VALUE_REGISTER_CONVENTION
;
1311 sh64_show_media_regs (struct frame_info
*frame
)
1313 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1317 ("PC=%s SR=%016llx \n",
1318 paddr (get_frame_register_unsigned (frame
,
1319 gdbarch_pc_regnum (gdbarch
))),
1320 (long long) get_frame_register_unsigned (frame
, SR_REGNUM
));
1323 ("SSR=%016llx SPC=%016llx \n",
1324 (long long) get_frame_register_unsigned (frame
, SSR_REGNUM
),
1325 (long long) get_frame_register_unsigned (frame
, SPC_REGNUM
));
1328 (long) get_frame_register_unsigned (frame
, FPSCR_REGNUM
));
1330 for (i
= 0; i
< 64; i
= i
+ 4)
1332 ("\nR%d-R%d %016llx %016llx %016llx %016llx\n",
1334 (long long) get_frame_register_unsigned (frame
, i
+ 0),
1335 (long long) get_frame_register_unsigned (frame
, i
+ 1),
1336 (long long) get_frame_register_unsigned (frame
, i
+ 2),
1337 (long long) get_frame_register_unsigned (frame
, i
+ 3));
1339 printf_filtered ("\n");
1341 for (i
= 0; i
< 64; i
= i
+ 8)
1343 ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1345 (long) get_frame_register_unsigned
1346 (frame
, gdbarch_fp0_regnum (gdbarch
) + i
+ 0),
1347 (long) get_frame_register_unsigned
1348 (frame
, gdbarch_fp0_regnum (gdbarch
) + i
+ 1),
1349 (long) get_frame_register_unsigned
1350 (frame
, gdbarch_fp0_regnum (gdbarch
) + i
+ 2),
1351 (long) get_frame_register_unsigned
1352 (frame
, gdbarch_fp0_regnum (gdbarch
) + i
+ 3),
1353 (long) get_frame_register_unsigned
1354 (frame
, gdbarch_fp0_regnum (gdbarch
) + i
+ 4),
1355 (long) get_frame_register_unsigned
1356 (frame
, gdbarch_fp0_regnum (gdbarch
) + i
+ 5),
1357 (long) get_frame_register_unsigned
1358 (frame
, gdbarch_fp0_regnum (gdbarch
) + i
+ 6),
1359 (long) get_frame_register_unsigned
1360 (frame
, gdbarch_fp0_regnum (gdbarch
) + i
+ 7));
1364 sh64_show_compact_regs (struct frame_info
*frame
)
1366 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1371 paddr (get_frame_register_unsigned (frame
, PC_C_REGNUM
)));
1374 ("GBR=%08lx MACH=%08lx MACL=%08lx PR=%08lx T=%08lx\n",
1375 (long) get_frame_register_unsigned (frame
, GBR_C_REGNUM
),
1376 (long) get_frame_register_unsigned (frame
, MACH_C_REGNUM
),
1377 (long) get_frame_register_unsigned (frame
, MACL_C_REGNUM
),
1378 (long) get_frame_register_unsigned (frame
, PR_C_REGNUM
),
1379 (long) get_frame_register_unsigned (frame
, T_C_REGNUM
));
1381 ("FPSCR=%08lx FPUL=%08lx\n",
1382 (long) get_frame_register_unsigned (frame
, FPSCR_C_REGNUM
),
1383 (long) get_frame_register_unsigned (frame
, FPUL_C_REGNUM
));
1385 for (i
= 0; i
< 16; i
= i
+ 4)
1387 ("\nR%d-R%d %08lx %08lx %08lx %08lx\n",
1389 (long) get_frame_register_unsigned (frame
, i
+ 0),
1390 (long) get_frame_register_unsigned (frame
, i
+ 1),
1391 (long) get_frame_register_unsigned (frame
, i
+ 2),
1392 (long) get_frame_register_unsigned (frame
, i
+ 3));
1394 printf_filtered ("\n");
1396 for (i
= 0; i
< 16; i
= i
+ 8)
1398 ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1400 (long) get_frame_register_unsigned
1401 (frame
, gdbarch_fp0_regnum (gdbarch
) + i
+ 0),
1402 (long) get_frame_register_unsigned
1403 (frame
, gdbarch_fp0_regnum (gdbarch
) + i
+ 1),
1404 (long) get_frame_register_unsigned
1405 (frame
, gdbarch_fp0_regnum (gdbarch
) + i
+ 2),
1406 (long) get_frame_register_unsigned
1407 (frame
, gdbarch_fp0_regnum (gdbarch
) + i
+ 3),
1408 (long) get_frame_register_unsigned
1409 (frame
, gdbarch_fp0_regnum (gdbarch
) + i
+ 4),
1410 (long) get_frame_register_unsigned
1411 (frame
, gdbarch_fp0_regnum (gdbarch
) + i
+ 5),
1412 (long) get_frame_register_unsigned
1413 (frame
, gdbarch_fp0_regnum (gdbarch
) + i
+ 6),
1414 (long) get_frame_register_unsigned
1415 (frame
, gdbarch_fp0_regnum (gdbarch
) + i
+ 7));
1418 /* FIXME!!! This only shows the registers for shmedia, excluding the
1419 pseudo registers. */
1421 sh64_show_regs (struct frame_info
*frame
)
1423 if (pc_is_isa32 (get_frame_pc (frame
)))
1424 sh64_show_media_regs (frame
);
1426 sh64_show_compact_regs (frame
);
1431 SH MEDIA MODE (ISA 32)
1432 general registers (64-bit) 0-63
1433 0 r0, r1, r2, r3, r4, r5, r6, r7,
1434 64 r8, r9, r10, r11, r12, r13, r14, r15,
1435 128 r16, r17, r18, r19, r20, r21, r22, r23,
1436 192 r24, r25, r26, r27, r28, r29, r30, r31,
1437 256 r32, r33, r34, r35, r36, r37, r38, r39,
1438 320 r40, r41, r42, r43, r44, r45, r46, r47,
1439 384 r48, r49, r50, r51, r52, r53, r54, r55,
1440 448 r56, r57, r58, r59, r60, r61, r62, r63,
1445 status reg., saved status reg., saved pc reg. (64-bit) 65-67
1448 target registers (64-bit) 68-75
1449 544 tr0, tr1, tr2, tr3, tr4, tr5, tr6, tr7,
1451 floating point state control register (32-bit) 76
1454 single precision floating point registers (32-bit) 77-140
1455 612 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
1456 644 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15,
1457 676 fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23,
1458 708 fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31,
1459 740 fr32, fr33, fr34, fr35, fr36, fr37, fr38, fr39,
1460 772 fr40, fr41, fr42, fr43, fr44, fr45, fr46, fr47,
1461 804 fr48, fr49, fr50, fr51, fr52, fr53, fr54, fr55,
1462 836 fr56, fr57, fr58, fr59, fr60, fr61, fr62, fr63,
1464 TOTAL SPACE FOR REGISTERS: 868 bytes
1466 From here on they are all pseudo registers: no memory allocated.
1467 REGISTER_BYTE returns the register byte for the base register.
1469 double precision registers (pseudo) 141-172
1470 dr0, dr2, dr4, dr6, dr8, dr10, dr12, dr14,
1471 dr16, dr18, dr20, dr22, dr24, dr26, dr28, dr30,
1472 dr32, dr34, dr36, dr38, dr40, dr42, dr44, dr46,
1473 dr48, dr50, dr52, dr54, dr56, dr58, dr60, dr62,
1475 floating point pairs (pseudo) 173-204
1476 fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14,
1477 fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30,
1478 fp32, fp34, fp36, fp38, fp40, fp42, fp44, fp46,
1479 fp48, fp50, fp52, fp54, fp56, fp58, fp60, fp62,
1481 floating point vectors (4 floating point regs) (pseudo) 205-220
1482 fv0, fv4, fv8, fv12, fv16, fv20, fv24, fv28,
1483 fv32, fv36, fv40, fv44, fv48, fv52, fv56, fv60,
1485 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
1486 r0_c, r1_c, r2_c, r3_c, r4_c, r5_c, r6_c, r7_c,
1487 r8_c, r9_c, r10_c, r11_c, r12_c, r13_c, r14_c, r15_c,
1489 gbr_c, mach_c, macl_c, pr_c, t_c,
1491 fr0_c, fr1_c, fr2_c, fr3_c, fr4_c, fr5_c, fr6_c, fr7_c,
1492 fr8_c, fr9_c, fr10_c, fr11_c, fr12_c, fr13_c, fr14_c, fr15_c
1493 dr0_c, dr2_c, dr4_c, dr6_c, dr8_c, dr10_c, dr12_c, dr14_c
1494 fv0_c, fv4_c, fv8_c, fv12_c
1497 static struct type
*
1498 sh64_build_float_register_type (struct gdbarch
*gdbarch
, int high
)
1502 temp
= create_range_type (NULL
, builtin_type_int32
, 0, high
);
1503 return create_array_type (NULL
, builtin_type (gdbarch
)->builtin_float
, temp
);
1506 /* Return the GDB type object for the "standard" data type
1507 of data in register REG_NR. */
1508 static struct type
*
1509 sh64_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
1511 if ((reg_nr
>= gdbarch_fp0_regnum (gdbarch
)
1512 && reg_nr
<= FP_LAST_REGNUM
)
1513 || (reg_nr
>= FP0_C_REGNUM
1514 && reg_nr
<= FP_LAST_C_REGNUM
))
1515 return builtin_type (gdbarch
)->builtin_float
;
1516 else if ((reg_nr
>= DR0_REGNUM
1517 && reg_nr
<= DR_LAST_REGNUM
)
1518 || (reg_nr
>= DR0_C_REGNUM
1519 && reg_nr
<= DR_LAST_C_REGNUM
))
1520 return builtin_type (gdbarch
)->builtin_double
;
1521 else if (reg_nr
>= FPP0_REGNUM
1522 && reg_nr
<= FPP_LAST_REGNUM
)
1523 return sh64_build_float_register_type (gdbarch
, 1);
1524 else if ((reg_nr
>= FV0_REGNUM
1525 && reg_nr
<= FV_LAST_REGNUM
)
1526 ||(reg_nr
>= FV0_C_REGNUM
1527 && reg_nr
<= FV_LAST_C_REGNUM
))
1528 return sh64_build_float_register_type (gdbarch
, 3);
1529 else if (reg_nr
== FPSCR_REGNUM
)
1530 return builtin_type (gdbarch
)->builtin_int
;
1531 else if (reg_nr
>= R0_C_REGNUM
1532 && reg_nr
< FP0_C_REGNUM
)
1533 return builtin_type (gdbarch
)->builtin_int
;
1535 return builtin_type (gdbarch
)->builtin_long_long
;
1539 sh64_register_convert_to_virtual (struct gdbarch
*gdbarch
, int regnum
,
1540 struct type
*type
, char *from
, char *to
)
1542 if (gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_LITTLE
)
1544 /* It is a no-op. */
1545 memcpy (to
, from
, register_size (gdbarch
, regnum
));
1549 if ((regnum
>= DR0_REGNUM
1550 && regnum
<= DR_LAST_REGNUM
)
1551 || (regnum
>= DR0_C_REGNUM
1552 && regnum
<= DR_LAST_C_REGNUM
))
1555 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword
,
1557 store_typed_floating (to
, type
, val
);
1560 error ("sh64_register_convert_to_virtual called with non DR register number");
1564 sh64_register_convert_to_raw (struct gdbarch
*gdbarch
, struct type
*type
,
1565 int regnum
, const void *from
, void *to
)
1567 if (gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_LITTLE
)
1569 /* It is a no-op. */
1570 memcpy (to
, from
, register_size (gdbarch
, regnum
));
1574 if ((regnum
>= DR0_REGNUM
1575 && regnum
<= DR_LAST_REGNUM
)
1576 || (regnum
>= DR0_C_REGNUM
1577 && regnum
<= DR_LAST_C_REGNUM
))
1579 DOUBLEST val
= deprecated_extract_floating (from
, TYPE_LENGTH(type
));
1580 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword
,
1584 error ("sh64_register_convert_to_raw called with non DR register number");
1588 sh64_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1589 int reg_nr
, gdb_byte
*buffer
)
1594 char temp_buffer
[MAX_REGISTER_SIZE
];
1596 if (reg_nr
>= DR0_REGNUM
1597 && reg_nr
<= DR_LAST_REGNUM
)
1599 base_regnum
= sh64_dr_reg_base_num (gdbarch
, reg_nr
);
1601 /* Build the value in the provided buffer. */
1602 /* DR regs are double precision registers obtained by
1603 concatenating 2 single precision floating point registers. */
1604 for (portion
= 0; portion
< 2; portion
++)
1605 regcache_raw_read (regcache
, base_regnum
+ portion
,
1607 + register_size (gdbarch
, base_regnum
) * portion
));
1609 /* We must pay attention to the endianness. */
1610 sh64_register_convert_to_virtual (gdbarch
, reg_nr
,
1611 register_type (gdbarch
, reg_nr
),
1612 temp_buffer
, buffer
);
1616 else if (reg_nr
>= FPP0_REGNUM
1617 && reg_nr
<= FPP_LAST_REGNUM
)
1619 base_regnum
= sh64_fpp_reg_base_num (gdbarch
, reg_nr
);
1621 /* Build the value in the provided buffer. */
1622 /* FPP regs are pairs of single precision registers obtained by
1623 concatenating 2 single precision floating point registers. */
1624 for (portion
= 0; portion
< 2; portion
++)
1625 regcache_raw_read (regcache
, base_regnum
+ portion
,
1627 + register_size (gdbarch
, base_regnum
) * portion
));
1630 else if (reg_nr
>= FV0_REGNUM
1631 && reg_nr
<= FV_LAST_REGNUM
)
1633 base_regnum
= sh64_fv_reg_base_num (gdbarch
, reg_nr
);
1635 /* Build the value in the provided buffer. */
1636 /* FV regs are vectors of single precision registers obtained by
1637 concatenating 4 single precision floating point registers. */
1638 for (portion
= 0; portion
< 4; portion
++)
1639 regcache_raw_read (regcache
, base_regnum
+ portion
,
1641 + register_size (gdbarch
, base_regnum
) * portion
));
1644 /* sh compact pseudo registers. 1-to-1 with a shmedia register */
1645 else if (reg_nr
>= R0_C_REGNUM
1646 && reg_nr
<= T_C_REGNUM
)
1648 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1650 /* Build the value in the provided buffer. */
1651 regcache_raw_read (regcache
, base_regnum
, temp_buffer
);
1652 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1654 memcpy (buffer
, temp_buffer
+ offset
, 4); /* get LOWER 32 bits only????*/
1657 else if (reg_nr
>= FP0_C_REGNUM
1658 && reg_nr
<= FP_LAST_C_REGNUM
)
1660 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1662 /* Build the value in the provided buffer. */
1663 /* Floating point registers map 1-1 to the media fp regs,
1664 they have the same size and endianness. */
1665 regcache_raw_read (regcache
, base_regnum
, buffer
);
1668 else if (reg_nr
>= DR0_C_REGNUM
1669 && reg_nr
<= DR_LAST_C_REGNUM
)
1671 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1673 /* DR_C regs are double precision registers obtained by
1674 concatenating 2 single precision floating point registers. */
1675 for (portion
= 0; portion
< 2; portion
++)
1676 regcache_raw_read (regcache
, base_regnum
+ portion
,
1678 + register_size (gdbarch
, base_regnum
) * portion
));
1680 /* We must pay attention to the endianness. */
1681 sh64_register_convert_to_virtual (gdbarch
, reg_nr
,
1682 register_type (gdbarch
, reg_nr
),
1683 temp_buffer
, buffer
);
1686 else if (reg_nr
>= FV0_C_REGNUM
1687 && reg_nr
<= FV_LAST_C_REGNUM
)
1689 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1691 /* Build the value in the provided buffer. */
1692 /* FV_C regs are vectors of single precision registers obtained by
1693 concatenating 4 single precision floating point registers. */
1694 for (portion
= 0; portion
< 4; portion
++)
1695 regcache_raw_read (regcache
, base_regnum
+ portion
,
1697 + register_size (gdbarch
, base_regnum
) * portion
));
1700 else if (reg_nr
== FPSCR_C_REGNUM
)
1702 int fpscr_base_regnum
;
1704 unsigned int fpscr_value
;
1705 unsigned int sr_value
;
1706 unsigned int fpscr_c_value
;
1707 unsigned int fpscr_c_part1_value
;
1708 unsigned int fpscr_c_part2_value
;
1710 fpscr_base_regnum
= FPSCR_REGNUM
;
1711 sr_base_regnum
= SR_REGNUM
;
1713 /* Build the value in the provided buffer. */
1714 /* FPSCR_C is a very weird register that contains sparse bits
1715 from the FPSCR and the SR architectural registers.
1722 2-17 Bit 2-18 of FPSCR
1723 18-20 Bits 12,13,14 of SR
1727 /* Get FPSCR into a local buffer */
1728 regcache_raw_read (regcache
, fpscr_base_regnum
, temp_buffer
);
1729 /* Get value as an int. */
1730 fpscr_value
= extract_unsigned_integer (temp_buffer
, 4);
1731 /* Get SR into a local buffer */
1732 regcache_raw_read (regcache
, sr_base_regnum
, temp_buffer
);
1733 /* Get value as an int. */
1734 sr_value
= extract_unsigned_integer (temp_buffer
, 4);
1735 /* Build the new value. */
1736 fpscr_c_part1_value
= fpscr_value
& 0x3fffd;
1737 fpscr_c_part2_value
= (sr_value
& 0x7000) << 6;
1738 fpscr_c_value
= fpscr_c_part1_value
| fpscr_c_part2_value
;
1739 /* Store that in out buffer!!! */
1740 store_unsigned_integer (buffer
, 4, fpscr_c_value
);
1741 /* FIXME There is surely an endianness gotcha here. */
1744 else if (reg_nr
== FPUL_C_REGNUM
)
1746 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1748 /* FPUL_C register is floating point register 32,
1749 same size, same endianness. */
1750 regcache_raw_read (regcache
, base_regnum
, buffer
);
1755 sh64_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1756 int reg_nr
, const gdb_byte
*buffer
)
1758 int base_regnum
, portion
;
1760 char temp_buffer
[MAX_REGISTER_SIZE
];
1762 if (reg_nr
>= DR0_REGNUM
1763 && reg_nr
<= DR_LAST_REGNUM
)
1765 base_regnum
= sh64_dr_reg_base_num (gdbarch
, reg_nr
);
1766 /* We must pay attention to the endianness. */
1767 sh64_register_convert_to_raw (gdbarch
, register_type (gdbarch
, reg_nr
),
1769 buffer
, temp_buffer
);
1771 /* Write the real regs for which this one is an alias. */
1772 for (portion
= 0; portion
< 2; portion
++)
1773 regcache_raw_write (regcache
, base_regnum
+ portion
,
1775 + register_size (gdbarch
,
1776 base_regnum
) * portion
));
1779 else if (reg_nr
>= FPP0_REGNUM
1780 && reg_nr
<= FPP_LAST_REGNUM
)
1782 base_regnum
= sh64_fpp_reg_base_num (gdbarch
, reg_nr
);
1784 /* Write the real regs for which this one is an alias. */
1785 for (portion
= 0; portion
< 2; portion
++)
1786 regcache_raw_write (regcache
, base_regnum
+ portion
,
1788 + register_size (gdbarch
,
1789 base_regnum
) * portion
));
1792 else if (reg_nr
>= FV0_REGNUM
1793 && reg_nr
<= FV_LAST_REGNUM
)
1795 base_regnum
= sh64_fv_reg_base_num (gdbarch
, reg_nr
);
1797 /* Write the real regs for which this one is an alias. */
1798 for (portion
= 0; portion
< 4; portion
++)
1799 regcache_raw_write (regcache
, base_regnum
+ portion
,
1801 + register_size (gdbarch
,
1802 base_regnum
) * portion
));
1805 /* sh compact general pseudo registers. 1-to-1 with a shmedia
1806 register but only 4 bytes of it. */
1807 else if (reg_nr
>= R0_C_REGNUM
1808 && reg_nr
<= T_C_REGNUM
)
1810 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1811 /* reg_nr is 32 bit here, and base_regnum is 64 bits. */
1812 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1816 /* Let's read the value of the base register into a temporary
1817 buffer, so that overwriting the last four bytes with the new
1818 value of the pseudo will leave the upper 4 bytes unchanged. */
1819 regcache_raw_read (regcache
, base_regnum
, temp_buffer
);
1820 /* Write as an 8 byte quantity */
1821 memcpy (temp_buffer
+ offset
, buffer
, 4);
1822 regcache_raw_write (regcache
, base_regnum
, temp_buffer
);
1825 /* sh floating point compact pseudo registers. 1-to-1 with a shmedia
1826 registers. Both are 4 bytes. */
1827 else if (reg_nr
>= FP0_C_REGNUM
1828 && reg_nr
<= FP_LAST_C_REGNUM
)
1830 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1831 regcache_raw_write (regcache
, base_regnum
, buffer
);
1834 else if (reg_nr
>= DR0_C_REGNUM
1835 && reg_nr
<= DR_LAST_C_REGNUM
)
1837 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1838 for (portion
= 0; portion
< 2; portion
++)
1840 /* We must pay attention to the endianness. */
1841 sh64_register_convert_to_raw (gdbarch
,
1842 register_type (gdbarch
, reg_nr
),
1844 buffer
, temp_buffer
);
1846 regcache_raw_write (regcache
, base_regnum
+ portion
,
1848 + register_size (gdbarch
,
1849 base_regnum
) * portion
));
1853 else if (reg_nr
>= FV0_C_REGNUM
1854 && reg_nr
<= FV_LAST_C_REGNUM
)
1856 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1858 for (portion
= 0; portion
< 4; portion
++)
1860 regcache_raw_write (regcache
, base_regnum
+ portion
,
1862 + register_size (gdbarch
,
1863 base_regnum
) * portion
));
1867 else if (reg_nr
== FPSCR_C_REGNUM
)
1869 int fpscr_base_regnum
;
1871 unsigned int fpscr_value
;
1872 unsigned int sr_value
;
1873 unsigned int old_fpscr_value
;
1874 unsigned int old_sr_value
;
1875 unsigned int fpscr_c_value
;
1876 unsigned int fpscr_mask
;
1877 unsigned int sr_mask
;
1879 fpscr_base_regnum
= FPSCR_REGNUM
;
1880 sr_base_regnum
= SR_REGNUM
;
1882 /* FPSCR_C is a very weird register that contains sparse bits
1883 from the FPSCR and the SR architectural registers.
1890 2-17 Bit 2-18 of FPSCR
1891 18-20 Bits 12,13,14 of SR
1895 /* Get value as an int. */
1896 fpscr_c_value
= extract_unsigned_integer (buffer
, 4);
1898 /* Build the new values. */
1899 fpscr_mask
= 0x0003fffd;
1900 sr_mask
= 0x001c0000;
1902 fpscr_value
= fpscr_c_value
& fpscr_mask
;
1903 sr_value
= (fpscr_value
& sr_mask
) >> 6;
1905 regcache_raw_read (regcache
, fpscr_base_regnum
, temp_buffer
);
1906 old_fpscr_value
= extract_unsigned_integer (temp_buffer
, 4);
1907 old_fpscr_value
&= 0xfffc0002;
1908 fpscr_value
|= old_fpscr_value
;
1909 store_unsigned_integer (temp_buffer
, 4, fpscr_value
);
1910 regcache_raw_write (regcache
, fpscr_base_regnum
, temp_buffer
);
1912 regcache_raw_read (regcache
, sr_base_regnum
, temp_buffer
);
1913 old_sr_value
= extract_unsigned_integer (temp_buffer
, 4);
1914 old_sr_value
&= 0xffff8fff;
1915 sr_value
|= old_sr_value
;
1916 store_unsigned_integer (temp_buffer
, 4, sr_value
);
1917 regcache_raw_write (regcache
, sr_base_regnum
, temp_buffer
);
1920 else if (reg_nr
== FPUL_C_REGNUM
)
1922 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1923 regcache_raw_write (regcache
, base_regnum
, buffer
);
1927 /* FIXME:!! THIS SHOULD TAKE CARE OF GETTING THE RIGHT PORTION OF THE
1928 shmedia REGISTERS. */
1929 /* Control registers, compact mode. */
1931 sh64_do_cr_c_register_info (struct ui_file
*file
, struct frame_info
*frame
,
1934 switch (cr_c_regnum
)
1937 fprintf_filtered (file
, "pc_c\t0x%08x\n",
1938 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1941 fprintf_filtered (file
, "gbr_c\t0x%08x\n",
1942 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1945 fprintf_filtered (file
, "mach_c\t0x%08x\n",
1946 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1949 fprintf_filtered (file
, "macl_c\t0x%08x\n",
1950 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1953 fprintf_filtered (file
, "pr_c\t0x%08x\n",
1954 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1957 fprintf_filtered (file
, "t_c\t0x%08x\n",
1958 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1960 case FPSCR_C_REGNUM
:
1961 fprintf_filtered (file
, "fpscr_c\t0x%08x\n",
1962 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1965 fprintf_filtered (file
, "fpul_c\t0x%08x\n",
1966 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1972 sh64_do_fp_register (struct gdbarch
*gdbarch
, struct ui_file
*file
,
1973 struct frame_info
*frame
, int regnum
)
1974 { /* do values for FP (float) regs */
1975 unsigned char *raw_buffer
;
1976 double flt
; /* double extracted from raw hex data */
1980 /* Allocate space for the float. */
1981 raw_buffer
= (unsigned char *) alloca
1982 (register_size (gdbarch
,
1986 /* Get the data in raw format. */
1987 if (!frame_register_read (frame
, regnum
, raw_buffer
))
1988 error ("can't read register %d (%s)",
1989 regnum
, gdbarch_register_name (gdbarch
, regnum
));
1991 /* Get the register as a number */
1992 flt
= unpack_double (builtin_type (gdbarch
)->builtin_float
, raw_buffer
, &inv
);
1994 /* Print the name and some spaces. */
1995 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
1996 print_spaces_filtered (15 - strlen (gdbarch_register_name
1997 (gdbarch
, regnum
)), file
);
1999 /* Print the value. */
2001 fprintf_filtered (file
, "<invalid float>");
2003 fprintf_filtered (file
, "%-10.9g", flt
);
2005 /* Print the fp register as hex. */
2006 fprintf_filtered (file
, "\t(raw 0x");
2007 for (j
= 0; j
< register_size (gdbarch
, regnum
); j
++)
2009 int idx
= gdbarch_byte_order (gdbarch
)
2010 == BFD_ENDIAN_BIG
? j
: register_size
2011 (gdbarch
, regnum
) - 1 - j
;
2012 fprintf_filtered (file
, "%02x", raw_buffer
[idx
]);
2014 fprintf_filtered (file
, ")");
2015 fprintf_filtered (file
, "\n");
2019 sh64_do_pseudo_register (struct gdbarch
*gdbarch
, struct ui_file
*file
,
2020 struct frame_info
*frame
, int regnum
)
2022 /* All the sh64-compact mode registers are pseudo registers. */
2024 if (regnum
< gdbarch_num_regs (gdbarch
)
2025 || regnum
>= gdbarch_num_regs (gdbarch
)
2026 + NUM_PSEUDO_REGS_SH_MEDIA
2027 + NUM_PSEUDO_REGS_SH_COMPACT
)
2028 internal_error (__FILE__
, __LINE__
,
2029 _("Invalid pseudo register number %d\n"), regnum
);
2031 else if ((regnum
>= DR0_REGNUM
&& regnum
<= DR_LAST_REGNUM
))
2033 int fp_regnum
= sh64_dr_reg_base_num (gdbarch
, regnum
);
2034 fprintf_filtered (file
, "dr%d\t0x%08x%08x\n", regnum
- DR0_REGNUM
,
2035 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
),
2036 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 1));
2039 else if ((regnum
>= DR0_C_REGNUM
&& regnum
<= DR_LAST_C_REGNUM
))
2041 int fp_regnum
= sh64_compact_reg_base_num (gdbarch
, regnum
);
2042 fprintf_filtered (file
, "dr%d_c\t0x%08x%08x\n", regnum
- DR0_C_REGNUM
,
2043 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
),
2044 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 1));
2047 else if ((regnum
>= FV0_REGNUM
&& regnum
<= FV_LAST_REGNUM
))
2049 int fp_regnum
= sh64_fv_reg_base_num (gdbarch
, regnum
);
2050 fprintf_filtered (file
, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
2051 regnum
- FV0_REGNUM
,
2052 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
),
2053 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 1),
2054 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 2),
2055 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 3));
2058 else if ((regnum
>= FV0_C_REGNUM
&& regnum
<= FV_LAST_C_REGNUM
))
2060 int fp_regnum
= sh64_compact_reg_base_num (gdbarch
, regnum
);
2061 fprintf_filtered (file
, "fv%d_c\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
2062 regnum
- FV0_C_REGNUM
,
2063 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
),
2064 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 1),
2065 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 2),
2066 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 3));
2069 else if (regnum
>= FPP0_REGNUM
&& regnum
<= FPP_LAST_REGNUM
)
2071 int fp_regnum
= sh64_fpp_reg_base_num (gdbarch
, regnum
);
2072 fprintf_filtered (file
, "fpp%d\t0x%08x\t0x%08x\n", regnum
- FPP0_REGNUM
,
2073 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
),
2074 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 1));
2077 else if (regnum
>= R0_C_REGNUM
&& regnum
<= R_LAST_C_REGNUM
)
2079 int c_regnum
= sh64_compact_reg_base_num (gdbarch
, regnum
);
2080 fprintf_filtered (file
, "r%d_c\t0x%08x\n", regnum
- R0_C_REGNUM
,
2081 (unsigned) get_frame_register_unsigned (frame
, c_regnum
));
2083 else if (regnum
>= FP0_C_REGNUM
&& regnum
<= FP_LAST_C_REGNUM
)
2084 /* This should work also for pseudoregs. */
2085 sh64_do_fp_register (gdbarch
, file
, frame
, regnum
);
2086 else if (regnum
>= PC_C_REGNUM
&& regnum
<= FPUL_C_REGNUM
)
2087 sh64_do_cr_c_register_info (file
, frame
, regnum
);
2091 sh64_do_register (struct gdbarch
*gdbarch
, struct ui_file
*file
,
2092 struct frame_info
*frame
, int regnum
)
2094 unsigned char raw_buffer
[MAX_REGISTER_SIZE
];
2096 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
2097 print_spaces_filtered (15 - strlen (gdbarch_register_name
2098 (gdbarch
, regnum
)), file
);
2100 /* Get the data in raw format. */
2101 if (!frame_register_read (frame
, regnum
, raw_buffer
))
2102 fprintf_filtered (file
, "*value not available*\n");
2104 val_print (register_type (gdbarch
, regnum
), raw_buffer
, 0, 0,
2105 file
, 'x', 1, 0, Val_pretty_default
, current_language
);
2106 fprintf_filtered (file
, "\t");
2107 val_print (register_type (gdbarch
, regnum
), raw_buffer
, 0, 0,
2108 file
, 0, 1, 0, Val_pretty_default
, current_language
);
2109 fprintf_filtered (file
, "\n");
2113 sh64_print_register (struct gdbarch
*gdbarch
, struct ui_file
*file
,
2114 struct frame_info
*frame
, int regnum
)
2116 if (regnum
< 0 || regnum
>= gdbarch_num_regs (gdbarch
)
2117 + gdbarch_num_pseudo_regs (gdbarch
))
2118 internal_error (__FILE__
, __LINE__
,
2119 _("Invalid register number %d\n"), regnum
);
2121 else if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
))
2123 if (TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
2124 sh64_do_fp_register (gdbarch
, file
, frame
, regnum
); /* FP regs */
2126 sh64_do_register (gdbarch
, file
, frame
, regnum
);
2129 else if (regnum
< gdbarch_num_regs (gdbarch
)
2130 + gdbarch_num_pseudo_regs (gdbarch
))
2131 sh64_do_pseudo_register (gdbarch
, file
, frame
, regnum
);
2135 sh64_media_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
2136 struct frame_info
*frame
, int regnum
,
2139 if (regnum
!= -1) /* do one specified register */
2141 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
2142 error ("Not a valid register for the current processor type");
2144 sh64_print_register (gdbarch
, file
, frame
, regnum
);
2147 /* do all (or most) registers */
2150 while (regnum
< gdbarch_num_regs (gdbarch
))
2152 /* If the register name is empty, it is undefined for this
2153 processor, so don't display anything. */
2154 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
2155 || *(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
2161 if (TYPE_CODE (register_type (gdbarch
, regnum
))
2166 /* true for "INFO ALL-REGISTERS" command */
2167 sh64_do_fp_register (gdbarch
, file
, frame
, regnum
);
2171 regnum
+= FP_LAST_REGNUM
- gdbarch_fp0_regnum (gdbarch
);
2176 sh64_do_register (gdbarch
, file
, frame
, regnum
);
2182 while (regnum
< gdbarch_num_regs (gdbarch
)
2183 + gdbarch_num_pseudo_regs (gdbarch
))
2185 sh64_do_pseudo_register (gdbarch
, file
, frame
, regnum
);
2192 sh64_compact_print_registers_info (struct gdbarch
*gdbarch
,
2193 struct ui_file
*file
,
2194 struct frame_info
*frame
, int regnum
,
2197 if (regnum
!= -1) /* do one specified register */
2199 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
2200 error ("Not a valid register for the current processor type");
2202 if (regnum
>= 0 && regnum
< R0_C_REGNUM
)
2203 error ("Not a valid register for the current processor mode.");
2205 sh64_print_register (gdbarch
, file
, frame
, regnum
);
2208 /* do all compact registers */
2210 regnum
= R0_C_REGNUM
;
2211 while (regnum
< gdbarch_num_regs (gdbarch
)
2212 + gdbarch_num_pseudo_regs (gdbarch
))
2214 sh64_do_pseudo_register (gdbarch
, file
, frame
, regnum
);
2221 sh64_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
2222 struct frame_info
*frame
, int regnum
, int fpregs
)
2224 if (pc_is_isa32 (get_frame_pc (frame
)))
2225 sh64_media_print_registers_info (gdbarch
, file
, frame
, regnum
, fpregs
);
2227 sh64_compact_print_registers_info (gdbarch
, file
, frame
, regnum
, fpregs
);
2230 static struct sh64_frame_cache
*
2231 sh64_alloc_frame_cache (void)
2233 struct sh64_frame_cache
*cache
;
2236 cache
= FRAME_OBSTACK_ZALLOC (struct sh64_frame_cache
);
2240 cache
->saved_sp
= 0;
2241 cache
->sp_offset
= 0;
2244 /* Frameless until proven otherwise. */
2247 /* Saved registers. We initialize these to -1 since zero is a valid
2248 offset (that's where fp is supposed to be stored). */
2249 for (i
= 0; i
< SIM_SH64_NR_REGS
; i
++)
2251 cache
->saved_regs
[i
] = -1;
2257 static struct sh64_frame_cache
*
2258 sh64_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2260 struct gdbarch
*gdbarch
;
2261 struct sh64_frame_cache
*cache
;
2262 CORE_ADDR current_pc
;
2268 gdbarch
= get_frame_arch (this_frame
);
2269 cache
= sh64_alloc_frame_cache ();
2270 *this_cache
= cache
;
2272 current_pc
= get_frame_pc (this_frame
);
2273 cache
->media_mode
= pc_is_isa32 (current_pc
);
2275 /* In principle, for normal frames, fp holds the frame pointer,
2276 which holds the base address for the current stack frame.
2277 However, for functions that don't need it, the frame pointer is
2278 optional. For these "frameless" functions the frame pointer is
2279 actually the frame pointer of the calling frame. */
2280 cache
->base
= get_frame_register_unsigned (this_frame
, MEDIA_FP_REGNUM
);
2281 if (cache
->base
== 0)
2284 cache
->pc
= get_frame_func (this_frame
);
2286 sh64_analyze_prologue (gdbarch
, cache
, cache
->pc
, current_pc
);
2288 if (!cache
->uses_fp
)
2290 /* We didn't find a valid frame, which means that CACHE->base
2291 currently holds the frame pointer for our calling frame. If
2292 we're at the start of a function, or somewhere half-way its
2293 prologue, the function's frame probably hasn't been fully
2294 setup yet. Try to reconstruct the base address for the stack
2295 frame by looking at the stack pointer. For truly "frameless"
2296 functions this might work too. */
2297 cache
->base
= get_frame_register_unsigned
2298 (this_frame
, gdbarch_sp_regnum (gdbarch
));
2301 /* Now that we have the base address for the stack frame we can
2302 calculate the value of sp in the calling frame. */
2303 cache
->saved_sp
= cache
->base
+ cache
->sp_offset
;
2305 /* Adjust all the saved registers such that they contain addresses
2306 instead of offsets. */
2307 for (i
= 0; i
< SIM_SH64_NR_REGS
; i
++)
2308 if (cache
->saved_regs
[i
] != -1)
2309 cache
->saved_regs
[i
] = cache
->saved_sp
- cache
->saved_regs
[i
];
2314 static struct value
*
2315 sh64_frame_prev_register (struct frame_info
*this_frame
,
2316 void **this_cache
, int regnum
)
2318 struct sh64_frame_cache
*cache
= sh64_frame_cache (this_frame
, this_cache
);
2319 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2321 gdb_assert (regnum
>= 0);
2323 if (regnum
== gdbarch_sp_regnum (gdbarch
) && cache
->saved_sp
)
2324 frame_unwind_got_constant (this_frame
, regnum
, cache
->saved_sp
);
2326 /* The PC of the previous frame is stored in the PR register of
2327 the current frame. Frob regnum so that we pull the value from
2328 the correct place. */
2329 if (regnum
== gdbarch_pc_regnum (gdbarch
))
2332 if (regnum
< SIM_SH64_NR_REGS
&& cache
->saved_regs
[regnum
] != -1)
2334 if (gdbarch_tdep (gdbarch
)->sh_abi
== SH_ABI_32
2335 && (regnum
== MEDIA_FP_REGNUM
|| regnum
== PR_REGNUM
))
2338 val
= read_memory_unsigned_integer (cache
->saved_regs
[regnum
], 4);
2339 return frame_unwind_got_constant (this_frame
, regnum
, val
);
2342 return frame_unwind_got_memory (this_frame
, regnum
,
2343 cache
->saved_regs
[regnum
]);
2346 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
2350 sh64_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2351 struct frame_id
*this_id
)
2353 struct sh64_frame_cache
*cache
= sh64_frame_cache (this_frame
, this_cache
);
2355 /* This marks the outermost frame. */
2356 if (cache
->base
== 0)
2359 *this_id
= frame_id_build (cache
->saved_sp
, cache
->pc
);
2362 static const struct frame_unwind sh64_frame_unwind
= {
2365 sh64_frame_prev_register
,
2367 default_frame_sniffer
2371 sh64_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2373 return frame_unwind_register_unsigned (next_frame
,
2374 gdbarch_sp_regnum (gdbarch
));
2378 sh64_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2380 return frame_unwind_register_unsigned (next_frame
,
2381 gdbarch_pc_regnum (gdbarch
));
2384 static struct frame_id
2385 sh64_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2387 CORE_ADDR sp
= get_frame_register_unsigned (this_frame
,
2388 gdbarch_sp_regnum (gdbarch
));
2389 return frame_id_build (sp
, get_frame_pc (this_frame
));
2393 sh64_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2395 struct sh64_frame_cache
*cache
= sh64_frame_cache (this_frame
, this_cache
);
2400 static const struct frame_base sh64_frame_base
= {
2402 sh64_frame_base_address
,
2403 sh64_frame_base_address
,
2404 sh64_frame_base_address
2409 sh64_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2411 struct gdbarch
*gdbarch
;
2412 struct gdbarch_tdep
*tdep
;
2414 /* If there is already a candidate, use it. */
2415 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2417 return arches
->gdbarch
;
2419 /* None found, create a new architecture from the information
2421 tdep
= XMALLOC (struct gdbarch_tdep
);
2422 gdbarch
= gdbarch_alloc (&info
, tdep
);
2424 /* Determine the ABI */
2425 if (info
.abfd
&& bfd_get_arch_size (info
.abfd
) == 64)
2427 /* If the ABI is the 64-bit one, it can only be sh-media. */
2428 tdep
->sh_abi
= SH_ABI_64
;
2429 set_gdbarch_ptr_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2430 set_gdbarch_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2434 /* If the ABI is the 32-bit one it could be either media or
2436 tdep
->sh_abi
= SH_ABI_32
;
2437 set_gdbarch_ptr_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2438 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2441 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
2442 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2443 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2444 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2445 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2446 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2447 set_gdbarch_long_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2449 /* The number of real registers is the same whether we are in
2450 ISA16(compact) or ISA32(media). */
2451 set_gdbarch_num_regs (gdbarch
, SIM_SH64_NR_REGS
);
2452 set_gdbarch_sp_regnum (gdbarch
, 15);
2453 set_gdbarch_pc_regnum (gdbarch
, 64);
2454 set_gdbarch_fp0_regnum (gdbarch
, SIM_SH64_FR0_REGNUM
);
2455 set_gdbarch_num_pseudo_regs (gdbarch
, NUM_PSEUDO_REGS_SH_MEDIA
2456 + NUM_PSEUDO_REGS_SH_COMPACT
);
2458 set_gdbarch_register_name (gdbarch
, sh64_register_name
);
2459 set_gdbarch_register_type (gdbarch
, sh64_register_type
);
2461 set_gdbarch_pseudo_register_read (gdbarch
, sh64_pseudo_register_read
);
2462 set_gdbarch_pseudo_register_write (gdbarch
, sh64_pseudo_register_write
);
2464 set_gdbarch_breakpoint_from_pc (gdbarch
, sh64_breakpoint_from_pc
);
2466 set_gdbarch_print_insn (gdbarch
, print_insn_sh
);
2467 set_gdbarch_register_sim_regno (gdbarch
, legacy_register_sim_regno
);
2469 set_gdbarch_return_value (gdbarch
, sh64_return_value
);
2471 set_gdbarch_skip_prologue (gdbarch
, sh64_skip_prologue
);
2472 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2474 set_gdbarch_push_dummy_call (gdbarch
, sh64_push_dummy_call
);
2476 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
2478 set_gdbarch_frame_align (gdbarch
, sh64_frame_align
);
2479 set_gdbarch_unwind_sp (gdbarch
, sh64_unwind_sp
);
2480 set_gdbarch_unwind_pc (gdbarch
, sh64_unwind_pc
);
2481 set_gdbarch_dummy_id (gdbarch
, sh64_dummy_id
);
2482 frame_base_set_default (gdbarch
, &sh64_frame_base
);
2484 set_gdbarch_print_registers_info (gdbarch
, sh64_print_registers_info
);
2486 set_gdbarch_elf_make_msymbol_special (gdbarch
,
2487 sh64_elf_make_msymbol_special
);
2489 /* Hook in ABI-specific overrides, if they have been registered. */
2490 gdbarch_init_osabi (info
, gdbarch
);
2492 dwarf2_append_unwinders (gdbarch
);
2493 frame_unwind_append_unwinder (gdbarch
, &sh64_frame_unwind
);