1 /* Target-dependent code for Renesas Super-H, for GDB.
3 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
4 2003, 2004, 2005, 2007, 2008, 2009, 2010, 2011
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 /* Contributed by Steve Chamberlain
27 #include "frame-base.h"
28 #include "frame-unwind.h"
29 #include "dwarf2-frame.h"
37 #include "gdb_string.h"
38 #include "gdb_assert.h"
39 #include "arch-utils.h"
48 /* Register numbers shared with the simulator. */
49 #include "gdb/sim-sh.h"
52 /* Information that is dependent on the processor variant. */
65 struct sh64_frame_cache
72 /* Flag showing that a frame has been created in the prologue code. */
77 /* Saved registers. */
78 CORE_ADDR saved_regs
[SIM_SH64_NR_REGS
];
82 /* Registers of SH5 */
86 DEFAULT_RETURN_REGNUM
= 2,
87 STRUCT_RETURN_REGNUM
= 2,
90 FLOAT_ARGLAST_REGNUM
= 11,
96 /* FPP stands for Floating Point Pair, to avoid confusion with
97 GDB's gdbarch_fp0_regnum, which is the number of the first Floating
98 point register. Unfortunately on the sh5, the floating point
99 registers are called FR, and the floating point pairs are called FP. */
101 FPP_LAST_REGNUM
= 204,
103 FV_LAST_REGNUM
= 220,
105 R_LAST_C_REGNUM
= 236,
112 FPSCR_C_REGNUM
= 243,
115 FP_LAST_C_REGNUM
= 260,
117 DR_LAST_C_REGNUM
= 268,
119 FV_LAST_C_REGNUM
= 272,
120 FPSCR_REGNUM
= SIM_SH64_FPCSR_REGNUM
,
121 SSR_REGNUM
= SIM_SH64_SSR_REGNUM
,
122 SPC_REGNUM
= SIM_SH64_SPC_REGNUM
,
123 TR7_REGNUM
= SIM_SH64_TR0_REGNUM
+ 7,
124 FP_LAST_REGNUM
= SIM_SH64_FR0_REGNUM
+ SIM_SH64_NR_FP_REGS
- 1
128 sh64_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
130 static char *register_names
[] =
132 /* SH MEDIA MODE (ISA 32) */
133 /* general registers (64-bit) 0-63 */
134 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
135 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
136 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
137 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
138 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
139 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
140 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
141 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
146 /* status reg., saved status reg., saved pc reg. (64-bit) 65-67 */
149 /* target registers (64-bit) 68-75 */
150 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7",
152 /* floating point state control register (32-bit) 76 */
155 /* single precision floating point registers (32-bit) 77-140 */
156 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
157 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
158 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
159 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31",
160 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39",
161 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47",
162 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55",
163 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63",
165 /* double precision registers (pseudo) 141-172 */
166 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
167 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30",
168 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46",
169 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62",
171 /* floating point pairs (pseudo) 173-204 */
172 "fp0", "fp2", "fp4", "fp6", "fp8", "fp10", "fp12", "fp14",
173 "fp16", "fp18", "fp20", "fp22", "fp24", "fp26", "fp28", "fp30",
174 "fp32", "fp34", "fp36", "fp38", "fp40", "fp42", "fp44", "fp46",
175 "fp48", "fp50", "fp52", "fp54", "fp56", "fp58", "fp60", "fp62",
177 /* floating point vectors (4 floating point regs) (pseudo) 205-220 */
178 "fv0", "fv4", "fv8", "fv12", "fv16", "fv20", "fv24", "fv28",
179 "fv32", "fv36", "fv40", "fv44", "fv48", "fv52", "fv56", "fv60",
181 /* SH COMPACT MODE (ISA 16) (all pseudo) 221-272 */
182 "r0_c", "r1_c", "r2_c", "r3_c", "r4_c", "r5_c", "r6_c", "r7_c",
183 "r8_c", "r9_c", "r10_c", "r11_c", "r12_c", "r13_c", "r14_c", "r15_c",
185 "gbr_c", "mach_c", "macl_c", "pr_c", "t_c",
187 "fr0_c", "fr1_c", "fr2_c", "fr3_c",
188 "fr4_c", "fr5_c", "fr6_c", "fr7_c",
189 "fr8_c", "fr9_c", "fr10_c", "fr11_c",
190 "fr12_c", "fr13_c", "fr14_c", "fr15_c",
191 "dr0_c", "dr2_c", "dr4_c", "dr6_c",
192 "dr8_c", "dr10_c", "dr12_c", "dr14_c",
193 "fv0_c", "fv4_c", "fv8_c", "fv12_c",
194 /* FIXME!!!! XF0 XF15, XD0 XD14 ????? */
199 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
201 return register_names
[reg_nr
];
204 #define NUM_PSEUDO_REGS_SH_MEDIA 80
205 #define NUM_PSEUDO_REGS_SH_COMPACT 51
207 /* Macros and functions for setting and testing a bit in a minimal
208 symbol that marks it as 32-bit function. The MSB of the minimal
209 symbol's "info" field is used for this purpose.
211 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
212 i.e. refers to a 32-bit function, and sets a "special" bit in a
213 minimal symbol to mark it as a 32-bit function
214 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
216 #define MSYMBOL_IS_SPECIAL(msym) \
217 MSYMBOL_TARGET_FLAG_1 (msym)
220 sh64_elf_make_msymbol_special (asymbol
*sym
, struct minimal_symbol
*msym
)
225 if (((elf_symbol_type
*)(sym
))->internal_elf_sym
.st_other
== STO_SH5_ISA32
)
227 MSYMBOL_TARGET_FLAG_1 (msym
) = 1;
228 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
232 /* ISA32 (shmedia) function addresses are odd (bit 0 is set). Here
233 are some macros to test, set, or clear bit 0 of addresses. */
234 #define IS_ISA32_ADDR(addr) ((addr) & 1)
235 #define MAKE_ISA32_ADDR(addr) ((addr) | 1)
236 #define UNMAKE_ISA32_ADDR(addr) ((addr) & ~1)
239 pc_is_isa32 (bfd_vma memaddr
)
241 struct minimal_symbol
*sym
;
243 /* If bit 0 of the address is set, assume this is a
244 ISA32 (shmedia) address. */
245 if (IS_ISA32_ADDR (memaddr
))
248 /* A flag indicating that this is a ISA32 function is stored by elfread.c in
249 the high bit of the info field. Use this to decide if the function is
251 sym
= lookup_minimal_symbol_by_pc (memaddr
);
253 return MSYMBOL_IS_SPECIAL (sym
);
258 static const unsigned char *
259 sh64_breakpoint_from_pc (struct gdbarch
*gdbarch
,
260 CORE_ADDR
*pcptr
, int *lenptr
)
262 /* The BRK instruction for shmedia is
263 01101111 11110101 11111111 11110000
264 which translates in big endian mode to 0x6f, 0xf5, 0xff, 0xf0
265 and in little endian mode to 0xf0, 0xff, 0xf5, 0x6f */
267 /* The BRK instruction for shcompact is
269 which translates in big endian mode to 0x0, 0x3b
270 and in little endian mode to 0x3b, 0x0 */
272 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
274 if (pc_is_isa32 (*pcptr
))
276 static unsigned char big_breakpoint_media
[] = {
277 0x6f, 0xf5, 0xff, 0xf0
279 *pcptr
= UNMAKE_ISA32_ADDR (*pcptr
);
280 *lenptr
= sizeof (big_breakpoint_media
);
281 return big_breakpoint_media
;
285 static unsigned char big_breakpoint_compact
[] = {0x0, 0x3b};
286 *lenptr
= sizeof (big_breakpoint_compact
);
287 return big_breakpoint_compact
;
292 if (pc_is_isa32 (*pcptr
))
294 static unsigned char little_breakpoint_media
[] = {
295 0xf0, 0xff, 0xf5, 0x6f
297 *pcptr
= UNMAKE_ISA32_ADDR (*pcptr
);
298 *lenptr
= sizeof (little_breakpoint_media
);
299 return little_breakpoint_media
;
303 static unsigned char little_breakpoint_compact
[] = {0x3b, 0x0};
304 *lenptr
= sizeof (little_breakpoint_compact
);
305 return little_breakpoint_compact
;
310 /* Prologue looks like
311 [mov.l <regs>,@-r15]...
316 Actually it can be more complicated than this. For instance, with
334 /* PTABS/L Rn, TRa 0110101111110001nnnnnnl00aaa0000
335 with l=1 and n = 18 0110101111110001010010100aaa0000 */
336 #define IS_PTABSL_R18(x) (((x) & 0xffffff8f) == 0x6bf14a00)
338 /* STS.L PR,@-r0 0100000000100010
339 r0-4-->r0, PR-->(r0) */
340 #define IS_STS_R0(x) ((x) == 0x4022)
342 /* STS PR, Rm 0000mmmm00101010
344 #define IS_STS_PR(x) (((x) & 0xf0ff) == 0x2a)
346 /* MOV.L Rm,@(disp,r15) 00011111mmmmdddd
348 #define IS_MOV_TO_R15(x) (((x) & 0xff00) == 0x1f00)
350 /* MOV.L R14,@(disp,r15) 000111111110dddd
351 R14-->(dispx4+r15) */
352 #define IS_MOV_R14(x) (((x) & 0xfff0) == 0x1fe0)
354 /* ST.Q R14, disp, R18 101011001110dddddddddd0100100000
355 R18-->(dispx8+R14) */
356 #define IS_STQ_R18_R14(x) (((x) & 0xfff003ff) == 0xace00120)
358 /* ST.Q R15, disp, R18 101011001111dddddddddd0100100000
359 R18-->(dispx8+R15) */
360 #define IS_STQ_R18_R15(x) (((x) & 0xfff003ff) == 0xacf00120)
362 /* ST.L R15, disp, R18 101010001111dddddddddd0100100000
363 R18-->(dispx4+R15) */
364 #define IS_STL_R18_R15(x) (((x) & 0xfff003ff) == 0xa8f00120)
366 /* ST.Q R15, disp, R14 1010 1100 1111 dddd dddd dd00 1110 0000
367 R14-->(dispx8+R15) */
368 #define IS_STQ_R14_R15(x) (((x) & 0xfff003ff) == 0xacf000e0)
370 /* ST.L R15, disp, R14 1010 1000 1111 dddd dddd dd00 1110 0000
371 R14-->(dispx4+R15) */
372 #define IS_STL_R14_R15(x) (((x) & 0xfff003ff) == 0xa8f000e0)
374 /* ADDI.L R15,imm,R15 1101 0100 1111 ssss ssss ss00 1111 0000
376 #define IS_ADDIL_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd4f000f0)
378 /* ADDI R15,imm,R15 1101 0000 1111 ssss ssss ss00 1111 0000
380 #define IS_ADDI_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd0f000f0)
382 /* ADD.L R15,R63,R14 0000 0000 1111 1000 1111 1100 1110 0000
384 #define IS_ADDL_SP_FP_MEDIA(x) ((x) == 0x00f8fce0)
386 /* ADD R15,R63,R14 0000 0000 1111 1001 1111 1100 1110 0000
388 #define IS_ADD_SP_FP_MEDIA(x) ((x) == 0x00f9fce0)
390 #define IS_MOV_SP_FP_MEDIA(x) \
391 (IS_ADDL_SP_FP_MEDIA(x) || IS_ADD_SP_FP_MEDIA(x))
393 /* MOV #imm, R0 1110 0000 ssss ssss
395 #define IS_MOV_R0(x) (((x) & 0xff00) == 0xe000)
397 /* MOV.L @(disp,PC), R0 1101 0000 iiii iiii */
398 #define IS_MOVL_R0(x) (((x) & 0xff00) == 0xd000)
400 /* ADD r15,r0 0011 0000 1111 1100
402 #define IS_ADD_SP_R0(x) ((x) == 0x30fc)
404 /* MOV.L R14 @-R0 0010 0000 1110 0110
405 R14-->(R0-4), R0-4-->R0 */
406 #define IS_MOV_R14_R0(x) ((x) == 0x20e6)
408 /* ADD Rm,R63,Rn Rm+R63-->Rn 0000 00mm mmmm 1001 1111 11nn nnnn 0000
409 where Rm is one of r2-r9 which are the argument registers. */
410 /* FIXME: Recognize the float and double register moves too! */
411 #define IS_MEDIA_IND_ARG_MOV(x) \
412 ((((x) & 0xfc0ffc0f) == 0x0009fc00) \
413 && (((x) & 0x03f00000) >= 0x00200000 \
414 && ((x) & 0x03f00000) <= 0x00900000))
416 /* ST.Q Rn,0,Rm Rm-->Rn+0 1010 11nn nnnn 0000 0000 00mm mmmm 0000
417 or ST.L Rn,0,Rm Rm-->Rn+0 1010 10nn nnnn 0000 0000 00mm mmmm 0000
418 where Rm is one of r2-r9 which are the argument registers. */
419 #define IS_MEDIA_ARG_MOV(x) \
420 (((((x) & 0xfc0ffc0f) == 0xac000000) || (((x) & 0xfc0ffc0f) == 0xa8000000)) \
421 && (((x) & 0x000003f0) >= 0x00000020 && ((x) & 0x000003f0) <= 0x00000090))
423 /* ST.B R14,0,Rn Rn-->(R14+0) 1010 0000 1110 0000 0000 00nn nnnn 0000 */
424 /* ST.W R14,0,Rn Rn-->(R14+0) 1010 0100 1110 0000 0000 00nn nnnn 0000 */
425 /* ST.L R14,0,Rn Rn-->(R14+0) 1010 1000 1110 0000 0000 00nn nnnn 0000 */
426 /* FST.S R14,0,FRn Rn-->(R14+0) 1011 0100 1110 0000 0000 00nn nnnn 0000 */
427 /* FST.D R14,0,DRn Rn-->(R14+0) 1011 1100 1110 0000 0000 00nn nnnn 0000 */
428 #define IS_MEDIA_MOV_TO_R14(x) \
429 ((((x) & 0xfffffc0f) == 0xa0e00000) \
430 || (((x) & 0xfffffc0f) == 0xa4e00000) \
431 || (((x) & 0xfffffc0f) == 0xa8e00000) \
432 || (((x) & 0xfffffc0f) == 0xb4e00000) \
433 || (((x) & 0xfffffc0f) == 0xbce00000))
435 /* MOV Rm, Rn Rm-->Rn 0110 nnnn mmmm 0011
437 #define IS_COMPACT_IND_ARG_MOV(x) \
438 ((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0020) \
439 && (((x) & 0x00f0) <= 0x0090))
441 /* compact direct arg move!
442 MOV.L Rn, @r14 0010 1110 mmmm 0010 */
443 #define IS_COMPACT_ARG_MOV(x) \
444 (((((x) & 0xff0f) == 0x2e02) && (((x) & 0x00f0) >= 0x0020) \
445 && ((x) & 0x00f0) <= 0x0090))
447 /* MOV.B Rm, @R14 0010 1110 mmmm 0000
448 MOV.W Rm, @R14 0010 1110 mmmm 0001 */
449 #define IS_COMPACT_MOV_TO_R14(x) \
450 ((((x) & 0xff0f) == 0x2e00) || (((x) & 0xff0f) == 0x2e01))
452 #define IS_JSR_R0(x) ((x) == 0x400b)
453 #define IS_NOP(x) ((x) == 0x0009)
456 /* MOV r15,r14 0110111011110011
458 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
460 /* ADD #imm,r15 01111111iiiiiiii
462 #define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00)
464 /* Skip any prologue before the guts of a function. */
466 /* Skip the prologue using the debug information. If this fails we'll
467 fall back on the 'guess' method below. */
469 after_prologue (CORE_ADDR pc
)
471 struct symtab_and_line sal
;
472 CORE_ADDR func_addr
, func_end
;
474 /* If we can not find the symbol in the partial symbol table, then
475 there is no hope we can determine the function's start address
477 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
481 /* Get the line associated with FUNC_ADDR. */
482 sal
= find_pc_line (func_addr
, 0);
484 /* There are only two cases to consider. First, the end of the source line
485 is within the function bounds. In that case we return the end of the
486 source line. Second is the end of the source line extends beyond the
487 bounds of the current function. We need to use the slow code to
488 examine instructions in that case. */
489 if (sal
.end
< func_end
)
496 look_for_args_moves (struct gdbarch
*gdbarch
,
497 CORE_ADDR start_pc
, int media_mode
)
499 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
502 int insn_size
= (media_mode
? 4 : 2);
504 for (here
= start_pc
, end
= start_pc
+ (insn_size
* 28); here
< end
;)
508 w
= read_memory_integer (UNMAKE_ISA32_ADDR (here
),
509 insn_size
, byte_order
);
511 if (IS_MEDIA_IND_ARG_MOV (w
))
513 /* This must be followed by a store to r14, so the argument
514 is where the debug info says it is. This can happen after
515 the SP has been saved, unfortunately. */
517 int next_insn
= read_memory_integer (UNMAKE_ISA32_ADDR (here
),
518 insn_size
, byte_order
);
520 if (IS_MEDIA_MOV_TO_R14 (next_insn
))
523 else if (IS_MEDIA_ARG_MOV (w
))
525 /* These instructions store directly the argument in r14. */
533 w
= read_memory_integer (here
, insn_size
, byte_order
);
536 if (IS_COMPACT_IND_ARG_MOV (w
))
538 /* This must be followed by a store to r14, so the argument
539 is where the debug info says it is. This can happen after
540 the SP has been saved, unfortunately. */
542 int next_insn
= 0xffff & read_memory_integer (here
, insn_size
,
545 if (IS_COMPACT_MOV_TO_R14 (next_insn
))
548 else if (IS_COMPACT_ARG_MOV (w
))
550 /* These instructions store directly the argument in r14. */
553 else if (IS_MOVL_R0 (w
))
555 /* There is a function that gcc calls to get the arguments
556 passed correctly to the function. Only after this
557 function call the arguments will be found at the place
558 where they are supposed to be. This happens in case the
559 argument has to be stored into a 64-bit register (for
560 instance doubles, long longs). SHcompact doesn't have
561 access to the full 64-bits, so we store the register in
562 stack slot and store the address of the stack slot in
563 the register, then do a call through a wrapper that
564 loads the memory value into the register. A SHcompact
565 callee calls an argument decoder
566 (GCC_shcompact_incoming_args) that stores the 64-bit
567 value in a stack slot and stores the address of the
568 stack slot in the register. GCC thinks the argument is
569 just passed by transparent reference, but this is only
570 true after the argument decoder is called. Such a call
571 needs to be considered part of the prologue. */
573 /* This must be followed by a JSR @r0 instruction and by
574 a NOP instruction. After these, the prologue is over! */
576 int next_insn
= 0xffff & read_memory_integer (here
, insn_size
,
579 if (IS_JSR_R0 (next_insn
))
581 next_insn
= 0xffff & read_memory_integer (here
, insn_size
,
585 if (IS_NOP (next_insn
))
598 sh64_skip_prologue_hard_way (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
600 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
609 if (pc_is_isa32 (start_pc
) == 0)
615 for (here
= start_pc
, end
= start_pc
+ (insn_size
* 28); here
< end
;)
620 int w
= read_memory_integer (UNMAKE_ISA32_ADDR (here
),
621 insn_size
, byte_order
);
623 if (IS_STQ_R18_R14 (w
) || IS_STQ_R18_R15 (w
) || IS_STQ_R14_R15 (w
)
624 || IS_STL_R14_R15 (w
) || IS_STL_R18_R15 (w
)
625 || IS_ADDIL_SP_MEDIA (w
) || IS_ADDI_SP_MEDIA (w
)
626 || IS_PTABSL_R18 (w
))
630 else if (IS_MOV_SP_FP (w
) || IS_MOV_SP_FP_MEDIA(w
))
638 /* Don't bail out yet, we may have arguments stored in
639 registers here, according to the debug info, so that
640 gdb can print the frames correctly. */
641 start_pc
= look_for_args_moves (gdbarch
,
642 here
- insn_size
, media_mode
);
648 int w
= 0xffff & read_memory_integer (here
, insn_size
, byte_order
);
651 if (IS_STS_R0 (w
) || IS_STS_PR (w
)
652 || IS_MOV_TO_R15 (w
) || IS_MOV_R14 (w
)
653 || IS_MOV_R0 (w
) || IS_ADD_SP_R0 (w
) || IS_MOV_R14_R0 (w
))
657 else if (IS_MOV_SP_FP (w
))
665 /* Don't bail out yet, we may have arguments stored in
666 registers here, according to the debug info, so that
667 gdb can print the frames correctly. */
668 start_pc
= look_for_args_moves (gdbarch
,
669 here
- insn_size
, media_mode
);
679 sh64_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
681 CORE_ADDR post_prologue_pc
;
683 /* See if we can determine the end of the prologue via the symbol table.
684 If so, then return either PC, or the PC after the prologue, whichever
686 post_prologue_pc
= after_prologue (pc
);
688 /* If after_prologue returned a useful address, then use it. Else
689 fall back on the instruction skipping code. */
690 if (post_prologue_pc
!= 0)
691 return max (pc
, post_prologue_pc
);
693 return sh64_skip_prologue_hard_way (gdbarch
, pc
);
696 /* Should call_function allocate stack space for a struct return? */
698 sh64_use_struct_convention (struct type
*type
)
700 return (TYPE_LENGTH (type
) > 8);
703 /* For vectors of 4 floating point registers. */
705 sh64_fv_reg_base_num (struct gdbarch
*gdbarch
, int fv_regnum
)
709 fp_regnum
= gdbarch_fp0_regnum (gdbarch
) + (fv_regnum
- FV0_REGNUM
) * 4;
713 /* For double precision floating point registers, i.e 2 fp regs. */
715 sh64_dr_reg_base_num (struct gdbarch
*gdbarch
, int dr_regnum
)
719 fp_regnum
= gdbarch_fp0_regnum (gdbarch
) + (dr_regnum
- DR0_REGNUM
) * 2;
723 /* For pairs of floating point registers. */
725 sh64_fpp_reg_base_num (struct gdbarch
*gdbarch
, int fpp_regnum
)
729 fp_regnum
= gdbarch_fp0_regnum (gdbarch
) + (fpp_regnum
- FPP0_REGNUM
) * 2;
735 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
736 GDB_REGNUM BASE_REGNUM
796 sh64_compact_reg_base_num (struct gdbarch
*gdbarch
, int reg_nr
)
798 int base_regnum
= reg_nr
;
800 /* general register N maps to general register N */
801 if (reg_nr
>= R0_C_REGNUM
802 && reg_nr
<= R_LAST_C_REGNUM
)
803 base_regnum
= reg_nr
- R0_C_REGNUM
;
805 /* floating point register N maps to floating point register N */
806 else if (reg_nr
>= FP0_C_REGNUM
807 && reg_nr
<= FP_LAST_C_REGNUM
)
808 base_regnum
= reg_nr
- FP0_C_REGNUM
+ gdbarch_fp0_regnum (gdbarch
);
810 /* double prec register N maps to base regnum for double prec register N */
811 else if (reg_nr
>= DR0_C_REGNUM
812 && reg_nr
<= DR_LAST_C_REGNUM
)
813 base_regnum
= sh64_dr_reg_base_num (gdbarch
,
814 DR0_REGNUM
+ reg_nr
- DR0_C_REGNUM
);
816 /* vector N maps to base regnum for vector register N */
817 else if (reg_nr
>= FV0_C_REGNUM
818 && reg_nr
<= FV_LAST_C_REGNUM
)
819 base_regnum
= sh64_fv_reg_base_num (gdbarch
,
820 FV0_REGNUM
+ reg_nr
- FV0_C_REGNUM
);
822 else if (reg_nr
== PC_C_REGNUM
)
823 base_regnum
= gdbarch_pc_regnum (gdbarch
);
825 else if (reg_nr
== GBR_C_REGNUM
)
828 else if (reg_nr
== MACH_C_REGNUM
829 || reg_nr
== MACL_C_REGNUM
)
832 else if (reg_nr
== PR_C_REGNUM
)
833 base_regnum
= PR_REGNUM
;
835 else if (reg_nr
== T_C_REGNUM
)
838 else if (reg_nr
== FPSCR_C_REGNUM
)
839 base_regnum
= FPSCR_REGNUM
; /*???? this register is a mess. */
841 else if (reg_nr
== FPUL_C_REGNUM
)
842 base_regnum
= gdbarch_fp0_regnum (gdbarch
) + 32;
848 sign_extend (int value
, int bits
)
850 value
= value
& ((1 << bits
) - 1);
851 return (value
& (1 << (bits
- 1))
852 ? value
| (~((1 << bits
) - 1))
857 sh64_analyze_prologue (struct gdbarch
*gdbarch
,
858 struct sh64_frame_cache
*cache
,
860 CORE_ADDR current_pc
)
868 int gdb_register_number
;
870 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
871 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
873 cache
->sp_offset
= 0;
875 /* Loop around examining the prologue insns until we find something
876 that does not appear to be part of the prologue. But give up
877 after 20 of them, since we're getting silly then. */
881 if (cache
->media_mode
)
886 opc
= pc
+ (insn_size
* 28);
887 if (opc
> current_pc
)
889 for ( ; pc
<= opc
; pc
+= insn_size
)
891 insn
= read_memory_integer (cache
->media_mode
? UNMAKE_ISA32_ADDR (pc
)
893 insn_size
, byte_order
);
895 if (!cache
->media_mode
)
897 if (IS_STS_PR (insn
))
899 int next_insn
= read_memory_integer (pc
+ insn_size
,
900 insn_size
, byte_order
);
901 if (IS_MOV_TO_R15 (next_insn
))
903 cache
->saved_regs
[PR_REGNUM
]
904 = cache
->sp_offset
- ((((next_insn
& 0xf) ^ 0x8)
910 else if (IS_MOV_R14 (insn
))
911 cache
->saved_regs
[MEDIA_FP_REGNUM
] =
912 cache
->sp_offset
- ((((insn
& 0xf) ^ 0x8) - 0x8) << 2);
914 else if (IS_MOV_R0 (insn
))
916 /* Put in R0 the offset from SP at which to store some
917 registers. We are interested in this value, because it
918 will tell us where the given registers are stored within
920 r0_val
= ((insn
& 0xff) ^ 0x80) - 0x80;
923 else if (IS_ADD_SP_R0 (insn
))
925 /* This instruction still prepares r0, but we don't care.
926 We already have the offset in r0_val. */
929 else if (IS_STS_R0 (insn
))
931 /* Store PR at r0_val-4 from SP. Decrement r0 by 4. */
932 cache
->saved_regs
[PR_REGNUM
] = cache
->sp_offset
- (r0_val
- 4);
936 else if (IS_MOV_R14_R0 (insn
))
938 /* Store R14 at r0_val-4 from SP. Decrement r0 by 4. */
939 cache
->saved_regs
[MEDIA_FP_REGNUM
] = cache
->sp_offset
944 else if (IS_ADD_SP (insn
))
945 cache
->sp_offset
-= ((insn
& 0xff) ^ 0x80) - 0x80;
947 else if (IS_MOV_SP_FP (insn
))
952 if (IS_ADDIL_SP_MEDIA (insn
) || IS_ADDI_SP_MEDIA (insn
))
954 sign_extend ((((insn
& 0xffc00) ^ 0x80000) - 0x80000) >> 10, 9);
956 else if (IS_STQ_R18_R15 (insn
))
957 cache
->saved_regs
[PR_REGNUM
]
958 = cache
->sp_offset
- (sign_extend ((insn
& 0xffc00) >> 10,
961 else if (IS_STL_R18_R15 (insn
))
962 cache
->saved_regs
[PR_REGNUM
]
963 = cache
->sp_offset
- (sign_extend ((insn
& 0xffc00) >> 10,
966 else if (IS_STQ_R14_R15 (insn
))
967 cache
->saved_regs
[MEDIA_FP_REGNUM
]
968 = cache
->sp_offset
- (sign_extend ((insn
& 0xffc00) >> 10,
971 else if (IS_STL_R14_R15 (insn
))
972 cache
->saved_regs
[MEDIA_FP_REGNUM
]
973 = cache
->sp_offset
- (sign_extend ((insn
& 0xffc00) >> 10,
976 else if (IS_MOV_SP_FP_MEDIA (insn
))
981 if (cache
->saved_regs
[MEDIA_FP_REGNUM
] >= 0)
986 sh64_frame_align (struct gdbarch
*ignore
, CORE_ADDR sp
)
991 /* Function: push_dummy_call
992 Setup the function arguments for calling a function in the inferior.
994 On the Renesas SH architecture, there are four registers (R4 to R7)
995 which are dedicated for passing function arguments. Up to the first
996 four arguments (depending on size) may go into these registers.
997 The rest go on the stack.
999 Arguments that are smaller than 4 bytes will still take up a whole
1000 register or a whole 32-bit word on the stack, and will be
1001 right-justified in the register or the stack word. This includes
1002 chars, shorts, and small aggregate types.
1004 Arguments that are larger than 4 bytes may be split between two or
1005 more registers. If there are not enough registers free, an argument
1006 may be passed partly in a register (or registers), and partly on the
1007 stack. This includes doubles, long longs, and larger aggregates.
1008 As far as I know, there is no upper limit to the size of aggregates
1009 that will be passed in this way; in other words, the convention of
1010 passing a pointer to a large aggregate instead of a copy is not used.
1012 An exceptional case exists for struct arguments (and possibly other
1013 aggregates such as arrays) if the size is larger than 4 bytes but
1014 not a multiple of 4 bytes. In this case the argument is never split
1015 between the registers and the stack, but instead is copied in its
1016 entirety onto the stack, AND also copied into as many registers as
1017 there is room for. In other words, space in registers permitting,
1018 two copies of the same argument are passed in. As far as I can tell,
1019 only the one on the stack is used, although that may be a function
1020 of the level of compiler optimization. I suspect this is a compiler
1021 bug. Arguments of these odd sizes are left-justified within the
1022 word (as opposed to arguments smaller than 4 bytes, which are
1025 If the function is to return an aggregate type such as a struct, it
1026 is either returned in the normal return value register R0 (if its
1027 size is no greater than one byte), or else the caller must allocate
1028 space into which the callee will copy the return value (if the size
1029 is greater than one byte). In this case, a pointer to the return
1030 value location is passed into the callee in register R2, which does
1031 not displace any of the other arguments passed in via registers R4
1034 /* R2-R9 for integer types and integer equivalent (char, pointers) and
1035 non-scalar (struct, union) elements (even if the elements are
1037 FR0-FR11 for single precision floating point (float)
1038 DR0-DR10 for double precision floating point (double)
1040 If a float is argument number 3 (for instance) and arguments number
1041 1,2, and 4 are integer, the mapping will be:
1042 arg1 -->R2, arg2 --> R3, arg3 -->FR0, arg4 --> R5. I.e. R4 is not used.
1044 If a float is argument number 10 (for instance) and arguments number
1045 1 through 10 are integer, the mapping will be:
1046 arg1->R2, arg2->R3, arg3->R4, arg4->R5, arg5->R6, arg6->R7, arg7->R8,
1047 arg8->R9, arg9->(0,SP)stack(8-byte aligned), arg10->FR0,
1048 arg11->stack(16,SP). I.e. there is hole in the stack.
1050 Different rules apply for variable arguments functions, and for functions
1051 for which the prototype is not known. */
1054 sh64_push_dummy_call (struct gdbarch
*gdbarch
,
1055 struct value
*function
,
1056 struct regcache
*regcache
,
1058 int nargs
, struct value
**args
,
1059 CORE_ADDR sp
, int struct_return
,
1060 CORE_ADDR struct_addr
)
1062 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1063 int stack_offset
, stack_alloc
;
1067 int float_arg_index
= 0;
1068 int double_arg_index
= 0;
1079 memset (fp_args
, 0, sizeof (fp_args
));
1081 /* First force sp to a 8-byte alignment. */
1082 sp
= sh64_frame_align (gdbarch
, sp
);
1084 /* The "struct return pointer" pseudo-argument has its own dedicated
1088 regcache_cooked_write_unsigned (regcache
,
1089 STRUCT_RETURN_REGNUM
, struct_addr
);
1091 /* Now make sure there's space on the stack. */
1092 for (argnum
= 0, stack_alloc
= 0; argnum
< nargs
; argnum
++)
1093 stack_alloc
+= ((TYPE_LENGTH (value_type (args
[argnum
])) + 7) & ~7);
1094 sp
-= stack_alloc
; /* Make room on stack for args. */
1096 /* Now load as many as possible of the first arguments into
1097 registers, and push the rest onto the stack. There are 64 bytes
1098 in eight registers available. Loop thru args from first to last. */
1100 int_argreg
= ARG0_REGNUM
;
1101 float_argreg
= gdbarch_fp0_regnum (gdbarch
);
1102 double_argreg
= DR0_REGNUM
;
1104 for (argnum
= 0, stack_offset
= 0; argnum
< nargs
; argnum
++)
1106 type
= value_type (args
[argnum
]);
1107 len
= TYPE_LENGTH (type
);
1108 memset (valbuf
, 0, sizeof (valbuf
));
1110 if (TYPE_CODE (type
) != TYPE_CODE_FLT
)
1112 argreg_size
= register_size (gdbarch
, int_argreg
);
1114 if (len
< argreg_size
)
1116 /* value gets right-justified in the register or stack word. */
1117 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1118 memcpy (valbuf
+ argreg_size
- len
,
1119 (char *) value_contents (args
[argnum
]), len
);
1121 memcpy (valbuf
, (char *) value_contents (args
[argnum
]), len
);
1126 val
= (char *) value_contents (args
[argnum
]);
1130 if (int_argreg
> ARGLAST_REGNUM
)
1132 /* Must go on the stack. */
1133 write_memory (sp
+ stack_offset
, (const bfd_byte
*) val
,
1135 stack_offset
+= 8;/*argreg_size;*/
1137 /* NOTE WELL!!!!! This is not an "else if" clause!!!
1138 That's because some *&^%$ things get passed on the stack
1139 AND in the registers! */
1140 if (int_argreg
<= ARGLAST_REGNUM
)
1142 /* There's room in a register. */
1143 regval
= extract_unsigned_integer (val
, argreg_size
,
1145 regcache_cooked_write_unsigned (regcache
,
1146 int_argreg
, regval
);
1148 /* Store the value 8 bytes at a time. This means that
1149 things larger than 8 bytes may go partly in registers
1150 and partly on the stack. FIXME: argreg is incremented
1151 before we use its size. */
1159 val
= (char *) value_contents (args
[argnum
]);
1162 /* Where is it going to be stored? */
1163 while (fp_args
[float_arg_index
])
1166 /* Now float_argreg points to the register where it
1167 should be stored. Are we still within the allowed
1169 if (float_arg_index
<= FLOAT_ARGLAST_REGNUM
)
1171 /* Goes in FR0...FR11 */
1172 regcache_cooked_write (regcache
,
1173 gdbarch_fp0_regnum (gdbarch
)
1176 fp_args
[float_arg_index
] = 1;
1177 /* Skip the corresponding general argument register. */
1182 /* Store it as the integers, 8 bytes at the time, if
1183 necessary spilling on the stack. */
1188 /* Where is it going to be stored? */
1189 while (fp_args
[double_arg_index
])
1190 double_arg_index
+= 2;
1191 /* Now double_argreg points to the register
1192 where it should be stored.
1193 Are we still within the allowed register set? */
1194 if (double_arg_index
< FLOAT_ARGLAST_REGNUM
)
1196 /* Goes in DR0...DR10 */
1197 /* The numbering of the DRi registers is consecutive,
1198 i.e. includes odd numbers. */
1199 int double_register_offset
= double_arg_index
/ 2;
1200 int regnum
= DR0_REGNUM
+ double_register_offset
;
1201 regcache_cooked_write (regcache
, regnum
, val
);
1202 fp_args
[double_arg_index
] = 1;
1203 fp_args
[double_arg_index
+ 1] = 1;
1204 /* Skip the corresponding general argument register. */
1209 /* Store it as the integers, 8 bytes at the time, if
1210 necessary spilling on the stack. */
1214 /* Store return address. */
1215 regcache_cooked_write_unsigned (regcache
, PR_REGNUM
, bp_addr
);
1217 /* Update stack pointer. */
1218 regcache_cooked_write_unsigned (regcache
,
1219 gdbarch_sp_regnum (gdbarch
), sp
);
1224 /* Find a function's return value in the appropriate registers (in
1225 regbuf), and copy it into valbuf. Extract from an array REGBUF
1226 containing the (raw) register state a function return value of type
1227 TYPE, and copy that, in virtual format, into VALBUF. */
1229 sh64_extract_return_value (struct type
*type
, struct regcache
*regcache
,
1232 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1233 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1234 int len
= TYPE_LENGTH (type
);
1236 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1240 /* Return value stored in gdbarch_fp0_regnum. */
1241 regcache_raw_read (regcache
,
1242 gdbarch_fp0_regnum (gdbarch
), valbuf
);
1246 /* return value stored in DR0_REGNUM. */
1250 regcache_cooked_read (regcache
, DR0_REGNUM
, buf
);
1252 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
1253 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword
,
1256 floatformat_to_doublest (&floatformat_ieee_double_big
,
1258 store_typed_floating (valbuf
, type
, val
);
1267 /* Result is in register 2. If smaller than 8 bytes, it is padded
1268 at the most significant end. */
1269 regcache_raw_read (regcache
, DEFAULT_RETURN_REGNUM
, buf
);
1271 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1272 offset
= register_size (gdbarch
, DEFAULT_RETURN_REGNUM
)
1276 memcpy (valbuf
, buf
+ offset
, len
);
1279 error (_("bad size for return value"));
1283 /* Write into appropriate registers a function return value
1284 of type TYPE, given in virtual format.
1285 If the architecture is sh4 or sh3e, store a function's return value
1286 in the R0 general register or in the FP0 floating point register,
1287 depending on the type of the return value. In all the other cases
1288 the result is stored in r0, left-justified. */
1291 sh64_store_return_value (struct type
*type
, struct regcache
*regcache
,
1294 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1295 char buf
[64]; /* more than enough... */
1296 int len
= TYPE_LENGTH (type
);
1298 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1300 int i
, regnum
= gdbarch_fp0_regnum (gdbarch
);
1301 for (i
= 0; i
< len
; i
+= 4)
1302 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
1303 regcache_raw_write (regcache
, regnum
++,
1304 (char *) valbuf
+ len
- 4 - i
);
1306 regcache_raw_write (regcache
, regnum
++, (char *) valbuf
+ i
);
1310 int return_register
= DEFAULT_RETURN_REGNUM
;
1313 if (len
<= register_size (gdbarch
, return_register
))
1315 /* Pad with zeros. */
1316 memset (buf
, 0, register_size (gdbarch
, return_register
));
1317 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
1318 offset
= 0; /*register_size (gdbarch,
1319 return_register) - len;*/
1321 offset
= register_size (gdbarch
, return_register
) - len
;
1323 memcpy (buf
+ offset
, valbuf
, len
);
1324 regcache_raw_write (regcache
, return_register
, buf
);
1327 regcache_raw_write (regcache
, return_register
, valbuf
);
1331 static enum return_value_convention
1332 sh64_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
1333 struct type
*type
, struct regcache
*regcache
,
1334 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1336 if (sh64_use_struct_convention (type
))
1337 return RETURN_VALUE_STRUCT_CONVENTION
;
1339 sh64_store_return_value (type
, regcache
, writebuf
);
1341 sh64_extract_return_value (type
, regcache
, readbuf
);
1342 return RETURN_VALUE_REGISTER_CONVENTION
;
1346 sh64_show_media_regs (struct frame_info
*frame
)
1348 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1353 phex (get_frame_register_unsigned (frame
,
1354 gdbarch_pc_regnum (gdbarch
)), 8),
1355 phex (get_frame_register_unsigned (frame
, SR_REGNUM
), 8));
1359 phex (get_frame_register_unsigned (frame
, SSR_REGNUM
), 8),
1360 phex (get_frame_register_unsigned (frame
, SPC_REGNUM
), 8));
1363 phex (get_frame_register_unsigned (frame
, FPSCR_REGNUM
), 8));
1365 for (i
= 0; i
< 64; i
= i
+ 4)
1367 ("\nR%d-R%d %s %s %s %s\n",
1369 phex (get_frame_register_unsigned (frame
, i
+ 0), 8),
1370 phex (get_frame_register_unsigned (frame
, i
+ 1), 8),
1371 phex (get_frame_register_unsigned (frame
, i
+ 2), 8),
1372 phex (get_frame_register_unsigned (frame
, i
+ 3), 8));
1374 printf_filtered ("\n");
1376 for (i
= 0; i
< 64; i
= i
+ 8)
1378 ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1380 (long) get_frame_register_unsigned
1381 (frame
, gdbarch_fp0_regnum (gdbarch
) + i
+ 0),
1382 (long) get_frame_register_unsigned
1383 (frame
, gdbarch_fp0_regnum (gdbarch
) + i
+ 1),
1384 (long) get_frame_register_unsigned
1385 (frame
, gdbarch_fp0_regnum (gdbarch
) + i
+ 2),
1386 (long) get_frame_register_unsigned
1387 (frame
, gdbarch_fp0_regnum (gdbarch
) + i
+ 3),
1388 (long) get_frame_register_unsigned
1389 (frame
, gdbarch_fp0_regnum (gdbarch
) + i
+ 4),
1390 (long) get_frame_register_unsigned
1391 (frame
, gdbarch_fp0_regnum (gdbarch
) + i
+ 5),
1392 (long) get_frame_register_unsigned
1393 (frame
, gdbarch_fp0_regnum (gdbarch
) + i
+ 6),
1394 (long) get_frame_register_unsigned
1395 (frame
, gdbarch_fp0_regnum (gdbarch
) + i
+ 7));
1399 sh64_show_compact_regs (struct frame_info
*frame
)
1401 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1406 phex (get_frame_register_unsigned (frame
, PC_C_REGNUM
), 8));
1409 ("GBR=%08lx MACH=%08lx MACL=%08lx PR=%08lx T=%08lx\n",
1410 (long) get_frame_register_unsigned (frame
, GBR_C_REGNUM
),
1411 (long) get_frame_register_unsigned (frame
, MACH_C_REGNUM
),
1412 (long) get_frame_register_unsigned (frame
, MACL_C_REGNUM
),
1413 (long) get_frame_register_unsigned (frame
, PR_C_REGNUM
),
1414 (long) get_frame_register_unsigned (frame
, T_C_REGNUM
));
1416 ("FPSCR=%08lx FPUL=%08lx\n",
1417 (long) get_frame_register_unsigned (frame
, FPSCR_C_REGNUM
),
1418 (long) get_frame_register_unsigned (frame
, FPUL_C_REGNUM
));
1420 for (i
= 0; i
< 16; i
= i
+ 4)
1422 ("\nR%d-R%d %08lx %08lx %08lx %08lx\n",
1424 (long) get_frame_register_unsigned (frame
, i
+ 0),
1425 (long) get_frame_register_unsigned (frame
, i
+ 1),
1426 (long) get_frame_register_unsigned (frame
, i
+ 2),
1427 (long) get_frame_register_unsigned (frame
, i
+ 3));
1429 printf_filtered ("\n");
1431 for (i
= 0; i
< 16; i
= i
+ 8)
1433 ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1435 (long) get_frame_register_unsigned
1436 (frame
, gdbarch_fp0_regnum (gdbarch
) + i
+ 0),
1437 (long) get_frame_register_unsigned
1438 (frame
, gdbarch_fp0_regnum (gdbarch
) + i
+ 1),
1439 (long) get_frame_register_unsigned
1440 (frame
, gdbarch_fp0_regnum (gdbarch
) + i
+ 2),
1441 (long) get_frame_register_unsigned
1442 (frame
, gdbarch_fp0_regnum (gdbarch
) + i
+ 3),
1443 (long) get_frame_register_unsigned
1444 (frame
, gdbarch_fp0_regnum (gdbarch
) + i
+ 4),
1445 (long) get_frame_register_unsigned
1446 (frame
, gdbarch_fp0_regnum (gdbarch
) + i
+ 5),
1447 (long) get_frame_register_unsigned
1448 (frame
, gdbarch_fp0_regnum (gdbarch
) + i
+ 6),
1449 (long) get_frame_register_unsigned
1450 (frame
, gdbarch_fp0_regnum (gdbarch
) + i
+ 7));
1453 /* FIXME!!! This only shows the registers for shmedia, excluding the
1454 pseudo registers. */
1456 sh64_show_regs (struct frame_info
*frame
)
1458 if (pc_is_isa32 (get_frame_pc (frame
)))
1459 sh64_show_media_regs (frame
);
1461 sh64_show_compact_regs (frame
);
1466 SH MEDIA MODE (ISA 32)
1467 general registers (64-bit) 0-63
1468 0 r0, r1, r2, r3, r4, r5, r6, r7,
1469 64 r8, r9, r10, r11, r12, r13, r14, r15,
1470 128 r16, r17, r18, r19, r20, r21, r22, r23,
1471 192 r24, r25, r26, r27, r28, r29, r30, r31,
1472 256 r32, r33, r34, r35, r36, r37, r38, r39,
1473 320 r40, r41, r42, r43, r44, r45, r46, r47,
1474 384 r48, r49, r50, r51, r52, r53, r54, r55,
1475 448 r56, r57, r58, r59, r60, r61, r62, r63,
1480 status reg., saved status reg., saved pc reg. (64-bit) 65-67
1483 target registers (64-bit) 68-75
1484 544 tr0, tr1, tr2, tr3, tr4, tr5, tr6, tr7,
1486 floating point state control register (32-bit) 76
1489 single precision floating point registers (32-bit) 77-140
1490 612 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
1491 644 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15,
1492 676 fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23,
1493 708 fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31,
1494 740 fr32, fr33, fr34, fr35, fr36, fr37, fr38, fr39,
1495 772 fr40, fr41, fr42, fr43, fr44, fr45, fr46, fr47,
1496 804 fr48, fr49, fr50, fr51, fr52, fr53, fr54, fr55,
1497 836 fr56, fr57, fr58, fr59, fr60, fr61, fr62, fr63,
1499 TOTAL SPACE FOR REGISTERS: 868 bytes
1501 From here on they are all pseudo registers: no memory allocated.
1502 REGISTER_BYTE returns the register byte for the base register.
1504 double precision registers (pseudo) 141-172
1505 dr0, dr2, dr4, dr6, dr8, dr10, dr12, dr14,
1506 dr16, dr18, dr20, dr22, dr24, dr26, dr28, dr30,
1507 dr32, dr34, dr36, dr38, dr40, dr42, dr44, dr46,
1508 dr48, dr50, dr52, dr54, dr56, dr58, dr60, dr62,
1510 floating point pairs (pseudo) 173-204
1511 fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14,
1512 fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30,
1513 fp32, fp34, fp36, fp38, fp40, fp42, fp44, fp46,
1514 fp48, fp50, fp52, fp54, fp56, fp58, fp60, fp62,
1516 floating point vectors (4 floating point regs) (pseudo) 205-220
1517 fv0, fv4, fv8, fv12, fv16, fv20, fv24, fv28,
1518 fv32, fv36, fv40, fv44, fv48, fv52, fv56, fv60,
1520 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
1521 r0_c, r1_c, r2_c, r3_c, r4_c, r5_c, r6_c, r7_c,
1522 r8_c, r9_c, r10_c, r11_c, r12_c, r13_c, r14_c, r15_c,
1524 gbr_c, mach_c, macl_c, pr_c, t_c,
1526 fr0_c, fr1_c, fr2_c, fr3_c, fr4_c, fr5_c, fr6_c, fr7_c,
1527 fr8_c, fr9_c, fr10_c, fr11_c, fr12_c, fr13_c, fr14_c, fr15_c
1528 dr0_c, dr2_c, dr4_c, dr6_c, dr8_c, dr10_c, dr12_c, dr14_c
1529 fv0_c, fv4_c, fv8_c, fv12_c
1532 static struct type
*
1533 sh64_build_float_register_type (struct gdbarch
*gdbarch
, int high
)
1535 return lookup_array_range_type (builtin_type (gdbarch
)->builtin_float
,
1539 /* Return the GDB type object for the "standard" data type
1540 of data in register REG_NR. */
1541 static struct type
*
1542 sh64_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
1544 if ((reg_nr
>= gdbarch_fp0_regnum (gdbarch
)
1545 && reg_nr
<= FP_LAST_REGNUM
)
1546 || (reg_nr
>= FP0_C_REGNUM
1547 && reg_nr
<= FP_LAST_C_REGNUM
))
1548 return builtin_type (gdbarch
)->builtin_float
;
1549 else if ((reg_nr
>= DR0_REGNUM
1550 && reg_nr
<= DR_LAST_REGNUM
)
1551 || (reg_nr
>= DR0_C_REGNUM
1552 && reg_nr
<= DR_LAST_C_REGNUM
))
1553 return builtin_type (gdbarch
)->builtin_double
;
1554 else if (reg_nr
>= FPP0_REGNUM
1555 && reg_nr
<= FPP_LAST_REGNUM
)
1556 return sh64_build_float_register_type (gdbarch
, 1);
1557 else if ((reg_nr
>= FV0_REGNUM
1558 && reg_nr
<= FV_LAST_REGNUM
)
1559 ||(reg_nr
>= FV0_C_REGNUM
1560 && reg_nr
<= FV_LAST_C_REGNUM
))
1561 return sh64_build_float_register_type (gdbarch
, 3);
1562 else if (reg_nr
== FPSCR_REGNUM
)
1563 return builtin_type (gdbarch
)->builtin_int
;
1564 else if (reg_nr
>= R0_C_REGNUM
1565 && reg_nr
< FP0_C_REGNUM
)
1566 return builtin_type (gdbarch
)->builtin_int
;
1568 return builtin_type (gdbarch
)->builtin_long_long
;
1572 sh64_register_convert_to_virtual (struct gdbarch
*gdbarch
, int regnum
,
1573 struct type
*type
, char *from
, char *to
)
1575 if (gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_LITTLE
)
1577 /* It is a no-op. */
1578 memcpy (to
, from
, register_size (gdbarch
, regnum
));
1582 if ((regnum
>= DR0_REGNUM
1583 && regnum
<= DR_LAST_REGNUM
)
1584 || (regnum
>= DR0_C_REGNUM
1585 && regnum
<= DR_LAST_C_REGNUM
))
1588 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword
,
1590 store_typed_floating (to
, type
, val
);
1593 error (_("sh64_register_convert_to_virtual "
1594 "called with non DR register number"));
1598 sh64_register_convert_to_raw (struct gdbarch
*gdbarch
, struct type
*type
,
1599 int regnum
, const void *from
, void *to
)
1601 if (gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_LITTLE
)
1603 /* It is a no-op. */
1604 memcpy (to
, from
, register_size (gdbarch
, regnum
));
1608 if ((regnum
>= DR0_REGNUM
1609 && regnum
<= DR_LAST_REGNUM
)
1610 || (regnum
>= DR0_C_REGNUM
1611 && regnum
<= DR_LAST_C_REGNUM
))
1613 DOUBLEST val
= extract_typed_floating (from
, type
);
1614 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword
,
1618 error (_("sh64_register_convert_to_raw called "
1619 "with non DR register number"));
1622 /* Concatenate PORTIONS contiguous raw registers starting at
1623 BASE_REGNUM into BUFFER. */
1625 static enum register_status
1626 pseudo_register_read_portions (struct gdbarch
*gdbarch
,
1627 struct regcache
*regcache
,
1629 int base_regnum
, gdb_byte
*buffer
)
1633 for (portion
= 0; portion
< portions
; portion
++)
1635 enum register_status status
;
1638 b
= buffer
+ register_size (gdbarch
, base_regnum
) * portion
;
1639 status
= regcache_raw_read (regcache
, base_regnum
+ portion
, b
);
1640 if (status
!= REG_VALID
)
1647 static enum register_status
1648 sh64_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1649 int reg_nr
, gdb_byte
*buffer
)
1651 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1654 char temp_buffer
[MAX_REGISTER_SIZE
];
1655 enum register_status status
;
1657 if (reg_nr
>= DR0_REGNUM
1658 && reg_nr
<= DR_LAST_REGNUM
)
1660 base_regnum
= sh64_dr_reg_base_num (gdbarch
, reg_nr
);
1662 /* Build the value in the provided buffer. */
1663 /* DR regs are double precision registers obtained by
1664 concatenating 2 single precision floating point registers. */
1665 status
= pseudo_register_read_portions (gdbarch
, regcache
,
1666 2, base_regnum
, temp_buffer
);
1667 if (status
== REG_VALID
)
1669 /* We must pay attention to the endianness. */
1670 sh64_register_convert_to_virtual (gdbarch
, reg_nr
,
1671 register_type (gdbarch
, reg_nr
),
1672 temp_buffer
, buffer
);
1678 else if (reg_nr
>= FPP0_REGNUM
1679 && reg_nr
<= FPP_LAST_REGNUM
)
1681 base_regnum
= sh64_fpp_reg_base_num (gdbarch
, reg_nr
);
1683 /* Build the value in the provided buffer. */
1684 /* FPP regs are pairs of single precision registers obtained by
1685 concatenating 2 single precision floating point registers. */
1686 return pseudo_register_read_portions (gdbarch
, regcache
,
1687 2, base_regnum
, buffer
);
1690 else if (reg_nr
>= FV0_REGNUM
1691 && reg_nr
<= FV_LAST_REGNUM
)
1693 base_regnum
= sh64_fv_reg_base_num (gdbarch
, reg_nr
);
1695 /* Build the value in the provided buffer. */
1696 /* FV regs are vectors of single precision registers obtained by
1697 concatenating 4 single precision floating point registers. */
1698 return pseudo_register_read_portions (gdbarch
, regcache
,
1699 4, base_regnum
, buffer
);
1702 /* sh compact pseudo registers. 1-to-1 with a shmedia register. */
1703 else if (reg_nr
>= R0_C_REGNUM
1704 && reg_nr
<= T_C_REGNUM
)
1706 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1708 /* Build the value in the provided buffer. */
1709 status
= regcache_raw_read (regcache
, base_regnum
, temp_buffer
);
1710 if (status
!= REG_VALID
)
1712 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1715 temp_buffer
+ offset
, 4); /* get LOWER 32 bits only???? */
1719 else if (reg_nr
>= FP0_C_REGNUM
1720 && reg_nr
<= FP_LAST_C_REGNUM
)
1722 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1724 /* Build the value in the provided buffer. */
1725 /* Floating point registers map 1-1 to the media fp regs,
1726 they have the same size and endianness. */
1727 return regcache_raw_read (regcache
, base_regnum
, buffer
);
1730 else if (reg_nr
>= DR0_C_REGNUM
1731 && reg_nr
<= DR_LAST_C_REGNUM
)
1733 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1735 /* DR_C regs are double precision registers obtained by
1736 concatenating 2 single precision floating point registers. */
1737 status
= pseudo_register_read_portions (gdbarch
, regcache
,
1738 2, base_regnum
, temp_buffer
);
1739 if (status
== REG_VALID
)
1741 /* We must pay attention to the endianness. */
1742 sh64_register_convert_to_virtual (gdbarch
, reg_nr
,
1743 register_type (gdbarch
, reg_nr
),
1744 temp_buffer
, buffer
);
1749 else if (reg_nr
>= FV0_C_REGNUM
1750 && reg_nr
<= FV_LAST_C_REGNUM
)
1752 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1754 /* Build the value in the provided buffer. */
1755 /* FV_C regs are vectors of single precision registers obtained by
1756 concatenating 4 single precision floating point registers. */
1757 return pseudo_register_read_portions (gdbarch
, regcache
,
1758 4, base_regnum
, buffer
);
1761 else if (reg_nr
== FPSCR_C_REGNUM
)
1763 int fpscr_base_regnum
;
1765 unsigned int fpscr_value
;
1766 unsigned int sr_value
;
1767 unsigned int fpscr_c_value
;
1768 unsigned int fpscr_c_part1_value
;
1769 unsigned int fpscr_c_part2_value
;
1771 fpscr_base_regnum
= FPSCR_REGNUM
;
1772 sr_base_regnum
= SR_REGNUM
;
1774 /* Build the value in the provided buffer. */
1775 /* FPSCR_C is a very weird register that contains sparse bits
1776 from the FPSCR and the SR architectural registers.
1783 2-17 Bit 2-18 of FPSCR
1784 18-20 Bits 12,13,14 of SR
1788 /* Get FPSCR into a local buffer. */
1789 status
= regcache_raw_read (regcache
, fpscr_base_regnum
, temp_buffer
);
1790 if (status
!= REG_VALID
)
1792 /* Get value as an int. */
1793 fpscr_value
= extract_unsigned_integer (temp_buffer
, 4, byte_order
);
1794 /* Get SR into a local buffer */
1795 status
= regcache_raw_read (regcache
, sr_base_regnum
, temp_buffer
);
1796 if (status
!= REG_VALID
)
1798 /* Get value as an int. */
1799 sr_value
= extract_unsigned_integer (temp_buffer
, 4, byte_order
);
1800 /* Build the new value. */
1801 fpscr_c_part1_value
= fpscr_value
& 0x3fffd;
1802 fpscr_c_part2_value
= (sr_value
& 0x7000) << 6;
1803 fpscr_c_value
= fpscr_c_part1_value
| fpscr_c_part2_value
;
1804 /* Store that in out buffer!!! */
1805 store_unsigned_integer (buffer
, 4, byte_order
, fpscr_c_value
);
1806 /* FIXME There is surely an endianness gotcha here. */
1811 else if (reg_nr
== FPUL_C_REGNUM
)
1813 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1815 /* FPUL_C register is floating point register 32,
1816 same size, same endianness. */
1817 return regcache_raw_read (regcache
, base_regnum
, buffer
);
1820 gdb_assert_not_reached ("invalid pseudo register number");
1824 sh64_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1825 int reg_nr
, const gdb_byte
*buffer
)
1827 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1828 int base_regnum
, portion
;
1830 char temp_buffer
[MAX_REGISTER_SIZE
];
1832 if (reg_nr
>= DR0_REGNUM
1833 && reg_nr
<= DR_LAST_REGNUM
)
1835 base_regnum
= sh64_dr_reg_base_num (gdbarch
, reg_nr
);
1836 /* We must pay attention to the endianness. */
1837 sh64_register_convert_to_raw (gdbarch
, register_type (gdbarch
, reg_nr
),
1839 buffer
, temp_buffer
);
1841 /* Write the real regs for which this one is an alias. */
1842 for (portion
= 0; portion
< 2; portion
++)
1843 regcache_raw_write (regcache
, base_regnum
+ portion
,
1845 + register_size (gdbarch
,
1846 base_regnum
) * portion
));
1849 else if (reg_nr
>= FPP0_REGNUM
1850 && reg_nr
<= FPP_LAST_REGNUM
)
1852 base_regnum
= sh64_fpp_reg_base_num (gdbarch
, reg_nr
);
1854 /* Write the real regs for which this one is an alias. */
1855 for (portion
= 0; portion
< 2; portion
++)
1856 regcache_raw_write (regcache
, base_regnum
+ portion
,
1858 + register_size (gdbarch
,
1859 base_regnum
) * portion
));
1862 else if (reg_nr
>= FV0_REGNUM
1863 && reg_nr
<= FV_LAST_REGNUM
)
1865 base_regnum
= sh64_fv_reg_base_num (gdbarch
, reg_nr
);
1867 /* Write the real regs for which this one is an alias. */
1868 for (portion
= 0; portion
< 4; portion
++)
1869 regcache_raw_write (regcache
, base_regnum
+ portion
,
1871 + register_size (gdbarch
,
1872 base_regnum
) * portion
));
1875 /* sh compact general pseudo registers. 1-to-1 with a shmedia
1876 register but only 4 bytes of it. */
1877 else if (reg_nr
>= R0_C_REGNUM
1878 && reg_nr
<= T_C_REGNUM
)
1880 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1881 /* reg_nr is 32 bit here, and base_regnum is 64 bits. */
1882 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1886 /* Let's read the value of the base register into a temporary
1887 buffer, so that overwriting the last four bytes with the new
1888 value of the pseudo will leave the upper 4 bytes unchanged. */
1889 regcache_raw_read (regcache
, base_regnum
, temp_buffer
);
1890 /* Write as an 8 byte quantity. */
1891 memcpy (temp_buffer
+ offset
, buffer
, 4);
1892 regcache_raw_write (regcache
, base_regnum
, temp_buffer
);
1895 /* sh floating point compact pseudo registers. 1-to-1 with a shmedia
1896 registers. Both are 4 bytes. */
1897 else if (reg_nr
>= FP0_C_REGNUM
1898 && reg_nr
<= FP_LAST_C_REGNUM
)
1900 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1901 regcache_raw_write (regcache
, base_regnum
, buffer
);
1904 else if (reg_nr
>= DR0_C_REGNUM
1905 && reg_nr
<= DR_LAST_C_REGNUM
)
1907 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1908 for (portion
= 0; portion
< 2; portion
++)
1910 /* We must pay attention to the endianness. */
1911 sh64_register_convert_to_raw (gdbarch
,
1912 register_type (gdbarch
, reg_nr
),
1914 buffer
, temp_buffer
);
1916 regcache_raw_write (regcache
, base_regnum
+ portion
,
1918 + register_size (gdbarch
,
1919 base_regnum
) * portion
));
1923 else if (reg_nr
>= FV0_C_REGNUM
1924 && reg_nr
<= FV_LAST_C_REGNUM
)
1926 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1928 for (portion
= 0; portion
< 4; portion
++)
1930 regcache_raw_write (regcache
, base_regnum
+ portion
,
1932 + register_size (gdbarch
,
1933 base_regnum
) * portion
));
1937 else if (reg_nr
== FPSCR_C_REGNUM
)
1939 int fpscr_base_regnum
;
1941 unsigned int fpscr_value
;
1942 unsigned int sr_value
;
1943 unsigned int old_fpscr_value
;
1944 unsigned int old_sr_value
;
1945 unsigned int fpscr_c_value
;
1946 unsigned int fpscr_mask
;
1947 unsigned int sr_mask
;
1949 fpscr_base_regnum
= FPSCR_REGNUM
;
1950 sr_base_regnum
= SR_REGNUM
;
1952 /* FPSCR_C is a very weird register that contains sparse bits
1953 from the FPSCR and the SR architectural registers.
1960 2-17 Bit 2-18 of FPSCR
1961 18-20 Bits 12,13,14 of SR
1965 /* Get value as an int. */
1966 fpscr_c_value
= extract_unsigned_integer (buffer
, 4, byte_order
);
1968 /* Build the new values. */
1969 fpscr_mask
= 0x0003fffd;
1970 sr_mask
= 0x001c0000;
1972 fpscr_value
= fpscr_c_value
& fpscr_mask
;
1973 sr_value
= (fpscr_value
& sr_mask
) >> 6;
1975 regcache_raw_read (regcache
, fpscr_base_regnum
, temp_buffer
);
1976 old_fpscr_value
= extract_unsigned_integer (temp_buffer
, 4, byte_order
);
1977 old_fpscr_value
&= 0xfffc0002;
1978 fpscr_value
|= old_fpscr_value
;
1979 store_unsigned_integer (temp_buffer
, 4, byte_order
, fpscr_value
);
1980 regcache_raw_write (regcache
, fpscr_base_regnum
, temp_buffer
);
1982 regcache_raw_read (regcache
, sr_base_regnum
, temp_buffer
);
1983 old_sr_value
= extract_unsigned_integer (temp_buffer
, 4, byte_order
);
1984 old_sr_value
&= 0xffff8fff;
1985 sr_value
|= old_sr_value
;
1986 store_unsigned_integer (temp_buffer
, 4, byte_order
, sr_value
);
1987 regcache_raw_write (regcache
, sr_base_regnum
, temp_buffer
);
1990 else if (reg_nr
== FPUL_C_REGNUM
)
1992 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1993 regcache_raw_write (regcache
, base_regnum
, buffer
);
1997 /* FIXME:!! THIS SHOULD TAKE CARE OF GETTING THE RIGHT PORTION OF THE
1998 shmedia REGISTERS. */
1999 /* Control registers, compact mode. */
2001 sh64_do_cr_c_register_info (struct ui_file
*file
, struct frame_info
*frame
,
2004 switch (cr_c_regnum
)
2007 fprintf_filtered (file
, "pc_c\t0x%08x\n",
2008 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
2011 fprintf_filtered (file
, "gbr_c\t0x%08x\n",
2012 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
2015 fprintf_filtered (file
, "mach_c\t0x%08x\n",
2016 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
2019 fprintf_filtered (file
, "macl_c\t0x%08x\n",
2020 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
2023 fprintf_filtered (file
, "pr_c\t0x%08x\n",
2024 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
2027 fprintf_filtered (file
, "t_c\t0x%08x\n",
2028 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
2030 case FPSCR_C_REGNUM
:
2031 fprintf_filtered (file
, "fpscr_c\t0x%08x\n",
2032 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
2035 fprintf_filtered (file
, "fpul_c\t0x%08x\n",
2036 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
2042 sh64_do_fp_register (struct gdbarch
*gdbarch
, struct ui_file
*file
,
2043 struct frame_info
*frame
, int regnum
)
2044 { /* Do values for FP (float) regs. */
2045 unsigned char *raw_buffer
;
2046 double flt
; /* Double extracted from raw hex data. */
2050 /* Allocate space for the float. */
2051 raw_buffer
= (unsigned char *)
2052 alloca (register_size (gdbarch
, gdbarch_fp0_regnum (gdbarch
)));
2054 /* Get the data in raw format. */
2055 if (!frame_register_read (frame
, regnum
, raw_buffer
))
2056 error (_("can't read register %d (%s)"),
2057 regnum
, gdbarch_register_name (gdbarch
, regnum
));
2059 /* Get the register as a number. */
2060 flt
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
2063 /* Print the name and some spaces. */
2064 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
2065 print_spaces_filtered (15 - strlen (gdbarch_register_name
2066 (gdbarch
, regnum
)), file
);
2068 /* Print the value. */
2070 fprintf_filtered (file
, "<invalid float>");
2072 fprintf_filtered (file
, "%-10.9g", flt
);
2074 /* Print the fp register as hex. */
2075 fprintf_filtered (file
, "\t(raw 0x");
2076 for (j
= 0; j
< register_size (gdbarch
, regnum
); j
++)
2078 int idx
= gdbarch_byte_order (gdbarch
)
2079 == BFD_ENDIAN_BIG
? j
: register_size
2080 (gdbarch
, regnum
) - 1 - j
;
2081 fprintf_filtered (file
, "%02x", raw_buffer
[idx
]);
2083 fprintf_filtered (file
, ")");
2084 fprintf_filtered (file
, "\n");
2088 sh64_do_pseudo_register (struct gdbarch
*gdbarch
, struct ui_file
*file
,
2089 struct frame_info
*frame
, int regnum
)
2091 /* All the sh64-compact mode registers are pseudo registers. */
2093 if (regnum
< gdbarch_num_regs (gdbarch
)
2094 || regnum
>= gdbarch_num_regs (gdbarch
)
2095 + NUM_PSEUDO_REGS_SH_MEDIA
2096 + NUM_PSEUDO_REGS_SH_COMPACT
)
2097 internal_error (__FILE__
, __LINE__
,
2098 _("Invalid pseudo register number %d\n"), regnum
);
2100 else if ((regnum
>= DR0_REGNUM
&& regnum
<= DR_LAST_REGNUM
))
2102 int fp_regnum
= sh64_dr_reg_base_num (gdbarch
, regnum
);
2103 fprintf_filtered (file
, "dr%d\t0x%08x%08x\n", regnum
- DR0_REGNUM
,
2104 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
),
2105 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 1));
2108 else if ((regnum
>= DR0_C_REGNUM
&& regnum
<= DR_LAST_C_REGNUM
))
2110 int fp_regnum
= sh64_compact_reg_base_num (gdbarch
, regnum
);
2111 fprintf_filtered (file
, "dr%d_c\t0x%08x%08x\n", regnum
- DR0_C_REGNUM
,
2112 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
),
2113 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 1));
2116 else if ((regnum
>= FV0_REGNUM
&& regnum
<= FV_LAST_REGNUM
))
2118 int fp_regnum
= sh64_fv_reg_base_num (gdbarch
, regnum
);
2119 fprintf_filtered (file
, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
2120 regnum
- FV0_REGNUM
,
2121 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
),
2122 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 1),
2123 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 2),
2124 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 3));
2127 else if ((regnum
>= FV0_C_REGNUM
&& regnum
<= FV_LAST_C_REGNUM
))
2129 int fp_regnum
= sh64_compact_reg_base_num (gdbarch
, regnum
);
2130 fprintf_filtered (file
, "fv%d_c\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
2131 regnum
- FV0_C_REGNUM
,
2132 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
),
2133 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 1),
2134 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 2),
2135 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 3));
2138 else if (regnum
>= FPP0_REGNUM
&& regnum
<= FPP_LAST_REGNUM
)
2140 int fp_regnum
= sh64_fpp_reg_base_num (gdbarch
, regnum
);
2141 fprintf_filtered (file
, "fpp%d\t0x%08x\t0x%08x\n", regnum
- FPP0_REGNUM
,
2142 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
),
2143 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 1));
2146 else if (regnum
>= R0_C_REGNUM
&& regnum
<= R_LAST_C_REGNUM
)
2148 int c_regnum
= sh64_compact_reg_base_num (gdbarch
, regnum
);
2149 fprintf_filtered (file
, "r%d_c\t0x%08x\n", regnum
- R0_C_REGNUM
,
2150 (unsigned) get_frame_register_unsigned (frame
, c_regnum
));
2152 else if (regnum
>= FP0_C_REGNUM
&& regnum
<= FP_LAST_C_REGNUM
)
2153 /* This should work also for pseudoregs. */
2154 sh64_do_fp_register (gdbarch
, file
, frame
, regnum
);
2155 else if (regnum
>= PC_C_REGNUM
&& regnum
<= FPUL_C_REGNUM
)
2156 sh64_do_cr_c_register_info (file
, frame
, regnum
);
2160 sh64_do_register (struct gdbarch
*gdbarch
, struct ui_file
*file
,
2161 struct frame_info
*frame
, int regnum
)
2163 unsigned char raw_buffer
[MAX_REGISTER_SIZE
];
2164 struct value_print_options opts
;
2166 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
2167 print_spaces_filtered (15 - strlen (gdbarch_register_name
2168 (gdbarch
, regnum
)), file
);
2170 /* Get the data in raw format. */
2171 if (!frame_register_read (frame
, regnum
, raw_buffer
))
2172 fprintf_filtered (file
, "*value not available*\n");
2174 get_formatted_print_options (&opts
, 'x');
2176 val_print (register_type (gdbarch
, regnum
), raw_buffer
, 0, 0,
2177 file
, 0, NULL
, &opts
, current_language
);
2178 fprintf_filtered (file
, "\t");
2179 get_formatted_print_options (&opts
, 0);
2181 val_print (register_type (gdbarch
, regnum
), raw_buffer
, 0, 0,
2182 file
, 0, NULL
, &opts
, current_language
);
2183 fprintf_filtered (file
, "\n");
2187 sh64_print_register (struct gdbarch
*gdbarch
, struct ui_file
*file
,
2188 struct frame_info
*frame
, int regnum
)
2190 if (regnum
< 0 || regnum
>= gdbarch_num_regs (gdbarch
)
2191 + gdbarch_num_pseudo_regs (gdbarch
))
2192 internal_error (__FILE__
, __LINE__
,
2193 _("Invalid register number %d\n"), regnum
);
2195 else if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
))
2197 if (TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
2198 sh64_do_fp_register (gdbarch
, file
, frame
, regnum
); /* FP regs */
2200 sh64_do_register (gdbarch
, file
, frame
, regnum
);
2203 else if (regnum
< gdbarch_num_regs (gdbarch
)
2204 + gdbarch_num_pseudo_regs (gdbarch
))
2205 sh64_do_pseudo_register (gdbarch
, file
, frame
, regnum
);
2209 sh64_media_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
2210 struct frame_info
*frame
, int regnum
,
2213 if (regnum
!= -1) /* Do one specified register. */
2215 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
2216 error (_("Not a valid register for the current processor type"));
2218 sh64_print_register (gdbarch
, file
, frame
, regnum
);
2221 /* Do all (or most) registers. */
2224 while (regnum
< gdbarch_num_regs (gdbarch
))
2226 /* If the register name is empty, it is undefined for this
2227 processor, so don't display anything. */
2228 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
2229 || *(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
2235 if (TYPE_CODE (register_type (gdbarch
, regnum
))
2240 /* true for "INFO ALL-REGISTERS" command. */
2241 sh64_do_fp_register (gdbarch
, file
, frame
, regnum
);
2245 regnum
+= FP_LAST_REGNUM
- gdbarch_fp0_regnum (gdbarch
);
2250 sh64_do_register (gdbarch
, file
, frame
, regnum
);
2256 while (regnum
< gdbarch_num_regs (gdbarch
)
2257 + gdbarch_num_pseudo_regs (gdbarch
))
2259 sh64_do_pseudo_register (gdbarch
, file
, frame
, regnum
);
2266 sh64_compact_print_registers_info (struct gdbarch
*gdbarch
,
2267 struct ui_file
*file
,
2268 struct frame_info
*frame
, int regnum
,
2271 if (regnum
!= -1) /* Do one specified register. */
2273 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
2274 error (_("Not a valid register for the current processor type"));
2276 if (regnum
>= 0 && regnum
< R0_C_REGNUM
)
2277 error (_("Not a valid register for the current processor mode."));
2279 sh64_print_register (gdbarch
, file
, frame
, regnum
);
2282 /* Do all compact registers. */
2284 regnum
= R0_C_REGNUM
;
2285 while (regnum
< gdbarch_num_regs (gdbarch
)
2286 + gdbarch_num_pseudo_regs (gdbarch
))
2288 sh64_do_pseudo_register (gdbarch
, file
, frame
, regnum
);
2295 sh64_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
2296 struct frame_info
*frame
, int regnum
, int fpregs
)
2298 if (pc_is_isa32 (get_frame_pc (frame
)))
2299 sh64_media_print_registers_info (gdbarch
, file
, frame
, regnum
, fpregs
);
2301 sh64_compact_print_registers_info (gdbarch
, file
, frame
, regnum
, fpregs
);
2304 static struct sh64_frame_cache
*
2305 sh64_alloc_frame_cache (void)
2307 struct sh64_frame_cache
*cache
;
2310 cache
= FRAME_OBSTACK_ZALLOC (struct sh64_frame_cache
);
2314 cache
->saved_sp
= 0;
2315 cache
->sp_offset
= 0;
2318 /* Frameless until proven otherwise. */
2321 /* Saved registers. We initialize these to -1 since zero is a valid
2322 offset (that's where fp is supposed to be stored). */
2323 for (i
= 0; i
< SIM_SH64_NR_REGS
; i
++)
2325 cache
->saved_regs
[i
] = -1;
2331 static struct sh64_frame_cache
*
2332 sh64_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2334 struct gdbarch
*gdbarch
;
2335 struct sh64_frame_cache
*cache
;
2336 CORE_ADDR current_pc
;
2342 gdbarch
= get_frame_arch (this_frame
);
2343 cache
= sh64_alloc_frame_cache ();
2344 *this_cache
= cache
;
2346 current_pc
= get_frame_pc (this_frame
);
2347 cache
->media_mode
= pc_is_isa32 (current_pc
);
2349 /* In principle, for normal frames, fp holds the frame pointer,
2350 which holds the base address for the current stack frame.
2351 However, for functions that don't need it, the frame pointer is
2352 optional. For these "frameless" functions the frame pointer is
2353 actually the frame pointer of the calling frame. */
2354 cache
->base
= get_frame_register_unsigned (this_frame
, MEDIA_FP_REGNUM
);
2355 if (cache
->base
== 0)
2358 cache
->pc
= get_frame_func (this_frame
);
2360 sh64_analyze_prologue (gdbarch
, cache
, cache
->pc
, current_pc
);
2362 if (!cache
->uses_fp
)
2364 /* We didn't find a valid frame, which means that CACHE->base
2365 currently holds the frame pointer for our calling frame. If
2366 we're at the start of a function, or somewhere half-way its
2367 prologue, the function's frame probably hasn't been fully
2368 setup yet. Try to reconstruct the base address for the stack
2369 frame by looking at the stack pointer. For truly "frameless"
2370 functions this might work too. */
2371 cache
->base
= get_frame_register_unsigned
2372 (this_frame
, gdbarch_sp_regnum (gdbarch
));
2375 /* Now that we have the base address for the stack frame we can
2376 calculate the value of sp in the calling frame. */
2377 cache
->saved_sp
= cache
->base
+ cache
->sp_offset
;
2379 /* Adjust all the saved registers such that they contain addresses
2380 instead of offsets. */
2381 for (i
= 0; i
< SIM_SH64_NR_REGS
; i
++)
2382 if (cache
->saved_regs
[i
] != -1)
2383 cache
->saved_regs
[i
] = cache
->saved_sp
- cache
->saved_regs
[i
];
2388 static struct value
*
2389 sh64_frame_prev_register (struct frame_info
*this_frame
,
2390 void **this_cache
, int regnum
)
2392 struct sh64_frame_cache
*cache
= sh64_frame_cache (this_frame
, this_cache
);
2393 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2394 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2396 gdb_assert (regnum
>= 0);
2398 if (regnum
== gdbarch_sp_regnum (gdbarch
) && cache
->saved_sp
)
2399 frame_unwind_got_constant (this_frame
, regnum
, cache
->saved_sp
);
2401 /* The PC of the previous frame is stored in the PR register of
2402 the current frame. Frob regnum so that we pull the value from
2403 the correct place. */
2404 if (regnum
== gdbarch_pc_regnum (gdbarch
))
2407 if (regnum
< SIM_SH64_NR_REGS
&& cache
->saved_regs
[regnum
] != -1)
2409 if (gdbarch_tdep (gdbarch
)->sh_abi
== SH_ABI_32
2410 && (regnum
== MEDIA_FP_REGNUM
|| regnum
== PR_REGNUM
))
2413 val
= read_memory_unsigned_integer (cache
->saved_regs
[regnum
],
2415 return frame_unwind_got_constant (this_frame
, regnum
, val
);
2418 return frame_unwind_got_memory (this_frame
, regnum
,
2419 cache
->saved_regs
[regnum
]);
2422 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
2426 sh64_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2427 struct frame_id
*this_id
)
2429 struct sh64_frame_cache
*cache
= sh64_frame_cache (this_frame
, this_cache
);
2431 /* This marks the outermost frame. */
2432 if (cache
->base
== 0)
2435 *this_id
= frame_id_build (cache
->saved_sp
, cache
->pc
);
2438 static const struct frame_unwind sh64_frame_unwind
= {
2440 default_frame_unwind_stop_reason
,
2442 sh64_frame_prev_register
,
2444 default_frame_sniffer
2448 sh64_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2450 return frame_unwind_register_unsigned (next_frame
,
2451 gdbarch_sp_regnum (gdbarch
));
2455 sh64_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2457 return frame_unwind_register_unsigned (next_frame
,
2458 gdbarch_pc_regnum (gdbarch
));
2461 static struct frame_id
2462 sh64_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2464 CORE_ADDR sp
= get_frame_register_unsigned (this_frame
,
2465 gdbarch_sp_regnum (gdbarch
));
2466 return frame_id_build (sp
, get_frame_pc (this_frame
));
2470 sh64_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2472 struct sh64_frame_cache
*cache
= sh64_frame_cache (this_frame
, this_cache
);
2477 static const struct frame_base sh64_frame_base
= {
2479 sh64_frame_base_address
,
2480 sh64_frame_base_address
,
2481 sh64_frame_base_address
2486 sh64_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2488 struct gdbarch
*gdbarch
;
2489 struct gdbarch_tdep
*tdep
;
2491 /* If there is already a candidate, use it. */
2492 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2494 return arches
->gdbarch
;
2496 /* None found, create a new architecture from the information
2498 tdep
= XMALLOC (struct gdbarch_tdep
);
2499 gdbarch
= gdbarch_alloc (&info
, tdep
);
2501 /* Determine the ABI */
2502 if (info
.abfd
&& bfd_get_arch_size (info
.abfd
) == 64)
2504 /* If the ABI is the 64-bit one, it can only be sh-media. */
2505 tdep
->sh_abi
= SH_ABI_64
;
2506 set_gdbarch_ptr_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2507 set_gdbarch_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2511 /* If the ABI is the 32-bit one it could be either media or
2513 tdep
->sh_abi
= SH_ABI_32
;
2514 set_gdbarch_ptr_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2515 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2518 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
2519 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2520 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2521 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2522 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2523 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2524 set_gdbarch_long_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2526 /* The number of real registers is the same whether we are in
2527 ISA16(compact) or ISA32(media). */
2528 set_gdbarch_num_regs (gdbarch
, SIM_SH64_NR_REGS
);
2529 set_gdbarch_sp_regnum (gdbarch
, 15);
2530 set_gdbarch_pc_regnum (gdbarch
, 64);
2531 set_gdbarch_fp0_regnum (gdbarch
, SIM_SH64_FR0_REGNUM
);
2532 set_gdbarch_num_pseudo_regs (gdbarch
, NUM_PSEUDO_REGS_SH_MEDIA
2533 + NUM_PSEUDO_REGS_SH_COMPACT
);
2535 set_gdbarch_register_name (gdbarch
, sh64_register_name
);
2536 set_gdbarch_register_type (gdbarch
, sh64_register_type
);
2538 set_gdbarch_pseudo_register_read (gdbarch
, sh64_pseudo_register_read
);
2539 set_gdbarch_pseudo_register_write (gdbarch
, sh64_pseudo_register_write
);
2541 set_gdbarch_breakpoint_from_pc (gdbarch
, sh64_breakpoint_from_pc
);
2543 set_gdbarch_print_insn (gdbarch
, print_insn_sh
);
2544 set_gdbarch_register_sim_regno (gdbarch
, legacy_register_sim_regno
);
2546 set_gdbarch_return_value (gdbarch
, sh64_return_value
);
2548 set_gdbarch_skip_prologue (gdbarch
, sh64_skip_prologue
);
2549 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2551 set_gdbarch_push_dummy_call (gdbarch
, sh64_push_dummy_call
);
2553 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
2555 set_gdbarch_frame_align (gdbarch
, sh64_frame_align
);
2556 set_gdbarch_unwind_sp (gdbarch
, sh64_unwind_sp
);
2557 set_gdbarch_unwind_pc (gdbarch
, sh64_unwind_pc
);
2558 set_gdbarch_dummy_id (gdbarch
, sh64_dummy_id
);
2559 frame_base_set_default (gdbarch
, &sh64_frame_base
);
2561 set_gdbarch_print_registers_info (gdbarch
, sh64_print_registers_info
);
2563 set_gdbarch_elf_make_msymbol_special (gdbarch
,
2564 sh64_elf_make_msymbol_special
);
2566 /* Hook in ABI-specific overrides, if they have been registered. */
2567 gdbarch_init_osabi (info
, gdbarch
);
2569 dwarf2_append_unwinders (gdbarch
);
2570 frame_unwind_append_unwinder (gdbarch
, &sh64_frame_unwind
);