1 /* Target-dependent code for Renesas Super-H, for GDB.
3 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
4 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 Contributed by Steve Chamberlain
28 #include "frame-base.h"
29 #include "frame-unwind.h"
30 #include "dwarf2-frame.h"
38 #include "gdb_string.h"
39 #include "gdb_assert.h"
40 #include "arch-utils.h"
48 /* registers numbers shared with the simulator */
49 #include "gdb/sim-sh.h"
51 /* Information that is dependent on the processor variant. */
64 struct sh64_frame_cache
71 /* Flag showing that a frame has been created in the prologue code. */
76 /* Saved registers. */
77 CORE_ADDR saved_regs
[SIM_SH64_NR_REGS
];
81 /* Registers of SH5 */
85 DEFAULT_RETURN_REGNUM
= 2,
86 STRUCT_RETURN_REGNUM
= 2,
89 FLOAT_ARGLAST_REGNUM
= 11,
95 /* FPP stands for Floating Point Pair, to avoid confusion with
96 GDB's gdbarch_fp0_regnum, which is the number of the first Floating
97 point register. Unfortunately on the sh5, the floating point
98 registers are called FR, and the floating point pairs are called FP. */
100 FPP_LAST_REGNUM
= 204,
102 FV_LAST_REGNUM
= 220,
104 R_LAST_C_REGNUM
= 236,
111 FPSCR_C_REGNUM
= 243,
114 FP_LAST_C_REGNUM
= 260,
116 DR_LAST_C_REGNUM
= 268,
118 FV_LAST_C_REGNUM
= 272,
119 FPSCR_REGNUM
= SIM_SH64_FPCSR_REGNUM
,
120 SSR_REGNUM
= SIM_SH64_SSR_REGNUM
,
121 SPC_REGNUM
= SIM_SH64_SPC_REGNUM
,
122 TR7_REGNUM
= SIM_SH64_TR0_REGNUM
+ 7,
123 FP_LAST_REGNUM
= SIM_SH64_FR0_REGNUM
+ SIM_SH64_NR_FP_REGS
- 1
127 sh64_register_name (int reg_nr
)
129 static char *register_names
[] =
131 /* SH MEDIA MODE (ISA 32) */
132 /* general registers (64-bit) 0-63 */
133 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
134 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
135 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
136 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
137 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
138 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
139 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
140 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
145 /* status reg., saved status reg., saved pc reg. (64-bit) 65-67 */
148 /* target registers (64-bit) 68-75*/
149 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7",
151 /* floating point state control register (32-bit) 76 */
154 /* single precision floating point registers (32-bit) 77-140*/
155 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
156 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
157 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
158 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31",
159 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39",
160 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47",
161 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55",
162 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63",
164 /* double precision registers (pseudo) 141-172 */
165 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
166 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30",
167 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46",
168 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62",
170 /* floating point pairs (pseudo) 173-204*/
171 "fp0", "fp2", "fp4", "fp6", "fp8", "fp10", "fp12", "fp14",
172 "fp16", "fp18", "fp20", "fp22", "fp24", "fp26", "fp28", "fp30",
173 "fp32", "fp34", "fp36", "fp38", "fp40", "fp42", "fp44", "fp46",
174 "fp48", "fp50", "fp52", "fp54", "fp56", "fp58", "fp60", "fp62",
176 /* floating point vectors (4 floating point regs) (pseudo) 205-220*/
177 "fv0", "fv4", "fv8", "fv12", "fv16", "fv20", "fv24", "fv28",
178 "fv32", "fv36", "fv40", "fv44", "fv48", "fv52", "fv56", "fv60",
180 /* SH COMPACT MODE (ISA 16) (all pseudo) 221-272*/
181 "r0_c", "r1_c", "r2_c", "r3_c", "r4_c", "r5_c", "r6_c", "r7_c",
182 "r8_c", "r9_c", "r10_c", "r11_c", "r12_c", "r13_c", "r14_c", "r15_c",
184 "gbr_c", "mach_c", "macl_c", "pr_c", "t_c",
186 "fr0_c", "fr1_c", "fr2_c", "fr3_c", "fr4_c", "fr5_c", "fr6_c", "fr7_c",
187 "fr8_c", "fr9_c", "fr10_c", "fr11_c", "fr12_c", "fr13_c", "fr14_c", "fr15_c",
188 "dr0_c", "dr2_c", "dr4_c", "dr6_c", "dr8_c", "dr10_c", "dr12_c", "dr14_c",
189 "fv0_c", "fv4_c", "fv8_c", "fv12_c",
190 /* FIXME!!!! XF0 XF15, XD0 XD14 ?????*/
195 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
197 return register_names
[reg_nr
];
200 #define NUM_PSEUDO_REGS_SH_MEDIA 80
201 #define NUM_PSEUDO_REGS_SH_COMPACT 51
203 /* Macros and functions for setting and testing a bit in a minimal
204 symbol that marks it as 32-bit function. The MSB of the minimal
205 symbol's "info" field is used for this purpose.
207 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
208 i.e. refers to a 32-bit function, and sets a "special" bit in a
209 minimal symbol to mark it as a 32-bit function
210 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
212 #define MSYMBOL_IS_SPECIAL(msym) \
213 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
216 sh64_elf_make_msymbol_special (asymbol
*sym
, struct minimal_symbol
*msym
)
221 if (((elf_symbol_type
*)(sym
))->internal_elf_sym
.st_other
== STO_SH5_ISA32
)
223 MSYMBOL_INFO (msym
) = (char *) (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
224 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
228 /* ISA32 (shmedia) function addresses are odd (bit 0 is set). Here
229 are some macros to test, set, or clear bit 0 of addresses. */
230 #define IS_ISA32_ADDR(addr) ((addr) & 1)
231 #define MAKE_ISA32_ADDR(addr) ((addr) | 1)
232 #define UNMAKE_ISA32_ADDR(addr) ((addr) & ~1)
235 pc_is_isa32 (bfd_vma memaddr
)
237 struct minimal_symbol
*sym
;
239 /* If bit 0 of the address is set, assume this is a
240 ISA32 (shmedia) address. */
241 if (IS_ISA32_ADDR (memaddr
))
244 /* A flag indicating that this is a ISA32 function is stored by elfread.c in
245 the high bit of the info field. Use this to decide if the function is
247 sym
= lookup_minimal_symbol_by_pc (memaddr
);
249 return MSYMBOL_IS_SPECIAL (sym
);
254 static const unsigned char *
255 sh64_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
257 /* The BRK instruction for shmedia is
258 01101111 11110101 11111111 11110000
259 which translates in big endian mode to 0x6f, 0xf5, 0xff, 0xf0
260 and in little endian mode to 0xf0, 0xff, 0xf5, 0x6f */
262 /* The BRK instruction for shcompact is
264 which translates in big endian mode to 0x0, 0x3b
265 and in little endian mode to 0x3b, 0x0*/
267 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
269 if (pc_is_isa32 (*pcptr
))
271 static unsigned char big_breakpoint_media
[] = {0x6f, 0xf5, 0xff, 0xf0};
272 *pcptr
= UNMAKE_ISA32_ADDR (*pcptr
);
273 *lenptr
= sizeof (big_breakpoint_media
);
274 return big_breakpoint_media
;
278 static unsigned char big_breakpoint_compact
[] = {0x0, 0x3b};
279 *lenptr
= sizeof (big_breakpoint_compact
);
280 return big_breakpoint_compact
;
285 if (pc_is_isa32 (*pcptr
))
287 static unsigned char little_breakpoint_media
[] = {0xf0, 0xff, 0xf5, 0x6f};
288 *pcptr
= UNMAKE_ISA32_ADDR (*pcptr
);
289 *lenptr
= sizeof (little_breakpoint_media
);
290 return little_breakpoint_media
;
294 static unsigned char little_breakpoint_compact
[] = {0x3b, 0x0};
295 *lenptr
= sizeof (little_breakpoint_compact
);
296 return little_breakpoint_compact
;
301 /* Prologue looks like
302 [mov.l <regs>,@-r15]...
307 Actually it can be more complicated than this. For instance, with
325 /* PTABS/L Rn, TRa 0110101111110001nnnnnnl00aaa0000
326 with l=1 and n = 18 0110101111110001010010100aaa0000 */
327 #define IS_PTABSL_R18(x) (((x) & 0xffffff8f) == 0x6bf14a00)
329 /* STS.L PR,@-r0 0100000000100010
330 r0-4-->r0, PR-->(r0) */
331 #define IS_STS_R0(x) ((x) == 0x4022)
333 /* STS PR, Rm 0000mmmm00101010
335 #define IS_STS_PR(x) (((x) & 0xf0ff) == 0x2a)
337 /* MOV.L Rm,@(disp,r15) 00011111mmmmdddd
339 #define IS_MOV_TO_R15(x) (((x) & 0xff00) == 0x1f00)
341 /* MOV.L R14,@(disp,r15) 000111111110dddd
342 R14-->(dispx4+r15) */
343 #define IS_MOV_R14(x) (((x) & 0xfff0) == 0x1fe0)
345 /* ST.Q R14, disp, R18 101011001110dddddddddd0100100000
346 R18-->(dispx8+R14) */
347 #define IS_STQ_R18_R14(x) (((x) & 0xfff003ff) == 0xace00120)
349 /* ST.Q R15, disp, R18 101011001111dddddddddd0100100000
350 R18-->(dispx8+R15) */
351 #define IS_STQ_R18_R15(x) (((x) & 0xfff003ff) == 0xacf00120)
353 /* ST.L R15, disp, R18 101010001111dddddddddd0100100000
354 R18-->(dispx4+R15) */
355 #define IS_STL_R18_R15(x) (((x) & 0xfff003ff) == 0xa8f00120)
357 /* ST.Q R15, disp, R14 1010 1100 1111 dddd dddd dd00 1110 0000
358 R14-->(dispx8+R15) */
359 #define IS_STQ_R14_R15(x) (((x) & 0xfff003ff) == 0xacf000e0)
361 /* ST.L R15, disp, R14 1010 1000 1111 dddd dddd dd00 1110 0000
362 R14-->(dispx4+R15) */
363 #define IS_STL_R14_R15(x) (((x) & 0xfff003ff) == 0xa8f000e0)
365 /* ADDI.L R15,imm,R15 1101 0100 1111 ssss ssss ss00 1111 0000
367 #define IS_ADDIL_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd4f000f0)
369 /* ADDI R15,imm,R15 1101 0000 1111 ssss ssss ss00 1111 0000
371 #define IS_ADDI_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd0f000f0)
373 /* ADD.L R15,R63,R14 0000 0000 1111 1000 1111 1100 1110 0000
375 #define IS_ADDL_SP_FP_MEDIA(x) ((x) == 0x00f8fce0)
377 /* ADD R15,R63,R14 0000 0000 1111 1001 1111 1100 1110 0000
379 #define IS_ADD_SP_FP_MEDIA(x) ((x) == 0x00f9fce0)
381 #define IS_MOV_SP_FP_MEDIA(x) (IS_ADDL_SP_FP_MEDIA(x) || IS_ADD_SP_FP_MEDIA(x))
383 /* MOV #imm, R0 1110 0000 ssss ssss
385 #define IS_MOV_R0(x) (((x) & 0xff00) == 0xe000)
387 /* MOV.L @(disp,PC), R0 1101 0000 iiii iiii */
388 #define IS_MOVL_R0(x) (((x) & 0xff00) == 0xd000)
390 /* ADD r15,r0 0011 0000 1111 1100
392 #define IS_ADD_SP_R0(x) ((x) == 0x30fc)
394 /* MOV.L R14 @-R0 0010 0000 1110 0110
395 R14-->(R0-4), R0-4-->R0 */
396 #define IS_MOV_R14_R0(x) ((x) == 0x20e6)
398 /* ADD Rm,R63,Rn Rm+R63-->Rn 0000 00mm mmmm 1001 1111 11nn nnnn 0000
399 where Rm is one of r2-r9 which are the argument registers. */
400 /* FIXME: Recognize the float and double register moves too! */
401 #define IS_MEDIA_IND_ARG_MOV(x) \
402 ((((x) & 0xfc0ffc0f) == 0x0009fc00) && (((x) & 0x03f00000) >= 0x00200000 && ((x) & 0x03f00000) <= 0x00900000))
404 /* ST.Q Rn,0,Rm Rm-->Rn+0 1010 11nn nnnn 0000 0000 00mm mmmm 0000
405 or ST.L Rn,0,Rm Rm-->Rn+0 1010 10nn nnnn 0000 0000 00mm mmmm 0000
406 where Rm is one of r2-r9 which are the argument registers. */
407 #define IS_MEDIA_ARG_MOV(x) \
408 (((((x) & 0xfc0ffc0f) == 0xac000000) || (((x) & 0xfc0ffc0f) == 0xa8000000)) \
409 && (((x) & 0x000003f0) >= 0x00000020 && ((x) & 0x000003f0) <= 0x00000090))
411 /* ST.B R14,0,Rn Rn-->(R14+0) 1010 0000 1110 0000 0000 00nn nnnn 0000*/
412 /* ST.W R14,0,Rn Rn-->(R14+0) 1010 0100 1110 0000 0000 00nn nnnn 0000*/
413 /* ST.L R14,0,Rn Rn-->(R14+0) 1010 1000 1110 0000 0000 00nn nnnn 0000*/
414 /* FST.S R14,0,FRn Rn-->(R14+0) 1011 0100 1110 0000 0000 00nn nnnn 0000*/
415 /* FST.D R14,0,DRn Rn-->(R14+0) 1011 1100 1110 0000 0000 00nn nnnn 0000*/
416 #define IS_MEDIA_MOV_TO_R14(x) \
417 ((((x) & 0xfffffc0f) == 0xa0e00000) \
418 || (((x) & 0xfffffc0f) == 0xa4e00000) \
419 || (((x) & 0xfffffc0f) == 0xa8e00000) \
420 || (((x) & 0xfffffc0f) == 0xb4e00000) \
421 || (((x) & 0xfffffc0f) == 0xbce00000))
423 /* MOV Rm, Rn Rm-->Rn 0110 nnnn mmmm 0011
425 #define IS_COMPACT_IND_ARG_MOV(x) \
426 ((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0020) && (((x) & 0x00f0) <= 0x0090))
428 /* compact direct arg move!
429 MOV.L Rn, @r14 0010 1110 mmmm 0010 */
430 #define IS_COMPACT_ARG_MOV(x) \
431 (((((x) & 0xff0f) == 0x2e02) && (((x) & 0x00f0) >= 0x0020) && ((x) & 0x00f0) <= 0x0090))
433 /* MOV.B Rm, @R14 0010 1110 mmmm 0000
434 MOV.W Rm, @R14 0010 1110 mmmm 0001 */
435 #define IS_COMPACT_MOV_TO_R14(x) \
436 ((((x) & 0xff0f) == 0x2e00) || (((x) & 0xff0f) == 0x2e01))
438 #define IS_JSR_R0(x) ((x) == 0x400b)
439 #define IS_NOP(x) ((x) == 0x0009)
442 /* MOV r15,r14 0110111011110011
444 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
446 /* ADD #imm,r15 01111111iiiiiiii
448 #define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00)
450 /* Skip any prologue before the guts of a function */
452 /* Skip the prologue using the debug information. If this fails we'll
453 fall back on the 'guess' method below. */
455 after_prologue (CORE_ADDR pc
)
457 struct symtab_and_line sal
;
458 CORE_ADDR func_addr
, func_end
;
460 /* If we can not find the symbol in the partial symbol table, then
461 there is no hope we can determine the function's start address
463 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
467 /* Get the line associated with FUNC_ADDR. */
468 sal
= find_pc_line (func_addr
, 0);
470 /* There are only two cases to consider. First, the end of the source line
471 is within the function bounds. In that case we return the end of the
472 source line. Second is the end of the source line extends beyond the
473 bounds of the current function. We need to use the slow code to
474 examine instructions in that case. */
475 if (sal
.end
< func_end
)
482 look_for_args_moves (CORE_ADDR start_pc
, int media_mode
)
486 int insn_size
= (media_mode
? 4 : 2);
488 for (here
= start_pc
, end
= start_pc
+ (insn_size
* 28); here
< end
;)
492 w
= read_memory_integer (UNMAKE_ISA32_ADDR (here
), insn_size
);
494 if (IS_MEDIA_IND_ARG_MOV (w
))
496 /* This must be followed by a store to r14, so the argument
497 is where the debug info says it is. This can happen after
498 the SP has been saved, unfortunately. */
500 int next_insn
= read_memory_integer (UNMAKE_ISA32_ADDR (here
),
503 if (IS_MEDIA_MOV_TO_R14 (next_insn
))
506 else if (IS_MEDIA_ARG_MOV (w
))
508 /* These instructions store directly the argument in r14. */
516 w
= read_memory_integer (here
, insn_size
);
519 if (IS_COMPACT_IND_ARG_MOV (w
))
521 /* This must be followed by a store to r14, so the argument
522 is where the debug info says it is. This can happen after
523 the SP has been saved, unfortunately. */
525 int next_insn
= 0xffff & read_memory_integer (here
, insn_size
);
527 if (IS_COMPACT_MOV_TO_R14 (next_insn
))
530 else if (IS_COMPACT_ARG_MOV (w
))
532 /* These instructions store directly the argument in r14. */
535 else if (IS_MOVL_R0 (w
))
537 /* There is a function that gcc calls to get the arguments
538 passed correctly to the function. Only after this
539 function call the arguments will be found at the place
540 where they are supposed to be. This happens in case the
541 argument has to be stored into a 64-bit register (for
542 instance doubles, long longs). SHcompact doesn't have
543 access to the full 64-bits, so we store the register in
544 stack slot and store the address of the stack slot in
545 the register, then do a call through a wrapper that
546 loads the memory value into the register. A SHcompact
547 callee calls an argument decoder
548 (GCC_shcompact_incoming_args) that stores the 64-bit
549 value in a stack slot and stores the address of the
550 stack slot in the register. GCC thinks the argument is
551 just passed by transparent reference, but this is only
552 true after the argument decoder is called. Such a call
553 needs to be considered part of the prologue. */
555 /* This must be followed by a JSR @r0 instruction and by
556 a NOP instruction. After these, the prologue is over! */
558 int next_insn
= 0xffff & read_memory_integer (here
, insn_size
);
560 if (IS_JSR_R0 (next_insn
))
562 next_insn
= 0xffff & read_memory_integer (here
, insn_size
);
565 if (IS_NOP (next_insn
))
578 sh64_skip_prologue_hard_way (CORE_ADDR start_pc
)
588 if (pc_is_isa32 (start_pc
) == 0)
594 for (here
= start_pc
, end
= start_pc
+ (insn_size
* 28); here
< end
;)
599 int w
= read_memory_integer (UNMAKE_ISA32_ADDR (here
), insn_size
);
601 if (IS_STQ_R18_R14 (w
) || IS_STQ_R18_R15 (w
) || IS_STQ_R14_R15 (w
)
602 || IS_STL_R14_R15 (w
) || IS_STL_R18_R15 (w
)
603 || IS_ADDIL_SP_MEDIA (w
) || IS_ADDI_SP_MEDIA (w
) || IS_PTABSL_R18 (w
))
607 else if (IS_MOV_SP_FP (w
) || IS_MOV_SP_FP_MEDIA(w
))
615 /* Don't bail out yet, we may have arguments stored in
616 registers here, according to the debug info, so that
617 gdb can print the frames correctly. */
618 start_pc
= look_for_args_moves (here
- insn_size
, media_mode
);
624 int w
= 0xffff & read_memory_integer (here
, insn_size
);
627 if (IS_STS_R0 (w
) || IS_STS_PR (w
)
628 || IS_MOV_TO_R15 (w
) || IS_MOV_R14 (w
)
629 || IS_MOV_R0 (w
) || IS_ADD_SP_R0 (w
) || IS_MOV_R14_R0 (w
))
633 else if (IS_MOV_SP_FP (w
))
641 /* Don't bail out yet, we may have arguments stored in
642 registers here, according to the debug info, so that
643 gdb can print the frames correctly. */
644 start_pc
= look_for_args_moves (here
- insn_size
, media_mode
);
654 sh64_skip_prologue (CORE_ADDR pc
)
656 CORE_ADDR post_prologue_pc
;
658 /* See if we can determine the end of the prologue via the symbol table.
659 If so, then return either PC, or the PC after the prologue, whichever
661 post_prologue_pc
= after_prologue (pc
);
663 /* If after_prologue returned a useful address, then use it. Else
664 fall back on the instruction skipping code. */
665 if (post_prologue_pc
!= 0)
666 return max (pc
, post_prologue_pc
);
668 return sh64_skip_prologue_hard_way (pc
);
671 /* Should call_function allocate stack space for a struct return? */
673 sh64_use_struct_convention (struct type
*type
)
675 return (TYPE_LENGTH (type
) > 8);
678 /* Disassemble an instruction. */
680 gdb_print_insn_sh64 (bfd_vma memaddr
, disassemble_info
*info
)
682 info
->endian
= gdbarch_byte_order (current_gdbarch
);
683 return print_insn_sh (memaddr
, info
);
686 /* For vectors of 4 floating point registers. */
688 sh64_fv_reg_base_num (int fv_regnum
)
692 fp_regnum
= gdbarch_fp0_regnum (current_gdbarch
) +
693 (fv_regnum
- FV0_REGNUM
) * 4;
697 /* For double precision floating point registers, i.e 2 fp regs.*/
699 sh64_dr_reg_base_num (int dr_regnum
)
703 fp_regnum
= gdbarch_fp0_regnum (current_gdbarch
) +
704 (dr_regnum
- DR0_REGNUM
) * 2;
708 /* For pairs of floating point registers */
710 sh64_fpp_reg_base_num (int fpp_regnum
)
714 fp_regnum
= gdbarch_fp0_regnum (current_gdbarch
) +
715 (fpp_regnum
- FPP0_REGNUM
) * 2;
721 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
722 GDB_REGNUM BASE_REGNUM
782 sh64_compact_reg_base_num (int reg_nr
)
784 int base_regnum
= reg_nr
;
786 /* general register N maps to general register N */
787 if (reg_nr
>= R0_C_REGNUM
788 && reg_nr
<= R_LAST_C_REGNUM
)
789 base_regnum
= reg_nr
- R0_C_REGNUM
;
791 /* floating point register N maps to floating point register N */
792 else if (reg_nr
>= FP0_C_REGNUM
793 && reg_nr
<= FP_LAST_C_REGNUM
)
794 base_regnum
= reg_nr
- FP0_C_REGNUM
+ gdbarch_fp0_regnum (current_gdbarch
);
796 /* double prec register N maps to base regnum for double prec register N */
797 else if (reg_nr
>= DR0_C_REGNUM
798 && reg_nr
<= DR_LAST_C_REGNUM
)
799 base_regnum
= sh64_dr_reg_base_num (DR0_REGNUM
+ reg_nr
- DR0_C_REGNUM
);
801 /* vector N maps to base regnum for vector register N */
802 else if (reg_nr
>= FV0_C_REGNUM
803 && reg_nr
<= FV_LAST_C_REGNUM
)
804 base_regnum
= sh64_fv_reg_base_num (FV0_REGNUM
+ reg_nr
- FV0_C_REGNUM
);
806 else if (reg_nr
== PC_C_REGNUM
)
807 base_regnum
= gdbarch_pc_regnum (current_gdbarch
);
809 else if (reg_nr
== GBR_C_REGNUM
)
812 else if (reg_nr
== MACH_C_REGNUM
813 || reg_nr
== MACL_C_REGNUM
)
816 else if (reg_nr
== PR_C_REGNUM
)
817 base_regnum
= PR_REGNUM
;
819 else if (reg_nr
== T_C_REGNUM
)
822 else if (reg_nr
== FPSCR_C_REGNUM
)
823 base_regnum
= FPSCR_REGNUM
; /*???? this register is a mess. */
825 else if (reg_nr
== FPUL_C_REGNUM
)
826 base_regnum
= gdbarch_fp0_regnum (current_gdbarch
) + 32;
832 sign_extend (int value
, int bits
)
834 value
= value
& ((1 << bits
) - 1);
835 return (value
& (1 << (bits
- 1))
836 ? value
| (~((1 << bits
) - 1))
841 sh64_analyze_prologue (struct gdbarch
*gdbarch
,
842 struct sh64_frame_cache
*cache
,
844 CORE_ADDR current_pc
)
852 int gdb_register_number
;
854 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
856 cache
->sp_offset
= 0;
858 /* Loop around examining the prologue insns until we find something
859 that does not appear to be part of the prologue. But give up
860 after 20 of them, since we're getting silly then. */
864 if (cache
->media_mode
)
869 opc
= pc
+ (insn_size
* 28);
870 if (opc
> current_pc
)
872 for ( ; pc
<= opc
; pc
+= insn_size
)
874 insn
= read_memory_integer (cache
->media_mode
? UNMAKE_ISA32_ADDR (pc
)
878 if (!cache
->media_mode
)
880 if (IS_STS_PR (insn
))
882 int next_insn
= read_memory_integer (pc
+ insn_size
, insn_size
);
883 if (IS_MOV_TO_R15 (next_insn
))
885 cache
->saved_regs
[PR_REGNUM
] =
886 cache
->sp_offset
- ((((next_insn
& 0xf) ^ 0x8) - 0x8) << 2);
891 else if (IS_MOV_R14 (insn
))
892 cache
->saved_regs
[MEDIA_FP_REGNUM
] =
893 cache
->sp_offset
- ((((insn
& 0xf) ^ 0x8) - 0x8) << 2);
895 else if (IS_MOV_R0 (insn
))
897 /* Put in R0 the offset from SP at which to store some
898 registers. We are interested in this value, because it
899 will tell us where the given registers are stored within
901 r0_val
= ((insn
& 0xff) ^ 0x80) - 0x80;
904 else if (IS_ADD_SP_R0 (insn
))
906 /* This instruction still prepares r0, but we don't care.
907 We already have the offset in r0_val. */
910 else if (IS_STS_R0 (insn
))
912 /* Store PR at r0_val-4 from SP. Decrement r0 by 4*/
913 cache
->saved_regs
[PR_REGNUM
] = cache
->sp_offset
- (r0_val
- 4);
917 else if (IS_MOV_R14_R0 (insn
))
919 /* Store R14 at r0_val-4 from SP. Decrement r0 by 4 */
920 cache
->saved_regs
[MEDIA_FP_REGNUM
] = cache
->sp_offset
925 else if (IS_ADD_SP (insn
))
926 cache
->sp_offset
-= ((insn
& 0xff) ^ 0x80) - 0x80;
928 else if (IS_MOV_SP_FP (insn
))
933 if (IS_ADDIL_SP_MEDIA (insn
) || IS_ADDI_SP_MEDIA (insn
))
935 sign_extend ((((insn
& 0xffc00) ^ 0x80000) - 0x80000) >> 10, 9);
937 else if (IS_STQ_R18_R15 (insn
))
938 cache
->saved_regs
[PR_REGNUM
] =
939 cache
->sp_offset
- (sign_extend ((insn
& 0xffc00) >> 10, 9) << 3);
941 else if (IS_STL_R18_R15 (insn
))
942 cache
->saved_regs
[PR_REGNUM
] =
943 cache
->sp_offset
- (sign_extend ((insn
& 0xffc00) >> 10, 9) << 2);
945 else if (IS_STQ_R14_R15 (insn
))
946 cache
->saved_regs
[MEDIA_FP_REGNUM
] =
947 cache
->sp_offset
- (sign_extend ((insn
& 0xffc00) >> 10, 9) << 3);
949 else if (IS_STL_R14_R15 (insn
))
950 cache
->saved_regs
[MEDIA_FP_REGNUM
] =
951 cache
->sp_offset
- (sign_extend ((insn
& 0xffc00) >> 10, 9) << 2);
953 else if (IS_MOV_SP_FP_MEDIA (insn
))
958 if (cache
->saved_regs
[MEDIA_FP_REGNUM
] >= 0)
963 sh64_frame_align (struct gdbarch
*ignore
, CORE_ADDR sp
)
968 /* Function: push_dummy_call
969 Setup the function arguments for calling a function in the inferior.
971 On the Renesas SH architecture, there are four registers (R4 to R7)
972 which are dedicated for passing function arguments. Up to the first
973 four arguments (depending on size) may go into these registers.
974 The rest go on the stack.
976 Arguments that are smaller than 4 bytes will still take up a whole
977 register or a whole 32-bit word on the stack, and will be
978 right-justified in the register or the stack word. This includes
979 chars, shorts, and small aggregate types.
981 Arguments that are larger than 4 bytes may be split between two or
982 more registers. If there are not enough registers free, an argument
983 may be passed partly in a register (or registers), and partly on the
984 stack. This includes doubles, long longs, and larger aggregates.
985 As far as I know, there is no upper limit to the size of aggregates
986 that will be passed in this way; in other words, the convention of
987 passing a pointer to a large aggregate instead of a copy is not used.
989 An exceptional case exists for struct arguments (and possibly other
990 aggregates such as arrays) if the size is larger than 4 bytes but
991 not a multiple of 4 bytes. In this case the argument is never split
992 between the registers and the stack, but instead is copied in its
993 entirety onto the stack, AND also copied into as many registers as
994 there is room for. In other words, space in registers permitting,
995 two copies of the same argument are passed in. As far as I can tell,
996 only the one on the stack is used, although that may be a function
997 of the level of compiler optimization. I suspect this is a compiler
998 bug. Arguments of these odd sizes are left-justified within the
999 word (as opposed to arguments smaller than 4 bytes, which are
1002 If the function is to return an aggregate type such as a struct, it
1003 is either returned in the normal return value register R0 (if its
1004 size is no greater than one byte), or else the caller must allocate
1005 space into which the callee will copy the return value (if the size
1006 is greater than one byte). In this case, a pointer to the return
1007 value location is passed into the callee in register R2, which does
1008 not displace any of the other arguments passed in via registers R4
1011 /* R2-R9 for integer types and integer equivalent (char, pointers) and
1012 non-scalar (struct, union) elements (even if the elements are
1014 FR0-FR11 for single precision floating point (float)
1015 DR0-DR10 for double precision floating point (double)
1017 If a float is argument number 3 (for instance) and arguments number
1018 1,2, and 4 are integer, the mapping will be:
1019 arg1 -->R2, arg2 --> R3, arg3 -->FR0, arg4 --> R5. I.e. R4 is not used.
1021 If a float is argument number 10 (for instance) and arguments number
1022 1 through 10 are integer, the mapping will be:
1023 arg1->R2, arg2->R3, arg3->R4, arg4->R5, arg5->R6, arg6->R7, arg7->R8,
1024 arg8->R9, arg9->(0,SP)stack(8-byte aligned), arg10->FR0, arg11->stack(16,SP).
1025 I.e. there is hole in the stack.
1027 Different rules apply for variable arguments functions, and for functions
1028 for which the prototype is not known. */
1031 sh64_push_dummy_call (struct gdbarch
*gdbarch
,
1032 struct value
*function
,
1033 struct regcache
*regcache
,
1035 int nargs
, struct value
**args
,
1036 CORE_ADDR sp
, int struct_return
,
1037 CORE_ADDR struct_addr
)
1039 int stack_offset
, stack_alloc
;
1043 int float_arg_index
= 0;
1044 int double_arg_index
= 0;
1055 memset (fp_args
, 0, sizeof (fp_args
));
1057 /* first force sp to a 8-byte alignment */
1058 sp
= sh64_frame_align (gdbarch
, sp
);
1060 /* The "struct return pointer" pseudo-argument has its own dedicated
1064 regcache_cooked_write_unsigned (regcache
,
1065 STRUCT_RETURN_REGNUM
, struct_addr
);
1067 /* Now make sure there's space on the stack */
1068 for (argnum
= 0, stack_alloc
= 0; argnum
< nargs
; argnum
++)
1069 stack_alloc
+= ((TYPE_LENGTH (value_type (args
[argnum
])) + 7) & ~7);
1070 sp
-= stack_alloc
; /* make room on stack for args */
1072 /* Now load as many as possible of the first arguments into
1073 registers, and push the rest onto the stack. There are 64 bytes
1074 in eight registers available. Loop thru args from first to last. */
1076 int_argreg
= ARG0_REGNUM
;
1077 float_argreg
= gdbarch_fp0_regnum (current_gdbarch
);
1078 double_argreg
= DR0_REGNUM
;
1080 for (argnum
= 0, stack_offset
= 0; argnum
< nargs
; argnum
++)
1082 type
= value_type (args
[argnum
]);
1083 len
= TYPE_LENGTH (type
);
1084 memset (valbuf
, 0, sizeof (valbuf
));
1086 if (TYPE_CODE (type
) != TYPE_CODE_FLT
)
1088 argreg_size
= register_size (current_gdbarch
, int_argreg
);
1090 if (len
< argreg_size
)
1092 /* value gets right-justified in the register or stack word */
1093 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
1094 memcpy (valbuf
+ argreg_size
- len
,
1095 (char *) value_contents (args
[argnum
]), len
);
1097 memcpy (valbuf
, (char *) value_contents (args
[argnum
]), len
);
1102 val
= (char *) value_contents (args
[argnum
]);
1106 if (int_argreg
> ARGLAST_REGNUM
)
1108 /* must go on the stack */
1109 write_memory (sp
+ stack_offset
, (const bfd_byte
*) val
,
1111 stack_offset
+= 8;/*argreg_size;*/
1113 /* NOTE WELL!!!!! This is not an "else if" clause!!!
1114 That's because some *&^%$ things get passed on the stack
1115 AND in the registers! */
1116 if (int_argreg
<= ARGLAST_REGNUM
)
1118 /* there's room in a register */
1119 regval
= extract_unsigned_integer (val
, argreg_size
);
1120 regcache_cooked_write_unsigned (regcache
, int_argreg
, regval
);
1122 /* Store the value 8 bytes at a time. This means that
1123 things larger than 8 bytes may go partly in registers
1124 and partly on the stack. FIXME: argreg is incremented
1125 before we use its size. */
1133 val
= (char *) value_contents (args
[argnum
]);
1136 /* Where is it going to be stored? */
1137 while (fp_args
[float_arg_index
])
1140 /* Now float_argreg points to the register where it
1141 should be stored. Are we still within the allowed
1143 if (float_arg_index
<= FLOAT_ARGLAST_REGNUM
)
1145 /* Goes in FR0...FR11 */
1146 regcache_cooked_write (regcache
,
1147 gdbarch_fp0_regnum (current_gdbarch
)
1150 fp_args
[float_arg_index
] = 1;
1151 /* Skip the corresponding general argument register. */
1156 /* Store it as the integers, 8 bytes at the time, if
1157 necessary spilling on the stack. */
1162 /* Where is it going to be stored? */
1163 while (fp_args
[double_arg_index
])
1164 double_arg_index
+= 2;
1165 /* Now double_argreg points to the register
1166 where it should be stored.
1167 Are we still within the allowed register set? */
1168 if (double_arg_index
< FLOAT_ARGLAST_REGNUM
)
1170 /* Goes in DR0...DR10 */
1171 /* The numbering of the DRi registers is consecutive,
1172 i.e. includes odd numbers. */
1173 int double_register_offset
= double_arg_index
/ 2;
1174 int regnum
= DR0_REGNUM
+ double_register_offset
;
1175 regcache_cooked_write (regcache
, regnum
, val
);
1176 fp_args
[double_arg_index
] = 1;
1177 fp_args
[double_arg_index
+ 1] = 1;
1178 /* Skip the corresponding general argument register. */
1183 /* Store it as the integers, 8 bytes at the time, if
1184 necessary spilling on the stack. */
1188 /* Store return address. */
1189 regcache_cooked_write_unsigned (regcache
, PR_REGNUM
, bp_addr
);
1191 /* Update stack pointer. */
1192 regcache_cooked_write_unsigned (regcache
,
1193 gdbarch_sp_regnum (current_gdbarch
), sp
);
1198 /* Find a function's return value in the appropriate registers (in
1199 regbuf), and copy it into valbuf. Extract from an array REGBUF
1200 containing the (raw) register state a function return value of type
1201 TYPE, and copy that, in virtual format, into VALBUF. */
1203 sh64_extract_return_value (struct type
*type
, struct regcache
*regcache
,
1206 int len
= TYPE_LENGTH (type
);
1208 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1212 /* Return value stored in gdbarch_fp0_regnum */
1213 regcache_raw_read (regcache
,
1214 gdbarch_fp0_regnum (current_gdbarch
), valbuf
);
1218 /* return value stored in DR0_REGNUM */
1222 regcache_cooked_read (regcache
, DR0_REGNUM
, buf
);
1224 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_LITTLE
)
1225 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword
,
1228 floatformat_to_doublest (&floatformat_ieee_double_big
,
1230 store_typed_floating (valbuf
, type
, val
);
1239 /* Result is in register 2. If smaller than 8 bytes, it is padded
1240 at the most significant end. */
1241 regcache_raw_read (regcache
, DEFAULT_RETURN_REGNUM
, buf
);
1243 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
1244 offset
= register_size (current_gdbarch
, DEFAULT_RETURN_REGNUM
)
1248 memcpy (valbuf
, buf
+ offset
, len
);
1251 error ("bad size for return value");
1255 /* Write into appropriate registers a function return value
1256 of type TYPE, given in virtual format.
1257 If the architecture is sh4 or sh3e, store a function's return value
1258 in the R0 general register or in the FP0 floating point register,
1259 depending on the type of the return value. In all the other cases
1260 the result is stored in r0, left-justified. */
1263 sh64_store_return_value (struct type
*type
, struct regcache
*regcache
,
1266 char buf
[64]; /* more than enough... */
1267 int len
= TYPE_LENGTH (type
);
1269 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1271 int i
, regnum
= gdbarch_fp0_regnum (current_gdbarch
);
1272 for (i
= 0; i
< len
; i
+= 4)
1273 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_LITTLE
)
1274 regcache_raw_write (regcache
, regnum
++,
1275 (char *) valbuf
+ len
- 4 - i
);
1277 regcache_raw_write (regcache
, regnum
++, (char *) valbuf
+ i
);
1281 int return_register
= DEFAULT_RETURN_REGNUM
;
1284 if (len
<= register_size (current_gdbarch
, return_register
))
1286 /* Pad with zeros. */
1287 memset (buf
, 0, register_size (current_gdbarch
, return_register
));
1288 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_LITTLE
)
1289 offset
= 0; /*register_size (current_gdbarch,
1290 return_register) - len;*/
1292 offset
= register_size (current_gdbarch
, return_register
) - len
;
1294 memcpy (buf
+ offset
, valbuf
, len
);
1295 regcache_raw_write (regcache
, return_register
, buf
);
1298 regcache_raw_write (regcache
, return_register
, valbuf
);
1302 static enum return_value_convention
1303 sh64_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
1304 struct regcache
*regcache
,
1305 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1307 if (sh64_use_struct_convention (type
))
1308 return RETURN_VALUE_STRUCT_CONVENTION
;
1310 sh64_store_return_value (type
, regcache
, writebuf
);
1312 sh64_extract_return_value (type
, regcache
, readbuf
);
1313 return RETURN_VALUE_REGISTER_CONVENTION
;
1317 sh64_show_media_regs (struct frame_info
*frame
)
1322 ("PC=%s SR=%016llx \n",
1323 paddr (get_frame_register_unsigned (frame
,
1324 gdbarch_pc_regnum (current_gdbarch
))),
1325 (long long) get_frame_register_unsigned (frame
, SR_REGNUM
));
1328 ("SSR=%016llx SPC=%016llx \n",
1329 (long long) get_frame_register_unsigned (frame
, SSR_REGNUM
),
1330 (long long) get_frame_register_unsigned (frame
, SPC_REGNUM
));
1333 (long) get_frame_register_unsigned (frame
, FPSCR_REGNUM
));
1335 for (i
= 0; i
< 64; i
= i
+ 4)
1337 ("\nR%d-R%d %016llx %016llx %016llx %016llx\n",
1339 (long long) get_frame_register_unsigned (frame
, i
+ 0),
1340 (long long) get_frame_register_unsigned (frame
, i
+ 1),
1341 (long long) get_frame_register_unsigned (frame
, i
+ 2),
1342 (long long) get_frame_register_unsigned (frame
, i
+ 3));
1344 printf_filtered ("\n");
1346 for (i
= 0; i
< 64; i
= i
+ 8)
1348 ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1350 (long) get_frame_register_unsigned
1351 (frame
, gdbarch_fp0_regnum (current_gdbarch
) + i
+ 0),
1352 (long) get_frame_register_unsigned
1353 (frame
, gdbarch_fp0_regnum (current_gdbarch
) + i
+ 1),
1354 (long) get_frame_register_unsigned
1355 (frame
, gdbarch_fp0_regnum (current_gdbarch
) + i
+ 2),
1356 (long) get_frame_register_unsigned
1357 (frame
, gdbarch_fp0_regnum (current_gdbarch
) + i
+ 3),
1358 (long) get_frame_register_unsigned
1359 (frame
, gdbarch_fp0_regnum (current_gdbarch
) + i
+ 4),
1360 (long) get_frame_register_unsigned
1361 (frame
, gdbarch_fp0_regnum (current_gdbarch
) + i
+ 5),
1362 (long) get_frame_register_unsigned
1363 (frame
, gdbarch_fp0_regnum (current_gdbarch
) + i
+ 6),
1364 (long) get_frame_register_unsigned
1365 (frame
, gdbarch_fp0_regnum (current_gdbarch
) + i
+ 7));
1369 sh64_show_compact_regs (struct frame_info
*frame
)
1375 paddr (get_frame_register_unsigned (frame
, PC_C_REGNUM
)));
1378 ("GBR=%08lx MACH=%08lx MACL=%08lx PR=%08lx T=%08lx\n",
1379 (long) get_frame_register_unsigned (frame
, GBR_C_REGNUM
),
1380 (long) get_frame_register_unsigned (frame
, MACH_C_REGNUM
),
1381 (long) get_frame_register_unsigned (frame
, MACL_C_REGNUM
),
1382 (long) get_frame_register_unsigned (frame
, PR_C_REGNUM
),
1383 (long) get_frame_register_unsigned (frame
, T_C_REGNUM
));
1385 ("FPSCR=%08lx FPUL=%08lx\n",
1386 (long) get_frame_register_unsigned (frame
, FPSCR_C_REGNUM
),
1387 (long) get_frame_register_unsigned (frame
, FPUL_C_REGNUM
));
1389 for (i
= 0; i
< 16; i
= i
+ 4)
1391 ("\nR%d-R%d %08lx %08lx %08lx %08lx\n",
1393 (long) get_frame_register_unsigned (frame
, i
+ 0),
1394 (long) get_frame_register_unsigned (frame
, i
+ 1),
1395 (long) get_frame_register_unsigned (frame
, i
+ 2),
1396 (long) get_frame_register_unsigned (frame
, i
+ 3));
1398 printf_filtered ("\n");
1400 for (i
= 0; i
< 16; i
= i
+ 8)
1402 ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1404 (long) get_frame_register_unsigned
1405 (frame
, gdbarch_fp0_regnum (current_gdbarch
) + i
+ 0),
1406 (long) get_frame_register_unsigned
1407 (frame
, gdbarch_fp0_regnum (current_gdbarch
) + i
+ 1),
1408 (long) get_frame_register_unsigned
1409 (frame
, gdbarch_fp0_regnum (current_gdbarch
) + i
+ 2),
1410 (long) get_frame_register_unsigned
1411 (frame
, gdbarch_fp0_regnum (current_gdbarch
) + i
+ 3),
1412 (long) get_frame_register_unsigned
1413 (frame
, gdbarch_fp0_regnum (current_gdbarch
) + i
+ 4),
1414 (long) get_frame_register_unsigned
1415 (frame
, gdbarch_fp0_regnum (current_gdbarch
) + i
+ 5),
1416 (long) get_frame_register_unsigned
1417 (frame
, gdbarch_fp0_regnum (current_gdbarch
) + i
+ 6),
1418 (long) get_frame_register_unsigned
1419 (frame
, gdbarch_fp0_regnum (current_gdbarch
) + i
+ 7));
1422 /* FIXME!!! This only shows the registers for shmedia, excluding the
1423 pseudo registers. */
1425 sh64_show_regs (struct frame_info
*frame
)
1427 if (pc_is_isa32 (get_frame_pc (frame
)))
1428 sh64_show_media_regs (frame
);
1430 sh64_show_compact_regs (frame
);
1435 SH MEDIA MODE (ISA 32)
1436 general registers (64-bit) 0-63
1437 0 r0, r1, r2, r3, r4, r5, r6, r7,
1438 64 r8, r9, r10, r11, r12, r13, r14, r15,
1439 128 r16, r17, r18, r19, r20, r21, r22, r23,
1440 192 r24, r25, r26, r27, r28, r29, r30, r31,
1441 256 r32, r33, r34, r35, r36, r37, r38, r39,
1442 320 r40, r41, r42, r43, r44, r45, r46, r47,
1443 384 r48, r49, r50, r51, r52, r53, r54, r55,
1444 448 r56, r57, r58, r59, r60, r61, r62, r63,
1449 status reg., saved status reg., saved pc reg. (64-bit) 65-67
1452 target registers (64-bit) 68-75
1453 544 tr0, tr1, tr2, tr3, tr4, tr5, tr6, tr7,
1455 floating point state control register (32-bit) 76
1458 single precision floating point registers (32-bit) 77-140
1459 612 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
1460 644 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15,
1461 676 fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23,
1462 708 fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31,
1463 740 fr32, fr33, fr34, fr35, fr36, fr37, fr38, fr39,
1464 772 fr40, fr41, fr42, fr43, fr44, fr45, fr46, fr47,
1465 804 fr48, fr49, fr50, fr51, fr52, fr53, fr54, fr55,
1466 836 fr56, fr57, fr58, fr59, fr60, fr61, fr62, fr63,
1468 TOTAL SPACE FOR REGISTERS: 868 bytes
1470 From here on they are all pseudo registers: no memory allocated.
1471 REGISTER_BYTE returns the register byte for the base register.
1473 double precision registers (pseudo) 141-172
1474 dr0, dr2, dr4, dr6, dr8, dr10, dr12, dr14,
1475 dr16, dr18, dr20, dr22, dr24, dr26, dr28, dr30,
1476 dr32, dr34, dr36, dr38, dr40, dr42, dr44, dr46,
1477 dr48, dr50, dr52, dr54, dr56, dr58, dr60, dr62,
1479 floating point pairs (pseudo) 173-204
1480 fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14,
1481 fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30,
1482 fp32, fp34, fp36, fp38, fp40, fp42, fp44, fp46,
1483 fp48, fp50, fp52, fp54, fp56, fp58, fp60, fp62,
1485 floating point vectors (4 floating point regs) (pseudo) 205-220
1486 fv0, fv4, fv8, fv12, fv16, fv20, fv24, fv28,
1487 fv32, fv36, fv40, fv44, fv48, fv52, fv56, fv60,
1489 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
1490 r0_c, r1_c, r2_c, r3_c, r4_c, r5_c, r6_c, r7_c,
1491 r8_c, r9_c, r10_c, r11_c, r12_c, r13_c, r14_c, r15_c,
1493 gbr_c, mach_c, macl_c, pr_c, t_c,
1495 fr0_c, fr1_c, fr2_c, fr3_c, fr4_c, fr5_c, fr6_c, fr7_c,
1496 fr8_c, fr9_c, fr10_c, fr11_c, fr12_c, fr13_c, fr14_c, fr15_c
1497 dr0_c, dr2_c, dr4_c, dr6_c, dr8_c, dr10_c, dr12_c, dr14_c
1498 fv0_c, fv4_c, fv8_c, fv12_c
1501 static struct type
*
1502 sh64_build_float_register_type (int high
)
1506 temp
= create_range_type (NULL
, builtin_type_int
, 0, high
);
1507 return create_array_type (NULL
, builtin_type_float
, temp
);
1510 /* Return the GDB type object for the "standard" data type
1511 of data in register REG_NR. */
1512 static struct type
*
1513 sh64_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
1515 if ((reg_nr
>= gdbarch_fp0_regnum (current_gdbarch
)
1516 && reg_nr
<= FP_LAST_REGNUM
)
1517 || (reg_nr
>= FP0_C_REGNUM
1518 && reg_nr
<= FP_LAST_C_REGNUM
))
1519 return builtin_type_float
;
1520 else if ((reg_nr
>= DR0_REGNUM
1521 && reg_nr
<= DR_LAST_REGNUM
)
1522 || (reg_nr
>= DR0_C_REGNUM
1523 && reg_nr
<= DR_LAST_C_REGNUM
))
1524 return builtin_type_double
;
1525 else if (reg_nr
>= FPP0_REGNUM
1526 && reg_nr
<= FPP_LAST_REGNUM
)
1527 return sh64_build_float_register_type (1);
1528 else if ((reg_nr
>= FV0_REGNUM
1529 && reg_nr
<= FV_LAST_REGNUM
)
1530 ||(reg_nr
>= FV0_C_REGNUM
1531 && reg_nr
<= FV_LAST_C_REGNUM
))
1532 return sh64_build_float_register_type (3);
1533 else if (reg_nr
== FPSCR_REGNUM
)
1534 return builtin_type_int
;
1535 else if (reg_nr
>= R0_C_REGNUM
1536 && reg_nr
< FP0_C_REGNUM
)
1537 return builtin_type_int
;
1539 return builtin_type_long_long
;
1543 sh64_register_convert_to_virtual (int regnum
, struct type
*type
,
1544 char *from
, char *to
)
1546 if (gdbarch_byte_order (current_gdbarch
) != BFD_ENDIAN_LITTLE
)
1548 /* It is a no-op. */
1549 memcpy (to
, from
, register_size (current_gdbarch
, regnum
));
1553 if ((regnum
>= DR0_REGNUM
1554 && regnum
<= DR_LAST_REGNUM
)
1555 || (regnum
>= DR0_C_REGNUM
1556 && regnum
<= DR_LAST_C_REGNUM
))
1559 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword
,
1561 store_typed_floating (to
, type
, val
);
1564 error ("sh64_register_convert_to_virtual called with non DR register number");
1568 sh64_register_convert_to_raw (struct type
*type
, int regnum
,
1569 const void *from
, void *to
)
1571 if (gdbarch_byte_order (current_gdbarch
) != BFD_ENDIAN_LITTLE
)
1573 /* It is a no-op. */
1574 memcpy (to
, from
, register_size (current_gdbarch
, regnum
));
1578 if ((regnum
>= DR0_REGNUM
1579 && regnum
<= DR_LAST_REGNUM
)
1580 || (regnum
>= DR0_C_REGNUM
1581 && regnum
<= DR_LAST_C_REGNUM
))
1583 DOUBLEST val
= deprecated_extract_floating (from
, TYPE_LENGTH(type
));
1584 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword
,
1588 error ("sh64_register_convert_to_raw called with non DR register number");
1592 sh64_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1593 int reg_nr
, gdb_byte
*buffer
)
1598 char temp_buffer
[MAX_REGISTER_SIZE
];
1600 if (reg_nr
>= DR0_REGNUM
1601 && reg_nr
<= DR_LAST_REGNUM
)
1603 base_regnum
= sh64_dr_reg_base_num (reg_nr
);
1605 /* Build the value in the provided buffer. */
1606 /* DR regs are double precision registers obtained by
1607 concatenating 2 single precision floating point registers. */
1608 for (portion
= 0; portion
< 2; portion
++)
1609 regcache_raw_read (regcache
, base_regnum
+ portion
,
1611 + register_size (gdbarch
, base_regnum
) * portion
));
1613 /* We must pay attention to the endianness. */
1614 sh64_register_convert_to_virtual (reg_nr
,
1615 register_type (gdbarch
, reg_nr
),
1616 temp_buffer
, buffer
);
1620 else if (reg_nr
>= FPP0_REGNUM
1621 && reg_nr
<= FPP_LAST_REGNUM
)
1623 base_regnum
= sh64_fpp_reg_base_num (reg_nr
);
1625 /* Build the value in the provided buffer. */
1626 /* FPP regs are pairs of single precision registers obtained by
1627 concatenating 2 single precision floating point registers. */
1628 for (portion
= 0; portion
< 2; portion
++)
1629 regcache_raw_read (regcache
, base_regnum
+ portion
,
1631 + register_size (gdbarch
, base_regnum
) * portion
));
1634 else if (reg_nr
>= FV0_REGNUM
1635 && reg_nr
<= FV_LAST_REGNUM
)
1637 base_regnum
= sh64_fv_reg_base_num (reg_nr
);
1639 /* Build the value in the provided buffer. */
1640 /* FV regs are vectors of single precision registers obtained by
1641 concatenating 4 single precision floating point registers. */
1642 for (portion
= 0; portion
< 4; portion
++)
1643 regcache_raw_read (regcache
, base_regnum
+ portion
,
1645 + register_size (gdbarch
, base_regnum
) * portion
));
1648 /* sh compact pseudo registers. 1-to-1 with a shmedia register */
1649 else if (reg_nr
>= R0_C_REGNUM
1650 && reg_nr
<= T_C_REGNUM
)
1652 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
1654 /* Build the value in the provided buffer. */
1655 regcache_raw_read (regcache
, base_regnum
, temp_buffer
);
1656 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
1658 memcpy (buffer
, temp_buffer
+ offset
, 4); /* get LOWER 32 bits only????*/
1661 else if (reg_nr
>= FP0_C_REGNUM
1662 && reg_nr
<= FP_LAST_C_REGNUM
)
1664 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
1666 /* Build the value in the provided buffer. */
1667 /* Floating point registers map 1-1 to the media fp regs,
1668 they have the same size and endianness. */
1669 regcache_raw_read (regcache
, base_regnum
, buffer
);
1672 else if (reg_nr
>= DR0_C_REGNUM
1673 && reg_nr
<= DR_LAST_C_REGNUM
)
1675 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
1677 /* DR_C regs are double precision registers obtained by
1678 concatenating 2 single precision floating point registers. */
1679 for (portion
= 0; portion
< 2; portion
++)
1680 regcache_raw_read (regcache
, base_regnum
+ portion
,
1682 + register_size (gdbarch
, base_regnum
) * portion
));
1684 /* We must pay attention to the endianness. */
1685 sh64_register_convert_to_virtual (reg_nr
,
1686 register_type (gdbarch
, reg_nr
),
1687 temp_buffer
, buffer
);
1690 else if (reg_nr
>= FV0_C_REGNUM
1691 && reg_nr
<= FV_LAST_C_REGNUM
)
1693 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
1695 /* Build the value in the provided buffer. */
1696 /* FV_C regs are vectors of single precision registers obtained by
1697 concatenating 4 single precision floating point registers. */
1698 for (portion
= 0; portion
< 4; portion
++)
1699 regcache_raw_read (regcache
, base_regnum
+ portion
,
1701 + register_size (gdbarch
, base_regnum
) * portion
));
1704 else if (reg_nr
== FPSCR_C_REGNUM
)
1706 int fpscr_base_regnum
;
1708 unsigned int fpscr_value
;
1709 unsigned int sr_value
;
1710 unsigned int fpscr_c_value
;
1711 unsigned int fpscr_c_part1_value
;
1712 unsigned int fpscr_c_part2_value
;
1714 fpscr_base_regnum
= FPSCR_REGNUM
;
1715 sr_base_regnum
= SR_REGNUM
;
1717 /* Build the value in the provided buffer. */
1718 /* FPSCR_C is a very weird register that contains sparse bits
1719 from the FPSCR and the SR architectural registers.
1726 2-17 Bit 2-18 of FPSCR
1727 18-20 Bits 12,13,14 of SR
1731 /* Get FPSCR into a local buffer */
1732 regcache_raw_read (regcache
, fpscr_base_regnum
, temp_buffer
);
1733 /* Get value as an int. */
1734 fpscr_value
= extract_unsigned_integer (temp_buffer
, 4);
1735 /* Get SR into a local buffer */
1736 regcache_raw_read (regcache
, sr_base_regnum
, temp_buffer
);
1737 /* Get value as an int. */
1738 sr_value
= extract_unsigned_integer (temp_buffer
, 4);
1739 /* Build the new value. */
1740 fpscr_c_part1_value
= fpscr_value
& 0x3fffd;
1741 fpscr_c_part2_value
= (sr_value
& 0x7000) << 6;
1742 fpscr_c_value
= fpscr_c_part1_value
| fpscr_c_part2_value
;
1743 /* Store that in out buffer!!! */
1744 store_unsigned_integer (buffer
, 4, fpscr_c_value
);
1745 /* FIXME There is surely an endianness gotcha here. */
1748 else if (reg_nr
== FPUL_C_REGNUM
)
1750 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
1752 /* FPUL_C register is floating point register 32,
1753 same size, same endianness. */
1754 regcache_raw_read (regcache
, base_regnum
, buffer
);
1759 sh64_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1760 int reg_nr
, const gdb_byte
*buffer
)
1762 int base_regnum
, portion
;
1764 char temp_buffer
[MAX_REGISTER_SIZE
];
1766 if (reg_nr
>= DR0_REGNUM
1767 && reg_nr
<= DR_LAST_REGNUM
)
1769 base_regnum
= sh64_dr_reg_base_num (reg_nr
);
1770 /* We must pay attention to the endianness. */
1771 sh64_register_convert_to_raw (register_type (gdbarch
, reg_nr
),
1773 buffer
, temp_buffer
);
1775 /* Write the real regs for which this one is an alias. */
1776 for (portion
= 0; portion
< 2; portion
++)
1777 regcache_raw_write (regcache
, base_regnum
+ portion
,
1779 + register_size (gdbarch
,
1780 base_regnum
) * portion
));
1783 else if (reg_nr
>= FPP0_REGNUM
1784 && reg_nr
<= FPP_LAST_REGNUM
)
1786 base_regnum
= sh64_fpp_reg_base_num (reg_nr
);
1788 /* Write the real regs for which this one is an alias. */
1789 for (portion
= 0; portion
< 2; portion
++)
1790 regcache_raw_write (regcache
, base_regnum
+ portion
,
1792 + register_size (gdbarch
,
1793 base_regnum
) * portion
));
1796 else if (reg_nr
>= FV0_REGNUM
1797 && reg_nr
<= FV_LAST_REGNUM
)
1799 base_regnum
= sh64_fv_reg_base_num (reg_nr
);
1801 /* Write the real regs for which this one is an alias. */
1802 for (portion
= 0; portion
< 4; portion
++)
1803 regcache_raw_write (regcache
, base_regnum
+ portion
,
1805 + register_size (gdbarch
,
1806 base_regnum
) * portion
));
1809 /* sh compact general pseudo registers. 1-to-1 with a shmedia
1810 register but only 4 bytes of it. */
1811 else if (reg_nr
>= R0_C_REGNUM
1812 && reg_nr
<= T_C_REGNUM
)
1814 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
1815 /* reg_nr is 32 bit here, and base_regnum is 64 bits. */
1816 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
1820 /* Let's read the value of the base register into a temporary
1821 buffer, so that overwriting the last four bytes with the new
1822 value of the pseudo will leave the upper 4 bytes unchanged. */
1823 regcache_raw_read (regcache
, base_regnum
, temp_buffer
);
1824 /* Write as an 8 byte quantity */
1825 memcpy (temp_buffer
+ offset
, buffer
, 4);
1826 regcache_raw_write (regcache
, base_regnum
, temp_buffer
);
1829 /* sh floating point compact pseudo registers. 1-to-1 with a shmedia
1830 registers. Both are 4 bytes. */
1831 else if (reg_nr
>= FP0_C_REGNUM
1832 && reg_nr
<= FP_LAST_C_REGNUM
)
1834 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
1835 regcache_raw_write (regcache
, base_regnum
, buffer
);
1838 else if (reg_nr
>= DR0_C_REGNUM
1839 && reg_nr
<= DR_LAST_C_REGNUM
)
1841 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
1842 for (portion
= 0; portion
< 2; portion
++)
1844 /* We must pay attention to the endianness. */
1845 sh64_register_convert_to_raw (register_type (gdbarch
, reg_nr
),
1847 buffer
, temp_buffer
);
1849 regcache_raw_write (regcache
, base_regnum
+ portion
,
1851 + register_size (gdbarch
,
1852 base_regnum
) * portion
));
1856 else if (reg_nr
>= FV0_C_REGNUM
1857 && reg_nr
<= FV_LAST_C_REGNUM
)
1859 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
1861 for (portion
= 0; portion
< 4; portion
++)
1863 regcache_raw_write (regcache
, base_regnum
+ portion
,
1865 + register_size (gdbarch
,
1866 base_regnum
) * portion
));
1870 else if (reg_nr
== FPSCR_C_REGNUM
)
1872 int fpscr_base_regnum
;
1874 unsigned int fpscr_value
;
1875 unsigned int sr_value
;
1876 unsigned int old_fpscr_value
;
1877 unsigned int old_sr_value
;
1878 unsigned int fpscr_c_value
;
1879 unsigned int fpscr_mask
;
1880 unsigned int sr_mask
;
1882 fpscr_base_regnum
= FPSCR_REGNUM
;
1883 sr_base_regnum
= SR_REGNUM
;
1885 /* FPSCR_C is a very weird register that contains sparse bits
1886 from the FPSCR and the SR architectural registers.
1893 2-17 Bit 2-18 of FPSCR
1894 18-20 Bits 12,13,14 of SR
1898 /* Get value as an int. */
1899 fpscr_c_value
= extract_unsigned_integer (buffer
, 4);
1901 /* Build the new values. */
1902 fpscr_mask
= 0x0003fffd;
1903 sr_mask
= 0x001c0000;
1905 fpscr_value
= fpscr_c_value
& fpscr_mask
;
1906 sr_value
= (fpscr_value
& sr_mask
) >> 6;
1908 regcache_raw_read (regcache
, fpscr_base_regnum
, temp_buffer
);
1909 old_fpscr_value
= extract_unsigned_integer (temp_buffer
, 4);
1910 old_fpscr_value
&= 0xfffc0002;
1911 fpscr_value
|= old_fpscr_value
;
1912 store_unsigned_integer (temp_buffer
, 4, fpscr_value
);
1913 regcache_raw_write (regcache
, fpscr_base_regnum
, temp_buffer
);
1915 regcache_raw_read (regcache
, sr_base_regnum
, temp_buffer
);
1916 old_sr_value
= extract_unsigned_integer (temp_buffer
, 4);
1917 old_sr_value
&= 0xffff8fff;
1918 sr_value
|= old_sr_value
;
1919 store_unsigned_integer (temp_buffer
, 4, sr_value
);
1920 regcache_raw_write (regcache
, sr_base_regnum
, temp_buffer
);
1923 else if (reg_nr
== FPUL_C_REGNUM
)
1925 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
1926 regcache_raw_write (regcache
, base_regnum
, buffer
);
1930 /* FIXME:!! THIS SHOULD TAKE CARE OF GETTING THE RIGHT PORTION OF THE
1931 shmedia REGISTERS. */
1932 /* Control registers, compact mode. */
1934 sh64_do_cr_c_register_info (struct ui_file
*file
, struct frame_info
*frame
,
1937 switch (cr_c_regnum
)
1940 fprintf_filtered (file
, "pc_c\t0x%08x\n",
1941 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1944 fprintf_filtered (file
, "gbr_c\t0x%08x\n",
1945 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1948 fprintf_filtered (file
, "mach_c\t0x%08x\n",
1949 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1952 fprintf_filtered (file
, "macl_c\t0x%08x\n",
1953 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1956 fprintf_filtered (file
, "pr_c\t0x%08x\n",
1957 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1960 fprintf_filtered (file
, "t_c\t0x%08x\n",
1961 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1963 case FPSCR_C_REGNUM
:
1964 fprintf_filtered (file
, "fpscr_c\t0x%08x\n",
1965 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1968 fprintf_filtered (file
, "fpul_c\t0x%08x\n",
1969 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1975 sh64_do_fp_register (struct gdbarch
*gdbarch
, struct ui_file
*file
,
1976 struct frame_info
*frame
, int regnum
)
1977 { /* do values for FP (float) regs */
1978 unsigned char *raw_buffer
;
1979 double flt
; /* double extracted from raw hex data */
1983 /* Allocate space for the float. */
1984 raw_buffer
= (unsigned char *) alloca
1985 (register_size (gdbarch
,
1987 (current_gdbarch
)));
1989 /* Get the data in raw format. */
1990 if (!frame_register_read (frame
, regnum
, raw_buffer
))
1991 error ("can't read register %d (%s)",
1992 regnum
, gdbarch_register_name (current_gdbarch
, regnum
));
1994 /* Get the register as a number */
1995 flt
= unpack_double (builtin_type_float
, raw_buffer
, &inv
);
1997 /* Print the name and some spaces. */
1998 fputs_filtered (gdbarch_register_name (current_gdbarch
, regnum
), file
);
1999 print_spaces_filtered (15 - strlen (gdbarch_register_name
2000 (current_gdbarch
, regnum
)), file
);
2002 /* Print the value. */
2004 fprintf_filtered (file
, "<invalid float>");
2006 fprintf_filtered (file
, "%-10.9g", flt
);
2008 /* Print the fp register as hex. */
2009 fprintf_filtered (file
, "\t(raw 0x");
2010 for (j
= 0; j
< register_size (gdbarch
, regnum
); j
++)
2012 int idx
= gdbarch_byte_order (current_gdbarch
)
2013 == BFD_ENDIAN_BIG
? j
: register_size
2014 (gdbarch
, regnum
) - 1 - j
;
2015 fprintf_filtered (file
, "%02x", raw_buffer
[idx
]);
2017 fprintf_filtered (file
, ")");
2018 fprintf_filtered (file
, "\n");
2022 sh64_do_pseudo_register (struct gdbarch
*gdbarch
, struct ui_file
*file
,
2023 struct frame_info
*frame
, int regnum
)
2025 /* All the sh64-compact mode registers are pseudo registers. */
2027 if (regnum
< gdbarch_num_regs (current_gdbarch
)
2028 || regnum
>= gdbarch_num_regs (current_gdbarch
)
2029 + NUM_PSEUDO_REGS_SH_MEDIA
2030 + NUM_PSEUDO_REGS_SH_COMPACT
)
2031 internal_error (__FILE__
, __LINE__
,
2032 _("Invalid pseudo register number %d\n"), regnum
);
2034 else if ((regnum
>= DR0_REGNUM
&& regnum
<= DR_LAST_REGNUM
))
2036 int fp_regnum
= sh64_dr_reg_base_num (regnum
);
2037 fprintf_filtered (file
, "dr%d\t0x%08x%08x\n", regnum
- DR0_REGNUM
,
2038 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
),
2039 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 1));
2042 else if ((regnum
>= DR0_C_REGNUM
&& regnum
<= DR_LAST_C_REGNUM
))
2044 int fp_regnum
= sh64_compact_reg_base_num (regnum
);
2045 fprintf_filtered (file
, "dr%d_c\t0x%08x%08x\n", regnum
- DR0_C_REGNUM
,
2046 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
),
2047 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 1));
2050 else if ((regnum
>= FV0_REGNUM
&& regnum
<= FV_LAST_REGNUM
))
2052 int fp_regnum
= sh64_fv_reg_base_num (regnum
);
2053 fprintf_filtered (file
, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
2054 regnum
- FV0_REGNUM
,
2055 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
),
2056 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 1),
2057 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 2),
2058 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 3));
2061 else if ((regnum
>= FV0_C_REGNUM
&& regnum
<= FV_LAST_C_REGNUM
))
2063 int fp_regnum
= sh64_compact_reg_base_num (regnum
);
2064 fprintf_filtered (file
, "fv%d_c\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
2065 regnum
- FV0_C_REGNUM
,
2066 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
),
2067 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 1),
2068 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 2),
2069 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 3));
2072 else if (regnum
>= FPP0_REGNUM
&& regnum
<= FPP_LAST_REGNUM
)
2074 int fp_regnum
= sh64_fpp_reg_base_num (regnum
);
2075 fprintf_filtered (file
, "fpp%d\t0x%08x\t0x%08x\n", regnum
- FPP0_REGNUM
,
2076 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
),
2077 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 1));
2080 else if (regnum
>= R0_C_REGNUM
&& regnum
<= R_LAST_C_REGNUM
)
2082 int c_regnum
= sh64_compact_reg_base_num (regnum
);
2083 fprintf_filtered (file
, "r%d_c\t0x%08x\n", regnum
- R0_C_REGNUM
,
2084 (unsigned) get_frame_register_unsigned (frame
, c_regnum
));
2086 else if (regnum
>= FP0_C_REGNUM
&& regnum
<= FP_LAST_C_REGNUM
)
2087 /* This should work also for pseudoregs. */
2088 sh64_do_fp_register (gdbarch
, file
, frame
, regnum
);
2089 else if (regnum
>= PC_C_REGNUM
&& regnum
<= FPUL_C_REGNUM
)
2090 sh64_do_cr_c_register_info (file
, frame
, regnum
);
2094 sh64_do_register (struct gdbarch
*gdbarch
, struct ui_file
*file
,
2095 struct frame_info
*frame
, int regnum
)
2097 unsigned char raw_buffer
[MAX_REGISTER_SIZE
];
2099 fputs_filtered (gdbarch_register_name (current_gdbarch
, regnum
), file
);
2100 print_spaces_filtered (15 - strlen (gdbarch_register_name
2101 (current_gdbarch
, regnum
)), file
);
2103 /* Get the data in raw format. */
2104 if (!frame_register_read (frame
, regnum
, raw_buffer
))
2105 fprintf_filtered (file
, "*value not available*\n");
2107 val_print (register_type (gdbarch
, regnum
), raw_buffer
, 0, 0,
2108 file
, 'x', 1, 0, Val_pretty_default
);
2109 fprintf_filtered (file
, "\t");
2110 val_print (register_type (gdbarch
, regnum
), raw_buffer
, 0, 0,
2111 file
, 0, 1, 0, Val_pretty_default
);
2112 fprintf_filtered (file
, "\n");
2116 sh64_print_register (struct gdbarch
*gdbarch
, struct ui_file
*file
,
2117 struct frame_info
*frame
, int regnum
)
2119 if (regnum
< 0 || regnum
>= gdbarch_num_regs (current_gdbarch
)
2120 + gdbarch_num_pseudo_regs (current_gdbarch
))
2121 internal_error (__FILE__
, __LINE__
,
2122 _("Invalid register number %d\n"), regnum
);
2124 else if (regnum
>= 0 && regnum
< gdbarch_num_regs (current_gdbarch
))
2126 if (TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
2127 sh64_do_fp_register (gdbarch
, file
, frame
, regnum
); /* FP regs */
2129 sh64_do_register (gdbarch
, file
, frame
, regnum
);
2132 else if (regnum
< gdbarch_num_regs (current_gdbarch
)
2133 + gdbarch_num_pseudo_regs (current_gdbarch
))
2134 sh64_do_pseudo_register (gdbarch
, file
, frame
, regnum
);
2138 sh64_media_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
2139 struct frame_info
*frame
, int regnum
,
2142 if (regnum
!= -1) /* do one specified register */
2144 if (*(gdbarch_register_name (current_gdbarch
, regnum
)) == '\0')
2145 error ("Not a valid register for the current processor type");
2147 sh64_print_register (gdbarch
, file
, frame
, regnum
);
2150 /* do all (or most) registers */
2153 while (regnum
< gdbarch_num_regs (current_gdbarch
))
2155 /* If the register name is empty, it is undefined for this
2156 processor, so don't display anything. */
2157 if (gdbarch_register_name (current_gdbarch
, regnum
) == NULL
2158 || *(gdbarch_register_name (current_gdbarch
, regnum
)) == '\0')
2164 if (TYPE_CODE (register_type (gdbarch
, regnum
))
2169 /* true for "INFO ALL-REGISTERS" command */
2170 sh64_do_fp_register (gdbarch
, file
, frame
, regnum
);
2174 regnum
+= FP_LAST_REGNUM
- gdbarch_fp0_regnum (current_gdbarch
);
2179 sh64_do_register (gdbarch
, file
, frame
, regnum
);
2185 while (regnum
< gdbarch_num_regs (current_gdbarch
)
2186 + gdbarch_num_pseudo_regs (current_gdbarch
))
2188 sh64_do_pseudo_register (gdbarch
, file
, frame
, regnum
);
2195 sh64_compact_print_registers_info (struct gdbarch
*gdbarch
,
2196 struct ui_file
*file
,
2197 struct frame_info
*frame
, int regnum
,
2200 if (regnum
!= -1) /* do one specified register */
2202 if (*(gdbarch_register_name (current_gdbarch
, regnum
)) == '\0')
2203 error ("Not a valid register for the current processor type");
2205 if (regnum
>= 0 && regnum
< R0_C_REGNUM
)
2206 error ("Not a valid register for the current processor mode.");
2208 sh64_print_register (gdbarch
, file
, frame
, regnum
);
2211 /* do all compact registers */
2213 regnum
= R0_C_REGNUM
;
2214 while (regnum
< gdbarch_num_regs (current_gdbarch
)
2215 + gdbarch_num_pseudo_regs (current_gdbarch
))
2217 sh64_do_pseudo_register (gdbarch
, file
, frame
, regnum
);
2224 sh64_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
2225 struct frame_info
*frame
, int regnum
, int fpregs
)
2227 if (pc_is_isa32 (get_frame_pc (frame
)))
2228 sh64_media_print_registers_info (gdbarch
, file
, frame
, regnum
, fpregs
);
2230 sh64_compact_print_registers_info (gdbarch
, file
, frame
, regnum
, fpregs
);
2233 static struct sh64_frame_cache
*
2234 sh64_alloc_frame_cache (void)
2236 struct sh64_frame_cache
*cache
;
2239 cache
= FRAME_OBSTACK_ZALLOC (struct sh64_frame_cache
);
2243 cache
->saved_sp
= 0;
2244 cache
->sp_offset
= 0;
2247 /* Frameless until proven otherwise. */
2250 /* Saved registers. We initialize these to -1 since zero is a valid
2251 offset (that's where fp is supposed to be stored). */
2252 for (i
= 0; i
< SIM_SH64_NR_REGS
; i
++)
2254 cache
->saved_regs
[i
] = -1;
2260 static struct sh64_frame_cache
*
2261 sh64_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2263 struct sh64_frame_cache
*cache
;
2264 CORE_ADDR current_pc
;
2270 cache
= sh64_alloc_frame_cache ();
2271 *this_cache
= cache
;
2273 current_pc
= frame_pc_unwind (next_frame
);
2274 cache
->media_mode
= pc_is_isa32 (current_pc
);
2276 /* In principle, for normal frames, fp holds the frame pointer,
2277 which holds the base address for the current stack frame.
2278 However, for functions that don't need it, the frame pointer is
2279 optional. For these "frameless" functions the frame pointer is
2280 actually the frame pointer of the calling frame. */
2281 cache
->base
= frame_unwind_register_unsigned (next_frame
, MEDIA_FP_REGNUM
);
2282 if (cache
->base
== 0)
2285 cache
->pc
= frame_func_unwind (next_frame
, NORMAL_FRAME
);
2287 sh64_analyze_prologue (current_gdbarch
, cache
, cache
->pc
, current_pc
);
2289 if (!cache
->uses_fp
)
2291 /* We didn't find a valid frame, which means that CACHE->base
2292 currently holds the frame pointer for our calling frame. If
2293 we're at the start of a function, or somewhere half-way its
2294 prologue, the function's frame probably hasn't been fully
2295 setup yet. Try to reconstruct the base address for the stack
2296 frame by looking at the stack pointer. For truly "frameless"
2297 functions this might work too. */
2298 cache
->base
= frame_unwind_register_unsigned
2299 (next_frame
, gdbarch_sp_regnum (current_gdbarch
));
2302 /* Now that we have the base address for the stack frame we can
2303 calculate the value of sp in the calling frame. */
2304 cache
->saved_sp
= cache
->base
+ cache
->sp_offset
;
2306 /* Adjust all the saved registers such that they contain addresses
2307 instead of offsets. */
2308 for (i
= 0; i
< SIM_SH64_NR_REGS
; i
++)
2309 if (cache
->saved_regs
[i
] != -1)
2310 cache
->saved_regs
[i
] = cache
->saved_sp
- cache
->saved_regs
[i
];
2316 sh64_frame_prev_register (struct frame_info
*next_frame
, void **this_cache
,
2317 int regnum
, int *optimizedp
,
2318 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2319 int *realnump
, gdb_byte
*valuep
)
2321 struct sh64_frame_cache
*cache
= sh64_frame_cache (next_frame
, this_cache
);
2323 gdb_assert (regnum
>= 0);
2325 if (regnum
== gdbarch_sp_regnum (current_gdbarch
) && cache
->saved_sp
)
2333 /* Store the value. */
2334 store_unsigned_integer (valuep
,
2335 register_size (current_gdbarch
,
2336 gdbarch_sp_regnum (current_gdbarch
)),
2342 /* The PC of the previous frame is stored in the PR register of
2343 the current frame. Frob regnum so that we pull the value from
2344 the correct place. */
2345 if (regnum
== gdbarch_pc_regnum (current_gdbarch
))
2348 if (regnum
< SIM_SH64_NR_REGS
&& cache
->saved_regs
[regnum
] != -1)
2350 int reg_size
= register_size (current_gdbarch
, regnum
);
2354 *lvalp
= lval_memory
;
2355 *addrp
= cache
->saved_regs
[regnum
];
2357 if (gdbarch_tdep (current_gdbarch
)->sh_abi
== SH_ABI_32
2358 && (regnum
== MEDIA_FP_REGNUM
|| regnum
== PR_REGNUM
))
2364 memset (valuep
, 0, reg_size
);
2365 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_LITTLE
)
2366 read_memory (*addrp
, valuep
, size
);
2368 read_memory (*addrp
, (char *) valuep
+ reg_size
- size
, size
);
2374 *lvalp
= lval_register
;
2378 frame_unwind_register (next_frame
, (*realnump
), valuep
);
2382 sh64_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2383 struct frame_id
*this_id
)
2385 struct sh64_frame_cache
*cache
= sh64_frame_cache (next_frame
, this_cache
);
2387 /* This marks the outermost frame. */
2388 if (cache
->base
== 0)
2391 *this_id
= frame_id_build (cache
->saved_sp
, cache
->pc
);
2394 static const struct frame_unwind sh64_frame_unwind
= {
2397 sh64_frame_prev_register
2400 static const struct frame_unwind
*
2401 sh64_frame_sniffer (struct frame_info
*next_frame
)
2403 return &sh64_frame_unwind
;
2407 sh64_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2409 return frame_unwind_register_unsigned (next_frame
,
2410 gdbarch_sp_regnum (current_gdbarch
));
2414 sh64_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2416 return frame_unwind_register_unsigned (next_frame
,
2417 gdbarch_pc_regnum (current_gdbarch
));
2420 static struct frame_id
2421 sh64_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2423 return frame_id_build (sh64_unwind_sp (gdbarch
, next_frame
),
2424 frame_pc_unwind (next_frame
));
2428 sh64_frame_base_address (struct frame_info
*next_frame
, void **this_cache
)
2430 struct sh64_frame_cache
*cache
= sh64_frame_cache (next_frame
, this_cache
);
2435 static const struct frame_base sh64_frame_base
= {
2437 sh64_frame_base_address
,
2438 sh64_frame_base_address
,
2439 sh64_frame_base_address
2444 sh64_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2446 struct gdbarch
*gdbarch
;
2447 struct gdbarch_tdep
*tdep
;
2449 /* If there is already a candidate, use it. */
2450 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2452 return arches
->gdbarch
;
2454 /* None found, create a new architecture from the information
2456 tdep
= XMALLOC (struct gdbarch_tdep
);
2457 gdbarch
= gdbarch_alloc (&info
, tdep
);
2459 /* Determine the ABI */
2460 if (info
.abfd
&& bfd_get_arch_size (info
.abfd
) == 64)
2462 /* If the ABI is the 64-bit one, it can only be sh-media. */
2463 tdep
->sh_abi
= SH_ABI_64
;
2464 set_gdbarch_ptr_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2465 set_gdbarch_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2469 /* If the ABI is the 32-bit one it could be either media or
2471 tdep
->sh_abi
= SH_ABI_32
;
2472 set_gdbarch_ptr_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2473 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2476 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
2477 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2478 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2479 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2480 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2481 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2482 set_gdbarch_long_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2484 /* The number of real registers is the same whether we are in
2485 ISA16(compact) or ISA32(media). */
2486 set_gdbarch_num_regs (gdbarch
, SIM_SH64_NR_REGS
);
2487 set_gdbarch_sp_regnum (gdbarch
, 15);
2488 set_gdbarch_pc_regnum (gdbarch
, 64);
2489 set_gdbarch_fp0_regnum (gdbarch
, SIM_SH64_FR0_REGNUM
);
2490 set_gdbarch_num_pseudo_regs (gdbarch
, NUM_PSEUDO_REGS_SH_MEDIA
2491 + NUM_PSEUDO_REGS_SH_COMPACT
);
2493 set_gdbarch_register_name (gdbarch
, sh64_register_name
);
2494 set_gdbarch_register_type (gdbarch
, sh64_register_type
);
2496 set_gdbarch_pseudo_register_read (gdbarch
, sh64_pseudo_register_read
);
2497 set_gdbarch_pseudo_register_write (gdbarch
, sh64_pseudo_register_write
);
2499 set_gdbarch_breakpoint_from_pc (gdbarch
, sh64_breakpoint_from_pc
);
2501 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_sh64
);
2502 set_gdbarch_register_sim_regno (gdbarch
, legacy_register_sim_regno
);
2504 set_gdbarch_return_value (gdbarch
, sh64_return_value
);
2506 set_gdbarch_skip_prologue (gdbarch
, sh64_skip_prologue
);
2507 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2509 set_gdbarch_push_dummy_call (gdbarch
, sh64_push_dummy_call
);
2511 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
2513 set_gdbarch_frame_align (gdbarch
, sh64_frame_align
);
2514 set_gdbarch_unwind_sp (gdbarch
, sh64_unwind_sp
);
2515 set_gdbarch_unwind_pc (gdbarch
, sh64_unwind_pc
);
2516 set_gdbarch_unwind_dummy_id (gdbarch
, sh64_unwind_dummy_id
);
2517 frame_base_set_default (gdbarch
, &sh64_frame_base
);
2519 set_gdbarch_print_registers_info (gdbarch
, sh64_print_registers_info
);
2521 set_gdbarch_elf_make_msymbol_special (gdbarch
,
2522 sh64_elf_make_msymbol_special
);
2524 /* Hook in ABI-specific overrides, if they have been registered. */
2525 gdbarch_init_osabi (info
, gdbarch
);
2527 frame_unwind_append_sniffer (gdbarch
, dwarf2_frame_sniffer
);
2528 frame_unwind_append_sniffer (gdbarch
, sh64_frame_sniffer
);