1 /* Target-dependent code for Renesas Super-H, for GDB.
3 Copyright (C) 1993-2017 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20 /* Contributed by Steve Chamberlain
25 #include "frame-base.h"
26 #include "frame-unwind.h"
27 #include "dwarf2-frame.h"
35 #include "arch-utils.h"
44 /* Register numbers shared with the simulator. */
45 #include "gdb/sim-sh.h"
47 #include "sh64-tdep.h"
50 /* Information that is dependent on the processor variant. */
61 /* ISA-specific data types. */
62 struct type
*sh_littlebyte_bigword_type
;
66 sh64_littlebyte_bigword_type (struct gdbarch
*gdbarch
)
68 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
70 if (tdep
->sh_littlebyte_bigword_type
== NULL
)
71 tdep
->sh_littlebyte_bigword_type
72 = arch_float_type (gdbarch
, -1, "builtin_type_sh_littlebyte_bigword",
73 floatformats_ieee_double_littlebyte_bigword
);
75 return tdep
->sh_littlebyte_bigword_type
;
78 struct sh64_frame_cache
85 /* Flag showing that a frame has been created in the prologue code. */
90 /* Saved registers. */
91 CORE_ADDR saved_regs
[SIM_SH64_NR_REGS
];
95 /* Registers of SH5 */
99 DEFAULT_RETURN_REGNUM
= 2,
100 STRUCT_RETURN_REGNUM
= 2,
103 FLOAT_ARGLAST_REGNUM
= 11,
104 MEDIA_FP_REGNUM
= 14,
108 DR_LAST_REGNUM
= 172,
109 /* FPP stands for Floating Point Pair, to avoid confusion with
110 GDB's gdbarch_fp0_regnum, which is the number of the first Floating
111 point register. Unfortunately on the sh5, the floating point
112 registers are called FR, and the floating point pairs are called FP. */
114 FPP_LAST_REGNUM
= 204,
116 FV_LAST_REGNUM
= 220,
118 R_LAST_C_REGNUM
= 236,
125 FPSCR_C_REGNUM
= 243,
128 FP_LAST_C_REGNUM
= 260,
130 DR_LAST_C_REGNUM
= 268,
132 FV_LAST_C_REGNUM
= 272,
133 FPSCR_REGNUM
= SIM_SH64_FPCSR_REGNUM
,
134 SSR_REGNUM
= SIM_SH64_SSR_REGNUM
,
135 SPC_REGNUM
= SIM_SH64_SPC_REGNUM
,
136 TR7_REGNUM
= SIM_SH64_TR0_REGNUM
+ 7,
137 FP_LAST_REGNUM
= SIM_SH64_FR0_REGNUM
+ SIM_SH64_NR_FP_REGS
- 1
141 sh64_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
143 static const char *register_names
[] =
145 /* SH MEDIA MODE (ISA 32) */
146 /* general registers (64-bit) 0-63 */
147 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
148 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
149 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
150 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
151 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
152 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
153 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
154 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
159 /* status reg., saved status reg., saved pc reg. (64-bit) 65-67 */
162 /* target registers (64-bit) 68-75 */
163 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7",
165 /* floating point state control register (32-bit) 76 */
168 /* single precision floating point registers (32-bit) 77-140 */
169 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
170 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
171 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
172 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31",
173 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39",
174 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47",
175 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55",
176 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63",
178 /* double precision registers (pseudo) 141-172 */
179 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
180 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30",
181 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46",
182 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62",
184 /* floating point pairs (pseudo) 173-204 */
185 "fp0", "fp2", "fp4", "fp6", "fp8", "fp10", "fp12", "fp14",
186 "fp16", "fp18", "fp20", "fp22", "fp24", "fp26", "fp28", "fp30",
187 "fp32", "fp34", "fp36", "fp38", "fp40", "fp42", "fp44", "fp46",
188 "fp48", "fp50", "fp52", "fp54", "fp56", "fp58", "fp60", "fp62",
190 /* floating point vectors (4 floating point regs) (pseudo) 205-220 */
191 "fv0", "fv4", "fv8", "fv12", "fv16", "fv20", "fv24", "fv28",
192 "fv32", "fv36", "fv40", "fv44", "fv48", "fv52", "fv56", "fv60",
194 /* SH COMPACT MODE (ISA 16) (all pseudo) 221-272 */
195 "r0_c", "r1_c", "r2_c", "r3_c", "r4_c", "r5_c", "r6_c", "r7_c",
196 "r8_c", "r9_c", "r10_c", "r11_c", "r12_c", "r13_c", "r14_c", "r15_c",
198 "gbr_c", "mach_c", "macl_c", "pr_c", "t_c",
200 "fr0_c", "fr1_c", "fr2_c", "fr3_c",
201 "fr4_c", "fr5_c", "fr6_c", "fr7_c",
202 "fr8_c", "fr9_c", "fr10_c", "fr11_c",
203 "fr12_c", "fr13_c", "fr14_c", "fr15_c",
204 "dr0_c", "dr2_c", "dr4_c", "dr6_c",
205 "dr8_c", "dr10_c", "dr12_c", "dr14_c",
206 "fv0_c", "fv4_c", "fv8_c", "fv12_c",
207 /* FIXME!!!! XF0 XF15, XD0 XD14 ????? */
212 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
214 return register_names
[reg_nr
];
217 #define NUM_PSEUDO_REGS_SH_MEDIA 80
218 #define NUM_PSEUDO_REGS_SH_COMPACT 51
220 /* Macros and functions for setting and testing a bit in a minimal
221 symbol that marks it as 32-bit function. The MSB of the minimal
222 symbol's "info" field is used for this purpose.
224 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
225 i.e. refers to a 32-bit function, and sets a "special" bit in a
226 minimal symbol to mark it as a 32-bit function
227 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
229 #define MSYMBOL_IS_SPECIAL(msym) \
230 MSYMBOL_TARGET_FLAG_1 (msym)
233 sh64_elf_make_msymbol_special (asymbol
*sym
, struct minimal_symbol
*msym
)
238 if (((elf_symbol_type
*)(sym
))->internal_elf_sym
.st_other
== STO_SH5_ISA32
)
240 MSYMBOL_TARGET_FLAG_1 (msym
) = 1;
241 SET_MSYMBOL_VALUE_ADDRESS (msym
, MSYMBOL_VALUE_RAW_ADDRESS (msym
) | 1);
245 /* ISA32 (shmedia) function addresses are odd (bit 0 is set). Here
246 are some macros to test, set, or clear bit 0 of addresses. */
247 #define IS_ISA32_ADDR(addr) ((addr) & 1)
248 #define MAKE_ISA32_ADDR(addr) ((addr) | 1)
249 #define UNMAKE_ISA32_ADDR(addr) ((addr) & ~1)
252 pc_is_isa32 (bfd_vma memaddr
)
254 struct bound_minimal_symbol sym
;
256 /* If bit 0 of the address is set, assume this is a
257 ISA32 (shmedia) address. */
258 if (IS_ISA32_ADDR (memaddr
))
261 /* A flag indicating that this is a ISA32 function is stored by elfread.c in
262 the high bit of the info field. Use this to decide if the function is
264 sym
= lookup_minimal_symbol_by_pc (memaddr
);
266 return MSYMBOL_IS_SPECIAL (sym
.minsym
);
272 sh64_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
274 if (pc_is_isa32 (*pcptr
))
276 *pcptr
= UNMAKE_ISA32_ADDR (*pcptr
);
283 static const gdb_byte
*
284 sh64_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
288 /* The BRK instruction for shmedia is
289 01101111 11110101 11111111 11110000
290 which translates in big endian mode to 0x6f, 0xf5, 0xff, 0xf0
291 and in little endian mode to 0xf0, 0xff, 0xf5, 0x6f */
293 /* The BRK instruction for shcompact is
295 which translates in big endian mode to 0x0, 0x3b
296 and in little endian mode to 0x3b, 0x0 */
300 static unsigned char big_breakpoint_media
[] = {
301 0x6f, 0xf5, 0xff, 0xf0
303 static unsigned char little_breakpoint_media
[] = {
304 0xf0, 0xff, 0xf5, 0x6f
307 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
308 return big_breakpoint_media
;
310 return little_breakpoint_media
;
314 static unsigned char big_breakpoint_compact
[] = {0x0, 0x3b};
315 static unsigned char little_breakpoint_compact
[] = {0x3b, 0x0};
317 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
318 return big_breakpoint_compact
;
320 return little_breakpoint_compact
;
324 /* Prologue looks like
325 [mov.l <regs>,@-r15]...
330 Actually it can be more complicated than this. For instance, with
348 /* PTABS/L Rn, TRa 0110101111110001nnnnnnl00aaa0000
349 with l=1 and n = 18 0110101111110001010010100aaa0000 */
350 #define IS_PTABSL_R18(x) (((x) & 0xffffff8f) == 0x6bf14a00)
352 /* STS.L PR,@-r0 0100000000100010
353 r0-4-->r0, PR-->(r0) */
354 #define IS_STS_R0(x) ((x) == 0x4022)
356 /* STS PR, Rm 0000mmmm00101010
358 #define IS_STS_PR(x) (((x) & 0xf0ff) == 0x2a)
360 /* MOV.L Rm,@(disp,r15) 00011111mmmmdddd
362 #define IS_MOV_TO_R15(x) (((x) & 0xff00) == 0x1f00)
364 /* MOV.L R14,@(disp,r15) 000111111110dddd
365 R14-->(dispx4+r15) */
366 #define IS_MOV_R14(x) (((x) & 0xfff0) == 0x1fe0)
368 /* ST.Q R14, disp, R18 101011001110dddddddddd0100100000
369 R18-->(dispx8+R14) */
370 #define IS_STQ_R18_R14(x) (((x) & 0xfff003ff) == 0xace00120)
372 /* ST.Q R15, disp, R18 101011001111dddddddddd0100100000
373 R18-->(dispx8+R15) */
374 #define IS_STQ_R18_R15(x) (((x) & 0xfff003ff) == 0xacf00120)
376 /* ST.L R15, disp, R18 101010001111dddddddddd0100100000
377 R18-->(dispx4+R15) */
378 #define IS_STL_R18_R15(x) (((x) & 0xfff003ff) == 0xa8f00120)
380 /* ST.Q R15, disp, R14 1010 1100 1111 dddd dddd dd00 1110 0000
381 R14-->(dispx8+R15) */
382 #define IS_STQ_R14_R15(x) (((x) & 0xfff003ff) == 0xacf000e0)
384 /* ST.L R15, disp, R14 1010 1000 1111 dddd dddd dd00 1110 0000
385 R14-->(dispx4+R15) */
386 #define IS_STL_R14_R15(x) (((x) & 0xfff003ff) == 0xa8f000e0)
388 /* ADDI.L R15,imm,R15 1101 0100 1111 ssss ssss ss00 1111 0000
390 #define IS_ADDIL_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd4f000f0)
392 /* ADDI R15,imm,R15 1101 0000 1111 ssss ssss ss00 1111 0000
394 #define IS_ADDI_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd0f000f0)
396 /* ADD.L R15,R63,R14 0000 0000 1111 1000 1111 1100 1110 0000
398 #define IS_ADDL_SP_FP_MEDIA(x) ((x) == 0x00f8fce0)
400 /* ADD R15,R63,R14 0000 0000 1111 1001 1111 1100 1110 0000
402 #define IS_ADD_SP_FP_MEDIA(x) ((x) == 0x00f9fce0)
404 #define IS_MOV_SP_FP_MEDIA(x) \
405 (IS_ADDL_SP_FP_MEDIA(x) || IS_ADD_SP_FP_MEDIA(x))
407 /* MOV #imm, R0 1110 0000 ssss ssss
409 #define IS_MOV_R0(x) (((x) & 0xff00) == 0xe000)
411 /* MOV.L @(disp,PC), R0 1101 0000 iiii iiii */
412 #define IS_MOVL_R0(x) (((x) & 0xff00) == 0xd000)
414 /* ADD r15,r0 0011 0000 1111 1100
416 #define IS_ADD_SP_R0(x) ((x) == 0x30fc)
418 /* MOV.L R14 @-R0 0010 0000 1110 0110
419 R14-->(R0-4), R0-4-->R0 */
420 #define IS_MOV_R14_R0(x) ((x) == 0x20e6)
422 /* ADD Rm,R63,Rn Rm+R63-->Rn 0000 00mm mmmm 1001 1111 11nn nnnn 0000
423 where Rm is one of r2-r9 which are the argument registers. */
424 /* FIXME: Recognize the float and double register moves too! */
425 #define IS_MEDIA_IND_ARG_MOV(x) \
426 ((((x) & 0xfc0ffc0f) == 0x0009fc00) \
427 && (((x) & 0x03f00000) >= 0x00200000 \
428 && ((x) & 0x03f00000) <= 0x00900000))
430 /* ST.Q Rn,0,Rm Rm-->Rn+0 1010 11nn nnnn 0000 0000 00mm mmmm 0000
431 or ST.L Rn,0,Rm Rm-->Rn+0 1010 10nn nnnn 0000 0000 00mm mmmm 0000
432 where Rm is one of r2-r9 which are the argument registers. */
433 #define IS_MEDIA_ARG_MOV(x) \
434 (((((x) & 0xfc0ffc0f) == 0xac000000) || (((x) & 0xfc0ffc0f) == 0xa8000000)) \
435 && (((x) & 0x000003f0) >= 0x00000020 && ((x) & 0x000003f0) <= 0x00000090))
437 /* ST.B R14,0,Rn Rn-->(R14+0) 1010 0000 1110 0000 0000 00nn nnnn 0000 */
438 /* ST.W R14,0,Rn Rn-->(R14+0) 1010 0100 1110 0000 0000 00nn nnnn 0000 */
439 /* ST.L R14,0,Rn Rn-->(R14+0) 1010 1000 1110 0000 0000 00nn nnnn 0000 */
440 /* FST.S R14,0,FRn Rn-->(R14+0) 1011 0100 1110 0000 0000 00nn nnnn 0000 */
441 /* FST.D R14,0,DRn Rn-->(R14+0) 1011 1100 1110 0000 0000 00nn nnnn 0000 */
442 #define IS_MEDIA_MOV_TO_R14(x) \
443 ((((x) & 0xfffffc0f) == 0xa0e00000) \
444 || (((x) & 0xfffffc0f) == 0xa4e00000) \
445 || (((x) & 0xfffffc0f) == 0xa8e00000) \
446 || (((x) & 0xfffffc0f) == 0xb4e00000) \
447 || (((x) & 0xfffffc0f) == 0xbce00000))
449 /* MOV Rm, Rn Rm-->Rn 0110 nnnn mmmm 0011
451 #define IS_COMPACT_IND_ARG_MOV(x) \
452 ((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0020) \
453 && (((x) & 0x00f0) <= 0x0090))
455 /* compact direct arg move!
456 MOV.L Rn, @r14 0010 1110 mmmm 0010 */
457 #define IS_COMPACT_ARG_MOV(x) \
458 (((((x) & 0xff0f) == 0x2e02) && (((x) & 0x00f0) >= 0x0020) \
459 && ((x) & 0x00f0) <= 0x0090))
461 /* MOV.B Rm, @R14 0010 1110 mmmm 0000
462 MOV.W Rm, @R14 0010 1110 mmmm 0001 */
463 #define IS_COMPACT_MOV_TO_R14(x) \
464 ((((x) & 0xff0f) == 0x2e00) || (((x) & 0xff0f) == 0x2e01))
466 #define IS_JSR_R0(x) ((x) == 0x400b)
467 #define IS_NOP(x) ((x) == 0x0009)
470 /* MOV r15,r14 0110111011110011
472 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
474 /* ADD #imm,r15 01111111iiiiiiii
476 #define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00)
478 /* Skip any prologue before the guts of a function. */
480 /* Skip the prologue using the debug information. If this fails we'll
481 fall back on the 'guess' method below. */
483 after_prologue (CORE_ADDR pc
)
485 struct symtab_and_line sal
;
486 CORE_ADDR func_addr
, func_end
;
488 /* If we can not find the symbol in the partial symbol table, then
489 there is no hope we can determine the function's start address
491 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
495 /* Get the line associated with FUNC_ADDR. */
496 sal
= find_pc_line (func_addr
, 0);
498 /* There are only two cases to consider. First, the end of the source line
499 is within the function bounds. In that case we return the end of the
500 source line. Second is the end of the source line extends beyond the
501 bounds of the current function. We need to use the slow code to
502 examine instructions in that case. */
503 if (sal
.end
< func_end
)
510 look_for_args_moves (struct gdbarch
*gdbarch
,
511 CORE_ADDR start_pc
, int media_mode
)
513 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
516 int insn_size
= (media_mode
? 4 : 2);
518 for (here
= start_pc
, end
= start_pc
+ (insn_size
* 28); here
< end
;)
522 w
= read_memory_integer (UNMAKE_ISA32_ADDR (here
),
523 insn_size
, byte_order
);
525 if (IS_MEDIA_IND_ARG_MOV (w
))
527 /* This must be followed by a store to r14, so the argument
528 is where the debug info says it is. This can happen after
529 the SP has been saved, unfortunately. */
531 int next_insn
= read_memory_integer (UNMAKE_ISA32_ADDR (here
),
532 insn_size
, byte_order
);
534 if (IS_MEDIA_MOV_TO_R14 (next_insn
))
537 else if (IS_MEDIA_ARG_MOV (w
))
539 /* These instructions store directly the argument in r14. */
547 w
= read_memory_integer (here
, insn_size
, byte_order
);
550 if (IS_COMPACT_IND_ARG_MOV (w
))
552 /* This must be followed by a store to r14, so the argument
553 is where the debug info says it is. This can happen after
554 the SP has been saved, unfortunately. */
556 int next_insn
= 0xffff & read_memory_integer (here
, insn_size
,
559 if (IS_COMPACT_MOV_TO_R14 (next_insn
))
562 else if (IS_COMPACT_ARG_MOV (w
))
564 /* These instructions store directly the argument in r14. */
567 else if (IS_MOVL_R0 (w
))
569 /* There is a function that gcc calls to get the arguments
570 passed correctly to the function. Only after this
571 function call the arguments will be found at the place
572 where they are supposed to be. This happens in case the
573 argument has to be stored into a 64-bit register (for
574 instance doubles, long longs). SHcompact doesn't have
575 access to the full 64-bits, so we store the register in
576 stack slot and store the address of the stack slot in
577 the register, then do a call through a wrapper that
578 loads the memory value into the register. A SHcompact
579 callee calls an argument decoder
580 (GCC_shcompact_incoming_args) that stores the 64-bit
581 value in a stack slot and stores the address of the
582 stack slot in the register. GCC thinks the argument is
583 just passed by transparent reference, but this is only
584 true after the argument decoder is called. Such a call
585 needs to be considered part of the prologue. */
587 /* This must be followed by a JSR @r0 instruction and by
588 a NOP instruction. After these, the prologue is over! */
590 int next_insn
= 0xffff & read_memory_integer (here
, insn_size
,
593 if (IS_JSR_R0 (next_insn
))
595 next_insn
= 0xffff & read_memory_integer (here
, insn_size
,
599 if (IS_NOP (next_insn
))
612 sh64_skip_prologue_hard_way (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
614 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
623 if (pc_is_isa32 (start_pc
) == 0)
629 for (here
= start_pc
, end
= start_pc
+ (insn_size
* 28); here
< end
;)
634 int w
= read_memory_integer (UNMAKE_ISA32_ADDR (here
),
635 insn_size
, byte_order
);
637 if (IS_STQ_R18_R14 (w
) || IS_STQ_R18_R15 (w
) || IS_STQ_R14_R15 (w
)
638 || IS_STL_R14_R15 (w
) || IS_STL_R18_R15 (w
)
639 || IS_ADDIL_SP_MEDIA (w
) || IS_ADDI_SP_MEDIA (w
)
640 || IS_PTABSL_R18 (w
))
644 else if (IS_MOV_SP_FP (w
) || IS_MOV_SP_FP_MEDIA(w
))
652 /* Don't bail out yet, we may have arguments stored in
653 registers here, according to the debug info, so that
654 gdb can print the frames correctly. */
655 start_pc
= look_for_args_moves (gdbarch
,
656 here
- insn_size
, media_mode
);
662 int w
= 0xffff & read_memory_integer (here
, insn_size
, byte_order
);
665 if (IS_STS_R0 (w
) || IS_STS_PR (w
)
666 || IS_MOV_TO_R15 (w
) || IS_MOV_R14 (w
)
667 || IS_MOV_R0 (w
) || IS_ADD_SP_R0 (w
) || IS_MOV_R14_R0 (w
))
671 else if (IS_MOV_SP_FP (w
))
679 /* Don't bail out yet, we may have arguments stored in
680 registers here, according to the debug info, so that
681 gdb can print the frames correctly. */
682 start_pc
= look_for_args_moves (gdbarch
,
683 here
- insn_size
, media_mode
);
693 sh64_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
695 CORE_ADDR post_prologue_pc
;
697 /* See if we can determine the end of the prologue via the symbol table.
698 If so, then return either PC, or the PC after the prologue, whichever
700 post_prologue_pc
= after_prologue (pc
);
702 /* If after_prologue returned a useful address, then use it. Else
703 fall back on the instruction skipping code. */
704 if (post_prologue_pc
!= 0)
705 return std::max (pc
, post_prologue_pc
);
707 return sh64_skip_prologue_hard_way (gdbarch
, pc
);
710 /* Should call_function allocate stack space for a struct return? */
712 sh64_use_struct_convention (struct type
*type
)
714 return (TYPE_LENGTH (type
) > 8);
717 /* For vectors of 4 floating point registers. */
719 sh64_fv_reg_base_num (struct gdbarch
*gdbarch
, int fv_regnum
)
723 fp_regnum
= gdbarch_fp0_regnum (gdbarch
) + (fv_regnum
- FV0_REGNUM
) * 4;
727 /* For double precision floating point registers, i.e 2 fp regs. */
729 sh64_dr_reg_base_num (struct gdbarch
*gdbarch
, int dr_regnum
)
733 fp_regnum
= gdbarch_fp0_regnum (gdbarch
) + (dr_regnum
- DR0_REGNUM
) * 2;
737 /* For pairs of floating point registers. */
739 sh64_fpp_reg_base_num (struct gdbarch
*gdbarch
, int fpp_regnum
)
743 fp_regnum
= gdbarch_fp0_regnum (gdbarch
) + (fpp_regnum
- FPP0_REGNUM
) * 2;
749 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
750 GDB_REGNUM BASE_REGNUM
810 sh64_compact_reg_base_num (struct gdbarch
*gdbarch
, int reg_nr
)
812 int base_regnum
= reg_nr
;
814 /* general register N maps to general register N */
815 if (reg_nr
>= R0_C_REGNUM
816 && reg_nr
<= R_LAST_C_REGNUM
)
817 base_regnum
= reg_nr
- R0_C_REGNUM
;
819 /* floating point register N maps to floating point register N */
820 else if (reg_nr
>= FP0_C_REGNUM
821 && reg_nr
<= FP_LAST_C_REGNUM
)
822 base_regnum
= reg_nr
- FP0_C_REGNUM
+ gdbarch_fp0_regnum (gdbarch
);
824 /* double prec register N maps to base regnum for double prec register N */
825 else if (reg_nr
>= DR0_C_REGNUM
826 && reg_nr
<= DR_LAST_C_REGNUM
)
827 base_regnum
= sh64_dr_reg_base_num (gdbarch
,
828 DR0_REGNUM
+ reg_nr
- DR0_C_REGNUM
);
830 /* vector N maps to base regnum for vector register N */
831 else if (reg_nr
>= FV0_C_REGNUM
832 && reg_nr
<= FV_LAST_C_REGNUM
)
833 base_regnum
= sh64_fv_reg_base_num (gdbarch
,
834 FV0_REGNUM
+ reg_nr
- FV0_C_REGNUM
);
836 else if (reg_nr
== PC_C_REGNUM
)
837 base_regnum
= gdbarch_pc_regnum (gdbarch
);
839 else if (reg_nr
== GBR_C_REGNUM
)
842 else if (reg_nr
== MACH_C_REGNUM
843 || reg_nr
== MACL_C_REGNUM
)
846 else if (reg_nr
== PR_C_REGNUM
)
847 base_regnum
= PR_REGNUM
;
849 else if (reg_nr
== T_C_REGNUM
)
852 else if (reg_nr
== FPSCR_C_REGNUM
)
853 base_regnum
= FPSCR_REGNUM
; /*???? this register is a mess. */
855 else if (reg_nr
== FPUL_C_REGNUM
)
856 base_regnum
= gdbarch_fp0_regnum (gdbarch
) + 32;
862 sign_extend (int value
, int bits
)
864 value
= value
& ((1 << bits
) - 1);
865 return (value
& (1 << (bits
- 1))
866 ? value
| (~((1 << bits
) - 1))
871 sh64_analyze_prologue (struct gdbarch
*gdbarch
,
872 struct sh64_frame_cache
*cache
,
874 CORE_ADDR current_pc
)
881 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
883 cache
->sp_offset
= 0;
885 /* Loop around examining the prologue insns until we find something
886 that does not appear to be part of the prologue. But give up
887 after 20 of them, since we're getting silly then. */
891 if (cache
->media_mode
)
896 opc
= pc
+ (insn_size
* 28);
897 if (opc
> current_pc
)
899 for ( ; pc
<= opc
; pc
+= insn_size
)
901 insn
= read_memory_integer (cache
->media_mode
? UNMAKE_ISA32_ADDR (pc
)
903 insn_size
, byte_order
);
905 if (!cache
->media_mode
)
907 if (IS_STS_PR (insn
))
909 int next_insn
= read_memory_integer (pc
+ insn_size
,
910 insn_size
, byte_order
);
911 if (IS_MOV_TO_R15 (next_insn
))
913 cache
->saved_regs
[PR_REGNUM
]
914 = cache
->sp_offset
- ((((next_insn
& 0xf) ^ 0x8)
920 else if (IS_MOV_R14 (insn
))
922 cache
->saved_regs
[MEDIA_FP_REGNUM
] =
923 cache
->sp_offset
- ((((insn
& 0xf) ^ 0x8) - 0x8) << 2);
927 else if (IS_MOV_R0 (insn
))
929 /* Put in R0 the offset from SP at which to store some
930 registers. We are interested in this value, because it
931 will tell us where the given registers are stored within
933 r0_val
= ((insn
& 0xff) ^ 0x80) - 0x80;
936 else if (IS_ADD_SP_R0 (insn
))
938 /* This instruction still prepares r0, but we don't care.
939 We already have the offset in r0_val. */
942 else if (IS_STS_R0 (insn
))
944 /* Store PR at r0_val-4 from SP. Decrement r0 by 4. */
945 cache
->saved_regs
[PR_REGNUM
] = cache
->sp_offset
- (r0_val
- 4);
949 else if (IS_MOV_R14_R0 (insn
))
951 /* Store R14 at r0_val-4 from SP. Decrement r0 by 4. */
952 cache
->saved_regs
[MEDIA_FP_REGNUM
] = cache
->sp_offset
958 else if (IS_ADD_SP (insn
))
959 cache
->sp_offset
-= ((insn
& 0xff) ^ 0x80) - 0x80;
961 else if (IS_MOV_SP_FP (insn
))
966 if (IS_ADDIL_SP_MEDIA (insn
) || IS_ADDI_SP_MEDIA (insn
))
968 sign_extend ((((insn
& 0xffc00) ^ 0x80000) - 0x80000) >> 10, 9);
970 else if (IS_STQ_R18_R15 (insn
))
971 cache
->saved_regs
[PR_REGNUM
]
972 = cache
->sp_offset
- (sign_extend ((insn
& 0xffc00) >> 10,
975 else if (IS_STL_R18_R15 (insn
))
976 cache
->saved_regs
[PR_REGNUM
]
977 = cache
->sp_offset
- (sign_extend ((insn
& 0xffc00) >> 10,
980 else if (IS_STQ_R14_R15 (insn
))
982 cache
->saved_regs
[MEDIA_FP_REGNUM
]
983 = cache
->sp_offset
- (sign_extend ((insn
& 0xffc00) >> 10,
988 else if (IS_STL_R14_R15 (insn
))
990 cache
->saved_regs
[MEDIA_FP_REGNUM
]
991 = cache
->sp_offset
- (sign_extend ((insn
& 0xffc00) >> 10,
996 else if (IS_MOV_SP_FP_MEDIA (insn
))
1003 sh64_frame_align (struct gdbarch
*ignore
, CORE_ADDR sp
)
1008 /* Function: push_dummy_call
1009 Setup the function arguments for calling a function in the inferior.
1011 On the Renesas SH architecture, there are four registers (R4 to R7)
1012 which are dedicated for passing function arguments. Up to the first
1013 four arguments (depending on size) may go into these registers.
1014 The rest go on the stack.
1016 Arguments that are smaller than 4 bytes will still take up a whole
1017 register or a whole 32-bit word on the stack, and will be
1018 right-justified in the register or the stack word. This includes
1019 chars, shorts, and small aggregate types.
1021 Arguments that are larger than 4 bytes may be split between two or
1022 more registers. If there are not enough registers free, an argument
1023 may be passed partly in a register (or registers), and partly on the
1024 stack. This includes doubles, long longs, and larger aggregates.
1025 As far as I know, there is no upper limit to the size of aggregates
1026 that will be passed in this way; in other words, the convention of
1027 passing a pointer to a large aggregate instead of a copy is not used.
1029 An exceptional case exists for struct arguments (and possibly other
1030 aggregates such as arrays) if the size is larger than 4 bytes but
1031 not a multiple of 4 bytes. In this case the argument is never split
1032 between the registers and the stack, but instead is copied in its
1033 entirety onto the stack, AND also copied into as many registers as
1034 there is room for. In other words, space in registers permitting,
1035 two copies of the same argument are passed in. As far as I can tell,
1036 only the one on the stack is used, although that may be a function
1037 of the level of compiler optimization. I suspect this is a compiler
1038 bug. Arguments of these odd sizes are left-justified within the
1039 word (as opposed to arguments smaller than 4 bytes, which are
1042 If the function is to return an aggregate type such as a struct, it
1043 is either returned in the normal return value register R0 (if its
1044 size is no greater than one byte), or else the caller must allocate
1045 space into which the callee will copy the return value (if the size
1046 is greater than one byte). In this case, a pointer to the return
1047 value location is passed into the callee in register R2, which does
1048 not displace any of the other arguments passed in via registers R4
1051 /* R2-R9 for integer types and integer equivalent (char, pointers) and
1052 non-scalar (struct, union) elements (even if the elements are
1054 FR0-FR11 for single precision floating point (float)
1055 DR0-DR10 for double precision floating point (double)
1057 If a float is argument number 3 (for instance) and arguments number
1058 1,2, and 4 are integer, the mapping will be:
1059 arg1 -->R2, arg2 --> R3, arg3 -->FR0, arg4 --> R5. I.e. R4 is not used.
1061 If a float is argument number 10 (for instance) and arguments number
1062 1 through 10 are integer, the mapping will be:
1063 arg1->R2, arg2->R3, arg3->R4, arg4->R5, arg5->R6, arg6->R7, arg7->R8,
1064 arg8->R9, arg9->(0,SP)stack(8-byte aligned), arg10->FR0,
1065 arg11->stack(16,SP). I.e. there is hole in the stack.
1067 Different rules apply for variable arguments functions, and for functions
1068 for which the prototype is not known. */
1071 sh64_push_dummy_call (struct gdbarch
*gdbarch
,
1072 struct value
*function
,
1073 struct regcache
*regcache
,
1075 int nargs
, struct value
**args
,
1076 CORE_ADDR sp
, int struct_return
,
1077 CORE_ADDR struct_addr
)
1079 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1080 int stack_offset
, stack_alloc
;
1082 int float_arg_index
= 0;
1083 int double_arg_index
= 0;
1087 const gdb_byte
*val
;
1093 memset (fp_args
, 0, sizeof (fp_args
));
1095 /* First force sp to a 8-byte alignment. */
1096 sp
= sh64_frame_align (gdbarch
, sp
);
1098 /* The "struct return pointer" pseudo-argument has its own dedicated
1102 regcache_cooked_write_unsigned (regcache
,
1103 STRUCT_RETURN_REGNUM
, struct_addr
);
1105 /* Now make sure there's space on the stack. */
1106 for (argnum
= 0, stack_alloc
= 0; argnum
< nargs
; argnum
++)
1107 stack_alloc
+= ((TYPE_LENGTH (value_type (args
[argnum
])) + 7) & ~7);
1108 sp
-= stack_alloc
; /* Make room on stack for args. */
1110 /* Now load as many as possible of the first arguments into
1111 registers, and push the rest onto the stack. There are 64 bytes
1112 in eight registers available. Loop thru args from first to last. */
1114 int_argreg
= ARG0_REGNUM
;
1116 for (argnum
= 0, stack_offset
= 0; argnum
< nargs
; argnum
++)
1118 type
= value_type (args
[argnum
]);
1119 len
= TYPE_LENGTH (type
);
1120 memset (valbuf
, 0, sizeof (valbuf
));
1122 if (TYPE_CODE (type
) != TYPE_CODE_FLT
)
1124 argreg_size
= register_size (gdbarch
, int_argreg
);
1126 if (len
< argreg_size
)
1128 /* value gets right-justified in the register or stack word. */
1129 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1130 memcpy (valbuf
+ argreg_size
- len
,
1131 value_contents (args
[argnum
]), len
);
1133 memcpy (valbuf
, value_contents (args
[argnum
]), len
);
1138 val
= value_contents (args
[argnum
]);
1142 if (int_argreg
> ARGLAST_REGNUM
)
1144 /* Must go on the stack. */
1145 write_memory (sp
+ stack_offset
, val
, argreg_size
);
1146 stack_offset
+= 8;/*argreg_size;*/
1148 /* NOTE WELL!!!!! This is not an "else if" clause!!!
1149 That's because some *&^%$ things get passed on the stack
1150 AND in the registers! */
1151 if (int_argreg
<= ARGLAST_REGNUM
)
1153 /* There's room in a register. */
1154 regval
= extract_unsigned_integer (val
, argreg_size
,
1156 regcache_cooked_write_unsigned (regcache
,
1157 int_argreg
, regval
);
1159 /* Store the value 8 bytes at a time. This means that
1160 things larger than 8 bytes may go partly in registers
1161 and partly on the stack. FIXME: argreg is incremented
1162 before we use its size. */
1170 val
= value_contents (args
[argnum
]);
1173 /* Where is it going to be stored? */
1174 while (fp_args
[float_arg_index
])
1177 /* Now float_argreg points to the register where it
1178 should be stored. Are we still within the allowed
1180 if (float_arg_index
<= FLOAT_ARGLAST_REGNUM
)
1182 /* Goes in FR0...FR11 */
1183 regcache_cooked_write (regcache
,
1184 gdbarch_fp0_regnum (gdbarch
)
1187 fp_args
[float_arg_index
] = 1;
1188 /* Skip the corresponding general argument register. */
1193 /* Store it as the integers, 8 bytes at the time, if
1194 necessary spilling on the stack. */
1199 /* Where is it going to be stored? */
1200 while (fp_args
[double_arg_index
])
1201 double_arg_index
+= 2;
1202 /* Now double_argreg points to the register
1203 where it should be stored.
1204 Are we still within the allowed register set? */
1205 if (double_arg_index
< FLOAT_ARGLAST_REGNUM
)
1207 /* Goes in DR0...DR10 */
1208 /* The numbering of the DRi registers is consecutive,
1209 i.e. includes odd numbers. */
1210 int double_register_offset
= double_arg_index
/ 2;
1211 int regnum
= DR0_REGNUM
+ double_register_offset
;
1212 regcache_cooked_write (regcache
, regnum
, val
);
1213 fp_args
[double_arg_index
] = 1;
1214 fp_args
[double_arg_index
+ 1] = 1;
1215 /* Skip the corresponding general argument register. */
1220 /* Store it as the integers, 8 bytes at the time, if
1221 necessary spilling on the stack. */
1226 /* Store return address. */
1227 regcache_cooked_write_unsigned (regcache
, PR_REGNUM
, bp_addr
);
1229 /* Update stack pointer. */
1230 regcache_cooked_write_unsigned (regcache
,
1231 gdbarch_sp_regnum (gdbarch
), sp
);
1236 /* Find a function's return value in the appropriate registers (in
1237 regbuf), and copy it into valbuf. Extract from an array REGBUF
1238 containing the (raw) register state a function return value of type
1239 TYPE, and copy that, in virtual format, into VALBUF. */
1241 sh64_extract_return_value (struct type
*type
, struct regcache
*regcache
,
1244 struct gdbarch
*gdbarch
= regcache
->arch ();
1245 int len
= TYPE_LENGTH (type
);
1247 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1251 /* Return value stored in gdbarch_fp0_regnum. */
1252 regcache_raw_read (regcache
,
1253 gdbarch_fp0_regnum (gdbarch
), valbuf
);
1257 /* return value stored in DR0_REGNUM. */
1259 regcache_cooked_read (regcache
, DR0_REGNUM
, buf
);
1261 convert_typed_floating (buf
, sh64_littlebyte_bigword_type (gdbarch
),
1271 /* Result is in register 2. If smaller than 8 bytes, it is padded
1272 at the most significant end. */
1273 regcache_raw_read (regcache
, DEFAULT_RETURN_REGNUM
, buf
);
1275 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1276 offset
= register_size (gdbarch
, DEFAULT_RETURN_REGNUM
)
1280 memcpy (valbuf
, buf
+ offset
, len
);
1283 error (_("bad size for return value"));
1287 /* Write into appropriate registers a function return value
1288 of type TYPE, given in virtual format.
1289 If the architecture is sh4 or sh3e, store a function's return value
1290 in the R0 general register or in the FP0 floating point register,
1291 depending on the type of the return value. In all the other cases
1292 the result is stored in r0, left-justified. */
1295 sh64_store_return_value (struct type
*type
, struct regcache
*regcache
,
1296 const gdb_byte
*valbuf
)
1298 struct gdbarch
*gdbarch
= regcache
->arch ();
1299 gdb_byte buf
[64]; /* more than enough... */
1300 int len
= TYPE_LENGTH (type
);
1302 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1304 int i
, regnum
= gdbarch_fp0_regnum (gdbarch
);
1305 for (i
= 0; i
< len
; i
+= 4)
1306 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
1307 regcache_raw_write (regcache
, regnum
++,
1308 valbuf
+ len
- 4 - i
);
1310 regcache_raw_write (regcache
, regnum
++, valbuf
+ i
);
1314 int return_register
= DEFAULT_RETURN_REGNUM
;
1317 if (len
<= register_size (gdbarch
, return_register
))
1319 /* Pad with zeros. */
1320 memset (buf
, 0, register_size (gdbarch
, return_register
));
1321 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
1322 offset
= 0; /*register_size (gdbarch,
1323 return_register) - len;*/
1325 offset
= register_size (gdbarch
, return_register
) - len
;
1327 memcpy (buf
+ offset
, valbuf
, len
);
1328 regcache_raw_write (regcache
, return_register
, buf
);
1331 regcache_raw_write (regcache
, return_register
, valbuf
);
1335 static enum return_value_convention
1336 sh64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
1337 struct type
*type
, struct regcache
*regcache
,
1338 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1340 if (sh64_use_struct_convention (type
))
1341 return RETURN_VALUE_STRUCT_CONVENTION
;
1343 sh64_store_return_value (type
, regcache
, writebuf
);
1345 sh64_extract_return_value (type
, regcache
, readbuf
);
1346 return RETURN_VALUE_REGISTER_CONVENTION
;
1351 SH MEDIA MODE (ISA 32)
1352 general registers (64-bit) 0-63
1353 0 r0, r1, r2, r3, r4, r5, r6, r7,
1354 64 r8, r9, r10, r11, r12, r13, r14, r15,
1355 128 r16, r17, r18, r19, r20, r21, r22, r23,
1356 192 r24, r25, r26, r27, r28, r29, r30, r31,
1357 256 r32, r33, r34, r35, r36, r37, r38, r39,
1358 320 r40, r41, r42, r43, r44, r45, r46, r47,
1359 384 r48, r49, r50, r51, r52, r53, r54, r55,
1360 448 r56, r57, r58, r59, r60, r61, r62, r63,
1365 status reg., saved status reg., saved pc reg. (64-bit) 65-67
1368 target registers (64-bit) 68-75
1369 544 tr0, tr1, tr2, tr3, tr4, tr5, tr6, tr7,
1371 floating point state control register (32-bit) 76
1374 single precision floating point registers (32-bit) 77-140
1375 612 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
1376 644 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15,
1377 676 fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23,
1378 708 fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31,
1379 740 fr32, fr33, fr34, fr35, fr36, fr37, fr38, fr39,
1380 772 fr40, fr41, fr42, fr43, fr44, fr45, fr46, fr47,
1381 804 fr48, fr49, fr50, fr51, fr52, fr53, fr54, fr55,
1382 836 fr56, fr57, fr58, fr59, fr60, fr61, fr62, fr63,
1384 TOTAL SPACE FOR REGISTERS: 868 bytes
1386 From here on they are all pseudo registers: no memory allocated.
1387 REGISTER_BYTE returns the register byte for the base register.
1389 double precision registers (pseudo) 141-172
1390 dr0, dr2, dr4, dr6, dr8, dr10, dr12, dr14,
1391 dr16, dr18, dr20, dr22, dr24, dr26, dr28, dr30,
1392 dr32, dr34, dr36, dr38, dr40, dr42, dr44, dr46,
1393 dr48, dr50, dr52, dr54, dr56, dr58, dr60, dr62,
1395 floating point pairs (pseudo) 173-204
1396 fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14,
1397 fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30,
1398 fp32, fp34, fp36, fp38, fp40, fp42, fp44, fp46,
1399 fp48, fp50, fp52, fp54, fp56, fp58, fp60, fp62,
1401 floating point vectors (4 floating point regs) (pseudo) 205-220
1402 fv0, fv4, fv8, fv12, fv16, fv20, fv24, fv28,
1403 fv32, fv36, fv40, fv44, fv48, fv52, fv56, fv60,
1405 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
1406 r0_c, r1_c, r2_c, r3_c, r4_c, r5_c, r6_c, r7_c,
1407 r8_c, r9_c, r10_c, r11_c, r12_c, r13_c, r14_c, r15_c,
1409 gbr_c, mach_c, macl_c, pr_c, t_c,
1411 fr0_c, fr1_c, fr2_c, fr3_c, fr4_c, fr5_c, fr6_c, fr7_c,
1412 fr8_c, fr9_c, fr10_c, fr11_c, fr12_c, fr13_c, fr14_c, fr15_c
1413 dr0_c, dr2_c, dr4_c, dr6_c, dr8_c, dr10_c, dr12_c, dr14_c
1414 fv0_c, fv4_c, fv8_c, fv12_c
1417 static struct type
*
1418 sh64_build_float_register_type (struct gdbarch
*gdbarch
, int high
)
1420 return lookup_array_range_type (builtin_type (gdbarch
)->builtin_float
,
1424 /* Return the GDB type object for the "standard" data type
1425 of data in register REG_NR. */
1426 static struct type
*
1427 sh64_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
1429 if ((reg_nr
>= gdbarch_fp0_regnum (gdbarch
)
1430 && reg_nr
<= FP_LAST_REGNUM
)
1431 || (reg_nr
>= FP0_C_REGNUM
1432 && reg_nr
<= FP_LAST_C_REGNUM
))
1433 return builtin_type (gdbarch
)->builtin_float
;
1434 else if ((reg_nr
>= DR0_REGNUM
1435 && reg_nr
<= DR_LAST_REGNUM
)
1436 || (reg_nr
>= DR0_C_REGNUM
1437 && reg_nr
<= DR_LAST_C_REGNUM
))
1438 return builtin_type (gdbarch
)->builtin_double
;
1439 else if (reg_nr
>= FPP0_REGNUM
1440 && reg_nr
<= FPP_LAST_REGNUM
)
1441 return sh64_build_float_register_type (gdbarch
, 1);
1442 else if ((reg_nr
>= FV0_REGNUM
1443 && reg_nr
<= FV_LAST_REGNUM
)
1444 ||(reg_nr
>= FV0_C_REGNUM
1445 && reg_nr
<= FV_LAST_C_REGNUM
))
1446 return sh64_build_float_register_type (gdbarch
, 3);
1447 else if (reg_nr
== FPSCR_REGNUM
)
1448 return builtin_type (gdbarch
)->builtin_int
;
1449 else if (reg_nr
>= R0_C_REGNUM
1450 && reg_nr
< FP0_C_REGNUM
)
1451 return builtin_type (gdbarch
)->builtin_int
;
1453 return builtin_type (gdbarch
)->builtin_long_long
;
1457 sh64_register_convert_to_virtual (struct gdbarch
*gdbarch
, int regnum
,
1458 struct type
*type
, gdb_byte
*from
, gdb_byte
*to
)
1460 if (gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_LITTLE
)
1462 /* It is a no-op. */
1463 memcpy (to
, from
, register_size (gdbarch
, regnum
));
1467 if ((regnum
>= DR0_REGNUM
1468 && regnum
<= DR_LAST_REGNUM
)
1469 || (regnum
>= DR0_C_REGNUM
1470 && regnum
<= DR_LAST_C_REGNUM
))
1471 convert_typed_floating (from
, sh64_littlebyte_bigword_type (gdbarch
),
1474 error (_("sh64_register_convert_to_virtual "
1475 "called with non DR register number"));
1479 sh64_register_convert_to_raw (struct gdbarch
*gdbarch
, struct type
*type
,
1480 int regnum
, const void *from
, void *to
)
1482 if (gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_LITTLE
)
1484 /* It is a no-op. */
1485 memcpy (to
, from
, register_size (gdbarch
, regnum
));
1489 if ((regnum
>= DR0_REGNUM
1490 && regnum
<= DR_LAST_REGNUM
)
1491 || (regnum
>= DR0_C_REGNUM
1492 && regnum
<= DR_LAST_C_REGNUM
))
1493 convert_typed_floating (from
, type
,
1494 to
, sh64_littlebyte_bigword_type (gdbarch
));
1496 error (_("sh64_register_convert_to_raw called "
1497 "with non DR register number"));
1500 /* Concatenate PORTIONS contiguous raw registers starting at
1501 BASE_REGNUM into BUFFER. */
1503 static enum register_status
1504 pseudo_register_read_portions (struct gdbarch
*gdbarch
,
1505 struct regcache
*regcache
,
1507 int base_regnum
, gdb_byte
*buffer
)
1511 for (portion
= 0; portion
< portions
; portion
++)
1513 enum register_status status
;
1516 b
= buffer
+ register_size (gdbarch
, base_regnum
) * portion
;
1517 status
= regcache_raw_read (regcache
, base_regnum
+ portion
, b
);
1518 if (status
!= REG_VALID
)
1525 static enum register_status
1526 sh64_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1527 int reg_nr
, gdb_byte
*buffer
)
1529 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1532 enum register_status status
;
1534 if (reg_nr
>= DR0_REGNUM
1535 && reg_nr
<= DR_LAST_REGNUM
)
1537 gdb_byte temp_buffer
[8];
1538 base_regnum
= sh64_dr_reg_base_num (gdbarch
, reg_nr
);
1540 /* Build the value in the provided buffer. */
1541 /* DR regs are double precision registers obtained by
1542 concatenating 2 single precision floating point registers. */
1543 status
= pseudo_register_read_portions (gdbarch
, regcache
,
1544 2, base_regnum
, temp_buffer
);
1545 if (status
== REG_VALID
)
1547 /* We must pay attention to the endianness. */
1548 sh64_register_convert_to_virtual (gdbarch
, reg_nr
,
1549 register_type (gdbarch
, reg_nr
),
1550 temp_buffer
, buffer
);
1556 else if (reg_nr
>= FPP0_REGNUM
1557 && reg_nr
<= FPP_LAST_REGNUM
)
1559 base_regnum
= sh64_fpp_reg_base_num (gdbarch
, reg_nr
);
1561 /* Build the value in the provided buffer. */
1562 /* FPP regs are pairs of single precision registers obtained by
1563 concatenating 2 single precision floating point registers. */
1564 return pseudo_register_read_portions (gdbarch
, regcache
,
1565 2, base_regnum
, buffer
);
1568 else if (reg_nr
>= FV0_REGNUM
1569 && reg_nr
<= FV_LAST_REGNUM
)
1571 base_regnum
= sh64_fv_reg_base_num (gdbarch
, reg_nr
);
1573 /* Build the value in the provided buffer. */
1574 /* FV regs are vectors of single precision registers obtained by
1575 concatenating 4 single precision floating point registers. */
1576 return pseudo_register_read_portions (gdbarch
, regcache
,
1577 4, base_regnum
, buffer
);
1580 /* sh compact pseudo registers. 1-to-1 with a shmedia register. */
1581 else if (reg_nr
>= R0_C_REGNUM
1582 && reg_nr
<= T_C_REGNUM
)
1584 gdb_byte temp_buffer
[8];
1585 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1587 /* Build the value in the provided buffer. */
1588 status
= regcache_raw_read (regcache
, base_regnum
, temp_buffer
);
1589 if (status
!= REG_VALID
)
1591 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1594 temp_buffer
+ offset
, 4); /* get LOWER 32 bits only???? */
1598 else if (reg_nr
>= FP0_C_REGNUM
1599 && reg_nr
<= FP_LAST_C_REGNUM
)
1601 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1603 /* Build the value in the provided buffer. */
1604 /* Floating point registers map 1-1 to the media fp regs,
1605 they have the same size and endianness. */
1606 return regcache_raw_read (regcache
, base_regnum
, buffer
);
1609 else if (reg_nr
>= DR0_C_REGNUM
1610 && reg_nr
<= DR_LAST_C_REGNUM
)
1612 gdb_byte temp_buffer
[8];
1613 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1615 /* DR_C regs are double precision registers obtained by
1616 concatenating 2 single precision floating point registers. */
1617 status
= pseudo_register_read_portions (gdbarch
, regcache
,
1618 2, base_regnum
, temp_buffer
);
1619 if (status
== REG_VALID
)
1621 /* We must pay attention to the endianness. */
1622 sh64_register_convert_to_virtual (gdbarch
, reg_nr
,
1623 register_type (gdbarch
, reg_nr
),
1624 temp_buffer
, buffer
);
1629 else if (reg_nr
>= FV0_C_REGNUM
1630 && reg_nr
<= FV_LAST_C_REGNUM
)
1632 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1634 /* Build the value in the provided buffer. */
1635 /* FV_C regs are vectors of single precision registers obtained by
1636 concatenating 4 single precision floating point registers. */
1637 return pseudo_register_read_portions (gdbarch
, regcache
,
1638 4, base_regnum
, buffer
);
1641 else if (reg_nr
== FPSCR_C_REGNUM
)
1643 int fpscr_base_regnum
;
1645 ULONGEST fpscr_value
;
1647 unsigned int fpscr_c_value
;
1648 unsigned int fpscr_c_part1_value
;
1649 unsigned int fpscr_c_part2_value
;
1651 fpscr_base_regnum
= FPSCR_REGNUM
;
1652 sr_base_regnum
= SR_REGNUM
;
1654 /* Build the value in the provided buffer. */
1655 /* FPSCR_C is a very weird register that contains sparse bits
1656 from the FPSCR and the SR architectural registers.
1663 2-17 Bit 2-18 of FPSCR
1664 18-20 Bits 12,13,14 of SR
1668 /* Get FPSCR as an int. */
1669 status
= regcache
->raw_read (fpscr_base_regnum
, &fpscr_value
);
1670 if (status
!= REG_VALID
)
1672 /* Get SR as an int. */
1673 status
= regcache
->raw_read (sr_base_regnum
, &sr_value
);
1674 if (status
!= REG_VALID
)
1676 /* Build the new value. */
1677 fpscr_c_part1_value
= fpscr_value
& 0x3fffd;
1678 fpscr_c_part2_value
= (sr_value
& 0x7000) << 6;
1679 fpscr_c_value
= fpscr_c_part1_value
| fpscr_c_part2_value
;
1680 /* Store that in out buffer!!! */
1681 store_unsigned_integer (buffer
, 4, byte_order
, fpscr_c_value
);
1682 /* FIXME There is surely an endianness gotcha here. */
1687 else if (reg_nr
== FPUL_C_REGNUM
)
1689 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1691 /* FPUL_C register is floating point register 32,
1692 same size, same endianness. */
1693 return regcache_raw_read (regcache
, base_regnum
, buffer
);
1696 gdb_assert_not_reached ("invalid pseudo register number");
1700 sh64_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1701 int reg_nr
, const gdb_byte
*buffer
)
1703 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1704 int base_regnum
, portion
;
1707 if (reg_nr
>= DR0_REGNUM
1708 && reg_nr
<= DR_LAST_REGNUM
)
1710 gdb_byte temp_buffer
[8];
1711 base_regnum
= sh64_dr_reg_base_num (gdbarch
, reg_nr
);
1712 /* We must pay attention to the endianness. */
1713 sh64_register_convert_to_raw (gdbarch
, register_type (gdbarch
, reg_nr
),
1715 buffer
, temp_buffer
);
1717 /* Write the real regs for which this one is an alias. */
1718 for (portion
= 0; portion
< 2; portion
++)
1719 regcache_raw_write (regcache
, base_regnum
+ portion
,
1721 + register_size (gdbarch
,
1722 base_regnum
) * portion
));
1725 else if (reg_nr
>= FPP0_REGNUM
1726 && reg_nr
<= FPP_LAST_REGNUM
)
1728 base_regnum
= sh64_fpp_reg_base_num (gdbarch
, reg_nr
);
1730 /* Write the real regs for which this one is an alias. */
1731 for (portion
= 0; portion
< 2; portion
++)
1732 regcache_raw_write (regcache
, base_regnum
+ portion
,
1733 (buffer
+ register_size (gdbarch
,
1734 base_regnum
) * portion
));
1737 else if (reg_nr
>= FV0_REGNUM
1738 && reg_nr
<= FV_LAST_REGNUM
)
1740 base_regnum
= sh64_fv_reg_base_num (gdbarch
, reg_nr
);
1742 /* Write the real regs for which this one is an alias. */
1743 for (portion
= 0; portion
< 4; portion
++)
1744 regcache_raw_write (regcache
, base_regnum
+ portion
,
1745 (buffer
+ register_size (gdbarch
,
1746 base_regnum
) * portion
));
1749 /* sh compact general pseudo registers. 1-to-1 with a shmedia
1750 register but only 4 bytes of it. */
1751 else if (reg_nr
>= R0_C_REGNUM
1752 && reg_nr
<= T_C_REGNUM
)
1754 gdb_byte temp_buffer
[8];
1755 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1756 /* reg_nr is 32 bit here, and base_regnum is 64 bits. */
1757 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1761 /* Let's read the value of the base register into a temporary
1762 buffer, so that overwriting the last four bytes with the new
1763 value of the pseudo will leave the upper 4 bytes unchanged. */
1764 regcache_raw_read (regcache
, base_regnum
, temp_buffer
);
1765 /* Write as an 8 byte quantity. */
1766 memcpy (temp_buffer
+ offset
, buffer
, 4);
1767 regcache_raw_write (regcache
, base_regnum
, temp_buffer
);
1770 /* sh floating point compact pseudo registers. 1-to-1 with a shmedia
1771 registers. Both are 4 bytes. */
1772 else if (reg_nr
>= FP0_C_REGNUM
1773 && reg_nr
<= FP_LAST_C_REGNUM
)
1775 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1776 regcache_raw_write (regcache
, base_regnum
, buffer
);
1779 else if (reg_nr
>= DR0_C_REGNUM
1780 && reg_nr
<= DR_LAST_C_REGNUM
)
1782 gdb_byte temp_buffer
[8];
1783 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1784 for (portion
= 0; portion
< 2; portion
++)
1786 /* We must pay attention to the endianness. */
1787 sh64_register_convert_to_raw (gdbarch
,
1788 register_type (gdbarch
, reg_nr
),
1790 buffer
, temp_buffer
);
1792 regcache_raw_write (regcache
, base_regnum
+ portion
,
1794 + register_size (gdbarch
,
1795 base_regnum
) * portion
));
1799 else if (reg_nr
>= FV0_C_REGNUM
1800 && reg_nr
<= FV_LAST_C_REGNUM
)
1802 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1804 for (portion
= 0; portion
< 4; portion
++)
1806 regcache_raw_write (regcache
, base_regnum
+ portion
,
1808 + register_size (gdbarch
,
1809 base_regnum
) * portion
));
1813 else if (reg_nr
== FPSCR_C_REGNUM
)
1815 int fpscr_base_regnum
;
1817 ULONGEST fpscr_value
;
1819 ULONGEST old_fpscr_value
;
1820 ULONGEST old_sr_value
;
1821 unsigned int fpscr_c_value
;
1822 unsigned int fpscr_mask
;
1823 unsigned int sr_mask
;
1825 fpscr_base_regnum
= FPSCR_REGNUM
;
1826 sr_base_regnum
= SR_REGNUM
;
1828 /* FPSCR_C is a very weird register that contains sparse bits
1829 from the FPSCR and the SR architectural registers.
1836 2-17 Bit 2-18 of FPSCR
1837 18-20 Bits 12,13,14 of SR
1841 /* Get value as an int. */
1842 fpscr_c_value
= extract_unsigned_integer (buffer
, 4, byte_order
);
1844 /* Build the new values. */
1845 fpscr_mask
= 0x0003fffd;
1846 sr_mask
= 0x001c0000;
1848 fpscr_value
= fpscr_c_value
& fpscr_mask
;
1849 sr_value
= (fpscr_value
& sr_mask
) >> 6;
1851 regcache
->raw_read (fpscr_base_regnum
, &old_fpscr_value
);
1852 old_fpscr_value
&= 0xfffc0002;
1853 fpscr_value
|= old_fpscr_value
;
1854 regcache
->raw_write (fpscr_base_regnum
, fpscr_value
);
1856 regcache
->raw_read (sr_base_regnum
, &old_sr_value
);
1857 old_sr_value
&= 0xffff8fff;
1858 sr_value
|= old_sr_value
;
1859 regcache
->raw_write (sr_base_regnum
, sr_value
);
1862 else if (reg_nr
== FPUL_C_REGNUM
)
1864 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1865 regcache_raw_write (regcache
, base_regnum
, buffer
);
1869 /* FIXME:!! THIS SHOULD TAKE CARE OF GETTING THE RIGHT PORTION OF THE
1870 shmedia REGISTERS. */
1871 /* Control registers, compact mode. */
1873 sh64_do_cr_c_register_info (struct ui_file
*file
, struct frame_info
*frame
,
1876 switch (cr_c_regnum
)
1879 fprintf_filtered (file
, "pc_c\t0x%08x\n",
1880 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1883 fprintf_filtered (file
, "gbr_c\t0x%08x\n",
1884 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1887 fprintf_filtered (file
, "mach_c\t0x%08x\n",
1888 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1891 fprintf_filtered (file
, "macl_c\t0x%08x\n",
1892 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1895 fprintf_filtered (file
, "pr_c\t0x%08x\n",
1896 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1899 fprintf_filtered (file
, "t_c\t0x%08x\n",
1900 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1902 case FPSCR_C_REGNUM
:
1903 fprintf_filtered (file
, "fpscr_c\t0x%08x\n",
1904 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1907 fprintf_filtered (file
, "fpul_c\t0x%08x\n",
1908 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1914 sh64_do_fp_register (struct gdbarch
*gdbarch
, struct ui_file
*file
,
1915 struct frame_info
*frame
, int regnum
)
1916 { /* Do values for FP (float) regs. */
1917 unsigned char *raw_buffer
;
1919 /* Allocate space for the float. */
1920 raw_buffer
= (unsigned char *)
1921 alloca (register_size (gdbarch
, gdbarch_fp0_regnum (gdbarch
)));
1923 /* Get the data in raw format. */
1924 if (!deprecated_frame_register_read (frame
, regnum
, raw_buffer
))
1925 error (_("can't read register %d (%s)"),
1926 regnum
, gdbarch_register_name (gdbarch
, regnum
));
1928 /* Print the name and some spaces. */
1929 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
1930 print_spaces_filtered (15 - strlen (gdbarch_register_name
1931 (gdbarch
, regnum
)), file
);
1933 /* Print the value. */
1934 const struct floatformat
*fmt
1935 = floatformat_from_type (builtin_type (gdbarch
)->builtin_float
);
1936 std::string str
= floatformat_to_string (fmt
, raw_buffer
, "%-10.9g");
1937 fprintf_filtered (file
, "%s", str
.c_str ());
1939 /* Print the fp register as hex. */
1940 fprintf_filtered (file
, "\t(raw ");
1941 print_hex_chars (file
, raw_buffer
,
1942 register_size (gdbarch
, regnum
),
1943 gdbarch_byte_order (gdbarch
), true);
1944 fprintf_filtered (file
, ")");
1945 fprintf_filtered (file
, "\n");
1949 sh64_do_pseudo_register (struct gdbarch
*gdbarch
, struct ui_file
*file
,
1950 struct frame_info
*frame
, int regnum
)
1952 /* All the sh64-compact mode registers are pseudo registers. */
1954 if (regnum
< gdbarch_num_regs (gdbarch
)
1955 || regnum
>= gdbarch_num_regs (gdbarch
)
1956 + NUM_PSEUDO_REGS_SH_MEDIA
1957 + NUM_PSEUDO_REGS_SH_COMPACT
)
1958 internal_error (__FILE__
, __LINE__
,
1959 _("Invalid pseudo register number %d\n"), regnum
);
1961 else if ((regnum
>= DR0_REGNUM
&& regnum
<= DR_LAST_REGNUM
))
1963 int fp_regnum
= sh64_dr_reg_base_num (gdbarch
, regnum
);
1964 fprintf_filtered (file
, "dr%d\t0x%08x%08x\n", regnum
- DR0_REGNUM
,
1965 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
),
1966 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 1));
1969 else if ((regnum
>= DR0_C_REGNUM
&& regnum
<= DR_LAST_C_REGNUM
))
1971 int fp_regnum
= sh64_compact_reg_base_num (gdbarch
, regnum
);
1972 fprintf_filtered (file
, "dr%d_c\t0x%08x%08x\n", regnum
- DR0_C_REGNUM
,
1973 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
),
1974 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 1));
1977 else if ((regnum
>= FV0_REGNUM
&& regnum
<= FV_LAST_REGNUM
))
1979 int fp_regnum
= sh64_fv_reg_base_num (gdbarch
, regnum
);
1980 fprintf_filtered (file
, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
1981 regnum
- FV0_REGNUM
,
1982 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
),
1983 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 1),
1984 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 2),
1985 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 3));
1988 else if ((regnum
>= FV0_C_REGNUM
&& regnum
<= FV_LAST_C_REGNUM
))
1990 int fp_regnum
= sh64_compact_reg_base_num (gdbarch
, regnum
);
1991 fprintf_filtered (file
, "fv%d_c\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
1992 regnum
- FV0_C_REGNUM
,
1993 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
),
1994 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 1),
1995 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 2),
1996 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 3));
1999 else if (regnum
>= FPP0_REGNUM
&& regnum
<= FPP_LAST_REGNUM
)
2001 int fp_regnum
= sh64_fpp_reg_base_num (gdbarch
, regnum
);
2002 fprintf_filtered (file
, "fpp%d\t0x%08x\t0x%08x\n", regnum
- FPP0_REGNUM
,
2003 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
),
2004 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 1));
2007 else if (regnum
>= R0_C_REGNUM
&& regnum
<= R_LAST_C_REGNUM
)
2009 int c_regnum
= sh64_compact_reg_base_num (gdbarch
, regnum
);
2010 fprintf_filtered (file
, "r%d_c\t0x%08x\n", regnum
- R0_C_REGNUM
,
2011 (unsigned) get_frame_register_unsigned (frame
, c_regnum
));
2013 else if (regnum
>= FP0_C_REGNUM
&& regnum
<= FP_LAST_C_REGNUM
)
2014 /* This should work also for pseudoregs. */
2015 sh64_do_fp_register (gdbarch
, file
, frame
, regnum
);
2016 else if (regnum
>= PC_C_REGNUM
&& regnum
<= FPUL_C_REGNUM
)
2017 sh64_do_cr_c_register_info (file
, frame
, regnum
);
2021 sh64_do_register (struct gdbarch
*gdbarch
, struct ui_file
*file
,
2022 struct frame_info
*frame
, int regnum
)
2024 struct value_print_options opts
;
2027 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
2028 print_spaces_filtered (15 - strlen (gdbarch_register_name
2029 (gdbarch
, regnum
)), file
);
2031 /* Get the data in raw format. */
2032 val
= get_frame_register_value (frame
, regnum
);
2033 if (value_optimized_out (val
) || !value_entirely_available (val
))
2035 fprintf_filtered (file
, "*value not available*\n");
2039 get_formatted_print_options (&opts
, 'x');
2041 val_print (register_type (gdbarch
, regnum
),
2043 file
, 0, val
, &opts
, current_language
);
2044 fprintf_filtered (file
, "\t");
2045 get_formatted_print_options (&opts
, 0);
2047 val_print (register_type (gdbarch
, regnum
),
2049 file
, 0, val
, &opts
, current_language
);
2050 fprintf_filtered (file
, "\n");
2054 sh64_print_register (struct gdbarch
*gdbarch
, struct ui_file
*file
,
2055 struct frame_info
*frame
, int regnum
)
2057 if (regnum
< 0 || regnum
>= gdbarch_num_regs (gdbarch
)
2058 + gdbarch_num_pseudo_regs (gdbarch
))
2059 internal_error (__FILE__
, __LINE__
,
2060 _("Invalid register number %d\n"), regnum
);
2062 else if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
))
2064 if (TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
2065 sh64_do_fp_register (gdbarch
, file
, frame
, regnum
); /* FP regs */
2067 sh64_do_register (gdbarch
, file
, frame
, regnum
);
2070 else if (regnum
< gdbarch_num_regs (gdbarch
)
2071 + gdbarch_num_pseudo_regs (gdbarch
))
2072 sh64_do_pseudo_register (gdbarch
, file
, frame
, regnum
);
2076 sh64_media_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
2077 struct frame_info
*frame
, int regnum
,
2080 if (regnum
!= -1) /* Do one specified register. */
2082 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
2083 error (_("Not a valid register for the current processor type"));
2085 sh64_print_register (gdbarch
, file
, frame
, regnum
);
2088 /* Do all (or most) registers. */
2091 while (regnum
< gdbarch_num_regs (gdbarch
))
2093 /* If the register name is empty, it is undefined for this
2094 processor, so don't display anything. */
2095 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
2096 || *(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
2102 if (TYPE_CODE (register_type (gdbarch
, regnum
))
2107 /* true for "INFO ALL-REGISTERS" command. */
2108 sh64_do_fp_register (gdbarch
, file
, frame
, regnum
);
2112 regnum
+= FP_LAST_REGNUM
- gdbarch_fp0_regnum (gdbarch
);
2117 sh64_do_register (gdbarch
, file
, frame
, regnum
);
2123 while (regnum
< gdbarch_num_regs (gdbarch
)
2124 + gdbarch_num_pseudo_regs (gdbarch
))
2126 sh64_do_pseudo_register (gdbarch
, file
, frame
, regnum
);
2133 sh64_compact_print_registers_info (struct gdbarch
*gdbarch
,
2134 struct ui_file
*file
,
2135 struct frame_info
*frame
, int regnum
,
2138 if (regnum
!= -1) /* Do one specified register. */
2140 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
2141 error (_("Not a valid register for the current processor type"));
2143 if (regnum
>= 0 && regnum
< R0_C_REGNUM
)
2144 error (_("Not a valid register for the current processor mode."));
2146 sh64_print_register (gdbarch
, file
, frame
, regnum
);
2149 /* Do all compact registers. */
2151 regnum
= R0_C_REGNUM
;
2152 while (regnum
< gdbarch_num_regs (gdbarch
)
2153 + gdbarch_num_pseudo_regs (gdbarch
))
2155 sh64_do_pseudo_register (gdbarch
, file
, frame
, regnum
);
2162 sh64_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
2163 struct frame_info
*frame
, int regnum
, int fpregs
)
2165 if (pc_is_isa32 (get_frame_pc (frame
)))
2166 sh64_media_print_registers_info (gdbarch
, file
, frame
, regnum
, fpregs
);
2168 sh64_compact_print_registers_info (gdbarch
, file
, frame
, regnum
, fpregs
);
2171 static struct sh64_frame_cache
*
2172 sh64_alloc_frame_cache (void)
2174 struct sh64_frame_cache
*cache
;
2177 cache
= FRAME_OBSTACK_ZALLOC (struct sh64_frame_cache
);
2181 cache
->saved_sp
= 0;
2182 cache
->sp_offset
= 0;
2185 /* Frameless until proven otherwise. */
2188 /* Saved registers. We initialize these to -1 since zero is a valid
2189 offset (that's where fp is supposed to be stored). */
2190 for (i
= 0; i
< SIM_SH64_NR_REGS
; i
++)
2192 cache
->saved_regs
[i
] = -1;
2198 static struct sh64_frame_cache
*
2199 sh64_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2201 struct gdbarch
*gdbarch
;
2202 struct sh64_frame_cache
*cache
;
2203 CORE_ADDR current_pc
;
2207 return (struct sh64_frame_cache
*) *this_cache
;
2209 gdbarch
= get_frame_arch (this_frame
);
2210 cache
= sh64_alloc_frame_cache ();
2211 *this_cache
= cache
;
2213 current_pc
= get_frame_pc (this_frame
);
2214 cache
->media_mode
= pc_is_isa32 (current_pc
);
2216 /* In principle, for normal frames, fp holds the frame pointer,
2217 which holds the base address for the current stack frame.
2218 However, for functions that don't need it, the frame pointer is
2219 optional. For these "frameless" functions the frame pointer is
2220 actually the frame pointer of the calling frame. */
2221 cache
->base
= get_frame_register_unsigned (this_frame
, MEDIA_FP_REGNUM
);
2222 if (cache
->base
== 0)
2225 cache
->pc
= get_frame_func (this_frame
);
2227 sh64_analyze_prologue (gdbarch
, cache
, cache
->pc
, current_pc
);
2229 if (!cache
->uses_fp
)
2231 /* We didn't find a valid frame, which means that CACHE->base
2232 currently holds the frame pointer for our calling frame. If
2233 we're at the start of a function, or somewhere half-way its
2234 prologue, the function's frame probably hasn't been fully
2235 setup yet. Try to reconstruct the base address for the stack
2236 frame by looking at the stack pointer. For truly "frameless"
2237 functions this might work too. */
2238 cache
->base
= get_frame_register_unsigned
2239 (this_frame
, gdbarch_sp_regnum (gdbarch
));
2242 /* Now that we have the base address for the stack frame we can
2243 calculate the value of sp in the calling frame. */
2244 cache
->saved_sp
= cache
->base
+ cache
->sp_offset
;
2246 /* Adjust all the saved registers such that they contain addresses
2247 instead of offsets. */
2248 for (i
= 0; i
< SIM_SH64_NR_REGS
; i
++)
2249 if (cache
->saved_regs
[i
] != -1)
2250 cache
->saved_regs
[i
] = cache
->saved_sp
- cache
->saved_regs
[i
];
2255 static struct value
*
2256 sh64_frame_prev_register (struct frame_info
*this_frame
,
2257 void **this_cache
, int regnum
)
2259 struct sh64_frame_cache
*cache
= sh64_frame_cache (this_frame
, this_cache
);
2260 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2261 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2263 gdb_assert (regnum
>= 0);
2265 if (regnum
== gdbarch_sp_regnum (gdbarch
) && cache
->saved_sp
)
2266 frame_unwind_got_constant (this_frame
, regnum
, cache
->saved_sp
);
2268 /* The PC of the previous frame is stored in the PR register of
2269 the current frame. Frob regnum so that we pull the value from
2270 the correct place. */
2271 if (regnum
== gdbarch_pc_regnum (gdbarch
))
2274 if (regnum
< SIM_SH64_NR_REGS
&& cache
->saved_regs
[regnum
] != -1)
2276 if (gdbarch_tdep (gdbarch
)->sh_abi
== SH_ABI_32
2277 && (regnum
== MEDIA_FP_REGNUM
|| regnum
== PR_REGNUM
))
2280 val
= read_memory_unsigned_integer (cache
->saved_regs
[regnum
],
2282 return frame_unwind_got_constant (this_frame
, regnum
, val
);
2285 return frame_unwind_got_memory (this_frame
, regnum
,
2286 cache
->saved_regs
[regnum
]);
2289 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
2293 sh64_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2294 struct frame_id
*this_id
)
2296 struct sh64_frame_cache
*cache
= sh64_frame_cache (this_frame
, this_cache
);
2298 /* This marks the outermost frame. */
2299 if (cache
->base
== 0)
2302 *this_id
= frame_id_build (cache
->saved_sp
, cache
->pc
);
2305 static const struct frame_unwind sh64_frame_unwind
= {
2307 default_frame_unwind_stop_reason
,
2309 sh64_frame_prev_register
,
2311 default_frame_sniffer
2315 sh64_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2317 return frame_unwind_register_unsigned (next_frame
,
2318 gdbarch_sp_regnum (gdbarch
));
2322 sh64_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2324 return frame_unwind_register_unsigned (next_frame
,
2325 gdbarch_pc_regnum (gdbarch
));
2328 static struct frame_id
2329 sh64_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2331 CORE_ADDR sp
= get_frame_register_unsigned (this_frame
,
2332 gdbarch_sp_regnum (gdbarch
));
2333 return frame_id_build (sp
, get_frame_pc (this_frame
));
2337 sh64_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2339 struct sh64_frame_cache
*cache
= sh64_frame_cache (this_frame
, this_cache
);
2344 static const struct frame_base sh64_frame_base
= {
2346 sh64_frame_base_address
,
2347 sh64_frame_base_address
,
2348 sh64_frame_base_address
2353 sh64_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2355 struct gdbarch
*gdbarch
;
2356 struct gdbarch_tdep
*tdep
;
2358 /* If there is already a candidate, use it. */
2359 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2361 return arches
->gdbarch
;
2363 /* None found, create a new architecture from the information
2365 tdep
= XCNEW (struct gdbarch_tdep
);
2366 gdbarch
= gdbarch_alloc (&info
, tdep
);
2368 /* Determine the ABI */
2369 if (info
.abfd
&& bfd_get_arch_size (info
.abfd
) == 64)
2371 /* If the ABI is the 64-bit one, it can only be sh-media. */
2372 tdep
->sh_abi
= SH_ABI_64
;
2373 set_gdbarch_ptr_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2374 set_gdbarch_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2378 /* If the ABI is the 32-bit one it could be either media or
2380 tdep
->sh_abi
= SH_ABI_32
;
2381 set_gdbarch_ptr_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2382 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2385 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
2386 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2387 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2388 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2389 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2390 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2391 set_gdbarch_long_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2393 /* The number of real registers is the same whether we are in
2394 ISA16(compact) or ISA32(media). */
2395 set_gdbarch_num_regs (gdbarch
, SIM_SH64_NR_REGS
);
2396 set_gdbarch_sp_regnum (gdbarch
, 15);
2397 set_gdbarch_pc_regnum (gdbarch
, 64);
2398 set_gdbarch_fp0_regnum (gdbarch
, SIM_SH64_FR0_REGNUM
);
2399 set_gdbarch_num_pseudo_regs (gdbarch
, NUM_PSEUDO_REGS_SH_MEDIA
2400 + NUM_PSEUDO_REGS_SH_COMPACT
);
2402 set_gdbarch_register_name (gdbarch
, sh64_register_name
);
2403 set_gdbarch_register_type (gdbarch
, sh64_register_type
);
2405 set_gdbarch_pseudo_register_read (gdbarch
, sh64_pseudo_register_read
);
2406 set_gdbarch_pseudo_register_write (gdbarch
, sh64_pseudo_register_write
);
2408 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, sh64_breakpoint_kind_from_pc
);
2409 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, sh64_sw_breakpoint_from_kind
);
2410 set_gdbarch_register_sim_regno (gdbarch
, legacy_register_sim_regno
);
2412 set_gdbarch_return_value (gdbarch
, sh64_return_value
);
2414 set_gdbarch_skip_prologue (gdbarch
, sh64_skip_prologue
);
2415 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2417 set_gdbarch_push_dummy_call (gdbarch
, sh64_push_dummy_call
);
2419 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
2421 set_gdbarch_frame_align (gdbarch
, sh64_frame_align
);
2422 set_gdbarch_unwind_sp (gdbarch
, sh64_unwind_sp
);
2423 set_gdbarch_unwind_pc (gdbarch
, sh64_unwind_pc
);
2424 set_gdbarch_dummy_id (gdbarch
, sh64_dummy_id
);
2425 frame_base_set_default (gdbarch
, &sh64_frame_base
);
2427 set_gdbarch_print_registers_info (gdbarch
, sh64_print_registers_info
);
2429 set_gdbarch_elf_make_msymbol_special (gdbarch
,
2430 sh64_elf_make_msymbol_special
);
2432 /* Hook in ABI-specific overrides, if they have been registered. */
2433 gdbarch_init_osabi (info
, gdbarch
);
2435 dwarf2_append_unwinders (gdbarch
);
2436 frame_unwind_append_unwinder (gdbarch
, &sh64_frame_unwind
);