1 /* Target-dependent code for Renesas Super-H, for GDB.
3 Copyright (C) 1993-2016 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20 /* Contributed by Steve Chamberlain
25 #include "frame-base.h"
26 #include "frame-unwind.h"
27 #include "dwarf2-frame.h"
35 #include "arch-utils.h"
44 /* Register numbers shared with the simulator. */
45 #include "gdb/sim-sh.h"
47 #include "sh64-tdep.h"
50 /* Information that is dependent on the processor variant. */
63 struct sh64_frame_cache
70 /* Flag showing that a frame has been created in the prologue code. */
75 /* Saved registers. */
76 CORE_ADDR saved_regs
[SIM_SH64_NR_REGS
];
80 /* Registers of SH5 */
84 DEFAULT_RETURN_REGNUM
= 2,
85 STRUCT_RETURN_REGNUM
= 2,
88 FLOAT_ARGLAST_REGNUM
= 11,
94 /* FPP stands for Floating Point Pair, to avoid confusion with
95 GDB's gdbarch_fp0_regnum, which is the number of the first Floating
96 point register. Unfortunately on the sh5, the floating point
97 registers are called FR, and the floating point pairs are called FP. */
99 FPP_LAST_REGNUM
= 204,
101 FV_LAST_REGNUM
= 220,
103 R_LAST_C_REGNUM
= 236,
110 FPSCR_C_REGNUM
= 243,
113 FP_LAST_C_REGNUM
= 260,
115 DR_LAST_C_REGNUM
= 268,
117 FV_LAST_C_REGNUM
= 272,
118 FPSCR_REGNUM
= SIM_SH64_FPCSR_REGNUM
,
119 SSR_REGNUM
= SIM_SH64_SSR_REGNUM
,
120 SPC_REGNUM
= SIM_SH64_SPC_REGNUM
,
121 TR7_REGNUM
= SIM_SH64_TR0_REGNUM
+ 7,
122 FP_LAST_REGNUM
= SIM_SH64_FR0_REGNUM
+ SIM_SH64_NR_FP_REGS
- 1
126 sh64_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
128 static char *register_names
[] =
130 /* SH MEDIA MODE (ISA 32) */
131 /* general registers (64-bit) 0-63 */
132 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
133 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
134 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
135 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
136 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
137 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
138 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
139 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
144 /* status reg., saved status reg., saved pc reg. (64-bit) 65-67 */
147 /* target registers (64-bit) 68-75 */
148 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7",
150 /* floating point state control register (32-bit) 76 */
153 /* single precision floating point registers (32-bit) 77-140 */
154 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
155 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
156 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
157 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31",
158 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39",
159 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47",
160 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55",
161 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63",
163 /* double precision registers (pseudo) 141-172 */
164 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
165 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30",
166 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46",
167 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62",
169 /* floating point pairs (pseudo) 173-204 */
170 "fp0", "fp2", "fp4", "fp6", "fp8", "fp10", "fp12", "fp14",
171 "fp16", "fp18", "fp20", "fp22", "fp24", "fp26", "fp28", "fp30",
172 "fp32", "fp34", "fp36", "fp38", "fp40", "fp42", "fp44", "fp46",
173 "fp48", "fp50", "fp52", "fp54", "fp56", "fp58", "fp60", "fp62",
175 /* floating point vectors (4 floating point regs) (pseudo) 205-220 */
176 "fv0", "fv4", "fv8", "fv12", "fv16", "fv20", "fv24", "fv28",
177 "fv32", "fv36", "fv40", "fv44", "fv48", "fv52", "fv56", "fv60",
179 /* SH COMPACT MODE (ISA 16) (all pseudo) 221-272 */
180 "r0_c", "r1_c", "r2_c", "r3_c", "r4_c", "r5_c", "r6_c", "r7_c",
181 "r8_c", "r9_c", "r10_c", "r11_c", "r12_c", "r13_c", "r14_c", "r15_c",
183 "gbr_c", "mach_c", "macl_c", "pr_c", "t_c",
185 "fr0_c", "fr1_c", "fr2_c", "fr3_c",
186 "fr4_c", "fr5_c", "fr6_c", "fr7_c",
187 "fr8_c", "fr9_c", "fr10_c", "fr11_c",
188 "fr12_c", "fr13_c", "fr14_c", "fr15_c",
189 "dr0_c", "dr2_c", "dr4_c", "dr6_c",
190 "dr8_c", "dr10_c", "dr12_c", "dr14_c",
191 "fv0_c", "fv4_c", "fv8_c", "fv12_c",
192 /* FIXME!!!! XF0 XF15, XD0 XD14 ????? */
197 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
199 return register_names
[reg_nr
];
202 #define NUM_PSEUDO_REGS_SH_MEDIA 80
203 #define NUM_PSEUDO_REGS_SH_COMPACT 51
205 /* Macros and functions for setting and testing a bit in a minimal
206 symbol that marks it as 32-bit function. The MSB of the minimal
207 symbol's "info" field is used for this purpose.
209 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
210 i.e. refers to a 32-bit function, and sets a "special" bit in a
211 minimal symbol to mark it as a 32-bit function
212 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
214 #define MSYMBOL_IS_SPECIAL(msym) \
215 MSYMBOL_TARGET_FLAG_1 (msym)
218 sh64_elf_make_msymbol_special (asymbol
*sym
, struct minimal_symbol
*msym
)
223 if (((elf_symbol_type
*)(sym
))->internal_elf_sym
.st_other
== STO_SH5_ISA32
)
225 MSYMBOL_TARGET_FLAG_1 (msym
) = 1;
226 SET_MSYMBOL_VALUE_ADDRESS (msym
, MSYMBOL_VALUE_RAW_ADDRESS (msym
) | 1);
230 /* ISA32 (shmedia) function addresses are odd (bit 0 is set). Here
231 are some macros to test, set, or clear bit 0 of addresses. */
232 #define IS_ISA32_ADDR(addr) ((addr) & 1)
233 #define MAKE_ISA32_ADDR(addr) ((addr) | 1)
234 #define UNMAKE_ISA32_ADDR(addr) ((addr) & ~1)
237 pc_is_isa32 (bfd_vma memaddr
)
239 struct bound_minimal_symbol sym
;
241 /* If bit 0 of the address is set, assume this is a
242 ISA32 (shmedia) address. */
243 if (IS_ISA32_ADDR (memaddr
))
246 /* A flag indicating that this is a ISA32 function is stored by elfread.c in
247 the high bit of the info field. Use this to decide if the function is
249 sym
= lookup_minimal_symbol_by_pc (memaddr
);
251 return MSYMBOL_IS_SPECIAL (sym
.minsym
);
256 static const unsigned char *
257 sh64_breakpoint_from_pc (struct gdbarch
*gdbarch
,
258 CORE_ADDR
*pcptr
, int *lenptr
)
260 /* The BRK instruction for shmedia is
261 01101111 11110101 11111111 11110000
262 which translates in big endian mode to 0x6f, 0xf5, 0xff, 0xf0
263 and in little endian mode to 0xf0, 0xff, 0xf5, 0x6f */
265 /* The BRK instruction for shcompact is
267 which translates in big endian mode to 0x0, 0x3b
268 and in little endian mode to 0x3b, 0x0 */
270 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
272 if (pc_is_isa32 (*pcptr
))
274 static unsigned char big_breakpoint_media
[] = {
275 0x6f, 0xf5, 0xff, 0xf0
277 *pcptr
= UNMAKE_ISA32_ADDR (*pcptr
);
278 *lenptr
= sizeof (big_breakpoint_media
);
279 return big_breakpoint_media
;
283 static unsigned char big_breakpoint_compact
[] = {0x0, 0x3b};
284 *lenptr
= sizeof (big_breakpoint_compact
);
285 return big_breakpoint_compact
;
290 if (pc_is_isa32 (*pcptr
))
292 static unsigned char little_breakpoint_media
[] = {
293 0xf0, 0xff, 0xf5, 0x6f
295 *pcptr
= UNMAKE_ISA32_ADDR (*pcptr
);
296 *lenptr
= sizeof (little_breakpoint_media
);
297 return little_breakpoint_media
;
301 static unsigned char little_breakpoint_compact
[] = {0x3b, 0x0};
302 *lenptr
= sizeof (little_breakpoint_compact
);
303 return little_breakpoint_compact
;
308 /* Prologue looks like
309 [mov.l <regs>,@-r15]...
314 Actually it can be more complicated than this. For instance, with
332 /* PTABS/L Rn, TRa 0110101111110001nnnnnnl00aaa0000
333 with l=1 and n = 18 0110101111110001010010100aaa0000 */
334 #define IS_PTABSL_R18(x) (((x) & 0xffffff8f) == 0x6bf14a00)
336 /* STS.L PR,@-r0 0100000000100010
337 r0-4-->r0, PR-->(r0) */
338 #define IS_STS_R0(x) ((x) == 0x4022)
340 /* STS PR, Rm 0000mmmm00101010
342 #define IS_STS_PR(x) (((x) & 0xf0ff) == 0x2a)
344 /* MOV.L Rm,@(disp,r15) 00011111mmmmdddd
346 #define IS_MOV_TO_R15(x) (((x) & 0xff00) == 0x1f00)
348 /* MOV.L R14,@(disp,r15) 000111111110dddd
349 R14-->(dispx4+r15) */
350 #define IS_MOV_R14(x) (((x) & 0xfff0) == 0x1fe0)
352 /* ST.Q R14, disp, R18 101011001110dddddddddd0100100000
353 R18-->(dispx8+R14) */
354 #define IS_STQ_R18_R14(x) (((x) & 0xfff003ff) == 0xace00120)
356 /* ST.Q R15, disp, R18 101011001111dddddddddd0100100000
357 R18-->(dispx8+R15) */
358 #define IS_STQ_R18_R15(x) (((x) & 0xfff003ff) == 0xacf00120)
360 /* ST.L R15, disp, R18 101010001111dddddddddd0100100000
361 R18-->(dispx4+R15) */
362 #define IS_STL_R18_R15(x) (((x) & 0xfff003ff) == 0xa8f00120)
364 /* ST.Q R15, disp, R14 1010 1100 1111 dddd dddd dd00 1110 0000
365 R14-->(dispx8+R15) */
366 #define IS_STQ_R14_R15(x) (((x) & 0xfff003ff) == 0xacf000e0)
368 /* ST.L R15, disp, R14 1010 1000 1111 dddd dddd dd00 1110 0000
369 R14-->(dispx4+R15) */
370 #define IS_STL_R14_R15(x) (((x) & 0xfff003ff) == 0xa8f000e0)
372 /* ADDI.L R15,imm,R15 1101 0100 1111 ssss ssss ss00 1111 0000
374 #define IS_ADDIL_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd4f000f0)
376 /* ADDI R15,imm,R15 1101 0000 1111 ssss ssss ss00 1111 0000
378 #define IS_ADDI_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd0f000f0)
380 /* ADD.L R15,R63,R14 0000 0000 1111 1000 1111 1100 1110 0000
382 #define IS_ADDL_SP_FP_MEDIA(x) ((x) == 0x00f8fce0)
384 /* ADD R15,R63,R14 0000 0000 1111 1001 1111 1100 1110 0000
386 #define IS_ADD_SP_FP_MEDIA(x) ((x) == 0x00f9fce0)
388 #define IS_MOV_SP_FP_MEDIA(x) \
389 (IS_ADDL_SP_FP_MEDIA(x) || IS_ADD_SP_FP_MEDIA(x))
391 /* MOV #imm, R0 1110 0000 ssss ssss
393 #define IS_MOV_R0(x) (((x) & 0xff00) == 0xe000)
395 /* MOV.L @(disp,PC), R0 1101 0000 iiii iiii */
396 #define IS_MOVL_R0(x) (((x) & 0xff00) == 0xd000)
398 /* ADD r15,r0 0011 0000 1111 1100
400 #define IS_ADD_SP_R0(x) ((x) == 0x30fc)
402 /* MOV.L R14 @-R0 0010 0000 1110 0110
403 R14-->(R0-4), R0-4-->R0 */
404 #define IS_MOV_R14_R0(x) ((x) == 0x20e6)
406 /* ADD Rm,R63,Rn Rm+R63-->Rn 0000 00mm mmmm 1001 1111 11nn nnnn 0000
407 where Rm is one of r2-r9 which are the argument registers. */
408 /* FIXME: Recognize the float and double register moves too! */
409 #define IS_MEDIA_IND_ARG_MOV(x) \
410 ((((x) & 0xfc0ffc0f) == 0x0009fc00) \
411 && (((x) & 0x03f00000) >= 0x00200000 \
412 && ((x) & 0x03f00000) <= 0x00900000))
414 /* ST.Q Rn,0,Rm Rm-->Rn+0 1010 11nn nnnn 0000 0000 00mm mmmm 0000
415 or ST.L Rn,0,Rm Rm-->Rn+0 1010 10nn nnnn 0000 0000 00mm mmmm 0000
416 where Rm is one of r2-r9 which are the argument registers. */
417 #define IS_MEDIA_ARG_MOV(x) \
418 (((((x) & 0xfc0ffc0f) == 0xac000000) || (((x) & 0xfc0ffc0f) == 0xa8000000)) \
419 && (((x) & 0x000003f0) >= 0x00000020 && ((x) & 0x000003f0) <= 0x00000090))
421 /* ST.B R14,0,Rn Rn-->(R14+0) 1010 0000 1110 0000 0000 00nn nnnn 0000 */
422 /* ST.W R14,0,Rn Rn-->(R14+0) 1010 0100 1110 0000 0000 00nn nnnn 0000 */
423 /* ST.L R14,0,Rn Rn-->(R14+0) 1010 1000 1110 0000 0000 00nn nnnn 0000 */
424 /* FST.S R14,0,FRn Rn-->(R14+0) 1011 0100 1110 0000 0000 00nn nnnn 0000 */
425 /* FST.D R14,0,DRn Rn-->(R14+0) 1011 1100 1110 0000 0000 00nn nnnn 0000 */
426 #define IS_MEDIA_MOV_TO_R14(x) \
427 ((((x) & 0xfffffc0f) == 0xa0e00000) \
428 || (((x) & 0xfffffc0f) == 0xa4e00000) \
429 || (((x) & 0xfffffc0f) == 0xa8e00000) \
430 || (((x) & 0xfffffc0f) == 0xb4e00000) \
431 || (((x) & 0xfffffc0f) == 0xbce00000))
433 /* MOV Rm, Rn Rm-->Rn 0110 nnnn mmmm 0011
435 #define IS_COMPACT_IND_ARG_MOV(x) \
436 ((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0020) \
437 && (((x) & 0x00f0) <= 0x0090))
439 /* compact direct arg move!
440 MOV.L Rn, @r14 0010 1110 mmmm 0010 */
441 #define IS_COMPACT_ARG_MOV(x) \
442 (((((x) & 0xff0f) == 0x2e02) && (((x) & 0x00f0) >= 0x0020) \
443 && ((x) & 0x00f0) <= 0x0090))
445 /* MOV.B Rm, @R14 0010 1110 mmmm 0000
446 MOV.W Rm, @R14 0010 1110 mmmm 0001 */
447 #define IS_COMPACT_MOV_TO_R14(x) \
448 ((((x) & 0xff0f) == 0x2e00) || (((x) & 0xff0f) == 0x2e01))
450 #define IS_JSR_R0(x) ((x) == 0x400b)
451 #define IS_NOP(x) ((x) == 0x0009)
454 /* MOV r15,r14 0110111011110011
456 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
458 /* ADD #imm,r15 01111111iiiiiiii
460 #define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00)
462 /* Skip any prologue before the guts of a function. */
464 /* Skip the prologue using the debug information. If this fails we'll
465 fall back on the 'guess' method below. */
467 after_prologue (CORE_ADDR pc
)
469 struct symtab_and_line sal
;
470 CORE_ADDR func_addr
, func_end
;
472 /* If we can not find the symbol in the partial symbol table, then
473 there is no hope we can determine the function's start address
475 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
479 /* Get the line associated with FUNC_ADDR. */
480 sal
= find_pc_line (func_addr
, 0);
482 /* There are only two cases to consider. First, the end of the source line
483 is within the function bounds. In that case we return the end of the
484 source line. Second is the end of the source line extends beyond the
485 bounds of the current function. We need to use the slow code to
486 examine instructions in that case. */
487 if (sal
.end
< func_end
)
494 look_for_args_moves (struct gdbarch
*gdbarch
,
495 CORE_ADDR start_pc
, int media_mode
)
497 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
500 int insn_size
= (media_mode
? 4 : 2);
502 for (here
= start_pc
, end
= start_pc
+ (insn_size
* 28); here
< end
;)
506 w
= read_memory_integer (UNMAKE_ISA32_ADDR (here
),
507 insn_size
, byte_order
);
509 if (IS_MEDIA_IND_ARG_MOV (w
))
511 /* This must be followed by a store to r14, so the argument
512 is where the debug info says it is. This can happen after
513 the SP has been saved, unfortunately. */
515 int next_insn
= read_memory_integer (UNMAKE_ISA32_ADDR (here
),
516 insn_size
, byte_order
);
518 if (IS_MEDIA_MOV_TO_R14 (next_insn
))
521 else if (IS_MEDIA_ARG_MOV (w
))
523 /* These instructions store directly the argument in r14. */
531 w
= read_memory_integer (here
, insn_size
, byte_order
);
534 if (IS_COMPACT_IND_ARG_MOV (w
))
536 /* This must be followed by a store to r14, so the argument
537 is where the debug info says it is. This can happen after
538 the SP has been saved, unfortunately. */
540 int next_insn
= 0xffff & read_memory_integer (here
, insn_size
,
543 if (IS_COMPACT_MOV_TO_R14 (next_insn
))
546 else if (IS_COMPACT_ARG_MOV (w
))
548 /* These instructions store directly the argument in r14. */
551 else if (IS_MOVL_R0 (w
))
553 /* There is a function that gcc calls to get the arguments
554 passed correctly to the function. Only after this
555 function call the arguments will be found at the place
556 where they are supposed to be. This happens in case the
557 argument has to be stored into a 64-bit register (for
558 instance doubles, long longs). SHcompact doesn't have
559 access to the full 64-bits, so we store the register in
560 stack slot and store the address of the stack slot in
561 the register, then do a call through a wrapper that
562 loads the memory value into the register. A SHcompact
563 callee calls an argument decoder
564 (GCC_shcompact_incoming_args) that stores the 64-bit
565 value in a stack slot and stores the address of the
566 stack slot in the register. GCC thinks the argument is
567 just passed by transparent reference, but this is only
568 true after the argument decoder is called. Such a call
569 needs to be considered part of the prologue. */
571 /* This must be followed by a JSR @r0 instruction and by
572 a NOP instruction. After these, the prologue is over! */
574 int next_insn
= 0xffff & read_memory_integer (here
, insn_size
,
577 if (IS_JSR_R0 (next_insn
))
579 next_insn
= 0xffff & read_memory_integer (here
, insn_size
,
583 if (IS_NOP (next_insn
))
596 sh64_skip_prologue_hard_way (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
598 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
607 if (pc_is_isa32 (start_pc
) == 0)
613 for (here
= start_pc
, end
= start_pc
+ (insn_size
* 28); here
< end
;)
618 int w
= read_memory_integer (UNMAKE_ISA32_ADDR (here
),
619 insn_size
, byte_order
);
621 if (IS_STQ_R18_R14 (w
) || IS_STQ_R18_R15 (w
) || IS_STQ_R14_R15 (w
)
622 || IS_STL_R14_R15 (w
) || IS_STL_R18_R15 (w
)
623 || IS_ADDIL_SP_MEDIA (w
) || IS_ADDI_SP_MEDIA (w
)
624 || IS_PTABSL_R18 (w
))
628 else if (IS_MOV_SP_FP (w
) || IS_MOV_SP_FP_MEDIA(w
))
636 /* Don't bail out yet, we may have arguments stored in
637 registers here, according to the debug info, so that
638 gdb can print the frames correctly. */
639 start_pc
= look_for_args_moves (gdbarch
,
640 here
- insn_size
, media_mode
);
646 int w
= 0xffff & read_memory_integer (here
, insn_size
, byte_order
);
649 if (IS_STS_R0 (w
) || IS_STS_PR (w
)
650 || IS_MOV_TO_R15 (w
) || IS_MOV_R14 (w
)
651 || IS_MOV_R0 (w
) || IS_ADD_SP_R0 (w
) || IS_MOV_R14_R0 (w
))
655 else if (IS_MOV_SP_FP (w
))
663 /* Don't bail out yet, we may have arguments stored in
664 registers here, according to the debug info, so that
665 gdb can print the frames correctly. */
666 start_pc
= look_for_args_moves (gdbarch
,
667 here
- insn_size
, media_mode
);
677 sh64_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
679 CORE_ADDR post_prologue_pc
;
681 /* See if we can determine the end of the prologue via the symbol table.
682 If so, then return either PC, or the PC after the prologue, whichever
684 post_prologue_pc
= after_prologue (pc
);
686 /* If after_prologue returned a useful address, then use it. Else
687 fall back on the instruction skipping code. */
688 if (post_prologue_pc
!= 0)
689 return std::max (pc
, post_prologue_pc
);
691 return sh64_skip_prologue_hard_way (gdbarch
, pc
);
694 /* Should call_function allocate stack space for a struct return? */
696 sh64_use_struct_convention (struct type
*type
)
698 return (TYPE_LENGTH (type
) > 8);
701 /* For vectors of 4 floating point registers. */
703 sh64_fv_reg_base_num (struct gdbarch
*gdbarch
, int fv_regnum
)
707 fp_regnum
= gdbarch_fp0_regnum (gdbarch
) + (fv_regnum
- FV0_REGNUM
) * 4;
711 /* For double precision floating point registers, i.e 2 fp regs. */
713 sh64_dr_reg_base_num (struct gdbarch
*gdbarch
, int dr_regnum
)
717 fp_regnum
= gdbarch_fp0_regnum (gdbarch
) + (dr_regnum
- DR0_REGNUM
) * 2;
721 /* For pairs of floating point registers. */
723 sh64_fpp_reg_base_num (struct gdbarch
*gdbarch
, int fpp_regnum
)
727 fp_regnum
= gdbarch_fp0_regnum (gdbarch
) + (fpp_regnum
- FPP0_REGNUM
) * 2;
733 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
734 GDB_REGNUM BASE_REGNUM
794 sh64_compact_reg_base_num (struct gdbarch
*gdbarch
, int reg_nr
)
796 int base_regnum
= reg_nr
;
798 /* general register N maps to general register N */
799 if (reg_nr
>= R0_C_REGNUM
800 && reg_nr
<= R_LAST_C_REGNUM
)
801 base_regnum
= reg_nr
- R0_C_REGNUM
;
803 /* floating point register N maps to floating point register N */
804 else if (reg_nr
>= FP0_C_REGNUM
805 && reg_nr
<= FP_LAST_C_REGNUM
)
806 base_regnum
= reg_nr
- FP0_C_REGNUM
+ gdbarch_fp0_regnum (gdbarch
);
808 /* double prec register N maps to base regnum for double prec register N */
809 else if (reg_nr
>= DR0_C_REGNUM
810 && reg_nr
<= DR_LAST_C_REGNUM
)
811 base_regnum
= sh64_dr_reg_base_num (gdbarch
,
812 DR0_REGNUM
+ reg_nr
- DR0_C_REGNUM
);
814 /* vector N maps to base regnum for vector register N */
815 else if (reg_nr
>= FV0_C_REGNUM
816 && reg_nr
<= FV_LAST_C_REGNUM
)
817 base_regnum
= sh64_fv_reg_base_num (gdbarch
,
818 FV0_REGNUM
+ reg_nr
- FV0_C_REGNUM
);
820 else if (reg_nr
== PC_C_REGNUM
)
821 base_regnum
= gdbarch_pc_regnum (gdbarch
);
823 else if (reg_nr
== GBR_C_REGNUM
)
826 else if (reg_nr
== MACH_C_REGNUM
827 || reg_nr
== MACL_C_REGNUM
)
830 else if (reg_nr
== PR_C_REGNUM
)
831 base_regnum
= PR_REGNUM
;
833 else if (reg_nr
== T_C_REGNUM
)
836 else if (reg_nr
== FPSCR_C_REGNUM
)
837 base_regnum
= FPSCR_REGNUM
; /*???? this register is a mess. */
839 else if (reg_nr
== FPUL_C_REGNUM
)
840 base_regnum
= gdbarch_fp0_regnum (gdbarch
) + 32;
846 sign_extend (int value
, int bits
)
848 value
= value
& ((1 << bits
) - 1);
849 return (value
& (1 << (bits
- 1))
850 ? value
| (~((1 << bits
) - 1))
855 sh64_analyze_prologue (struct gdbarch
*gdbarch
,
856 struct sh64_frame_cache
*cache
,
858 CORE_ADDR current_pc
)
865 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
867 cache
->sp_offset
= 0;
869 /* Loop around examining the prologue insns until we find something
870 that does not appear to be part of the prologue. But give up
871 after 20 of them, since we're getting silly then. */
875 if (cache
->media_mode
)
880 opc
= pc
+ (insn_size
* 28);
881 if (opc
> current_pc
)
883 for ( ; pc
<= opc
; pc
+= insn_size
)
885 insn
= read_memory_integer (cache
->media_mode
? UNMAKE_ISA32_ADDR (pc
)
887 insn_size
, byte_order
);
889 if (!cache
->media_mode
)
891 if (IS_STS_PR (insn
))
893 int next_insn
= read_memory_integer (pc
+ insn_size
,
894 insn_size
, byte_order
);
895 if (IS_MOV_TO_R15 (next_insn
))
897 cache
->saved_regs
[PR_REGNUM
]
898 = cache
->sp_offset
- ((((next_insn
& 0xf) ^ 0x8)
904 else if (IS_MOV_R14 (insn
))
906 cache
->saved_regs
[MEDIA_FP_REGNUM
] =
907 cache
->sp_offset
- ((((insn
& 0xf) ^ 0x8) - 0x8) << 2);
911 else if (IS_MOV_R0 (insn
))
913 /* Put in R0 the offset from SP at which to store some
914 registers. We are interested in this value, because it
915 will tell us where the given registers are stored within
917 r0_val
= ((insn
& 0xff) ^ 0x80) - 0x80;
920 else if (IS_ADD_SP_R0 (insn
))
922 /* This instruction still prepares r0, but we don't care.
923 We already have the offset in r0_val. */
926 else if (IS_STS_R0 (insn
))
928 /* Store PR at r0_val-4 from SP. Decrement r0 by 4. */
929 cache
->saved_regs
[PR_REGNUM
] = cache
->sp_offset
- (r0_val
- 4);
933 else if (IS_MOV_R14_R0 (insn
))
935 /* Store R14 at r0_val-4 from SP. Decrement r0 by 4. */
936 cache
->saved_regs
[MEDIA_FP_REGNUM
] = cache
->sp_offset
942 else if (IS_ADD_SP (insn
))
943 cache
->sp_offset
-= ((insn
& 0xff) ^ 0x80) - 0x80;
945 else if (IS_MOV_SP_FP (insn
))
950 if (IS_ADDIL_SP_MEDIA (insn
) || IS_ADDI_SP_MEDIA (insn
))
952 sign_extend ((((insn
& 0xffc00) ^ 0x80000) - 0x80000) >> 10, 9);
954 else if (IS_STQ_R18_R15 (insn
))
955 cache
->saved_regs
[PR_REGNUM
]
956 = cache
->sp_offset
- (sign_extend ((insn
& 0xffc00) >> 10,
959 else if (IS_STL_R18_R15 (insn
))
960 cache
->saved_regs
[PR_REGNUM
]
961 = cache
->sp_offset
- (sign_extend ((insn
& 0xffc00) >> 10,
964 else if (IS_STQ_R14_R15 (insn
))
966 cache
->saved_regs
[MEDIA_FP_REGNUM
]
967 = cache
->sp_offset
- (sign_extend ((insn
& 0xffc00) >> 10,
972 else if (IS_STL_R14_R15 (insn
))
974 cache
->saved_regs
[MEDIA_FP_REGNUM
]
975 = cache
->sp_offset
- (sign_extend ((insn
& 0xffc00) >> 10,
980 else if (IS_MOV_SP_FP_MEDIA (insn
))
987 sh64_frame_align (struct gdbarch
*ignore
, CORE_ADDR sp
)
992 /* Function: push_dummy_call
993 Setup the function arguments for calling a function in the inferior.
995 On the Renesas SH architecture, there are four registers (R4 to R7)
996 which are dedicated for passing function arguments. Up to the first
997 four arguments (depending on size) may go into these registers.
998 The rest go on the stack.
1000 Arguments that are smaller than 4 bytes will still take up a whole
1001 register or a whole 32-bit word on the stack, and will be
1002 right-justified in the register or the stack word. This includes
1003 chars, shorts, and small aggregate types.
1005 Arguments that are larger than 4 bytes may be split between two or
1006 more registers. If there are not enough registers free, an argument
1007 may be passed partly in a register (or registers), and partly on the
1008 stack. This includes doubles, long longs, and larger aggregates.
1009 As far as I know, there is no upper limit to the size of aggregates
1010 that will be passed in this way; in other words, the convention of
1011 passing a pointer to a large aggregate instead of a copy is not used.
1013 An exceptional case exists for struct arguments (and possibly other
1014 aggregates such as arrays) if the size is larger than 4 bytes but
1015 not a multiple of 4 bytes. In this case the argument is never split
1016 between the registers and the stack, but instead is copied in its
1017 entirety onto the stack, AND also copied into as many registers as
1018 there is room for. In other words, space in registers permitting,
1019 two copies of the same argument are passed in. As far as I can tell,
1020 only the one on the stack is used, although that may be a function
1021 of the level of compiler optimization. I suspect this is a compiler
1022 bug. Arguments of these odd sizes are left-justified within the
1023 word (as opposed to arguments smaller than 4 bytes, which are
1026 If the function is to return an aggregate type such as a struct, it
1027 is either returned in the normal return value register R0 (if its
1028 size is no greater than one byte), or else the caller must allocate
1029 space into which the callee will copy the return value (if the size
1030 is greater than one byte). In this case, a pointer to the return
1031 value location is passed into the callee in register R2, which does
1032 not displace any of the other arguments passed in via registers R4
1035 /* R2-R9 for integer types and integer equivalent (char, pointers) and
1036 non-scalar (struct, union) elements (even if the elements are
1038 FR0-FR11 for single precision floating point (float)
1039 DR0-DR10 for double precision floating point (double)
1041 If a float is argument number 3 (for instance) and arguments number
1042 1,2, and 4 are integer, the mapping will be:
1043 arg1 -->R2, arg2 --> R3, arg3 -->FR0, arg4 --> R5. I.e. R4 is not used.
1045 If a float is argument number 10 (for instance) and arguments number
1046 1 through 10 are integer, the mapping will be:
1047 arg1->R2, arg2->R3, arg3->R4, arg4->R5, arg5->R6, arg6->R7, arg7->R8,
1048 arg8->R9, arg9->(0,SP)stack(8-byte aligned), arg10->FR0,
1049 arg11->stack(16,SP). I.e. there is hole in the stack.
1051 Different rules apply for variable arguments functions, and for functions
1052 for which the prototype is not known. */
1055 sh64_push_dummy_call (struct gdbarch
*gdbarch
,
1056 struct value
*function
,
1057 struct regcache
*regcache
,
1059 int nargs
, struct value
**args
,
1060 CORE_ADDR sp
, int struct_return
,
1061 CORE_ADDR struct_addr
)
1063 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1064 int stack_offset
, stack_alloc
;
1066 int float_arg_index
= 0;
1067 int double_arg_index
= 0;
1071 const gdb_byte
*val
;
1077 memset (fp_args
, 0, sizeof (fp_args
));
1079 /* First force sp to a 8-byte alignment. */
1080 sp
= sh64_frame_align (gdbarch
, sp
);
1082 /* The "struct return pointer" pseudo-argument has its own dedicated
1086 regcache_cooked_write_unsigned (regcache
,
1087 STRUCT_RETURN_REGNUM
, struct_addr
);
1089 /* Now make sure there's space on the stack. */
1090 for (argnum
= 0, stack_alloc
= 0; argnum
< nargs
; argnum
++)
1091 stack_alloc
+= ((TYPE_LENGTH (value_type (args
[argnum
])) + 7) & ~7);
1092 sp
-= stack_alloc
; /* Make room on stack for args. */
1094 /* Now load as many as possible of the first arguments into
1095 registers, and push the rest onto the stack. There are 64 bytes
1096 in eight registers available. Loop thru args from first to last. */
1098 int_argreg
= ARG0_REGNUM
;
1100 for (argnum
= 0, stack_offset
= 0; argnum
< nargs
; argnum
++)
1102 type
= value_type (args
[argnum
]);
1103 len
= TYPE_LENGTH (type
);
1104 memset (valbuf
, 0, sizeof (valbuf
));
1106 if (TYPE_CODE (type
) != TYPE_CODE_FLT
)
1108 argreg_size
= register_size (gdbarch
, int_argreg
);
1110 if (len
< argreg_size
)
1112 /* value gets right-justified in the register or stack word. */
1113 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1114 memcpy (valbuf
+ argreg_size
- len
,
1115 value_contents (args
[argnum
]), len
);
1117 memcpy (valbuf
, value_contents (args
[argnum
]), len
);
1122 val
= value_contents (args
[argnum
]);
1126 if (int_argreg
> ARGLAST_REGNUM
)
1128 /* Must go on the stack. */
1129 write_memory (sp
+ stack_offset
, val
, argreg_size
);
1130 stack_offset
+= 8;/*argreg_size;*/
1132 /* NOTE WELL!!!!! This is not an "else if" clause!!!
1133 That's because some *&^%$ things get passed on the stack
1134 AND in the registers! */
1135 if (int_argreg
<= ARGLAST_REGNUM
)
1137 /* There's room in a register. */
1138 regval
= extract_unsigned_integer (val
, argreg_size
,
1140 regcache_cooked_write_unsigned (regcache
,
1141 int_argreg
, regval
);
1143 /* Store the value 8 bytes at a time. This means that
1144 things larger than 8 bytes may go partly in registers
1145 and partly on the stack. FIXME: argreg is incremented
1146 before we use its size. */
1154 val
= value_contents (args
[argnum
]);
1157 /* Where is it going to be stored? */
1158 while (fp_args
[float_arg_index
])
1161 /* Now float_argreg points to the register where it
1162 should be stored. Are we still within the allowed
1164 if (float_arg_index
<= FLOAT_ARGLAST_REGNUM
)
1166 /* Goes in FR0...FR11 */
1167 regcache_cooked_write (regcache
,
1168 gdbarch_fp0_regnum (gdbarch
)
1171 fp_args
[float_arg_index
] = 1;
1172 /* Skip the corresponding general argument register. */
1177 /* Store it as the integers, 8 bytes at the time, if
1178 necessary spilling on the stack. */
1183 /* Where is it going to be stored? */
1184 while (fp_args
[double_arg_index
])
1185 double_arg_index
+= 2;
1186 /* Now double_argreg points to the register
1187 where it should be stored.
1188 Are we still within the allowed register set? */
1189 if (double_arg_index
< FLOAT_ARGLAST_REGNUM
)
1191 /* Goes in DR0...DR10 */
1192 /* The numbering of the DRi registers is consecutive,
1193 i.e. includes odd numbers. */
1194 int double_register_offset
= double_arg_index
/ 2;
1195 int regnum
= DR0_REGNUM
+ double_register_offset
;
1196 regcache_cooked_write (regcache
, regnum
, val
);
1197 fp_args
[double_arg_index
] = 1;
1198 fp_args
[double_arg_index
+ 1] = 1;
1199 /* Skip the corresponding general argument register. */
1204 /* Store it as the integers, 8 bytes at the time, if
1205 necessary spilling on the stack. */
1210 /* Store return address. */
1211 regcache_cooked_write_unsigned (regcache
, PR_REGNUM
, bp_addr
);
1213 /* Update stack pointer. */
1214 regcache_cooked_write_unsigned (regcache
,
1215 gdbarch_sp_regnum (gdbarch
), sp
);
1220 /* Find a function's return value in the appropriate registers (in
1221 regbuf), and copy it into valbuf. Extract from an array REGBUF
1222 containing the (raw) register state a function return value of type
1223 TYPE, and copy that, in virtual format, into VALBUF. */
1225 sh64_extract_return_value (struct type
*type
, struct regcache
*regcache
,
1228 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1229 int len
= TYPE_LENGTH (type
);
1231 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1235 /* Return value stored in gdbarch_fp0_regnum. */
1236 regcache_raw_read (regcache
,
1237 gdbarch_fp0_regnum (gdbarch
), valbuf
);
1241 /* return value stored in DR0_REGNUM. */
1245 regcache_cooked_read (regcache
, DR0_REGNUM
, buf
);
1247 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
1248 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword
,
1251 floatformat_to_doublest (&floatformat_ieee_double_big
,
1253 store_typed_floating (valbuf
, type
, val
);
1262 /* Result is in register 2. If smaller than 8 bytes, it is padded
1263 at the most significant end. */
1264 regcache_raw_read (regcache
, DEFAULT_RETURN_REGNUM
, buf
);
1266 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1267 offset
= register_size (gdbarch
, DEFAULT_RETURN_REGNUM
)
1271 memcpy (valbuf
, buf
+ offset
, len
);
1274 error (_("bad size for return value"));
1278 /* Write into appropriate registers a function return value
1279 of type TYPE, given in virtual format.
1280 If the architecture is sh4 or sh3e, store a function's return value
1281 in the R0 general register or in the FP0 floating point register,
1282 depending on the type of the return value. In all the other cases
1283 the result is stored in r0, left-justified. */
1286 sh64_store_return_value (struct type
*type
, struct regcache
*regcache
,
1287 const gdb_byte
*valbuf
)
1289 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1290 gdb_byte buf
[64]; /* more than enough... */
1291 int len
= TYPE_LENGTH (type
);
1293 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1295 int i
, regnum
= gdbarch_fp0_regnum (gdbarch
);
1296 for (i
= 0; i
< len
; i
+= 4)
1297 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
1298 regcache_raw_write (regcache
, regnum
++,
1299 valbuf
+ len
- 4 - i
);
1301 regcache_raw_write (regcache
, regnum
++, valbuf
+ i
);
1305 int return_register
= DEFAULT_RETURN_REGNUM
;
1308 if (len
<= register_size (gdbarch
, return_register
))
1310 /* Pad with zeros. */
1311 memset (buf
, 0, register_size (gdbarch
, return_register
));
1312 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
1313 offset
= 0; /*register_size (gdbarch,
1314 return_register) - len;*/
1316 offset
= register_size (gdbarch
, return_register
) - len
;
1318 memcpy (buf
+ offset
, valbuf
, len
);
1319 regcache_raw_write (regcache
, return_register
, buf
);
1322 regcache_raw_write (regcache
, return_register
, valbuf
);
1326 static enum return_value_convention
1327 sh64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
1328 struct type
*type
, struct regcache
*regcache
,
1329 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1331 if (sh64_use_struct_convention (type
))
1332 return RETURN_VALUE_STRUCT_CONVENTION
;
1334 sh64_store_return_value (type
, regcache
, writebuf
);
1336 sh64_extract_return_value (type
, regcache
, readbuf
);
1337 return RETURN_VALUE_REGISTER_CONVENTION
;
1342 SH MEDIA MODE (ISA 32)
1343 general registers (64-bit) 0-63
1344 0 r0, r1, r2, r3, r4, r5, r6, r7,
1345 64 r8, r9, r10, r11, r12, r13, r14, r15,
1346 128 r16, r17, r18, r19, r20, r21, r22, r23,
1347 192 r24, r25, r26, r27, r28, r29, r30, r31,
1348 256 r32, r33, r34, r35, r36, r37, r38, r39,
1349 320 r40, r41, r42, r43, r44, r45, r46, r47,
1350 384 r48, r49, r50, r51, r52, r53, r54, r55,
1351 448 r56, r57, r58, r59, r60, r61, r62, r63,
1356 status reg., saved status reg., saved pc reg. (64-bit) 65-67
1359 target registers (64-bit) 68-75
1360 544 tr0, tr1, tr2, tr3, tr4, tr5, tr6, tr7,
1362 floating point state control register (32-bit) 76
1365 single precision floating point registers (32-bit) 77-140
1366 612 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
1367 644 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15,
1368 676 fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23,
1369 708 fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31,
1370 740 fr32, fr33, fr34, fr35, fr36, fr37, fr38, fr39,
1371 772 fr40, fr41, fr42, fr43, fr44, fr45, fr46, fr47,
1372 804 fr48, fr49, fr50, fr51, fr52, fr53, fr54, fr55,
1373 836 fr56, fr57, fr58, fr59, fr60, fr61, fr62, fr63,
1375 TOTAL SPACE FOR REGISTERS: 868 bytes
1377 From here on they are all pseudo registers: no memory allocated.
1378 REGISTER_BYTE returns the register byte for the base register.
1380 double precision registers (pseudo) 141-172
1381 dr0, dr2, dr4, dr6, dr8, dr10, dr12, dr14,
1382 dr16, dr18, dr20, dr22, dr24, dr26, dr28, dr30,
1383 dr32, dr34, dr36, dr38, dr40, dr42, dr44, dr46,
1384 dr48, dr50, dr52, dr54, dr56, dr58, dr60, dr62,
1386 floating point pairs (pseudo) 173-204
1387 fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14,
1388 fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30,
1389 fp32, fp34, fp36, fp38, fp40, fp42, fp44, fp46,
1390 fp48, fp50, fp52, fp54, fp56, fp58, fp60, fp62,
1392 floating point vectors (4 floating point regs) (pseudo) 205-220
1393 fv0, fv4, fv8, fv12, fv16, fv20, fv24, fv28,
1394 fv32, fv36, fv40, fv44, fv48, fv52, fv56, fv60,
1396 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
1397 r0_c, r1_c, r2_c, r3_c, r4_c, r5_c, r6_c, r7_c,
1398 r8_c, r9_c, r10_c, r11_c, r12_c, r13_c, r14_c, r15_c,
1400 gbr_c, mach_c, macl_c, pr_c, t_c,
1402 fr0_c, fr1_c, fr2_c, fr3_c, fr4_c, fr5_c, fr6_c, fr7_c,
1403 fr8_c, fr9_c, fr10_c, fr11_c, fr12_c, fr13_c, fr14_c, fr15_c
1404 dr0_c, dr2_c, dr4_c, dr6_c, dr8_c, dr10_c, dr12_c, dr14_c
1405 fv0_c, fv4_c, fv8_c, fv12_c
1408 static struct type
*
1409 sh64_build_float_register_type (struct gdbarch
*gdbarch
, int high
)
1411 return lookup_array_range_type (builtin_type (gdbarch
)->builtin_float
,
1415 /* Return the GDB type object for the "standard" data type
1416 of data in register REG_NR. */
1417 static struct type
*
1418 sh64_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
1420 if ((reg_nr
>= gdbarch_fp0_regnum (gdbarch
)
1421 && reg_nr
<= FP_LAST_REGNUM
)
1422 || (reg_nr
>= FP0_C_REGNUM
1423 && reg_nr
<= FP_LAST_C_REGNUM
))
1424 return builtin_type (gdbarch
)->builtin_float
;
1425 else if ((reg_nr
>= DR0_REGNUM
1426 && reg_nr
<= DR_LAST_REGNUM
)
1427 || (reg_nr
>= DR0_C_REGNUM
1428 && reg_nr
<= DR_LAST_C_REGNUM
))
1429 return builtin_type (gdbarch
)->builtin_double
;
1430 else if (reg_nr
>= FPP0_REGNUM
1431 && reg_nr
<= FPP_LAST_REGNUM
)
1432 return sh64_build_float_register_type (gdbarch
, 1);
1433 else if ((reg_nr
>= FV0_REGNUM
1434 && reg_nr
<= FV_LAST_REGNUM
)
1435 ||(reg_nr
>= FV0_C_REGNUM
1436 && reg_nr
<= FV_LAST_C_REGNUM
))
1437 return sh64_build_float_register_type (gdbarch
, 3);
1438 else if (reg_nr
== FPSCR_REGNUM
)
1439 return builtin_type (gdbarch
)->builtin_int
;
1440 else if (reg_nr
>= R0_C_REGNUM
1441 && reg_nr
< FP0_C_REGNUM
)
1442 return builtin_type (gdbarch
)->builtin_int
;
1444 return builtin_type (gdbarch
)->builtin_long_long
;
1448 sh64_register_convert_to_virtual (struct gdbarch
*gdbarch
, int regnum
,
1449 struct type
*type
, gdb_byte
*from
, gdb_byte
*to
)
1451 if (gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_LITTLE
)
1453 /* It is a no-op. */
1454 memcpy (to
, from
, register_size (gdbarch
, regnum
));
1458 if ((regnum
>= DR0_REGNUM
1459 && regnum
<= DR_LAST_REGNUM
)
1460 || (regnum
>= DR0_C_REGNUM
1461 && regnum
<= DR_LAST_C_REGNUM
))
1464 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword
,
1466 store_typed_floating (to
, type
, val
);
1469 error (_("sh64_register_convert_to_virtual "
1470 "called with non DR register number"));
1474 sh64_register_convert_to_raw (struct gdbarch
*gdbarch
, struct type
*type
,
1475 int regnum
, const void *from
, void *to
)
1477 if (gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_LITTLE
)
1479 /* It is a no-op. */
1480 memcpy (to
, from
, register_size (gdbarch
, regnum
));
1484 if ((regnum
>= DR0_REGNUM
1485 && regnum
<= DR_LAST_REGNUM
)
1486 || (regnum
>= DR0_C_REGNUM
1487 && regnum
<= DR_LAST_C_REGNUM
))
1489 DOUBLEST val
= extract_typed_floating (from
, type
);
1490 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword
,
1494 error (_("sh64_register_convert_to_raw called "
1495 "with non DR register number"));
1498 /* Concatenate PORTIONS contiguous raw registers starting at
1499 BASE_REGNUM into BUFFER. */
1501 static enum register_status
1502 pseudo_register_read_portions (struct gdbarch
*gdbarch
,
1503 struct regcache
*regcache
,
1505 int base_regnum
, gdb_byte
*buffer
)
1509 for (portion
= 0; portion
< portions
; portion
++)
1511 enum register_status status
;
1514 b
= buffer
+ register_size (gdbarch
, base_regnum
) * portion
;
1515 status
= regcache_raw_read (regcache
, base_regnum
+ portion
, b
);
1516 if (status
!= REG_VALID
)
1523 static enum register_status
1524 sh64_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1525 int reg_nr
, gdb_byte
*buffer
)
1527 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1530 gdb_byte temp_buffer
[MAX_REGISTER_SIZE
];
1531 enum register_status status
;
1533 if (reg_nr
>= DR0_REGNUM
1534 && reg_nr
<= DR_LAST_REGNUM
)
1536 base_regnum
= sh64_dr_reg_base_num (gdbarch
, reg_nr
);
1538 /* Build the value in the provided buffer. */
1539 /* DR regs are double precision registers obtained by
1540 concatenating 2 single precision floating point registers. */
1541 status
= pseudo_register_read_portions (gdbarch
, regcache
,
1542 2, base_regnum
, temp_buffer
);
1543 if (status
== REG_VALID
)
1545 /* We must pay attention to the endianness. */
1546 sh64_register_convert_to_virtual (gdbarch
, reg_nr
,
1547 register_type (gdbarch
, reg_nr
),
1548 temp_buffer
, buffer
);
1554 else if (reg_nr
>= FPP0_REGNUM
1555 && reg_nr
<= FPP_LAST_REGNUM
)
1557 base_regnum
= sh64_fpp_reg_base_num (gdbarch
, reg_nr
);
1559 /* Build the value in the provided buffer. */
1560 /* FPP regs are pairs of single precision registers obtained by
1561 concatenating 2 single precision floating point registers. */
1562 return pseudo_register_read_portions (gdbarch
, regcache
,
1563 2, base_regnum
, buffer
);
1566 else if (reg_nr
>= FV0_REGNUM
1567 && reg_nr
<= FV_LAST_REGNUM
)
1569 base_regnum
= sh64_fv_reg_base_num (gdbarch
, reg_nr
);
1571 /* Build the value in the provided buffer. */
1572 /* FV regs are vectors of single precision registers obtained by
1573 concatenating 4 single precision floating point registers. */
1574 return pseudo_register_read_portions (gdbarch
, regcache
,
1575 4, base_regnum
, buffer
);
1578 /* sh compact pseudo registers. 1-to-1 with a shmedia register. */
1579 else if (reg_nr
>= R0_C_REGNUM
1580 && reg_nr
<= T_C_REGNUM
)
1582 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1584 /* Build the value in the provided buffer. */
1585 status
= regcache_raw_read (regcache
, base_regnum
, temp_buffer
);
1586 if (status
!= REG_VALID
)
1588 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1591 temp_buffer
+ offset
, 4); /* get LOWER 32 bits only???? */
1595 else if (reg_nr
>= FP0_C_REGNUM
1596 && reg_nr
<= FP_LAST_C_REGNUM
)
1598 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1600 /* Build the value in the provided buffer. */
1601 /* Floating point registers map 1-1 to the media fp regs,
1602 they have the same size and endianness. */
1603 return regcache_raw_read (regcache
, base_regnum
, buffer
);
1606 else if (reg_nr
>= DR0_C_REGNUM
1607 && reg_nr
<= DR_LAST_C_REGNUM
)
1609 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1611 /* DR_C regs are double precision registers obtained by
1612 concatenating 2 single precision floating point registers. */
1613 status
= pseudo_register_read_portions (gdbarch
, regcache
,
1614 2, base_regnum
, temp_buffer
);
1615 if (status
== REG_VALID
)
1617 /* We must pay attention to the endianness. */
1618 sh64_register_convert_to_virtual (gdbarch
, reg_nr
,
1619 register_type (gdbarch
, reg_nr
),
1620 temp_buffer
, buffer
);
1625 else if (reg_nr
>= FV0_C_REGNUM
1626 && reg_nr
<= FV_LAST_C_REGNUM
)
1628 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1630 /* Build the value in the provided buffer. */
1631 /* FV_C regs are vectors of single precision registers obtained by
1632 concatenating 4 single precision floating point registers. */
1633 return pseudo_register_read_portions (gdbarch
, regcache
,
1634 4, base_regnum
, buffer
);
1637 else if (reg_nr
== FPSCR_C_REGNUM
)
1639 int fpscr_base_regnum
;
1641 unsigned int fpscr_value
;
1642 unsigned int sr_value
;
1643 unsigned int fpscr_c_value
;
1644 unsigned int fpscr_c_part1_value
;
1645 unsigned int fpscr_c_part2_value
;
1647 fpscr_base_regnum
= FPSCR_REGNUM
;
1648 sr_base_regnum
= SR_REGNUM
;
1650 /* Build the value in the provided buffer. */
1651 /* FPSCR_C is a very weird register that contains sparse bits
1652 from the FPSCR and the SR architectural registers.
1659 2-17 Bit 2-18 of FPSCR
1660 18-20 Bits 12,13,14 of SR
1664 /* Get FPSCR into a local buffer. */
1665 status
= regcache_raw_read (regcache
, fpscr_base_regnum
, temp_buffer
);
1666 if (status
!= REG_VALID
)
1668 /* Get value as an int. */
1669 fpscr_value
= extract_unsigned_integer (temp_buffer
, 4, byte_order
);
1670 /* Get SR into a local buffer */
1671 status
= regcache_raw_read (regcache
, sr_base_regnum
, temp_buffer
);
1672 if (status
!= REG_VALID
)
1674 /* Get value as an int. */
1675 sr_value
= extract_unsigned_integer (temp_buffer
, 4, byte_order
);
1676 /* Build the new value. */
1677 fpscr_c_part1_value
= fpscr_value
& 0x3fffd;
1678 fpscr_c_part2_value
= (sr_value
& 0x7000) << 6;
1679 fpscr_c_value
= fpscr_c_part1_value
| fpscr_c_part2_value
;
1680 /* Store that in out buffer!!! */
1681 store_unsigned_integer (buffer
, 4, byte_order
, fpscr_c_value
);
1682 /* FIXME There is surely an endianness gotcha here. */
1687 else if (reg_nr
== FPUL_C_REGNUM
)
1689 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1691 /* FPUL_C register is floating point register 32,
1692 same size, same endianness. */
1693 return regcache_raw_read (regcache
, base_regnum
, buffer
);
1696 gdb_assert_not_reached ("invalid pseudo register number");
1700 sh64_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1701 int reg_nr
, const gdb_byte
*buffer
)
1703 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1704 int base_regnum
, portion
;
1706 gdb_byte temp_buffer
[MAX_REGISTER_SIZE
];
1708 if (reg_nr
>= DR0_REGNUM
1709 && reg_nr
<= DR_LAST_REGNUM
)
1711 base_regnum
= sh64_dr_reg_base_num (gdbarch
, reg_nr
);
1712 /* We must pay attention to the endianness. */
1713 sh64_register_convert_to_raw (gdbarch
, register_type (gdbarch
, reg_nr
),
1715 buffer
, temp_buffer
);
1717 /* Write the real regs for which this one is an alias. */
1718 for (portion
= 0; portion
< 2; portion
++)
1719 regcache_raw_write (regcache
, base_regnum
+ portion
,
1721 + register_size (gdbarch
,
1722 base_regnum
) * portion
));
1725 else if (reg_nr
>= FPP0_REGNUM
1726 && reg_nr
<= FPP_LAST_REGNUM
)
1728 base_regnum
= sh64_fpp_reg_base_num (gdbarch
, reg_nr
);
1730 /* Write the real regs for which this one is an alias. */
1731 for (portion
= 0; portion
< 2; portion
++)
1732 regcache_raw_write (regcache
, base_regnum
+ portion
,
1733 (buffer
+ register_size (gdbarch
,
1734 base_regnum
) * portion
));
1737 else if (reg_nr
>= FV0_REGNUM
1738 && reg_nr
<= FV_LAST_REGNUM
)
1740 base_regnum
= sh64_fv_reg_base_num (gdbarch
, reg_nr
);
1742 /* Write the real regs for which this one is an alias. */
1743 for (portion
= 0; portion
< 4; portion
++)
1744 regcache_raw_write (regcache
, base_regnum
+ portion
,
1745 (buffer
+ register_size (gdbarch
,
1746 base_regnum
) * portion
));
1749 /* sh compact general pseudo registers. 1-to-1 with a shmedia
1750 register but only 4 bytes of it. */
1751 else if (reg_nr
>= R0_C_REGNUM
1752 && reg_nr
<= T_C_REGNUM
)
1754 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1755 /* reg_nr is 32 bit here, and base_regnum is 64 bits. */
1756 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1760 /* Let's read the value of the base register into a temporary
1761 buffer, so that overwriting the last four bytes with the new
1762 value of the pseudo will leave the upper 4 bytes unchanged. */
1763 regcache_raw_read (regcache
, base_regnum
, temp_buffer
);
1764 /* Write as an 8 byte quantity. */
1765 memcpy (temp_buffer
+ offset
, buffer
, 4);
1766 regcache_raw_write (regcache
, base_regnum
, temp_buffer
);
1769 /* sh floating point compact pseudo registers. 1-to-1 with a shmedia
1770 registers. Both are 4 bytes. */
1771 else if (reg_nr
>= FP0_C_REGNUM
1772 && reg_nr
<= FP_LAST_C_REGNUM
)
1774 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1775 regcache_raw_write (regcache
, base_regnum
, buffer
);
1778 else if (reg_nr
>= DR0_C_REGNUM
1779 && reg_nr
<= DR_LAST_C_REGNUM
)
1781 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1782 for (portion
= 0; portion
< 2; portion
++)
1784 /* We must pay attention to the endianness. */
1785 sh64_register_convert_to_raw (gdbarch
,
1786 register_type (gdbarch
, reg_nr
),
1788 buffer
, temp_buffer
);
1790 regcache_raw_write (regcache
, base_regnum
+ portion
,
1792 + register_size (gdbarch
,
1793 base_regnum
) * portion
));
1797 else if (reg_nr
>= FV0_C_REGNUM
1798 && reg_nr
<= FV_LAST_C_REGNUM
)
1800 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1802 for (portion
= 0; portion
< 4; portion
++)
1804 regcache_raw_write (regcache
, base_regnum
+ portion
,
1806 + register_size (gdbarch
,
1807 base_regnum
) * portion
));
1811 else if (reg_nr
== FPSCR_C_REGNUM
)
1813 int fpscr_base_regnum
;
1815 unsigned int fpscr_value
;
1816 unsigned int sr_value
;
1817 unsigned int old_fpscr_value
;
1818 unsigned int old_sr_value
;
1819 unsigned int fpscr_c_value
;
1820 unsigned int fpscr_mask
;
1821 unsigned int sr_mask
;
1823 fpscr_base_regnum
= FPSCR_REGNUM
;
1824 sr_base_regnum
= SR_REGNUM
;
1826 /* FPSCR_C is a very weird register that contains sparse bits
1827 from the FPSCR and the SR architectural registers.
1834 2-17 Bit 2-18 of FPSCR
1835 18-20 Bits 12,13,14 of SR
1839 /* Get value as an int. */
1840 fpscr_c_value
= extract_unsigned_integer (buffer
, 4, byte_order
);
1842 /* Build the new values. */
1843 fpscr_mask
= 0x0003fffd;
1844 sr_mask
= 0x001c0000;
1846 fpscr_value
= fpscr_c_value
& fpscr_mask
;
1847 sr_value
= (fpscr_value
& sr_mask
) >> 6;
1849 regcache_raw_read (regcache
, fpscr_base_regnum
, temp_buffer
);
1850 old_fpscr_value
= extract_unsigned_integer (temp_buffer
, 4, byte_order
);
1851 old_fpscr_value
&= 0xfffc0002;
1852 fpscr_value
|= old_fpscr_value
;
1853 store_unsigned_integer (temp_buffer
, 4, byte_order
, fpscr_value
);
1854 regcache_raw_write (regcache
, fpscr_base_regnum
, temp_buffer
);
1856 regcache_raw_read (regcache
, sr_base_regnum
, temp_buffer
);
1857 old_sr_value
= extract_unsigned_integer (temp_buffer
, 4, byte_order
);
1858 old_sr_value
&= 0xffff8fff;
1859 sr_value
|= old_sr_value
;
1860 store_unsigned_integer (temp_buffer
, 4, byte_order
, sr_value
);
1861 regcache_raw_write (regcache
, sr_base_regnum
, temp_buffer
);
1864 else if (reg_nr
== FPUL_C_REGNUM
)
1866 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1867 regcache_raw_write (regcache
, base_regnum
, buffer
);
1871 /* FIXME:!! THIS SHOULD TAKE CARE OF GETTING THE RIGHT PORTION OF THE
1872 shmedia REGISTERS. */
1873 /* Control registers, compact mode. */
1875 sh64_do_cr_c_register_info (struct ui_file
*file
, struct frame_info
*frame
,
1878 switch (cr_c_regnum
)
1881 fprintf_filtered (file
, "pc_c\t0x%08x\n",
1882 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1885 fprintf_filtered (file
, "gbr_c\t0x%08x\n",
1886 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1889 fprintf_filtered (file
, "mach_c\t0x%08x\n",
1890 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1893 fprintf_filtered (file
, "macl_c\t0x%08x\n",
1894 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1897 fprintf_filtered (file
, "pr_c\t0x%08x\n",
1898 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1901 fprintf_filtered (file
, "t_c\t0x%08x\n",
1902 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1904 case FPSCR_C_REGNUM
:
1905 fprintf_filtered (file
, "fpscr_c\t0x%08x\n",
1906 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1909 fprintf_filtered (file
, "fpul_c\t0x%08x\n",
1910 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1916 sh64_do_fp_register (struct gdbarch
*gdbarch
, struct ui_file
*file
,
1917 struct frame_info
*frame
, int regnum
)
1918 { /* Do values for FP (float) regs. */
1919 unsigned char *raw_buffer
;
1920 double flt
; /* Double extracted from raw hex data. */
1923 /* Allocate space for the float. */
1924 raw_buffer
= (unsigned char *)
1925 alloca (register_size (gdbarch
, gdbarch_fp0_regnum (gdbarch
)));
1927 /* Get the data in raw format. */
1928 if (!deprecated_frame_register_read (frame
, regnum
, raw_buffer
))
1929 error (_("can't read register %d (%s)"),
1930 regnum
, gdbarch_register_name (gdbarch
, regnum
));
1932 /* Get the register as a number. */
1933 flt
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
1936 /* Print the name and some spaces. */
1937 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
1938 print_spaces_filtered (15 - strlen (gdbarch_register_name
1939 (gdbarch
, regnum
)), file
);
1941 /* Print the value. */
1943 fprintf_filtered (file
, "<invalid float>");
1945 fprintf_filtered (file
, "%-10.9g", flt
);
1947 /* Print the fp register as hex. */
1948 fprintf_filtered (file
, "\t(raw ");
1949 print_hex_chars (file
, raw_buffer
,
1950 register_size (gdbarch
, regnum
),
1951 gdbarch_byte_order (gdbarch
));
1952 fprintf_filtered (file
, ")");
1953 fprintf_filtered (file
, "\n");
1957 sh64_do_pseudo_register (struct gdbarch
*gdbarch
, struct ui_file
*file
,
1958 struct frame_info
*frame
, int regnum
)
1960 /* All the sh64-compact mode registers are pseudo registers. */
1962 if (regnum
< gdbarch_num_regs (gdbarch
)
1963 || regnum
>= gdbarch_num_regs (gdbarch
)
1964 + NUM_PSEUDO_REGS_SH_MEDIA
1965 + NUM_PSEUDO_REGS_SH_COMPACT
)
1966 internal_error (__FILE__
, __LINE__
,
1967 _("Invalid pseudo register number %d\n"), regnum
);
1969 else if ((regnum
>= DR0_REGNUM
&& regnum
<= DR_LAST_REGNUM
))
1971 int fp_regnum
= sh64_dr_reg_base_num (gdbarch
, regnum
);
1972 fprintf_filtered (file
, "dr%d\t0x%08x%08x\n", regnum
- DR0_REGNUM
,
1973 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
),
1974 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 1));
1977 else if ((regnum
>= DR0_C_REGNUM
&& regnum
<= DR_LAST_C_REGNUM
))
1979 int fp_regnum
= sh64_compact_reg_base_num (gdbarch
, regnum
);
1980 fprintf_filtered (file
, "dr%d_c\t0x%08x%08x\n", regnum
- DR0_C_REGNUM
,
1981 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
),
1982 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 1));
1985 else if ((regnum
>= FV0_REGNUM
&& regnum
<= FV_LAST_REGNUM
))
1987 int fp_regnum
= sh64_fv_reg_base_num (gdbarch
, regnum
);
1988 fprintf_filtered (file
, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
1989 regnum
- FV0_REGNUM
,
1990 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
),
1991 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 1),
1992 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 2),
1993 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 3));
1996 else if ((regnum
>= FV0_C_REGNUM
&& regnum
<= FV_LAST_C_REGNUM
))
1998 int fp_regnum
= sh64_compact_reg_base_num (gdbarch
, regnum
);
1999 fprintf_filtered (file
, "fv%d_c\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
2000 regnum
- FV0_C_REGNUM
,
2001 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
),
2002 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 1),
2003 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 2),
2004 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 3));
2007 else if (regnum
>= FPP0_REGNUM
&& regnum
<= FPP_LAST_REGNUM
)
2009 int fp_regnum
= sh64_fpp_reg_base_num (gdbarch
, regnum
);
2010 fprintf_filtered (file
, "fpp%d\t0x%08x\t0x%08x\n", regnum
- FPP0_REGNUM
,
2011 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
),
2012 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 1));
2015 else if (regnum
>= R0_C_REGNUM
&& regnum
<= R_LAST_C_REGNUM
)
2017 int c_regnum
= sh64_compact_reg_base_num (gdbarch
, regnum
);
2018 fprintf_filtered (file
, "r%d_c\t0x%08x\n", regnum
- R0_C_REGNUM
,
2019 (unsigned) get_frame_register_unsigned (frame
, c_regnum
));
2021 else if (regnum
>= FP0_C_REGNUM
&& regnum
<= FP_LAST_C_REGNUM
)
2022 /* This should work also for pseudoregs. */
2023 sh64_do_fp_register (gdbarch
, file
, frame
, regnum
);
2024 else if (regnum
>= PC_C_REGNUM
&& regnum
<= FPUL_C_REGNUM
)
2025 sh64_do_cr_c_register_info (file
, frame
, regnum
);
2029 sh64_do_register (struct gdbarch
*gdbarch
, struct ui_file
*file
,
2030 struct frame_info
*frame
, int regnum
)
2032 unsigned char raw_buffer
[MAX_REGISTER_SIZE
];
2033 struct value_print_options opts
;
2035 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
2036 print_spaces_filtered (15 - strlen (gdbarch_register_name
2037 (gdbarch
, regnum
)), file
);
2039 /* Get the data in raw format. */
2040 if (!deprecated_frame_register_read (frame
, regnum
, raw_buffer
))
2042 fprintf_filtered (file
, "*value not available*\n");
2046 get_formatted_print_options (&opts
, 'x');
2048 val_print (register_type (gdbarch
, regnum
), raw_buffer
, 0, 0,
2049 file
, 0, NULL
, &opts
, current_language
);
2050 fprintf_filtered (file
, "\t");
2051 get_formatted_print_options (&opts
, 0);
2053 val_print (register_type (gdbarch
, regnum
), raw_buffer
, 0, 0,
2054 file
, 0, NULL
, &opts
, current_language
);
2055 fprintf_filtered (file
, "\n");
2059 sh64_print_register (struct gdbarch
*gdbarch
, struct ui_file
*file
,
2060 struct frame_info
*frame
, int regnum
)
2062 if (regnum
< 0 || regnum
>= gdbarch_num_regs (gdbarch
)
2063 + gdbarch_num_pseudo_regs (gdbarch
))
2064 internal_error (__FILE__
, __LINE__
,
2065 _("Invalid register number %d\n"), regnum
);
2067 else if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
))
2069 if (TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
2070 sh64_do_fp_register (gdbarch
, file
, frame
, regnum
); /* FP regs */
2072 sh64_do_register (gdbarch
, file
, frame
, regnum
);
2075 else if (regnum
< gdbarch_num_regs (gdbarch
)
2076 + gdbarch_num_pseudo_regs (gdbarch
))
2077 sh64_do_pseudo_register (gdbarch
, file
, frame
, regnum
);
2081 sh64_media_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
2082 struct frame_info
*frame
, int regnum
,
2085 if (regnum
!= -1) /* Do one specified register. */
2087 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
2088 error (_("Not a valid register for the current processor type"));
2090 sh64_print_register (gdbarch
, file
, frame
, regnum
);
2093 /* Do all (or most) registers. */
2096 while (regnum
< gdbarch_num_regs (gdbarch
))
2098 /* If the register name is empty, it is undefined for this
2099 processor, so don't display anything. */
2100 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
2101 || *(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
2107 if (TYPE_CODE (register_type (gdbarch
, regnum
))
2112 /* true for "INFO ALL-REGISTERS" command. */
2113 sh64_do_fp_register (gdbarch
, file
, frame
, regnum
);
2117 regnum
+= FP_LAST_REGNUM
- gdbarch_fp0_regnum (gdbarch
);
2122 sh64_do_register (gdbarch
, file
, frame
, regnum
);
2128 while (regnum
< gdbarch_num_regs (gdbarch
)
2129 + gdbarch_num_pseudo_regs (gdbarch
))
2131 sh64_do_pseudo_register (gdbarch
, file
, frame
, regnum
);
2138 sh64_compact_print_registers_info (struct gdbarch
*gdbarch
,
2139 struct ui_file
*file
,
2140 struct frame_info
*frame
, int regnum
,
2143 if (regnum
!= -1) /* Do one specified register. */
2145 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
2146 error (_("Not a valid register for the current processor type"));
2148 if (regnum
>= 0 && regnum
< R0_C_REGNUM
)
2149 error (_("Not a valid register for the current processor mode."));
2151 sh64_print_register (gdbarch
, file
, frame
, regnum
);
2154 /* Do all compact registers. */
2156 regnum
= R0_C_REGNUM
;
2157 while (regnum
< gdbarch_num_regs (gdbarch
)
2158 + gdbarch_num_pseudo_regs (gdbarch
))
2160 sh64_do_pseudo_register (gdbarch
, file
, frame
, regnum
);
2167 sh64_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
2168 struct frame_info
*frame
, int regnum
, int fpregs
)
2170 if (pc_is_isa32 (get_frame_pc (frame
)))
2171 sh64_media_print_registers_info (gdbarch
, file
, frame
, regnum
, fpregs
);
2173 sh64_compact_print_registers_info (gdbarch
, file
, frame
, regnum
, fpregs
);
2176 static struct sh64_frame_cache
*
2177 sh64_alloc_frame_cache (void)
2179 struct sh64_frame_cache
*cache
;
2182 cache
= FRAME_OBSTACK_ZALLOC (struct sh64_frame_cache
);
2186 cache
->saved_sp
= 0;
2187 cache
->sp_offset
= 0;
2190 /* Frameless until proven otherwise. */
2193 /* Saved registers. We initialize these to -1 since zero is a valid
2194 offset (that's where fp is supposed to be stored). */
2195 for (i
= 0; i
< SIM_SH64_NR_REGS
; i
++)
2197 cache
->saved_regs
[i
] = -1;
2203 static struct sh64_frame_cache
*
2204 sh64_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2206 struct gdbarch
*gdbarch
;
2207 struct sh64_frame_cache
*cache
;
2208 CORE_ADDR current_pc
;
2212 return (struct sh64_frame_cache
*) *this_cache
;
2214 gdbarch
= get_frame_arch (this_frame
);
2215 cache
= sh64_alloc_frame_cache ();
2216 *this_cache
= cache
;
2218 current_pc
= get_frame_pc (this_frame
);
2219 cache
->media_mode
= pc_is_isa32 (current_pc
);
2221 /* In principle, for normal frames, fp holds the frame pointer,
2222 which holds the base address for the current stack frame.
2223 However, for functions that don't need it, the frame pointer is
2224 optional. For these "frameless" functions the frame pointer is
2225 actually the frame pointer of the calling frame. */
2226 cache
->base
= get_frame_register_unsigned (this_frame
, MEDIA_FP_REGNUM
);
2227 if (cache
->base
== 0)
2230 cache
->pc
= get_frame_func (this_frame
);
2232 sh64_analyze_prologue (gdbarch
, cache
, cache
->pc
, current_pc
);
2234 if (!cache
->uses_fp
)
2236 /* We didn't find a valid frame, which means that CACHE->base
2237 currently holds the frame pointer for our calling frame. If
2238 we're at the start of a function, or somewhere half-way its
2239 prologue, the function's frame probably hasn't been fully
2240 setup yet. Try to reconstruct the base address for the stack
2241 frame by looking at the stack pointer. For truly "frameless"
2242 functions this might work too. */
2243 cache
->base
= get_frame_register_unsigned
2244 (this_frame
, gdbarch_sp_regnum (gdbarch
));
2247 /* Now that we have the base address for the stack frame we can
2248 calculate the value of sp in the calling frame. */
2249 cache
->saved_sp
= cache
->base
+ cache
->sp_offset
;
2251 /* Adjust all the saved registers such that they contain addresses
2252 instead of offsets. */
2253 for (i
= 0; i
< SIM_SH64_NR_REGS
; i
++)
2254 if (cache
->saved_regs
[i
] != -1)
2255 cache
->saved_regs
[i
] = cache
->saved_sp
- cache
->saved_regs
[i
];
2260 static struct value
*
2261 sh64_frame_prev_register (struct frame_info
*this_frame
,
2262 void **this_cache
, int regnum
)
2264 struct sh64_frame_cache
*cache
= sh64_frame_cache (this_frame
, this_cache
);
2265 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2266 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2268 gdb_assert (regnum
>= 0);
2270 if (regnum
== gdbarch_sp_regnum (gdbarch
) && cache
->saved_sp
)
2271 frame_unwind_got_constant (this_frame
, regnum
, cache
->saved_sp
);
2273 /* The PC of the previous frame is stored in the PR register of
2274 the current frame. Frob regnum so that we pull the value from
2275 the correct place. */
2276 if (regnum
== gdbarch_pc_regnum (gdbarch
))
2279 if (regnum
< SIM_SH64_NR_REGS
&& cache
->saved_regs
[regnum
] != -1)
2281 if (gdbarch_tdep (gdbarch
)->sh_abi
== SH_ABI_32
2282 && (regnum
== MEDIA_FP_REGNUM
|| regnum
== PR_REGNUM
))
2285 val
= read_memory_unsigned_integer (cache
->saved_regs
[regnum
],
2287 return frame_unwind_got_constant (this_frame
, regnum
, val
);
2290 return frame_unwind_got_memory (this_frame
, regnum
,
2291 cache
->saved_regs
[regnum
]);
2294 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
2298 sh64_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2299 struct frame_id
*this_id
)
2301 struct sh64_frame_cache
*cache
= sh64_frame_cache (this_frame
, this_cache
);
2303 /* This marks the outermost frame. */
2304 if (cache
->base
== 0)
2307 *this_id
= frame_id_build (cache
->saved_sp
, cache
->pc
);
2310 static const struct frame_unwind sh64_frame_unwind
= {
2312 default_frame_unwind_stop_reason
,
2314 sh64_frame_prev_register
,
2316 default_frame_sniffer
2320 sh64_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2322 return frame_unwind_register_unsigned (next_frame
,
2323 gdbarch_sp_regnum (gdbarch
));
2327 sh64_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2329 return frame_unwind_register_unsigned (next_frame
,
2330 gdbarch_pc_regnum (gdbarch
));
2333 static struct frame_id
2334 sh64_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2336 CORE_ADDR sp
= get_frame_register_unsigned (this_frame
,
2337 gdbarch_sp_regnum (gdbarch
));
2338 return frame_id_build (sp
, get_frame_pc (this_frame
));
2342 sh64_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2344 struct sh64_frame_cache
*cache
= sh64_frame_cache (this_frame
, this_cache
);
2349 static const struct frame_base sh64_frame_base
= {
2351 sh64_frame_base_address
,
2352 sh64_frame_base_address
,
2353 sh64_frame_base_address
2358 sh64_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2360 struct gdbarch
*gdbarch
;
2361 struct gdbarch_tdep
*tdep
;
2363 /* If there is already a candidate, use it. */
2364 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2366 return arches
->gdbarch
;
2368 /* None found, create a new architecture from the information
2370 tdep
= XNEW (struct gdbarch_tdep
);
2371 gdbarch
= gdbarch_alloc (&info
, tdep
);
2373 /* Determine the ABI */
2374 if (info
.abfd
&& bfd_get_arch_size (info
.abfd
) == 64)
2376 /* If the ABI is the 64-bit one, it can only be sh-media. */
2377 tdep
->sh_abi
= SH_ABI_64
;
2378 set_gdbarch_ptr_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2379 set_gdbarch_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2383 /* If the ABI is the 32-bit one it could be either media or
2385 tdep
->sh_abi
= SH_ABI_32
;
2386 set_gdbarch_ptr_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2387 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2390 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
2391 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2392 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2393 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2394 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2395 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2396 set_gdbarch_long_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2398 /* The number of real registers is the same whether we are in
2399 ISA16(compact) or ISA32(media). */
2400 set_gdbarch_num_regs (gdbarch
, SIM_SH64_NR_REGS
);
2401 set_gdbarch_sp_regnum (gdbarch
, 15);
2402 set_gdbarch_pc_regnum (gdbarch
, 64);
2403 set_gdbarch_fp0_regnum (gdbarch
, SIM_SH64_FR0_REGNUM
);
2404 set_gdbarch_num_pseudo_regs (gdbarch
, NUM_PSEUDO_REGS_SH_MEDIA
2405 + NUM_PSEUDO_REGS_SH_COMPACT
);
2407 set_gdbarch_register_name (gdbarch
, sh64_register_name
);
2408 set_gdbarch_register_type (gdbarch
, sh64_register_type
);
2410 set_gdbarch_pseudo_register_read (gdbarch
, sh64_pseudo_register_read
);
2411 set_gdbarch_pseudo_register_write (gdbarch
, sh64_pseudo_register_write
);
2413 set_gdbarch_breakpoint_from_pc (gdbarch
, sh64_breakpoint_from_pc
);
2415 set_gdbarch_print_insn (gdbarch
, print_insn_sh
);
2416 set_gdbarch_register_sim_regno (gdbarch
, legacy_register_sim_regno
);
2418 set_gdbarch_return_value (gdbarch
, sh64_return_value
);
2420 set_gdbarch_skip_prologue (gdbarch
, sh64_skip_prologue
);
2421 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2423 set_gdbarch_push_dummy_call (gdbarch
, sh64_push_dummy_call
);
2425 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
2427 set_gdbarch_frame_align (gdbarch
, sh64_frame_align
);
2428 set_gdbarch_unwind_sp (gdbarch
, sh64_unwind_sp
);
2429 set_gdbarch_unwind_pc (gdbarch
, sh64_unwind_pc
);
2430 set_gdbarch_dummy_id (gdbarch
, sh64_dummy_id
);
2431 frame_base_set_default (gdbarch
, &sh64_frame_base
);
2433 set_gdbarch_print_registers_info (gdbarch
, sh64_print_registers_info
);
2435 set_gdbarch_elf_make_msymbol_special (gdbarch
,
2436 sh64_elf_make_msymbol_special
);
2438 /* Hook in ABI-specific overrides, if they have been registered. */
2439 gdbarch_init_osabi (info
, gdbarch
);
2441 dwarf2_append_unwinders (gdbarch
);
2442 frame_unwind_append_unwinder (gdbarch
, &sh64_frame_unwind
);