1 /* Target-dependent code for the SPARC for GDB, the GNU debugger.
3 Copyright 1986, 1987, 1989, 1990, 1991, 1992, 1993, 1994, 1995,
4 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation,
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
24 /* ??? Support for calling functions from gdb in sparc64 is unfinished. */
27 #include "arch-utils.h"
33 #include "gdb_string.h"
38 #include <sys/procfs.h>
39 /* Prototypes for supply_gregset etc. */
45 #include "symfile.h" /* for 'entry_point_address' */
48 * Some local macros that have multi-arch and non-multi-arch versions:
51 #if (GDB_MULTI_ARCH > 0)
53 /* Does the target have Floating Point registers? */
54 #define SPARC_HAS_FPU (gdbarch_tdep (current_gdbarch)->has_fpu)
55 /* Number of bytes devoted to Floating Point registers: */
56 #define FP_REGISTER_BYTES (gdbarch_tdep (current_gdbarch)->fp_register_bytes)
57 /* Highest numbered Floating Point register. */
58 #define FP_MAX_REGNUM (gdbarch_tdep (current_gdbarch)->fp_max_regnum)
59 /* Size of a general (integer) register: */
60 #define SPARC_INTREG_SIZE (gdbarch_tdep (current_gdbarch)->intreg_size)
61 /* Offset within the call dummy stack of the saved registers. */
62 #define DUMMY_REG_SAVE_OFFSET (gdbarch_tdep (current_gdbarch)->reg_save_offset)
64 #else /* non-multi-arch */
67 /* Does the target have Floating Point registers? */
68 #if defined(TARGET_SPARCLET) || defined(TARGET_SPARCLITE)
69 #define SPARC_HAS_FPU 0
71 #define SPARC_HAS_FPU 1
74 /* Number of bytes devoted to Floating Point registers: */
75 #if (GDB_TARGET_IS_SPARC64)
76 #define FP_REGISTER_BYTES (64 * 4)
79 #define FP_REGISTER_BYTES (32 * 4)
81 #define FP_REGISTER_BYTES 0
85 /* Highest numbered Floating Point register. */
86 #if (GDB_TARGET_IS_SPARC64)
87 #define FP_MAX_REGNUM (FP0_REGNUM + 48)
89 #define FP_MAX_REGNUM (FP0_REGNUM + 32)
92 /* Size of a general (integer) register: */
93 #define SPARC_INTREG_SIZE (REGISTER_RAW_SIZE (G0_REGNUM))
95 /* Offset within the call dummy stack of the saved registers. */
96 #if (GDB_TARGET_IS_SPARC64)
97 #define DUMMY_REG_SAVE_OFFSET (128 + 16)
99 #define DUMMY_REG_SAVE_OFFSET 0x60
102 #endif /* GDB_MULTI_ARCH */
107 int fp_register_bytes
;
112 int call_dummy_call_offset
;
115 enum gdb_osabi osabi
;
118 /* Now make GDB_TARGET_IS_SPARC64 a runtime test. */
119 /* FIXME MVS: or try testing bfd_arch_info.arch and bfd_arch_info.mach ...
120 * define GDB_TARGET_IS_SPARC64 \
121 * (TARGET_ARCHITECTURE->arch == bfd_arch_sparc && \
122 * (TARGET_ARCHITECTURE->mach == bfd_mach_sparc_v9 || \
123 * TARGET_ARCHITECTURE->mach == bfd_mach_sparc_v9a))
127 extern int stop_after_trap
;
129 /* We don't store all registers immediately when requested, since they
130 get sent over in large chunks anyway. Instead, we accumulate most
131 of the changes and send them over once. "deferred_stores" keeps
132 track of which sets of registers we have locally-changed copies of,
133 so we only need send the groups that have changed. */
135 int deferred_stores
= 0; /* Accumulated stores we want to do eventually. */
138 /* Some machines, such as Fujitsu SPARClite 86x, have a bi-endian mode
139 where instructions are big-endian and data are little-endian.
140 This flag is set when we detect that the target is of this type. */
145 /* Fetch a single instruction. Even on bi-endian machines
146 such as sparc86x, instructions are always big-endian. */
149 fetch_instruction (CORE_ADDR pc
)
151 unsigned long retval
;
153 unsigned char buf
[4];
155 read_memory (pc
, buf
, sizeof (buf
));
157 /* Start at the most significant end of the integer, and work towards
158 the least significant. */
160 for (i
= 0; i
< sizeof (buf
); ++i
)
161 retval
= (retval
<< 8) | buf
[i
];
166 /* Branches with prediction are treated like their non-predicting cousins. */
167 /* FIXME: What about floating point branches? */
169 /* Macros to extract fields from sparc instructions. */
170 #define X_OP(i) (((i) >> 30) & 0x3)
171 #define X_RD(i) (((i) >> 25) & 0x1f)
172 #define X_A(i) (((i) >> 29) & 1)
173 #define X_COND(i) (((i) >> 25) & 0xf)
174 #define X_OP2(i) (((i) >> 22) & 0x7)
175 #define X_IMM22(i) ((i) & 0x3fffff)
176 #define X_OP3(i) (((i) >> 19) & 0x3f)
177 #define X_RS1(i) (((i) >> 14) & 0x1f)
178 #define X_I(i) (((i) >> 13) & 1)
179 #define X_IMM13(i) ((i) & 0x1fff)
180 /* Sign extension macros. */
181 #define X_SIMM13(i) ((X_IMM13 (i) ^ 0x1000) - 0x1000)
182 #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000)
183 #define X_CC(i) (((i) >> 20) & 3)
184 #define X_P(i) (((i) >> 19) & 1)
185 #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000)
186 #define X_RCOND(i) (((i) >> 25) & 7)
187 #define X_DISP16(i) ((((((i) >> 6) && 0xc000) | ((i) & 0x3fff)) ^ 0x8000) - 0x8000)
188 #define X_FCN(i) (((i) >> 25) & 31)
192 Error
, not_branch
, bicc
, bicca
, ba
, baa
, ticc
, ta
, done_retry
195 /* Simulate single-step ptrace call for sun4. Code written by Gary
196 Beihl (beihl@mcc.com). */
198 /* npc4 and next_pc describe the situation at the time that the
199 step-breakpoint was set, not necessary the current value of NPC_REGNUM. */
200 static CORE_ADDR next_pc
, npc4
, target
;
201 static int brknpc4
, brktrg
;
202 typedef char binsn_quantum
[BREAKPOINT_MAX
];
203 static binsn_quantum break_mem
[3];
205 static branch_type
isbranch (long, CORE_ADDR
, CORE_ADDR
*);
207 /* single_step() is called just before we want to resume the inferior,
208 if we want to single-step it but there is no hardware or kernel single-step
209 support (as on all SPARCs). We find all the possible targets of the
210 coming instruction and breakpoint them.
212 single_step is also called just after the inferior stops. If we had
213 set up a simulated single-step, we undo our damage. */
216 sparc_software_single_step (enum target_signal ignore
, /* pid, but we don't need it */
217 int insert_breakpoints_p
)
223 if (insert_breakpoints_p
)
225 /* Always set breakpoint for NPC. */
226 next_pc
= read_register (NPC_REGNUM
);
227 npc4
= next_pc
+ 4; /* branch not taken */
229 target_insert_breakpoint (next_pc
, break_mem
[0]);
230 /* printf_unfiltered ("set break at %x\n",next_pc); */
232 pc
= read_register (PC_REGNUM
);
233 pc_instruction
= fetch_instruction (pc
);
234 br
= isbranch (pc_instruction
, pc
, &target
);
235 brknpc4
= brktrg
= 0;
239 /* Conditional annulled branch will either end up at
240 npc (if taken) or at npc+4 (if not taken).
243 target_insert_breakpoint (npc4
, break_mem
[1]);
245 else if (br
== baa
&& target
!= next_pc
)
247 /* Unconditional annulled branch will always end up at
250 target_insert_breakpoint (target
, break_mem
[2]);
252 else if (GDB_TARGET_IS_SPARC64
&& br
== done_retry
)
255 target_insert_breakpoint (target
, break_mem
[2]);
260 /* Remove breakpoints */
261 target_remove_breakpoint (next_pc
, break_mem
[0]);
264 target_remove_breakpoint (npc4
, break_mem
[1]);
267 target_remove_breakpoint (target
, break_mem
[2]);
271 struct frame_extra_info
276 /* Following fields only relevant for flat frames. */
279 /* Add this to ->frame to get the value of the stack pointer at the
280 time of the register saves. */
284 /* Call this for each newly created frame. For SPARC, we need to
285 calculate the bottom of the frame, and do some extra work if the
286 prologue has been generated via the -mflat option to GCC. In
287 particular, we need to know where the previous fp and the pc have
288 been stashed, since their exact position within the frame may vary. */
291 sparc_init_extra_frame_info (int fromleaf
, struct frame_info
*fi
)
294 CORE_ADDR prologue_start
, prologue_end
;
297 fi
->extra_info
= (struct frame_extra_info
*)
298 frame_obstack_alloc (sizeof (struct frame_extra_info
));
299 frame_saved_regs_zalloc (fi
);
301 fi
->extra_info
->bottom
=
303 (fi
->frame
== fi
->next
->frame
? fi
->next
->extra_info
->bottom
:
304 fi
->next
->frame
) : read_sp ());
306 /* If fi->next is NULL, then we already set ->frame by passing read_fp()
307 to create_new_frame. */
312 buf
= alloca (MAX_REGISTER_RAW_SIZE
);
314 /* Compute ->frame as if not flat. If it is flat, we'll change
316 if (fi
->next
->next
!= NULL
317 && (fi
->next
->next
->signal_handler_caller
318 || frame_in_dummy (fi
->next
->next
))
319 && frameless_look_for_prologue (fi
->next
))
321 /* A frameless function interrupted by a signal did not change
322 the frame pointer, fix up frame pointer accordingly. */
323 fi
->frame
= FRAME_FP (fi
->next
);
324 fi
->extra_info
->bottom
= fi
->next
->extra_info
->bottom
;
328 /* Should we adjust for stack bias here? */
329 get_saved_register (buf
, 0, 0, fi
, FP_REGNUM
, 0);
330 fi
->frame
= extract_address (buf
, REGISTER_RAW_SIZE (FP_REGNUM
));
332 if (GDB_TARGET_IS_SPARC64
&& (fi
->frame
& 1))
337 /* Decide whether this is a function with a ``flat register window''
338 frame. For such functions, the frame pointer is actually in %i7. */
339 fi
->extra_info
->flat
= 0;
340 fi
->extra_info
->in_prologue
= 0;
341 if (find_pc_partial_function (fi
->pc
, &name
, &prologue_start
, &prologue_end
))
343 /* See if the function starts with an add (which will be of a
344 negative number if a flat frame) to the sp. FIXME: Does not
345 handle large frames which will need more than one instruction
347 insn
= fetch_instruction (prologue_start
);
348 if (X_OP (insn
) == 2 && X_RD (insn
) == 14 && X_OP3 (insn
) == 0
349 && X_I (insn
) && X_SIMM13 (insn
) < 0)
351 int offset
= X_SIMM13 (insn
);
353 /* Then look for a save of %i7 into the frame. */
354 insn
= fetch_instruction (prologue_start
+ 4);
358 && X_RS1 (insn
) == 14)
362 buf
= alloca (MAX_REGISTER_RAW_SIZE
);
364 /* We definitely have a flat frame now. */
365 fi
->extra_info
->flat
= 1;
367 fi
->extra_info
->sp_offset
= offset
;
369 /* Overwrite the frame's address with the value in %i7. */
370 get_saved_register (buf
, 0, 0, fi
, I7_REGNUM
, 0);
371 fi
->frame
= extract_address (buf
, REGISTER_RAW_SIZE (I7_REGNUM
));
373 if (GDB_TARGET_IS_SPARC64
&& (fi
->frame
& 1))
376 /* Record where the fp got saved. */
377 fi
->extra_info
->fp_addr
=
378 fi
->frame
+ fi
->extra_info
->sp_offset
+ X_SIMM13 (insn
);
380 /* Also try to collect where the pc got saved to. */
381 fi
->extra_info
->pc_addr
= 0;
382 insn
= fetch_instruction (prologue_start
+ 12);
386 && X_RS1 (insn
) == 14)
387 fi
->extra_info
->pc_addr
=
388 fi
->frame
+ fi
->extra_info
->sp_offset
+ X_SIMM13 (insn
);
393 /* Check if the PC is in the function prologue before a SAVE
394 instruction has been executed yet. If so, set the frame
395 to the current value of the stack pointer and set
396 the in_prologue flag. */
398 struct symtab_and_line sal
;
400 sal
= find_pc_line (prologue_start
, 0);
401 if (sal
.line
== 0) /* no line info, use PC */
402 prologue_end
= fi
->pc
;
403 else if (sal
.end
< prologue_end
)
404 prologue_end
= sal
.end
;
405 if (fi
->pc
< prologue_end
)
407 for (addr
= prologue_start
; addr
< fi
->pc
; addr
+= 4)
409 insn
= read_memory_integer (addr
, 4);
410 if (X_OP (insn
) == 2 && X_OP3 (insn
) == 0x3c)
411 break; /* SAVE seen, stop searching */
415 fi
->extra_info
->in_prologue
= 1;
416 fi
->frame
= read_register (SP_REGNUM
);
421 if (fi
->next
&& fi
->frame
== 0)
423 /* Kludge to cause init_prev_frame_info to destroy the new frame. */
424 fi
->frame
= fi
->next
->frame
;
425 fi
->pc
= fi
->next
->pc
;
430 sparc_frame_chain (struct frame_info
*frame
)
432 /* Value that will cause FRAME_CHAIN_VALID to not worry about the chain
433 value. If it really is zero, we detect it later in
434 sparc_init_prev_frame. */
435 return (CORE_ADDR
) 1;
439 sparc_extract_struct_value_address (char *regbuf
)
441 return extract_address (regbuf
+ REGISTER_BYTE (O0_REGNUM
),
442 REGISTER_RAW_SIZE (O0_REGNUM
));
445 /* Find the pc saved in frame FRAME. */
448 sparc_frame_saved_pc (struct frame_info
*frame
)
453 buf
= alloca (MAX_REGISTER_RAW_SIZE
);
454 if (frame
->signal_handler_caller
)
456 /* This is the signal trampoline frame.
457 Get the saved PC from the sigcontext structure. */
459 #ifndef SIGCONTEXT_PC_OFFSET
460 #define SIGCONTEXT_PC_OFFSET 12
463 CORE_ADDR sigcontext_addr
;
465 int saved_pc_offset
= SIGCONTEXT_PC_OFFSET
;
468 scbuf
= alloca (TARGET_PTR_BIT
/ HOST_CHAR_BIT
);
470 /* Solaris2 ucbsigvechandler passes a pointer to a sigcontext
471 as the third parameter. The offset to the saved pc is 12. */
472 find_pc_partial_function (frame
->pc
, &name
,
473 (CORE_ADDR
*) NULL
, (CORE_ADDR
*) NULL
);
474 if (name
&& STREQ (name
, "ucbsigvechandler"))
475 saved_pc_offset
= 12;
477 /* The sigcontext address is contained in register O2. */
478 get_saved_register (buf
, (int *) NULL
, (CORE_ADDR
*) NULL
,
479 frame
, O0_REGNUM
+ 2, (enum lval_type
*) NULL
);
480 sigcontext_addr
= extract_address (buf
, REGISTER_RAW_SIZE (O0_REGNUM
+ 2));
482 /* Don't cause a memory_error when accessing sigcontext in case the
483 stack layout has changed or the stack is corrupt. */
484 target_read_memory (sigcontext_addr
+ saved_pc_offset
,
485 scbuf
, sizeof (scbuf
));
486 return extract_address (scbuf
, sizeof (scbuf
));
488 else if (frame
->extra_info
->in_prologue
||
489 (frame
->next
!= NULL
&&
490 (frame
->next
->signal_handler_caller
||
491 frame_in_dummy (frame
->next
)) &&
492 frameless_look_for_prologue (frame
)))
494 /* A frameless function interrupted by a signal did not save
495 the PC, it is still in %o7. */
496 get_saved_register (buf
, (int *) NULL
, (CORE_ADDR
*) NULL
,
497 frame
, O7_REGNUM
, (enum lval_type
*) NULL
);
498 return PC_ADJUST (extract_address (buf
, SPARC_INTREG_SIZE
));
500 if (frame
->extra_info
->flat
)
501 addr
= frame
->extra_info
->pc_addr
;
503 addr
= frame
->extra_info
->bottom
+ FRAME_SAVED_I0
+
504 SPARC_INTREG_SIZE
* (I7_REGNUM
- I0_REGNUM
);
507 /* A flat frame leaf function might not save the PC anywhere,
508 just leave it in %o7. */
509 return PC_ADJUST (read_register (O7_REGNUM
));
511 read_memory (addr
, buf
, SPARC_INTREG_SIZE
);
512 return PC_ADJUST (extract_address (buf
, SPARC_INTREG_SIZE
));
515 /* Since an individual frame in the frame cache is defined by two
516 arguments (a frame pointer and a stack pointer), we need two
517 arguments to get info for an arbitrary stack frame. This routine
518 takes two arguments and makes the cached frames look as if these
519 two arguments defined a frame on the cache. This allows the rest
520 of info frame to extract the important arguments without
524 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
526 struct frame_info
*frame
;
529 error ("Sparc frame specifications require two arguments: fp and sp");
531 frame
= create_new_frame (argv
[0], 0);
534 internal_error (__FILE__
, __LINE__
,
535 "create_new_frame returned invalid frame");
537 frame
->extra_info
->bottom
= argv
[1];
538 frame
->pc
= FRAME_SAVED_PC (frame
);
542 /* Given a pc value, skip it forward past the function prologue by
543 disassembling instructions that appear to be a prologue.
545 If FRAMELESS_P is set, we are only testing to see if the function
546 is frameless. This allows a quicker answer.
548 This routine should be more specific in its actions; making sure
549 that it uses the same register in the initial prologue section. */
551 static CORE_ADDR
examine_prologue (CORE_ADDR
, int, struct frame_info
*,
555 examine_prologue (CORE_ADDR start_pc
, int frameless_p
, struct frame_info
*fi
,
556 CORE_ADDR
*saved_regs
)
560 CORE_ADDR pc
= start_pc
;
563 insn
= fetch_instruction (pc
);
565 /* Recognize the `sethi' insn and record its destination. */
566 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 4)
570 insn
= fetch_instruction (pc
);
573 /* Recognize an add immediate value to register to either %g1 or
574 the destination register recorded above. Actually, this might
575 well recognize several different arithmetic operations.
576 It doesn't check that rs1 == rd because in theory "sub %g0, 5, %g1"
577 followed by "save %sp, %g1, %sp" is a valid prologue (Not that
578 I imagine any compiler really does that, however). */
581 && (X_RD (insn
) == 1 || X_RD (insn
) == dest
))
584 insn
= fetch_instruction (pc
);
587 /* Recognize any SAVE insn. */
588 if (X_OP (insn
) == 2 && X_OP3 (insn
) == 60)
591 if (frameless_p
) /* If the save is all we care about, */
592 return pc
; /* return before doing more work */
593 insn
= fetch_instruction (pc
);
595 /* Recognize add to %sp. */
596 else if (X_OP (insn
) == 2 && X_RD (insn
) == 14 && X_OP3 (insn
) == 0)
599 if (frameless_p
) /* If the add is all we care about, */
600 return pc
; /* return before doing more work */
602 insn
= fetch_instruction (pc
);
603 /* Recognize store of frame pointer (i7). */
607 && X_RS1 (insn
) == 14)
610 insn
= fetch_instruction (pc
);
612 /* Recognize sub %sp, <anything>, %i7. */
615 && X_RS1 (insn
) == 14
616 && X_RD (insn
) == 31)
619 insn
= fetch_instruction (pc
);
628 /* Without a save or add instruction, it's not a prologue. */
633 /* Recognize stores into the frame from the input registers.
634 This recognizes all non alternate stores of an input register,
635 into a location offset from the frame pointer between
638 /* The above will fail for arguments that are promoted
639 (eg. shorts to ints or floats to doubles), because the compiler
640 will pass them in positive-offset frame space, but the prologue
641 will save them (after conversion) in negative frame space at an
642 unpredictable offset. Therefore I am going to remove the
643 restriction on the target-address of the save, on the theory
644 that any unbroken sequence of saves from input registers must
645 be part of the prologue. In un-optimized code (at least), I'm
646 fairly sure that the compiler would emit SOME other instruction
647 (eg. a move or add) before emitting another save that is actually
648 a part of the function body.
650 Besides, the reserved stack space is different for SPARC64 anyway.
655 && (X_OP3 (insn
) & 0x3c) == 4 /* Store, non-alternate. */
656 && (X_RD (insn
) & 0x18) == 0x18 /* Input register. */
657 && X_I (insn
) /* Immediate mode. */
658 && X_RS1 (insn
) == 30) /* Off of frame pointer. */
659 ; /* empty statement -- fall thru to end of loop */
660 else if (GDB_TARGET_IS_SPARC64
662 && (X_OP3 (insn
) & 0x3c) == 12 /* store, extended (64-bit) */
663 && (X_RD (insn
) & 0x18) == 0x18 /* input register */
664 && X_I (insn
) /* immediate mode */
665 && X_RS1 (insn
) == 30) /* off of frame pointer */
666 ; /* empty statement -- fall thru to end of loop */
667 else if (X_OP (insn
) == 3
668 && (X_OP3 (insn
) & 0x3c) == 36 /* store, floating-point */
669 && X_I (insn
) /* immediate mode */
670 && X_RS1 (insn
) == 30) /* off of frame pointer */
671 ; /* empty statement -- fall thru to end of loop */
674 && X_OP3 (insn
) == 4 /* store? */
675 && X_RS1 (insn
) == 14) /* off of frame pointer */
677 if (saved_regs
&& X_I (insn
))
678 saved_regs
[X_RD (insn
)] =
679 fi
->frame
+ fi
->extra_info
->sp_offset
+ X_SIMM13 (insn
);
684 insn
= fetch_instruction (pc
);
690 /* Advance PC across any function entry prologue instructions to reach
694 sparc_skip_prologue (CORE_ADDR start_pc
)
696 struct symtab_and_line sal
;
697 CORE_ADDR func_start
, func_end
;
699 /* This is the preferred method, find the end of the prologue by
700 using the debugging information. */
701 if (find_pc_partial_function (start_pc
, NULL
, &func_start
, &func_end
))
703 sal
= find_pc_line (func_start
, 0);
705 if (sal
.end
< func_end
706 && start_pc
<= sal
.end
)
710 /* Oh well, examine the code by hand. */
711 return examine_prologue (start_pc
, 0, NULL
, NULL
);
714 /* Is the prologue at IP frameless? */
717 sparc_prologue_frameless_p (CORE_ADDR ip
)
719 return ip
== examine_prologue (ip
, 1, NULL
, NULL
);
722 /* Check instruction at ADDR to see if it is a branch.
723 All non-annulled instructions will go to NPC or will trap.
724 Set *TARGET if we find a candidate branch; set to zero if not.
726 This isn't static as it's used by remote-sa.sparc.c. */
729 isbranch (long instruction
, CORE_ADDR addr
, CORE_ADDR
*target
)
731 branch_type val
= not_branch
;
732 long int offset
= 0; /* Must be signed for sign-extend. */
736 if (X_OP (instruction
) == 0
737 && (X_OP2 (instruction
) == 2
738 || X_OP2 (instruction
) == 6
739 || X_OP2 (instruction
) == 1
740 || X_OP2 (instruction
) == 3
741 || X_OP2 (instruction
) == 5
742 || (GDB_TARGET_IS_SPARC64
&& X_OP2 (instruction
) == 7)))
744 if (X_COND (instruction
) == 8)
745 val
= X_A (instruction
) ? baa
: ba
;
747 val
= X_A (instruction
) ? bicca
: bicc
;
748 switch (X_OP2 (instruction
))
751 if (!GDB_TARGET_IS_SPARC64
)
756 offset
= 4 * X_DISP22 (instruction
);
760 offset
= 4 * X_DISP19 (instruction
);
763 offset
= 4 * X_DISP16 (instruction
);
766 *target
= addr
+ offset
;
768 else if (GDB_TARGET_IS_SPARC64
769 && X_OP (instruction
) == 2
770 && X_OP3 (instruction
) == 62)
772 if (X_FCN (instruction
) == 0)
775 *target
= read_register (TNPC_REGNUM
);
778 else if (X_FCN (instruction
) == 1)
781 *target
= read_register (TPC_REGNUM
);
789 /* Find register number REGNUM relative to FRAME and put its
790 (raw) contents in *RAW_BUFFER. Set *OPTIMIZED if the variable
791 was optimized out (and thus can't be fetched). If the variable
792 was fetched from memory, set *ADDRP to where it was fetched from,
793 otherwise it was fetched from a register.
795 The argument RAW_BUFFER must point to aligned memory. */
798 sparc_get_saved_register (char *raw_buffer
, int *optimized
, CORE_ADDR
*addrp
,
799 struct frame_info
*frame
, int regnum
,
800 enum lval_type
*lval
)
802 struct frame_info
*frame1
;
805 if (!target_has_registers
)
806 error ("No registers.");
813 /* FIXME This code extracted from infcmd.c; should put elsewhere! */
816 /* error ("No selected frame."); */
817 if (!target_has_registers
)
818 error ("The program has no registers now.");
819 if (selected_frame
== NULL
)
820 error ("No selected frame.");
821 /* Try to use selected frame */
822 frame
= get_prev_frame (selected_frame
);
824 error ("Cmd not meaningful in the outermost frame.");
828 frame1
= frame
->next
;
830 /* Get saved PC from the frame info if not in innermost frame. */
831 if (regnum
== PC_REGNUM
&& frame1
!= NULL
)
835 if (raw_buffer
!= NULL
)
837 /* Put it back in target format. */
838 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
), frame
->pc
);
845 while (frame1
!= NULL
)
847 /* FIXME MVS: wrong test for dummy frame at entry. */
849 if (frame1
->pc
>= (frame1
->extra_info
->bottom
?
850 frame1
->extra_info
->bottom
: read_sp ())
851 && frame1
->pc
<= FRAME_FP (frame1
))
853 /* Dummy frame. All but the window regs are in there somewhere.
854 The window registers are saved on the stack, just like in a
856 if (regnum
>= G1_REGNUM
&& regnum
< G1_REGNUM
+ 7)
857 addr
= frame1
->frame
+ (regnum
- G0_REGNUM
) * SPARC_INTREG_SIZE
858 - (FP_REGISTER_BYTES
+ 8 * SPARC_INTREG_SIZE
);
859 else if (regnum
>= I0_REGNUM
&& regnum
< I0_REGNUM
+ 8)
860 /* NOTE: cagney/2002-05-04: The call to get_prev_frame()
861 is safe/cheap - there will always be a prev frame.
862 This is because frame1 is initialized to frame->next
863 (frame1->prev == frame) and is then advanced towards
864 the innermost (next) frame. */
865 addr
= (get_prev_frame (frame1
)->extra_info
->bottom
866 + (regnum
- I0_REGNUM
) * SPARC_INTREG_SIZE
868 else if (regnum
>= L0_REGNUM
&& regnum
< L0_REGNUM
+ 8)
869 /* NOTE: cagney/2002-05-04: The call to get_prev_frame()
870 is safe/cheap - there will always be a prev frame.
871 This is because frame1 is initialized to frame->next
872 (frame1->prev == frame) and is then advanced towards
873 the innermost (next) frame. */
874 addr
= (get_prev_frame (frame1
)->extra_info
->bottom
875 + (regnum
- L0_REGNUM
) * SPARC_INTREG_SIZE
877 else if (regnum
>= O0_REGNUM
&& regnum
< O0_REGNUM
+ 8)
878 addr
= frame1
->frame
+ (regnum
- O0_REGNUM
) * SPARC_INTREG_SIZE
879 - (FP_REGISTER_BYTES
+ 16 * SPARC_INTREG_SIZE
);
880 else if (SPARC_HAS_FPU
&&
881 regnum
>= FP0_REGNUM
&& regnum
< FP0_REGNUM
+ 32)
882 addr
= frame1
->frame
+ (regnum
- FP0_REGNUM
) * 4
883 - (FP_REGISTER_BYTES
);
884 else if (GDB_TARGET_IS_SPARC64
&& SPARC_HAS_FPU
&&
885 regnum
>= FP0_REGNUM
+ 32 && regnum
< FP_MAX_REGNUM
)
886 addr
= frame1
->frame
+ 32 * 4 + (regnum
- FP0_REGNUM
- 32) * 8
887 - (FP_REGISTER_BYTES
);
888 else if (regnum
>= Y_REGNUM
&& regnum
< NUM_REGS
)
889 addr
= frame1
->frame
+ (regnum
- Y_REGNUM
) * SPARC_INTREG_SIZE
890 - (FP_REGISTER_BYTES
+ 24 * SPARC_INTREG_SIZE
);
892 else if (frame1
->extra_info
->flat
)
895 if (regnum
== RP_REGNUM
)
896 addr
= frame1
->extra_info
->pc_addr
;
897 else if (regnum
== I7_REGNUM
)
898 addr
= frame1
->extra_info
->fp_addr
;
901 CORE_ADDR func_start
;
904 regs
= alloca (NUM_REGS
* sizeof (CORE_ADDR
));
905 memset (regs
, 0, NUM_REGS
* sizeof (CORE_ADDR
));
907 find_pc_partial_function (frame1
->pc
, NULL
, &func_start
, NULL
);
908 examine_prologue (func_start
, 0, frame1
, regs
);
914 /* Normal frame. Local and In registers are saved on stack. */
915 if (regnum
>= I0_REGNUM
&& regnum
< I0_REGNUM
+ 8)
916 addr
= (get_prev_frame (frame1
)->extra_info
->bottom
917 + (regnum
- I0_REGNUM
) * SPARC_INTREG_SIZE
919 else if (regnum
>= L0_REGNUM
&& regnum
< L0_REGNUM
+ 8)
920 addr
= (get_prev_frame (frame1
)->extra_info
->bottom
921 + (regnum
- L0_REGNUM
) * SPARC_INTREG_SIZE
923 else if (regnum
>= O0_REGNUM
&& regnum
< O0_REGNUM
+ 8)
925 /* Outs become ins. */
926 get_saved_register (raw_buffer
, optimized
, addrp
, frame1
,
927 (regnum
- O0_REGNUM
+ I0_REGNUM
), lval
);
933 frame1
= frame1
->next
;
939 if (regnum
== SP_REGNUM
)
941 if (raw_buffer
!= NULL
)
943 /* Put it back in target format. */
944 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
), addr
);
950 if (raw_buffer
!= NULL
)
951 read_memory (addr
, raw_buffer
, REGISTER_RAW_SIZE (regnum
));
956 *lval
= lval_register
;
957 addr
= REGISTER_BYTE (regnum
);
958 if (raw_buffer
!= NULL
)
959 read_register_gen (regnum
, raw_buffer
);
965 /* Push an empty stack frame, and record in it the current PC, regs, etc.
967 We save the non-windowed registers and the ins. The locals and outs
968 are new; they don't need to be saved. The i's and l's of
969 the last frame were already saved on the stack. */
971 /* Definitely see tm-sparc.h for more doc of the frame format here. */
973 /* See tm-sparc.h for how this is calculated. */
975 #define DUMMY_STACK_REG_BUF_SIZE \
976 (((8+8+8) * SPARC_INTREG_SIZE) + FP_REGISTER_BYTES)
977 #define DUMMY_STACK_SIZE \
978 (DUMMY_STACK_REG_BUF_SIZE + DUMMY_REG_SAVE_OFFSET)
981 sparc_push_dummy_frame (void)
983 CORE_ADDR sp
, old_sp
;
986 register_temp
= alloca (DUMMY_STACK_SIZE
);
988 old_sp
= sp
= read_sp ();
990 if (GDB_TARGET_IS_SPARC64
)
992 /* PC, NPC, CCR, FSR, FPRS, Y, ASI */
993 read_register_bytes (REGISTER_BYTE (PC_REGNUM
), ®ister_temp
[0],
994 REGISTER_RAW_SIZE (PC_REGNUM
) * 7);
995 read_register_bytes (REGISTER_BYTE (PSTATE_REGNUM
),
996 ®ister_temp
[7 * SPARC_INTREG_SIZE
],
997 REGISTER_RAW_SIZE (PSTATE_REGNUM
));
998 /* FIXME: not sure what needs to be saved here. */
1002 /* Y, PS, WIM, TBR, PC, NPC, FPS, CPS regs */
1003 read_register_bytes (REGISTER_BYTE (Y_REGNUM
), ®ister_temp
[0],
1004 REGISTER_RAW_SIZE (Y_REGNUM
) * 8);
1007 read_register_bytes (REGISTER_BYTE (O0_REGNUM
),
1008 ®ister_temp
[8 * SPARC_INTREG_SIZE
],
1009 SPARC_INTREG_SIZE
* 8);
1011 read_register_bytes (REGISTER_BYTE (G0_REGNUM
),
1012 ®ister_temp
[16 * SPARC_INTREG_SIZE
],
1013 SPARC_INTREG_SIZE
* 8);
1016 read_register_bytes (REGISTER_BYTE (FP0_REGNUM
),
1017 ®ister_temp
[24 * SPARC_INTREG_SIZE
],
1020 sp
-= DUMMY_STACK_SIZE
;
1024 write_memory (sp
+ DUMMY_REG_SAVE_OFFSET
, ®ister_temp
[0],
1025 DUMMY_STACK_REG_BUF_SIZE
);
1027 if (strcmp (target_shortname
, "sim") != 0)
1029 /* NOTE: cagney/2002-04-04: The code below originally contained
1030 GDB's _only_ call to write_fp(). That call was eliminated by
1031 inlining the corresponding code. For the 64 bit case, the
1032 old function (sparc64_write_fp) did the below although I'm
1033 not clear why. The same goes for why this is only done when
1034 the underlying target is a simulator. */
1035 if (GDB_TARGET_IS_SPARC64
)
1037 /* Target is a 64 bit SPARC. */
1038 CORE_ADDR oldfp
= read_register (FP_REGNUM
);
1040 write_register (FP_REGNUM
, old_sp
- 2047);
1042 write_register (FP_REGNUM
, old_sp
);
1046 /* Target is a 32 bit SPARC. */
1047 write_register (FP_REGNUM
, old_sp
);
1049 /* Set return address register for the call dummy to the current PC. */
1050 write_register (I7_REGNUM
, read_pc () - 8);
1054 /* The call dummy will write this value to FP before executing
1055 the 'save'. This ensures that register window flushes work
1056 correctly in the simulator. */
1057 write_register (G0_REGNUM
+ 1, read_register (FP_REGNUM
));
1059 /* The call dummy will write this value to FP after executing
1061 write_register (G0_REGNUM
+ 2, old_sp
);
1063 /* The call dummy will write this value to the return address (%i7) after
1064 executing the 'save'. */
1065 write_register (G0_REGNUM
+ 3, read_pc () - 8);
1067 /* Set the FP that the call dummy will be using after the 'save'.
1068 This makes backtraces from an inferior function call work properly. */
1069 write_register (FP_REGNUM
, old_sp
);
1073 /* sparc_frame_find_saved_regs (). This function is here only because
1074 pop_frame uses it. Note there is an interesting corner case which
1075 I think few ports of GDB get right--if you are popping a frame
1076 which does not save some register that *is* saved by a more inner
1077 frame (such a frame will never be a dummy frame because dummy
1078 frames save all registers). Rewriting pop_frame to use
1079 get_saved_register would solve this problem and also get rid of the
1080 ugly duplication between sparc_frame_find_saved_regs and
1083 Stores, into an array of CORE_ADDR,
1084 the addresses of the saved registers of frame described by FRAME_INFO.
1085 This includes special registers such as pc and fp saved in special
1086 ways in the stack frame. sp is even more special:
1087 the address we return for it IS the sp for the next frame.
1089 Note that on register window machines, we are currently making the
1090 assumption that window registers are being saved somewhere in the
1091 frame in which they are being used. If they are stored in an
1092 inferior frame, find_saved_register will break.
1094 On the Sun 4, the only time all registers are saved is when
1095 a dummy frame is involved. Otherwise, the only saved registers
1096 are the LOCAL and IN registers which are saved as a result
1097 of the "save/restore" opcodes. This condition is determined
1098 by address rather than by value.
1100 The "pc" is not stored in a frame on the SPARC. (What is stored
1101 is a return address minus 8.) sparc_pop_frame knows how to
1102 deal with that. Other routines might or might not.
1104 See tm-sparc.h (PUSH_DUMMY_FRAME and friends) for CRITICAL information
1105 about how this works. */
1107 static void sparc_frame_find_saved_regs (struct frame_info
*, CORE_ADDR
*);
1110 sparc_frame_find_saved_regs (struct frame_info
*fi
, CORE_ADDR
*saved_regs_addr
)
1112 register int regnum
;
1113 CORE_ADDR frame_addr
= FRAME_FP (fi
);
1116 internal_error (__FILE__
, __LINE__
,
1117 "Bad frame info struct in FRAME_FIND_SAVED_REGS");
1119 memset (saved_regs_addr
, 0, NUM_REGS
* sizeof (CORE_ADDR
));
1121 if (fi
->pc
>= (fi
->extra_info
->bottom
?
1122 fi
->extra_info
->bottom
: read_sp ())
1123 && fi
->pc
<= FRAME_FP (fi
))
1125 /* Dummy frame. All but the window regs are in there somewhere. */
1126 for (regnum
= G1_REGNUM
; regnum
< G1_REGNUM
+ 7; regnum
++)
1127 saved_regs_addr
[regnum
] =
1128 frame_addr
+ (regnum
- G0_REGNUM
) * SPARC_INTREG_SIZE
1129 - DUMMY_STACK_REG_BUF_SIZE
+ 16 * SPARC_INTREG_SIZE
;
1131 for (regnum
= I0_REGNUM
; regnum
< I0_REGNUM
+ 8; regnum
++)
1132 saved_regs_addr
[regnum
] =
1133 frame_addr
+ (regnum
- I0_REGNUM
) * SPARC_INTREG_SIZE
1134 - DUMMY_STACK_REG_BUF_SIZE
+ 8 * SPARC_INTREG_SIZE
;
1137 for (regnum
= FP0_REGNUM
; regnum
< FP_MAX_REGNUM
; regnum
++)
1138 saved_regs_addr
[regnum
] = frame_addr
+ (regnum
- FP0_REGNUM
) * 4
1139 - DUMMY_STACK_REG_BUF_SIZE
+ 24 * SPARC_INTREG_SIZE
;
1141 if (GDB_TARGET_IS_SPARC64
)
1143 for (regnum
= PC_REGNUM
; regnum
< PC_REGNUM
+ 7; regnum
++)
1145 saved_regs_addr
[regnum
] =
1146 frame_addr
+ (regnum
- PC_REGNUM
) * SPARC_INTREG_SIZE
1147 - DUMMY_STACK_REG_BUF_SIZE
;
1149 saved_regs_addr
[PSTATE_REGNUM
] =
1150 frame_addr
+ 8 * SPARC_INTREG_SIZE
- DUMMY_STACK_REG_BUF_SIZE
;
1153 for (regnum
= Y_REGNUM
; regnum
< NUM_REGS
; regnum
++)
1154 saved_regs_addr
[regnum
] =
1155 frame_addr
+ (regnum
- Y_REGNUM
) * SPARC_INTREG_SIZE
1156 - DUMMY_STACK_REG_BUF_SIZE
;
1158 frame_addr
= fi
->extra_info
->bottom
?
1159 fi
->extra_info
->bottom
: read_sp ();
1161 else if (fi
->extra_info
->flat
)
1163 CORE_ADDR func_start
;
1164 find_pc_partial_function (fi
->pc
, NULL
, &func_start
, NULL
);
1165 examine_prologue (func_start
, 0, fi
, saved_regs_addr
);
1167 /* Flat register window frame. */
1168 saved_regs_addr
[RP_REGNUM
] = fi
->extra_info
->pc_addr
;
1169 saved_regs_addr
[I7_REGNUM
] = fi
->extra_info
->fp_addr
;
1173 /* Normal frame. Just Local and In registers */
1174 frame_addr
= fi
->extra_info
->bottom
?
1175 fi
->extra_info
->bottom
: read_sp ();
1176 for (regnum
= L0_REGNUM
; regnum
< L0_REGNUM
+ 8; regnum
++)
1177 saved_regs_addr
[regnum
] =
1178 (frame_addr
+ (regnum
- L0_REGNUM
) * SPARC_INTREG_SIZE
1180 for (regnum
= I0_REGNUM
; regnum
< I0_REGNUM
+ 8; regnum
++)
1181 saved_regs_addr
[regnum
] =
1182 (frame_addr
+ (regnum
- I0_REGNUM
) * SPARC_INTREG_SIZE
1187 if (fi
->extra_info
->flat
)
1189 saved_regs_addr
[O7_REGNUM
] = fi
->extra_info
->pc_addr
;
1193 /* Pull off either the next frame pointer or the stack pointer */
1194 CORE_ADDR next_next_frame_addr
=
1195 (fi
->next
->extra_info
->bottom
?
1196 fi
->next
->extra_info
->bottom
: read_sp ());
1197 for (regnum
= O0_REGNUM
; regnum
< O0_REGNUM
+ 8; regnum
++)
1198 saved_regs_addr
[regnum
] =
1199 (next_next_frame_addr
1200 + (regnum
- O0_REGNUM
) * SPARC_INTREG_SIZE
1204 /* Otherwise, whatever we would get from ptrace(GETREGS) is accurate */
1205 /* FIXME -- should this adjust for the sparc64 offset? */
1206 saved_regs_addr
[SP_REGNUM
] = FRAME_FP (fi
);
1209 /* Discard from the stack the innermost frame, restoring all saved registers.
1211 Note that the values stored in fsr by get_frame_saved_regs are *in
1212 the context of the called frame*. What this means is that the i
1213 regs of fsr must be restored into the o regs of the (calling) frame that
1214 we pop into. We don't care about the output regs of the calling frame,
1215 since unless it's a dummy frame, it won't have any output regs in it.
1217 We never have to bother with %l (local) regs, since the called routine's
1218 locals get tossed, and the calling routine's locals are already saved
1221 /* Definitely see tm-sparc.h for more doc of the frame format here. */
1224 sparc_pop_frame (void)
1226 register struct frame_info
*frame
= get_current_frame ();
1227 register CORE_ADDR pc
;
1232 fsr
= alloca (NUM_REGS
* sizeof (CORE_ADDR
));
1233 raw_buffer
= alloca (REGISTER_BYTES
);
1234 sparc_frame_find_saved_regs (frame
, &fsr
[0]);
1237 if (fsr
[FP0_REGNUM
])
1239 read_memory (fsr
[FP0_REGNUM
], raw_buffer
, FP_REGISTER_BYTES
);
1240 write_register_bytes (REGISTER_BYTE (FP0_REGNUM
),
1241 raw_buffer
, FP_REGISTER_BYTES
);
1243 if (!(GDB_TARGET_IS_SPARC64
))
1245 if (fsr
[FPS_REGNUM
])
1247 read_memory (fsr
[FPS_REGNUM
], raw_buffer
, SPARC_INTREG_SIZE
);
1248 write_register_gen (FPS_REGNUM
, raw_buffer
);
1250 if (fsr
[CPS_REGNUM
])
1252 read_memory (fsr
[CPS_REGNUM
], raw_buffer
, SPARC_INTREG_SIZE
);
1253 write_register_gen (CPS_REGNUM
, raw_buffer
);
1259 read_memory (fsr
[G1_REGNUM
], raw_buffer
, 7 * SPARC_INTREG_SIZE
);
1260 write_register_bytes (REGISTER_BYTE (G1_REGNUM
), raw_buffer
,
1261 7 * SPARC_INTREG_SIZE
);
1264 if (frame
->extra_info
->flat
)
1266 /* Each register might or might not have been saved, need to test
1268 for (regnum
= L0_REGNUM
; regnum
< L0_REGNUM
+ 8; ++regnum
)
1270 write_register (regnum
, read_memory_integer (fsr
[regnum
],
1271 SPARC_INTREG_SIZE
));
1272 for (regnum
= I0_REGNUM
; regnum
< I0_REGNUM
+ 8; ++regnum
)
1274 write_register (regnum
, read_memory_integer (fsr
[regnum
],
1275 SPARC_INTREG_SIZE
));
1277 /* Handle all outs except stack pointer (o0-o5; o7). */
1278 for (regnum
= O0_REGNUM
; regnum
< O0_REGNUM
+ 6; ++regnum
)
1280 write_register (regnum
, read_memory_integer (fsr
[regnum
],
1281 SPARC_INTREG_SIZE
));
1282 if (fsr
[O0_REGNUM
+ 7])
1283 write_register (O0_REGNUM
+ 7,
1284 read_memory_integer (fsr
[O0_REGNUM
+ 7],
1285 SPARC_INTREG_SIZE
));
1287 write_sp (frame
->frame
);
1289 else if (fsr
[I0_REGNUM
])
1295 reg_temp
= alloca (SPARC_INTREG_SIZE
* 16);
1297 read_memory (fsr
[I0_REGNUM
], raw_buffer
, 8 * SPARC_INTREG_SIZE
);
1299 /* Get the ins and locals which we are about to restore. Just
1300 moving the stack pointer is all that is really needed, except
1301 store_inferior_registers is then going to write the ins and
1302 locals from the registers array, so we need to muck with the
1304 sp
= fsr
[SP_REGNUM
];
1306 if (GDB_TARGET_IS_SPARC64
&& (sp
& 1))
1309 read_memory (sp
, reg_temp
, SPARC_INTREG_SIZE
* 16);
1311 /* Restore the out registers.
1312 Among other things this writes the new stack pointer. */
1313 write_register_bytes (REGISTER_BYTE (O0_REGNUM
), raw_buffer
,
1314 SPARC_INTREG_SIZE
* 8);
1316 write_register_bytes (REGISTER_BYTE (L0_REGNUM
), reg_temp
,
1317 SPARC_INTREG_SIZE
* 16);
1320 if (!(GDB_TARGET_IS_SPARC64
))
1322 write_register (PS_REGNUM
,
1323 read_memory_integer (fsr
[PS_REGNUM
],
1324 REGISTER_RAW_SIZE (PS_REGNUM
)));
1327 write_register (Y_REGNUM
,
1328 read_memory_integer (fsr
[Y_REGNUM
],
1329 REGISTER_RAW_SIZE (Y_REGNUM
)));
1332 /* Explicitly specified PC (and maybe NPC) -- just restore them. */
1333 write_register (PC_REGNUM
,
1334 read_memory_integer (fsr
[PC_REGNUM
],
1335 REGISTER_RAW_SIZE (PC_REGNUM
)));
1336 if (fsr
[NPC_REGNUM
])
1337 write_register (NPC_REGNUM
,
1338 read_memory_integer (fsr
[NPC_REGNUM
],
1339 REGISTER_RAW_SIZE (NPC_REGNUM
)));
1341 else if (frame
->extra_info
->flat
)
1343 if (frame
->extra_info
->pc_addr
)
1344 pc
= PC_ADJUST ((CORE_ADDR
)
1345 read_memory_integer (frame
->extra_info
->pc_addr
,
1346 REGISTER_RAW_SIZE (PC_REGNUM
)));
1349 /* I think this happens only in the innermost frame, if so then
1350 it is a complicated way of saying
1351 "pc = read_register (O7_REGNUM);". */
1354 buf
= alloca (MAX_REGISTER_RAW_SIZE
);
1355 get_saved_register (buf
, 0, 0, frame
, O7_REGNUM
, 0);
1356 pc
= PC_ADJUST (extract_address
1357 (buf
, REGISTER_RAW_SIZE (O7_REGNUM
)));
1360 write_register (PC_REGNUM
, pc
);
1361 write_register (NPC_REGNUM
, pc
+ 4);
1363 else if (fsr
[I7_REGNUM
])
1365 /* Return address in %i7 -- adjust it, then restore PC and NPC from it */
1366 pc
= PC_ADJUST ((CORE_ADDR
) read_memory_integer (fsr
[I7_REGNUM
],
1367 SPARC_INTREG_SIZE
));
1368 write_register (PC_REGNUM
, pc
);
1369 write_register (NPC_REGNUM
, pc
+ 4);
1371 flush_cached_frames ();
1374 /* On the Sun 4 under SunOS, the compile will leave a fake insn which
1375 encodes the structure size being returned. If we detect such
1376 a fake insn, step past it. */
1379 sparc_pc_adjust (CORE_ADDR pc
)
1385 err
= target_read_memory (pc
+ 8, buf
, 4);
1386 insn
= extract_unsigned_integer (buf
, 4);
1387 if ((err
== 0) && (insn
& 0xffc00000) == 0)
1393 /* If pc is in a shared library trampoline, return its target.
1394 The SunOs 4.x linker rewrites the jump table entries for PIC
1395 compiled modules in the main executable to bypass the dynamic linker
1396 with jumps of the form
1399 and removes the corresponding jump table relocation entry in the
1400 dynamic relocations.
1401 find_solib_trampoline_target relies on the presence of the jump
1402 table relocation entry, so we have to detect these jump instructions
1406 sunos4_skip_trampoline_code (CORE_ADDR pc
)
1408 unsigned long insn1
;
1412 err
= target_read_memory (pc
, buf
, 4);
1413 insn1
= extract_unsigned_integer (buf
, 4);
1414 if (err
== 0 && (insn1
& 0xffc00000) == 0x03000000)
1416 unsigned long insn2
;
1418 err
= target_read_memory (pc
+ 4, buf
, 4);
1419 insn2
= extract_unsigned_integer (buf
, 4);
1420 if (err
== 0 && (insn2
& 0xffffe000) == 0x81c06000)
1422 CORE_ADDR target_pc
= (insn1
& 0x3fffff) << 10;
1423 int delta
= insn2
& 0x1fff;
1425 /* Sign extend the displacement. */
1428 return target_pc
+ delta
;
1431 return find_solib_trampoline_target (pc
);
1434 #ifdef USE_PROC_FS /* Target dependent support for /proc */
1436 /* The /proc interface divides the target machine's register set up into
1437 two different sets, the general register set (gregset) and the floating
1438 point register set (fpregset). For each set, there is an ioctl to get
1439 the current register set and another ioctl to set the current values.
1441 The actual structure passed through the ioctl interface is, of course,
1442 naturally machine dependent, and is different for each set of registers.
1443 For the sparc for example, the general register set is typically defined
1446 typedef int gregset_t[38];
1452 and the floating point set by:
1454 typedef struct prfpregset {
1457 double pr_dregs[16];
1462 u_char pr_q_entrysize;
1467 These routines provide the packing and unpacking of gregset_t and
1468 fpregset_t formatted data.
1473 /* Given a pointer to a general register set in /proc format (gregset_t *),
1474 unpack the register contents and supply them as gdb's idea of the current
1478 supply_gregset (gdb_gregset_t
*gregsetp
)
1480 prgreg_t
*regp
= (prgreg_t
*) gregsetp
;
1481 int regi
, offset
= 0;
1483 /* If the host is 64-bit sparc, but the target is 32-bit sparc,
1484 then the gregset may contain 64-bit ints while supply_register
1485 is expecting 32-bit ints. Compensate. */
1486 if (sizeof (regp
[0]) == 8 && SPARC_INTREG_SIZE
== 4)
1489 /* GDB register numbers for Gn, On, Ln, In all match /proc reg numbers. */
1490 /* FIXME MVS: assumes the order of the first 32 elements... */
1491 for (regi
= G0_REGNUM
; regi
<= I7_REGNUM
; regi
++)
1493 supply_register (regi
, ((char *) (regp
+ regi
)) + offset
);
1496 /* These require a bit more care. */
1497 supply_register (PC_REGNUM
, ((char *) (regp
+ R_PC
)) + offset
);
1498 supply_register (NPC_REGNUM
, ((char *) (regp
+ R_nPC
)) + offset
);
1499 supply_register (Y_REGNUM
, ((char *) (regp
+ R_Y
)) + offset
);
1501 if (GDB_TARGET_IS_SPARC64
)
1504 supply_register (CCR_REGNUM
, ((char *) (regp
+ R_CCR
)) + offset
);
1506 supply_register (CCR_REGNUM
, NULL
);
1509 supply_register (FPRS_REGNUM
, ((char *) (regp
+ R_FPRS
)) + offset
);
1511 supply_register (FPRS_REGNUM
, NULL
);
1514 supply_register (ASI_REGNUM
, ((char *) (regp
+ R_ASI
)) + offset
);
1516 supply_register (ASI_REGNUM
, NULL
);
1522 supply_register (PS_REGNUM
, ((char *) (regp
+ R_PS
)) + offset
);
1524 supply_register (PS_REGNUM
, NULL
);
1527 /* For 64-bit hosts, R_WIM and R_TBR may not be defined.
1528 Steal R_ASI and R_FPRS, and hope for the best! */
1530 #if !defined (R_WIM) && defined (R_ASI)
1534 #if !defined (R_TBR) && defined (R_FPRS)
1535 #define R_TBR R_FPRS
1539 supply_register (WIM_REGNUM
, ((char *) (regp
+ R_WIM
)) + offset
);
1541 supply_register (WIM_REGNUM
, NULL
);
1545 supply_register (TBR_REGNUM
, ((char *) (regp
+ R_TBR
)) + offset
);
1547 supply_register (TBR_REGNUM
, NULL
);
1551 /* Fill inaccessible registers with zero. */
1552 if (GDB_TARGET_IS_SPARC64
)
1555 * don't know how to get value of any of the following:
1557 supply_register (VER_REGNUM
, NULL
);
1558 supply_register (TICK_REGNUM
, NULL
);
1559 supply_register (PIL_REGNUM
, NULL
);
1560 supply_register (PSTATE_REGNUM
, NULL
);
1561 supply_register (TSTATE_REGNUM
, NULL
);
1562 supply_register (TBA_REGNUM
, NULL
);
1563 supply_register (TL_REGNUM
, NULL
);
1564 supply_register (TT_REGNUM
, NULL
);
1565 supply_register (TPC_REGNUM
, NULL
);
1566 supply_register (TNPC_REGNUM
, NULL
);
1567 supply_register (WSTATE_REGNUM
, NULL
);
1568 supply_register (CWP_REGNUM
, NULL
);
1569 supply_register (CANSAVE_REGNUM
, NULL
);
1570 supply_register (CANRESTORE_REGNUM
, NULL
);
1571 supply_register (CLEANWIN_REGNUM
, NULL
);
1572 supply_register (OTHERWIN_REGNUM
, NULL
);
1573 supply_register (ASR16_REGNUM
, NULL
);
1574 supply_register (ASR17_REGNUM
, NULL
);
1575 supply_register (ASR18_REGNUM
, NULL
);
1576 supply_register (ASR19_REGNUM
, NULL
);
1577 supply_register (ASR20_REGNUM
, NULL
);
1578 supply_register (ASR21_REGNUM
, NULL
);
1579 supply_register (ASR22_REGNUM
, NULL
);
1580 supply_register (ASR23_REGNUM
, NULL
);
1581 supply_register (ASR24_REGNUM
, NULL
);
1582 supply_register (ASR25_REGNUM
, NULL
);
1583 supply_register (ASR26_REGNUM
, NULL
);
1584 supply_register (ASR27_REGNUM
, NULL
);
1585 supply_register (ASR28_REGNUM
, NULL
);
1586 supply_register (ASR29_REGNUM
, NULL
);
1587 supply_register (ASR30_REGNUM
, NULL
);
1588 supply_register (ASR31_REGNUM
, NULL
);
1589 supply_register (ICC_REGNUM
, NULL
);
1590 supply_register (XCC_REGNUM
, NULL
);
1594 supply_register (CPS_REGNUM
, NULL
);
1599 fill_gregset (gdb_gregset_t
*gregsetp
, int regno
)
1601 prgreg_t
*regp
= (prgreg_t
*) gregsetp
;
1602 int regi
, offset
= 0;
1604 /* If the host is 64-bit sparc, but the target is 32-bit sparc,
1605 then the gregset may contain 64-bit ints while supply_register
1606 is expecting 32-bit ints. Compensate. */
1607 if (sizeof (regp
[0]) == 8 && SPARC_INTREG_SIZE
== 4)
1610 for (regi
= 0; regi
<= R_I7
; regi
++)
1611 if ((regno
== -1) || (regno
== regi
))
1612 read_register_gen (regi
, (char *) (regp
+ regi
) + offset
);
1614 if ((regno
== -1) || (regno
== PC_REGNUM
))
1615 read_register_gen (PC_REGNUM
, (char *) (regp
+ R_PC
) + offset
);
1617 if ((regno
== -1) || (regno
== NPC_REGNUM
))
1618 read_register_gen (NPC_REGNUM
, (char *) (regp
+ R_nPC
) + offset
);
1620 if ((regno
== -1) || (regno
== Y_REGNUM
))
1621 read_register_gen (Y_REGNUM
, (char *) (regp
+ R_Y
) + offset
);
1623 if (GDB_TARGET_IS_SPARC64
)
1626 if (regno
== -1 || regno
== CCR_REGNUM
)
1627 read_register_gen (CCR_REGNUM
, ((char *) (regp
+ R_CCR
)) + offset
);
1630 if (regno
== -1 || regno
== FPRS_REGNUM
)
1631 read_register_gen (FPRS_REGNUM
, ((char *) (regp
+ R_FPRS
)) + offset
);
1634 if (regno
== -1 || regno
== ASI_REGNUM
)
1635 read_register_gen (ASI_REGNUM
, ((char *) (regp
+ R_ASI
)) + offset
);
1641 if (regno
== -1 || regno
== PS_REGNUM
)
1642 read_register_gen (PS_REGNUM
, ((char *) (regp
+ R_PS
)) + offset
);
1645 /* For 64-bit hosts, R_WIM and R_TBR may not be defined.
1646 Steal R_ASI and R_FPRS, and hope for the best! */
1648 #if !defined (R_WIM) && defined (R_ASI)
1652 #if !defined (R_TBR) && defined (R_FPRS)
1653 #define R_TBR R_FPRS
1657 if (regno
== -1 || regno
== WIM_REGNUM
)
1658 read_register_gen (WIM_REGNUM
, ((char *) (regp
+ R_WIM
)) + offset
);
1660 if (regno
== -1 || regno
== WIM_REGNUM
)
1661 read_register_gen (WIM_REGNUM
, NULL
);
1665 if (regno
== -1 || regno
== TBR_REGNUM
)
1666 read_register_gen (TBR_REGNUM
, ((char *) (regp
+ R_TBR
)) + offset
);
1668 if (regno
== -1 || regno
== TBR_REGNUM
)
1669 read_register_gen (TBR_REGNUM
, NULL
);
1674 /* Given a pointer to a floating point register set in /proc format
1675 (fpregset_t *), unpack the register contents and supply them as gdb's
1676 idea of the current floating point register values. */
1679 supply_fpregset (gdb_fpregset_t
*fpregsetp
)
1687 for (regi
= FP0_REGNUM
; regi
< FP_MAX_REGNUM
; regi
++)
1689 from
= (char *) &fpregsetp
->pr_fr
.pr_regs
[regi
- FP0_REGNUM
];
1690 supply_register (regi
, from
);
1693 if (GDB_TARGET_IS_SPARC64
)
1696 * don't know how to get value of the following.
1698 supply_register (FSR_REGNUM
, NULL
); /* zero it out for now */
1699 supply_register (FCC0_REGNUM
, NULL
);
1700 supply_register (FCC1_REGNUM
, NULL
); /* don't know how to get value */
1701 supply_register (FCC2_REGNUM
, NULL
); /* don't know how to get value */
1702 supply_register (FCC3_REGNUM
, NULL
); /* don't know how to get value */
1706 supply_register (FPS_REGNUM
, (char *) &(fpregsetp
->pr_fsr
));
1710 /* Given a pointer to a floating point register set in /proc format
1711 (fpregset_t *), update the register specified by REGNO from gdb's idea
1712 of the current floating point register set. If REGNO is -1, update
1714 /* This will probably need some changes for sparc64. */
1717 fill_fpregset (gdb_fpregset_t
*fpregsetp
, int regno
)
1726 for (regi
= FP0_REGNUM
; regi
< FP_MAX_REGNUM
; regi
++)
1728 if ((regno
== -1) || (regno
== regi
))
1730 from
= (char *) ®isters
[REGISTER_BYTE (regi
)];
1731 to
= (char *) &fpregsetp
->pr_fr
.pr_regs
[regi
- FP0_REGNUM
];
1732 memcpy (to
, from
, REGISTER_RAW_SIZE (regi
));
1736 if (!(GDB_TARGET_IS_SPARC64
)) /* FIXME: does Sparc64 have this register? */
1737 if ((regno
== -1) || (regno
== FPS_REGNUM
))
1739 from
= (char *)®isters
[REGISTER_BYTE (FPS_REGNUM
)];
1740 to
= (char *) &fpregsetp
->pr_fsr
;
1741 memcpy (to
, from
, REGISTER_RAW_SIZE (FPS_REGNUM
));
1745 #endif /* USE_PROC_FS */
1747 /* Because of Multi-arch, GET_LONGJMP_TARGET is always defined. So test
1748 for a definition of JB_PC. */
1751 /* Figure out where the longjmp will land. We expect that we have just entered
1752 longjmp and haven't yet setup the stack frame, so the args are still in the
1753 output regs. %o0 (O0_REGNUM) points at the jmp_buf structure from which we
1754 extract the pc (JB_PC) that we will land at. The pc is copied into ADDR.
1755 This routine returns true on success */
1758 get_longjmp_target (CORE_ADDR
*pc
)
1761 #define LONGJMP_TARGET_SIZE 4
1762 char buf
[LONGJMP_TARGET_SIZE
];
1764 jb_addr
= read_register (O0_REGNUM
);
1766 if (target_read_memory (jb_addr
+ JB_PC
* JB_ELEMENT_SIZE
, buf
,
1767 LONGJMP_TARGET_SIZE
))
1770 *pc
= extract_address (buf
, LONGJMP_TARGET_SIZE
);
1774 #endif /* GET_LONGJMP_TARGET */
1776 #ifdef STATIC_TRANSFORM_NAME
1777 /* SunPRO (3.0 at least), encodes the static variables. This is not
1778 related to C++ mangling, it is done for C too. */
1781 sunpro_static_transform_name (char *name
)
1786 /* For file-local statics there will be a dollar sign, a bunch
1787 of junk (the contents of which match a string given in the
1788 N_OPT), a period and the name. For function-local statics
1789 there will be a bunch of junk (which seems to change the
1790 second character from 'A' to 'B'), a period, the name of the
1791 function, and the name. So just skip everything before the
1793 p
= strrchr (name
, '.');
1799 #endif /* STATIC_TRANSFORM_NAME */
1802 /* Utilities for printing registers.
1803 Page numbers refer to the SPARC Architecture Manual. */
1805 static void dump_ccreg (char *, int);
1808 dump_ccreg (char *reg
, int val
)
1811 printf_unfiltered ("%s:%s,%s,%s,%s", reg
,
1812 val
& 8 ? "N" : "NN",
1813 val
& 4 ? "Z" : "NZ",
1814 val
& 2 ? "O" : "NO",
1815 val
& 1 ? "C" : "NC");
1819 decode_asi (int val
)
1825 return "ASI_NUCLEUS";
1827 return "ASI_NUCLEUS_LITTLE";
1829 return "ASI_AS_IF_USER_PRIMARY";
1831 return "ASI_AS_IF_USER_SECONDARY";
1833 return "ASI_AS_IF_USER_PRIMARY_LITTLE";
1835 return "ASI_AS_IF_USER_SECONDARY_LITTLE";
1837 return "ASI_PRIMARY";
1839 return "ASI_SECONDARY";
1841 return "ASI_PRIMARY_NOFAULT";
1843 return "ASI_SECONDARY_NOFAULT";
1845 return "ASI_PRIMARY_LITTLE";
1847 return "ASI_SECONDARY_LITTLE";
1849 return "ASI_PRIMARY_NOFAULT_LITTLE";
1851 return "ASI_SECONDARY_NOFAULT_LITTLE";
1857 /* PRINT_REGISTER_HOOK routine.
1858 Pretty print various registers. */
1859 /* FIXME: Would be nice if this did some fancy things for 32 bit sparc. */
1862 sparc_print_register_hook (int regno
)
1866 /* Handle double/quad versions of lower 32 fp regs. */
1867 if (regno
>= FP0_REGNUM
&& regno
< FP0_REGNUM
+ 32
1868 && (regno
& 1) == 0)
1872 if (frame_register_read (selected_frame
, regno
, value
)
1873 && frame_register_read (selected_frame
, regno
+ 1, value
+ 4))
1875 printf_unfiltered ("\t");
1876 print_floating (value
, builtin_type_double
, gdb_stdout
);
1878 #if 0 /* FIXME: gdb doesn't handle long doubles */
1879 if ((regno
& 3) == 0)
1881 if (frame_register_read (selected_frame
, regno
+ 2, value
+ 8)
1882 && frame_register_read (selected_frame
, regno
+ 3, value
+ 12))
1884 printf_unfiltered ("\t");
1885 print_floating (value
, builtin_type_long_double
, gdb_stdout
);
1892 #if 0 /* FIXME: gdb doesn't handle long doubles */
1893 /* Print upper fp regs as long double if appropriate. */
1894 if (regno
>= FP0_REGNUM
+ 32 && regno
< FP_MAX_REGNUM
1895 /* We test for even numbered regs and not a multiple of 4 because
1896 the upper fp regs are recorded as doubles. */
1897 && (regno
& 1) == 0)
1901 if (frame_register_read (selected_frame
, regno
, value
)
1902 && frame_register_read (selected_frame
, regno
+ 1, value
+ 8))
1904 printf_unfiltered ("\t");
1905 print_floating (value
, builtin_type_long_double
, gdb_stdout
);
1911 /* FIXME: Some of these are priviledged registers.
1912 Not sure how they should be handled. */
1914 #define BITS(n, mask) ((int) (((val) >> (n)) & (mask)))
1916 val
= read_register (regno
);
1919 if (GDB_TARGET_IS_SPARC64
)
1923 printf_unfiltered ("\t");
1924 dump_ccreg ("xcc", val
>> 4);
1925 printf_unfiltered (", ");
1926 dump_ccreg ("icc", val
& 15);
1929 printf ("\tfef:%d, du:%d, dl:%d",
1930 BITS (2, 1), BITS (1, 1), BITS (0, 1));
1934 static char *fcc
[4] =
1935 {"=", "<", ">", "?"};
1936 static char *rd
[4] =
1937 {"N", "0", "+", "-"};
1938 /* Long, but I'd rather leave it as is and use a wide screen. */
1939 printf_filtered ("\t0:%s, 1:%s, 2:%s, 3:%s, rd:%s, tem:%d, ",
1940 fcc
[BITS (10, 3)], fcc
[BITS (32, 3)],
1941 fcc
[BITS (34, 3)], fcc
[BITS (36, 3)],
1942 rd
[BITS (30, 3)], BITS (23, 31));
1943 printf_filtered ("ns:%d, ver:%d, ftt:%d, qne:%d, aexc:%d, cexc:%d",
1944 BITS (22, 1), BITS (17, 7), BITS (14, 7),
1945 BITS (13, 1), BITS (5, 31), BITS (0, 31));
1950 char *asi
= decode_asi (val
);
1952 printf ("\t%s", asi
);
1956 printf ("\tmanuf:%d, impl:%d, mask:%d, maxtl:%d, maxwin:%d",
1957 BITS (48, 0xffff), BITS (32, 0xffff),
1958 BITS (24, 0xff), BITS (8, 0xff), BITS (0, 31));
1962 static char *mm
[4] =
1963 {"tso", "pso", "rso", "?"};
1964 printf_filtered ("\tcle:%d, tle:%d, mm:%s, red:%d, ",
1965 BITS (9, 1), BITS (8, 1),
1966 mm
[BITS (6, 3)], BITS (5, 1));
1967 printf_filtered ("pef:%d, am:%d, priv:%d, ie:%d, ag:%d",
1968 BITS (4, 1), BITS (3, 1), BITS (2, 1),
1969 BITS (1, 1), BITS (0, 1));
1973 /* FIXME: print all 4? */
1976 /* FIXME: print all 4? */
1979 /* FIXME: print all 4? */
1982 /* FIXME: print all 4? */
1985 printf ("\tother:%d, normal:%d", BITS (3, 7), BITS (0, 7));
1988 printf ("\t%d", BITS (0, 31));
1990 case CANSAVE_REGNUM
:
1991 printf ("\t%-2d before spill", BITS (0, 31));
1993 case CANRESTORE_REGNUM
:
1994 printf ("\t%-2d before fill", BITS (0, 31));
1996 case CLEANWIN_REGNUM
:
1997 printf ("\t%-2d before clean", BITS (0, 31));
1999 case OTHERWIN_REGNUM
:
2000 printf ("\t%d", BITS (0, 31));
2007 printf ("\ticc:%c%c%c%c, pil:%d, s:%d, ps:%d, et:%d, cwp:%d",
2008 BITS (23, 1) ? 'N' : '-', BITS (22, 1) ? 'Z' : '-',
2009 BITS (21, 1) ? 'V' : '-', BITS (20, 1) ? 'C' : '-',
2010 BITS (8, 15), BITS (7, 1), BITS (6, 1), BITS (5, 1),
2015 static char *fcc
[4] =
2016 {"=", "<", ">", "?"};
2017 static char *rd
[4] =
2018 {"N", "0", "+", "-"};
2019 /* Long, but I'd rather leave it as is and use a wide screen. */
2020 printf ("\trd:%s, tem:%d, ns:%d, ver:%d, ftt:%d, qne:%d, "
2021 "fcc:%s, aexc:%d, cexc:%d",
2022 rd
[BITS (30, 3)], BITS (23, 31), BITS (22, 1), BITS (17, 7),
2023 BITS (14, 7), BITS (13, 1), fcc
[BITS (10, 3)], BITS (5, 31),
2033 gdb_print_insn_sparc (bfd_vma memaddr
, disassemble_info
*info
)
2035 /* It's necessary to override mach again because print_insn messes it up. */
2036 info
->mach
= TARGET_ARCHITECTURE
->mach
;
2037 return print_insn_sparc (memaddr
, info
);
2040 /* The SPARC passes the arguments on the stack; arguments smaller
2041 than an int are promoted to an int. The first 6 words worth of
2042 args are also passed in registers o0 - o5. */
2045 sparc32_push_arguments (int nargs
, struct value
**args
, CORE_ADDR sp
,
2046 int struct_return
, CORE_ADDR struct_addr
)
2049 int accumulate_size
= 0;
2056 struct sparc_arg
*sparc_args
=
2057 (struct sparc_arg
*) alloca (nargs
* sizeof (struct sparc_arg
));
2058 struct sparc_arg
*m_arg
;
2060 /* Promote arguments if necessary, and calculate their stack offsets
2062 for (i
= 0, m_arg
= sparc_args
; i
< nargs
; i
++, m_arg
++)
2064 struct value
*arg
= args
[i
];
2065 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2066 /* Cast argument to long if necessary as the compiler does it too. */
2067 switch (TYPE_CODE (arg_type
))
2070 case TYPE_CODE_BOOL
:
2071 case TYPE_CODE_CHAR
:
2072 case TYPE_CODE_RANGE
:
2073 case TYPE_CODE_ENUM
:
2074 if (TYPE_LENGTH (arg_type
) < TYPE_LENGTH (builtin_type_long
))
2076 arg_type
= builtin_type_long
;
2077 arg
= value_cast (arg_type
, arg
);
2083 m_arg
->len
= TYPE_LENGTH (arg_type
);
2084 m_arg
->offset
= accumulate_size
;
2085 accumulate_size
= (accumulate_size
+ m_arg
->len
+ 3) & ~3;
2086 m_arg
->contents
= VALUE_CONTENTS (arg
);
2089 /* Make room for the arguments on the stack. */
2090 accumulate_size
+= CALL_DUMMY_STACK_ADJUST
;
2091 sp
= ((sp
- accumulate_size
) & ~7) + CALL_DUMMY_STACK_ADJUST
;
2093 /* `Push' arguments on the stack. */
2094 for (i
= 0, oregnum
= 0, m_arg
= sparc_args
;
2098 write_memory (sp
+ m_arg
->offset
, m_arg
->contents
, m_arg
->len
);
2100 j
< m_arg
->len
&& oregnum
< 6;
2101 j
+= SPARC_INTREG_SIZE
, oregnum
++)
2102 write_register_gen (O0_REGNUM
+ oregnum
, m_arg
->contents
+ j
);
2109 /* Extract from an array REGBUF containing the (raw) register state
2110 a function return value of type TYPE, and copy that, in virtual format,
2114 sparc32_extract_return_value (struct type
*type
, char *regbuf
, char *valbuf
)
2116 int typelen
= TYPE_LENGTH (type
);
2117 int regsize
= REGISTER_RAW_SIZE (O0_REGNUM
);
2119 if (TYPE_CODE (type
) == TYPE_CODE_FLT
&& SPARC_HAS_FPU
)
2120 memcpy (valbuf
, ®buf
[REGISTER_BYTE (FP0_REGNUM
)], typelen
);
2123 ®buf
[O0_REGNUM
* regsize
+
2125 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
? 0
2126 : regsize
- typelen
)],
2131 /* Write into appropriate registers a function return value
2132 of type TYPE, given in virtual format. On SPARCs with FPUs,
2133 float values are returned in %f0 (and %f1). In all other cases,
2134 values are returned in register %o0. */
2137 sparc_store_return_value (struct type
*type
, char *valbuf
)
2142 buffer
= alloca (MAX_REGISTER_RAW_SIZE
);
2144 if (TYPE_CODE (type
) == TYPE_CODE_FLT
&& SPARC_HAS_FPU
)
2145 /* Floating-point values are returned in the register pair */
2146 /* formed by %f0 and %f1 (doubles are, anyway). */
2149 /* Other values are returned in register %o0. */
2152 /* Add leading zeros to the value. */
2153 if (TYPE_LENGTH (type
) < REGISTER_RAW_SIZE (regno
))
2155 memset (buffer
, 0, REGISTER_RAW_SIZE (regno
));
2156 memcpy (buffer
+ REGISTER_RAW_SIZE (regno
) - TYPE_LENGTH (type
), valbuf
,
2157 TYPE_LENGTH (type
));
2158 write_register_gen (regno
, buffer
);
2161 write_register_bytes (REGISTER_BYTE (regno
), valbuf
, TYPE_LENGTH (type
));
2165 sparclet_store_return_value (struct type
*type
, char *valbuf
)
2167 /* Other values are returned in register %o0. */
2168 write_register_bytes (REGISTER_BYTE (O0_REGNUM
), valbuf
,
2169 TYPE_LENGTH (type
));
2173 #ifndef CALL_DUMMY_CALL_OFFSET
2174 #define CALL_DUMMY_CALL_OFFSET \
2175 (gdbarch_tdep (current_gdbarch)->call_dummy_call_offset)
2176 #endif /* CALL_DUMMY_CALL_OFFSET */
2178 /* Insert the function address into a call dummy instruction sequence
2181 For structs and unions, if the function was compiled with Sun cc,
2182 it expects 'unimp' after the call. But gcc doesn't use that
2183 (twisted) convention. So leave a nop there for gcc (FIX_CALL_DUMMY
2184 can assume it is operating on a pristine CALL_DUMMY, not one that
2185 has already been customized for a different function). */
2188 sparc_fix_call_dummy (char *dummy
, CORE_ADDR pc
, CORE_ADDR fun
,
2189 struct type
*value_type
, int using_gcc
)
2193 /* Store the relative adddress of the target function into the
2194 'call' instruction. */
2195 store_unsigned_integer (dummy
+ CALL_DUMMY_CALL_OFFSET
, 4,
2197 | (((fun
- (pc
+ CALL_DUMMY_CALL_OFFSET
)) >> 2)
2200 /* If the called function returns an aggregate value, fill in the UNIMP
2201 instruction containing the size of the returned aggregate return value,
2202 which follows the call instruction.
2203 For details see the SPARC Architecture Manual Version 8, Appendix D.3.
2205 Adjust the call_dummy_breakpoint_offset for the bp_call_dummy breakpoint
2206 to the proper address in the call dummy, so that `finish' after a stop
2207 in a call dummy works.
2208 Tweeking current_gdbarch is not an optimal solution, but the call to
2209 sparc_fix_call_dummy is immediately followed by a call to run_stack_dummy,
2210 which is the only function where dummy_breakpoint_offset is actually
2211 used, if it is non-zero. */
2212 if (TYPE_CODE (value_type
) == TYPE_CODE_STRUCT
2213 || TYPE_CODE (value_type
) == TYPE_CODE_UNION
)
2215 store_unsigned_integer (dummy
+ CALL_DUMMY_CALL_OFFSET
+ 8, 4,
2216 TYPE_LENGTH (value_type
) & 0x1fff);
2217 set_gdbarch_call_dummy_breakpoint_offset (current_gdbarch
, 0x30);
2220 set_gdbarch_call_dummy_breakpoint_offset (current_gdbarch
, 0x2c);
2222 if (!(GDB_TARGET_IS_SPARC64
))
2224 /* If this is not a simulator target, change the first four
2225 instructions of the call dummy to NOPs. Those instructions
2226 include a 'save' instruction and are designed to work around
2227 problems with register window flushing in the simulator. */
2229 if (strcmp (target_shortname
, "sim") != 0)
2231 for (i
= 0; i
< 4; i
++)
2232 store_unsigned_integer (dummy
+ (i
* 4), 4, 0x01000000);
2236 /* If this is a bi-endian target, GDB has written the call dummy
2237 in little-endian order. We must byte-swap it back to big-endian. */
2240 for (i
= 0; i
< CALL_DUMMY_LENGTH
; i
+= 4)
2242 char tmp
= dummy
[i
];
2243 dummy
[i
] = dummy
[i
+ 3];
2246 dummy
[i
+ 1] = dummy
[i
+ 2];
2253 /* Set target byte order based on machine type. */
2256 sparc_target_architecture_hook (const bfd_arch_info_type
*ap
)
2260 if (ap
->mach
== bfd_mach_sparc_sparclite_le
)
2262 target_byte_order
= BFD_ENDIAN_LITTLE
;
2272 * Module "constructor" function.
2275 static struct gdbarch
* sparc_gdbarch_init (struct gdbarch_info info
,
2276 struct gdbarch_list
*arches
);
2277 static void sparc_dump_tdep (struct gdbarch
*, struct ui_file
*);
2280 _initialize_sparc_tdep (void)
2282 /* Hook us into the gdbarch mechanism. */
2283 gdbarch_register (bfd_arch_sparc
, sparc_gdbarch_init
, sparc_dump_tdep
);
2285 tm_print_insn
= gdb_print_insn_sparc
;
2286 tm_print_insn_info
.mach
= TM_PRINT_INSN_MACH
; /* Selects sparc/sparclite */
2287 target_architecture_hook
= sparc_target_architecture_hook
;
2290 /* Compensate for stack bias. Note that we currently don't handle
2291 mixed 32/64 bit code. */
2294 sparc64_read_sp (void)
2296 CORE_ADDR sp
= read_register (SP_REGNUM
);
2304 sparc64_read_fp (void)
2306 CORE_ADDR fp
= read_register (FP_REGNUM
);
2314 sparc64_write_sp (CORE_ADDR val
)
2316 CORE_ADDR oldsp
= read_register (SP_REGNUM
);
2318 write_register (SP_REGNUM
, val
- 2047);
2320 write_register (SP_REGNUM
, val
);
2323 /* The SPARC 64 ABI passes floating-point arguments in FP0 to FP31,
2324 and all other arguments in O0 to O5. They are also copied onto
2325 the stack in the correct places. Apparently (empirically),
2326 structs of less than 16 bytes are passed member-by-member in
2327 separate registers, but I am unable to figure out the algorithm.
2328 Some members go in floating point regs, but I don't know which.
2330 FIXME: Handle small structs (less than 16 bytes containing floats).
2332 The counting regimen for using both integer and FP registers
2333 for argument passing is rather odd -- a single counter is used
2334 for both; this means that if the arguments alternate between
2335 int and float, we will waste every other register of both types. */
2338 sparc64_push_arguments (int nargs
, struct value
**args
, CORE_ADDR sp
,
2339 int struct_return
, CORE_ADDR struct_retaddr
)
2341 int i
, j
, register_counter
= 0;
2343 struct type
*sparc_intreg_type
=
2344 TYPE_LENGTH (builtin_type_long
) == SPARC_INTREG_SIZE
?
2345 builtin_type_long
: builtin_type_long_long
;
2347 sp
= (sp
& ~(((unsigned long) SPARC_INTREG_SIZE
) - 1UL));
2349 /* Figure out how much space we'll need. */
2350 for (i
= nargs
- 1; i
>= 0; i
--)
2352 int len
= TYPE_LENGTH (check_typedef (VALUE_TYPE (args
[i
])));
2353 struct value
*copyarg
= args
[i
];
2356 if (copylen
< SPARC_INTREG_SIZE
)
2358 copyarg
= value_cast (sparc_intreg_type
, copyarg
);
2359 copylen
= SPARC_INTREG_SIZE
;
2368 /* if STRUCT_RETURN, then first argument is the struct return location. */
2370 write_register (O0_REGNUM
+ register_counter
++, struct_retaddr
);
2372 /* Now write the arguments onto the stack, while writing FP
2373 arguments into the FP registers, and other arguments into the
2374 first six 'O' registers. */
2376 for (i
= 0; i
< nargs
; i
++)
2378 int len
= TYPE_LENGTH (check_typedef (VALUE_TYPE (args
[i
])));
2379 struct value
*copyarg
= args
[i
];
2380 enum type_code typecode
= TYPE_CODE (VALUE_TYPE (args
[i
]));
2383 if (typecode
== TYPE_CODE_INT
||
2384 typecode
== TYPE_CODE_BOOL
||
2385 typecode
== TYPE_CODE_CHAR
||
2386 typecode
== TYPE_CODE_RANGE
||
2387 typecode
== TYPE_CODE_ENUM
)
2388 if (len
< SPARC_INTREG_SIZE
)
2390 /* Small ints will all take up the size of one intreg on
2392 copyarg
= value_cast (sparc_intreg_type
, copyarg
);
2393 copylen
= SPARC_INTREG_SIZE
;
2396 write_memory (tempsp
, VALUE_CONTENTS (copyarg
), copylen
);
2399 /* Corner case: Structs consisting of a single float member are floats.
2400 * FIXME! I don't know about structs containing multiple floats!
2401 * Structs containing mixed floats and ints are even more weird.
2406 /* Separate float args from all other args. */
2407 if (typecode
== TYPE_CODE_FLT
&& SPARC_HAS_FPU
)
2409 if (register_counter
< 16)
2411 /* This arg gets copied into a FP register. */
2415 case 4: /* Single-precision (float) */
2416 fpreg
= FP0_REGNUM
+ 2 * register_counter
+ 1;
2417 register_counter
+= 1;
2419 case 8: /* Double-precision (double) */
2420 fpreg
= FP0_REGNUM
+ 2 * register_counter
;
2421 register_counter
+= 1;
2423 case 16: /* Quad-precision (long double) */
2424 fpreg
= FP0_REGNUM
+ 2 * register_counter
;
2425 register_counter
+= 2;
2428 internal_error (__FILE__
, __LINE__
, "bad switch");
2430 write_register_bytes (REGISTER_BYTE (fpreg
),
2431 VALUE_CONTENTS (args
[i
]),
2435 else /* all other args go into the first six 'o' registers */
2438 j
< len
&& register_counter
< 6;
2439 j
+= SPARC_INTREG_SIZE
)
2441 int oreg
= O0_REGNUM
+ register_counter
;
2443 write_register_gen (oreg
, VALUE_CONTENTS (copyarg
) + j
);
2444 register_counter
+= 1;
2451 /* Values <= 32 bytes are returned in o0-o3 (floating-point values are
2452 returned in f0-f3). */
2455 sp64_extract_return_value (struct type
*type
, char *regbuf
, char *valbuf
,
2458 int typelen
= TYPE_LENGTH (type
);
2459 int regsize
= REGISTER_RAW_SIZE (O0_REGNUM
);
2461 if (TYPE_CODE (type
) == TYPE_CODE_FLT
&& SPARC_HAS_FPU
)
2463 memcpy (valbuf
, ®buf
[REGISTER_BYTE (FP0_REGNUM
)], typelen
);
2467 if (TYPE_CODE (type
) != TYPE_CODE_STRUCT
2468 || (TYPE_LENGTH (type
) > 32))
2471 ®buf
[O0_REGNUM
* regsize
+
2472 (typelen
>= regsize
? 0 : regsize
- typelen
)],
2478 char *o0
= ®buf
[O0_REGNUM
* regsize
];
2479 char *f0
= ®buf
[FP0_REGNUM
* regsize
];
2482 for (x
= 0; x
< TYPE_NFIELDS (type
); x
++)
2484 struct field
*f
= &TYPE_FIELDS (type
)[x
];
2485 /* FIXME: We may need to handle static fields here. */
2486 int whichreg
= (f
->loc
.bitpos
+ bitoffset
) / 32;
2487 int remainder
= ((f
->loc
.bitpos
+ bitoffset
) % 32) / 8;
2488 int where
= (f
->loc
.bitpos
+ bitoffset
) / 8;
2489 int size
= TYPE_LENGTH (f
->type
);
2490 int typecode
= TYPE_CODE (f
->type
);
2492 if (typecode
== TYPE_CODE_STRUCT
)
2494 sp64_extract_return_value (f
->type
,
2497 bitoffset
+ f
->loc
.bitpos
);
2499 else if (typecode
== TYPE_CODE_FLT
&& SPARC_HAS_FPU
)
2501 memcpy (valbuf
+ where
, &f0
[whichreg
* 4] + remainder
, size
);
2505 memcpy (valbuf
+ where
, &o0
[whichreg
* 4] + remainder
, size
);
2512 sparc64_extract_return_value (struct type
*type
, char *regbuf
, char *valbuf
)
2514 sp64_extract_return_value (type
, regbuf
, valbuf
, 0);
2518 sparclet_extract_return_value (struct type
*type
,
2522 regbuf
+= REGISTER_RAW_SIZE (O0_REGNUM
) * 8;
2523 if (TYPE_LENGTH (type
) < REGISTER_RAW_SIZE (O0_REGNUM
))
2524 regbuf
+= REGISTER_RAW_SIZE (O0_REGNUM
) - TYPE_LENGTH (type
);
2526 memcpy ((void *) valbuf
, regbuf
, TYPE_LENGTH (type
));
2531 sparc32_stack_align (CORE_ADDR addr
)
2533 return ((addr
+ 7) & -8);
2537 sparc64_stack_align (CORE_ADDR addr
)
2539 return ((addr
+ 15) & -16);
2543 sparc_print_extra_frame_info (struct frame_info
*fi
)
2545 if (fi
&& fi
->extra_info
&& fi
->extra_info
->flat
)
2546 printf_filtered (" flat, pc saved at 0x%s, fp saved at 0x%s\n",
2547 paddr_nz (fi
->extra_info
->pc_addr
),
2548 paddr_nz (fi
->extra_info
->fp_addr
));
2551 /* MULTI_ARCH support */
2554 sparc32_register_name (int regno
)
2556 static char *register_names
[] =
2557 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
2558 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
2559 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
2560 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
2562 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
2563 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
2564 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
2565 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
2567 "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr"
2571 regno
>= (sizeof (register_names
) / sizeof (register_names
[0])))
2574 return register_names
[regno
];
2578 sparc64_register_name (int regno
)
2580 static char *register_names
[] =
2581 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
2582 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
2583 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
2584 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
2586 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
2587 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
2588 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
2589 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
2590 "f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46",
2591 "f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62",
2593 "pc", "npc", "ccr", "fsr", "fprs", "y", "asi", "ver",
2594 "tick", "pil", "pstate", "tstate", "tba", "tl", "tt", "tpc",
2595 "tnpc", "wstate", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
2596 "asr16", "asr17", "asr18", "asr19", "asr20", "asr21", "asr22", "asr23",
2597 "asr24", "asr25", "asr26", "asr27", "asr28", "asr29", "asr30", "asr31",
2598 /* These are here at the end to simplify removing them if we have to. */
2599 "icc", "xcc", "fcc0", "fcc1", "fcc2", "fcc3"
2603 regno
>= (sizeof (register_names
) / sizeof (register_names
[0])))
2606 return register_names
[regno
];
2610 sparclite_register_name (int regno
)
2612 static char *register_names
[] =
2613 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
2614 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
2615 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
2616 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
2618 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
2619 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
2620 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
2621 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
2623 "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr",
2624 "dia1", "dia2", "dda1", "dda2", "ddv1", "ddv2", "dcr", "dsr"
2628 regno
>= (sizeof (register_names
) / sizeof (register_names
[0])))
2631 return register_names
[regno
];
2635 sparclet_register_name (int regno
)
2637 static char *register_names
[] =
2638 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
2639 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
2640 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
2641 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
2643 "", "", "", "", "", "", "", "", /* no floating point registers */
2644 "", "", "", "", "", "", "", "",
2645 "", "", "", "", "", "", "", "",
2646 "", "", "", "", "", "", "", "",
2648 "y", "psr", "wim", "tbr", "pc", "npc", "", "", /* no FPSR or CPSR */
2649 "ccsr", "ccpr", "cccrcr", "ccor", "ccobr", "ccibr", "ccir", "",
2651 /* ASR15 ASR19 (don't display them) */
2652 "asr1", "", "asr17", "asr18", "", "asr20", "asr21", "asr22"
2653 /* None of the rest get displayed */
2655 "awr0", "awr1", "awr2", "awr3", "awr4", "awr5", "awr6", "awr7",
2656 "awr8", "awr9", "awr10", "awr11", "awr12", "awr13", "awr14", "awr15",
2657 "awr16", "awr17", "awr18", "awr19", "awr20", "awr21", "awr22", "awr23",
2658 "awr24", "awr25", "awr26", "awr27", "awr28", "awr29", "awr30", "awr31",
2664 regno
>= (sizeof (register_names
) / sizeof (register_names
[0])))
2667 return register_names
[regno
];
2671 sparc_push_return_address (CORE_ADDR pc_unused
, CORE_ADDR sp
)
2673 if (CALL_DUMMY_LOCATION
== AT_ENTRY_POINT
)
2675 /* The return PC of the dummy_frame is the former 'current' PC
2676 (where we were before we made the target function call).
2677 This is saved in %i7 by push_dummy_frame.
2679 We will save the 'call dummy location' (ie. the address
2680 to which the target function will return) in %o7.
2681 This address will actually be the program's entry point.
2682 There will be a special call_dummy breakpoint there. */
2684 write_register (O7_REGNUM
,
2685 CALL_DUMMY_ADDRESS () - 8);
2691 /* Should call_function allocate stack space for a struct return? */
2694 sparc64_use_struct_convention (int gcc_p
, struct type
*type
)
2696 return (TYPE_LENGTH (type
) > 32);
2699 /* Store the address of the place in which to copy the structure the
2700 subroutine will return. This is called from call_function_by_hand.
2701 The ultimate mystery is, tho, what is the value "16"?
2703 MVS: That's the offset from where the sp is now, to where the
2704 subroutine is gonna expect to find the struct return address. */
2707 sparc32_store_struct_return (CORE_ADDR addr
, CORE_ADDR sp
)
2712 val
= alloca (SPARC_INTREG_SIZE
);
2713 store_unsigned_integer (val
, SPARC_INTREG_SIZE
, addr
);
2714 write_memory (sp
+ (16 * SPARC_INTREG_SIZE
), val
, SPARC_INTREG_SIZE
);
2716 if (CALL_DUMMY_LOCATION
== AT_ENTRY_POINT
)
2718 /* Now adjust the value of the link register, which was previously
2719 stored by push_return_address. Functions that return structs are
2720 peculiar in that they return to link register + 12, rather than
2721 link register + 8. */
2723 o7
= read_register (O7_REGNUM
);
2724 write_register (O7_REGNUM
, o7
- 4);
2729 sparc64_store_struct_return (CORE_ADDR addr
, CORE_ADDR sp
)
2731 /* FIXME: V9 uses %o0 for this. */
2732 /* FIXME MVS: Only for small enough structs!!! */
2734 target_write_memory (sp
+ (16 * SPARC_INTREG_SIZE
),
2735 (char *) &addr
, SPARC_INTREG_SIZE
);
2737 if (CALL_DUMMY_LOCATION
== AT_ENTRY_POINT
)
2739 /* Now adjust the value of the link register, which was previously
2740 stored by push_return_address. Functions that return structs are
2741 peculiar in that they return to link register + 12, rather than
2742 link register + 8. */
2744 write_register (O7_REGNUM
, read_register (O7_REGNUM
) - 4);
2749 /* Default target data type for register REGNO. */
2751 static struct type
*
2752 sparc32_register_virtual_type (int regno
)
2754 if (regno
== PC_REGNUM
||
2755 regno
== FP_REGNUM
||
2757 return builtin_type_unsigned_int
;
2759 return builtin_type_int
;
2761 return builtin_type_float
;
2762 return builtin_type_int
;
2765 static struct type
*
2766 sparc64_register_virtual_type (int regno
)
2768 if (regno
== PC_REGNUM
||
2769 regno
== FP_REGNUM
||
2771 return builtin_type_unsigned_long_long
;
2773 return builtin_type_long_long
;
2775 return builtin_type_float
;
2777 return builtin_type_double
;
2778 return builtin_type_long_long
;
2781 /* Number of bytes of storage in the actual machine representation for
2785 sparc32_register_size (int regno
)
2791 sparc64_register_size (int regno
)
2793 return (regno
< 32 ? 8 : regno
< 64 ? 4 : 8);
2796 /* Index within the `registers' buffer of the first byte of the space
2797 for register REGNO. */
2800 sparc32_register_byte (int regno
)
2806 sparc64_register_byte (int regno
)
2810 else if (regno
< 64)
2811 return 32 * 8 + (regno
- 32) * 4;
2812 else if (regno
< 80)
2813 return 32 * 8 + 32 * 4 + (regno
- 64) * 8;
2815 return 64 * 8 + (regno
- 80) * 8;
2818 /* Immediately after a function call, return the saved pc.
2819 Can't go through the frames for this because on some machines
2820 the new frame is not set up until the new function executes
2821 some instructions. */
2824 sparc_saved_pc_after_call (struct frame_info
*fi
)
2826 return sparc_pc_adjust (read_register (RP_REGNUM
));
2829 /* Convert registers between 'raw' and 'virtual' formats.
2830 They are the same on sparc, so there's nothing to do. */
2833 sparc_convert_to_virtual (int regnum
, struct type
*type
, char *from
, char *to
)
2834 { /* do nothing (should never be called) */
2838 sparc_convert_to_raw (struct type
*type
, int regnum
, char *from
, char *to
)
2839 { /* do nothing (should never be called) */
2842 /* Init saved regs: nothing to do, just a place-holder function. */
2845 sparc_frame_init_saved_regs (struct frame_info
*fi_ignored
)
2849 /* gdbarch fix call dummy:
2850 All this function does is rearrange the arguments before calling
2851 sparc_fix_call_dummy (which does the real work). */
2854 sparc_gdbarch_fix_call_dummy (char *dummy
,
2858 struct value
**args
,
2862 if (CALL_DUMMY_LOCATION
== ON_STACK
)
2863 sparc_fix_call_dummy (dummy
, pc
, fun
, type
, gcc_p
);
2866 /* Coerce float to double: a no-op. */
2869 sparc_coerce_float_to_double (struct type
*formal
, struct type
*actual
)
2874 /* CALL_DUMMY_ADDRESS: fetch the breakpoint address for a call dummy. */
2877 sparc_call_dummy_address (void)
2879 return (CALL_DUMMY_START_OFFSET
) + CALL_DUMMY_BREAKPOINT_OFFSET
;
2882 /* Supply the Y register number to those that need it. */
2885 sparc_y_regnum (void)
2887 return gdbarch_tdep (current_gdbarch
)->y_regnum
;
2891 sparc_reg_struct_has_addr (int gcc_p
, struct type
*type
)
2893 if (GDB_TARGET_IS_SPARC64
)
2894 return (TYPE_LENGTH (type
) > 32);
2896 return (gcc_p
!= 1);
2900 sparc_intreg_size (void)
2902 return SPARC_INTREG_SIZE
;
2906 sparc_return_value_on_stack (struct type
*type
)
2908 if (TYPE_CODE (type
) == TYPE_CODE_FLT
&&
2909 TYPE_LENGTH (type
) > 8)
2916 * Gdbarch "constructor" function.
2919 #define SPARC32_CALL_DUMMY_ON_STACK
2921 #define SPARC_SP_REGNUM 14
2922 #define SPARC_FP_REGNUM 30
2923 #define SPARC_FP0_REGNUM 32
2924 #define SPARC32_NPC_REGNUM 69
2925 #define SPARC32_PC_REGNUM 68
2926 #define SPARC32_Y_REGNUM 64
2927 #define SPARC64_PC_REGNUM 80
2928 #define SPARC64_NPC_REGNUM 81
2929 #define SPARC64_Y_REGNUM 85
2931 static struct gdbarch
*
2932 sparc_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2934 struct gdbarch
*gdbarch
;
2935 struct gdbarch_tdep
*tdep
;
2936 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
2938 static LONGEST call_dummy_32
[] =
2939 { 0xbc100001, 0x9de38000, 0xbc100002, 0xbe100003,
2940 0xda03a058, 0xd803a054, 0xd603a050, 0xd403a04c,
2941 0xd203a048, 0x40000000, 0xd003a044, 0x01000000,
2942 0x91d02001, 0x01000000
2944 static LONGEST call_dummy_64
[] =
2945 { 0x9de3bec0fd3fa7f7LL
, 0xf93fa7eff53fa7e7LL
,
2946 0xf13fa7dfed3fa7d7LL
, 0xe93fa7cfe53fa7c7LL
,
2947 0xe13fa7bfdd3fa7b7LL
, 0xd93fa7afd53fa7a7LL
,
2948 0xd13fa79fcd3fa797LL
, 0xc93fa78fc53fa787LL
,
2949 0xc13fa77fcc3fa777LL
, 0xc83fa76fc43fa767LL
,
2950 0xc03fa75ffc3fa757LL
, 0xf83fa74ff43fa747LL
,
2951 0xf03fa73f01000000LL
, 0x0100000001000000LL
,
2952 0x0100000091580000LL
, 0xd027a72b93500000LL
,
2953 0xd027a72791480000LL
, 0xd027a72391400000LL
,
2954 0xd027a71fda5ba8a7LL
, 0xd85ba89fd65ba897LL
,
2955 0xd45ba88fd25ba887LL
, 0x9fc02000d05ba87fLL
,
2956 0x0100000091d02001LL
, 0x0100000001000000LL
2958 static LONGEST call_dummy_nil
[] = {0};
2960 /* Try to determine the OS ABI of the object we are loading. */
2962 if (info
.abfd
!= NULL
)
2964 osabi
= gdbarch_lookup_osabi (info
.abfd
);
2965 if (osabi
== GDB_OSABI_UNKNOWN
)
2967 /* If it's an ELF file, assume it's Solaris. */
2968 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
2969 osabi
= GDB_OSABI_SOLARIS
;
2973 /* First see if there is already a gdbarch that can satisfy the request. */
2974 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2976 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
2978 /* Make sure the ABI selection matches. */
2979 tdep
= gdbarch_tdep (arches
->gdbarch
);
2980 if (tdep
&& tdep
->osabi
== osabi
)
2981 return arches
->gdbarch
;
2984 /* None found: is the request for a sparc architecture? */
2985 if (info
.bfd_arch_info
->arch
!= bfd_arch_sparc
)
2986 return NULL
; /* No; then it's not for us. */
2988 /* Yes: create a new gdbarch for the specified machine type. */
2989 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
2990 gdbarch
= gdbarch_alloc (&info
, tdep
);
2992 tdep
->osabi
= osabi
;
2994 /* First set settings that are common for all sparc architectures. */
2995 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
2996 set_gdbarch_breakpoint_from_pc (gdbarch
, memory_breakpoint_from_pc
);
2997 set_gdbarch_coerce_float_to_double (gdbarch
,
2998 sparc_coerce_float_to_double
);
2999 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1);
3000 set_gdbarch_call_dummy_p (gdbarch
, 1);
3001 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 1);
3002 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
3003 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
3004 set_gdbarch_deprecated_extract_struct_value_address (gdbarch
, sparc_extract_struct_value_address
);
3005 set_gdbarch_fix_call_dummy (gdbarch
, sparc_gdbarch_fix_call_dummy
);
3006 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
3007 set_gdbarch_fp_regnum (gdbarch
, SPARC_FP_REGNUM
);
3008 set_gdbarch_fp0_regnum (gdbarch
, SPARC_FP0_REGNUM
);
3009 set_gdbarch_frame_args_address (gdbarch
, default_frame_address
);
3010 set_gdbarch_frame_chain (gdbarch
, sparc_frame_chain
);
3011 set_gdbarch_frame_init_saved_regs (gdbarch
, sparc_frame_init_saved_regs
);
3012 set_gdbarch_frame_locals_address (gdbarch
, default_frame_address
);
3013 set_gdbarch_frame_num_args (gdbarch
, frame_num_args_unknown
);
3014 set_gdbarch_frame_saved_pc (gdbarch
, sparc_frame_saved_pc
);
3015 set_gdbarch_frameless_function_invocation (gdbarch
,
3016 frameless_look_for_prologue
);
3017 set_gdbarch_get_saved_register (gdbarch
, sparc_get_saved_register
);
3018 set_gdbarch_init_extra_frame_info (gdbarch
, sparc_init_extra_frame_info
);
3019 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3020 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
3021 set_gdbarch_long_double_bit (gdbarch
, 16 * TARGET_CHAR_BIT
);
3022 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
3023 set_gdbarch_max_register_raw_size (gdbarch
, 8);
3024 set_gdbarch_max_register_virtual_size (gdbarch
, 8);
3025 set_gdbarch_pop_frame (gdbarch
, sparc_pop_frame
);
3026 set_gdbarch_push_return_address (gdbarch
, sparc_push_return_address
);
3027 set_gdbarch_push_dummy_frame (gdbarch
, sparc_push_dummy_frame
);
3028 set_gdbarch_read_pc (gdbarch
, generic_target_read_pc
);
3029 set_gdbarch_register_convert_to_raw (gdbarch
, sparc_convert_to_raw
);
3030 set_gdbarch_register_convert_to_virtual (gdbarch
,
3031 sparc_convert_to_virtual
);
3032 set_gdbarch_register_convertible (gdbarch
,
3033 generic_register_convertible_not
);
3034 set_gdbarch_reg_struct_has_addr (gdbarch
, sparc_reg_struct_has_addr
);
3035 set_gdbarch_return_value_on_stack (gdbarch
, sparc_return_value_on_stack
);
3036 set_gdbarch_saved_pc_after_call (gdbarch
, sparc_saved_pc_after_call
);
3037 set_gdbarch_prologue_frameless_p (gdbarch
, sparc_prologue_frameless_p
);
3038 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
3039 set_gdbarch_skip_prologue (gdbarch
, sparc_skip_prologue
);
3040 set_gdbarch_sp_regnum (gdbarch
, SPARC_SP_REGNUM
);
3041 set_gdbarch_use_generic_dummy_frames (gdbarch
, 0);
3042 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
3045 * Settings that depend only on 32/64 bit word size
3048 switch (info
.bfd_arch_info
->mach
)
3050 case bfd_mach_sparc
:
3051 case bfd_mach_sparc_sparclet
:
3052 case bfd_mach_sparc_sparclite
:
3053 case bfd_mach_sparc_v8plus
:
3054 case bfd_mach_sparc_v8plusa
:
3055 case bfd_mach_sparc_sparclite_le
:
3056 /* 32-bit machine types: */
3058 #ifdef SPARC32_CALL_DUMMY_ON_STACK
3059 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_on_stack
);
3060 set_gdbarch_call_dummy_address (gdbarch
, sparc_call_dummy_address
);
3061 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0x30);
3062 set_gdbarch_call_dummy_length (gdbarch
, 0x38);
3064 /* NOTE: cagney/2002-04-26: Based from info posted by Peter
3065 Schauer around Oct '99. Briefly, due to aspects of the SPARC
3066 ABI, it isn't possible to use ON_STACK with a strictly
3069 Peter Schauer writes ...
3071 No, any call from GDB to a user function returning a
3072 struct/union will fail miserably. Try this:
3091 for (i = 0; i < 4; i++)
3097 Set a breakpoint at the gx = sret () statement, run to it and
3098 issue a `print sret()'. It will not succed with your
3099 approach, and I doubt that continuing the program will work
3102 For details of the ABI see the Sparc Architecture Manual. I
3103 have Version 8 (Prentice Hall ISBN 0-13-825001-4) and the
3104 calling conventions for functions returning aggregate values
3105 are explained in Appendix D.3. */
3107 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
3108 set_gdbarch_call_dummy_words (gdbarch
, call_dummy_32
);
3110 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_at_entry_point
);
3111 set_gdbarch_call_dummy_address (gdbarch
, entry_point_address
);
3112 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
3113 set_gdbarch_call_dummy_length (gdbarch
, 0);
3114 set_gdbarch_call_dummy_location (gdbarch
, AT_ENTRY_POINT
);
3115 set_gdbarch_call_dummy_words (gdbarch
, call_dummy_nil
);
3117 set_gdbarch_call_dummy_stack_adjust (gdbarch
, 68);
3118 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
3119 set_gdbarch_frame_args_skip (gdbarch
, 68);
3120 set_gdbarch_function_start_offset (gdbarch
, 0);
3121 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
3122 set_gdbarch_npc_regnum (gdbarch
, SPARC32_NPC_REGNUM
);
3123 set_gdbarch_pc_regnum (gdbarch
, SPARC32_PC_REGNUM
);
3124 set_gdbarch_ptr_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
3125 set_gdbarch_push_arguments (gdbarch
, sparc32_push_arguments
);
3126 set_gdbarch_read_fp (gdbarch
, generic_target_read_fp
);
3127 set_gdbarch_read_sp (gdbarch
, generic_target_read_sp
);
3129 set_gdbarch_register_byte (gdbarch
, sparc32_register_byte
);
3130 set_gdbarch_register_raw_size (gdbarch
, sparc32_register_size
);
3131 set_gdbarch_register_size (gdbarch
, 4);
3132 set_gdbarch_register_virtual_size (gdbarch
, sparc32_register_size
);
3133 set_gdbarch_register_virtual_type (gdbarch
,
3134 sparc32_register_virtual_type
);
3135 #ifdef SPARC32_CALL_DUMMY_ON_STACK
3136 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (call_dummy_32
));
3138 set_gdbarch_sizeof_call_dummy_words (gdbarch
, 0);
3140 set_gdbarch_stack_align (gdbarch
, sparc32_stack_align
);
3141 set_gdbarch_store_struct_return (gdbarch
, sparc32_store_struct_return
);
3142 set_gdbarch_use_struct_convention (gdbarch
,
3143 generic_use_struct_convention
);
3144 set_gdbarch_write_sp (gdbarch
, generic_target_write_sp
);
3145 tdep
->y_regnum
= SPARC32_Y_REGNUM
;
3146 tdep
->fp_max_regnum
= SPARC_FP0_REGNUM
+ 32;
3147 tdep
->intreg_size
= 4;
3148 tdep
->reg_save_offset
= 0x60;
3149 tdep
->call_dummy_call_offset
= 0x24;
3152 case bfd_mach_sparc_v9
:
3153 case bfd_mach_sparc_v9a
:
3154 /* 64-bit machine types: */
3155 default: /* Any new machine type is likely to be 64-bit. */
3157 #ifdef SPARC64_CALL_DUMMY_ON_STACK
3158 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_on_stack
);
3159 set_gdbarch_call_dummy_address (gdbarch
, sparc_call_dummy_address
);
3160 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 8 * 4);
3161 set_gdbarch_call_dummy_length (gdbarch
, 192);
3162 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
3163 set_gdbarch_call_dummy_start_offset (gdbarch
, 148);
3164 set_gdbarch_call_dummy_words (gdbarch
, call_dummy_64
);
3166 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_at_entry_point
);
3167 set_gdbarch_call_dummy_address (gdbarch
, entry_point_address
);
3168 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
3169 set_gdbarch_call_dummy_length (gdbarch
, 0);
3170 set_gdbarch_call_dummy_location (gdbarch
, AT_ENTRY_POINT
);
3171 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
3172 set_gdbarch_call_dummy_words (gdbarch
, call_dummy_nil
);
3174 set_gdbarch_call_dummy_stack_adjust (gdbarch
, 128);
3175 set_gdbarch_frame_args_skip (gdbarch
, 136);
3176 set_gdbarch_function_start_offset (gdbarch
, 0);
3177 set_gdbarch_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
3178 set_gdbarch_npc_regnum (gdbarch
, SPARC64_NPC_REGNUM
);
3179 set_gdbarch_pc_regnum (gdbarch
, SPARC64_PC_REGNUM
);
3180 set_gdbarch_ptr_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
3181 set_gdbarch_push_arguments (gdbarch
, sparc64_push_arguments
);
3182 /* NOTE different for at_entry */
3183 set_gdbarch_read_fp (gdbarch
, sparc64_read_fp
);
3184 set_gdbarch_read_sp (gdbarch
, sparc64_read_sp
);
3185 /* Some of the registers aren't 64 bits, but it's a lot simpler just
3186 to assume they all are (since most of them are). */
3187 set_gdbarch_register_byte (gdbarch
, sparc64_register_byte
);
3188 set_gdbarch_register_raw_size (gdbarch
, sparc64_register_size
);
3189 set_gdbarch_register_size (gdbarch
, 8);
3190 set_gdbarch_register_virtual_size (gdbarch
, sparc64_register_size
);
3191 set_gdbarch_register_virtual_type (gdbarch
,
3192 sparc64_register_virtual_type
);
3193 #ifdef SPARC64_CALL_DUMMY_ON_STACK
3194 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (call_dummy_64
));
3196 set_gdbarch_sizeof_call_dummy_words (gdbarch
, 0);
3198 set_gdbarch_stack_align (gdbarch
, sparc64_stack_align
);
3199 set_gdbarch_store_struct_return (gdbarch
, sparc64_store_struct_return
);
3200 set_gdbarch_use_struct_convention (gdbarch
,
3201 sparc64_use_struct_convention
);
3202 set_gdbarch_write_sp (gdbarch
, sparc64_write_sp
);
3203 tdep
->y_regnum
= SPARC64_Y_REGNUM
;
3204 tdep
->fp_max_regnum
= SPARC_FP0_REGNUM
+ 48;
3205 tdep
->intreg_size
= 8;
3206 tdep
->reg_save_offset
= 0x90;
3207 tdep
->call_dummy_call_offset
= 148 + 4 * 5;
3212 * Settings that vary per-architecture:
3215 switch (info
.bfd_arch_info
->mach
)
3217 case bfd_mach_sparc
:
3218 set_gdbarch_deprecated_extract_return_value (gdbarch
, sparc32_extract_return_value
);
3219 set_gdbarch_frame_chain_valid (gdbarch
, file_frame_chain_valid
);
3220 set_gdbarch_num_regs (gdbarch
, 72);
3221 set_gdbarch_register_bytes (gdbarch
, 32*4 + 32*4 + 8*4);
3222 set_gdbarch_register_name (gdbarch
, sparc32_register_name
);
3223 set_gdbarch_deprecated_store_return_value (gdbarch
, sparc_store_return_value
);
3224 tdep
->has_fpu
= 1; /* (all but sparclet and sparclite) */
3225 tdep
->fp_register_bytes
= 32 * 4;
3226 tdep
->print_insn_mach
= bfd_mach_sparc
;
3228 case bfd_mach_sparc_sparclet
:
3229 set_gdbarch_deprecated_extract_return_value (gdbarch
, sparclet_extract_return_value
);
3230 set_gdbarch_frame_chain_valid (gdbarch
, file_frame_chain_valid
);
3231 set_gdbarch_num_regs (gdbarch
, 32 + 32 + 8 + 8 + 8);
3232 set_gdbarch_register_bytes (gdbarch
, 32*4 + 32*4 + 8*4 + 8*4 + 8*4);
3233 set_gdbarch_register_name (gdbarch
, sparclet_register_name
);
3234 set_gdbarch_deprecated_store_return_value (gdbarch
, sparclet_store_return_value
);
3235 tdep
->has_fpu
= 0; /* (all but sparclet and sparclite) */
3236 tdep
->fp_register_bytes
= 0;
3237 tdep
->print_insn_mach
= bfd_mach_sparc_sparclet
;
3239 case bfd_mach_sparc_sparclite
:
3240 set_gdbarch_deprecated_extract_return_value (gdbarch
, sparc32_extract_return_value
);
3241 set_gdbarch_frame_chain_valid (gdbarch
, func_frame_chain_valid
);
3242 set_gdbarch_num_regs (gdbarch
, 80);
3243 set_gdbarch_register_bytes (gdbarch
, 32*4 + 32*4 + 8*4 + 8*4);
3244 set_gdbarch_register_name (gdbarch
, sparclite_register_name
);
3245 set_gdbarch_deprecated_store_return_value (gdbarch
, sparc_store_return_value
);
3246 tdep
->has_fpu
= 0; /* (all but sparclet and sparclite) */
3247 tdep
->fp_register_bytes
= 0;
3248 tdep
->print_insn_mach
= bfd_mach_sparc_sparclite
;
3250 case bfd_mach_sparc_v8plus
:
3251 set_gdbarch_deprecated_extract_return_value (gdbarch
, sparc32_extract_return_value
);
3252 set_gdbarch_frame_chain_valid (gdbarch
, file_frame_chain_valid
);
3253 set_gdbarch_num_regs (gdbarch
, 72);
3254 set_gdbarch_register_bytes (gdbarch
, 32*4 + 32*4 + 8*4);
3255 set_gdbarch_register_name (gdbarch
, sparc32_register_name
);
3256 set_gdbarch_deprecated_store_return_value (gdbarch
, sparc_store_return_value
);
3257 tdep
->print_insn_mach
= bfd_mach_sparc
;
3258 tdep
->fp_register_bytes
= 32 * 4;
3259 tdep
->has_fpu
= 1; /* (all but sparclet and sparclite) */
3261 case bfd_mach_sparc_v8plusa
:
3262 set_gdbarch_deprecated_extract_return_value (gdbarch
, sparc32_extract_return_value
);
3263 set_gdbarch_frame_chain_valid (gdbarch
, file_frame_chain_valid
);
3264 set_gdbarch_num_regs (gdbarch
, 72);
3265 set_gdbarch_register_bytes (gdbarch
, 32*4 + 32*4 + 8*4);
3266 set_gdbarch_register_name (gdbarch
, sparc32_register_name
);
3267 set_gdbarch_deprecated_store_return_value (gdbarch
, sparc_store_return_value
);
3268 tdep
->has_fpu
= 1; /* (all but sparclet and sparclite) */
3269 tdep
->fp_register_bytes
= 32 * 4;
3270 tdep
->print_insn_mach
= bfd_mach_sparc
;
3272 case bfd_mach_sparc_sparclite_le
:
3273 set_gdbarch_deprecated_extract_return_value (gdbarch
, sparc32_extract_return_value
);
3274 set_gdbarch_frame_chain_valid (gdbarch
, func_frame_chain_valid
);
3275 set_gdbarch_num_regs (gdbarch
, 80);
3276 set_gdbarch_register_bytes (gdbarch
, 32*4 + 32*4 + 8*4 + 8*4);
3277 set_gdbarch_register_name (gdbarch
, sparclite_register_name
);
3278 set_gdbarch_deprecated_store_return_value (gdbarch
, sparc_store_return_value
);
3279 tdep
->has_fpu
= 0; /* (all but sparclet and sparclite) */
3280 tdep
->fp_register_bytes
= 0;
3281 tdep
->print_insn_mach
= bfd_mach_sparc_sparclite
;
3283 case bfd_mach_sparc_v9
:
3284 set_gdbarch_deprecated_extract_return_value (gdbarch
, sparc64_extract_return_value
);
3285 set_gdbarch_frame_chain_valid (gdbarch
, file_frame_chain_valid
);
3286 set_gdbarch_num_regs (gdbarch
, 125);
3287 set_gdbarch_register_bytes (gdbarch
, 32*8 + 32*8 + 45*8);
3288 set_gdbarch_register_name (gdbarch
, sparc64_register_name
);
3289 set_gdbarch_deprecated_store_return_value (gdbarch
, sparc_store_return_value
);
3290 tdep
->has_fpu
= 1; /* (all but sparclet and sparclite) */
3291 tdep
->fp_register_bytes
= 64 * 4;
3292 tdep
->print_insn_mach
= bfd_mach_sparc_v9a
;
3294 case bfd_mach_sparc_v9a
:
3295 set_gdbarch_deprecated_extract_return_value (gdbarch
, sparc64_extract_return_value
);
3296 set_gdbarch_frame_chain_valid (gdbarch
, file_frame_chain_valid
);
3297 set_gdbarch_num_regs (gdbarch
, 125);
3298 set_gdbarch_register_bytes (gdbarch
, 32*8 + 32*8 + 45*8);
3299 set_gdbarch_register_name (gdbarch
, sparc64_register_name
);
3300 set_gdbarch_deprecated_store_return_value (gdbarch
, sparc_store_return_value
);
3301 tdep
->has_fpu
= 1; /* (all but sparclet and sparclite) */
3302 tdep
->fp_register_bytes
= 64 * 4;
3303 tdep
->print_insn_mach
= bfd_mach_sparc_v9a
;
3307 /* Hook in OS ABI-specific overrides, if they have been registered. */
3308 gdbarch_init_osabi (info
, gdbarch
, osabi
);
3314 sparc_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
3316 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3321 fprintf_unfiltered (file
, "sparc_dump_tdep: OS ABI = %s\n",
3322 gdbarch_osabi_name (tdep
->osabi
));