1 /* Target-dependent code for SPARC.
3 Copyright (C) 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street, Fifth Floor,
20 Boston, MA 02110-1301, USA. */
23 #include "arch-utils.h"
25 #include "dwarf2-frame.h"
26 #include "floatformat.h"
28 #include "frame-base.h"
29 #include "frame-unwind.h"
40 #include "gdb_assert.h"
41 #include "gdb_string.h"
43 #include "sparc-tdep.h"
47 /* This file implements the SPARC 32-bit ABI as defined by the section
48 "Low-Level System Information" of the SPARC Compliance Definition
49 (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC. The SCD
50 lists changes with respect to the original 32-bit psABI as defined
51 in the "System V ABI, SPARC Processor Supplement".
53 Note that if we talk about SunOS, we mean SunOS 4.x, which was
54 BSD-based, which is sometimes (retroactively?) referred to as
55 Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and
56 above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9
57 suffering from severe version number inflation). Solaris 2.x is
58 also known as SunOS 5.x, since that's what uname(1) says. Solaris
61 /* Please use the sparc32_-prefix for 32-bit specific code, the
62 sparc64_-prefix for 64-bit specific code and the sparc_-prefix for
63 code that can handle both. The 64-bit specific code lives in
64 sparc64-tdep.c; don't add any here. */
66 /* The SPARC Floating-Point Quad-Precision format is similar to
67 big-endian IA-64 Quad-recision format. */
68 #define floatformats_sparc_quad floatformats_ia64_quad
70 /* The stack pointer is offset from the stack frame by a BIAS of 2047
71 (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC
72 hosts, so undefine it first. */
76 /* Macros to extract fields from SPARC instructions. */
77 #define X_OP(i) (((i) >> 30) & 0x3)
78 #define X_RD(i) (((i) >> 25) & 0x1f)
79 #define X_A(i) (((i) >> 29) & 1)
80 #define X_COND(i) (((i) >> 25) & 0xf)
81 #define X_OP2(i) (((i) >> 22) & 0x7)
82 #define X_IMM22(i) ((i) & 0x3fffff)
83 #define X_OP3(i) (((i) >> 19) & 0x3f)
84 #define X_RS1(i) (((i) >> 14) & 0x1f)
85 #define X_RS2(i) ((i) & 0x1f)
86 #define X_I(i) (((i) >> 13) & 1)
87 /* Sign extension macros. */
88 #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000)
89 #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000)
90 #define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000)
92 /* Fetch the instruction at PC. Instructions are always big-endian
93 even if the processor operates in little-endian mode. */
96 sparc_fetch_instruction (CORE_ADDR pc
)
102 /* If we can't read the instruction at PC, return zero. */
103 if (read_memory_nobpt (pc
, buf
, sizeof (buf
)))
107 for (i
= 0; i
< sizeof (buf
); i
++)
108 insn
= (insn
<< 8) | buf
[i
];
113 /* Return non-zero if the instruction corresponding to PC is an "unimp"
117 sparc_is_unimp_insn (CORE_ADDR pc
)
119 const unsigned long insn
= sparc_fetch_instruction (pc
);
121 return ((insn
& 0xc1c00000) == 0);
124 /* OpenBSD/sparc includes StackGhost, which according to the author's
125 website http://stackghost.cerias.purdue.edu "... transparently and
126 automatically protects applications' stack frames; more
127 specifically, it guards the return pointers. The protection
128 mechanisms require no application source or binary modification and
129 imposes only a negligible performance penalty."
131 The same website provides the following description of how
134 "StackGhost interfaces with the kernel trap handler that would
135 normally write out registers to the stack and the handler that
136 would read them back in. By XORing a cookie into the
137 return-address saved in the user stack when it is actually written
138 to the stack, and then XOR it out when the return-address is pulled
139 from the stack, StackGhost can cause attacker corrupted return
140 pointers to behave in a manner the attacker cannot predict.
141 StackGhost can also use several unused bits in the return pointer
142 to detect a smashed return pointer and abort the process."
144 For GDB this means that whenever we're reading %i7 from a stack
145 frame's window save area, we'll have to XOR the cookie.
147 More information on StackGuard can be found on in:
149 Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated
150 Stack Protection." 2001. Published in USENIX Security Symposium
153 /* Fetch StackGhost Per-Process XOR cookie. */
156 sparc_fetch_wcookie (void)
158 struct target_ops
*ops
= ¤t_target
;
162 len
= target_read (ops
, TARGET_OBJECT_WCOOKIE
, NULL
, buf
, 0, 8);
166 /* We should have either an 32-bit or an 64-bit cookie. */
167 gdb_assert (len
== 4 || len
== 8);
169 return extract_unsigned_integer (buf
, len
);
173 /* Return the contents if register REGNUM as an address. */
176 sparc_address_from_register (int regnum
)
180 regcache_cooked_read_unsigned (current_regcache
, regnum
, &addr
);
185 /* The functions on this page are intended to be used to classify
186 function arguments. */
188 /* Check whether TYPE is "Integral or Pointer". */
191 sparc_integral_or_pointer_p (const struct type
*type
)
193 int len
= TYPE_LENGTH (type
);
195 switch (TYPE_CODE (type
))
201 case TYPE_CODE_RANGE
:
202 /* We have byte, half-word, word and extended-word/doubleword
203 integral types. The doubleword is an extension to the
204 original 32-bit ABI by the SCD 2.4.x. */
205 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
208 /* Allow either 32-bit or 64-bit pointers. */
209 return (len
== 4 || len
== 8);
217 /* Check whether TYPE is "Floating". */
220 sparc_floating_p (const struct type
*type
)
222 switch (TYPE_CODE (type
))
226 int len
= TYPE_LENGTH (type
);
227 return (len
== 4 || len
== 8 || len
== 16);
236 /* Check whether TYPE is "Structure or Union". */
239 sparc_structure_or_union_p (const struct type
*type
)
241 switch (TYPE_CODE (type
))
243 case TYPE_CODE_STRUCT
:
244 case TYPE_CODE_UNION
:
253 /* Register information. */
255 static const char *sparc32_register_names
[] =
257 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
258 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
259 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
260 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
262 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
263 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
264 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
265 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
267 "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr"
270 /* Total number of registers. */
271 #define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names)
273 /* We provide the aliases %d0..%d30 for the floating registers as
274 "psuedo" registers. */
276 static const char *sparc32_pseudo_register_names
[] =
278 "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14",
279 "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30"
282 /* Total number of pseudo registers. */
283 #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names)
285 /* Return the name of register REGNUM. */
288 sparc32_register_name (int regnum
)
290 if (regnum
>= 0 && regnum
< SPARC32_NUM_REGS
)
291 return sparc32_register_names
[regnum
];
293 if (regnum
< SPARC32_NUM_REGS
+ SPARC32_NUM_PSEUDO_REGS
)
294 return sparc32_pseudo_register_names
[regnum
- SPARC32_NUM_REGS
];
301 struct type
*sparc_psr_type
;
304 struct type
*sparc_fsr_type
;
306 /* Construct types for ISA-specific registers. */
309 sparc_init_types (void)
313 type
= init_flags_type ("builtin_type_sparc_psr", 4);
314 append_flags_type_flag (type
, 5, "ET");
315 append_flags_type_flag (type
, 6, "PS");
316 append_flags_type_flag (type
, 7, "S");
317 append_flags_type_flag (type
, 12, "EF");
318 append_flags_type_flag (type
, 13, "EC");
319 sparc_psr_type
= type
;
321 type
= init_flags_type ("builtin_type_sparc_fsr", 4);
322 append_flags_type_flag (type
, 0, "NXA");
323 append_flags_type_flag (type
, 1, "DZA");
324 append_flags_type_flag (type
, 2, "UFA");
325 append_flags_type_flag (type
, 3, "OFA");
326 append_flags_type_flag (type
, 4, "NVA");
327 append_flags_type_flag (type
, 5, "NXC");
328 append_flags_type_flag (type
, 6, "DZC");
329 append_flags_type_flag (type
, 7, "UFC");
330 append_flags_type_flag (type
, 8, "OFC");
331 append_flags_type_flag (type
, 9, "NVC");
332 append_flags_type_flag (type
, 22, "NS");
333 append_flags_type_flag (type
, 23, "NXM");
334 append_flags_type_flag (type
, 24, "DZM");
335 append_flags_type_flag (type
, 25, "UFM");
336 append_flags_type_flag (type
, 26, "OFM");
337 append_flags_type_flag (type
, 27, "NVM");
338 sparc_fsr_type
= type
;
341 /* Return the GDB type object for the "standard" data type of data in
345 sparc32_register_type (struct gdbarch
*gdbarch
, int regnum
)
347 if (regnum
>= SPARC_F0_REGNUM
&& regnum
<= SPARC_F31_REGNUM
)
348 return builtin_type_float
;
350 if (regnum
>= SPARC32_D0_REGNUM
&& regnum
<= SPARC32_D30_REGNUM
)
351 return builtin_type_double
;
353 if (regnum
== SPARC_SP_REGNUM
|| regnum
== SPARC_FP_REGNUM
)
354 return builtin_type_void_data_ptr
;
356 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== SPARC32_NPC_REGNUM
)
357 return builtin_type_void_func_ptr
;
359 if (regnum
== SPARC32_PSR_REGNUM
)
360 return sparc_psr_type
;
362 if (regnum
== SPARC32_FSR_REGNUM
)
363 return sparc_fsr_type
;
365 return builtin_type_int32
;
369 sparc32_pseudo_register_read (struct gdbarch
*gdbarch
,
370 struct regcache
*regcache
,
371 int regnum
, gdb_byte
*buf
)
373 gdb_assert (regnum
>= SPARC32_D0_REGNUM
&& regnum
<= SPARC32_D30_REGNUM
);
375 regnum
= SPARC_F0_REGNUM
+ 2 * (regnum
- SPARC32_D0_REGNUM
);
376 regcache_raw_read (regcache
, regnum
, buf
);
377 regcache_raw_read (regcache
, regnum
+ 1, buf
+ 4);
381 sparc32_pseudo_register_write (struct gdbarch
*gdbarch
,
382 struct regcache
*regcache
,
383 int regnum
, const gdb_byte
*buf
)
385 gdb_assert (regnum
>= SPARC32_D0_REGNUM
&& regnum
<= SPARC32_D30_REGNUM
);
387 regnum
= SPARC_F0_REGNUM
+ 2 * (regnum
- SPARC32_D0_REGNUM
);
388 regcache_raw_write (regcache
, regnum
, buf
);
389 regcache_raw_write (regcache
, regnum
+ 1, buf
+ 4);
394 sparc32_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
395 CORE_ADDR funcaddr
, int using_gcc
,
396 struct value
**args
, int nargs
,
397 struct type
*value_type
,
398 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
)
403 if (using_struct_return (value_type
, using_gcc
))
407 /* This is an UNIMP instruction. */
408 store_unsigned_integer (buf
, 4, TYPE_LENGTH (value_type
) & 0x1fff);
409 write_memory (sp
- 8, buf
, 4);
417 sparc32_store_arguments (struct regcache
*regcache
, int nargs
,
418 struct value
**args
, CORE_ADDR sp
,
419 int struct_return
, CORE_ADDR struct_addr
)
421 /* Number of words in the "parameter array". */
422 int num_elements
= 0;
426 for (i
= 0; i
< nargs
; i
++)
428 struct type
*type
= value_type (args
[i
]);
429 int len
= TYPE_LENGTH (type
);
431 if (sparc_structure_or_union_p (type
)
432 || (sparc_floating_p (type
) && len
== 16))
434 /* Structure, Union and Quad-Precision Arguments. */
437 /* Use doubleword alignment for these values. That's always
438 correct, and wasting a few bytes shouldn't be a problem. */
441 write_memory (sp
, value_contents (args
[i
]), len
);
442 args
[i
] = value_from_pointer (lookup_pointer_type (type
), sp
);
445 else if (sparc_floating_p (type
))
447 /* Floating arguments. */
448 gdb_assert (len
== 4 || len
== 8);
449 num_elements
+= (len
/ 4);
453 /* Integral and pointer arguments. */
454 gdb_assert (sparc_integral_or_pointer_p (type
));
457 args
[i
] = value_cast (builtin_type_int32
, args
[i
]);
458 num_elements
+= ((len
+ 3) / 4);
462 /* Always allocate at least six words. */
463 sp
-= max (6, num_elements
) * 4;
465 /* The psABI says that "Software convention requires space for the
466 struct/union return value pointer, even if the word is unused." */
469 /* The psABI says that "Although software convention and the
470 operating system require every stack frame to be doubleword
474 for (i
= 0; i
< nargs
; i
++)
476 const bfd_byte
*valbuf
= value_contents (args
[i
]);
477 struct type
*type
= value_type (args
[i
]);
478 int len
= TYPE_LENGTH (type
);
480 gdb_assert (len
== 4 || len
== 8);
484 int regnum
= SPARC_O0_REGNUM
+ element
;
486 regcache_cooked_write (regcache
, regnum
, valbuf
);
487 if (len
> 4 && element
< 5)
488 regcache_cooked_write (regcache
, regnum
+ 1, valbuf
+ 4);
491 /* Always store the argument in memory. */
492 write_memory (sp
+ 4 + element
* 4, valbuf
, len
);
496 gdb_assert (element
== num_elements
);
502 store_unsigned_integer (buf
, 4, struct_addr
);
503 write_memory (sp
, buf
, 4);
510 sparc32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
511 struct regcache
*regcache
, CORE_ADDR bp_addr
,
512 int nargs
, struct value
**args
, CORE_ADDR sp
,
513 int struct_return
, CORE_ADDR struct_addr
)
515 CORE_ADDR call_pc
= (struct_return
? (bp_addr
- 12) : (bp_addr
- 8));
517 /* Set return address. */
518 regcache_cooked_write_unsigned (regcache
, SPARC_O7_REGNUM
, call_pc
);
520 /* Set up function arguments. */
521 sp
= sparc32_store_arguments (regcache
, nargs
, args
, sp
,
522 struct_return
, struct_addr
);
524 /* Allocate the 16-word window save area. */
527 /* Stack should be doubleword aligned at this point. */
528 gdb_assert (sp
% 8 == 0);
530 /* Finally, update the stack pointer. */
531 regcache_cooked_write_unsigned (regcache
, SPARC_SP_REGNUM
, sp
);
537 /* Use the program counter to determine the contents and size of a
538 breakpoint instruction. Return a pointer to a string of bytes that
539 encode a breakpoint instruction, store the length of the string in
540 *LEN and optionally adjust *PC to point to the correct memory
541 location for inserting the breakpoint. */
543 static const gdb_byte
*
544 sparc_breakpoint_from_pc (CORE_ADDR
*pc
, int *len
)
546 static const gdb_byte break_insn
[] = { 0x91, 0xd0, 0x20, 0x01 };
548 *len
= sizeof (break_insn
);
553 /* Allocate and initialize a frame cache. */
555 static struct sparc_frame_cache
*
556 sparc_alloc_frame_cache (void)
558 struct sparc_frame_cache
*cache
;
561 cache
= FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache
);
567 /* Frameless until proven otherwise. */
568 cache
->frameless_p
= 1;
570 cache
->struct_return_p
= 0;
575 /* GCC generates several well-known sequences of instructions at the begining
576 of each function prologue when compiling with -fstack-check. If one of
577 such sequences starts at START_PC, then return the address of the
578 instruction immediately past this sequence. Otherwise, return START_PC. */
581 sparc_skip_stack_check (const CORE_ADDR start_pc
)
583 CORE_ADDR pc
= start_pc
;
585 int offset_stack_checking_sequence
= 0;
587 /* With GCC, all stack checking sequences begin with the same two
590 /* sethi <some immediate>,%g1 */
591 insn
= sparc_fetch_instruction (pc
);
593 if (!(X_OP (insn
) == 0 && X_OP2 (insn
) == 0x4 && X_RD (insn
) == 1))
596 /* sub %sp, %g1, %g1 */
597 insn
= sparc_fetch_instruction (pc
);
599 if (!(X_OP (insn
) == 2 && X_OP3 (insn
) == 0x4 && !X_I(insn
)
600 && X_RD (insn
) == 1 && X_RS1 (insn
) == 14 && X_RS2 (insn
) == 1))
603 insn
= sparc_fetch_instruction (pc
);
606 /* First possible sequence:
607 [first two instructions above]
608 clr [%g1 - some immediate] */
610 /* clr [%g1 - some immediate] */
611 if (X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && X_I(insn
)
612 && X_RS1 (insn
) == 1 && X_RD (insn
) == 0)
614 /* Valid stack-check sequence, return the new PC. */
618 /* Second possible sequence: A small number of probes.
619 [first two instructions above]
621 add %g1, -<some immediate>, %g1
623 [repeat the two instructions above any (small) number of times]
624 clr [%g1 - some immediate] */
627 else if (X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && !X_I(insn
)
628 && X_RS1 (insn
) == 1 && X_RD (insn
) == 0)
632 /* add %g1, -<some immediate>, %g1 */
633 insn
= sparc_fetch_instruction (pc
);
635 if (!(X_OP (insn
) == 2 && X_OP3(insn
) == 0 && X_I(insn
)
636 && X_RS1 (insn
) == 1 && X_RD (insn
) == 1))
640 insn
= sparc_fetch_instruction (pc
);
642 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && !X_I(insn
)
643 && X_RD (insn
) == 0 && X_RS1 (insn
) == 1))
647 /* clr [%g1 - some immediate] */
648 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && X_I(insn
)
649 && X_RS1 (insn
) == 1 && X_RD (insn
) == 0))
652 /* We found a valid stack-check sequence, return the new PC. */
656 /* Third sequence: A probing loop.
657 [first two instructions above]
658 sethi <some immediate>, %g4
662 add %g1, -<some immediate>, %g1
665 clr [%g4 - some immediate] */
667 /* sethi <some immediate>, %g4 */
668 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 0x4 && X_RD (insn
) == 4)
670 /* sub %g1, %g4, %g4 */
671 insn
= sparc_fetch_instruction (pc
);
673 if (!(X_OP (insn
) == 2 && X_OP3 (insn
) == 0x4 && !X_I(insn
)
674 && X_RD (insn
) == 4 && X_RS1 (insn
) == 1 && X_RS2 (insn
) == 4))
678 insn
= sparc_fetch_instruction (pc
);
680 if (!(X_OP (insn
) == 2 && X_OP3 (insn
) == 0x14 && !X_I(insn
)
681 && X_RD (insn
) == 0 && X_RS1 (insn
) == 1 && X_RS2 (insn
) == 4))
685 insn
= sparc_fetch_instruction (pc
);
687 if (!(X_OP (insn
) == 0 && X_COND (insn
) == 0x1))
690 /* add %g1, -<some immediate>, %g1 */
691 insn
= sparc_fetch_instruction (pc
);
693 if (!(X_OP (insn
) == 2 && X_OP3(insn
) == 0 && X_I(insn
)
694 && X_RS1 (insn
) == 1 && X_RD (insn
) == 1))
698 insn
= sparc_fetch_instruction (pc
);
700 if (!(X_OP (insn
) == 0 && X_COND (insn
) == 0x8))
704 insn
= sparc_fetch_instruction (pc
);
706 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && !X_I(insn
)
707 && X_RD (insn
) == 0 && X_RS1 (insn
) == 1))
710 /* clr [%g4 - some immediate] */
711 insn
= sparc_fetch_instruction (pc
);
713 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && X_I(insn
)
714 && X_RS1 (insn
) == 4 && X_RD (insn
) == 0))
717 /* We found a valid stack-check sequence, return the new PC. */
721 /* No stack check code in our prologue, return the start_pc. */
726 sparc_analyze_prologue (CORE_ADDR pc
, CORE_ADDR current_pc
,
727 struct sparc_frame_cache
*cache
)
729 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
734 pc
= sparc_skip_stack_check (pc
);
736 if (current_pc
<= pc
)
739 /* We have to handle to "Procedure Linkage Table" (PLT) special. On
740 SPARC the linker usually defines a symbol (typically
741 _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section.
742 This symbol makes us end up here with PC pointing at the start of
743 the PLT and CURRENT_PC probably pointing at a PLT entry. If we
744 would do our normal prologue analysis, we would probably conclude
745 that we've got a frame when in reality we don't, since the
746 dynamic linker patches up the first PLT with some code that
747 starts with a SAVE instruction. Patch up PC such that it points
748 at the start of our PLT entry. */
749 if (tdep
->plt_entry_size
> 0 && in_plt_section (current_pc
, NULL
))
750 pc
= current_pc
- ((current_pc
- pc
) % tdep
->plt_entry_size
);
752 insn
= sparc_fetch_instruction (pc
);
754 /* Recognize a SETHI insn and record its destination. */
755 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 0x04)
760 insn
= sparc_fetch_instruction (pc
+ 4);
763 /* Allow for an arithmetic operation on DEST or %g1. */
764 if (X_OP (insn
) == 2 && X_I (insn
)
765 && (X_RD (insn
) == 1 || X_RD (insn
) == dest
))
769 insn
= sparc_fetch_instruction (pc
+ 8);
772 /* Check for the SAVE instruction that sets up the frame. */
773 if (X_OP (insn
) == 2 && X_OP3 (insn
) == 0x3c)
775 cache
->frameless_p
= 0;
776 return pc
+ offset
+ 4;
783 sparc_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
785 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
786 return frame_unwind_register_unsigned (next_frame
, tdep
->pc_regnum
);
789 /* Return PC of first real instruction of the function starting at
793 sparc32_skip_prologue (CORE_ADDR start_pc
)
795 struct symtab_and_line sal
;
796 CORE_ADDR func_start
, func_end
;
797 struct sparc_frame_cache cache
;
799 /* This is the preferred method, find the end of the prologue by
800 using the debugging information. */
801 if (find_pc_partial_function (start_pc
, NULL
, &func_start
, &func_end
))
803 sal
= find_pc_line (func_start
, 0);
805 if (sal
.end
< func_end
806 && start_pc
<= sal
.end
)
810 start_pc
= sparc_analyze_prologue (start_pc
, 0xffffffffUL
, &cache
);
812 /* The psABI says that "Although the first 6 words of arguments
813 reside in registers, the standard stack frame reserves space for
814 them.". It also suggests that a function may use that space to
815 "write incoming arguments 0 to 5" into that space, and that's
816 indeed what GCC seems to be doing. In that case GCC will
817 generate debug information that points to the stack slots instead
818 of the registers, so we should consider the instructions that
819 write out these incoming arguments onto the stack. Of course we
820 only need to do this if we have a stack frame. */
822 while (!cache
.frameless_p
)
824 unsigned long insn
= sparc_fetch_instruction (start_pc
);
826 /* Recognize instructions that store incoming arguments in
827 %i0...%i5 into the corresponding stack slot. */
828 if (X_OP (insn
) == 3 && (X_OP3 (insn
) & 0x3c) == 0x04 && X_I (insn
)
829 && (X_RD (insn
) >= 24 && X_RD (insn
) <= 29) && X_RS1 (insn
) == 30
830 && X_SIMM13 (insn
) == 68 + (X_RD (insn
) - 24) * 4)
844 struct sparc_frame_cache
*
845 sparc_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
847 struct sparc_frame_cache
*cache
;
852 cache
= sparc_alloc_frame_cache ();
855 cache
->pc
= frame_func_unwind (next_frame
, NORMAL_FRAME
);
857 sparc_analyze_prologue (cache
->pc
, frame_pc_unwind (next_frame
), cache
);
859 if (cache
->frameless_p
)
861 /* This function is frameless, so %fp (%i6) holds the frame
862 pointer for our calling frame. Use %sp (%o6) as this frame's
865 frame_unwind_register_unsigned (next_frame
, SPARC_SP_REGNUM
);
869 /* For normal frames, %fp (%i6) holds the frame pointer, the
870 base address for the current stack frame. */
872 frame_unwind_register_unsigned (next_frame
, SPARC_FP_REGNUM
);
882 sparc32_struct_return_from_sym (struct symbol
*sym
)
884 struct type
*type
= check_typedef (SYMBOL_TYPE (sym
));
885 enum type_code code
= TYPE_CODE (type
);
887 if (code
== TYPE_CODE_FUNC
|| code
== TYPE_CODE_METHOD
)
889 type
= check_typedef (TYPE_TARGET_TYPE (type
));
890 if (sparc_structure_or_union_p (type
)
891 || (sparc_floating_p (type
) && TYPE_LENGTH (type
) == 16))
898 struct sparc_frame_cache
*
899 sparc32_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
901 struct sparc_frame_cache
*cache
;
907 cache
= sparc_frame_cache (next_frame
, this_cache
);
909 sym
= find_pc_function (cache
->pc
);
912 cache
->struct_return_p
= sparc32_struct_return_from_sym (sym
);
916 /* There is no debugging information for this function to
917 help us determine whether this function returns a struct
918 or not. So we rely on another heuristic which is to check
919 the instruction at the return address and see if this is
920 an "unimp" instruction. If it is, then it is a struct-return
923 int regnum
= cache
->frameless_p
? SPARC_O7_REGNUM
: SPARC_I7_REGNUM
;
925 pc
= frame_unwind_register_unsigned (next_frame
, regnum
) + 8;
926 if (sparc_is_unimp_insn (pc
))
927 cache
->struct_return_p
= 1;
934 sparc32_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
935 struct frame_id
*this_id
)
937 struct sparc_frame_cache
*cache
=
938 sparc32_frame_cache (next_frame
, this_cache
);
940 /* This marks the outermost frame. */
941 if (cache
->base
== 0)
944 (*this_id
) = frame_id_build (cache
->base
, cache
->pc
);
948 sparc32_frame_prev_register (struct frame_info
*next_frame
, void **this_cache
,
949 int regnum
, int *optimizedp
,
950 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
951 int *realnump
, gdb_byte
*valuep
)
953 struct sparc_frame_cache
*cache
=
954 sparc32_frame_cache (next_frame
, this_cache
);
956 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== SPARC32_NPC_REGNUM
)
964 CORE_ADDR pc
= (regnum
== SPARC32_NPC_REGNUM
) ? 4 : 0;
966 /* If this functions has a Structure, Union or
967 Quad-Precision return value, we have to skip the UNIMP
968 instruction that encodes the size of the structure. */
969 if (cache
->struct_return_p
)
972 regnum
= cache
->frameless_p
? SPARC_O7_REGNUM
: SPARC_I7_REGNUM
;
973 pc
+= frame_unwind_register_unsigned (next_frame
, regnum
) + 8;
974 store_unsigned_integer (valuep
, 4, pc
);
979 /* Handle StackGhost. */
981 ULONGEST wcookie
= sparc_fetch_wcookie ();
983 if (wcookie
!= 0 && !cache
->frameless_p
&& regnum
== SPARC_I7_REGNUM
)
991 CORE_ADDR addr
= cache
->base
+ (regnum
- SPARC_L0_REGNUM
) * 4;
994 /* Read the value in from memory. */
995 i7
= get_frame_memory_unsigned (next_frame
, addr
, 4);
996 store_unsigned_integer (valuep
, 4, i7
^ wcookie
);
1002 /* The previous frame's `local' and `in' registers have been saved
1003 in the register save area. */
1004 if (!cache
->frameless_p
1005 && regnum
>= SPARC_L0_REGNUM
&& regnum
<= SPARC_I7_REGNUM
)
1008 *lvalp
= lval_memory
;
1009 *addrp
= cache
->base
+ (regnum
- SPARC_L0_REGNUM
) * 4;
1013 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
1015 /* Read the value in from memory. */
1016 read_memory (*addrp
, valuep
, register_size (gdbarch
, regnum
));
1021 /* The previous frame's `out' registers are accessable as the
1022 current frame's `in' registers. */
1023 if (!cache
->frameless_p
1024 && regnum
>= SPARC_O0_REGNUM
&& regnum
<= SPARC_O7_REGNUM
)
1025 regnum
+= (SPARC_I0_REGNUM
- SPARC_O0_REGNUM
);
1028 *lvalp
= lval_register
;
1032 frame_unwind_register (next_frame
, (*realnump
), valuep
);
1035 static const struct frame_unwind sparc32_frame_unwind
=
1038 sparc32_frame_this_id
,
1039 sparc32_frame_prev_register
1042 static const struct frame_unwind
*
1043 sparc32_frame_sniffer (struct frame_info
*next_frame
)
1045 return &sparc32_frame_unwind
;
1050 sparc32_frame_base_address (struct frame_info
*next_frame
, void **this_cache
)
1052 struct sparc_frame_cache
*cache
=
1053 sparc32_frame_cache (next_frame
, this_cache
);
1058 static const struct frame_base sparc32_frame_base
=
1060 &sparc32_frame_unwind
,
1061 sparc32_frame_base_address
,
1062 sparc32_frame_base_address
,
1063 sparc32_frame_base_address
1066 static struct frame_id
1067 sparc_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1071 sp
= frame_unwind_register_unsigned (next_frame
, SPARC_SP_REGNUM
);
1074 return frame_id_build (sp
, frame_pc_unwind (next_frame
));
1078 /* Extract from an array REGBUF containing the (raw) register state, a
1079 function return value of TYPE, and copy that into VALBUF. */
1082 sparc32_extract_return_value (struct type
*type
, struct regcache
*regcache
,
1085 int len
= TYPE_LENGTH (type
);
1088 gdb_assert (!sparc_structure_or_union_p (type
));
1089 gdb_assert (!(sparc_floating_p (type
) && len
== 16));
1091 if (sparc_floating_p (type
))
1093 /* Floating return values. */
1094 regcache_cooked_read (regcache
, SPARC_F0_REGNUM
, buf
);
1096 regcache_cooked_read (regcache
, SPARC_F1_REGNUM
, buf
+ 4);
1097 memcpy (valbuf
, buf
, len
);
1101 /* Integral and pointer return values. */
1102 gdb_assert (sparc_integral_or_pointer_p (type
));
1104 regcache_cooked_read (regcache
, SPARC_O0_REGNUM
, buf
);
1107 regcache_cooked_read (regcache
, SPARC_O1_REGNUM
, buf
+ 4);
1108 gdb_assert (len
== 8);
1109 memcpy (valbuf
, buf
, 8);
1113 /* Just stripping off any unused bytes should preserve the
1114 signed-ness just fine. */
1115 memcpy (valbuf
, buf
+ 4 - len
, len
);
1120 /* Write into the appropriate registers a function return value stored
1121 in VALBUF of type TYPE. */
1124 sparc32_store_return_value (struct type
*type
, struct regcache
*regcache
,
1125 const gdb_byte
*valbuf
)
1127 int len
= TYPE_LENGTH (type
);
1130 gdb_assert (!sparc_structure_or_union_p (type
));
1131 gdb_assert (!(sparc_floating_p (type
) && len
== 16));
1133 if (sparc_floating_p (type
))
1135 /* Floating return values. */
1136 memcpy (buf
, valbuf
, len
);
1137 regcache_cooked_write (regcache
, SPARC_F0_REGNUM
, buf
);
1139 regcache_cooked_write (regcache
, SPARC_F1_REGNUM
, buf
+ 4);
1143 /* Integral and pointer return values. */
1144 gdb_assert (sparc_integral_or_pointer_p (type
));
1148 gdb_assert (len
== 8);
1149 memcpy (buf
, valbuf
, 8);
1150 regcache_cooked_write (regcache
, SPARC_O1_REGNUM
, buf
+ 4);
1154 /* ??? Do we need to do any sign-extension here? */
1155 memcpy (buf
+ 4 - len
, valbuf
, len
);
1157 regcache_cooked_write (regcache
, SPARC_O0_REGNUM
, buf
);
1161 static enum return_value_convention
1162 sparc32_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
1163 struct regcache
*regcache
, gdb_byte
*readbuf
,
1164 const gdb_byte
*writebuf
)
1166 /* The psABI says that "...every stack frame reserves the word at
1167 %fp+64. If a function returns a structure, union, or
1168 quad-precision value, this word should hold the address of the
1169 object into which the return value should be copied." This
1170 guarantees that we can always find the return value, not just
1171 before the function returns. */
1173 if (sparc_structure_or_union_p (type
)
1174 || (sparc_floating_p (type
) && TYPE_LENGTH (type
) == 16))
1181 regcache_cooked_read_unsigned (regcache
, SPARC_SP_REGNUM
, &sp
);
1182 addr
= read_memory_unsigned_integer (sp
+ 64, 4);
1183 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
1186 return RETURN_VALUE_ABI_PRESERVES_ADDRESS
;
1190 sparc32_extract_return_value (type
, regcache
, readbuf
);
1192 sparc32_store_return_value (type
, regcache
, writebuf
);
1194 return RETURN_VALUE_REGISTER_CONVENTION
;
1198 sparc32_stabs_argument_has_addr (struct gdbarch
*gdbarch
, struct type
*type
)
1200 return (sparc_structure_or_union_p (type
)
1201 || (sparc_floating_p (type
) && TYPE_LENGTH (type
) == 16));
1205 sparc32_dwarf2_struct_return_p (struct frame_info
*next_frame
)
1207 CORE_ADDR pc
= frame_unwind_address_in_block (next_frame
, NORMAL_FRAME
);
1208 struct symbol
*sym
= find_pc_function (pc
);
1211 return sparc32_struct_return_from_sym (sym
);
1216 sparc32_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1217 struct dwarf2_frame_state_reg
*reg
,
1218 struct frame_info
*next_frame
)
1224 case SPARC_G0_REGNUM
:
1225 /* Since %g0 is always zero, there is no point in saving it, and
1226 people will be inclined omit it from the CFI. Make sure we
1227 don't warn about that. */
1228 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
1230 case SPARC_SP_REGNUM
:
1231 reg
->how
= DWARF2_FRAME_REG_CFA
;
1233 case SPARC32_PC_REGNUM
:
1234 case SPARC32_NPC_REGNUM
:
1235 reg
->how
= DWARF2_FRAME_REG_RA_OFFSET
;
1237 if (sparc32_dwarf2_struct_return_p (next_frame
))
1239 if (regnum
== SPARC32_NPC_REGNUM
)
1241 reg
->loc
.offset
= off
;
1247 /* The SPARC Architecture doesn't have hardware single-step support,
1248 and most operating systems don't implement it either, so we provide
1249 software single-step mechanism. */
1252 sparc_analyze_control_transfer (struct gdbarch
*arch
,
1253 CORE_ADDR pc
, CORE_ADDR
*npc
)
1255 unsigned long insn
= sparc_fetch_instruction (pc
);
1256 int conditional_p
= X_COND (insn
) & 0x7;
1258 long offset
= 0; /* Must be signed for sign-extend. */
1260 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 3 && (insn
& 0x1000000) == 0)
1262 /* Branch on Integer Register with Prediction (BPr). */
1266 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 6)
1268 /* Branch on Floating-Point Condition Codes (FBfcc). */
1270 offset
= 4 * X_DISP22 (insn
);
1272 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 5)
1274 /* Branch on Floating-Point Condition Codes with Prediction
1277 offset
= 4 * X_DISP19 (insn
);
1279 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 2)
1281 /* Branch on Integer Condition Codes (Bicc). */
1283 offset
= 4 * X_DISP22 (insn
);
1285 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 1)
1287 /* Branch on Integer Condition Codes with Prediction (BPcc). */
1289 offset
= 4 * X_DISP19 (insn
);
1291 else if (X_OP (insn
) == 2 && X_OP3 (insn
) == 0x3a)
1293 /* Trap instruction (TRAP). */
1294 return gdbarch_tdep (arch
)->step_trap (insn
);
1297 /* FIXME: Handle DONE and RETRY instructions. */
1303 /* For conditional branches, return nPC + 4 iff the annul
1305 return (X_A (insn
) ? *npc
+ 4 : 0);
1309 /* For unconditional branches, return the target if its
1310 specified condition is "always" and return nPC + 4 if the
1311 condition is "never". If the annul bit is 1, set *NPC to
1313 if (X_COND (insn
) == 0x0)
1314 pc
= *npc
, offset
= 4;
1318 gdb_assert (offset
!= 0);
1327 sparc_step_trap (unsigned long insn
)
1333 sparc_software_single_step (struct regcache
*regcache
)
1335 struct gdbarch
*arch
= current_gdbarch
;
1336 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
1337 CORE_ADDR npc
, nnpc
;
1339 CORE_ADDR pc
, orig_npc
;
1341 pc
= sparc_address_from_register (tdep
->pc_regnum
);
1342 orig_npc
= npc
= sparc_address_from_register (tdep
->npc_regnum
);
1344 /* Analyze the instruction at PC. */
1345 nnpc
= sparc_analyze_control_transfer (arch
, pc
, &npc
);
1347 insert_single_step_breakpoint (npc
);
1350 insert_single_step_breakpoint (nnpc
);
1352 /* Assert that we have set at least one breakpoint, and that
1353 they're not set at the same spot - unless we're going
1354 from here straight to NULL, i.e. a call or jump to 0. */
1355 gdb_assert (npc
!= 0 || nnpc
!= 0 || orig_npc
== 0);
1356 gdb_assert (nnpc
!= npc
|| orig_npc
== 0);
1362 sparc_write_pc (CORE_ADDR pc
, ptid_t ptid
)
1364 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1366 write_register_pid (tdep
->pc_regnum
, pc
, ptid
);
1367 write_register_pid (tdep
->npc_regnum
, pc
+ 4, ptid
);
1370 /* Unglobalize NAME. */
1373 sparc_stabs_unglobalize_name (char *name
)
1375 /* The Sun compilers (Sun ONE Studio, Forte Developer, Sun WorkShop,
1376 SunPRO) convert file static variables into global values, a
1377 process known as globalization. In order to do this, the
1378 compiler will create a unique prefix and prepend it to each file
1379 static variable. For static variables within a function, this
1380 globalization prefix is followed by the function name (nested
1381 static variables within a function are supposed to generate a
1382 warning message, and are left alone). The procedure is
1383 documented in the Stabs Interface Manual, which is distrubuted
1384 with the compilers, although version 4.0 of the manual seems to
1385 be incorrect in some places, at least for SPARC. The
1386 globalization prefix is encoded into an N_OPT stab, with the form
1387 "G=<prefix>". The globalization prefix always seems to start
1388 with a dollar sign '$'; a dot '.' is used as a seperator. So we
1389 simply strip everything up until the last dot. */
1393 char *p
= strrchr (name
, '.');
1402 /* Return the appropriate register set for the core section identified
1403 by SECT_NAME and SECT_SIZE. */
1405 const struct regset
*
1406 sparc_regset_from_core_section (struct gdbarch
*gdbarch
,
1407 const char *sect_name
, size_t sect_size
)
1409 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1411 if (strcmp (sect_name
, ".reg") == 0 && sect_size
>= tdep
->sizeof_gregset
)
1412 return tdep
->gregset
;
1414 if (strcmp (sect_name
, ".reg2") == 0 && sect_size
>= tdep
->sizeof_fpregset
)
1415 return tdep
->fpregset
;
1421 static struct gdbarch
*
1422 sparc32_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1424 struct gdbarch_tdep
*tdep
;
1425 struct gdbarch
*gdbarch
;
1427 /* If there is already a candidate, use it. */
1428 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
1430 return arches
->gdbarch
;
1432 /* Allocate space for the new architecture. */
1433 tdep
= XMALLOC (struct gdbarch_tdep
);
1434 gdbarch
= gdbarch_alloc (&info
, tdep
);
1436 tdep
->pc_regnum
= SPARC32_PC_REGNUM
;
1437 tdep
->npc_regnum
= SPARC32_NPC_REGNUM
;
1438 tdep
->gregset
= NULL
;
1439 tdep
->sizeof_gregset
= 0;
1440 tdep
->fpregset
= NULL
;
1441 tdep
->sizeof_fpregset
= 0;
1442 tdep
->plt_entry_size
= 0;
1443 tdep
->step_trap
= sparc_step_trap
;
1445 set_gdbarch_long_double_bit (gdbarch
, 128);
1446 set_gdbarch_long_double_format (gdbarch
, floatformats_sparc_quad
);
1448 set_gdbarch_num_regs (gdbarch
, SPARC32_NUM_REGS
);
1449 set_gdbarch_register_name (gdbarch
, sparc32_register_name
);
1450 set_gdbarch_register_type (gdbarch
, sparc32_register_type
);
1451 set_gdbarch_num_pseudo_regs (gdbarch
, SPARC32_NUM_PSEUDO_REGS
);
1452 set_gdbarch_pseudo_register_read (gdbarch
, sparc32_pseudo_register_read
);
1453 set_gdbarch_pseudo_register_write (gdbarch
, sparc32_pseudo_register_write
);
1455 /* Register numbers of various important registers. */
1456 set_gdbarch_sp_regnum (gdbarch
, SPARC_SP_REGNUM
); /* %sp */
1457 set_gdbarch_pc_regnum (gdbarch
, SPARC32_PC_REGNUM
); /* %pc */
1458 set_gdbarch_fp0_regnum (gdbarch
, SPARC_F0_REGNUM
); /* %f0 */
1460 /* Call dummy code. */
1461 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
1462 set_gdbarch_push_dummy_code (gdbarch
, sparc32_push_dummy_code
);
1463 set_gdbarch_push_dummy_call (gdbarch
, sparc32_push_dummy_call
);
1465 set_gdbarch_return_value (gdbarch
, sparc32_return_value
);
1466 set_gdbarch_stabs_argument_has_addr
1467 (gdbarch
, sparc32_stabs_argument_has_addr
);
1469 set_gdbarch_skip_prologue (gdbarch
, sparc32_skip_prologue
);
1471 /* Stack grows downward. */
1472 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
1474 set_gdbarch_breakpoint_from_pc (gdbarch
, sparc_breakpoint_from_pc
);
1476 set_gdbarch_frame_args_skip (gdbarch
, 8);
1478 set_gdbarch_print_insn (gdbarch
, print_insn_sparc
);
1480 set_gdbarch_software_single_step (gdbarch
, sparc_software_single_step
);
1481 set_gdbarch_write_pc (gdbarch
, sparc_write_pc
);
1483 set_gdbarch_unwind_dummy_id (gdbarch
, sparc_unwind_dummy_id
);
1485 set_gdbarch_unwind_pc (gdbarch
, sparc_unwind_pc
);
1487 frame_base_set_default (gdbarch
, &sparc32_frame_base
);
1489 /* Hook in the DWARF CFI frame unwinder. */
1490 dwarf2_frame_set_init_reg (gdbarch
, sparc32_dwarf2_frame_init_reg
);
1491 /* FIXME: kettenis/20050423: Don't enable the unwinder until the
1492 StackGhost issues have been resolved. */
1494 /* Hook in ABI-specific overrides, if they have been registered. */
1495 gdbarch_init_osabi (info
, gdbarch
);
1497 frame_unwind_append_sniffer (gdbarch
, sparc32_frame_sniffer
);
1499 /* If we have register sets, enable the generic core file support. */
1501 set_gdbarch_regset_from_core_section (gdbarch
,
1502 sparc_regset_from_core_section
);
1507 /* Helper functions for dealing with register windows. */
1510 sparc_supply_rwindow (struct regcache
*regcache
, CORE_ADDR sp
, int regnum
)
1518 /* Registers are 64-bit. */
1521 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1523 if (regnum
== i
|| regnum
== -1)
1525 target_read_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 8), buf
, 8);
1527 /* Handle StackGhost. */
1528 if (i
== SPARC_I7_REGNUM
)
1530 ULONGEST wcookie
= sparc_fetch_wcookie ();
1531 ULONGEST i7
= extract_unsigned_integer (buf
+ offset
, 8);
1533 store_unsigned_integer (buf
+ offset
, 8, i7
^ wcookie
);
1536 regcache_raw_supply (regcache
, i
, buf
);
1542 /* Registers are 32-bit. Toss any sign-extension of the stack
1546 /* Clear out the top half of the temporary buffer, and put the
1547 register value in the bottom half if we're in 64-bit mode. */
1548 if (gdbarch_ptr_bit (current_gdbarch
) == 64)
1554 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1556 if (regnum
== i
|| regnum
== -1)
1558 target_read_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 4),
1561 /* Handle StackGhost. */
1562 if (i
== SPARC_I7_REGNUM
)
1564 ULONGEST wcookie
= sparc_fetch_wcookie ();
1565 ULONGEST i7
= extract_unsigned_integer (buf
+ offset
, 4);
1567 store_unsigned_integer (buf
+ offset
, 4, i7
^ wcookie
);
1570 regcache_raw_supply (regcache
, i
, buf
);
1577 sparc_collect_rwindow (const struct regcache
*regcache
,
1578 CORE_ADDR sp
, int regnum
)
1586 /* Registers are 64-bit. */
1589 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1591 if (regnum
== -1 || regnum
== SPARC_SP_REGNUM
|| regnum
== i
)
1593 regcache_raw_collect (regcache
, i
, buf
);
1595 /* Handle StackGhost. */
1596 if (i
== SPARC_I7_REGNUM
)
1598 ULONGEST wcookie
= sparc_fetch_wcookie ();
1599 ULONGEST i7
= extract_unsigned_integer (buf
+ offset
, 8);
1601 store_unsigned_integer (buf
, 8, i7
^ wcookie
);
1604 target_write_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 8), buf
, 8);
1610 /* Registers are 32-bit. Toss any sign-extension of the stack
1614 /* Only use the bottom half if we're in 64-bit mode. */
1615 if (gdbarch_ptr_bit (current_gdbarch
) == 64)
1618 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1620 if (regnum
== -1 || regnum
== SPARC_SP_REGNUM
|| regnum
== i
)
1622 regcache_raw_collect (regcache
, i
, buf
);
1624 /* Handle StackGhost. */
1625 if (i
== SPARC_I7_REGNUM
)
1627 ULONGEST wcookie
= sparc_fetch_wcookie ();
1628 ULONGEST i7
= extract_unsigned_integer (buf
+ offset
, 4);
1630 store_unsigned_integer (buf
+ offset
, 4, i7
^ wcookie
);
1633 target_write_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 4),
1640 /* Helper functions for dealing with register sets. */
1643 sparc32_supply_gregset (const struct sparc_gregset
*gregset
,
1644 struct regcache
*regcache
,
1645 int regnum
, const void *gregs
)
1647 const gdb_byte
*regs
= gregs
;
1650 if (regnum
== SPARC32_PSR_REGNUM
|| regnum
== -1)
1651 regcache_raw_supply (regcache
, SPARC32_PSR_REGNUM
,
1652 regs
+ gregset
->r_psr_offset
);
1654 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== -1)
1655 regcache_raw_supply (regcache
, SPARC32_PC_REGNUM
,
1656 regs
+ gregset
->r_pc_offset
);
1658 if (regnum
== SPARC32_NPC_REGNUM
|| regnum
== -1)
1659 regcache_raw_supply (regcache
, SPARC32_NPC_REGNUM
,
1660 regs
+ gregset
->r_npc_offset
);
1662 if (regnum
== SPARC32_Y_REGNUM
|| regnum
== -1)
1663 regcache_raw_supply (regcache
, SPARC32_Y_REGNUM
,
1664 regs
+ gregset
->r_y_offset
);
1666 if (regnum
== SPARC_G0_REGNUM
|| regnum
== -1)
1667 regcache_raw_supply (regcache
, SPARC_G0_REGNUM
, NULL
);
1669 if ((regnum
>= SPARC_G1_REGNUM
&& regnum
<= SPARC_O7_REGNUM
) || regnum
== -1)
1671 int offset
= gregset
->r_g1_offset
;
1673 for (i
= SPARC_G1_REGNUM
; i
<= SPARC_O7_REGNUM
; i
++)
1675 if (regnum
== i
|| regnum
== -1)
1676 regcache_raw_supply (regcache
, i
, regs
+ offset
);
1681 if ((regnum
>= SPARC_L0_REGNUM
&& regnum
<= SPARC_I7_REGNUM
) || regnum
== -1)
1683 /* Not all of the register set variants include Locals and
1684 Inputs. For those that don't, we read them off the stack. */
1685 if (gregset
->r_l0_offset
== -1)
1689 regcache_cooked_read_unsigned (regcache
, SPARC_SP_REGNUM
, &sp
);
1690 sparc_supply_rwindow (regcache
, sp
, regnum
);
1694 int offset
= gregset
->r_l0_offset
;
1696 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1698 if (regnum
== i
|| regnum
== -1)
1699 regcache_raw_supply (regcache
, i
, regs
+ offset
);
1707 sparc32_collect_gregset (const struct sparc_gregset
*gregset
,
1708 const struct regcache
*regcache
,
1709 int regnum
, void *gregs
)
1711 gdb_byte
*regs
= gregs
;
1714 if (regnum
== SPARC32_PSR_REGNUM
|| regnum
== -1)
1715 regcache_raw_collect (regcache
, SPARC32_PSR_REGNUM
,
1716 regs
+ gregset
->r_psr_offset
);
1718 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== -1)
1719 regcache_raw_collect (regcache
, SPARC32_PC_REGNUM
,
1720 regs
+ gregset
->r_pc_offset
);
1722 if (regnum
== SPARC32_NPC_REGNUM
|| regnum
== -1)
1723 regcache_raw_collect (regcache
, SPARC32_NPC_REGNUM
,
1724 regs
+ gregset
->r_npc_offset
);
1726 if (regnum
== SPARC32_Y_REGNUM
|| regnum
== -1)
1727 regcache_raw_collect (regcache
, SPARC32_Y_REGNUM
,
1728 regs
+ gregset
->r_y_offset
);
1730 if ((regnum
>= SPARC_G1_REGNUM
&& regnum
<= SPARC_O7_REGNUM
) || regnum
== -1)
1732 int offset
= gregset
->r_g1_offset
;
1734 /* %g0 is always zero. */
1735 for (i
= SPARC_G1_REGNUM
; i
<= SPARC_O7_REGNUM
; i
++)
1737 if (regnum
== i
|| regnum
== -1)
1738 regcache_raw_collect (regcache
, i
, regs
+ offset
);
1743 if ((regnum
>= SPARC_L0_REGNUM
&& regnum
<= SPARC_I7_REGNUM
) || regnum
== -1)
1745 /* Not all of the register set variants include Locals and
1746 Inputs. For those that don't, we read them off the stack. */
1747 if (gregset
->r_l0_offset
!= -1)
1749 int offset
= gregset
->r_l0_offset
;
1751 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1753 if (regnum
== i
|| regnum
== -1)
1754 regcache_raw_collect (regcache
, i
, regs
+ offset
);
1762 sparc32_supply_fpregset (struct regcache
*regcache
,
1763 int regnum
, const void *fpregs
)
1765 const gdb_byte
*regs
= fpregs
;
1768 for (i
= 0; i
< 32; i
++)
1770 if (regnum
== (SPARC_F0_REGNUM
+ i
) || regnum
== -1)
1771 regcache_raw_supply (regcache
, SPARC_F0_REGNUM
+ i
, regs
+ (i
* 4));
1774 if (regnum
== SPARC32_FSR_REGNUM
|| regnum
== -1)
1775 regcache_raw_supply (regcache
, SPARC32_FSR_REGNUM
, regs
+ (32 * 4) + 4);
1779 sparc32_collect_fpregset (const struct regcache
*regcache
,
1780 int regnum
, void *fpregs
)
1782 gdb_byte
*regs
= fpregs
;
1785 for (i
= 0; i
< 32; i
++)
1787 if (regnum
== (SPARC_F0_REGNUM
+ i
) || regnum
== -1)
1788 regcache_raw_collect (regcache
, SPARC_F0_REGNUM
+ i
, regs
+ (i
* 4));
1791 if (regnum
== SPARC32_FSR_REGNUM
|| regnum
== -1)
1792 regcache_raw_collect (regcache
, SPARC32_FSR_REGNUM
, regs
+ (32 * 4) + 4);
1798 /* From <machine/reg.h>. */
1799 const struct sparc_gregset sparc32_sunos4_gregset
=
1812 /* Provide a prototype to silence -Wmissing-prototypes. */
1813 void _initialize_sparc_tdep (void);
1816 _initialize_sparc_tdep (void)
1818 register_gdbarch_init (bfd_arch_sparc
, sparc32_gdbarch_init
);
1820 /* Initialize the SPARC-specific register types. */