1 /* Target-dependent code for SPARC.
3 Copyright (C) 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include "arch-utils.h"
24 #include "dwarf2-frame.h"
25 #include "floatformat.h"
27 #include "frame-base.h"
28 #include "frame-unwind.h"
39 #include "gdb_assert.h"
40 #include "gdb_string.h"
42 #include "sparc-tdep.h"
46 /* This file implements the SPARC 32-bit ABI as defined by the section
47 "Low-Level System Information" of the SPARC Compliance Definition
48 (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC. The SCD
49 lists changes with respect to the original 32-bit psABI as defined
50 in the "System V ABI, SPARC Processor Supplement".
52 Note that if we talk about SunOS, we mean SunOS 4.x, which was
53 BSD-based, which is sometimes (retroactively?) referred to as
54 Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and
55 above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9
56 suffering from severe version number inflation). Solaris 2.x is
57 also known as SunOS 5.x, since that's what uname(1) says. Solaris
60 /* Please use the sparc32_-prefix for 32-bit specific code, the
61 sparc64_-prefix for 64-bit specific code and the sparc_-prefix for
62 code that can handle both. The 64-bit specific code lives in
63 sparc64-tdep.c; don't add any here. */
65 /* The SPARC Floating-Point Quad-Precision format is similar to
66 big-endian IA-64 Quad-Precision format. */
67 #define floatformats_sparc_quad floatformats_ia64_quad
69 /* The stack pointer is offset from the stack frame by a BIAS of 2047
70 (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC
71 hosts, so undefine it first. */
75 /* Macros to extract fields from SPARC instructions. */
76 #define X_OP(i) (((i) >> 30) & 0x3)
77 #define X_RD(i) (((i) >> 25) & 0x1f)
78 #define X_A(i) (((i) >> 29) & 1)
79 #define X_COND(i) (((i) >> 25) & 0xf)
80 #define X_OP2(i) (((i) >> 22) & 0x7)
81 #define X_IMM22(i) ((i) & 0x3fffff)
82 #define X_OP3(i) (((i) >> 19) & 0x3f)
83 #define X_RS1(i) (((i) >> 14) & 0x1f)
84 #define X_RS2(i) ((i) & 0x1f)
85 #define X_I(i) (((i) >> 13) & 1)
86 /* Sign extension macros. */
87 #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000)
88 #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000)
89 #define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000)
91 /* Fetch the instruction at PC. Instructions are always big-endian
92 even if the processor operates in little-endian mode. */
95 sparc_fetch_instruction (CORE_ADDR pc
)
101 /* If we can't read the instruction at PC, return zero. */
102 if (target_read_memory (pc
, buf
, sizeof (buf
)))
106 for (i
= 0; i
< sizeof (buf
); i
++)
107 insn
= (insn
<< 8) | buf
[i
];
112 /* Return non-zero if the instruction corresponding to PC is an "unimp"
116 sparc_is_unimp_insn (CORE_ADDR pc
)
118 const unsigned long insn
= sparc_fetch_instruction (pc
);
120 return ((insn
& 0xc1c00000) == 0);
123 /* OpenBSD/sparc includes StackGhost, which according to the author's
124 website http://stackghost.cerias.purdue.edu "... transparently and
125 automatically protects applications' stack frames; more
126 specifically, it guards the return pointers. The protection
127 mechanisms require no application source or binary modification and
128 imposes only a negligible performance penalty."
130 The same website provides the following description of how
133 "StackGhost interfaces with the kernel trap handler that would
134 normally write out registers to the stack and the handler that
135 would read them back in. By XORing a cookie into the
136 return-address saved in the user stack when it is actually written
137 to the stack, and then XOR it out when the return-address is pulled
138 from the stack, StackGhost can cause attacker corrupted return
139 pointers to behave in a manner the attacker cannot predict.
140 StackGhost can also use several unused bits in the return pointer
141 to detect a smashed return pointer and abort the process."
143 For GDB this means that whenever we're reading %i7 from a stack
144 frame's window save area, we'll have to XOR the cookie.
146 More information on StackGuard can be found on in:
148 Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated
149 Stack Protection." 2001. Published in USENIX Security Symposium
152 /* Fetch StackGhost Per-Process XOR cookie. */
155 sparc_fetch_wcookie (struct gdbarch
*gdbarch
)
157 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
158 struct target_ops
*ops
= ¤t_target
;
162 len
= target_read (ops
, TARGET_OBJECT_WCOOKIE
, NULL
, buf
, 0, 8);
166 /* We should have either an 32-bit or an 64-bit cookie. */
167 gdb_assert (len
== 4 || len
== 8);
169 return extract_unsigned_integer (buf
, len
, byte_order
);
173 /* The functions on this page are intended to be used to classify
174 function arguments. */
176 /* Check whether TYPE is "Integral or Pointer". */
179 sparc_integral_or_pointer_p (const struct type
*type
)
181 int len
= TYPE_LENGTH (type
);
183 switch (TYPE_CODE (type
))
189 case TYPE_CODE_RANGE
:
190 /* We have byte, half-word, word and extended-word/doubleword
191 integral types. The doubleword is an extension to the
192 original 32-bit ABI by the SCD 2.4.x. */
193 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
196 /* Allow either 32-bit or 64-bit pointers. */
197 return (len
== 4 || len
== 8);
205 /* Check whether TYPE is "Floating". */
208 sparc_floating_p (const struct type
*type
)
210 switch (TYPE_CODE (type
))
214 int len
= TYPE_LENGTH (type
);
215 return (len
== 4 || len
== 8 || len
== 16);
224 /* Check whether TYPE is "Structure or Union".
226 In terms of Ada subprogram calls, arrays are treated the same as
227 struct and union types. So this function also returns non-zero
231 sparc_structure_or_union_p (const struct type
*type
)
233 switch (TYPE_CODE (type
))
235 case TYPE_CODE_STRUCT
:
236 case TYPE_CODE_UNION
:
237 case TYPE_CODE_ARRAY
:
246 /* Register information. */
248 static const char *sparc32_register_names
[] =
250 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
251 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
252 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
253 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
255 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
256 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
257 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
258 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
260 "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr"
263 /* Total number of registers. */
264 #define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names)
266 /* We provide the aliases %d0..%d30 for the floating registers as
267 "psuedo" registers. */
269 static const char *sparc32_pseudo_register_names
[] =
271 "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14",
272 "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30"
275 /* Total number of pseudo registers. */
276 #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names)
278 /* Return the name of register REGNUM. */
281 sparc32_register_name (struct gdbarch
*gdbarch
, int regnum
)
283 if (regnum
>= 0 && regnum
< SPARC32_NUM_REGS
)
284 return sparc32_register_names
[regnum
];
286 if (regnum
< SPARC32_NUM_REGS
+ SPARC32_NUM_PSEUDO_REGS
)
287 return sparc32_pseudo_register_names
[regnum
- SPARC32_NUM_REGS
];
292 /* Construct types for ISA-specific registers. */
295 sparc_psr_type (struct gdbarch
*gdbarch
)
297 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
299 if (!tdep
->sparc_psr_type
)
303 type
= arch_flags_type (gdbarch
, "builtin_type_sparc_psr", 4);
304 append_flags_type_flag (type
, 5, "ET");
305 append_flags_type_flag (type
, 6, "PS");
306 append_flags_type_flag (type
, 7, "S");
307 append_flags_type_flag (type
, 12, "EF");
308 append_flags_type_flag (type
, 13, "EC");
310 tdep
->sparc_psr_type
= type
;
313 return tdep
->sparc_psr_type
;
317 sparc_fsr_type (struct gdbarch
*gdbarch
)
319 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
321 if (!tdep
->sparc_fsr_type
)
325 type
= arch_flags_type (gdbarch
, "builtin_type_sparc_fsr", 4);
326 append_flags_type_flag (type
, 0, "NXA");
327 append_flags_type_flag (type
, 1, "DZA");
328 append_flags_type_flag (type
, 2, "UFA");
329 append_flags_type_flag (type
, 3, "OFA");
330 append_flags_type_flag (type
, 4, "NVA");
331 append_flags_type_flag (type
, 5, "NXC");
332 append_flags_type_flag (type
, 6, "DZC");
333 append_flags_type_flag (type
, 7, "UFC");
334 append_flags_type_flag (type
, 8, "OFC");
335 append_flags_type_flag (type
, 9, "NVC");
336 append_flags_type_flag (type
, 22, "NS");
337 append_flags_type_flag (type
, 23, "NXM");
338 append_flags_type_flag (type
, 24, "DZM");
339 append_flags_type_flag (type
, 25, "UFM");
340 append_flags_type_flag (type
, 26, "OFM");
341 append_flags_type_flag (type
, 27, "NVM");
343 tdep
->sparc_fsr_type
= type
;
346 return tdep
->sparc_fsr_type
;
349 /* Return the GDB type object for the "standard" data type of data in
353 sparc32_register_type (struct gdbarch
*gdbarch
, int regnum
)
355 if (regnum
>= SPARC_F0_REGNUM
&& regnum
<= SPARC_F31_REGNUM
)
356 return builtin_type (gdbarch
)->builtin_float
;
358 if (regnum
>= SPARC32_D0_REGNUM
&& regnum
<= SPARC32_D30_REGNUM
)
359 return builtin_type (gdbarch
)->builtin_double
;
361 if (regnum
== SPARC_SP_REGNUM
|| regnum
== SPARC_FP_REGNUM
)
362 return builtin_type (gdbarch
)->builtin_data_ptr
;
364 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== SPARC32_NPC_REGNUM
)
365 return builtin_type (gdbarch
)->builtin_func_ptr
;
367 if (regnum
== SPARC32_PSR_REGNUM
)
368 return sparc_psr_type (gdbarch
);
370 if (regnum
== SPARC32_FSR_REGNUM
)
371 return sparc_fsr_type (gdbarch
);
373 return builtin_type (gdbarch
)->builtin_int32
;
376 static enum register_status
377 sparc32_pseudo_register_read (struct gdbarch
*gdbarch
,
378 struct regcache
*regcache
,
379 int regnum
, gdb_byte
*buf
)
381 enum register_status status
;
383 gdb_assert (regnum
>= SPARC32_D0_REGNUM
&& regnum
<= SPARC32_D30_REGNUM
);
385 regnum
= SPARC_F0_REGNUM
+ 2 * (regnum
- SPARC32_D0_REGNUM
);
386 status
= regcache_raw_read (regcache
, regnum
, buf
);
387 if (status
== REG_VALID
)
388 status
= regcache_raw_read (regcache
, regnum
+ 1, buf
+ 4);
393 sparc32_pseudo_register_write (struct gdbarch
*gdbarch
,
394 struct regcache
*regcache
,
395 int regnum
, const gdb_byte
*buf
)
397 gdb_assert (regnum
>= SPARC32_D0_REGNUM
&& regnum
<= SPARC32_D30_REGNUM
);
399 regnum
= SPARC_F0_REGNUM
+ 2 * (regnum
- SPARC32_D0_REGNUM
);
400 regcache_raw_write (regcache
, regnum
, buf
);
401 regcache_raw_write (regcache
, regnum
+ 1, buf
+ 4);
406 sparc32_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR address
)
408 /* The ABI requires double-word alignment. */
409 return address
& ~0x7;
413 sparc32_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
415 struct value
**args
, int nargs
,
416 struct type
*value_type
,
417 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
418 struct regcache
*regcache
)
420 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
425 if (using_struct_return (gdbarch
, NULL
, value_type
))
429 /* This is an UNIMP instruction. */
430 store_unsigned_integer (buf
, 4, byte_order
,
431 TYPE_LENGTH (value_type
) & 0x1fff);
432 write_memory (sp
- 8, buf
, 4);
440 sparc32_store_arguments (struct regcache
*regcache
, int nargs
,
441 struct value
**args
, CORE_ADDR sp
,
442 int struct_return
, CORE_ADDR struct_addr
)
444 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
445 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
446 /* Number of words in the "parameter array". */
447 int num_elements
= 0;
451 for (i
= 0; i
< nargs
; i
++)
453 struct type
*type
= value_type (args
[i
]);
454 int len
= TYPE_LENGTH (type
);
456 if (sparc_structure_or_union_p (type
)
457 || (sparc_floating_p (type
) && len
== 16))
459 /* Structure, Union and Quad-Precision Arguments. */
462 /* Use doubleword alignment for these values. That's always
463 correct, and wasting a few bytes shouldn't be a problem. */
466 write_memory (sp
, value_contents (args
[i
]), len
);
467 args
[i
] = value_from_pointer (lookup_pointer_type (type
), sp
);
470 else if (sparc_floating_p (type
))
472 /* Floating arguments. */
473 gdb_assert (len
== 4 || len
== 8);
474 num_elements
+= (len
/ 4);
478 /* Integral and pointer arguments. */
479 gdb_assert (sparc_integral_or_pointer_p (type
));
482 args
[i
] = value_cast (builtin_type (gdbarch
)->builtin_int32
,
484 num_elements
+= ((len
+ 3) / 4);
488 /* Always allocate at least six words. */
489 sp
-= max (6, num_elements
) * 4;
491 /* The psABI says that "Software convention requires space for the
492 struct/union return value pointer, even if the word is unused." */
495 /* The psABI says that "Although software convention and the
496 operating system require every stack frame to be doubleword
500 for (i
= 0; i
< nargs
; i
++)
502 const bfd_byte
*valbuf
= value_contents (args
[i
]);
503 struct type
*type
= value_type (args
[i
]);
504 int len
= TYPE_LENGTH (type
);
506 gdb_assert (len
== 4 || len
== 8);
510 int regnum
= SPARC_O0_REGNUM
+ element
;
512 regcache_cooked_write (regcache
, regnum
, valbuf
);
513 if (len
> 4 && element
< 5)
514 regcache_cooked_write (regcache
, regnum
+ 1, valbuf
+ 4);
517 /* Always store the argument in memory. */
518 write_memory (sp
+ 4 + element
* 4, valbuf
, len
);
522 gdb_assert (element
== num_elements
);
528 store_unsigned_integer (buf
, 4, byte_order
, struct_addr
);
529 write_memory (sp
, buf
, 4);
536 sparc32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
537 struct regcache
*regcache
, CORE_ADDR bp_addr
,
538 int nargs
, struct value
**args
, CORE_ADDR sp
,
539 int struct_return
, CORE_ADDR struct_addr
)
541 CORE_ADDR call_pc
= (struct_return
? (bp_addr
- 12) : (bp_addr
- 8));
543 /* Set return address. */
544 regcache_cooked_write_unsigned (regcache
, SPARC_O7_REGNUM
, call_pc
);
546 /* Set up function arguments. */
547 sp
= sparc32_store_arguments (regcache
, nargs
, args
, sp
,
548 struct_return
, struct_addr
);
550 /* Allocate the 16-word window save area. */
553 /* Stack should be doubleword aligned at this point. */
554 gdb_assert (sp
% 8 == 0);
556 /* Finally, update the stack pointer. */
557 regcache_cooked_write_unsigned (regcache
, SPARC_SP_REGNUM
, sp
);
563 /* Use the program counter to determine the contents and size of a
564 breakpoint instruction. Return a pointer to a string of bytes that
565 encode a breakpoint instruction, store the length of the string in
566 *LEN and optionally adjust *PC to point to the correct memory
567 location for inserting the breakpoint. */
569 static const gdb_byte
*
570 sparc_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pc
, int *len
)
572 static const gdb_byte break_insn
[] = { 0x91, 0xd0, 0x20, 0x01 };
574 *len
= sizeof (break_insn
);
579 /* Allocate and initialize a frame cache. */
581 static struct sparc_frame_cache
*
582 sparc_alloc_frame_cache (void)
584 struct sparc_frame_cache
*cache
;
587 cache
= FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache
);
593 /* Frameless until proven otherwise. */
594 cache
->frameless_p
= 1;
596 cache
->struct_return_p
= 0;
601 /* GCC generates several well-known sequences of instructions at the begining
602 of each function prologue when compiling with -fstack-check. If one of
603 such sequences starts at START_PC, then return the address of the
604 instruction immediately past this sequence. Otherwise, return START_PC. */
607 sparc_skip_stack_check (const CORE_ADDR start_pc
)
609 CORE_ADDR pc
= start_pc
;
611 int offset_stack_checking_sequence
= 0;
613 /* With GCC, all stack checking sequences begin with the same two
616 /* sethi <some immediate>,%g1 */
617 insn
= sparc_fetch_instruction (pc
);
619 if (!(X_OP (insn
) == 0 && X_OP2 (insn
) == 0x4 && X_RD (insn
) == 1))
622 /* sub %sp, %g1, %g1 */
623 insn
= sparc_fetch_instruction (pc
);
625 if (!(X_OP (insn
) == 2 && X_OP3 (insn
) == 0x4 && !X_I(insn
)
626 && X_RD (insn
) == 1 && X_RS1 (insn
) == 14 && X_RS2 (insn
) == 1))
629 insn
= sparc_fetch_instruction (pc
);
632 /* First possible sequence:
633 [first two instructions above]
634 clr [%g1 - some immediate] */
636 /* clr [%g1 - some immediate] */
637 if (X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && X_I(insn
)
638 && X_RS1 (insn
) == 1 && X_RD (insn
) == 0)
640 /* Valid stack-check sequence, return the new PC. */
644 /* Second possible sequence: A small number of probes.
645 [first two instructions above]
647 add %g1, -<some immediate>, %g1
649 [repeat the two instructions above any (small) number of times]
650 clr [%g1 - some immediate] */
653 else if (X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && !X_I(insn
)
654 && X_RS1 (insn
) == 1 && X_RD (insn
) == 0)
658 /* add %g1, -<some immediate>, %g1 */
659 insn
= sparc_fetch_instruction (pc
);
661 if (!(X_OP (insn
) == 2 && X_OP3(insn
) == 0 && X_I(insn
)
662 && X_RS1 (insn
) == 1 && X_RD (insn
) == 1))
666 insn
= sparc_fetch_instruction (pc
);
668 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && !X_I(insn
)
669 && X_RD (insn
) == 0 && X_RS1 (insn
) == 1))
673 /* clr [%g1 - some immediate] */
674 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && X_I(insn
)
675 && X_RS1 (insn
) == 1 && X_RD (insn
) == 0))
678 /* We found a valid stack-check sequence, return the new PC. */
682 /* Third sequence: A probing loop.
683 [first two instructions above]
684 sethi <some immediate>, %g4
688 add %g1, -<some immediate>, %g1
691 clr [%g4 - some immediate] */
693 /* sethi <some immediate>, %g4 */
694 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 0x4 && X_RD (insn
) == 4)
696 /* sub %g1, %g4, %g4 */
697 insn
= sparc_fetch_instruction (pc
);
699 if (!(X_OP (insn
) == 2 && X_OP3 (insn
) == 0x4 && !X_I(insn
)
700 && X_RD (insn
) == 4 && X_RS1 (insn
) == 1 && X_RS2 (insn
) == 4))
704 insn
= sparc_fetch_instruction (pc
);
706 if (!(X_OP (insn
) == 2 && X_OP3 (insn
) == 0x14 && !X_I(insn
)
707 && X_RD (insn
) == 0 && X_RS1 (insn
) == 1 && X_RS2 (insn
) == 4))
711 insn
= sparc_fetch_instruction (pc
);
713 if (!(X_OP (insn
) == 0 && X_COND (insn
) == 0x1))
716 /* add %g1, -<some immediate>, %g1 */
717 insn
= sparc_fetch_instruction (pc
);
719 if (!(X_OP (insn
) == 2 && X_OP3(insn
) == 0 && X_I(insn
)
720 && X_RS1 (insn
) == 1 && X_RD (insn
) == 1))
724 insn
= sparc_fetch_instruction (pc
);
726 if (!(X_OP (insn
) == 0 && X_COND (insn
) == 0x8))
730 insn
= sparc_fetch_instruction (pc
);
732 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && !X_I(insn
)
733 && X_RD (insn
) == 0 && X_RS1 (insn
) == 1))
736 /* clr [%g4 - some immediate] */
737 insn
= sparc_fetch_instruction (pc
);
739 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && X_I(insn
)
740 && X_RS1 (insn
) == 4 && X_RD (insn
) == 0))
743 /* We found a valid stack-check sequence, return the new PC. */
747 /* No stack check code in our prologue, return the start_pc. */
752 sparc_analyze_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
753 CORE_ADDR current_pc
, struct sparc_frame_cache
*cache
)
755 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
760 pc
= sparc_skip_stack_check (pc
);
762 if (current_pc
<= pc
)
765 /* We have to handle to "Procedure Linkage Table" (PLT) special. On
766 SPARC the linker usually defines a symbol (typically
767 _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section.
768 This symbol makes us end up here with PC pointing at the start of
769 the PLT and CURRENT_PC probably pointing at a PLT entry. If we
770 would do our normal prologue analysis, we would probably conclude
771 that we've got a frame when in reality we don't, since the
772 dynamic linker patches up the first PLT with some code that
773 starts with a SAVE instruction. Patch up PC such that it points
774 at the start of our PLT entry. */
775 if (tdep
->plt_entry_size
> 0 && in_plt_section (current_pc
, NULL
))
776 pc
= current_pc
- ((current_pc
- pc
) % tdep
->plt_entry_size
);
778 insn
= sparc_fetch_instruction (pc
);
780 /* Recognize a SETHI insn and record its destination. */
781 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 0x04)
786 insn
= sparc_fetch_instruction (pc
+ 4);
789 /* Allow for an arithmetic operation on DEST or %g1. */
790 if (X_OP (insn
) == 2 && X_I (insn
)
791 && (X_RD (insn
) == 1 || X_RD (insn
) == dest
))
795 insn
= sparc_fetch_instruction (pc
+ 8);
798 /* Check for the SAVE instruction that sets up the frame. */
799 if (X_OP (insn
) == 2 && X_OP3 (insn
) == 0x3c)
801 cache
->frameless_p
= 0;
802 return pc
+ offset
+ 4;
809 sparc_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
811 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
812 return frame_unwind_register_unsigned (this_frame
, tdep
->pc_regnum
);
815 /* Return PC of first real instruction of the function starting at
819 sparc32_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
821 struct symtab_and_line sal
;
822 CORE_ADDR func_start
, func_end
;
823 struct sparc_frame_cache cache
;
825 /* This is the preferred method, find the end of the prologue by
826 using the debugging information. */
827 if (find_pc_partial_function (start_pc
, NULL
, &func_start
, &func_end
))
829 sal
= find_pc_line (func_start
, 0);
831 if (sal
.end
< func_end
832 && start_pc
<= sal
.end
)
836 start_pc
= sparc_analyze_prologue (gdbarch
, start_pc
, 0xffffffffUL
, &cache
);
838 /* The psABI says that "Although the first 6 words of arguments
839 reside in registers, the standard stack frame reserves space for
840 them.". It also suggests that a function may use that space to
841 "write incoming arguments 0 to 5" into that space, and that's
842 indeed what GCC seems to be doing. In that case GCC will
843 generate debug information that points to the stack slots instead
844 of the registers, so we should consider the instructions that
845 write out these incoming arguments onto the stack. Of course we
846 only need to do this if we have a stack frame. */
848 while (!cache
.frameless_p
)
850 unsigned long insn
= sparc_fetch_instruction (start_pc
);
852 /* Recognize instructions that store incoming arguments in
853 %i0...%i5 into the corresponding stack slot. */
854 if (X_OP (insn
) == 3 && (X_OP3 (insn
) & 0x3c) == 0x04 && X_I (insn
)
855 && (X_RD (insn
) >= 24 && X_RD (insn
) <= 29) && X_RS1 (insn
) == 30
856 && X_SIMM13 (insn
) == 68 + (X_RD (insn
) - 24) * 4)
870 struct sparc_frame_cache
*
871 sparc_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
873 struct sparc_frame_cache
*cache
;
878 cache
= sparc_alloc_frame_cache ();
881 cache
->pc
= get_frame_func (this_frame
);
883 sparc_analyze_prologue (get_frame_arch (this_frame
), cache
->pc
,
884 get_frame_pc (this_frame
), cache
);
886 if (cache
->frameless_p
)
888 /* This function is frameless, so %fp (%i6) holds the frame
889 pointer for our calling frame. Use %sp (%o6) as this frame's
892 get_frame_register_unsigned (this_frame
, SPARC_SP_REGNUM
);
896 /* For normal frames, %fp (%i6) holds the frame pointer, the
897 base address for the current stack frame. */
899 get_frame_register_unsigned (this_frame
, SPARC_FP_REGNUM
);
909 sparc32_struct_return_from_sym (struct symbol
*sym
)
911 struct type
*type
= check_typedef (SYMBOL_TYPE (sym
));
912 enum type_code code
= TYPE_CODE (type
);
914 if (code
== TYPE_CODE_FUNC
|| code
== TYPE_CODE_METHOD
)
916 type
= check_typedef (TYPE_TARGET_TYPE (type
));
917 if (sparc_structure_or_union_p (type
)
918 || (sparc_floating_p (type
) && TYPE_LENGTH (type
) == 16))
925 struct sparc_frame_cache
*
926 sparc32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
928 struct sparc_frame_cache
*cache
;
934 cache
= sparc_frame_cache (this_frame
, this_cache
);
936 sym
= find_pc_function (cache
->pc
);
939 cache
->struct_return_p
= sparc32_struct_return_from_sym (sym
);
943 /* There is no debugging information for this function to
944 help us determine whether this function returns a struct
945 or not. So we rely on another heuristic which is to check
946 the instruction at the return address and see if this is
947 an "unimp" instruction. If it is, then it is a struct-return
950 int regnum
= cache
->frameless_p
? SPARC_O7_REGNUM
: SPARC_I7_REGNUM
;
952 pc
= get_frame_register_unsigned (this_frame
, regnum
) + 8;
953 if (sparc_is_unimp_insn (pc
))
954 cache
->struct_return_p
= 1;
961 sparc32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
962 struct frame_id
*this_id
)
964 struct sparc_frame_cache
*cache
=
965 sparc32_frame_cache (this_frame
, this_cache
);
967 /* This marks the outermost frame. */
968 if (cache
->base
== 0)
971 (*this_id
) = frame_id_build (cache
->base
, cache
->pc
);
974 static struct value
*
975 sparc32_frame_prev_register (struct frame_info
*this_frame
,
976 void **this_cache
, int regnum
)
978 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
979 struct sparc_frame_cache
*cache
=
980 sparc32_frame_cache (this_frame
, this_cache
);
982 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== SPARC32_NPC_REGNUM
)
984 CORE_ADDR pc
= (regnum
== SPARC32_NPC_REGNUM
) ? 4 : 0;
986 /* If this functions has a Structure, Union or Quad-Precision
987 return value, we have to skip the UNIMP instruction that encodes
988 the size of the structure. */
989 if (cache
->struct_return_p
)
992 regnum
= cache
->frameless_p
? SPARC_O7_REGNUM
: SPARC_I7_REGNUM
;
993 pc
+= get_frame_register_unsigned (this_frame
, regnum
) + 8;
994 return frame_unwind_got_constant (this_frame
, regnum
, pc
);
997 /* Handle StackGhost. */
999 ULONGEST wcookie
= sparc_fetch_wcookie (gdbarch
);
1001 if (wcookie
!= 0 && !cache
->frameless_p
&& regnum
== SPARC_I7_REGNUM
)
1003 CORE_ADDR addr
= cache
->base
+ (regnum
- SPARC_L0_REGNUM
) * 4;
1006 /* Read the value in from memory. */
1007 i7
= get_frame_memory_unsigned (this_frame
, addr
, 4);
1008 return frame_unwind_got_constant (this_frame
, regnum
, i7
^ wcookie
);
1012 /* The previous frame's `local' and `in' registers have been saved
1013 in the register save area. */
1014 if (!cache
->frameless_p
1015 && regnum
>= SPARC_L0_REGNUM
&& regnum
<= SPARC_I7_REGNUM
)
1017 CORE_ADDR addr
= cache
->base
+ (regnum
- SPARC_L0_REGNUM
) * 4;
1019 return frame_unwind_got_memory (this_frame
, regnum
, addr
);
1022 /* The previous frame's `out' registers are accessible as the
1023 current frame's `in' registers. */
1024 if (!cache
->frameless_p
1025 && regnum
>= SPARC_O0_REGNUM
&& regnum
<= SPARC_O7_REGNUM
)
1026 regnum
+= (SPARC_I0_REGNUM
- SPARC_O0_REGNUM
);
1028 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1031 static const struct frame_unwind sparc32_frame_unwind
=
1034 default_frame_unwind_stop_reason
,
1035 sparc32_frame_this_id
,
1036 sparc32_frame_prev_register
,
1038 default_frame_sniffer
1043 sparc32_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
1045 struct sparc_frame_cache
*cache
=
1046 sparc32_frame_cache (this_frame
, this_cache
);
1051 static const struct frame_base sparc32_frame_base
=
1053 &sparc32_frame_unwind
,
1054 sparc32_frame_base_address
,
1055 sparc32_frame_base_address
,
1056 sparc32_frame_base_address
1059 static struct frame_id
1060 sparc_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1064 sp
= get_frame_register_unsigned (this_frame
, SPARC_SP_REGNUM
);
1067 return frame_id_build (sp
, get_frame_pc (this_frame
));
1071 /* Extract a function return value of TYPE from REGCACHE, and copy
1072 that into VALBUF. */
1075 sparc32_extract_return_value (struct type
*type
, struct regcache
*regcache
,
1078 int len
= TYPE_LENGTH (type
);
1081 gdb_assert (!sparc_structure_or_union_p (type
));
1082 gdb_assert (!(sparc_floating_p (type
) && len
== 16));
1084 if (sparc_floating_p (type
))
1086 /* Floating return values. */
1087 regcache_cooked_read (regcache
, SPARC_F0_REGNUM
, buf
);
1089 regcache_cooked_read (regcache
, SPARC_F1_REGNUM
, buf
+ 4);
1090 memcpy (valbuf
, buf
, len
);
1094 /* Integral and pointer return values. */
1095 gdb_assert (sparc_integral_or_pointer_p (type
));
1097 regcache_cooked_read (regcache
, SPARC_O0_REGNUM
, buf
);
1100 regcache_cooked_read (regcache
, SPARC_O1_REGNUM
, buf
+ 4);
1101 gdb_assert (len
== 8);
1102 memcpy (valbuf
, buf
, 8);
1106 /* Just stripping off any unused bytes should preserve the
1107 signed-ness just fine. */
1108 memcpy (valbuf
, buf
+ 4 - len
, len
);
1113 /* Store the function return value of type TYPE from VALBUF into
1117 sparc32_store_return_value (struct type
*type
, struct regcache
*regcache
,
1118 const gdb_byte
*valbuf
)
1120 int len
= TYPE_LENGTH (type
);
1123 gdb_assert (!sparc_structure_or_union_p (type
));
1124 gdb_assert (!(sparc_floating_p (type
) && len
== 16));
1125 gdb_assert (len
<= 8);
1127 if (sparc_floating_p (type
))
1129 /* Floating return values. */
1130 memcpy (buf
, valbuf
, len
);
1131 regcache_cooked_write (regcache
, SPARC_F0_REGNUM
, buf
);
1133 regcache_cooked_write (regcache
, SPARC_F1_REGNUM
, buf
+ 4);
1137 /* Integral and pointer return values. */
1138 gdb_assert (sparc_integral_or_pointer_p (type
));
1142 gdb_assert (len
== 8);
1143 memcpy (buf
, valbuf
, 8);
1144 regcache_cooked_write (regcache
, SPARC_O1_REGNUM
, buf
+ 4);
1148 /* ??? Do we need to do any sign-extension here? */
1149 memcpy (buf
+ 4 - len
, valbuf
, len
);
1151 regcache_cooked_write (regcache
, SPARC_O0_REGNUM
, buf
);
1155 static enum return_value_convention
1156 sparc32_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
1157 struct type
*type
, struct regcache
*regcache
,
1158 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1160 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1162 /* The psABI says that "...every stack frame reserves the word at
1163 %fp+64. If a function returns a structure, union, or
1164 quad-precision value, this word should hold the address of the
1165 object into which the return value should be copied." This
1166 guarantees that we can always find the return value, not just
1167 before the function returns. */
1169 if (sparc_structure_or_union_p (type
)
1170 || (sparc_floating_p (type
) && TYPE_LENGTH (type
) == 16))
1177 regcache_cooked_read_unsigned (regcache
, SPARC_SP_REGNUM
, &sp
);
1178 addr
= read_memory_unsigned_integer (sp
+ 64, 4, byte_order
);
1179 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
1182 return RETURN_VALUE_ABI_PRESERVES_ADDRESS
;
1186 sparc32_extract_return_value (type
, regcache
, readbuf
);
1188 sparc32_store_return_value (type
, regcache
, writebuf
);
1190 return RETURN_VALUE_REGISTER_CONVENTION
;
1194 sparc32_stabs_argument_has_addr (struct gdbarch
*gdbarch
, struct type
*type
)
1196 return (sparc_structure_or_union_p (type
)
1197 || (sparc_floating_p (type
) && TYPE_LENGTH (type
) == 16));
1201 sparc32_dwarf2_struct_return_p (struct frame_info
*this_frame
)
1203 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
1204 struct symbol
*sym
= find_pc_function (pc
);
1207 return sparc32_struct_return_from_sym (sym
);
1212 sparc32_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1213 struct dwarf2_frame_state_reg
*reg
,
1214 struct frame_info
*this_frame
)
1220 case SPARC_G0_REGNUM
:
1221 /* Since %g0 is always zero, there is no point in saving it, and
1222 people will be inclined omit it from the CFI. Make sure we
1223 don't warn about that. */
1224 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
1226 case SPARC_SP_REGNUM
:
1227 reg
->how
= DWARF2_FRAME_REG_CFA
;
1229 case SPARC32_PC_REGNUM
:
1230 case SPARC32_NPC_REGNUM
:
1231 reg
->how
= DWARF2_FRAME_REG_RA_OFFSET
;
1233 if (sparc32_dwarf2_struct_return_p (this_frame
))
1235 if (regnum
== SPARC32_NPC_REGNUM
)
1237 reg
->loc
.offset
= off
;
1243 /* The SPARC Architecture doesn't have hardware single-step support,
1244 and most operating systems don't implement it either, so we provide
1245 software single-step mechanism. */
1248 sparc_analyze_control_transfer (struct frame_info
*frame
,
1249 CORE_ADDR pc
, CORE_ADDR
*npc
)
1251 unsigned long insn
= sparc_fetch_instruction (pc
);
1252 int conditional_p
= X_COND (insn
) & 0x7;
1254 long offset
= 0; /* Must be signed for sign-extend. */
1256 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 3 && (insn
& 0x1000000) == 0)
1258 /* Branch on Integer Register with Prediction (BPr). */
1262 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 6)
1264 /* Branch on Floating-Point Condition Codes (FBfcc). */
1266 offset
= 4 * X_DISP22 (insn
);
1268 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 5)
1270 /* Branch on Floating-Point Condition Codes with Prediction
1273 offset
= 4 * X_DISP19 (insn
);
1275 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 2)
1277 /* Branch on Integer Condition Codes (Bicc). */
1279 offset
= 4 * X_DISP22 (insn
);
1281 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 1)
1283 /* Branch on Integer Condition Codes with Prediction (BPcc). */
1285 offset
= 4 * X_DISP19 (insn
);
1287 else if (X_OP (insn
) == 2 && X_OP3 (insn
) == 0x3a)
1289 /* Trap instruction (TRAP). */
1290 return gdbarch_tdep (get_frame_arch (frame
))->step_trap (frame
, insn
);
1293 /* FIXME: Handle DONE and RETRY instructions. */
1299 /* For conditional branches, return nPC + 4 iff the annul
1301 return (X_A (insn
) ? *npc
+ 4 : 0);
1305 /* For unconditional branches, return the target if its
1306 specified condition is "always" and return nPC + 4 if the
1307 condition is "never". If the annul bit is 1, set *NPC to
1309 if (X_COND (insn
) == 0x0)
1310 pc
= *npc
, offset
= 4;
1314 gdb_assert (offset
!= 0);
1323 sparc_step_trap (struct frame_info
*frame
, unsigned long insn
)
1329 sparc_software_single_step (struct frame_info
*frame
)
1331 struct gdbarch
*arch
= get_frame_arch (frame
);
1332 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
1333 struct address_space
*aspace
= get_frame_address_space (frame
);
1334 CORE_ADDR npc
, nnpc
;
1336 CORE_ADDR pc
, orig_npc
;
1338 pc
= get_frame_register_unsigned (frame
, tdep
->pc_regnum
);
1339 orig_npc
= npc
= get_frame_register_unsigned (frame
, tdep
->npc_regnum
);
1341 /* Analyze the instruction at PC. */
1342 nnpc
= sparc_analyze_control_transfer (frame
, pc
, &npc
);
1344 insert_single_step_breakpoint (arch
, aspace
, npc
);
1347 insert_single_step_breakpoint (arch
, aspace
, nnpc
);
1349 /* Assert that we have set at least one breakpoint, and that
1350 they're not set at the same spot - unless we're going
1351 from here straight to NULL, i.e. a call or jump to 0. */
1352 gdb_assert (npc
!= 0 || nnpc
!= 0 || orig_npc
== 0);
1353 gdb_assert (nnpc
!= npc
|| orig_npc
== 0);
1359 sparc_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1361 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_regcache_arch (regcache
));
1363 regcache_cooked_write_unsigned (regcache
, tdep
->pc_regnum
, pc
);
1364 regcache_cooked_write_unsigned (regcache
, tdep
->npc_regnum
, pc
+ 4);
1368 /* Return the appropriate register set for the core section identified
1369 by SECT_NAME and SECT_SIZE. */
1371 static const struct regset
*
1372 sparc_regset_from_core_section (struct gdbarch
*gdbarch
,
1373 const char *sect_name
, size_t sect_size
)
1375 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1377 if (strcmp (sect_name
, ".reg") == 0 && sect_size
>= tdep
->sizeof_gregset
)
1378 return tdep
->gregset
;
1380 if (strcmp (sect_name
, ".reg2") == 0 && sect_size
>= tdep
->sizeof_fpregset
)
1381 return tdep
->fpregset
;
1387 static struct gdbarch
*
1388 sparc32_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1390 struct gdbarch_tdep
*tdep
;
1391 struct gdbarch
*gdbarch
;
1393 /* If there is already a candidate, use it. */
1394 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
1396 return arches
->gdbarch
;
1398 /* Allocate space for the new architecture. */
1399 tdep
= XZALLOC (struct gdbarch_tdep
);
1400 gdbarch
= gdbarch_alloc (&info
, tdep
);
1402 tdep
->pc_regnum
= SPARC32_PC_REGNUM
;
1403 tdep
->npc_regnum
= SPARC32_NPC_REGNUM
;
1404 tdep
->step_trap
= sparc_step_trap
;
1406 set_gdbarch_long_double_bit (gdbarch
, 128);
1407 set_gdbarch_long_double_format (gdbarch
, floatformats_sparc_quad
);
1409 set_gdbarch_num_regs (gdbarch
, SPARC32_NUM_REGS
);
1410 set_gdbarch_register_name (gdbarch
, sparc32_register_name
);
1411 set_gdbarch_register_type (gdbarch
, sparc32_register_type
);
1412 set_gdbarch_num_pseudo_regs (gdbarch
, SPARC32_NUM_PSEUDO_REGS
);
1413 set_gdbarch_pseudo_register_read (gdbarch
, sparc32_pseudo_register_read
);
1414 set_gdbarch_pseudo_register_write (gdbarch
, sparc32_pseudo_register_write
);
1416 /* Register numbers of various important registers. */
1417 set_gdbarch_sp_regnum (gdbarch
, SPARC_SP_REGNUM
); /* %sp */
1418 set_gdbarch_pc_regnum (gdbarch
, SPARC32_PC_REGNUM
); /* %pc */
1419 set_gdbarch_fp0_regnum (gdbarch
, SPARC_F0_REGNUM
); /* %f0 */
1421 /* Call dummy code. */
1422 set_gdbarch_frame_align (gdbarch
, sparc32_frame_align
);
1423 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
1424 set_gdbarch_push_dummy_code (gdbarch
, sparc32_push_dummy_code
);
1425 set_gdbarch_push_dummy_call (gdbarch
, sparc32_push_dummy_call
);
1427 set_gdbarch_return_value (gdbarch
, sparc32_return_value
);
1428 set_gdbarch_stabs_argument_has_addr
1429 (gdbarch
, sparc32_stabs_argument_has_addr
);
1431 set_gdbarch_skip_prologue (gdbarch
, sparc32_skip_prologue
);
1433 /* Stack grows downward. */
1434 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
1436 set_gdbarch_breakpoint_from_pc (gdbarch
, sparc_breakpoint_from_pc
);
1438 set_gdbarch_frame_args_skip (gdbarch
, 8);
1440 set_gdbarch_print_insn (gdbarch
, print_insn_sparc
);
1442 set_gdbarch_software_single_step (gdbarch
, sparc_software_single_step
);
1443 set_gdbarch_write_pc (gdbarch
, sparc_write_pc
);
1445 set_gdbarch_dummy_id (gdbarch
, sparc_dummy_id
);
1447 set_gdbarch_unwind_pc (gdbarch
, sparc_unwind_pc
);
1449 frame_base_set_default (gdbarch
, &sparc32_frame_base
);
1451 /* Hook in the DWARF CFI frame unwinder. */
1452 dwarf2_frame_set_init_reg (gdbarch
, sparc32_dwarf2_frame_init_reg
);
1453 /* FIXME: kettenis/20050423: Don't enable the unwinder until the
1454 StackGhost issues have been resolved. */
1456 /* Hook in ABI-specific overrides, if they have been registered. */
1457 gdbarch_init_osabi (info
, gdbarch
);
1459 frame_unwind_append_unwinder (gdbarch
, &sparc32_frame_unwind
);
1461 /* If we have register sets, enable the generic core file support. */
1463 set_gdbarch_regset_from_core_section (gdbarch
,
1464 sparc_regset_from_core_section
);
1469 /* Helper functions for dealing with register windows. */
1472 sparc_supply_rwindow (struct regcache
*regcache
, CORE_ADDR sp
, int regnum
)
1474 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1475 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1482 /* Registers are 64-bit. */
1485 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1487 if (regnum
== i
|| regnum
== -1)
1489 target_read_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 8), buf
, 8);
1491 /* Handle StackGhost. */
1492 if (i
== SPARC_I7_REGNUM
)
1494 ULONGEST wcookie
= sparc_fetch_wcookie (gdbarch
);
1497 i7
= extract_unsigned_integer (buf
+ offset
, 8, byte_order
);
1498 store_unsigned_integer (buf
+ offset
, 8, byte_order
,
1502 regcache_raw_supply (regcache
, i
, buf
);
1508 /* Registers are 32-bit. Toss any sign-extension of the stack
1512 /* Clear out the top half of the temporary buffer, and put the
1513 register value in the bottom half if we're in 64-bit mode. */
1514 if (gdbarch_ptr_bit (get_regcache_arch (regcache
)) == 64)
1520 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1522 if (regnum
== i
|| regnum
== -1)
1524 target_read_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 4),
1527 /* Handle StackGhost. */
1528 if (i
== SPARC_I7_REGNUM
)
1530 ULONGEST wcookie
= sparc_fetch_wcookie (gdbarch
);
1533 i7
= extract_unsigned_integer (buf
+ offset
, 4, byte_order
);
1534 store_unsigned_integer (buf
+ offset
, 4, byte_order
,
1538 regcache_raw_supply (regcache
, i
, buf
);
1545 sparc_collect_rwindow (const struct regcache
*regcache
,
1546 CORE_ADDR sp
, int regnum
)
1548 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1549 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1556 /* Registers are 64-bit. */
1559 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1561 if (regnum
== -1 || regnum
== SPARC_SP_REGNUM
|| regnum
== i
)
1563 regcache_raw_collect (regcache
, i
, buf
);
1565 /* Handle StackGhost. */
1566 if (i
== SPARC_I7_REGNUM
)
1568 ULONGEST wcookie
= sparc_fetch_wcookie (gdbarch
);
1571 i7
= extract_unsigned_integer (buf
+ offset
, 8, byte_order
);
1572 store_unsigned_integer (buf
, 8, byte_order
, i7
^ wcookie
);
1575 target_write_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 8), buf
, 8);
1581 /* Registers are 32-bit. Toss any sign-extension of the stack
1585 /* Only use the bottom half if we're in 64-bit mode. */
1586 if (gdbarch_ptr_bit (get_regcache_arch (regcache
)) == 64)
1589 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1591 if (regnum
== -1 || regnum
== SPARC_SP_REGNUM
|| regnum
== i
)
1593 regcache_raw_collect (regcache
, i
, buf
);
1595 /* Handle StackGhost. */
1596 if (i
== SPARC_I7_REGNUM
)
1598 ULONGEST wcookie
= sparc_fetch_wcookie (gdbarch
);
1601 i7
= extract_unsigned_integer (buf
+ offset
, 4, byte_order
);
1602 store_unsigned_integer (buf
+ offset
, 4, byte_order
,
1606 target_write_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 4),
1613 /* Helper functions for dealing with register sets. */
1616 sparc32_supply_gregset (const struct sparc_gregset
*gregset
,
1617 struct regcache
*regcache
,
1618 int regnum
, const void *gregs
)
1620 const gdb_byte
*regs
= gregs
;
1623 if (regnum
== SPARC32_PSR_REGNUM
|| regnum
== -1)
1624 regcache_raw_supply (regcache
, SPARC32_PSR_REGNUM
,
1625 regs
+ gregset
->r_psr_offset
);
1627 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== -1)
1628 regcache_raw_supply (regcache
, SPARC32_PC_REGNUM
,
1629 regs
+ gregset
->r_pc_offset
);
1631 if (regnum
== SPARC32_NPC_REGNUM
|| regnum
== -1)
1632 regcache_raw_supply (regcache
, SPARC32_NPC_REGNUM
,
1633 regs
+ gregset
->r_npc_offset
);
1635 if (regnum
== SPARC32_Y_REGNUM
|| regnum
== -1)
1636 regcache_raw_supply (regcache
, SPARC32_Y_REGNUM
,
1637 regs
+ gregset
->r_y_offset
);
1639 if (regnum
== SPARC_G0_REGNUM
|| regnum
== -1)
1640 regcache_raw_supply (regcache
, SPARC_G0_REGNUM
, NULL
);
1642 if ((regnum
>= SPARC_G1_REGNUM
&& regnum
<= SPARC_O7_REGNUM
) || regnum
== -1)
1644 int offset
= gregset
->r_g1_offset
;
1646 for (i
= SPARC_G1_REGNUM
; i
<= SPARC_O7_REGNUM
; i
++)
1648 if (regnum
== i
|| regnum
== -1)
1649 regcache_raw_supply (regcache
, i
, regs
+ offset
);
1654 if ((regnum
>= SPARC_L0_REGNUM
&& regnum
<= SPARC_I7_REGNUM
) || regnum
== -1)
1656 /* Not all of the register set variants include Locals and
1657 Inputs. For those that don't, we read them off the stack. */
1658 if (gregset
->r_l0_offset
== -1)
1662 regcache_cooked_read_unsigned (regcache
, SPARC_SP_REGNUM
, &sp
);
1663 sparc_supply_rwindow (regcache
, sp
, regnum
);
1667 int offset
= gregset
->r_l0_offset
;
1669 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1671 if (regnum
== i
|| regnum
== -1)
1672 regcache_raw_supply (regcache
, i
, regs
+ offset
);
1680 sparc32_collect_gregset (const struct sparc_gregset
*gregset
,
1681 const struct regcache
*regcache
,
1682 int regnum
, void *gregs
)
1684 gdb_byte
*regs
= gregs
;
1687 if (regnum
== SPARC32_PSR_REGNUM
|| regnum
== -1)
1688 regcache_raw_collect (regcache
, SPARC32_PSR_REGNUM
,
1689 regs
+ gregset
->r_psr_offset
);
1691 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== -1)
1692 regcache_raw_collect (regcache
, SPARC32_PC_REGNUM
,
1693 regs
+ gregset
->r_pc_offset
);
1695 if (regnum
== SPARC32_NPC_REGNUM
|| regnum
== -1)
1696 regcache_raw_collect (regcache
, SPARC32_NPC_REGNUM
,
1697 regs
+ gregset
->r_npc_offset
);
1699 if (regnum
== SPARC32_Y_REGNUM
|| regnum
== -1)
1700 regcache_raw_collect (regcache
, SPARC32_Y_REGNUM
,
1701 regs
+ gregset
->r_y_offset
);
1703 if ((regnum
>= SPARC_G1_REGNUM
&& regnum
<= SPARC_O7_REGNUM
) || regnum
== -1)
1705 int offset
= gregset
->r_g1_offset
;
1707 /* %g0 is always zero. */
1708 for (i
= SPARC_G1_REGNUM
; i
<= SPARC_O7_REGNUM
; i
++)
1710 if (regnum
== i
|| regnum
== -1)
1711 regcache_raw_collect (regcache
, i
, regs
+ offset
);
1716 if ((regnum
>= SPARC_L0_REGNUM
&& regnum
<= SPARC_I7_REGNUM
) || regnum
== -1)
1718 /* Not all of the register set variants include Locals and
1719 Inputs. For those that don't, we read them off the stack. */
1720 if (gregset
->r_l0_offset
!= -1)
1722 int offset
= gregset
->r_l0_offset
;
1724 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1726 if (regnum
== i
|| regnum
== -1)
1727 regcache_raw_collect (regcache
, i
, regs
+ offset
);
1735 sparc32_supply_fpregset (struct regcache
*regcache
,
1736 int regnum
, const void *fpregs
)
1738 const gdb_byte
*regs
= fpregs
;
1741 for (i
= 0; i
< 32; i
++)
1743 if (regnum
== (SPARC_F0_REGNUM
+ i
) || regnum
== -1)
1744 regcache_raw_supply (regcache
, SPARC_F0_REGNUM
+ i
, regs
+ (i
* 4));
1747 if (regnum
== SPARC32_FSR_REGNUM
|| regnum
== -1)
1748 regcache_raw_supply (regcache
, SPARC32_FSR_REGNUM
, regs
+ (32 * 4) + 4);
1752 sparc32_collect_fpregset (const struct regcache
*regcache
,
1753 int regnum
, void *fpregs
)
1755 gdb_byte
*regs
= fpregs
;
1758 for (i
= 0; i
< 32; i
++)
1760 if (regnum
== (SPARC_F0_REGNUM
+ i
) || regnum
== -1)
1761 regcache_raw_collect (regcache
, SPARC_F0_REGNUM
+ i
, regs
+ (i
* 4));
1764 if (regnum
== SPARC32_FSR_REGNUM
|| regnum
== -1)
1765 regcache_raw_collect (regcache
, SPARC32_FSR_REGNUM
, regs
+ (32 * 4) + 4);
1771 /* From <machine/reg.h>. */
1772 const struct sparc_gregset sparc32_sunos4_gregset
=
1785 /* Provide a prototype to silence -Wmissing-prototypes. */
1786 void _initialize_sparc_tdep (void);
1789 _initialize_sparc_tdep (void)
1791 register_gdbarch_init (bfd_arch_sparc
, sparc32_gdbarch_init
);