1 /* Target-dependent code for the SPARC for GDB, the GNU debugger.
2 Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997
3 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
21 /* ??? Support for calling functions from gdb in sparc64 is unfinished. */
30 #include "gdb_string.h"
33 #include <sys/procfs.h>
38 #if defined(TARGET_SPARCLET) || defined(TARGET_SPARCLITE)
39 #define SPARC_HAS_FPU 0
41 #define SPARC_HAS_FPU 1
44 #ifdef GDB_TARGET_IS_SPARC64
45 #define FP_REGISTER_BYTES (64 * 4)
47 #define FP_REGISTER_BYTES (32 * 4)
50 /* If not defined, assume 32 bit sparc. */
52 #define FP_MAX_REGNUM (FP0_REGNUM + 32)
55 #define SPARC_INTREG_SIZE (REGISTER_RAW_SIZE (G0_REGNUM))
58 extern int stop_after_trap
;
60 /* We don't store all registers immediately when requested, since they
61 get sent over in large chunks anyway. Instead, we accumulate most
62 of the changes and send them over once. "deferred_stores" keeps
63 track of which sets of registers we have locally-changed copies of,
64 so we only need send the groups that have changed. */
66 int deferred_stores
= 0; /* Cumulates stores we want to do eventually. */
69 /* Some machines, such as Fujitsu SPARClite 86x, have a bi-endian mode
70 where instructions are big-endian and data are little-endian.
71 This flag is set when we detect that the target is of this type. */
76 /* Fetch a single instruction. Even on bi-endian machines
77 such as sparc86x, instructions are always big-endian. */
80 fetch_instruction (pc
)
87 read_memory (pc
, buf
, sizeof (buf
));
89 /* Start at the most significant end of the integer, and work towards
90 the least significant. */
92 for (i
= 0; i
< sizeof (buf
); ++i
)
93 retval
= (retval
<< 8) | buf
[i
];
98 /* Branches with prediction are treated like their non-predicting cousins. */
99 /* FIXME: What about floating point branches? */
101 /* Macros to extract fields from sparc instructions. */
102 #define X_OP(i) (((i) >> 30) & 0x3)
103 #define X_RD(i) (((i) >> 25) & 0x1f)
104 #define X_A(i) (((i) >> 29) & 1)
105 #define X_COND(i) (((i) >> 25) & 0xf)
106 #define X_OP2(i) (((i) >> 22) & 0x7)
107 #define X_IMM22(i) ((i) & 0x3fffff)
108 #define X_OP3(i) (((i) >> 19) & 0x3f)
109 #define X_RS1(i) (((i) >> 14) & 0x1f)
110 #define X_I(i) (((i) >> 13) & 1)
111 #define X_IMM13(i) ((i) & 0x1fff)
112 /* Sign extension macros. */
113 #define X_SIMM13(i) ((X_IMM13 (i) ^ 0x1000) - 0x1000)
114 #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000)
115 #define X_CC(i) (((i) >> 20) & 3)
116 #define X_P(i) (((i) >> 19) & 1)
117 #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000)
118 #define X_RCOND(i) (((i) >> 25) & 7)
119 #define X_DISP16(i) ((((((i) >> 6) && 0xc000) | ((i) & 0x3fff)) ^ 0x8000) - 0x8000)
120 #define X_FCN(i) (((i) >> 25) & 31)
124 Error
, not_branch
, bicc
, bicca
, ba
, baa
, ticc
, ta
,
125 #ifdef GDB_TARGET_IS_SPARC64
130 /* Simulate single-step ptrace call for sun4. Code written by Gary
131 Beihl (beihl@mcc.com). */
133 /* npc4 and next_pc describe the situation at the time that the
134 step-breakpoint was set, not necessary the current value of NPC_REGNUM. */
135 static CORE_ADDR next_pc
, npc4
, target
;
136 static int brknpc4
, brktrg
;
137 typedef char binsn_quantum
[BREAKPOINT_MAX
];
138 static binsn_quantum break_mem
[3];
140 static branch_type isbranch
PARAMS ((long, CORE_ADDR
, CORE_ADDR
*));
142 /* single_step() is called just before we want to resume the inferior,
143 if we want to single-step it but there is no hardware or kernel single-step
144 support (as on all SPARCs). We find all the possible targets of the
145 coming instruction and breakpoint them.
147 single_step is also called just after the inferior stops. If we had
148 set up a simulated single-step, we undo our damage. */
151 sparc_software_single_step (ignore
, insert_breakpoints_p
)
152 enum target_signal ignore
; /* pid, but we don't need it */
153 int insert_breakpoints_p
;
159 if (insert_breakpoints_p
)
161 /* Always set breakpoint for NPC. */
162 next_pc
= read_register (NPC_REGNUM
);
163 npc4
= next_pc
+ 4; /* branch not taken */
165 target_insert_breakpoint (next_pc
, break_mem
[0]);
166 /* printf_unfiltered ("set break at %x\n",next_pc); */
168 pc
= read_register (PC_REGNUM
);
169 pc_instruction
= fetch_instruction (pc
);
170 br
= isbranch (pc_instruction
, pc
, &target
);
171 brknpc4
= brktrg
= 0;
175 /* Conditional annulled branch will either end up at
176 npc (if taken) or at npc+4 (if not taken).
179 target_insert_breakpoint (npc4
, break_mem
[1]);
181 else if (br
== baa
&& target
!= next_pc
)
183 /* Unconditional annulled branch will always end up at
186 target_insert_breakpoint (target
, break_mem
[2]);
188 #ifdef GDB_TARGET_IS_SPARC64
189 else if (br
== done_retry
)
192 target_insert_breakpoint (target
, break_mem
[2]);
198 /* Remove breakpoints */
199 target_remove_breakpoint (next_pc
, break_mem
[0]);
202 target_remove_breakpoint (npc4
, break_mem
[1]);
205 target_remove_breakpoint (target
, break_mem
[2]);
209 /* Call this for each newly created frame. For SPARC, we need to calculate
210 the bottom of the frame, and do some extra work if the prologue
211 has been generated via the -mflat option to GCC. In particular,
212 we need to know where the previous fp and the pc have been stashed,
213 since their exact position within the frame may vary. */
216 sparc_init_extra_frame_info (fromleaf
, fi
)
218 struct frame_info
*fi
;
221 CORE_ADDR prologue_start
, prologue_end
;
226 (fi
->frame
== fi
->next
->frame
? fi
->next
->bottom
: fi
->next
->frame
) :
229 /* If fi->next is NULL, then we already set ->frame by passing read_fp()
230 to create_new_frame. */
233 char buf
[MAX_REGISTER_RAW_SIZE
];
235 /* Compute ->frame as if not flat. If it is flat, we'll change
237 if (fi
->next
->next
!= NULL
238 && (fi
->next
->next
->signal_handler_caller
239 || frame_in_dummy (fi
->next
->next
))
240 && frameless_look_for_prologue (fi
->next
))
242 /* A frameless function interrupted by a signal did not change
243 the frame pointer, fix up frame pointer accordingly. */
244 fi
->frame
= FRAME_FP (fi
->next
);
245 fi
->bottom
= fi
->next
->bottom
;
249 /* Should we adjust for stack bias here? */
250 get_saved_register (buf
, 0, 0, fi
, FP_REGNUM
, 0);
251 fi
->frame
= extract_address (buf
, REGISTER_RAW_SIZE (FP_REGNUM
));
252 #ifdef GDB_TARGET_IS_SPARC64
260 /* Decide whether this is a function with a ``flat register window''
261 frame. For such functions, the frame pointer is actually in %i7. */
264 if (find_pc_partial_function (fi
->pc
, &name
, &prologue_start
, &prologue_end
))
266 /* See if the function starts with an add (which will be of a
267 negative number if a flat frame) to the sp. FIXME: Does not
268 handle large frames which will need more than one instruction
270 insn
= fetch_instruction (prologue_start
, 4);
271 if (X_OP (insn
) == 2 && X_RD (insn
) == 14 && X_OP3 (insn
) == 0
272 && X_I (insn
) && X_SIMM13 (insn
) < 0)
274 int offset
= X_SIMM13 (insn
);
276 /* Then look for a save of %i7 into the frame. */
277 insn
= fetch_instruction (prologue_start
+ 4);
281 && X_RS1 (insn
) == 14)
283 char buf
[MAX_REGISTER_RAW_SIZE
];
285 /* We definitely have a flat frame now. */
288 fi
->sp_offset
= offset
;
290 /* Overwrite the frame's address with the value in %i7. */
291 get_saved_register (buf
, 0, 0, fi
, I7_REGNUM
, 0);
292 fi
->frame
= extract_address (buf
, REGISTER_RAW_SIZE (I7_REGNUM
));
293 #ifdef GDB_TARGET_IS_SPARC64
297 /* Record where the fp got saved. */
298 fi
->fp_addr
= fi
->frame
+ fi
->sp_offset
+ X_SIMM13 (insn
);
300 /* Also try to collect where the pc got saved to. */
302 insn
= fetch_instruction (prologue_start
+ 12);
306 && X_RS1 (insn
) == 14)
307 fi
->pc_addr
= fi
->frame
+ fi
->sp_offset
+ X_SIMM13 (insn
);
312 /* Check if the PC is in the function prologue before a SAVE
313 instruction has been executed yet. If so, set the frame
314 to the current value of the stack pointer and set
315 the in_prologue flag. */
317 struct symtab_and_line sal
;
319 sal
= find_pc_line (prologue_start
, 0);
320 if (sal
.line
== 0) /* no line info, use PC */
321 prologue_end
= fi
->pc
;
322 else if (sal
.end
< prologue_end
)
323 prologue_end
= sal
.end
;
324 if (fi
->pc
< prologue_end
)
326 for (addr
= prologue_start
; addr
< fi
->pc
; addr
+= 4)
328 insn
= read_memory_integer (addr
, 4);
329 if (X_OP (insn
) == 2 && X_OP3 (insn
) == 0x3c)
330 break; /* SAVE seen, stop searching */
335 fi
->frame
= read_register (SP_REGNUM
);
340 if (fi
->next
&& fi
->frame
== 0)
342 /* Kludge to cause init_prev_frame_info to destroy the new frame. */
343 fi
->frame
= fi
->next
->frame
;
344 fi
->pc
= fi
->next
->pc
;
349 sparc_frame_chain (frame
)
350 struct frame_info
*frame
;
352 /* Value that will cause FRAME_CHAIN_VALID to not worry about the chain
353 value. If it realy is zero, we detect it later in
354 sparc_init_prev_frame. */
359 sparc_extract_struct_value_address (regbuf
)
360 char regbuf
[REGISTER_BYTES
];
362 return extract_address (regbuf
+ REGISTER_BYTE (O0_REGNUM
),
363 REGISTER_RAW_SIZE (O0_REGNUM
));
366 /* Find the pc saved in frame FRAME. */
369 sparc_frame_saved_pc (frame
)
370 struct frame_info
*frame
;
372 char buf
[MAX_REGISTER_RAW_SIZE
];
375 if (frame
->signal_handler_caller
)
377 /* This is the signal trampoline frame.
378 Get the saved PC from the sigcontext structure. */
380 #ifndef SIGCONTEXT_PC_OFFSET
381 #define SIGCONTEXT_PC_OFFSET 12
384 CORE_ADDR sigcontext_addr
;
385 char scbuf
[TARGET_PTR_BIT
/ HOST_CHAR_BIT
];
386 int saved_pc_offset
= SIGCONTEXT_PC_OFFSET
;
389 /* Solaris2 ucbsigvechandler passes a pointer to a sigcontext
390 as the third parameter. The offset to the saved pc is 12. */
391 find_pc_partial_function (frame
->pc
, &name
,
392 (CORE_ADDR
*)NULL
,(CORE_ADDR
*)NULL
);
393 if (name
&& STREQ (name
, "ucbsigvechandler"))
394 saved_pc_offset
= 12;
396 /* The sigcontext address is contained in register O2. */
397 get_saved_register (buf
, (int *)NULL
, (CORE_ADDR
*)NULL
,
398 frame
, O0_REGNUM
+ 2, (enum lval_type
*)NULL
);
399 sigcontext_addr
= extract_address (buf
, REGISTER_RAW_SIZE (O0_REGNUM
+ 2));
401 /* Don't cause a memory_error when accessing sigcontext in case the
402 stack layout has changed or the stack is corrupt. */
403 target_read_memory (sigcontext_addr
+ saved_pc_offset
,
404 scbuf
, sizeof (scbuf
));
405 return extract_address (scbuf
, sizeof (scbuf
));
407 else if (frame
->in_prologue
||
409 && (frame
->next
->signal_handler_caller
410 || frame_in_dummy (frame
->next
))
411 && frameless_look_for_prologue (frame
)))
413 /* A frameless function interrupted by a signal did not save
414 the PC, it is still in %o7. */
415 get_saved_register (buf
, (int *)NULL
, (CORE_ADDR
*)NULL
,
416 frame
, O7_REGNUM
, (enum lval_type
*)NULL
);
417 return PC_ADJUST (extract_address (buf
, SPARC_INTREG_SIZE
));
420 addr
= frame
->pc_addr
;
422 addr
= frame
->bottom
+ FRAME_SAVED_I0
+
423 SPARC_INTREG_SIZE
* (I7_REGNUM
- I0_REGNUM
);
426 /* A flat frame leaf function might not save the PC anywhere,
427 just leave it in %o7. */
428 return PC_ADJUST (read_register (O7_REGNUM
));
430 read_memory (addr
, buf
, SPARC_INTREG_SIZE
);
431 return PC_ADJUST (extract_address (buf
, SPARC_INTREG_SIZE
));
434 /* Since an individual frame in the frame cache is defined by two
435 arguments (a frame pointer and a stack pointer), we need two
436 arguments to get info for an arbitrary stack frame. This routine
437 takes two arguments and makes the cached frames look as if these
438 two arguments defined a frame on the cache. This allows the rest
439 of info frame to extract the important arguments without
443 setup_arbitrary_frame (argc
, argv
)
447 struct frame_info
*frame
;
450 error ("Sparc frame specifications require two arguments: fp and sp");
452 frame
= create_new_frame (argv
[0], 0);
455 fatal ("internal: create_new_frame returned invalid frame");
457 frame
->bottom
= argv
[1];
458 frame
->pc
= FRAME_SAVED_PC (frame
);
462 /* Given a pc value, skip it forward past the function prologue by
463 disassembling instructions that appear to be a prologue.
465 If FRAMELESS_P is set, we are only testing to see if the function
466 is frameless. This allows a quicker answer.
468 This routine should be more specific in its actions; making sure
469 that it uses the same register in the initial prologue section. */
471 static CORE_ADDR examine_prologue
PARAMS ((CORE_ADDR
, int, struct frame_info
*,
472 struct frame_saved_regs
*));
475 examine_prologue (start_pc
, frameless_p
, fi
, saved_regs
)
478 struct frame_info
*fi
;
479 struct frame_saved_regs
*saved_regs
;
483 CORE_ADDR pc
= start_pc
;
486 insn
= fetch_instruction (pc
);
488 /* Recognize the `sethi' insn and record its destination. */
489 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 4)
493 insn
= fetch_instruction (pc
);
496 /* Recognize an add immediate value to register to either %g1 or
497 the destination register recorded above. Actually, this might
498 well recognize several different arithmetic operations.
499 It doesn't check that rs1 == rd because in theory "sub %g0, 5, %g1"
500 followed by "save %sp, %g1, %sp" is a valid prologue (Not that
501 I imagine any compiler really does that, however). */
504 && (X_RD (insn
) == 1 || X_RD (insn
) == dest
))
507 insn
= fetch_instruction (pc
);
510 /* Recognize any SAVE insn. */
511 if (X_OP (insn
) == 2 && X_OP3 (insn
) == 60)
514 if (frameless_p
) /* If the save is all we care about, */
515 return pc
; /* return before doing more work */
516 insn
= fetch_instruction (pc
);
518 /* Recognize add to %sp. */
519 else if (X_OP (insn
) == 2 && X_RD (insn
) == 14 && X_OP3 (insn
) == 0)
522 if (frameless_p
) /* If the add is all we care about, */
523 return pc
; /* return before doing more work */
525 insn
= fetch_instruction (pc
);
526 /* Recognize store of frame pointer (i7). */
530 && X_RS1 (insn
) == 14)
533 insn
= fetch_instruction (pc
);
535 /* Recognize sub %sp, <anything>, %i7. */
538 && X_RS1 (insn
) == 14
539 && X_RD (insn
) == 31)
542 insn
= fetch_instruction (pc
);
551 /* Without a save or add instruction, it's not a prologue. */
556 /* Recognize stores into the frame from the input registers.
557 This recognizes all non alternate stores of input register,
558 into a location offset from the frame pointer. */
559 if ((X_OP (insn
) == 3
560 && (X_OP3 (insn
) & 0x3c) == 4 /* Store, non-alternate. */
561 && (X_RD (insn
) & 0x18) == 0x18 /* Input register. */
562 && X_I (insn
) /* Immediate mode. */
563 && X_RS1 (insn
) == 30 /* Off of frame pointer. */
564 /* Into reserved stack space. */
565 && X_SIMM13 (insn
) >= 0x44
566 && X_SIMM13 (insn
) < 0x5b))
571 && X_RS1 (insn
) == 14
574 if (saved_regs
&& X_I (insn
))
575 saved_regs
->regs
[X_RD (insn
)] =
576 fi
->frame
+ fi
->sp_offset
+ X_SIMM13 (insn
);
581 insn
= fetch_instruction (pc
);
588 skip_prologue (start_pc
, frameless_p
)
592 return examine_prologue (start_pc
, frameless_p
, NULL
, NULL
);
595 /* Check instruction at ADDR to see if it is a branch.
596 All non-annulled instructions will go to NPC or will trap.
597 Set *TARGET if we find a candidate branch; set to zero if not.
599 This isn't static as it's used by remote-sa.sparc.c. */
602 isbranch (instruction
, addr
, target
)
604 CORE_ADDR addr
, *target
;
606 branch_type val
= not_branch
;
607 long int offset
= 0; /* Must be signed for sign-extend. */
611 if (X_OP (instruction
) == 0
612 && (X_OP2 (instruction
) == 2
613 || X_OP2 (instruction
) == 6
614 || X_OP2 (instruction
) == 1
615 || X_OP2 (instruction
) == 3
616 || X_OP2 (instruction
) == 5
617 #ifndef GDB_TARGET_IS_SPARC64
618 || X_OP2 (instruction
) == 7
622 if (X_COND (instruction
) == 8)
623 val
= X_A (instruction
) ? baa
: ba
;
625 val
= X_A (instruction
) ? bicca
: bicc
;
626 switch (X_OP2 (instruction
))
630 #ifndef GDB_TARGET_IS_SPARC64
633 offset
= 4 * X_DISP22 (instruction
);
637 offset
= 4 * X_DISP19 (instruction
);
640 offset
= 4 * X_DISP16 (instruction
);
643 *target
= addr
+ offset
;
645 #ifdef GDB_TARGET_IS_SPARC64
646 else if (X_OP (instruction
) == 2
647 && X_OP3 (instruction
) == 62)
649 if (X_FCN (instruction
) == 0)
652 *target
= read_register (TNPC_REGNUM
);
655 else if (X_FCN (instruction
) == 1)
658 *target
= read_register (TPC_REGNUM
);
667 /* Find register number REGNUM relative to FRAME and put its
668 (raw) contents in *RAW_BUFFER. Set *OPTIMIZED if the variable
669 was optimized out (and thus can't be fetched). If the variable
670 was fetched from memory, set *ADDRP to where it was fetched from,
671 otherwise it was fetched from a register.
673 The argument RAW_BUFFER must point to aligned memory. */
676 get_saved_register (raw_buffer
, optimized
, addrp
, frame
, regnum
, lval
)
680 struct frame_info
*frame
;
682 enum lval_type
*lval
;
684 struct frame_info
*frame1
;
687 if (!target_has_registers
)
688 error ("No registers.");
695 /* FIXME This code extracted from infcmd.c; should put elsewhere! */
698 /* error ("No selected frame."); */
699 if (!target_has_registers
)
700 error ("The program has no registers now.");
701 if (selected_frame
== NULL
)
702 error ("No selected frame.");
703 /* Try to use selected frame */
704 frame
= get_prev_frame (selected_frame
);
706 error ("Cmd not meaningful in the outermost frame.");
710 frame1
= frame
->next
;
712 /* Get saved PC from the frame info if not in innermost frame. */
713 if (regnum
== PC_REGNUM
&& frame1
!= NULL
)
717 if (raw_buffer
!= NULL
)
719 /* Put it back in target format. */
720 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
), frame
->pc
);
727 while (frame1
!= NULL
)
729 if (frame1
->pc
>= (frame1
->bottom
? frame1
->bottom
:
731 && frame1
->pc
<= FRAME_FP (frame1
))
733 /* Dummy frame. All but the window regs are in there somewhere.
734 The window registers are saved on the stack, just like in a
736 if (regnum
>= G1_REGNUM
&& regnum
< G1_REGNUM
+ 7)
737 addr
= frame1
->frame
+ (regnum
- G0_REGNUM
) * SPARC_INTREG_SIZE
738 - (FP_REGISTER_BYTES
+ 8 * SPARC_INTREG_SIZE
);
739 else if (regnum
>= I0_REGNUM
&& regnum
< I0_REGNUM
+ 8)
740 addr
= (frame1
->prev
->bottom
741 + (regnum
- I0_REGNUM
) * SPARC_INTREG_SIZE
743 else if (regnum
>= L0_REGNUM
&& regnum
< L0_REGNUM
+ 8)
744 addr
= (frame1
->prev
->bottom
745 + (regnum
- L0_REGNUM
) * SPARC_INTREG_SIZE
747 else if (regnum
>= O0_REGNUM
&& regnum
< O0_REGNUM
+ 8)
748 addr
= frame1
->frame
+ (regnum
- O0_REGNUM
) * SPARC_INTREG_SIZE
749 - (FP_REGISTER_BYTES
+ 16 * SPARC_INTREG_SIZE
);
751 else if (regnum
>= FP0_REGNUM
&& regnum
< FP0_REGNUM
+ 32)
752 addr
= frame1
->frame
+ (regnum
- FP0_REGNUM
) * 4
753 - (FP_REGISTER_BYTES
);
754 #ifdef GDB_TARGET_IS_SPARC64
755 else if (regnum
>= FP0_REGNUM
+ 32 && regnum
< FP_MAX_REGNUM
)
756 addr
= frame1
->frame
+ 32 * 4 + (regnum
- FP0_REGNUM
- 32) * 8
757 - (FP_REGISTER_BYTES
);
759 #endif /* FP0_REGNUM */
760 else if (regnum
>= Y_REGNUM
&& regnum
< NUM_REGS
)
761 addr
= frame1
->frame
+ (regnum
- Y_REGNUM
) * SPARC_INTREG_SIZE
762 - (FP_REGISTER_BYTES
+ 24 * SPARC_INTREG_SIZE
);
764 else if (frame1
->flat
)
767 if (regnum
== RP_REGNUM
)
768 addr
= frame1
->pc_addr
;
769 else if (regnum
== I7_REGNUM
)
770 addr
= frame1
->fp_addr
;
773 CORE_ADDR func_start
;
774 struct frame_saved_regs regs
;
775 memset (®s
, 0, sizeof (regs
));
777 find_pc_partial_function (frame1
->pc
, NULL
, &func_start
, NULL
);
778 examine_prologue (func_start
, 0, frame1
, ®s
);
779 addr
= regs
.regs
[regnum
];
784 /* Normal frame. Local and In registers are saved on stack. */
785 if (regnum
>= I0_REGNUM
&& regnum
< I0_REGNUM
+ 8)
786 addr
= (frame1
->prev
->bottom
787 + (regnum
- I0_REGNUM
) * SPARC_INTREG_SIZE
789 else if (regnum
>= L0_REGNUM
&& regnum
< L0_REGNUM
+ 8)
790 addr
= (frame1
->prev
->bottom
791 + (regnum
- L0_REGNUM
) * SPARC_INTREG_SIZE
793 else if (regnum
>= O0_REGNUM
&& regnum
< O0_REGNUM
+ 8)
795 /* Outs become ins. */
796 get_saved_register (raw_buffer
, optimized
, addrp
, frame1
,
797 (regnum
- O0_REGNUM
+ I0_REGNUM
), lval
);
803 frame1
= frame1
->next
;
809 if (regnum
== SP_REGNUM
)
811 if (raw_buffer
!= NULL
)
813 /* Put it back in target format. */
814 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
), addr
);
820 if (raw_buffer
!= NULL
)
821 read_memory (addr
, raw_buffer
, REGISTER_RAW_SIZE (regnum
));
826 *lval
= lval_register
;
827 addr
= REGISTER_BYTE (regnum
);
828 if (raw_buffer
!= NULL
)
829 read_register_gen (regnum
, raw_buffer
);
835 /* Push an empty stack frame, and record in it the current PC, regs, etc.
837 We save the non-windowed registers and the ins. The locals and outs
838 are new; they don't need to be saved. The i's and l's of
839 the last frame were already saved on the stack. */
841 /* Definitely see tm-sparc.h for more doc of the frame format here. */
843 #ifdef GDB_TARGET_IS_SPARC64
844 #define DUMMY_REG_SAVE_OFFSET (128 + 16)
846 #define DUMMY_REG_SAVE_OFFSET 0x60
849 /* See tm-sparc.h for how this is calculated. */
851 #define DUMMY_STACK_REG_BUF_SIZE \
852 (((8+8+8) * SPARC_INTREG_SIZE) + FP_REGISTER_BYTES)
854 #define DUMMY_STACK_REG_BUF_SIZE \
855 (((8+8+8) * SPARC_INTREG_SIZE) )
856 #endif /* FP0_REGNUM */
857 #define DUMMY_STACK_SIZE (DUMMY_STACK_REG_BUF_SIZE + DUMMY_REG_SAVE_OFFSET)
860 sparc_push_dummy_frame ()
862 CORE_ADDR sp
, old_sp
;
863 char register_temp
[DUMMY_STACK_SIZE
];
865 old_sp
= sp
= read_sp ();
867 #ifdef GDB_TARGET_IS_SPARC64
868 /* PC, NPC, CCR, FSR, FPRS, Y, ASI */
869 read_register_bytes (REGISTER_BYTE (PC_REGNUM
), ®ister_temp
[0],
870 REGISTER_RAW_SIZE (PC_REGNUM
) * 7);
871 read_register_bytes (REGISTER_BYTE (PSTATE_REGNUM
), ®ister_temp
[8],
872 REGISTER_RAW_SIZE (PSTATE_REGNUM
));
873 /* FIXME: not sure what needs to be saved here. */
875 /* Y, PS, WIM, TBR, PC, NPC, FPS, CPS regs */
876 read_register_bytes (REGISTER_BYTE (Y_REGNUM
), ®ister_temp
[0],
877 REGISTER_RAW_SIZE (Y_REGNUM
) * 8);
880 read_register_bytes (REGISTER_BYTE (O0_REGNUM
),
881 ®ister_temp
[8 * SPARC_INTREG_SIZE
],
882 SPARC_INTREG_SIZE
* 8);
884 read_register_bytes (REGISTER_BYTE (G0_REGNUM
),
885 ®ister_temp
[16 * SPARC_INTREG_SIZE
],
886 SPARC_INTREG_SIZE
* 8);
889 read_register_bytes (REGISTER_BYTE (FP0_REGNUM
),
890 ®ister_temp
[24 * SPARC_INTREG_SIZE
],
892 #endif /* FP0_REGNUM */
894 sp
-= DUMMY_STACK_SIZE
;
898 write_memory (sp
+ DUMMY_REG_SAVE_OFFSET
, ®ister_temp
[0],
899 DUMMY_STACK_REG_BUF_SIZE
);
901 if (strcmp (target_shortname
, "sim") != 0)
905 /* Set return address register for the call dummy to the current PC. */
906 write_register (I7_REGNUM
, read_pc() - 8);
910 /* The call dummy will write this value to FP before executing
911 the 'save'. This ensures that register window flushes work
912 correctly in the simulator. */
913 write_register (G0_REGNUM
+1, read_register (FP_REGNUM
));
915 /* The call dummy will write this value to FP after executing
917 write_register (G0_REGNUM
+2, old_sp
);
919 /* The call dummy will write this value to the return address (%i7) after
920 executing the 'save'. */
921 write_register (G0_REGNUM
+3, read_pc() - 8);
923 /* Set the FP that the call dummy will be using after the 'save'.
924 This makes backtraces from an inferior function call work properly. */
925 write_register (FP_REGNUM
, old_sp
);
929 /* sparc_frame_find_saved_regs (). This function is here only because
930 pop_frame uses it. Note there is an interesting corner case which
931 I think few ports of GDB get right--if you are popping a frame
932 which does not save some register that *is* saved by a more inner
933 frame (such a frame will never be a dummy frame because dummy
934 frames save all registers). Rewriting pop_frame to use
935 get_saved_register would solve this problem and also get rid of the
936 ugly duplication between sparc_frame_find_saved_regs and
939 Stores, into a struct frame_saved_regs,
940 the addresses of the saved registers of frame described by FRAME_INFO.
941 This includes special registers such as pc and fp saved in special
942 ways in the stack frame. sp is even more special:
943 the address we return for it IS the sp for the next frame.
945 Note that on register window machines, we are currently making the
946 assumption that window registers are being saved somewhere in the
947 frame in which they are being used. If they are stored in an
948 inferior frame, find_saved_register will break.
950 On the Sun 4, the only time all registers are saved is when
951 a dummy frame is involved. Otherwise, the only saved registers
952 are the LOCAL and IN registers which are saved as a result
953 of the "save/restore" opcodes. This condition is determined
954 by address rather than by value.
956 The "pc" is not stored in a frame on the SPARC. (What is stored
957 is a return address minus 8.) sparc_pop_frame knows how to
958 deal with that. Other routines might or might not.
960 See tm-sparc.h (PUSH_DUMMY_FRAME and friends) for CRITICAL information
961 about how this works. */
963 static void sparc_frame_find_saved_regs
PARAMS ((struct frame_info
*,
964 struct frame_saved_regs
*));
967 sparc_frame_find_saved_regs (fi
, saved_regs_addr
)
968 struct frame_info
*fi
;
969 struct frame_saved_regs
*saved_regs_addr
;
972 CORE_ADDR frame_addr
= FRAME_FP (fi
);
975 fatal ("Bad frame info struct in FRAME_FIND_SAVED_REGS");
977 memset (saved_regs_addr
, 0, sizeof (*saved_regs_addr
));
979 if (fi
->pc
>= (fi
->bottom
? fi
->bottom
:
981 && fi
->pc
<= FRAME_FP(fi
))
983 /* Dummy frame. All but the window regs are in there somewhere. */
984 for (regnum
= G1_REGNUM
; regnum
< G1_REGNUM
+7; regnum
++)
985 saved_regs_addr
->regs
[regnum
] =
986 frame_addr
+ (regnum
- G0_REGNUM
) * SPARC_INTREG_SIZE
987 - DUMMY_STACK_REG_BUF_SIZE
+ 16 * SPARC_INTREG_SIZE
;
988 for (regnum
= I0_REGNUM
; regnum
< I0_REGNUM
+8; regnum
++)
989 saved_regs_addr
->regs
[regnum
] =
990 frame_addr
+ (regnum
- I0_REGNUM
) * SPARC_INTREG_SIZE
991 - DUMMY_STACK_REG_BUF_SIZE
+ 8 * SPARC_INTREG_SIZE
;
993 for (regnum
= FP0_REGNUM
; regnum
< FP0_REGNUM
+ 32; regnum
++)
994 saved_regs_addr
->regs
[regnum
] =
995 frame_addr
+ (regnum
- FP0_REGNUM
) * 4
996 - DUMMY_STACK_REG_BUF_SIZE
+ 24 * SPARC_INTREG_SIZE
;
997 #ifdef GDB_TARGET_IS_SPARC64
998 for (regnum
= FP0_REGNUM
+ 32; regnum
< FP_MAX_REGNUM
; regnum
++)
999 saved_regs_addr
->regs
[regnum
] =
1000 frame_addr
+ 32 * 4 + (regnum
- FP0_REGNUM
- 32) * 4
1001 - DUMMY_STACK_REG_BUF_SIZE
+ 24 * SPARC_INTREG_SIZE
;
1003 #endif /* FP0_REGNUM */
1004 #ifdef GDB_TARGET_IS_SPARC64
1005 for (regnum
= PC_REGNUM
; regnum
< PC_REGNUM
+ 7; regnum
++)
1007 saved_regs_addr
->regs
[regnum
] =
1008 frame_addr
+ (regnum
- PC_REGNUM
) * SPARC_INTREG_SIZE
1009 - DUMMY_STACK_REG_BUF_SIZE
;
1011 saved_regs_addr
->regs
[PSTATE_REGNUM
] =
1012 frame_addr
+ 8 * SPARC_INTREG_SIZE
- DUMMY_STACK_REG_BUF_SIZE
;
1014 for (regnum
= Y_REGNUM
; regnum
< NUM_REGS
; regnum
++)
1015 saved_regs_addr
->regs
[regnum
] =
1016 frame_addr
+ (regnum
- Y_REGNUM
) * SPARC_INTREG_SIZE
1017 - DUMMY_STACK_REG_BUF_SIZE
;
1019 frame_addr
= fi
->bottom
?
1020 fi
->bottom
: read_sp ();
1024 CORE_ADDR func_start
;
1025 find_pc_partial_function (fi
->pc
, NULL
, &func_start
, NULL
);
1026 examine_prologue (func_start
, 0, fi
, saved_regs_addr
);
1028 /* Flat register window frame. */
1029 saved_regs_addr
->regs
[RP_REGNUM
] = fi
->pc_addr
;
1030 saved_regs_addr
->regs
[I7_REGNUM
] = fi
->fp_addr
;
1034 /* Normal frame. Just Local and In registers */
1035 frame_addr
= fi
->bottom
?
1036 fi
->bottom
: read_sp ();
1037 for (regnum
= L0_REGNUM
; regnum
< L0_REGNUM
+8; regnum
++)
1038 saved_regs_addr
->regs
[regnum
] =
1039 (frame_addr
+ (regnum
- L0_REGNUM
) * SPARC_INTREG_SIZE
1041 for (regnum
= I0_REGNUM
; regnum
< I0_REGNUM
+8; regnum
++)
1042 saved_regs_addr
->regs
[regnum
] =
1043 (frame_addr
+ (regnum
- I0_REGNUM
) * SPARC_INTREG_SIZE
1050 saved_regs_addr
->regs
[O7_REGNUM
] = fi
->pc_addr
;
1054 /* Pull off either the next frame pointer or the stack pointer */
1055 CORE_ADDR next_next_frame_addr
=
1059 for (regnum
= O0_REGNUM
; regnum
< O0_REGNUM
+8; regnum
++)
1060 saved_regs_addr
->regs
[regnum
] =
1061 (next_next_frame_addr
1062 + (regnum
- O0_REGNUM
) * SPARC_INTREG_SIZE
1066 /* Otherwise, whatever we would get from ptrace(GETREGS) is accurate */
1067 /* FIXME -- should this adjust for the sparc64 offset? */
1068 saved_regs_addr
->regs
[SP_REGNUM
] = FRAME_FP (fi
);
1071 /* Discard from the stack the innermost frame, restoring all saved registers.
1073 Note that the values stored in fsr by get_frame_saved_regs are *in
1074 the context of the called frame*. What this means is that the i
1075 regs of fsr must be restored into the o regs of the (calling) frame that
1076 we pop into. We don't care about the output regs of the calling frame,
1077 since unless it's a dummy frame, it won't have any output regs in it.
1079 We never have to bother with %l (local) regs, since the called routine's
1080 locals get tossed, and the calling routine's locals are already saved
1083 /* Definitely see tm-sparc.h for more doc of the frame format here. */
1088 register struct frame_info
*frame
= get_current_frame ();
1089 register CORE_ADDR pc
;
1090 struct frame_saved_regs fsr
;
1091 char raw_buffer
[REGISTER_BYTES
];
1094 sparc_frame_find_saved_regs (frame
, &fsr
);
1096 if (fsr
.regs
[FP0_REGNUM
])
1098 read_memory (fsr
.regs
[FP0_REGNUM
], raw_buffer
, FP_REGISTER_BYTES
);
1099 write_register_bytes (REGISTER_BYTE (FP0_REGNUM
),
1100 raw_buffer
, FP_REGISTER_BYTES
);
1102 #ifndef GDB_TARGET_IS_SPARC64
1103 if (fsr
.regs
[FPS_REGNUM
])
1105 read_memory (fsr
.regs
[FPS_REGNUM
], raw_buffer
, 4);
1106 write_register_bytes (REGISTER_BYTE (FPS_REGNUM
), raw_buffer
, 4);
1108 if (fsr
.regs
[CPS_REGNUM
])
1110 read_memory (fsr
.regs
[CPS_REGNUM
], raw_buffer
, 4);
1111 write_register_bytes (REGISTER_BYTE (CPS_REGNUM
), raw_buffer
, 4);
1114 #endif /* FP0_REGNUM */
1115 if (fsr
.regs
[G1_REGNUM
])
1117 read_memory (fsr
.regs
[G1_REGNUM
], raw_buffer
, 7 * SPARC_INTREG_SIZE
);
1118 write_register_bytes (REGISTER_BYTE (G1_REGNUM
), raw_buffer
,
1119 7 * SPARC_INTREG_SIZE
);
1124 /* Each register might or might not have been saved, need to test
1126 for (regnum
= L0_REGNUM
; regnum
< L0_REGNUM
+ 8; ++regnum
)
1127 if (fsr
.regs
[regnum
])
1128 write_register (regnum
, read_memory_integer (fsr
.regs
[regnum
],
1129 SPARC_INTREG_SIZE
));
1130 for (regnum
= I0_REGNUM
; regnum
< I0_REGNUM
+ 8; ++regnum
)
1131 if (fsr
.regs
[regnum
])
1132 write_register (regnum
, read_memory_integer (fsr
.regs
[regnum
],
1133 SPARC_INTREG_SIZE
));
1135 /* Handle all outs except stack pointer (o0-o5; o7). */
1136 for (regnum
= O0_REGNUM
; regnum
< O0_REGNUM
+ 6; ++regnum
)
1137 if (fsr
.regs
[regnum
])
1138 write_register (regnum
, read_memory_integer (fsr
.regs
[regnum
],
1139 SPARC_INTREG_SIZE
));
1140 if (fsr
.regs
[O0_REGNUM
+ 7])
1141 write_register (O0_REGNUM
+ 7,
1142 read_memory_integer (fsr
.regs
[O0_REGNUM
+ 7],
1143 SPARC_INTREG_SIZE
));
1145 write_sp (frame
->frame
);
1147 else if (fsr
.regs
[I0_REGNUM
])
1151 char reg_temp
[REGISTER_BYTES
];
1153 read_memory (fsr
.regs
[I0_REGNUM
], raw_buffer
, 8 * SPARC_INTREG_SIZE
);
1155 /* Get the ins and locals which we are about to restore. Just
1156 moving the stack pointer is all that is really needed, except
1157 store_inferior_registers is then going to write the ins and
1158 locals from the registers array, so we need to muck with the
1160 sp
= fsr
.regs
[SP_REGNUM
];
1161 #ifdef GDB_TARGET_IS_SPARC64
1165 read_memory (sp
, reg_temp
, SPARC_INTREG_SIZE
* 16);
1167 /* Restore the out registers.
1168 Among other things this writes the new stack pointer. */
1169 write_register_bytes (REGISTER_BYTE (O0_REGNUM
), raw_buffer
,
1170 SPARC_INTREG_SIZE
* 8);
1172 write_register_bytes (REGISTER_BYTE (L0_REGNUM
), reg_temp
,
1173 SPARC_INTREG_SIZE
* 16);
1175 #ifndef GDB_TARGET_IS_SPARC64
1176 if (fsr
.regs
[PS_REGNUM
])
1177 write_register (PS_REGNUM
, read_memory_integer (fsr
.regs
[PS_REGNUM
], 4));
1179 if (fsr
.regs
[Y_REGNUM
])
1180 write_register (Y_REGNUM
, read_memory_integer (fsr
.regs
[Y_REGNUM
], REGISTER_RAW_SIZE (Y_REGNUM
)));
1181 if (fsr
.regs
[PC_REGNUM
])
1183 /* Explicitly specified PC (and maybe NPC) -- just restore them. */
1184 write_register (PC_REGNUM
, read_memory_integer (fsr
.regs
[PC_REGNUM
],
1185 REGISTER_RAW_SIZE (PC_REGNUM
)));
1186 if (fsr
.regs
[NPC_REGNUM
])
1187 write_register (NPC_REGNUM
,
1188 read_memory_integer (fsr
.regs
[NPC_REGNUM
],
1189 REGISTER_RAW_SIZE (NPC_REGNUM
)));
1191 else if (frame
->flat
)
1194 pc
= PC_ADJUST ((CORE_ADDR
)
1195 read_memory_integer (frame
->pc_addr
,
1196 REGISTER_RAW_SIZE (PC_REGNUM
)));
1199 /* I think this happens only in the innermost frame, if so then
1200 it is a complicated way of saying
1201 "pc = read_register (O7_REGNUM);". */
1202 char buf
[MAX_REGISTER_RAW_SIZE
];
1203 get_saved_register (buf
, 0, 0, frame
, O7_REGNUM
, 0);
1204 pc
= PC_ADJUST (extract_address
1205 (buf
, REGISTER_RAW_SIZE (O7_REGNUM
)));
1208 write_register (PC_REGNUM
, pc
);
1209 write_register (NPC_REGNUM
, pc
+ 4);
1211 else if (fsr
.regs
[I7_REGNUM
])
1213 /* Return address in %i7 -- adjust it, then restore PC and NPC from it */
1214 pc
= PC_ADJUST ((CORE_ADDR
) read_memory_integer (fsr
.regs
[I7_REGNUM
],
1215 SPARC_INTREG_SIZE
));
1216 write_register (PC_REGNUM
, pc
);
1217 write_register (NPC_REGNUM
, pc
+ 4);
1219 flush_cached_frames ();
1222 /* On the Sun 4 under SunOS, the compile will leave a fake insn which
1223 encodes the structure size being returned. If we detect such
1224 a fake insn, step past it. */
1234 err
= target_read_memory (pc
+ 8, buf
, 4);
1235 insn
= extract_unsigned_integer (buf
, 4);
1236 if ((err
== 0) && (insn
& 0xffc00000) == 0)
1242 /* If pc is in a shared library trampoline, return its target.
1243 The SunOs 4.x linker rewrites the jump table entries for PIC
1244 compiled modules in the main executable to bypass the dynamic linker
1245 with jumps of the form
1248 and removes the corresponding jump table relocation entry in the
1249 dynamic relocations.
1250 find_solib_trampoline_target relies on the presence of the jump
1251 table relocation entry, so we have to detect these jump instructions
1255 sunos4_skip_trampoline_code (pc
)
1258 unsigned long insn1
;
1262 err
= target_read_memory (pc
, buf
, 4);
1263 insn1
= extract_unsigned_integer (buf
, 4);
1264 if (err
== 0 && (insn1
& 0xffc00000) == 0x03000000)
1266 unsigned long insn2
;
1268 err
= target_read_memory (pc
+ 4, buf
, 4);
1269 insn2
= extract_unsigned_integer (buf
, 4);
1270 if (err
== 0 && (insn2
& 0xffffe000) == 0x81c06000)
1272 CORE_ADDR target_pc
= (insn1
& 0x3fffff) << 10;
1273 int delta
= insn2
& 0x1fff;
1275 /* Sign extend the displacement. */
1278 return target_pc
+ delta
;
1281 return find_solib_trampoline_target (pc
);
1284 #ifdef USE_PROC_FS /* Target dependent support for /proc */
1286 /* The /proc interface divides the target machine's register set up into
1287 two different sets, the general register set (gregset) and the floating
1288 point register set (fpregset). For each set, there is an ioctl to get
1289 the current register set and another ioctl to set the current values.
1291 The actual structure passed through the ioctl interface is, of course,
1292 naturally machine dependent, and is different for each set of registers.
1293 For the sparc for example, the general register set is typically defined
1296 typedef int gregset_t[38];
1302 and the floating point set by:
1304 typedef struct prfpregset {
1307 double pr_dregs[16];
1312 u_char pr_q_entrysize;
1317 These routines provide the packing and unpacking of gregset_t and
1318 fpregset_t formatted data.
1322 /* Given a pointer to a general register set in /proc format (gregset_t *),
1323 unpack the register contents and supply them as gdb's idea of the current
1327 supply_gregset (gregsetp
)
1328 prgregset_t
*gregsetp
;
1331 register prgreg_t
*regp
= (prgreg_t
*) gregsetp
;
1332 static char zerobuf
[MAX_REGISTER_RAW_SIZE
] = {0};
1334 /* GDB register numbers for Gn, On, Ln, In all match /proc reg numbers. */
1335 for (regi
= G0_REGNUM
; regi
<= I7_REGNUM
; regi
++)
1337 supply_register (regi
, (char *) (regp
+ regi
));
1340 /* These require a bit more care. */
1341 supply_register (PS_REGNUM
, (char *) (regp
+ R_PS
));
1342 supply_register (PC_REGNUM
, (char *) (regp
+ R_PC
));
1343 supply_register (NPC_REGNUM
,(char *) (regp
+ R_nPC
));
1344 supply_register (Y_REGNUM
, (char *) (regp
+ R_Y
));
1346 /* Fill inaccessible registers with zero. */
1347 supply_register (WIM_REGNUM
, zerobuf
);
1348 supply_register (TBR_REGNUM
, zerobuf
);
1349 supply_register (CPS_REGNUM
, zerobuf
);
1353 fill_gregset (gregsetp
, regno
)
1354 prgregset_t
*gregsetp
;
1358 register prgreg_t
*regp
= (prgreg_t
*) gregsetp
;
1360 for (regi
= 0 ; regi
<= R_I7
; regi
++)
1362 if ((regno
== -1) || (regno
== regi
))
1364 *(regp
+ regi
) = *(int *) ®isters
[REGISTER_BYTE (regi
)];
1367 if ((regno
== -1) || (regno
== PS_REGNUM
))
1369 *(regp
+ R_PS
) = *(int *) ®isters
[REGISTER_BYTE (PS_REGNUM
)];
1371 if ((regno
== -1) || (regno
== PC_REGNUM
))
1373 *(regp
+ R_PC
) = *(int *) ®isters
[REGISTER_BYTE (PC_REGNUM
)];
1375 if ((regno
== -1) || (regno
== NPC_REGNUM
))
1377 *(regp
+ R_nPC
) = *(int *) ®isters
[REGISTER_BYTE (NPC_REGNUM
)];
1379 if ((regno
== -1) || (regno
== Y_REGNUM
))
1381 *(regp
+ R_Y
) = *(int *) ®isters
[REGISTER_BYTE (Y_REGNUM
)];
1385 #if defined (FP0_REGNUM)
1387 /* Given a pointer to a floating point register set in /proc format
1388 (fpregset_t *), unpack the register contents and supply them as gdb's
1389 idea of the current floating point register values. */
1392 supply_fpregset (fpregsetp
)
1393 prfpregset_t
*fpregsetp
;
1398 for (regi
= FP0_REGNUM
; regi
< FP_MAX_REGNUM
; regi
++)
1400 from
= (char *) &fpregsetp
->pr_fr
.pr_regs
[regi
-FP0_REGNUM
];
1401 supply_register (regi
, from
);
1403 supply_register (FPS_REGNUM
, (char *) &(fpregsetp
->pr_fsr
));
1406 /* Given a pointer to a floating point register set in /proc format
1407 (fpregset_t *), update the register specified by REGNO from gdb's idea
1408 of the current floating point register set. If REGNO is -1, update
1410 /* ??? This will probably need some changes for sparc64. */
1413 fill_fpregset (fpregsetp
, regno
)
1414 prfpregset_t
*fpregsetp
;
1421 for (regi
= FP0_REGNUM
; regi
< FP_MAX_REGNUM
; regi
++)
1423 if ((regno
== -1) || (regno
== regi
))
1425 from
= (char *) ®isters
[REGISTER_BYTE (regi
)];
1426 to
= (char *) &fpregsetp
->pr_fr
.pr_regs
[regi
-FP0_REGNUM
];
1427 memcpy (to
, from
, REGISTER_RAW_SIZE (regi
));
1430 if ((regno
== -1) || (regno
== FPS_REGNUM
))
1432 fpregsetp
->pr_fsr
= *(int *) ®isters
[REGISTER_BYTE (FPS_REGNUM
)];
1436 #endif /* defined (FP0_REGNUM) */
1438 #endif /* USE_PROC_FS */
1441 #ifdef GET_LONGJMP_TARGET
1443 /* Figure out where the longjmp will land. We expect that we have just entered
1444 longjmp and haven't yet setup the stack frame, so the args are still in the
1445 output regs. %o0 (O0_REGNUM) points at the jmp_buf structure from which we
1446 extract the pc (JB_PC) that we will land at. The pc is copied into ADDR.
1447 This routine returns true on success */
1450 get_longjmp_target (pc
)
1454 #define LONGJMP_TARGET_SIZE 4
1455 char buf
[LONGJMP_TARGET_SIZE
];
1457 jb_addr
= read_register (O0_REGNUM
);
1459 if (target_read_memory (jb_addr
+ JB_PC
* JB_ELEMENT_SIZE
, buf
,
1460 LONGJMP_TARGET_SIZE
))
1463 *pc
= extract_address (buf
, LONGJMP_TARGET_SIZE
);
1467 #endif /* GET_LONGJMP_TARGET */
1469 #ifdef STATIC_TRANSFORM_NAME
1470 /* SunPRO (3.0 at least), encodes the static variables. This is not
1471 related to C++ mangling, it is done for C too. */
1474 sunpro_static_transform_name (name
)
1480 /* For file-local statics there will be a dollar sign, a bunch
1481 of junk (the contents of which match a string given in the
1482 N_OPT), a period and the name. For function-local statics
1483 there will be a bunch of junk (which seems to change the
1484 second character from 'A' to 'B'), a period, the name of the
1485 function, and the name. So just skip everything before the
1487 p
= strrchr (name
, '.');
1493 #endif /* STATIC_TRANSFORM_NAME */
1496 /* Utilities for printing registers.
1497 Page numbers refer to the SPARC Architecture Manual. */
1499 static void dump_ccreg
PARAMS ((char *, int));
1502 dump_ccreg (reg
, val
)
1507 printf_unfiltered ("%s:%s,%s,%s,%s", reg
,
1508 val
& 8 ? "N" : "NN",
1509 val
& 4 ? "Z" : "NZ",
1510 val
& 2 ? "O" : "NO",
1511 val
& 1 ? "C" : "NC"
1522 case 4 : return "ASI_NUCLEUS";
1523 case 0x0c : return "ASI_NUCLEUS_LITTLE";
1524 case 0x10 : return "ASI_AS_IF_USER_PRIMARY";
1525 case 0x11 : return "ASI_AS_IF_USER_SECONDARY";
1526 case 0x18 : return "ASI_AS_IF_USER_PRIMARY_LITTLE";
1527 case 0x19 : return "ASI_AS_IF_USER_SECONDARY_LITTLE";
1528 case 0x80 : return "ASI_PRIMARY";
1529 case 0x81 : return "ASI_SECONDARY";
1530 case 0x82 : return "ASI_PRIMARY_NOFAULT";
1531 case 0x83 : return "ASI_SECONDARY_NOFAULT";
1532 case 0x88 : return "ASI_PRIMARY_LITTLE";
1533 case 0x89 : return "ASI_SECONDARY_LITTLE";
1534 case 0x8a : return "ASI_PRIMARY_NOFAULT_LITTLE";
1535 case 0x8b : return "ASI_SECONDARY_NOFAULT_LITTLE";
1536 default : return NULL
;
1540 /* PRINT_REGISTER_HOOK routine.
1541 Pretty print various registers. */
1542 /* FIXME: Would be nice if this did some fancy things for 32 bit sparc. */
1545 sparc_print_register_hook (regno
)
1550 /* Handle double/quad versions of lower 32 fp regs. */
1551 if (regno
>= FP0_REGNUM
&& regno
< FP0_REGNUM
+ 32
1552 && (regno
& 1) == 0)
1556 if (!read_relative_register_raw_bytes (regno
, value
)
1557 && !read_relative_register_raw_bytes (regno
+ 1, value
+ 4))
1559 printf_unfiltered ("\t");
1560 print_floating (value
, builtin_type_double
, gdb_stdout
);
1562 #if 0 /* FIXME: gdb doesn't handle long doubles */
1563 if ((regno
& 3) == 0)
1565 if (!read_relative_register_raw_bytes (regno
+ 2, value
+ 8)
1566 && !read_relative_register_raw_bytes (regno
+ 3, value
+ 12))
1568 printf_unfiltered ("\t");
1569 print_floating (value
, builtin_type_long_double
, gdb_stdout
);
1576 #if 0 /* FIXME: gdb doesn't handle long doubles */
1577 /* Print upper fp regs as long double if appropriate. */
1578 if (regno
>= FP0_REGNUM
+ 32 && regno
< FP_MAX_REGNUM
1579 /* We test for even numbered regs and not a multiple of 4 because
1580 the upper fp regs are recorded as doubles. */
1581 && (regno
& 1) == 0)
1585 if (!read_relative_register_raw_bytes (regno
, value
)
1586 && !read_relative_register_raw_bytes (regno
+ 1, value
+ 8))
1588 printf_unfiltered ("\t");
1589 print_floating (value
, builtin_type_long_double
, gdb_stdout
);
1595 /* FIXME: Some of these are priviledged registers.
1596 Not sure how they should be handled. */
1598 #define BITS(n, mask) ((int) (((val) >> (n)) & (mask)))
1600 val
= read_register (regno
);
1605 #ifdef GDB_TARGET_IS_SPARC64
1607 printf_unfiltered("\t");
1608 dump_ccreg ("xcc", val
>> 4);
1609 printf_unfiltered(", ");
1610 dump_ccreg ("icc", val
& 15);
1613 printf ("\tfef:%d, du:%d, dl:%d",
1614 BITS (2, 1), BITS (1, 1), BITS (0, 1));
1618 static char *fcc
[4] = { "=", "<", ">", "?" };
1619 static char *rd
[4] = { "N", "0", "+", "-" };
1620 /* Long, yes, but I'd rather leave it as is and use a wide screen. */
1621 printf ("\t0:%s, 1:%s, 2:%s, 3:%s, rd:%s, tem:%d, ns:%d, ver:%d, ftt:%d, qne:%d, aexc:%d, cexc:%d",
1622 fcc
[BITS (10, 3)], fcc
[BITS (32, 3)],
1623 fcc
[BITS (34, 3)], fcc
[BITS (36, 3)],
1624 rd
[BITS (30, 3)], BITS (23, 31), BITS (22, 1), BITS (17, 7),
1625 BITS (14, 7), BITS (13, 1), BITS (5, 31), BITS (0, 31));
1630 char *asi
= decode_asi (val
);
1632 printf ("\t%s", asi
);
1636 printf ("\tmanuf:%d, impl:%d, mask:%d, maxtl:%d, maxwin:%d",
1637 BITS (48, 0xffff), BITS (32, 0xffff),
1638 BITS (24, 0xff), BITS (8, 0xff), BITS (0, 31));
1640 case PSTATE_REGNUM
:
1642 static char *mm
[4] = { "tso", "pso", "rso", "?" };
1643 printf ("\tcle:%d, tle:%d, mm:%s, red:%d, pef:%d, am:%d, priv:%d, ie:%d, ag:%d",
1644 BITS (9, 1), BITS (8, 1), mm
[BITS (6, 3)], BITS (5, 1),
1645 BITS (4, 1), BITS (3, 1), BITS (2, 1), BITS (1, 1),
1649 case TSTATE_REGNUM
:
1650 /* FIXME: print all 4? */
1653 /* FIXME: print all 4? */
1656 /* FIXME: print all 4? */
1659 /* FIXME: print all 4? */
1661 case WSTATE_REGNUM
:
1662 printf ("\tother:%d, normal:%d", BITS (3, 7), BITS (0, 7));
1665 printf ("\t%d", BITS (0, 31));
1667 case CANSAVE_REGNUM
:
1668 printf ("\t%-2d before spill", BITS (0, 31));
1670 case CANRESTORE_REGNUM
:
1671 printf ("\t%-2d before fill", BITS (0, 31));
1673 case CLEANWIN_REGNUM
:
1674 printf ("\t%-2d before clean", BITS (0, 31));
1676 case OTHERWIN_REGNUM
:
1677 printf ("\t%d", BITS (0, 31));
1681 printf ("\ticc:%c%c%c%c, pil:%d, s:%d, ps:%d, et:%d, cwp:%d",
1682 BITS (23, 1) ? 'N' : '-', BITS (22, 1) ? 'Z' : '-',
1683 BITS (21, 1) ? 'V' : '-', BITS (20, 1) ? 'C' : '-',
1684 BITS (8, 15), BITS (7, 1), BITS (6, 1), BITS (5, 1),
1689 static char *fcc
[4] = { "=", "<", ">", "?" };
1690 static char *rd
[4] = { "N", "0", "+", "-" };
1691 /* Long, yes, but I'd rather leave it as is and use a wide screen. */
1692 printf ("\trd:%s, tem:%d, ns:%d, ver:%d, ftt:%d, qne:%d, "
1693 "fcc:%s, aexc:%d, cexc:%d",
1694 rd
[BITS (30, 3)], BITS (23, 31), BITS (22, 1), BITS (17, 7),
1695 BITS (14, 7), BITS (13, 1), fcc
[BITS (10, 3)], BITS (5, 31),
1700 #endif /* GDB_TARGET_IS_SPARC64 */
1707 gdb_print_insn_sparc (memaddr
, info
)
1709 disassemble_info
*info
;
1711 /* It's necessary to override mach again because print_insn messes it up. */
1712 info
->mach
= TM_PRINT_INSN_MACH
;
1713 return print_insn_sparc (memaddr
, info
);
1716 /* The SPARC passes the arguments on the stack; arguments smaller
1717 than an int are promoted to an int. */
1720 sparc_push_arguments (nargs
, args
, sp
, struct_return
, struct_addr
)
1725 CORE_ADDR struct_addr
;
1728 int accumulate_size
= 0;
1735 struct sparc_arg
*sparc_args
=
1736 (struct sparc_arg
*)alloca (nargs
* sizeof (struct sparc_arg
));
1737 struct sparc_arg
*m_arg
;
1739 /* Promote arguments if necessary, and calculate their stack offsets
1741 for (i
= 0, m_arg
= sparc_args
; i
< nargs
; i
++, m_arg
++)
1743 value_ptr arg
= args
[i
];
1744 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
1745 /* Cast argument to long if necessary as the compiler does it too. */
1746 switch (TYPE_CODE (arg_type
))
1749 case TYPE_CODE_BOOL
:
1750 case TYPE_CODE_CHAR
:
1751 case TYPE_CODE_RANGE
:
1752 case TYPE_CODE_ENUM
:
1753 if (TYPE_LENGTH (arg_type
) < TYPE_LENGTH (builtin_type_long
))
1755 arg_type
= builtin_type_long
;
1756 arg
= value_cast (arg_type
, arg
);
1762 m_arg
->len
= TYPE_LENGTH (arg_type
);
1763 m_arg
->offset
= accumulate_size
;
1764 accumulate_size
= (accumulate_size
+ m_arg
->len
+ 3) & ~3;
1765 m_arg
->contents
= VALUE_CONTENTS(arg
);
1768 /* Make room for the arguments on the stack. */
1769 accumulate_size
+= CALL_DUMMY_STACK_ADJUST
;
1770 sp
= ((sp
- accumulate_size
) & ~7) + CALL_DUMMY_STACK_ADJUST
;
1772 /* `Push' arguments on the stack. */
1773 for (i
= nargs
; m_arg
--, --i
>= 0; )
1774 write_memory(sp
+ m_arg
->offset
, m_arg
->contents
, m_arg
->len
);
1780 /* Extract from an array REGBUF containing the (raw) register state
1781 a function return value of type TYPE, and copy that, in virtual format,
1785 sparc_extract_return_value (type
, regbuf
, valbuf
)
1790 int typelen
= TYPE_LENGTH (type
);
1791 int regsize
= REGISTER_RAW_SIZE (O0_REGNUM
);
1793 if (TYPE_CODE (type
) == TYPE_CODE_FLT
&& SPARC_HAS_FPU
)
1794 memcpy (valbuf
, ®buf
[REGISTER_BYTE (FP0_REGNUM
)], typelen
);
1797 ®buf
[O0_REGNUM
* regsize
+
1799 || TARGET_BYTE_ORDER
== LITTLE_ENDIAN
? 0
1800 : regsize
- typelen
)],
1805 /* Write into appropriate registers a function return value
1806 of type TYPE, given in virtual format. On SPARCs with FPUs,
1807 float values are returned in %f0 (and %f1). In all other cases,
1808 values are returned in register %o0. */
1811 sparc_store_return_value (type
, valbuf
)
1816 char buffer
[MAX_REGISTER_RAW_SIZE
];
1818 if (TYPE_CODE (type
) == TYPE_CODE_FLT
&& SPARC_HAS_FPU
)
1819 /* Floating-point values are returned in the register pair */
1820 /* formed by %f0 and %f1 (doubles are, anyway). */
1823 /* Other values are returned in register %o0. */
1826 /* Add leading zeros to the value. */
1827 if (TYPE_LENGTH (type
) < REGISTER_RAW_SIZE(regno
))
1829 bzero (buffer
, REGISTER_RAW_SIZE(regno
));
1830 memcpy (buffer
+ REGISTER_RAW_SIZE(regno
) - TYPE_LENGTH (type
), valbuf
,
1831 TYPE_LENGTH (type
));
1832 write_register_bytes (REGISTER_BYTE (regno
), buffer
,
1833 REGISTER_RAW_SIZE(regno
));
1836 write_register_bytes (REGISTER_BYTE (regno
), valbuf
, TYPE_LENGTH (type
));
1840 /* Insert the function address into a call dummy instruction sequence
1843 For structs and unions, if the function was compiled with Sun cc,
1844 it expects 'unimp' after the call. But gcc doesn't use that
1845 (twisted) convention. So leave a nop there for gcc (FIX_CALL_DUMMY
1846 can assume it is operating on a pristine CALL_DUMMY, not one that
1847 has already been customized for a different function). */
1850 sparc_fix_call_dummy (dummy
, pc
, fun
, value_type
, using_gcc
)
1854 struct type
*value_type
;
1859 /* Store the relative adddress of the target function into the
1860 'call' instruction. */
1861 store_unsigned_integer (dummy
+ CALL_DUMMY_CALL_OFFSET
, 4,
1863 | (((fun
- (pc
+ CALL_DUMMY_CALL_OFFSET
)) >> 2)
1866 /* Comply with strange Sun cc calling convention for struct-returning
1869 && (TYPE_CODE (value_type
) == TYPE_CODE_STRUCT
1870 || TYPE_CODE (value_type
) == TYPE_CODE_UNION
))
1871 store_unsigned_integer (dummy
+ CALL_DUMMY_CALL_OFFSET
+ 8, 4,
1872 TYPE_LENGTH (value_type
) & 0x1fff);
1874 #ifndef GDB_TARGET_IS_SPARC64
1875 /* If this is not a simulator target, change the first four instructions
1876 of the call dummy to NOPs. Those instructions include a 'save'
1877 instruction and are designed to work around problems with register
1878 window flushing in the simulator. */
1879 if (strcmp (target_shortname
, "sim") != 0)
1881 for (i
= 0; i
< 4; i
++)
1882 store_unsigned_integer (dummy
+ (i
* 4), 4, 0x01000000);
1886 /* If this is a bi-endian target, GDB has written the call dummy
1887 in little-endian order. We must byte-swap it back to big-endian. */
1890 for (i
= 0; i
< CALL_DUMMY_LENGTH
; i
+= 4)
1892 char tmp
= dummy
[i
];
1893 dummy
[i
] = dummy
[i
+3];
1896 dummy
[i
+1] = dummy
[i
+2];
1903 /* Set target byte order based on machine type. */
1906 sparc_target_architecture_hook (ap
)
1907 const bfd_arch_info_type
*ap
;
1911 if (ap
->mach
== bfd_mach_sparc_sparclite_le
)
1913 if (TARGET_BYTE_ORDER_SELECTABLE_P
)
1915 target_byte_order
= LITTLE_ENDIAN
;
1920 warning ("This GDB does not support little endian sparclite.");
1930 _initialize_sparc_tdep ()
1932 tm_print_insn
= gdb_print_insn_sparc
;
1933 tm_print_insn_info
.mach
= TM_PRINT_INSN_MACH
; /* Selects sparc/sparclite */
1934 target_architecture_hook
= sparc_target_architecture_hook
;
1938 #ifdef GDB_TARGET_IS_SPARC64
1940 /* Compensate for stack bias. Note that we currently don't handle mixed
1945 CORE_ADDR sp
= read_register (SP_REGNUM
);
1955 CORE_ADDR fp
= read_register (FP_REGNUM
);
1963 sparc64_write_sp (val
)
1966 CORE_ADDR oldsp
= read_register (SP_REGNUM
);
1968 write_register (SP_REGNUM
, val
- 2047);
1970 write_register (SP_REGNUM
, val
);
1974 sparc64_write_fp (val
)
1977 CORE_ADDR oldfp
= read_register (FP_REGNUM
);
1979 write_register (FP_REGNUM
, val
- 2047);
1981 write_register (FP_REGNUM
, val
);
1984 /* The SPARC 64 ABI passes floating-point arguments in FP0-31. They are
1985 also copied onto the stack in the correct places. */
1988 sp64_push_arguments (nargs
, args
, sp
, struct_return
, struct_retaddr
)
1992 unsigned char struct_return
;
1993 CORE_ADDR struct_retaddr
;
1999 sp
= (sp
& ~(((unsigned long)TYPE_LENGTH (builtin_type_long
)) - 1UL));
2001 /* Figure out how much space we'll need. */
2002 for (x
= nargs
- 1; x
>= 0; x
--)
2004 int len
= TYPE_LENGTH (check_typedef (VALUE_TYPE (args
[x
])));
2005 value_ptr copyarg
= args
[x
];
2008 /* This code is, of course, no longer correct. */
2009 if (copylen
< TYPE_LENGTH (builtin_type_long
))
2011 copyarg
= value_cast(builtin_type_long
, copyarg
);
2012 copylen
= TYPE_LENGTH (builtin_type_long
);
2021 /* Now write the arguments onto the stack, while writing FP arguments
2022 into the FP registers. */
2023 for (x
= 0; x
< nargs
; x
++)
2025 int len
= TYPE_LENGTH (check_typedef (VALUE_TYPE (args
[x
])));
2026 value_ptr copyarg
= args
[x
];
2029 /* This code is, of course, no longer correct. */
2030 if (copylen
< TYPE_LENGTH (builtin_type_long
))
2032 copyarg
= value_cast(builtin_type_long
, copyarg
);
2033 copylen
= TYPE_LENGTH (builtin_type_long
);
2035 write_memory (tempsp
, VALUE_CONTENTS (copyarg
), copylen
);
2037 if (TYPE_CODE (VALUE_TYPE (args
[x
])) == TYPE_CODE_FLT
&& regnum
< 32)
2039 /* This gets copied into a FP register. */
2040 int nextreg
= regnum
+ 2;
2041 char *data
= VALUE_CONTENTS (args
[x
]);
2042 /* Floats go into the lower half of a FP register pair; quads
2050 write_register_bytes (REGISTER_BYTE (FP0_REGNUM
+ regnum
),
2059 /* Values <= 32 bytes are returned in o0-o3 (floating-point values are
2060 returned in f0-f3). */
2062 sparc64_extract_return_value (type
, regbuf
, valbuf
, bitoffset
)
2068 int typelen
= TYPE_LENGTH (type
);
2069 int regsize
= REGISTER_RAW_SIZE (O0_REGNUM
);
2071 if (TYPE_CODE (type
) == TYPE_CODE_FLT
&& SPARC_HAS_FPU
)
2073 memcpy (valbuf
, ®buf
[REGISTER_BYTE (FP0_REGNUM
)], typelen
);
2077 if (TYPE_CODE (type
) != TYPE_CODE_STRUCT
2078 || (TYPE_LENGTH (type
) > 32))
2081 ®buf
[O0_REGNUM
* regsize
+
2082 (typelen
>= regsize
? 0 : regsize
- typelen
)],
2088 char *o0
= ®buf
[O0_REGNUM
* regsize
];
2089 char *f0
= ®buf
[FP0_REGNUM
* regsize
];
2092 for (x
= 0; x
< TYPE_NFIELDS (type
); x
++)
2094 struct field
*f
= &TYPE_FIELDS(type
)[x
];
2095 /* FIXME: We may need to handle static fields here. */
2096 int whichreg
= (f
->loc
.bitpos
+ bitoffset
) / 32;
2097 int remainder
= ((f
->loc
.bitpos
+ bitoffset
) % 32) / 8;
2098 int where
= (f
->loc
.bitpos
+ bitoffset
) / 8;
2099 int size
= TYPE_LENGTH (f
->type
);
2100 int typecode
= TYPE_CODE (f
->type
);
2102 if (typecode
== TYPE_CODE_STRUCT
)
2104 sparc64_extract_return_value (f
->type
,
2107 bitoffset
+ f
->loc
.bitpos
);
2109 else if (typecode
== TYPE_CODE_FLT
)
2111 memcpy (valbuf
+ where
, &f0
[whichreg
* 4] + remainder
, size
);
2115 memcpy (valbuf
+ where
, &o0
[whichreg
* 4] + remainder
, size
);