1 /* Target-dependent code for SPARC.
3 Copyright (C) 2003-2012 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "arch-utils.h"
23 #include "dwarf2-frame.h"
24 #include "floatformat.h"
26 #include "frame-base.h"
27 #include "frame-unwind.h"
38 #include "gdb_assert.h"
39 #include "gdb_string.h"
41 #include "sparc-tdep.h"
45 /* This file implements the SPARC 32-bit ABI as defined by the section
46 "Low-Level System Information" of the SPARC Compliance Definition
47 (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC. The SCD
48 lists changes with respect to the original 32-bit psABI as defined
49 in the "System V ABI, SPARC Processor Supplement".
51 Note that if we talk about SunOS, we mean SunOS 4.x, which was
52 BSD-based, which is sometimes (retroactively?) referred to as
53 Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and
54 above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9
55 suffering from severe version number inflation). Solaris 2.x is
56 also known as SunOS 5.x, since that's what uname(1) says. Solaris
59 /* Please use the sparc32_-prefix for 32-bit specific code, the
60 sparc64_-prefix for 64-bit specific code and the sparc_-prefix for
61 code that can handle both. The 64-bit specific code lives in
62 sparc64-tdep.c; don't add any here. */
64 /* The SPARC Floating-Point Quad-Precision format is similar to
65 big-endian IA-64 Quad-Precision format. */
66 #define floatformats_sparc_quad floatformats_ia64_quad
68 /* The stack pointer is offset from the stack frame by a BIAS of 2047
69 (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC
70 hosts, so undefine it first. */
74 /* Macros to extract fields from SPARC instructions. */
75 #define X_OP(i) (((i) >> 30) & 0x3)
76 #define X_RD(i) (((i) >> 25) & 0x1f)
77 #define X_A(i) (((i) >> 29) & 1)
78 #define X_COND(i) (((i) >> 25) & 0xf)
79 #define X_OP2(i) (((i) >> 22) & 0x7)
80 #define X_IMM22(i) ((i) & 0x3fffff)
81 #define X_OP3(i) (((i) >> 19) & 0x3f)
82 #define X_RS1(i) (((i) >> 14) & 0x1f)
83 #define X_RS2(i) ((i) & 0x1f)
84 #define X_I(i) (((i) >> 13) & 1)
85 /* Sign extension macros. */
86 #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000)
87 #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000)
88 #define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000)
90 /* Fetch the instruction at PC. Instructions are always big-endian
91 even if the processor operates in little-endian mode. */
94 sparc_fetch_instruction (CORE_ADDR pc
)
100 /* If we can't read the instruction at PC, return zero. */
101 if (target_read_memory (pc
, buf
, sizeof (buf
)))
105 for (i
= 0; i
< sizeof (buf
); i
++)
106 insn
= (insn
<< 8) | buf
[i
];
111 /* Return non-zero if the instruction corresponding to PC is an "unimp"
115 sparc_is_unimp_insn (CORE_ADDR pc
)
117 const unsigned long insn
= sparc_fetch_instruction (pc
);
119 return ((insn
& 0xc1c00000) == 0);
122 /* OpenBSD/sparc includes StackGhost, which according to the author's
123 website http://stackghost.cerias.purdue.edu "... transparently and
124 automatically protects applications' stack frames; more
125 specifically, it guards the return pointers. The protection
126 mechanisms require no application source or binary modification and
127 imposes only a negligible performance penalty."
129 The same website provides the following description of how
132 "StackGhost interfaces with the kernel trap handler that would
133 normally write out registers to the stack and the handler that
134 would read them back in. By XORing a cookie into the
135 return-address saved in the user stack when it is actually written
136 to the stack, and then XOR it out when the return-address is pulled
137 from the stack, StackGhost can cause attacker corrupted return
138 pointers to behave in a manner the attacker cannot predict.
139 StackGhost can also use several unused bits in the return pointer
140 to detect a smashed return pointer and abort the process."
142 For GDB this means that whenever we're reading %i7 from a stack
143 frame's window save area, we'll have to XOR the cookie.
145 More information on StackGuard can be found on in:
147 Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated
148 Stack Protection." 2001. Published in USENIX Security Symposium
151 /* Fetch StackGhost Per-Process XOR cookie. */
154 sparc_fetch_wcookie (struct gdbarch
*gdbarch
)
156 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
157 struct target_ops
*ops
= ¤t_target
;
161 len
= target_read (ops
, TARGET_OBJECT_WCOOKIE
, NULL
, buf
, 0, 8);
165 /* We should have either an 32-bit or an 64-bit cookie. */
166 gdb_assert (len
== 4 || len
== 8);
168 return extract_unsigned_integer (buf
, len
, byte_order
);
172 /* The functions on this page are intended to be used to classify
173 function arguments. */
175 /* Check whether TYPE is "Integral or Pointer". */
178 sparc_integral_or_pointer_p (const struct type
*type
)
180 int len
= TYPE_LENGTH (type
);
182 switch (TYPE_CODE (type
))
188 case TYPE_CODE_RANGE
:
189 /* We have byte, half-word, word and extended-word/doubleword
190 integral types. The doubleword is an extension to the
191 original 32-bit ABI by the SCD 2.4.x. */
192 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
195 /* Allow either 32-bit or 64-bit pointers. */
196 return (len
== 4 || len
== 8);
204 /* Check whether TYPE is "Floating". */
207 sparc_floating_p (const struct type
*type
)
209 switch (TYPE_CODE (type
))
213 int len
= TYPE_LENGTH (type
);
214 return (len
== 4 || len
== 8 || len
== 16);
223 /* Check whether TYPE is "Complex Floating". */
226 sparc_complex_floating_p (const struct type
*type
)
228 switch (TYPE_CODE (type
))
230 case TYPE_CODE_COMPLEX
:
232 int len
= TYPE_LENGTH (type
);
233 return (len
== 8 || len
== 16 || len
== 32);
242 /* Check whether TYPE is "Structure or Union".
244 In terms of Ada subprogram calls, arrays are treated the same as
245 struct and union types. So this function also returns non-zero
249 sparc_structure_or_union_p (const struct type
*type
)
251 switch (TYPE_CODE (type
))
253 case TYPE_CODE_STRUCT
:
254 case TYPE_CODE_UNION
:
255 case TYPE_CODE_ARRAY
:
264 /* Register information. */
266 static const char *sparc32_register_names
[] =
268 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
269 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
270 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
271 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
273 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
274 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
275 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
276 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
278 "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr"
281 /* Total number of registers. */
282 #define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names)
284 /* We provide the aliases %d0..%d30 for the floating registers as
285 "psuedo" registers. */
287 static const char *sparc32_pseudo_register_names
[] =
289 "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14",
290 "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30"
293 /* Total number of pseudo registers. */
294 #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names)
296 /* Return the name of register REGNUM. */
299 sparc32_register_name (struct gdbarch
*gdbarch
, int regnum
)
301 if (regnum
>= 0 && regnum
< SPARC32_NUM_REGS
)
302 return sparc32_register_names
[regnum
];
304 if (regnum
< SPARC32_NUM_REGS
+ SPARC32_NUM_PSEUDO_REGS
)
305 return sparc32_pseudo_register_names
[regnum
- SPARC32_NUM_REGS
];
310 /* Construct types for ISA-specific registers. */
313 sparc_psr_type (struct gdbarch
*gdbarch
)
315 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
317 if (!tdep
->sparc_psr_type
)
321 type
= arch_flags_type (gdbarch
, "builtin_type_sparc_psr", 4);
322 append_flags_type_flag (type
, 5, "ET");
323 append_flags_type_flag (type
, 6, "PS");
324 append_flags_type_flag (type
, 7, "S");
325 append_flags_type_flag (type
, 12, "EF");
326 append_flags_type_flag (type
, 13, "EC");
328 tdep
->sparc_psr_type
= type
;
331 return tdep
->sparc_psr_type
;
335 sparc_fsr_type (struct gdbarch
*gdbarch
)
337 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
339 if (!tdep
->sparc_fsr_type
)
343 type
= arch_flags_type (gdbarch
, "builtin_type_sparc_fsr", 4);
344 append_flags_type_flag (type
, 0, "NXA");
345 append_flags_type_flag (type
, 1, "DZA");
346 append_flags_type_flag (type
, 2, "UFA");
347 append_flags_type_flag (type
, 3, "OFA");
348 append_flags_type_flag (type
, 4, "NVA");
349 append_flags_type_flag (type
, 5, "NXC");
350 append_flags_type_flag (type
, 6, "DZC");
351 append_flags_type_flag (type
, 7, "UFC");
352 append_flags_type_flag (type
, 8, "OFC");
353 append_flags_type_flag (type
, 9, "NVC");
354 append_flags_type_flag (type
, 22, "NS");
355 append_flags_type_flag (type
, 23, "NXM");
356 append_flags_type_flag (type
, 24, "DZM");
357 append_flags_type_flag (type
, 25, "UFM");
358 append_flags_type_flag (type
, 26, "OFM");
359 append_flags_type_flag (type
, 27, "NVM");
361 tdep
->sparc_fsr_type
= type
;
364 return tdep
->sparc_fsr_type
;
367 /* Return the GDB type object for the "standard" data type of data in
371 sparc32_register_type (struct gdbarch
*gdbarch
, int regnum
)
373 if (regnum
>= SPARC_F0_REGNUM
&& regnum
<= SPARC_F31_REGNUM
)
374 return builtin_type (gdbarch
)->builtin_float
;
376 if (regnum
>= SPARC32_D0_REGNUM
&& regnum
<= SPARC32_D30_REGNUM
)
377 return builtin_type (gdbarch
)->builtin_double
;
379 if (regnum
== SPARC_SP_REGNUM
|| regnum
== SPARC_FP_REGNUM
)
380 return builtin_type (gdbarch
)->builtin_data_ptr
;
382 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== SPARC32_NPC_REGNUM
)
383 return builtin_type (gdbarch
)->builtin_func_ptr
;
385 if (regnum
== SPARC32_PSR_REGNUM
)
386 return sparc_psr_type (gdbarch
);
388 if (regnum
== SPARC32_FSR_REGNUM
)
389 return sparc_fsr_type (gdbarch
);
391 return builtin_type (gdbarch
)->builtin_int32
;
394 static enum register_status
395 sparc32_pseudo_register_read (struct gdbarch
*gdbarch
,
396 struct regcache
*regcache
,
397 int regnum
, gdb_byte
*buf
)
399 enum register_status status
;
401 gdb_assert (regnum
>= SPARC32_D0_REGNUM
&& regnum
<= SPARC32_D30_REGNUM
);
403 regnum
= SPARC_F0_REGNUM
+ 2 * (regnum
- SPARC32_D0_REGNUM
);
404 status
= regcache_raw_read (regcache
, regnum
, buf
);
405 if (status
== REG_VALID
)
406 status
= regcache_raw_read (regcache
, regnum
+ 1, buf
+ 4);
411 sparc32_pseudo_register_write (struct gdbarch
*gdbarch
,
412 struct regcache
*regcache
,
413 int regnum
, const gdb_byte
*buf
)
415 gdb_assert (regnum
>= SPARC32_D0_REGNUM
&& regnum
<= SPARC32_D30_REGNUM
);
417 regnum
= SPARC_F0_REGNUM
+ 2 * (regnum
- SPARC32_D0_REGNUM
);
418 regcache_raw_write (regcache
, regnum
, buf
);
419 regcache_raw_write (regcache
, regnum
+ 1, buf
+ 4);
424 sparc32_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR address
)
426 /* The ABI requires double-word alignment. */
427 return address
& ~0x7;
431 sparc32_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
433 struct value
**args
, int nargs
,
434 struct type
*value_type
,
435 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
436 struct regcache
*regcache
)
438 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
443 if (using_struct_return (gdbarch
, NULL
, value_type
))
447 /* This is an UNIMP instruction. */
448 store_unsigned_integer (buf
, 4, byte_order
,
449 TYPE_LENGTH (value_type
) & 0x1fff);
450 write_memory (sp
- 8, buf
, 4);
458 sparc32_store_arguments (struct regcache
*regcache
, int nargs
,
459 struct value
**args
, CORE_ADDR sp
,
460 int struct_return
, CORE_ADDR struct_addr
)
462 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
463 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
464 /* Number of words in the "parameter array". */
465 int num_elements
= 0;
469 for (i
= 0; i
< nargs
; i
++)
471 struct type
*type
= value_type (args
[i
]);
472 int len
= TYPE_LENGTH (type
);
474 if (sparc_structure_or_union_p (type
)
475 || (sparc_floating_p (type
) && len
== 16)
476 || sparc_complex_floating_p (type
))
478 /* Structure, Union and Quad-Precision Arguments. */
481 /* Use doubleword alignment for these values. That's always
482 correct, and wasting a few bytes shouldn't be a problem. */
485 write_memory (sp
, value_contents (args
[i
]), len
);
486 args
[i
] = value_from_pointer (lookup_pointer_type (type
), sp
);
489 else if (sparc_floating_p (type
))
491 /* Floating arguments. */
492 gdb_assert (len
== 4 || len
== 8);
493 num_elements
+= (len
/ 4);
497 /* Integral and pointer arguments. */
498 gdb_assert (sparc_integral_or_pointer_p (type
));
501 args
[i
] = value_cast (builtin_type (gdbarch
)->builtin_int32
,
503 num_elements
+= ((len
+ 3) / 4);
507 /* Always allocate at least six words. */
508 sp
-= max (6, num_elements
) * 4;
510 /* The psABI says that "Software convention requires space for the
511 struct/union return value pointer, even if the word is unused." */
514 /* The psABI says that "Although software convention and the
515 operating system require every stack frame to be doubleword
519 for (i
= 0; i
< nargs
; i
++)
521 const bfd_byte
*valbuf
= value_contents (args
[i
]);
522 struct type
*type
= value_type (args
[i
]);
523 int len
= TYPE_LENGTH (type
);
525 gdb_assert (len
== 4 || len
== 8);
529 int regnum
= SPARC_O0_REGNUM
+ element
;
531 regcache_cooked_write (regcache
, regnum
, valbuf
);
532 if (len
> 4 && element
< 5)
533 regcache_cooked_write (regcache
, regnum
+ 1, valbuf
+ 4);
536 /* Always store the argument in memory. */
537 write_memory (sp
+ 4 + element
* 4, valbuf
, len
);
541 gdb_assert (element
== num_elements
);
547 store_unsigned_integer (buf
, 4, byte_order
, struct_addr
);
548 write_memory (sp
, buf
, 4);
555 sparc32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
556 struct regcache
*regcache
, CORE_ADDR bp_addr
,
557 int nargs
, struct value
**args
, CORE_ADDR sp
,
558 int struct_return
, CORE_ADDR struct_addr
)
560 CORE_ADDR call_pc
= (struct_return
? (bp_addr
- 12) : (bp_addr
- 8));
562 /* Set return address. */
563 regcache_cooked_write_unsigned (regcache
, SPARC_O7_REGNUM
, call_pc
);
565 /* Set up function arguments. */
566 sp
= sparc32_store_arguments (regcache
, nargs
, args
, sp
,
567 struct_return
, struct_addr
);
569 /* Allocate the 16-word window save area. */
572 /* Stack should be doubleword aligned at this point. */
573 gdb_assert (sp
% 8 == 0);
575 /* Finally, update the stack pointer. */
576 regcache_cooked_write_unsigned (regcache
, SPARC_SP_REGNUM
, sp
);
582 /* Use the program counter to determine the contents and size of a
583 breakpoint instruction. Return a pointer to a string of bytes that
584 encode a breakpoint instruction, store the length of the string in
585 *LEN and optionally adjust *PC to point to the correct memory
586 location for inserting the breakpoint. */
588 static const gdb_byte
*
589 sparc_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pc
, int *len
)
591 static const gdb_byte break_insn
[] = { 0x91, 0xd0, 0x20, 0x01 };
593 *len
= sizeof (break_insn
);
598 /* Allocate and initialize a frame cache. */
600 static struct sparc_frame_cache
*
601 sparc_alloc_frame_cache (void)
603 struct sparc_frame_cache
*cache
;
606 cache
= FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache
);
612 /* Frameless until proven otherwise. */
613 cache
->frameless_p
= 1;
614 cache
->frame_offset
= 0;
615 cache
->saved_regs_mask
= 0;
616 cache
->copied_regs_mask
= 0;
617 cache
->struct_return_p
= 0;
622 /* GCC generates several well-known sequences of instructions at the begining
623 of each function prologue when compiling with -fstack-check. If one of
624 such sequences starts at START_PC, then return the address of the
625 instruction immediately past this sequence. Otherwise, return START_PC. */
628 sparc_skip_stack_check (const CORE_ADDR start_pc
)
630 CORE_ADDR pc
= start_pc
;
632 int offset_stack_checking_sequence
= 0;
633 int probing_loop
= 0;
635 /* With GCC, all stack checking sequences begin with the same two
636 instructions, plus an optional one in the case of a probing loop:
638 sethi <some immediate>, %g1
643 sethi <some immediate>, %g1
644 sethi <some immediate>, %g4
649 sethi <some immediate>, %g1
651 sethi <some immediate>, %g4
653 If the optional instruction is found (setting g4), assume that a
654 probing loop will follow. */
656 /* sethi <some immediate>, %g1 */
657 insn
= sparc_fetch_instruction (pc
);
659 if (!(X_OP (insn
) == 0 && X_OP2 (insn
) == 0x4 && X_RD (insn
) == 1))
662 /* optional: sethi <some immediate>, %g4 */
663 insn
= sparc_fetch_instruction (pc
);
665 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 0x4 && X_RD (insn
) == 4)
668 insn
= sparc_fetch_instruction (pc
);
672 /* sub %sp, %g1, %g1 */
673 if (!(X_OP (insn
) == 2 && X_OP3 (insn
) == 0x4 && !X_I(insn
)
674 && X_RD (insn
) == 1 && X_RS1 (insn
) == 14 && X_RS2 (insn
) == 1))
677 insn
= sparc_fetch_instruction (pc
);
680 /* optional: sethi <some immediate>, %g4 */
681 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 0x4 && X_RD (insn
) == 4)
684 insn
= sparc_fetch_instruction (pc
);
688 /* First possible sequence:
689 [first two instructions above]
690 clr [%g1 - some immediate] */
692 /* clr [%g1 - some immediate] */
693 if (X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && X_I(insn
)
694 && X_RS1 (insn
) == 1 && X_RD (insn
) == 0)
696 /* Valid stack-check sequence, return the new PC. */
700 /* Second possible sequence: A small number of probes.
701 [first two instructions above]
703 add %g1, -<some immediate>, %g1
705 [repeat the two instructions above any (small) number of times]
706 clr [%g1 - some immediate] */
709 else if (X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && !X_I(insn
)
710 && X_RS1 (insn
) == 1 && X_RD (insn
) == 0)
714 /* add %g1, -<some immediate>, %g1 */
715 insn
= sparc_fetch_instruction (pc
);
717 if (!(X_OP (insn
) == 2 && X_OP3(insn
) == 0 && X_I(insn
)
718 && X_RS1 (insn
) == 1 && X_RD (insn
) == 1))
722 insn
= sparc_fetch_instruction (pc
);
724 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && !X_I(insn
)
725 && X_RD (insn
) == 0 && X_RS1 (insn
) == 1))
729 /* clr [%g1 - some immediate] */
730 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && X_I(insn
)
731 && X_RS1 (insn
) == 1 && X_RD (insn
) == 0))
734 /* We found a valid stack-check sequence, return the new PC. */
738 /* Third sequence: A probing loop.
739 [first three instructions above]
743 add %g1, -<some immediate>, %g1
747 And an optional last probe for the remainder:
749 clr [%g4 - some immediate] */
753 /* sub %g1, %g4, %g4 */
754 if (!(X_OP (insn
) == 2 && X_OP3 (insn
) == 0x4 && !X_I(insn
)
755 && X_RD (insn
) == 4 && X_RS1 (insn
) == 1 && X_RS2 (insn
) == 4))
759 insn
= sparc_fetch_instruction (pc
);
761 if (!(X_OP (insn
) == 2 && X_OP3 (insn
) == 0x14 && !X_I(insn
)
762 && X_RD (insn
) == 0 && X_RS1 (insn
) == 1 && X_RS2 (insn
) == 4))
766 insn
= sparc_fetch_instruction (pc
);
768 if (!(X_OP (insn
) == 0 && X_COND (insn
) == 0x1))
771 /* add %g1, -<some immediate>, %g1 */
772 insn
= sparc_fetch_instruction (pc
);
774 if (!(X_OP (insn
) == 2 && X_OP3(insn
) == 0 && X_I(insn
)
775 && X_RS1 (insn
) == 1 && X_RD (insn
) == 1))
779 insn
= sparc_fetch_instruction (pc
);
781 if (!(X_OP (insn
) == 0 && X_COND (insn
) == 0x8))
784 /* clr [%g1] (st %g0, [%g1] or st %g0, [%g1+0]) */
785 insn
= sparc_fetch_instruction (pc
);
787 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4
788 && X_RD (insn
) == 0 && X_RS1 (insn
) == 1
789 && (!X_I(insn
) || X_SIMM13 (insn
) == 0)))
792 /* We found a valid stack-check sequence, return the new PC. */
794 /* optional: clr [%g4 - some immediate] */
795 insn
= sparc_fetch_instruction (pc
);
797 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && X_I(insn
)
798 && X_RS1 (insn
) == 4 && X_RD (insn
) == 0))
804 /* No stack check code in our prologue, return the start_pc. */
808 /* Record the effect of a SAVE instruction on CACHE. */
811 sparc_record_save_insn (struct sparc_frame_cache
*cache
)
813 /* The frame is set up. */
814 cache
->frameless_p
= 0;
816 /* The frame pointer contains the CFA. */
817 cache
->frame_offset
= 0;
819 /* The `local' and `in' registers are all saved. */
820 cache
->saved_regs_mask
= 0xffff;
822 /* The `out' registers are all renamed. */
823 cache
->copied_regs_mask
= 0xff;
826 /* Do a full analysis of the prologue at PC and update CACHE accordingly.
827 Bail out early if CURRENT_PC is reached. Return the address where
828 the analysis stopped.
830 We handle both the traditional register window model and the single
831 register window (aka flat) model. */
834 sparc_analyze_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
835 CORE_ADDR current_pc
, struct sparc_frame_cache
*cache
)
837 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
842 pc
= sparc_skip_stack_check (pc
);
844 if (current_pc
<= pc
)
847 /* We have to handle to "Procedure Linkage Table" (PLT) special. On
848 SPARC the linker usually defines a symbol (typically
849 _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section.
850 This symbol makes us end up here with PC pointing at the start of
851 the PLT and CURRENT_PC probably pointing at a PLT entry. If we
852 would do our normal prologue analysis, we would probably conclude
853 that we've got a frame when in reality we don't, since the
854 dynamic linker patches up the first PLT with some code that
855 starts with a SAVE instruction. Patch up PC such that it points
856 at the start of our PLT entry. */
857 if (tdep
->plt_entry_size
> 0 && in_plt_section (current_pc
, NULL
))
858 pc
= current_pc
- ((current_pc
- pc
) % tdep
->plt_entry_size
);
860 insn
= sparc_fetch_instruction (pc
);
862 /* Recognize store insns and record their sources. */
863 while (X_OP (insn
) == 3
864 && (X_OP3 (insn
) == 0x4 /* stw */
865 || X_OP3 (insn
) == 0x7 /* std */
866 || X_OP3 (insn
) == 0xe) /* stx */
867 && X_RS1 (insn
) == SPARC_SP_REGNUM
)
869 int regnum
= X_RD (insn
);
871 /* Recognize stores into the corresponding stack slots. */
872 if (regnum
>= SPARC_L0_REGNUM
&& regnum
<= SPARC_I7_REGNUM
874 && X_SIMM13 (insn
) == (X_OP3 (insn
) == 0xe
875 ? (regnum
- SPARC_L0_REGNUM
) * 8 + BIAS
876 : (regnum
- SPARC_L0_REGNUM
) * 4))
877 || (!X_I (insn
) && regnum
== SPARC_L0_REGNUM
)))
879 cache
->saved_regs_mask
|= (1 << (regnum
- SPARC_L0_REGNUM
));
880 if (X_OP3 (insn
) == 0x7)
881 cache
->saved_regs_mask
|= (1 << (regnum
+ 1 - SPARC_L0_REGNUM
));
886 insn
= sparc_fetch_instruction (pc
+ offset
);
889 /* Recognize a SETHI insn and record its destination. */
890 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 0x04)
895 insn
= sparc_fetch_instruction (pc
+ offset
);
898 /* Allow for an arithmetic operation on DEST or %g1. */
899 if (X_OP (insn
) == 2 && X_I (insn
)
900 && (X_RD (insn
) == 1 || X_RD (insn
) == dest
))
904 insn
= sparc_fetch_instruction (pc
+ offset
);
907 /* Check for the SAVE instruction that sets up the frame. */
908 if (X_OP (insn
) == 2 && X_OP3 (insn
) == 0x3c)
910 sparc_record_save_insn (cache
);
915 /* Check for an arithmetic operation on %sp. */
917 && (X_OP3 (insn
) == 0 || X_OP3 (insn
) == 0x4)
918 && X_RS1 (insn
) == SPARC_SP_REGNUM
919 && X_RD (insn
) == SPARC_SP_REGNUM
)
923 cache
->frame_offset
= X_SIMM13 (insn
);
924 if (X_OP3 (insn
) == 0)
925 cache
->frame_offset
= -cache
->frame_offset
;
929 insn
= sparc_fetch_instruction (pc
+ offset
);
931 /* Check for an arithmetic operation that sets up the frame. */
933 && (X_OP3 (insn
) == 0 || X_OP3 (insn
) == 0x4)
934 && X_RS1 (insn
) == SPARC_SP_REGNUM
935 && X_RD (insn
) == SPARC_FP_REGNUM
)
937 cache
->frameless_p
= 0;
938 cache
->frame_offset
= 0;
939 /* We could check that the amount subtracted to %sp above is the
940 same as the one added here, but this seems superfluous. */
941 cache
->copied_regs_mask
|= 0x40;
944 insn
= sparc_fetch_instruction (pc
+ offset
);
947 /* Check for a move (or) operation that copies the return register. */
949 && X_OP3 (insn
) == 0x2
951 && X_RS1 (insn
) == SPARC_G0_REGNUM
952 && X_RS2 (insn
) == SPARC_O7_REGNUM
953 && X_RD (insn
) == SPARC_I7_REGNUM
)
955 cache
->copied_regs_mask
|= 0x80;
966 sparc_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
968 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
969 return frame_unwind_register_unsigned (this_frame
, tdep
->pc_regnum
);
972 /* Return PC of first real instruction of the function starting at
976 sparc32_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
978 struct symtab_and_line sal
;
979 CORE_ADDR func_start
, func_end
;
980 struct sparc_frame_cache cache
;
982 /* This is the preferred method, find the end of the prologue by
983 using the debugging information. */
984 if (find_pc_partial_function (start_pc
, NULL
, &func_start
, &func_end
))
986 sal
= find_pc_line (func_start
, 0);
988 if (sal
.end
< func_end
989 && start_pc
<= sal
.end
)
993 start_pc
= sparc_analyze_prologue (gdbarch
, start_pc
, 0xffffffffUL
, &cache
);
995 /* The psABI says that "Although the first 6 words of arguments
996 reside in registers, the standard stack frame reserves space for
997 them.". It also suggests that a function may use that space to
998 "write incoming arguments 0 to 5" into that space, and that's
999 indeed what GCC seems to be doing. In that case GCC will
1000 generate debug information that points to the stack slots instead
1001 of the registers, so we should consider the instructions that
1002 write out these incoming arguments onto the stack. */
1006 unsigned long insn
= sparc_fetch_instruction (start_pc
);
1008 /* Recognize instructions that store incoming arguments into the
1009 corresponding stack slots. */
1010 if (X_OP (insn
) == 3 && (X_OP3 (insn
) & 0x3c) == 0x04
1011 && X_I (insn
) && X_RS1 (insn
) == SPARC_FP_REGNUM
)
1013 int regnum
= X_RD (insn
);
1015 /* Case of arguments still in %o[0..5]. */
1016 if (regnum
>= SPARC_O0_REGNUM
&& regnum
<= SPARC_O5_REGNUM
1017 && !(cache
.copied_regs_mask
& (1 << (regnum
- SPARC_O0_REGNUM
)))
1018 && X_SIMM13 (insn
) == 68 + (regnum
- SPARC_O0_REGNUM
) * 4)
1024 /* Case of arguments copied into %i[0..5]. */
1025 if (regnum
>= SPARC_I0_REGNUM
&& regnum
<= SPARC_I5_REGNUM
1026 && (cache
.copied_regs_mask
& (1 << (regnum
- SPARC_I0_REGNUM
)))
1027 && X_SIMM13 (insn
) == 68 + (regnum
- SPARC_I0_REGNUM
) * 4)
1040 /* Normal frames. */
1042 struct sparc_frame_cache
*
1043 sparc_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1045 struct sparc_frame_cache
*cache
;
1050 cache
= sparc_alloc_frame_cache ();
1051 *this_cache
= cache
;
1053 cache
->pc
= get_frame_func (this_frame
);
1055 sparc_analyze_prologue (get_frame_arch (this_frame
), cache
->pc
,
1056 get_frame_pc (this_frame
), cache
);
1058 if (cache
->frameless_p
)
1060 /* This function is frameless, so %fp (%i6) holds the frame
1061 pointer for our calling frame. Use %sp (%o6) as this frame's
1064 get_frame_register_unsigned (this_frame
, SPARC_SP_REGNUM
);
1068 /* For normal frames, %fp (%i6) holds the frame pointer, the
1069 base address for the current stack frame. */
1071 get_frame_register_unsigned (this_frame
, SPARC_FP_REGNUM
);
1074 cache
->base
+= cache
->frame_offset
;
1076 if (cache
->base
& 1)
1077 cache
->base
+= BIAS
;
1083 sparc32_struct_return_from_sym (struct symbol
*sym
)
1085 struct type
*type
= check_typedef (SYMBOL_TYPE (sym
));
1086 enum type_code code
= TYPE_CODE (type
);
1088 if (code
== TYPE_CODE_FUNC
|| code
== TYPE_CODE_METHOD
)
1090 type
= check_typedef (TYPE_TARGET_TYPE (type
));
1091 if (sparc_structure_or_union_p (type
)
1092 || (sparc_floating_p (type
) && TYPE_LENGTH (type
) == 16))
1099 struct sparc_frame_cache
*
1100 sparc32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1102 struct sparc_frame_cache
*cache
;
1108 cache
= sparc_frame_cache (this_frame
, this_cache
);
1110 sym
= find_pc_function (cache
->pc
);
1113 cache
->struct_return_p
= sparc32_struct_return_from_sym (sym
);
1117 /* There is no debugging information for this function to
1118 help us determine whether this function returns a struct
1119 or not. So we rely on another heuristic which is to check
1120 the instruction at the return address and see if this is
1121 an "unimp" instruction. If it is, then it is a struct-return
1125 (cache
->copied_regs_mask
& 0x80) ? SPARC_I7_REGNUM
: SPARC_O7_REGNUM
;
1127 pc
= get_frame_register_unsigned (this_frame
, regnum
) + 8;
1128 if (sparc_is_unimp_insn (pc
))
1129 cache
->struct_return_p
= 1;
1136 sparc32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1137 struct frame_id
*this_id
)
1139 struct sparc_frame_cache
*cache
=
1140 sparc32_frame_cache (this_frame
, this_cache
);
1142 /* This marks the outermost frame. */
1143 if (cache
->base
== 0)
1146 (*this_id
) = frame_id_build (cache
->base
, cache
->pc
);
1149 static struct value
*
1150 sparc32_frame_prev_register (struct frame_info
*this_frame
,
1151 void **this_cache
, int regnum
)
1153 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1154 struct sparc_frame_cache
*cache
=
1155 sparc32_frame_cache (this_frame
, this_cache
);
1157 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== SPARC32_NPC_REGNUM
)
1159 CORE_ADDR pc
= (regnum
== SPARC32_NPC_REGNUM
) ? 4 : 0;
1161 /* If this functions has a Structure, Union or Quad-Precision
1162 return value, we have to skip the UNIMP instruction that encodes
1163 the size of the structure. */
1164 if (cache
->struct_return_p
)
1168 (cache
->copied_regs_mask
& 0x80) ? SPARC_I7_REGNUM
: SPARC_O7_REGNUM
;
1169 pc
+= get_frame_register_unsigned (this_frame
, regnum
) + 8;
1170 return frame_unwind_got_constant (this_frame
, regnum
, pc
);
1173 /* Handle StackGhost. */
1175 ULONGEST wcookie
= sparc_fetch_wcookie (gdbarch
);
1177 if (wcookie
!= 0 && !cache
->frameless_p
&& regnum
== SPARC_I7_REGNUM
)
1179 CORE_ADDR addr
= cache
->base
+ (regnum
- SPARC_L0_REGNUM
) * 4;
1182 /* Read the value in from memory. */
1183 i7
= get_frame_memory_unsigned (this_frame
, addr
, 4);
1184 return frame_unwind_got_constant (this_frame
, regnum
, i7
^ wcookie
);
1188 /* The previous frame's `local' and `in' registers may have been saved
1189 in the register save area. */
1190 if (regnum
>= SPARC_L0_REGNUM
&& regnum
<= SPARC_I7_REGNUM
1191 && (cache
->saved_regs_mask
& (1 << (regnum
- SPARC_L0_REGNUM
))))
1193 CORE_ADDR addr
= cache
->base
+ (regnum
- SPARC_L0_REGNUM
) * 4;
1195 return frame_unwind_got_memory (this_frame
, regnum
, addr
);
1198 /* The previous frame's `out' registers may be accessible as the current
1199 frame's `in' registers. */
1200 if (regnum
>= SPARC_O0_REGNUM
&& regnum
<= SPARC_O7_REGNUM
1201 && (cache
->copied_regs_mask
& (1 << (regnum
- SPARC_O0_REGNUM
))))
1202 regnum
+= (SPARC_I0_REGNUM
- SPARC_O0_REGNUM
);
1204 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1207 static const struct frame_unwind sparc32_frame_unwind
=
1210 default_frame_unwind_stop_reason
,
1211 sparc32_frame_this_id
,
1212 sparc32_frame_prev_register
,
1214 default_frame_sniffer
1219 sparc32_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
1221 struct sparc_frame_cache
*cache
=
1222 sparc32_frame_cache (this_frame
, this_cache
);
1227 static const struct frame_base sparc32_frame_base
=
1229 &sparc32_frame_unwind
,
1230 sparc32_frame_base_address
,
1231 sparc32_frame_base_address
,
1232 sparc32_frame_base_address
1235 static struct frame_id
1236 sparc_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1240 sp
= get_frame_register_unsigned (this_frame
, SPARC_SP_REGNUM
);
1243 return frame_id_build (sp
, get_frame_pc (this_frame
));
1247 /* Extract a function return value of TYPE from REGCACHE, and copy
1248 that into VALBUF. */
1251 sparc32_extract_return_value (struct type
*type
, struct regcache
*regcache
,
1254 int len
= TYPE_LENGTH (type
);
1257 gdb_assert (!sparc_structure_or_union_p (type
));
1258 gdb_assert (!(sparc_floating_p (type
) && len
== 16));
1260 if (sparc_floating_p (type
) || sparc_complex_floating_p (type
))
1262 /* Floating return values. */
1263 regcache_cooked_read (regcache
, SPARC_F0_REGNUM
, buf
);
1265 regcache_cooked_read (regcache
, SPARC_F1_REGNUM
, buf
+ 4);
1268 regcache_cooked_read (regcache
, SPARC_F2_REGNUM
, buf
+ 8);
1269 regcache_cooked_read (regcache
, SPARC_F3_REGNUM
, buf
+ 12);
1273 regcache_cooked_read (regcache
, SPARC_F4_REGNUM
, buf
+ 16);
1274 regcache_cooked_read (regcache
, SPARC_F5_REGNUM
, buf
+ 20);
1275 regcache_cooked_read (regcache
, SPARC_F6_REGNUM
, buf
+ 24);
1276 regcache_cooked_read (regcache
, SPARC_F7_REGNUM
, buf
+ 28);
1278 memcpy (valbuf
, buf
, len
);
1282 /* Integral and pointer return values. */
1283 gdb_assert (sparc_integral_or_pointer_p (type
));
1285 regcache_cooked_read (regcache
, SPARC_O0_REGNUM
, buf
);
1288 regcache_cooked_read (regcache
, SPARC_O1_REGNUM
, buf
+ 4);
1289 gdb_assert (len
== 8);
1290 memcpy (valbuf
, buf
, 8);
1294 /* Just stripping off any unused bytes should preserve the
1295 signed-ness just fine. */
1296 memcpy (valbuf
, buf
+ 4 - len
, len
);
1301 /* Store the function return value of type TYPE from VALBUF into
1305 sparc32_store_return_value (struct type
*type
, struct regcache
*regcache
,
1306 const gdb_byte
*valbuf
)
1308 int len
= TYPE_LENGTH (type
);
1311 gdb_assert (!sparc_structure_or_union_p (type
));
1312 gdb_assert (!(sparc_floating_p (type
) && len
== 16));
1313 gdb_assert (len
<= 8);
1315 if (sparc_floating_p (type
) || sparc_complex_floating_p (type
))
1317 /* Floating return values. */
1318 memcpy (buf
, valbuf
, len
);
1319 regcache_cooked_write (regcache
, SPARC_F0_REGNUM
, buf
);
1321 regcache_cooked_write (regcache
, SPARC_F1_REGNUM
, buf
+ 4);
1324 regcache_cooked_write (regcache
, SPARC_F2_REGNUM
, buf
+ 8);
1325 regcache_cooked_write (regcache
, SPARC_F3_REGNUM
, buf
+ 12);
1329 regcache_cooked_write (regcache
, SPARC_F4_REGNUM
, buf
+ 16);
1330 regcache_cooked_write (regcache
, SPARC_F5_REGNUM
, buf
+ 20);
1331 regcache_cooked_write (regcache
, SPARC_F6_REGNUM
, buf
+ 24);
1332 regcache_cooked_write (regcache
, SPARC_F7_REGNUM
, buf
+ 28);
1337 /* Integral and pointer return values. */
1338 gdb_assert (sparc_integral_or_pointer_p (type
));
1342 gdb_assert (len
== 8);
1343 memcpy (buf
, valbuf
, 8);
1344 regcache_cooked_write (regcache
, SPARC_O1_REGNUM
, buf
+ 4);
1348 /* ??? Do we need to do any sign-extension here? */
1349 memcpy (buf
+ 4 - len
, valbuf
, len
);
1351 regcache_cooked_write (regcache
, SPARC_O0_REGNUM
, buf
);
1355 static enum return_value_convention
1356 sparc32_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
1357 struct type
*type
, struct regcache
*regcache
,
1358 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1360 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1362 /* The psABI says that "...every stack frame reserves the word at
1363 %fp+64. If a function returns a structure, union, or
1364 quad-precision value, this word should hold the address of the
1365 object into which the return value should be copied." This
1366 guarantees that we can always find the return value, not just
1367 before the function returns. */
1369 if (sparc_structure_or_union_p (type
)
1370 || (sparc_floating_p (type
) && TYPE_LENGTH (type
) == 16))
1377 regcache_cooked_read_unsigned (regcache
, SPARC_SP_REGNUM
, &sp
);
1378 addr
= read_memory_unsigned_integer (sp
+ 64, 4, byte_order
);
1379 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
1382 return RETURN_VALUE_ABI_PRESERVES_ADDRESS
;
1386 sparc32_extract_return_value (type
, regcache
, readbuf
);
1388 sparc32_store_return_value (type
, regcache
, writebuf
);
1390 return RETURN_VALUE_REGISTER_CONVENTION
;
1394 sparc32_stabs_argument_has_addr (struct gdbarch
*gdbarch
, struct type
*type
)
1396 return (sparc_structure_or_union_p (type
)
1397 || (sparc_floating_p (type
) && TYPE_LENGTH (type
) == 16)
1398 || sparc_complex_floating_p (type
));
1402 sparc32_dwarf2_struct_return_p (struct frame_info
*this_frame
)
1404 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
1405 struct symbol
*sym
= find_pc_function (pc
);
1408 return sparc32_struct_return_from_sym (sym
);
1413 sparc32_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1414 struct dwarf2_frame_state_reg
*reg
,
1415 struct frame_info
*this_frame
)
1421 case SPARC_G0_REGNUM
:
1422 /* Since %g0 is always zero, there is no point in saving it, and
1423 people will be inclined omit it from the CFI. Make sure we
1424 don't warn about that. */
1425 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
1427 case SPARC_SP_REGNUM
:
1428 reg
->how
= DWARF2_FRAME_REG_CFA
;
1430 case SPARC32_PC_REGNUM
:
1431 case SPARC32_NPC_REGNUM
:
1432 reg
->how
= DWARF2_FRAME_REG_RA_OFFSET
;
1434 if (sparc32_dwarf2_struct_return_p (this_frame
))
1436 if (regnum
== SPARC32_NPC_REGNUM
)
1438 reg
->loc
.offset
= off
;
1444 /* The SPARC Architecture doesn't have hardware single-step support,
1445 and most operating systems don't implement it either, so we provide
1446 software single-step mechanism. */
1449 sparc_analyze_control_transfer (struct frame_info
*frame
,
1450 CORE_ADDR pc
, CORE_ADDR
*npc
)
1452 unsigned long insn
= sparc_fetch_instruction (pc
);
1453 int conditional_p
= X_COND (insn
) & 0x7;
1455 long offset
= 0; /* Must be signed for sign-extend. */
1457 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 3 && (insn
& 0x1000000) == 0)
1459 /* Branch on Integer Register with Prediction (BPr). */
1463 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 6)
1465 /* Branch on Floating-Point Condition Codes (FBfcc). */
1467 offset
= 4 * X_DISP22 (insn
);
1469 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 5)
1471 /* Branch on Floating-Point Condition Codes with Prediction
1474 offset
= 4 * X_DISP19 (insn
);
1476 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 2)
1478 /* Branch on Integer Condition Codes (Bicc). */
1480 offset
= 4 * X_DISP22 (insn
);
1482 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 1)
1484 /* Branch on Integer Condition Codes with Prediction (BPcc). */
1486 offset
= 4 * X_DISP19 (insn
);
1488 else if (X_OP (insn
) == 2 && X_OP3 (insn
) == 0x3a)
1490 /* Trap instruction (TRAP). */
1491 return gdbarch_tdep (get_frame_arch (frame
))->step_trap (frame
, insn
);
1494 /* FIXME: Handle DONE and RETRY instructions. */
1500 /* For conditional branches, return nPC + 4 iff the annul
1502 return (X_A (insn
) ? *npc
+ 4 : 0);
1506 /* For unconditional branches, return the target if its
1507 specified condition is "always" and return nPC + 4 if the
1508 condition is "never". If the annul bit is 1, set *NPC to
1510 if (X_COND (insn
) == 0x0)
1511 pc
= *npc
, offset
= 4;
1515 gdb_assert (offset
!= 0);
1524 sparc_step_trap (struct frame_info
*frame
, unsigned long insn
)
1530 sparc_software_single_step (struct frame_info
*frame
)
1532 struct gdbarch
*arch
= get_frame_arch (frame
);
1533 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
1534 struct address_space
*aspace
= get_frame_address_space (frame
);
1535 CORE_ADDR npc
, nnpc
;
1537 CORE_ADDR pc
, orig_npc
;
1539 pc
= get_frame_register_unsigned (frame
, tdep
->pc_regnum
);
1540 orig_npc
= npc
= get_frame_register_unsigned (frame
, tdep
->npc_regnum
);
1542 /* Analyze the instruction at PC. */
1543 nnpc
= sparc_analyze_control_transfer (frame
, pc
, &npc
);
1545 insert_single_step_breakpoint (arch
, aspace
, npc
);
1548 insert_single_step_breakpoint (arch
, aspace
, nnpc
);
1550 /* Assert that we have set at least one breakpoint, and that
1551 they're not set at the same spot - unless we're going
1552 from here straight to NULL, i.e. a call or jump to 0. */
1553 gdb_assert (npc
!= 0 || nnpc
!= 0 || orig_npc
== 0);
1554 gdb_assert (nnpc
!= npc
|| orig_npc
== 0);
1560 sparc_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1562 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_regcache_arch (regcache
));
1564 regcache_cooked_write_unsigned (regcache
, tdep
->pc_regnum
, pc
);
1565 regcache_cooked_write_unsigned (regcache
, tdep
->npc_regnum
, pc
+ 4);
1569 /* Return the appropriate register set for the core section identified
1570 by SECT_NAME and SECT_SIZE. */
1572 static const struct regset
*
1573 sparc_regset_from_core_section (struct gdbarch
*gdbarch
,
1574 const char *sect_name
, size_t sect_size
)
1576 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1578 if (strcmp (sect_name
, ".reg") == 0 && sect_size
>= tdep
->sizeof_gregset
)
1579 return tdep
->gregset
;
1581 if (strcmp (sect_name
, ".reg2") == 0 && sect_size
>= tdep
->sizeof_fpregset
)
1582 return tdep
->fpregset
;
1588 static struct gdbarch
*
1589 sparc32_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1591 struct gdbarch_tdep
*tdep
;
1592 struct gdbarch
*gdbarch
;
1594 /* If there is already a candidate, use it. */
1595 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
1597 return arches
->gdbarch
;
1599 /* Allocate space for the new architecture. */
1600 tdep
= XZALLOC (struct gdbarch_tdep
);
1601 gdbarch
= gdbarch_alloc (&info
, tdep
);
1603 tdep
->pc_regnum
= SPARC32_PC_REGNUM
;
1604 tdep
->npc_regnum
= SPARC32_NPC_REGNUM
;
1605 tdep
->step_trap
= sparc_step_trap
;
1607 set_gdbarch_long_double_bit (gdbarch
, 128);
1608 set_gdbarch_long_double_format (gdbarch
, floatformats_sparc_quad
);
1610 set_gdbarch_num_regs (gdbarch
, SPARC32_NUM_REGS
);
1611 set_gdbarch_register_name (gdbarch
, sparc32_register_name
);
1612 set_gdbarch_register_type (gdbarch
, sparc32_register_type
);
1613 set_gdbarch_num_pseudo_regs (gdbarch
, SPARC32_NUM_PSEUDO_REGS
);
1614 set_gdbarch_pseudo_register_read (gdbarch
, sparc32_pseudo_register_read
);
1615 set_gdbarch_pseudo_register_write (gdbarch
, sparc32_pseudo_register_write
);
1617 /* Register numbers of various important registers. */
1618 set_gdbarch_sp_regnum (gdbarch
, SPARC_SP_REGNUM
); /* %sp */
1619 set_gdbarch_pc_regnum (gdbarch
, SPARC32_PC_REGNUM
); /* %pc */
1620 set_gdbarch_fp0_regnum (gdbarch
, SPARC_F0_REGNUM
); /* %f0 */
1622 /* Call dummy code. */
1623 set_gdbarch_frame_align (gdbarch
, sparc32_frame_align
);
1624 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
1625 set_gdbarch_push_dummy_code (gdbarch
, sparc32_push_dummy_code
);
1626 set_gdbarch_push_dummy_call (gdbarch
, sparc32_push_dummy_call
);
1628 set_gdbarch_return_value (gdbarch
, sparc32_return_value
);
1629 set_gdbarch_stabs_argument_has_addr
1630 (gdbarch
, sparc32_stabs_argument_has_addr
);
1632 set_gdbarch_skip_prologue (gdbarch
, sparc32_skip_prologue
);
1634 /* Stack grows downward. */
1635 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
1637 set_gdbarch_breakpoint_from_pc (gdbarch
, sparc_breakpoint_from_pc
);
1639 set_gdbarch_frame_args_skip (gdbarch
, 8);
1641 set_gdbarch_print_insn (gdbarch
, print_insn_sparc
);
1643 set_gdbarch_software_single_step (gdbarch
, sparc_software_single_step
);
1644 set_gdbarch_write_pc (gdbarch
, sparc_write_pc
);
1646 set_gdbarch_dummy_id (gdbarch
, sparc_dummy_id
);
1648 set_gdbarch_unwind_pc (gdbarch
, sparc_unwind_pc
);
1650 frame_base_set_default (gdbarch
, &sparc32_frame_base
);
1652 /* Hook in the DWARF CFI frame unwinder. */
1653 dwarf2_frame_set_init_reg (gdbarch
, sparc32_dwarf2_frame_init_reg
);
1654 /* FIXME: kettenis/20050423: Don't enable the unwinder until the
1655 StackGhost issues have been resolved. */
1657 /* Hook in ABI-specific overrides, if they have been registered. */
1658 gdbarch_init_osabi (info
, gdbarch
);
1660 frame_unwind_append_unwinder (gdbarch
, &sparc32_frame_unwind
);
1662 /* If we have register sets, enable the generic core file support. */
1664 set_gdbarch_regset_from_core_section (gdbarch
,
1665 sparc_regset_from_core_section
);
1670 /* Helper functions for dealing with register windows. */
1673 sparc_supply_rwindow (struct regcache
*regcache
, CORE_ADDR sp
, int regnum
)
1675 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1676 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1683 /* Registers are 64-bit. */
1686 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1688 if (regnum
== i
|| regnum
== -1)
1690 target_read_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 8), buf
, 8);
1692 /* Handle StackGhost. */
1693 if (i
== SPARC_I7_REGNUM
)
1695 ULONGEST wcookie
= sparc_fetch_wcookie (gdbarch
);
1698 i7
= extract_unsigned_integer (buf
+ offset
, 8, byte_order
);
1699 store_unsigned_integer (buf
+ offset
, 8, byte_order
,
1703 regcache_raw_supply (regcache
, i
, buf
);
1709 /* Registers are 32-bit. Toss any sign-extension of the stack
1713 /* Clear out the top half of the temporary buffer, and put the
1714 register value in the bottom half if we're in 64-bit mode. */
1715 if (gdbarch_ptr_bit (get_regcache_arch (regcache
)) == 64)
1721 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1723 if (regnum
== i
|| regnum
== -1)
1725 target_read_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 4),
1728 /* Handle StackGhost. */
1729 if (i
== SPARC_I7_REGNUM
)
1731 ULONGEST wcookie
= sparc_fetch_wcookie (gdbarch
);
1734 i7
= extract_unsigned_integer (buf
+ offset
, 4, byte_order
);
1735 store_unsigned_integer (buf
+ offset
, 4, byte_order
,
1739 regcache_raw_supply (regcache
, i
, buf
);
1746 sparc_collect_rwindow (const struct regcache
*regcache
,
1747 CORE_ADDR sp
, int regnum
)
1749 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1750 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1757 /* Registers are 64-bit. */
1760 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1762 if (regnum
== -1 || regnum
== SPARC_SP_REGNUM
|| regnum
== i
)
1764 regcache_raw_collect (regcache
, i
, buf
);
1766 /* Handle StackGhost. */
1767 if (i
== SPARC_I7_REGNUM
)
1769 ULONGEST wcookie
= sparc_fetch_wcookie (gdbarch
);
1772 i7
= extract_unsigned_integer (buf
+ offset
, 8, byte_order
);
1773 store_unsigned_integer (buf
, 8, byte_order
, i7
^ wcookie
);
1776 target_write_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 8), buf
, 8);
1782 /* Registers are 32-bit. Toss any sign-extension of the stack
1786 /* Only use the bottom half if we're in 64-bit mode. */
1787 if (gdbarch_ptr_bit (get_regcache_arch (regcache
)) == 64)
1790 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1792 if (regnum
== -1 || regnum
== SPARC_SP_REGNUM
|| regnum
== i
)
1794 regcache_raw_collect (regcache
, i
, buf
);
1796 /* Handle StackGhost. */
1797 if (i
== SPARC_I7_REGNUM
)
1799 ULONGEST wcookie
= sparc_fetch_wcookie (gdbarch
);
1802 i7
= extract_unsigned_integer (buf
+ offset
, 4, byte_order
);
1803 store_unsigned_integer (buf
+ offset
, 4, byte_order
,
1807 target_write_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 4),
1814 /* Helper functions for dealing with register sets. */
1817 sparc32_supply_gregset (const struct sparc_gregset
*gregset
,
1818 struct regcache
*regcache
,
1819 int regnum
, const void *gregs
)
1821 const gdb_byte
*regs
= gregs
;
1822 gdb_byte zero
[4] = { 0 };
1825 if (regnum
== SPARC32_PSR_REGNUM
|| regnum
== -1)
1826 regcache_raw_supply (regcache
, SPARC32_PSR_REGNUM
,
1827 regs
+ gregset
->r_psr_offset
);
1829 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== -1)
1830 regcache_raw_supply (regcache
, SPARC32_PC_REGNUM
,
1831 regs
+ gregset
->r_pc_offset
);
1833 if (regnum
== SPARC32_NPC_REGNUM
|| regnum
== -1)
1834 regcache_raw_supply (regcache
, SPARC32_NPC_REGNUM
,
1835 regs
+ gregset
->r_npc_offset
);
1837 if (regnum
== SPARC32_Y_REGNUM
|| regnum
== -1)
1838 regcache_raw_supply (regcache
, SPARC32_Y_REGNUM
,
1839 regs
+ gregset
->r_y_offset
);
1841 if (regnum
== SPARC_G0_REGNUM
|| regnum
== -1)
1842 regcache_raw_supply (regcache
, SPARC_G0_REGNUM
, &zero
);
1844 if ((regnum
>= SPARC_G1_REGNUM
&& regnum
<= SPARC_O7_REGNUM
) || regnum
== -1)
1846 int offset
= gregset
->r_g1_offset
;
1848 for (i
= SPARC_G1_REGNUM
; i
<= SPARC_O7_REGNUM
; i
++)
1850 if (regnum
== i
|| regnum
== -1)
1851 regcache_raw_supply (regcache
, i
, regs
+ offset
);
1856 if ((regnum
>= SPARC_L0_REGNUM
&& regnum
<= SPARC_I7_REGNUM
) || regnum
== -1)
1858 /* Not all of the register set variants include Locals and
1859 Inputs. For those that don't, we read them off the stack. */
1860 if (gregset
->r_l0_offset
== -1)
1864 regcache_cooked_read_unsigned (regcache
, SPARC_SP_REGNUM
, &sp
);
1865 sparc_supply_rwindow (regcache
, sp
, regnum
);
1869 int offset
= gregset
->r_l0_offset
;
1871 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1873 if (regnum
== i
|| regnum
== -1)
1874 regcache_raw_supply (regcache
, i
, regs
+ offset
);
1882 sparc32_collect_gregset (const struct sparc_gregset
*gregset
,
1883 const struct regcache
*regcache
,
1884 int regnum
, void *gregs
)
1886 gdb_byte
*regs
= gregs
;
1889 if (regnum
== SPARC32_PSR_REGNUM
|| regnum
== -1)
1890 regcache_raw_collect (regcache
, SPARC32_PSR_REGNUM
,
1891 regs
+ gregset
->r_psr_offset
);
1893 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== -1)
1894 regcache_raw_collect (regcache
, SPARC32_PC_REGNUM
,
1895 regs
+ gregset
->r_pc_offset
);
1897 if (regnum
== SPARC32_NPC_REGNUM
|| regnum
== -1)
1898 regcache_raw_collect (regcache
, SPARC32_NPC_REGNUM
,
1899 regs
+ gregset
->r_npc_offset
);
1901 if (regnum
== SPARC32_Y_REGNUM
|| regnum
== -1)
1902 regcache_raw_collect (regcache
, SPARC32_Y_REGNUM
,
1903 regs
+ gregset
->r_y_offset
);
1905 if ((regnum
>= SPARC_G1_REGNUM
&& regnum
<= SPARC_O7_REGNUM
) || regnum
== -1)
1907 int offset
= gregset
->r_g1_offset
;
1909 /* %g0 is always zero. */
1910 for (i
= SPARC_G1_REGNUM
; i
<= SPARC_O7_REGNUM
; i
++)
1912 if (regnum
== i
|| regnum
== -1)
1913 regcache_raw_collect (regcache
, i
, regs
+ offset
);
1918 if ((regnum
>= SPARC_L0_REGNUM
&& regnum
<= SPARC_I7_REGNUM
) || regnum
== -1)
1920 /* Not all of the register set variants include Locals and
1921 Inputs. For those that don't, we read them off the stack. */
1922 if (gregset
->r_l0_offset
!= -1)
1924 int offset
= gregset
->r_l0_offset
;
1926 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1928 if (regnum
== i
|| regnum
== -1)
1929 regcache_raw_collect (regcache
, i
, regs
+ offset
);
1937 sparc32_supply_fpregset (struct regcache
*regcache
,
1938 int regnum
, const void *fpregs
)
1940 const gdb_byte
*regs
= fpregs
;
1943 for (i
= 0; i
< 32; i
++)
1945 if (regnum
== (SPARC_F0_REGNUM
+ i
) || regnum
== -1)
1946 regcache_raw_supply (regcache
, SPARC_F0_REGNUM
+ i
, regs
+ (i
* 4));
1949 if (regnum
== SPARC32_FSR_REGNUM
|| regnum
== -1)
1950 regcache_raw_supply (regcache
, SPARC32_FSR_REGNUM
, regs
+ (32 * 4) + 4);
1954 sparc32_collect_fpregset (const struct regcache
*regcache
,
1955 int regnum
, void *fpregs
)
1957 gdb_byte
*regs
= fpregs
;
1960 for (i
= 0; i
< 32; i
++)
1962 if (regnum
== (SPARC_F0_REGNUM
+ i
) || regnum
== -1)
1963 regcache_raw_collect (regcache
, SPARC_F0_REGNUM
+ i
, regs
+ (i
* 4));
1966 if (regnum
== SPARC32_FSR_REGNUM
|| regnum
== -1)
1967 regcache_raw_collect (regcache
, SPARC32_FSR_REGNUM
, regs
+ (32 * 4) + 4);
1973 /* From <machine/reg.h>. */
1974 const struct sparc_gregset sparc32_sunos4_gregset
=
1987 /* Provide a prototype to silence -Wmissing-prototypes. */
1988 void _initialize_sparc_tdep (void);
1991 _initialize_sparc_tdep (void)
1993 register_gdbarch_init (bfd_arch_sparc
, sparc32_gdbarch_init
);