1 /* Target-dependent code for SPARC.
3 Copyright (C) 2003-2012 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "arch-utils.h"
23 #include "dwarf2-frame.h"
24 #include "floatformat.h"
26 #include "frame-base.h"
27 #include "frame-unwind.h"
38 #include "gdb_assert.h"
39 #include "gdb_string.h"
41 #include "sparc-tdep.h"
45 /* This file implements the SPARC 32-bit ABI as defined by the section
46 "Low-Level System Information" of the SPARC Compliance Definition
47 (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC. The SCD
48 lists changes with respect to the original 32-bit psABI as defined
49 in the "System V ABI, SPARC Processor Supplement".
51 Note that if we talk about SunOS, we mean SunOS 4.x, which was
52 BSD-based, which is sometimes (retroactively?) referred to as
53 Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and
54 above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9
55 suffering from severe version number inflation). Solaris 2.x is
56 also known as SunOS 5.x, since that's what uname(1) says. Solaris
59 /* Please use the sparc32_-prefix for 32-bit specific code, the
60 sparc64_-prefix for 64-bit specific code and the sparc_-prefix for
61 code that can handle both. The 64-bit specific code lives in
62 sparc64-tdep.c; don't add any here. */
64 /* The SPARC Floating-Point Quad-Precision format is similar to
65 big-endian IA-64 Quad-Precision format. */
66 #define floatformats_sparc_quad floatformats_ia64_quad
68 /* The stack pointer is offset from the stack frame by a BIAS of 2047
69 (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC
70 hosts, so undefine it first. */
74 /* Macros to extract fields from SPARC instructions. */
75 #define X_OP(i) (((i) >> 30) & 0x3)
76 #define X_RD(i) (((i) >> 25) & 0x1f)
77 #define X_A(i) (((i) >> 29) & 1)
78 #define X_COND(i) (((i) >> 25) & 0xf)
79 #define X_OP2(i) (((i) >> 22) & 0x7)
80 #define X_IMM22(i) ((i) & 0x3fffff)
81 #define X_OP3(i) (((i) >> 19) & 0x3f)
82 #define X_RS1(i) (((i) >> 14) & 0x1f)
83 #define X_RS2(i) ((i) & 0x1f)
84 #define X_I(i) (((i) >> 13) & 1)
85 /* Sign extension macros. */
86 #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000)
87 #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000)
88 #define X_DISP10(i) ((((((i) >> 11) && 0x300) | (((i) >> 5) & 0xff)) ^ 0x200) - 0x200)
89 #define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000)
91 /* Fetch the instruction at PC. Instructions are always big-endian
92 even if the processor operates in little-endian mode. */
95 sparc_fetch_instruction (CORE_ADDR pc
)
101 /* If we can't read the instruction at PC, return zero. */
102 if (target_read_memory (pc
, buf
, sizeof (buf
)))
106 for (i
= 0; i
< sizeof (buf
); i
++)
107 insn
= (insn
<< 8) | buf
[i
];
112 /* Return non-zero if the instruction corresponding to PC is an "unimp"
116 sparc_is_unimp_insn (CORE_ADDR pc
)
118 const unsigned long insn
= sparc_fetch_instruction (pc
);
120 return ((insn
& 0xc1c00000) == 0);
123 /* OpenBSD/sparc includes StackGhost, which according to the author's
124 website http://stackghost.cerias.purdue.edu "... transparently and
125 automatically protects applications' stack frames; more
126 specifically, it guards the return pointers. The protection
127 mechanisms require no application source or binary modification and
128 imposes only a negligible performance penalty."
130 The same website provides the following description of how
133 "StackGhost interfaces with the kernel trap handler that would
134 normally write out registers to the stack and the handler that
135 would read them back in. By XORing a cookie into the
136 return-address saved in the user stack when it is actually written
137 to the stack, and then XOR it out when the return-address is pulled
138 from the stack, StackGhost can cause attacker corrupted return
139 pointers to behave in a manner the attacker cannot predict.
140 StackGhost can also use several unused bits in the return pointer
141 to detect a smashed return pointer and abort the process."
143 For GDB this means that whenever we're reading %i7 from a stack
144 frame's window save area, we'll have to XOR the cookie.
146 More information on StackGuard can be found on in:
148 Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated
149 Stack Protection." 2001. Published in USENIX Security Symposium
152 /* Fetch StackGhost Per-Process XOR cookie. */
155 sparc_fetch_wcookie (struct gdbarch
*gdbarch
)
157 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
158 struct target_ops
*ops
= ¤t_target
;
162 len
= target_read (ops
, TARGET_OBJECT_WCOOKIE
, NULL
, buf
, 0, 8);
166 /* We should have either an 32-bit or an 64-bit cookie. */
167 gdb_assert (len
== 4 || len
== 8);
169 return extract_unsigned_integer (buf
, len
, byte_order
);
173 /* The functions on this page are intended to be used to classify
174 function arguments. */
176 /* Check whether TYPE is "Integral or Pointer". */
179 sparc_integral_or_pointer_p (const struct type
*type
)
181 int len
= TYPE_LENGTH (type
);
183 switch (TYPE_CODE (type
))
189 case TYPE_CODE_RANGE
:
190 /* We have byte, half-word, word and extended-word/doubleword
191 integral types. The doubleword is an extension to the
192 original 32-bit ABI by the SCD 2.4.x. */
193 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
196 /* Allow either 32-bit or 64-bit pointers. */
197 return (len
== 4 || len
== 8);
205 /* Check whether TYPE is "Floating". */
208 sparc_floating_p (const struct type
*type
)
210 switch (TYPE_CODE (type
))
214 int len
= TYPE_LENGTH (type
);
215 return (len
== 4 || len
== 8 || len
== 16);
224 /* Check whether TYPE is "Complex Floating". */
227 sparc_complex_floating_p (const struct type
*type
)
229 switch (TYPE_CODE (type
))
231 case TYPE_CODE_COMPLEX
:
233 int len
= TYPE_LENGTH (type
);
234 return (len
== 8 || len
== 16 || len
== 32);
243 /* Check whether TYPE is "Structure or Union".
245 In terms of Ada subprogram calls, arrays are treated the same as
246 struct and union types. So this function also returns non-zero
250 sparc_structure_or_union_p (const struct type
*type
)
252 switch (TYPE_CODE (type
))
254 case TYPE_CODE_STRUCT
:
255 case TYPE_CODE_UNION
:
256 case TYPE_CODE_ARRAY
:
265 /* Register information. */
267 static const char *sparc32_register_names
[] =
269 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
270 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
271 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
272 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
274 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
275 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
276 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
277 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
279 "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr"
282 /* Total number of registers. */
283 #define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names)
285 /* We provide the aliases %d0..%d30 for the floating registers as
286 "psuedo" registers. */
288 static const char *sparc32_pseudo_register_names
[] =
290 "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14",
291 "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30"
294 /* Total number of pseudo registers. */
295 #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names)
297 /* Return the name of register REGNUM. */
300 sparc32_register_name (struct gdbarch
*gdbarch
, int regnum
)
302 if (regnum
>= 0 && regnum
< SPARC32_NUM_REGS
)
303 return sparc32_register_names
[regnum
];
305 if (regnum
< SPARC32_NUM_REGS
+ SPARC32_NUM_PSEUDO_REGS
)
306 return sparc32_pseudo_register_names
[regnum
- SPARC32_NUM_REGS
];
311 /* Construct types for ISA-specific registers. */
314 sparc_psr_type (struct gdbarch
*gdbarch
)
316 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
318 if (!tdep
->sparc_psr_type
)
322 type
= arch_flags_type (gdbarch
, "builtin_type_sparc_psr", 4);
323 append_flags_type_flag (type
, 5, "ET");
324 append_flags_type_flag (type
, 6, "PS");
325 append_flags_type_flag (type
, 7, "S");
326 append_flags_type_flag (type
, 12, "EF");
327 append_flags_type_flag (type
, 13, "EC");
329 tdep
->sparc_psr_type
= type
;
332 return tdep
->sparc_psr_type
;
336 sparc_fsr_type (struct gdbarch
*gdbarch
)
338 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
340 if (!tdep
->sparc_fsr_type
)
344 type
= arch_flags_type (gdbarch
, "builtin_type_sparc_fsr", 4);
345 append_flags_type_flag (type
, 0, "NXA");
346 append_flags_type_flag (type
, 1, "DZA");
347 append_flags_type_flag (type
, 2, "UFA");
348 append_flags_type_flag (type
, 3, "OFA");
349 append_flags_type_flag (type
, 4, "NVA");
350 append_flags_type_flag (type
, 5, "NXC");
351 append_flags_type_flag (type
, 6, "DZC");
352 append_flags_type_flag (type
, 7, "UFC");
353 append_flags_type_flag (type
, 8, "OFC");
354 append_flags_type_flag (type
, 9, "NVC");
355 append_flags_type_flag (type
, 22, "NS");
356 append_flags_type_flag (type
, 23, "NXM");
357 append_flags_type_flag (type
, 24, "DZM");
358 append_flags_type_flag (type
, 25, "UFM");
359 append_flags_type_flag (type
, 26, "OFM");
360 append_flags_type_flag (type
, 27, "NVM");
362 tdep
->sparc_fsr_type
= type
;
365 return tdep
->sparc_fsr_type
;
368 /* Return the GDB type object for the "standard" data type of data in
372 sparc32_register_type (struct gdbarch
*gdbarch
, int regnum
)
374 if (regnum
>= SPARC_F0_REGNUM
&& regnum
<= SPARC_F31_REGNUM
)
375 return builtin_type (gdbarch
)->builtin_float
;
377 if (regnum
>= SPARC32_D0_REGNUM
&& regnum
<= SPARC32_D30_REGNUM
)
378 return builtin_type (gdbarch
)->builtin_double
;
380 if (regnum
== SPARC_SP_REGNUM
|| regnum
== SPARC_FP_REGNUM
)
381 return builtin_type (gdbarch
)->builtin_data_ptr
;
383 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== SPARC32_NPC_REGNUM
)
384 return builtin_type (gdbarch
)->builtin_func_ptr
;
386 if (regnum
== SPARC32_PSR_REGNUM
)
387 return sparc_psr_type (gdbarch
);
389 if (regnum
== SPARC32_FSR_REGNUM
)
390 return sparc_fsr_type (gdbarch
);
392 return builtin_type (gdbarch
)->builtin_int32
;
395 static enum register_status
396 sparc32_pseudo_register_read (struct gdbarch
*gdbarch
,
397 struct regcache
*regcache
,
398 int regnum
, gdb_byte
*buf
)
400 enum register_status status
;
402 gdb_assert (regnum
>= SPARC32_D0_REGNUM
&& regnum
<= SPARC32_D30_REGNUM
);
404 regnum
= SPARC_F0_REGNUM
+ 2 * (regnum
- SPARC32_D0_REGNUM
);
405 status
= regcache_raw_read (regcache
, regnum
, buf
);
406 if (status
== REG_VALID
)
407 status
= regcache_raw_read (regcache
, regnum
+ 1, buf
+ 4);
412 sparc32_pseudo_register_write (struct gdbarch
*gdbarch
,
413 struct regcache
*regcache
,
414 int regnum
, const gdb_byte
*buf
)
416 gdb_assert (regnum
>= SPARC32_D0_REGNUM
&& regnum
<= SPARC32_D30_REGNUM
);
418 regnum
= SPARC_F0_REGNUM
+ 2 * (regnum
- SPARC32_D0_REGNUM
);
419 regcache_raw_write (regcache
, regnum
, buf
);
420 regcache_raw_write (regcache
, regnum
+ 1, buf
+ 4);
425 sparc32_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR address
)
427 /* The ABI requires double-word alignment. */
428 return address
& ~0x7;
432 sparc32_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
434 struct value
**args
, int nargs
,
435 struct type
*value_type
,
436 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
437 struct regcache
*regcache
)
439 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
444 if (using_struct_return (gdbarch
, NULL
, value_type
))
448 /* This is an UNIMP instruction. */
449 store_unsigned_integer (buf
, 4, byte_order
,
450 TYPE_LENGTH (value_type
) & 0x1fff);
451 write_memory (sp
- 8, buf
, 4);
459 sparc32_store_arguments (struct regcache
*regcache
, int nargs
,
460 struct value
**args
, CORE_ADDR sp
,
461 int struct_return
, CORE_ADDR struct_addr
)
463 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
464 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
465 /* Number of words in the "parameter array". */
466 int num_elements
= 0;
470 for (i
= 0; i
< nargs
; i
++)
472 struct type
*type
= value_type (args
[i
]);
473 int len
= TYPE_LENGTH (type
);
475 if (sparc_structure_or_union_p (type
)
476 || (sparc_floating_p (type
) && len
== 16)
477 || sparc_complex_floating_p (type
))
479 /* Structure, Union and Quad-Precision Arguments. */
482 /* Use doubleword alignment for these values. That's always
483 correct, and wasting a few bytes shouldn't be a problem. */
486 write_memory (sp
, value_contents (args
[i
]), len
);
487 args
[i
] = value_from_pointer (lookup_pointer_type (type
), sp
);
490 else if (sparc_floating_p (type
))
492 /* Floating arguments. */
493 gdb_assert (len
== 4 || len
== 8);
494 num_elements
+= (len
/ 4);
498 /* Integral and pointer arguments. */
499 gdb_assert (sparc_integral_or_pointer_p (type
));
502 args
[i
] = value_cast (builtin_type (gdbarch
)->builtin_int32
,
504 num_elements
+= ((len
+ 3) / 4);
508 /* Always allocate at least six words. */
509 sp
-= max (6, num_elements
) * 4;
511 /* The psABI says that "Software convention requires space for the
512 struct/union return value pointer, even if the word is unused." */
515 /* The psABI says that "Although software convention and the
516 operating system require every stack frame to be doubleword
520 for (i
= 0; i
< nargs
; i
++)
522 const bfd_byte
*valbuf
= value_contents (args
[i
]);
523 struct type
*type
= value_type (args
[i
]);
524 int len
= TYPE_LENGTH (type
);
526 gdb_assert (len
== 4 || len
== 8);
530 int regnum
= SPARC_O0_REGNUM
+ element
;
532 regcache_cooked_write (regcache
, regnum
, valbuf
);
533 if (len
> 4 && element
< 5)
534 regcache_cooked_write (regcache
, regnum
+ 1, valbuf
+ 4);
537 /* Always store the argument in memory. */
538 write_memory (sp
+ 4 + element
* 4, valbuf
, len
);
542 gdb_assert (element
== num_elements
);
548 store_unsigned_integer (buf
, 4, byte_order
, struct_addr
);
549 write_memory (sp
, buf
, 4);
556 sparc32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
557 struct regcache
*regcache
, CORE_ADDR bp_addr
,
558 int nargs
, struct value
**args
, CORE_ADDR sp
,
559 int struct_return
, CORE_ADDR struct_addr
)
561 CORE_ADDR call_pc
= (struct_return
? (bp_addr
- 12) : (bp_addr
- 8));
563 /* Set return address. */
564 regcache_cooked_write_unsigned (regcache
, SPARC_O7_REGNUM
, call_pc
);
566 /* Set up function arguments. */
567 sp
= sparc32_store_arguments (regcache
, nargs
, args
, sp
,
568 struct_return
, struct_addr
);
570 /* Allocate the 16-word window save area. */
573 /* Stack should be doubleword aligned at this point. */
574 gdb_assert (sp
% 8 == 0);
576 /* Finally, update the stack pointer. */
577 regcache_cooked_write_unsigned (regcache
, SPARC_SP_REGNUM
, sp
);
583 /* Use the program counter to determine the contents and size of a
584 breakpoint instruction. Return a pointer to a string of bytes that
585 encode a breakpoint instruction, store the length of the string in
586 *LEN and optionally adjust *PC to point to the correct memory
587 location for inserting the breakpoint. */
589 static const gdb_byte
*
590 sparc_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pc
, int *len
)
592 static const gdb_byte break_insn
[] = { 0x91, 0xd0, 0x20, 0x01 };
594 *len
= sizeof (break_insn
);
599 /* Allocate and initialize a frame cache. */
601 static struct sparc_frame_cache
*
602 sparc_alloc_frame_cache (void)
604 struct sparc_frame_cache
*cache
;
606 cache
= FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache
);
612 /* Frameless until proven otherwise. */
613 cache
->frameless_p
= 1;
614 cache
->frame_offset
= 0;
615 cache
->saved_regs_mask
= 0;
616 cache
->copied_regs_mask
= 0;
617 cache
->struct_return_p
= 0;
622 /* GCC generates several well-known sequences of instructions at the begining
623 of each function prologue when compiling with -fstack-check. If one of
624 such sequences starts at START_PC, then return the address of the
625 instruction immediately past this sequence. Otherwise, return START_PC. */
628 sparc_skip_stack_check (const CORE_ADDR start_pc
)
630 CORE_ADDR pc
= start_pc
;
632 int offset_stack_checking_sequence
= 0;
633 int probing_loop
= 0;
635 /* With GCC, all stack checking sequences begin with the same two
636 instructions, plus an optional one in the case of a probing loop:
638 sethi <some immediate>, %g1
643 sethi <some immediate>, %g1
644 sethi <some immediate>, %g4
649 sethi <some immediate>, %g1
651 sethi <some immediate>, %g4
653 If the optional instruction is found (setting g4), assume that a
654 probing loop will follow. */
656 /* sethi <some immediate>, %g1 */
657 insn
= sparc_fetch_instruction (pc
);
659 if (!(X_OP (insn
) == 0 && X_OP2 (insn
) == 0x4 && X_RD (insn
) == 1))
662 /* optional: sethi <some immediate>, %g4 */
663 insn
= sparc_fetch_instruction (pc
);
665 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 0x4 && X_RD (insn
) == 4)
668 insn
= sparc_fetch_instruction (pc
);
672 /* sub %sp, %g1, %g1 */
673 if (!(X_OP (insn
) == 2 && X_OP3 (insn
) == 0x4 && !X_I(insn
)
674 && X_RD (insn
) == 1 && X_RS1 (insn
) == 14 && X_RS2 (insn
) == 1))
677 insn
= sparc_fetch_instruction (pc
);
680 /* optional: sethi <some immediate>, %g4 */
681 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 0x4 && X_RD (insn
) == 4)
684 insn
= sparc_fetch_instruction (pc
);
688 /* First possible sequence:
689 [first two instructions above]
690 clr [%g1 - some immediate] */
692 /* clr [%g1 - some immediate] */
693 if (X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && X_I(insn
)
694 && X_RS1 (insn
) == 1 && X_RD (insn
) == 0)
696 /* Valid stack-check sequence, return the new PC. */
700 /* Second possible sequence: A small number of probes.
701 [first two instructions above]
703 add %g1, -<some immediate>, %g1
705 [repeat the two instructions above any (small) number of times]
706 clr [%g1 - some immediate] */
709 else if (X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && !X_I(insn
)
710 && X_RS1 (insn
) == 1 && X_RD (insn
) == 0)
714 /* add %g1, -<some immediate>, %g1 */
715 insn
= sparc_fetch_instruction (pc
);
717 if (!(X_OP (insn
) == 2 && X_OP3(insn
) == 0 && X_I(insn
)
718 && X_RS1 (insn
) == 1 && X_RD (insn
) == 1))
722 insn
= sparc_fetch_instruction (pc
);
724 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && !X_I(insn
)
725 && X_RD (insn
) == 0 && X_RS1 (insn
) == 1))
729 /* clr [%g1 - some immediate] */
730 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && X_I(insn
)
731 && X_RS1 (insn
) == 1 && X_RD (insn
) == 0))
734 /* We found a valid stack-check sequence, return the new PC. */
738 /* Third sequence: A probing loop.
739 [first three instructions above]
743 add %g1, -<some immediate>, %g1
747 And an optional last probe for the remainder:
749 clr [%g4 - some immediate] */
753 /* sub %g1, %g4, %g4 */
754 if (!(X_OP (insn
) == 2 && X_OP3 (insn
) == 0x4 && !X_I(insn
)
755 && X_RD (insn
) == 4 && X_RS1 (insn
) == 1 && X_RS2 (insn
) == 4))
759 insn
= sparc_fetch_instruction (pc
);
761 if (!(X_OP (insn
) == 2 && X_OP3 (insn
) == 0x14 && !X_I(insn
)
762 && X_RD (insn
) == 0 && X_RS1 (insn
) == 1 && X_RS2 (insn
) == 4))
766 insn
= sparc_fetch_instruction (pc
);
768 if (!(X_OP (insn
) == 0 && X_COND (insn
) == 0x1))
771 /* add %g1, -<some immediate>, %g1 */
772 insn
= sparc_fetch_instruction (pc
);
774 if (!(X_OP (insn
) == 2 && X_OP3(insn
) == 0 && X_I(insn
)
775 && X_RS1 (insn
) == 1 && X_RD (insn
) == 1))
779 insn
= sparc_fetch_instruction (pc
);
781 if (!(X_OP (insn
) == 0 && X_COND (insn
) == 0x8))
784 /* clr [%g1] (st %g0, [%g1] or st %g0, [%g1+0]) */
785 insn
= sparc_fetch_instruction (pc
);
787 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4
788 && X_RD (insn
) == 0 && X_RS1 (insn
) == 1
789 && (!X_I(insn
) || X_SIMM13 (insn
) == 0)))
792 /* We found a valid stack-check sequence, return the new PC. */
794 /* optional: clr [%g4 - some immediate] */
795 insn
= sparc_fetch_instruction (pc
);
797 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && X_I(insn
)
798 && X_RS1 (insn
) == 4 && X_RD (insn
) == 0))
804 /* No stack check code in our prologue, return the start_pc. */
808 /* Record the effect of a SAVE instruction on CACHE. */
811 sparc_record_save_insn (struct sparc_frame_cache
*cache
)
813 /* The frame is set up. */
814 cache
->frameless_p
= 0;
816 /* The frame pointer contains the CFA. */
817 cache
->frame_offset
= 0;
819 /* The `local' and `in' registers are all saved. */
820 cache
->saved_regs_mask
= 0xffff;
822 /* The `out' registers are all renamed. */
823 cache
->copied_regs_mask
= 0xff;
826 /* Do a full analysis of the prologue at PC and update CACHE accordingly.
827 Bail out early if CURRENT_PC is reached. Return the address where
828 the analysis stopped.
830 We handle both the traditional register window model and the single
831 register window (aka flat) model. */
834 sparc_analyze_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
835 CORE_ADDR current_pc
, struct sparc_frame_cache
*cache
)
837 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
842 pc
= sparc_skip_stack_check (pc
);
844 if (current_pc
<= pc
)
847 /* We have to handle to "Procedure Linkage Table" (PLT) special. On
848 SPARC the linker usually defines a symbol (typically
849 _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section.
850 This symbol makes us end up here with PC pointing at the start of
851 the PLT and CURRENT_PC probably pointing at a PLT entry. If we
852 would do our normal prologue analysis, we would probably conclude
853 that we've got a frame when in reality we don't, since the
854 dynamic linker patches up the first PLT with some code that
855 starts with a SAVE instruction. Patch up PC such that it points
856 at the start of our PLT entry. */
857 if (tdep
->plt_entry_size
> 0 && in_plt_section (current_pc
, NULL
))
858 pc
= current_pc
- ((current_pc
- pc
) % tdep
->plt_entry_size
);
860 insn
= sparc_fetch_instruction (pc
);
862 /* Recognize store insns and record their sources. */
863 while (X_OP (insn
) == 3
864 && (X_OP3 (insn
) == 0x4 /* stw */
865 || X_OP3 (insn
) == 0x7 /* std */
866 || X_OP3 (insn
) == 0xe) /* stx */
867 && X_RS1 (insn
) == SPARC_SP_REGNUM
)
869 int regnum
= X_RD (insn
);
871 /* Recognize stores into the corresponding stack slots. */
872 if (regnum
>= SPARC_L0_REGNUM
&& regnum
<= SPARC_I7_REGNUM
874 && X_SIMM13 (insn
) == (X_OP3 (insn
) == 0xe
875 ? (regnum
- SPARC_L0_REGNUM
) * 8 + BIAS
876 : (regnum
- SPARC_L0_REGNUM
) * 4))
877 || (!X_I (insn
) && regnum
== SPARC_L0_REGNUM
)))
879 cache
->saved_regs_mask
|= (1 << (regnum
- SPARC_L0_REGNUM
));
880 if (X_OP3 (insn
) == 0x7)
881 cache
->saved_regs_mask
|= (1 << (regnum
+ 1 - SPARC_L0_REGNUM
));
886 insn
= sparc_fetch_instruction (pc
+ offset
);
889 /* Recognize a SETHI insn and record its destination. */
890 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 0x04)
895 insn
= sparc_fetch_instruction (pc
+ offset
);
898 /* Allow for an arithmetic operation on DEST or %g1. */
899 if (X_OP (insn
) == 2 && X_I (insn
)
900 && (X_RD (insn
) == 1 || X_RD (insn
) == dest
))
904 insn
= sparc_fetch_instruction (pc
+ offset
);
907 /* Check for the SAVE instruction that sets up the frame. */
908 if (X_OP (insn
) == 2 && X_OP3 (insn
) == 0x3c)
910 sparc_record_save_insn (cache
);
915 /* Check for an arithmetic operation on %sp. */
917 && (X_OP3 (insn
) == 0 || X_OP3 (insn
) == 0x4)
918 && X_RS1 (insn
) == SPARC_SP_REGNUM
919 && X_RD (insn
) == SPARC_SP_REGNUM
)
923 cache
->frame_offset
= X_SIMM13 (insn
);
924 if (X_OP3 (insn
) == 0)
925 cache
->frame_offset
= -cache
->frame_offset
;
929 insn
= sparc_fetch_instruction (pc
+ offset
);
931 /* Check for an arithmetic operation that sets up the frame. */
933 && (X_OP3 (insn
) == 0 || X_OP3 (insn
) == 0x4)
934 && X_RS1 (insn
) == SPARC_SP_REGNUM
935 && X_RD (insn
) == SPARC_FP_REGNUM
)
937 cache
->frameless_p
= 0;
938 cache
->frame_offset
= 0;
939 /* We could check that the amount subtracted to %sp above is the
940 same as the one added here, but this seems superfluous. */
941 cache
->copied_regs_mask
|= 0x40;
944 insn
= sparc_fetch_instruction (pc
+ offset
);
947 /* Check for a move (or) operation that copies the return register. */
949 && X_OP3 (insn
) == 0x2
951 && X_RS1 (insn
) == SPARC_G0_REGNUM
952 && X_RS2 (insn
) == SPARC_O7_REGNUM
953 && X_RD (insn
) == SPARC_I7_REGNUM
)
955 cache
->copied_regs_mask
|= 0x80;
966 sparc_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
968 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
969 return frame_unwind_register_unsigned (this_frame
, tdep
->pc_regnum
);
972 /* Return PC of first real instruction of the function starting at
976 sparc32_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
978 struct symtab_and_line sal
;
979 CORE_ADDR func_start
, func_end
;
980 struct sparc_frame_cache cache
;
982 /* This is the preferred method, find the end of the prologue by
983 using the debugging information. */
984 if (find_pc_partial_function (start_pc
, NULL
, &func_start
, &func_end
))
986 sal
= find_pc_line (func_start
, 0);
988 if (sal
.end
< func_end
989 && start_pc
<= sal
.end
)
993 start_pc
= sparc_analyze_prologue (gdbarch
, start_pc
, 0xffffffffUL
, &cache
);
995 /* The psABI says that "Although the first 6 words of arguments
996 reside in registers, the standard stack frame reserves space for
997 them.". It also suggests that a function may use that space to
998 "write incoming arguments 0 to 5" into that space, and that's
999 indeed what GCC seems to be doing. In that case GCC will
1000 generate debug information that points to the stack slots instead
1001 of the registers, so we should consider the instructions that
1002 write out these incoming arguments onto the stack. */
1006 unsigned long insn
= sparc_fetch_instruction (start_pc
);
1008 /* Recognize instructions that store incoming arguments into the
1009 corresponding stack slots. */
1010 if (X_OP (insn
) == 3 && (X_OP3 (insn
) & 0x3c) == 0x04
1011 && X_I (insn
) && X_RS1 (insn
) == SPARC_FP_REGNUM
)
1013 int regnum
= X_RD (insn
);
1015 /* Case of arguments still in %o[0..5]. */
1016 if (regnum
>= SPARC_O0_REGNUM
&& regnum
<= SPARC_O5_REGNUM
1017 && !(cache
.copied_regs_mask
& (1 << (regnum
- SPARC_O0_REGNUM
)))
1018 && X_SIMM13 (insn
) == 68 + (regnum
- SPARC_O0_REGNUM
) * 4)
1024 /* Case of arguments copied into %i[0..5]. */
1025 if (regnum
>= SPARC_I0_REGNUM
&& regnum
<= SPARC_I5_REGNUM
1026 && (cache
.copied_regs_mask
& (1 << (regnum
- SPARC_I0_REGNUM
)))
1027 && X_SIMM13 (insn
) == 68 + (regnum
- SPARC_I0_REGNUM
) * 4)
1040 /* Normal frames. */
1042 struct sparc_frame_cache
*
1043 sparc_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1045 struct sparc_frame_cache
*cache
;
1050 cache
= sparc_alloc_frame_cache ();
1051 *this_cache
= cache
;
1053 cache
->pc
= get_frame_func (this_frame
);
1055 sparc_analyze_prologue (get_frame_arch (this_frame
), cache
->pc
,
1056 get_frame_pc (this_frame
), cache
);
1058 if (cache
->frameless_p
)
1060 /* This function is frameless, so %fp (%i6) holds the frame
1061 pointer for our calling frame. Use %sp (%o6) as this frame's
1064 get_frame_register_unsigned (this_frame
, SPARC_SP_REGNUM
);
1068 /* For normal frames, %fp (%i6) holds the frame pointer, the
1069 base address for the current stack frame. */
1071 get_frame_register_unsigned (this_frame
, SPARC_FP_REGNUM
);
1074 cache
->base
+= cache
->frame_offset
;
1076 if (cache
->base
& 1)
1077 cache
->base
+= BIAS
;
1083 sparc32_struct_return_from_sym (struct symbol
*sym
)
1085 struct type
*type
= check_typedef (SYMBOL_TYPE (sym
));
1086 enum type_code code
= TYPE_CODE (type
);
1088 if (code
== TYPE_CODE_FUNC
|| code
== TYPE_CODE_METHOD
)
1090 type
= check_typedef (TYPE_TARGET_TYPE (type
));
1091 if (sparc_structure_or_union_p (type
)
1092 || (sparc_floating_p (type
) && TYPE_LENGTH (type
) == 16))
1099 struct sparc_frame_cache
*
1100 sparc32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1102 struct sparc_frame_cache
*cache
;
1108 cache
= sparc_frame_cache (this_frame
, this_cache
);
1110 sym
= find_pc_function (cache
->pc
);
1113 cache
->struct_return_p
= sparc32_struct_return_from_sym (sym
);
1117 /* There is no debugging information for this function to
1118 help us determine whether this function returns a struct
1119 or not. So we rely on another heuristic which is to check
1120 the instruction at the return address and see if this is
1121 an "unimp" instruction. If it is, then it is a struct-return
1125 (cache
->copied_regs_mask
& 0x80) ? SPARC_I7_REGNUM
: SPARC_O7_REGNUM
;
1127 pc
= get_frame_register_unsigned (this_frame
, regnum
) + 8;
1128 if (sparc_is_unimp_insn (pc
))
1129 cache
->struct_return_p
= 1;
1136 sparc32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1137 struct frame_id
*this_id
)
1139 struct sparc_frame_cache
*cache
=
1140 sparc32_frame_cache (this_frame
, this_cache
);
1142 /* This marks the outermost frame. */
1143 if (cache
->base
== 0)
1146 (*this_id
) = frame_id_build (cache
->base
, cache
->pc
);
1149 static struct value
*
1150 sparc32_frame_prev_register (struct frame_info
*this_frame
,
1151 void **this_cache
, int regnum
)
1153 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1154 struct sparc_frame_cache
*cache
=
1155 sparc32_frame_cache (this_frame
, this_cache
);
1157 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== SPARC32_NPC_REGNUM
)
1159 CORE_ADDR pc
= (regnum
== SPARC32_NPC_REGNUM
) ? 4 : 0;
1161 /* If this functions has a Structure, Union or Quad-Precision
1162 return value, we have to skip the UNIMP instruction that encodes
1163 the size of the structure. */
1164 if (cache
->struct_return_p
)
1168 (cache
->copied_regs_mask
& 0x80) ? SPARC_I7_REGNUM
: SPARC_O7_REGNUM
;
1169 pc
+= get_frame_register_unsigned (this_frame
, regnum
) + 8;
1170 return frame_unwind_got_constant (this_frame
, regnum
, pc
);
1173 /* Handle StackGhost. */
1175 ULONGEST wcookie
= sparc_fetch_wcookie (gdbarch
);
1177 if (wcookie
!= 0 && !cache
->frameless_p
&& regnum
== SPARC_I7_REGNUM
)
1179 CORE_ADDR addr
= cache
->base
+ (regnum
- SPARC_L0_REGNUM
) * 4;
1182 /* Read the value in from memory. */
1183 i7
= get_frame_memory_unsigned (this_frame
, addr
, 4);
1184 return frame_unwind_got_constant (this_frame
, regnum
, i7
^ wcookie
);
1188 /* The previous frame's `local' and `in' registers may have been saved
1189 in the register save area. */
1190 if (regnum
>= SPARC_L0_REGNUM
&& regnum
<= SPARC_I7_REGNUM
1191 && (cache
->saved_regs_mask
& (1 << (regnum
- SPARC_L0_REGNUM
))))
1193 CORE_ADDR addr
= cache
->base
+ (regnum
- SPARC_L0_REGNUM
) * 4;
1195 return frame_unwind_got_memory (this_frame
, regnum
, addr
);
1198 /* The previous frame's `out' registers may be accessible as the current
1199 frame's `in' registers. */
1200 if (regnum
>= SPARC_O0_REGNUM
&& regnum
<= SPARC_O7_REGNUM
1201 && (cache
->copied_regs_mask
& (1 << (regnum
- SPARC_O0_REGNUM
))))
1202 regnum
+= (SPARC_I0_REGNUM
- SPARC_O0_REGNUM
);
1204 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1207 static const struct frame_unwind sparc32_frame_unwind
=
1210 default_frame_unwind_stop_reason
,
1211 sparc32_frame_this_id
,
1212 sparc32_frame_prev_register
,
1214 default_frame_sniffer
1219 sparc32_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
1221 struct sparc_frame_cache
*cache
=
1222 sparc32_frame_cache (this_frame
, this_cache
);
1227 static const struct frame_base sparc32_frame_base
=
1229 &sparc32_frame_unwind
,
1230 sparc32_frame_base_address
,
1231 sparc32_frame_base_address
,
1232 sparc32_frame_base_address
1235 static struct frame_id
1236 sparc_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1240 sp
= get_frame_register_unsigned (this_frame
, SPARC_SP_REGNUM
);
1243 return frame_id_build (sp
, get_frame_pc (this_frame
));
1247 /* Extract a function return value of TYPE from REGCACHE, and copy
1248 that into VALBUF. */
1251 sparc32_extract_return_value (struct type
*type
, struct regcache
*regcache
,
1254 int len
= TYPE_LENGTH (type
);
1257 gdb_assert (!sparc_structure_or_union_p (type
));
1258 gdb_assert (!(sparc_floating_p (type
) && len
== 16));
1260 if (sparc_floating_p (type
) || sparc_complex_floating_p (type
))
1262 /* Floating return values. */
1263 regcache_cooked_read (regcache
, SPARC_F0_REGNUM
, buf
);
1265 regcache_cooked_read (regcache
, SPARC_F1_REGNUM
, buf
+ 4);
1268 regcache_cooked_read (regcache
, SPARC_F2_REGNUM
, buf
+ 8);
1269 regcache_cooked_read (regcache
, SPARC_F3_REGNUM
, buf
+ 12);
1273 regcache_cooked_read (regcache
, SPARC_F4_REGNUM
, buf
+ 16);
1274 regcache_cooked_read (regcache
, SPARC_F5_REGNUM
, buf
+ 20);
1275 regcache_cooked_read (regcache
, SPARC_F6_REGNUM
, buf
+ 24);
1276 regcache_cooked_read (regcache
, SPARC_F7_REGNUM
, buf
+ 28);
1278 memcpy (valbuf
, buf
, len
);
1282 /* Integral and pointer return values. */
1283 gdb_assert (sparc_integral_or_pointer_p (type
));
1285 regcache_cooked_read (regcache
, SPARC_O0_REGNUM
, buf
);
1288 regcache_cooked_read (regcache
, SPARC_O1_REGNUM
, buf
+ 4);
1289 gdb_assert (len
== 8);
1290 memcpy (valbuf
, buf
, 8);
1294 /* Just stripping off any unused bytes should preserve the
1295 signed-ness just fine. */
1296 memcpy (valbuf
, buf
+ 4 - len
, len
);
1301 /* Store the function return value of type TYPE from VALBUF into
1305 sparc32_store_return_value (struct type
*type
, struct regcache
*regcache
,
1306 const gdb_byte
*valbuf
)
1308 int len
= TYPE_LENGTH (type
);
1311 gdb_assert (!sparc_structure_or_union_p (type
));
1312 gdb_assert (!(sparc_floating_p (type
) && len
== 16));
1313 gdb_assert (len
<= 8);
1315 if (sparc_floating_p (type
) || sparc_complex_floating_p (type
))
1317 /* Floating return values. */
1318 memcpy (buf
, valbuf
, len
);
1319 regcache_cooked_write (regcache
, SPARC_F0_REGNUM
, buf
);
1321 regcache_cooked_write (regcache
, SPARC_F1_REGNUM
, buf
+ 4);
1324 regcache_cooked_write (regcache
, SPARC_F2_REGNUM
, buf
+ 8);
1325 regcache_cooked_write (regcache
, SPARC_F3_REGNUM
, buf
+ 12);
1329 regcache_cooked_write (regcache
, SPARC_F4_REGNUM
, buf
+ 16);
1330 regcache_cooked_write (regcache
, SPARC_F5_REGNUM
, buf
+ 20);
1331 regcache_cooked_write (regcache
, SPARC_F6_REGNUM
, buf
+ 24);
1332 regcache_cooked_write (regcache
, SPARC_F7_REGNUM
, buf
+ 28);
1337 /* Integral and pointer return values. */
1338 gdb_assert (sparc_integral_or_pointer_p (type
));
1342 gdb_assert (len
== 8);
1343 memcpy (buf
, valbuf
, 8);
1344 regcache_cooked_write (regcache
, SPARC_O1_REGNUM
, buf
+ 4);
1348 /* ??? Do we need to do any sign-extension here? */
1349 memcpy (buf
+ 4 - len
, valbuf
, len
);
1351 regcache_cooked_write (regcache
, SPARC_O0_REGNUM
, buf
);
1355 static enum return_value_convention
1356 sparc32_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
1357 struct type
*type
, struct regcache
*regcache
,
1358 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1360 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1362 /* The psABI says that "...every stack frame reserves the word at
1363 %fp+64. If a function returns a structure, union, or
1364 quad-precision value, this word should hold the address of the
1365 object into which the return value should be copied." This
1366 guarantees that we can always find the return value, not just
1367 before the function returns. */
1369 if (sparc_structure_or_union_p (type
)
1370 || (sparc_floating_p (type
) && TYPE_LENGTH (type
) == 16))
1377 regcache_cooked_read_unsigned (regcache
, SPARC_SP_REGNUM
, &sp
);
1378 addr
= read_memory_unsigned_integer (sp
+ 64, 4, byte_order
);
1379 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
1382 return RETURN_VALUE_ABI_PRESERVES_ADDRESS
;
1386 sparc32_extract_return_value (type
, regcache
, readbuf
);
1388 sparc32_store_return_value (type
, regcache
, writebuf
);
1390 return RETURN_VALUE_REGISTER_CONVENTION
;
1394 sparc32_stabs_argument_has_addr (struct gdbarch
*gdbarch
, struct type
*type
)
1396 return (sparc_structure_or_union_p (type
)
1397 || (sparc_floating_p (type
) && TYPE_LENGTH (type
) == 16)
1398 || sparc_complex_floating_p (type
));
1402 sparc32_dwarf2_struct_return_p (struct frame_info
*this_frame
)
1404 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
1405 struct symbol
*sym
= find_pc_function (pc
);
1408 return sparc32_struct_return_from_sym (sym
);
1413 sparc32_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1414 struct dwarf2_frame_state_reg
*reg
,
1415 struct frame_info
*this_frame
)
1421 case SPARC_G0_REGNUM
:
1422 /* Since %g0 is always zero, there is no point in saving it, and
1423 people will be inclined omit it from the CFI. Make sure we
1424 don't warn about that. */
1425 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
1427 case SPARC_SP_REGNUM
:
1428 reg
->how
= DWARF2_FRAME_REG_CFA
;
1430 case SPARC32_PC_REGNUM
:
1431 case SPARC32_NPC_REGNUM
:
1432 reg
->how
= DWARF2_FRAME_REG_RA_OFFSET
;
1434 if (sparc32_dwarf2_struct_return_p (this_frame
))
1436 if (regnum
== SPARC32_NPC_REGNUM
)
1438 reg
->loc
.offset
= off
;
1444 /* The SPARC Architecture doesn't have hardware single-step support,
1445 and most operating systems don't implement it either, so we provide
1446 software single-step mechanism. */
1449 sparc_analyze_control_transfer (struct frame_info
*frame
,
1450 CORE_ADDR pc
, CORE_ADDR
*npc
)
1452 unsigned long insn
= sparc_fetch_instruction (pc
);
1453 int conditional_p
= X_COND (insn
) & 0x7;
1454 int branch_p
= 0, fused_p
= 0;
1455 long offset
= 0; /* Must be signed for sign-extend. */
1457 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 3)
1459 if ((insn
& 0x10000000) == 0)
1461 /* Branch on Integer Register with Prediction (BPr). */
1467 /* Compare and Branch */
1470 offset
= 4 * X_DISP10 (insn
);
1473 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 6)
1475 /* Branch on Floating-Point Condition Codes (FBfcc). */
1477 offset
= 4 * X_DISP22 (insn
);
1479 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 5)
1481 /* Branch on Floating-Point Condition Codes with Prediction
1484 offset
= 4 * X_DISP19 (insn
);
1486 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 2)
1488 /* Branch on Integer Condition Codes (Bicc). */
1490 offset
= 4 * X_DISP22 (insn
);
1492 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 1)
1494 /* Branch on Integer Condition Codes with Prediction (BPcc). */
1496 offset
= 4 * X_DISP19 (insn
);
1498 else if (X_OP (insn
) == 2 && X_OP3 (insn
) == 0x3a)
1500 /* Trap instruction (TRAP). */
1501 return gdbarch_tdep (get_frame_arch (frame
))->step_trap (frame
, insn
);
1504 /* FIXME: Handle DONE and RETRY instructions. */
1510 /* Fused compare-and-branch instructions are non-delayed,
1511 and do not have an annuling capability. So we need to
1512 always set a breakpoint on both the NPC and the branch
1514 gdb_assert (offset
!= 0);
1517 else if (conditional_p
)
1519 /* For conditional branches, return nPC + 4 iff the annul
1521 return (X_A (insn
) ? *npc
+ 4 : 0);
1525 /* For unconditional branches, return the target if its
1526 specified condition is "always" and return nPC + 4 if the
1527 condition is "never". If the annul bit is 1, set *NPC to
1529 if (X_COND (insn
) == 0x0)
1530 pc
= *npc
, offset
= 4;
1534 gdb_assert (offset
!= 0);
1543 sparc_step_trap (struct frame_info
*frame
, unsigned long insn
)
1549 sparc_software_single_step (struct frame_info
*frame
)
1551 struct gdbarch
*arch
= get_frame_arch (frame
);
1552 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
1553 struct address_space
*aspace
= get_frame_address_space (frame
);
1554 CORE_ADDR npc
, nnpc
;
1556 CORE_ADDR pc
, orig_npc
;
1558 pc
= get_frame_register_unsigned (frame
, tdep
->pc_regnum
);
1559 orig_npc
= npc
= get_frame_register_unsigned (frame
, tdep
->npc_regnum
);
1561 /* Analyze the instruction at PC. */
1562 nnpc
= sparc_analyze_control_transfer (frame
, pc
, &npc
);
1564 insert_single_step_breakpoint (arch
, aspace
, npc
);
1567 insert_single_step_breakpoint (arch
, aspace
, nnpc
);
1569 /* Assert that we have set at least one breakpoint, and that
1570 they're not set at the same spot - unless we're going
1571 from here straight to NULL, i.e. a call or jump to 0. */
1572 gdb_assert (npc
!= 0 || nnpc
!= 0 || orig_npc
== 0);
1573 gdb_assert (nnpc
!= npc
|| orig_npc
== 0);
1579 sparc_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1581 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_regcache_arch (regcache
));
1583 regcache_cooked_write_unsigned (regcache
, tdep
->pc_regnum
, pc
);
1584 regcache_cooked_write_unsigned (regcache
, tdep
->npc_regnum
, pc
+ 4);
1588 /* Return the appropriate register set for the core section identified
1589 by SECT_NAME and SECT_SIZE. */
1591 static const struct regset
*
1592 sparc_regset_from_core_section (struct gdbarch
*gdbarch
,
1593 const char *sect_name
, size_t sect_size
)
1595 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1597 if (strcmp (sect_name
, ".reg") == 0 && sect_size
>= tdep
->sizeof_gregset
)
1598 return tdep
->gregset
;
1600 if (strcmp (sect_name
, ".reg2") == 0 && sect_size
>= tdep
->sizeof_fpregset
)
1601 return tdep
->fpregset
;
1607 static struct gdbarch
*
1608 sparc32_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1610 struct gdbarch_tdep
*tdep
;
1611 struct gdbarch
*gdbarch
;
1613 /* If there is already a candidate, use it. */
1614 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
1616 return arches
->gdbarch
;
1618 /* Allocate space for the new architecture. */
1619 tdep
= XZALLOC (struct gdbarch_tdep
);
1620 gdbarch
= gdbarch_alloc (&info
, tdep
);
1622 tdep
->pc_regnum
= SPARC32_PC_REGNUM
;
1623 tdep
->npc_regnum
= SPARC32_NPC_REGNUM
;
1624 tdep
->step_trap
= sparc_step_trap
;
1626 set_gdbarch_long_double_bit (gdbarch
, 128);
1627 set_gdbarch_long_double_format (gdbarch
, floatformats_sparc_quad
);
1629 set_gdbarch_num_regs (gdbarch
, SPARC32_NUM_REGS
);
1630 set_gdbarch_register_name (gdbarch
, sparc32_register_name
);
1631 set_gdbarch_register_type (gdbarch
, sparc32_register_type
);
1632 set_gdbarch_num_pseudo_regs (gdbarch
, SPARC32_NUM_PSEUDO_REGS
);
1633 set_gdbarch_pseudo_register_read (gdbarch
, sparc32_pseudo_register_read
);
1634 set_gdbarch_pseudo_register_write (gdbarch
, sparc32_pseudo_register_write
);
1636 /* Register numbers of various important registers. */
1637 set_gdbarch_sp_regnum (gdbarch
, SPARC_SP_REGNUM
); /* %sp */
1638 set_gdbarch_pc_regnum (gdbarch
, SPARC32_PC_REGNUM
); /* %pc */
1639 set_gdbarch_fp0_regnum (gdbarch
, SPARC_F0_REGNUM
); /* %f0 */
1641 /* Call dummy code. */
1642 set_gdbarch_frame_align (gdbarch
, sparc32_frame_align
);
1643 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
1644 set_gdbarch_push_dummy_code (gdbarch
, sparc32_push_dummy_code
);
1645 set_gdbarch_push_dummy_call (gdbarch
, sparc32_push_dummy_call
);
1647 set_gdbarch_return_value (gdbarch
, sparc32_return_value
);
1648 set_gdbarch_stabs_argument_has_addr
1649 (gdbarch
, sparc32_stabs_argument_has_addr
);
1651 set_gdbarch_skip_prologue (gdbarch
, sparc32_skip_prologue
);
1653 /* Stack grows downward. */
1654 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
1656 set_gdbarch_breakpoint_from_pc (gdbarch
, sparc_breakpoint_from_pc
);
1658 set_gdbarch_frame_args_skip (gdbarch
, 8);
1660 set_gdbarch_print_insn (gdbarch
, print_insn_sparc
);
1662 set_gdbarch_software_single_step (gdbarch
, sparc_software_single_step
);
1663 set_gdbarch_write_pc (gdbarch
, sparc_write_pc
);
1665 set_gdbarch_dummy_id (gdbarch
, sparc_dummy_id
);
1667 set_gdbarch_unwind_pc (gdbarch
, sparc_unwind_pc
);
1669 frame_base_set_default (gdbarch
, &sparc32_frame_base
);
1671 /* Hook in the DWARF CFI frame unwinder. */
1672 dwarf2_frame_set_init_reg (gdbarch
, sparc32_dwarf2_frame_init_reg
);
1673 /* FIXME: kettenis/20050423: Don't enable the unwinder until the
1674 StackGhost issues have been resolved. */
1676 /* Hook in ABI-specific overrides, if they have been registered. */
1677 gdbarch_init_osabi (info
, gdbarch
);
1679 frame_unwind_append_unwinder (gdbarch
, &sparc32_frame_unwind
);
1681 /* If we have register sets, enable the generic core file support. */
1683 set_gdbarch_regset_from_core_section (gdbarch
,
1684 sparc_regset_from_core_section
);
1689 /* Helper functions for dealing with register windows. */
1692 sparc_supply_rwindow (struct regcache
*regcache
, CORE_ADDR sp
, int regnum
)
1694 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1695 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1702 /* Registers are 64-bit. */
1705 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1707 if (regnum
== i
|| regnum
== -1)
1709 target_read_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 8), buf
, 8);
1711 /* Handle StackGhost. */
1712 if (i
== SPARC_I7_REGNUM
)
1714 ULONGEST wcookie
= sparc_fetch_wcookie (gdbarch
);
1717 i7
= extract_unsigned_integer (buf
+ offset
, 8, byte_order
);
1718 store_unsigned_integer (buf
+ offset
, 8, byte_order
,
1722 regcache_raw_supply (regcache
, i
, buf
);
1728 /* Registers are 32-bit. Toss any sign-extension of the stack
1732 /* Clear out the top half of the temporary buffer, and put the
1733 register value in the bottom half if we're in 64-bit mode. */
1734 if (gdbarch_ptr_bit (get_regcache_arch (regcache
)) == 64)
1740 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1742 if (regnum
== i
|| regnum
== -1)
1744 target_read_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 4),
1747 /* Handle StackGhost. */
1748 if (i
== SPARC_I7_REGNUM
)
1750 ULONGEST wcookie
= sparc_fetch_wcookie (gdbarch
);
1753 i7
= extract_unsigned_integer (buf
+ offset
, 4, byte_order
);
1754 store_unsigned_integer (buf
+ offset
, 4, byte_order
,
1758 regcache_raw_supply (regcache
, i
, buf
);
1765 sparc_collect_rwindow (const struct regcache
*regcache
,
1766 CORE_ADDR sp
, int regnum
)
1768 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1769 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1776 /* Registers are 64-bit. */
1779 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1781 if (regnum
== -1 || regnum
== SPARC_SP_REGNUM
|| regnum
== i
)
1783 regcache_raw_collect (regcache
, i
, buf
);
1785 /* Handle StackGhost. */
1786 if (i
== SPARC_I7_REGNUM
)
1788 ULONGEST wcookie
= sparc_fetch_wcookie (gdbarch
);
1791 i7
= extract_unsigned_integer (buf
+ offset
, 8, byte_order
);
1792 store_unsigned_integer (buf
, 8, byte_order
, i7
^ wcookie
);
1795 target_write_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 8), buf
, 8);
1801 /* Registers are 32-bit. Toss any sign-extension of the stack
1805 /* Only use the bottom half if we're in 64-bit mode. */
1806 if (gdbarch_ptr_bit (get_regcache_arch (regcache
)) == 64)
1809 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1811 if (regnum
== -1 || regnum
== SPARC_SP_REGNUM
|| regnum
== i
)
1813 regcache_raw_collect (regcache
, i
, buf
);
1815 /* Handle StackGhost. */
1816 if (i
== SPARC_I7_REGNUM
)
1818 ULONGEST wcookie
= sparc_fetch_wcookie (gdbarch
);
1821 i7
= extract_unsigned_integer (buf
+ offset
, 4, byte_order
);
1822 store_unsigned_integer (buf
+ offset
, 4, byte_order
,
1826 target_write_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 4),
1833 /* Helper functions for dealing with register sets. */
1836 sparc32_supply_gregset (const struct sparc_gregset
*gregset
,
1837 struct regcache
*regcache
,
1838 int regnum
, const void *gregs
)
1840 const gdb_byte
*regs
= gregs
;
1841 gdb_byte zero
[4] = { 0 };
1844 if (regnum
== SPARC32_PSR_REGNUM
|| regnum
== -1)
1845 regcache_raw_supply (regcache
, SPARC32_PSR_REGNUM
,
1846 regs
+ gregset
->r_psr_offset
);
1848 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== -1)
1849 regcache_raw_supply (regcache
, SPARC32_PC_REGNUM
,
1850 regs
+ gregset
->r_pc_offset
);
1852 if (regnum
== SPARC32_NPC_REGNUM
|| regnum
== -1)
1853 regcache_raw_supply (regcache
, SPARC32_NPC_REGNUM
,
1854 regs
+ gregset
->r_npc_offset
);
1856 if (regnum
== SPARC32_Y_REGNUM
|| regnum
== -1)
1857 regcache_raw_supply (regcache
, SPARC32_Y_REGNUM
,
1858 regs
+ gregset
->r_y_offset
);
1860 if (regnum
== SPARC_G0_REGNUM
|| regnum
== -1)
1861 regcache_raw_supply (regcache
, SPARC_G0_REGNUM
, &zero
);
1863 if ((regnum
>= SPARC_G1_REGNUM
&& regnum
<= SPARC_O7_REGNUM
) || regnum
== -1)
1865 int offset
= gregset
->r_g1_offset
;
1867 for (i
= SPARC_G1_REGNUM
; i
<= SPARC_O7_REGNUM
; i
++)
1869 if (regnum
== i
|| regnum
== -1)
1870 regcache_raw_supply (regcache
, i
, regs
+ offset
);
1875 if ((regnum
>= SPARC_L0_REGNUM
&& regnum
<= SPARC_I7_REGNUM
) || regnum
== -1)
1877 /* Not all of the register set variants include Locals and
1878 Inputs. For those that don't, we read them off the stack. */
1879 if (gregset
->r_l0_offset
== -1)
1883 regcache_cooked_read_unsigned (regcache
, SPARC_SP_REGNUM
, &sp
);
1884 sparc_supply_rwindow (regcache
, sp
, regnum
);
1888 int offset
= gregset
->r_l0_offset
;
1890 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1892 if (regnum
== i
|| regnum
== -1)
1893 regcache_raw_supply (regcache
, i
, regs
+ offset
);
1901 sparc32_collect_gregset (const struct sparc_gregset
*gregset
,
1902 const struct regcache
*regcache
,
1903 int regnum
, void *gregs
)
1905 gdb_byte
*regs
= gregs
;
1908 if (regnum
== SPARC32_PSR_REGNUM
|| regnum
== -1)
1909 regcache_raw_collect (regcache
, SPARC32_PSR_REGNUM
,
1910 regs
+ gregset
->r_psr_offset
);
1912 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== -1)
1913 regcache_raw_collect (regcache
, SPARC32_PC_REGNUM
,
1914 regs
+ gregset
->r_pc_offset
);
1916 if (regnum
== SPARC32_NPC_REGNUM
|| regnum
== -1)
1917 regcache_raw_collect (regcache
, SPARC32_NPC_REGNUM
,
1918 regs
+ gregset
->r_npc_offset
);
1920 if (regnum
== SPARC32_Y_REGNUM
|| regnum
== -1)
1921 regcache_raw_collect (regcache
, SPARC32_Y_REGNUM
,
1922 regs
+ gregset
->r_y_offset
);
1924 if ((regnum
>= SPARC_G1_REGNUM
&& regnum
<= SPARC_O7_REGNUM
) || regnum
== -1)
1926 int offset
= gregset
->r_g1_offset
;
1928 /* %g0 is always zero. */
1929 for (i
= SPARC_G1_REGNUM
; i
<= SPARC_O7_REGNUM
; i
++)
1931 if (regnum
== i
|| regnum
== -1)
1932 regcache_raw_collect (regcache
, i
, regs
+ offset
);
1937 if ((regnum
>= SPARC_L0_REGNUM
&& regnum
<= SPARC_I7_REGNUM
) || regnum
== -1)
1939 /* Not all of the register set variants include Locals and
1940 Inputs. For those that don't, we read them off the stack. */
1941 if (gregset
->r_l0_offset
!= -1)
1943 int offset
= gregset
->r_l0_offset
;
1945 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1947 if (regnum
== i
|| regnum
== -1)
1948 regcache_raw_collect (regcache
, i
, regs
+ offset
);
1956 sparc32_supply_fpregset (struct regcache
*regcache
,
1957 int regnum
, const void *fpregs
)
1959 const gdb_byte
*regs
= fpregs
;
1962 for (i
= 0; i
< 32; i
++)
1964 if (regnum
== (SPARC_F0_REGNUM
+ i
) || regnum
== -1)
1965 regcache_raw_supply (regcache
, SPARC_F0_REGNUM
+ i
, regs
+ (i
* 4));
1968 if (regnum
== SPARC32_FSR_REGNUM
|| regnum
== -1)
1969 regcache_raw_supply (regcache
, SPARC32_FSR_REGNUM
, regs
+ (32 * 4) + 4);
1973 sparc32_collect_fpregset (const struct regcache
*regcache
,
1974 int regnum
, void *fpregs
)
1976 gdb_byte
*regs
= fpregs
;
1979 for (i
= 0; i
< 32; i
++)
1981 if (regnum
== (SPARC_F0_REGNUM
+ i
) || regnum
== -1)
1982 regcache_raw_collect (regcache
, SPARC_F0_REGNUM
+ i
, regs
+ (i
* 4));
1985 if (regnum
== SPARC32_FSR_REGNUM
|| regnum
== -1)
1986 regcache_raw_collect (regcache
, SPARC32_FSR_REGNUM
, regs
+ (32 * 4) + 4);
1992 /* From <machine/reg.h>. */
1993 const struct sparc_gregset sparc32_sunos4_gregset
=
2006 /* Provide a prototype to silence -Wmissing-prototypes. */
2007 void _initialize_sparc_tdep (void);
2010 _initialize_sparc_tdep (void)
2012 register_gdbarch_init (bfd_arch_sparc
, sparc32_gdbarch_init
);