1 /* Target-dependent code for SPARC.
3 Copyright (C) 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street, Fifth Floor,
20 Boston, MA 02110-1301, USA. */
23 #include "arch-utils.h"
25 #include "dwarf2-frame.h"
26 #include "floatformat.h"
28 #include "frame-base.h"
29 #include "frame-unwind.h"
40 #include "gdb_assert.h"
41 #include "gdb_string.h"
43 #include "sparc-tdep.h"
47 /* This file implements the SPARC 32-bit ABI as defined by the section
48 "Low-Level System Information" of the SPARC Compliance Definition
49 (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC. The SCD
50 lists changes with respect to the original 32-bit psABI as defined
51 in the "System V ABI, SPARC Processor Supplement".
53 Note that if we talk about SunOS, we mean SunOS 4.x, which was
54 BSD-based, which is sometimes (retroactively?) referred to as
55 Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and
56 above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9
57 suffering from severe version number inflation). Solaris 2.x is
58 also known as SunOS 5.x, since that's what uname(1) says. Solaris
61 /* Please use the sparc32_-prefix for 32-bit specific code, the
62 sparc64_-prefix for 64-bit specific code and the sparc_-prefix for
63 code that can handle both. The 64-bit specific code lives in
64 sparc64-tdep.c; don't add any here. */
66 /* The SPARC Floating-Point Quad-Precision format is similar to
67 big-endian IA-64 Quad-recision format. */
68 #define floatformats_sparc_quad floatformats_ia64_quad
70 /* The stack pointer is offset from the stack frame by a BIAS of 2047
71 (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC
72 hosts, so undefine it first. */
76 /* Macros to extract fields from SPARC instructions. */
77 #define X_OP(i) (((i) >> 30) & 0x3)
78 #define X_RD(i) (((i) >> 25) & 0x1f)
79 #define X_A(i) (((i) >> 29) & 1)
80 #define X_COND(i) (((i) >> 25) & 0xf)
81 #define X_OP2(i) (((i) >> 22) & 0x7)
82 #define X_IMM22(i) ((i) & 0x3fffff)
83 #define X_OP3(i) (((i) >> 19) & 0x3f)
84 #define X_RS1(i) (((i) >> 14) & 0x1f)
85 #define X_RS2(i) ((i) & 0x1f)
86 #define X_I(i) (((i) >> 13) & 1)
87 /* Sign extension macros. */
88 #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000)
89 #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000)
90 #define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000)
92 /* Fetch the instruction at PC. Instructions are always big-endian
93 even if the processor operates in little-endian mode. */
96 sparc_fetch_instruction (CORE_ADDR pc
)
102 /* If we can't read the instruction at PC, return zero. */
103 if (read_memory_nobpt (pc
, buf
, sizeof (buf
)))
107 for (i
= 0; i
< sizeof (buf
); i
++)
108 insn
= (insn
<< 8) | buf
[i
];
113 /* Return non-zero if the instruction corresponding to PC is an "unimp"
117 sparc_is_unimp_insn (CORE_ADDR pc
)
119 const unsigned long insn
= sparc_fetch_instruction (pc
);
121 return ((insn
& 0xc1c00000) == 0);
124 /* OpenBSD/sparc includes StackGhost, which according to the author's
125 website http://stackghost.cerias.purdue.edu "... transparently and
126 automatically protects applications' stack frames; more
127 specifically, it guards the return pointers. The protection
128 mechanisms require no application source or binary modification and
129 imposes only a negligible performance penalty."
131 The same website provides the following description of how
134 "StackGhost interfaces with the kernel trap handler that would
135 normally write out registers to the stack and the handler that
136 would read them back in. By XORing a cookie into the
137 return-address saved in the user stack when it is actually written
138 to the stack, and then XOR it out when the return-address is pulled
139 from the stack, StackGhost can cause attacker corrupted return
140 pointers to behave in a manner the attacker cannot predict.
141 StackGhost can also use several unused bits in the return pointer
142 to detect a smashed return pointer and abort the process."
144 For GDB this means that whenever we're reading %i7 from a stack
145 frame's window save area, we'll have to XOR the cookie.
147 More information on StackGuard can be found on in:
149 Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated
150 Stack Protection." 2001. Published in USENIX Security Symposium
153 /* Fetch StackGhost Per-Process XOR cookie. */
156 sparc_fetch_wcookie (void)
158 struct target_ops
*ops
= ¤t_target
;
162 len
= target_read (ops
, TARGET_OBJECT_WCOOKIE
, NULL
, buf
, 0, 8);
166 /* We should have either an 32-bit or an 64-bit cookie. */
167 gdb_assert (len
== 4 || len
== 8);
169 return extract_unsigned_integer (buf
, len
);
173 /* The functions on this page are intended to be used to classify
174 function arguments. */
176 /* Check whether TYPE is "Integral or Pointer". */
179 sparc_integral_or_pointer_p (const struct type
*type
)
181 int len
= TYPE_LENGTH (type
);
183 switch (TYPE_CODE (type
))
189 case TYPE_CODE_RANGE
:
190 /* We have byte, half-word, word and extended-word/doubleword
191 integral types. The doubleword is an extension to the
192 original 32-bit ABI by the SCD 2.4.x. */
193 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
196 /* Allow either 32-bit or 64-bit pointers. */
197 return (len
== 4 || len
== 8);
205 /* Check whether TYPE is "Floating". */
208 sparc_floating_p (const struct type
*type
)
210 switch (TYPE_CODE (type
))
214 int len
= TYPE_LENGTH (type
);
215 return (len
== 4 || len
== 8 || len
== 16);
224 /* Check whether TYPE is "Structure or Union". */
227 sparc_structure_or_union_p (const struct type
*type
)
229 switch (TYPE_CODE (type
))
231 case TYPE_CODE_STRUCT
:
232 case TYPE_CODE_UNION
:
241 /* Register information. */
243 static const char *sparc32_register_names
[] =
245 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
246 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
247 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
248 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
250 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
251 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
252 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
253 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
255 "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr"
258 /* Total number of registers. */
259 #define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names)
261 /* We provide the aliases %d0..%d30 for the floating registers as
262 "psuedo" registers. */
264 static const char *sparc32_pseudo_register_names
[] =
266 "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14",
267 "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30"
270 /* Total number of pseudo registers. */
271 #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names)
273 /* Return the name of register REGNUM. */
276 sparc32_register_name (int regnum
)
278 if (regnum
>= 0 && regnum
< SPARC32_NUM_REGS
)
279 return sparc32_register_names
[regnum
];
281 if (regnum
< SPARC32_NUM_REGS
+ SPARC32_NUM_PSEUDO_REGS
)
282 return sparc32_pseudo_register_names
[regnum
- SPARC32_NUM_REGS
];
289 struct type
*sparc_psr_type
;
292 struct type
*sparc_fsr_type
;
294 /* Construct types for ISA-specific registers. */
297 sparc_init_types (void)
301 type
= init_flags_type ("builtin_type_sparc_psr", 4);
302 append_flags_type_flag (type
, 5, "ET");
303 append_flags_type_flag (type
, 6, "PS");
304 append_flags_type_flag (type
, 7, "S");
305 append_flags_type_flag (type
, 12, "EF");
306 append_flags_type_flag (type
, 13, "EC");
307 sparc_psr_type
= type
;
309 type
= init_flags_type ("builtin_type_sparc_fsr", 4);
310 append_flags_type_flag (type
, 0, "NXA");
311 append_flags_type_flag (type
, 1, "DZA");
312 append_flags_type_flag (type
, 2, "UFA");
313 append_flags_type_flag (type
, 3, "OFA");
314 append_flags_type_flag (type
, 4, "NVA");
315 append_flags_type_flag (type
, 5, "NXC");
316 append_flags_type_flag (type
, 6, "DZC");
317 append_flags_type_flag (type
, 7, "UFC");
318 append_flags_type_flag (type
, 8, "OFC");
319 append_flags_type_flag (type
, 9, "NVC");
320 append_flags_type_flag (type
, 22, "NS");
321 append_flags_type_flag (type
, 23, "NXM");
322 append_flags_type_flag (type
, 24, "DZM");
323 append_flags_type_flag (type
, 25, "UFM");
324 append_flags_type_flag (type
, 26, "OFM");
325 append_flags_type_flag (type
, 27, "NVM");
326 sparc_fsr_type
= type
;
329 /* Return the GDB type object for the "standard" data type of data in
333 sparc32_register_type (struct gdbarch
*gdbarch
, int regnum
)
335 if (regnum
>= SPARC_F0_REGNUM
&& regnum
<= SPARC_F31_REGNUM
)
336 return builtin_type_float
;
338 if (regnum
>= SPARC32_D0_REGNUM
&& regnum
<= SPARC32_D30_REGNUM
)
339 return builtin_type_double
;
341 if (regnum
== SPARC_SP_REGNUM
|| regnum
== SPARC_FP_REGNUM
)
342 return builtin_type_void_data_ptr
;
344 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== SPARC32_NPC_REGNUM
)
345 return builtin_type_void_func_ptr
;
347 if (regnum
== SPARC32_PSR_REGNUM
)
348 return sparc_psr_type
;
350 if (regnum
== SPARC32_FSR_REGNUM
)
351 return sparc_fsr_type
;
353 return builtin_type_int32
;
357 sparc32_pseudo_register_read (struct gdbarch
*gdbarch
,
358 struct regcache
*regcache
,
359 int regnum
, gdb_byte
*buf
)
361 gdb_assert (regnum
>= SPARC32_D0_REGNUM
&& regnum
<= SPARC32_D30_REGNUM
);
363 regnum
= SPARC_F0_REGNUM
+ 2 * (regnum
- SPARC32_D0_REGNUM
);
364 regcache_raw_read (regcache
, regnum
, buf
);
365 regcache_raw_read (regcache
, regnum
+ 1, buf
+ 4);
369 sparc32_pseudo_register_write (struct gdbarch
*gdbarch
,
370 struct regcache
*regcache
,
371 int regnum
, const gdb_byte
*buf
)
373 gdb_assert (regnum
>= SPARC32_D0_REGNUM
&& regnum
<= SPARC32_D30_REGNUM
);
375 regnum
= SPARC_F0_REGNUM
+ 2 * (regnum
- SPARC32_D0_REGNUM
);
376 regcache_raw_write (regcache
, regnum
, buf
);
377 regcache_raw_write (regcache
, regnum
+ 1, buf
+ 4);
382 sparc32_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
383 CORE_ADDR funcaddr
, int using_gcc
,
384 struct value
**args
, int nargs
,
385 struct type
*value_type
,
386 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
)
391 if (using_struct_return (value_type
, using_gcc
))
395 /* This is an UNIMP instruction. */
396 store_unsigned_integer (buf
, 4, TYPE_LENGTH (value_type
) & 0x1fff);
397 write_memory (sp
- 8, buf
, 4);
405 sparc32_store_arguments (struct regcache
*regcache
, int nargs
,
406 struct value
**args
, CORE_ADDR sp
,
407 int struct_return
, CORE_ADDR struct_addr
)
409 /* Number of words in the "parameter array". */
410 int num_elements
= 0;
414 for (i
= 0; i
< nargs
; i
++)
416 struct type
*type
= value_type (args
[i
]);
417 int len
= TYPE_LENGTH (type
);
419 if (sparc_structure_or_union_p (type
)
420 || (sparc_floating_p (type
) && len
== 16))
422 /* Structure, Union and Quad-Precision Arguments. */
425 /* Use doubleword alignment for these values. That's always
426 correct, and wasting a few bytes shouldn't be a problem. */
429 write_memory (sp
, value_contents (args
[i
]), len
);
430 args
[i
] = value_from_pointer (lookup_pointer_type (type
), sp
);
433 else if (sparc_floating_p (type
))
435 /* Floating arguments. */
436 gdb_assert (len
== 4 || len
== 8);
437 num_elements
+= (len
/ 4);
441 /* Integral and pointer arguments. */
442 gdb_assert (sparc_integral_or_pointer_p (type
));
445 args
[i
] = value_cast (builtin_type_int32
, args
[i
]);
446 num_elements
+= ((len
+ 3) / 4);
450 /* Always allocate at least six words. */
451 sp
-= max (6, num_elements
) * 4;
453 /* The psABI says that "Software convention requires space for the
454 struct/union return value pointer, even if the word is unused." */
457 /* The psABI says that "Although software convention and the
458 operating system require every stack frame to be doubleword
462 for (i
= 0; i
< nargs
; i
++)
464 const bfd_byte
*valbuf
= value_contents (args
[i
]);
465 struct type
*type
= value_type (args
[i
]);
466 int len
= TYPE_LENGTH (type
);
468 gdb_assert (len
== 4 || len
== 8);
472 int regnum
= SPARC_O0_REGNUM
+ element
;
474 regcache_cooked_write (regcache
, regnum
, valbuf
);
475 if (len
> 4 && element
< 5)
476 regcache_cooked_write (regcache
, regnum
+ 1, valbuf
+ 4);
479 /* Always store the argument in memory. */
480 write_memory (sp
+ 4 + element
* 4, valbuf
, len
);
484 gdb_assert (element
== num_elements
);
490 store_unsigned_integer (buf
, 4, struct_addr
);
491 write_memory (sp
, buf
, 4);
498 sparc32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
499 struct regcache
*regcache
, CORE_ADDR bp_addr
,
500 int nargs
, struct value
**args
, CORE_ADDR sp
,
501 int struct_return
, CORE_ADDR struct_addr
)
503 CORE_ADDR call_pc
= (struct_return
? (bp_addr
- 12) : (bp_addr
- 8));
505 /* Set return address. */
506 regcache_cooked_write_unsigned (regcache
, SPARC_O7_REGNUM
, call_pc
);
508 /* Set up function arguments. */
509 sp
= sparc32_store_arguments (regcache
, nargs
, args
, sp
,
510 struct_return
, struct_addr
);
512 /* Allocate the 16-word window save area. */
515 /* Stack should be doubleword aligned at this point. */
516 gdb_assert (sp
% 8 == 0);
518 /* Finally, update the stack pointer. */
519 regcache_cooked_write_unsigned (regcache
, SPARC_SP_REGNUM
, sp
);
525 /* Use the program counter to determine the contents and size of a
526 breakpoint instruction. Return a pointer to a string of bytes that
527 encode a breakpoint instruction, store the length of the string in
528 *LEN and optionally adjust *PC to point to the correct memory
529 location for inserting the breakpoint. */
531 static const gdb_byte
*
532 sparc_breakpoint_from_pc (CORE_ADDR
*pc
, int *len
)
534 static const gdb_byte break_insn
[] = { 0x91, 0xd0, 0x20, 0x01 };
536 *len
= sizeof (break_insn
);
541 /* Allocate and initialize a frame cache. */
543 static struct sparc_frame_cache
*
544 sparc_alloc_frame_cache (void)
546 struct sparc_frame_cache
*cache
;
549 cache
= FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache
);
555 /* Frameless until proven otherwise. */
556 cache
->frameless_p
= 1;
558 cache
->struct_return_p
= 0;
563 /* GCC generates several well-known sequences of instructions at the begining
564 of each function prologue when compiling with -fstack-check. If one of
565 such sequences starts at START_PC, then return the address of the
566 instruction immediately past this sequence. Otherwise, return START_PC. */
569 sparc_skip_stack_check (const CORE_ADDR start_pc
)
571 CORE_ADDR pc
= start_pc
;
573 int offset_stack_checking_sequence
= 0;
575 /* With GCC, all stack checking sequences begin with the same two
578 /* sethi <some immediate>,%g1 */
579 insn
= sparc_fetch_instruction (pc
);
581 if (!(X_OP (insn
) == 0 && X_OP2 (insn
) == 0x4 && X_RD (insn
) == 1))
584 /* sub %sp, %g1, %g1 */
585 insn
= sparc_fetch_instruction (pc
);
587 if (!(X_OP (insn
) == 2 && X_OP3 (insn
) == 0x4 && !X_I(insn
)
588 && X_RD (insn
) == 1 && X_RS1 (insn
) == 14 && X_RS2 (insn
) == 1))
591 insn
= sparc_fetch_instruction (pc
);
594 /* First possible sequence:
595 [first two instructions above]
596 clr [%g1 - some immediate] */
598 /* clr [%g1 - some immediate] */
599 if (X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && X_I(insn
)
600 && X_RS1 (insn
) == 1 && X_RD (insn
) == 0)
602 /* Valid stack-check sequence, return the new PC. */
606 /* Second possible sequence: A small number of probes.
607 [first two instructions above]
609 add %g1, -<some immediate>, %g1
611 [repeat the two instructions above any (small) number of times]
612 clr [%g1 - some immediate] */
615 else if (X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && !X_I(insn
)
616 && X_RS1 (insn
) == 1 && X_RD (insn
) == 0)
620 /* add %g1, -<some immediate>, %g1 */
621 insn
= sparc_fetch_instruction (pc
);
623 if (!(X_OP (insn
) == 2 && X_OP3(insn
) == 0 && X_I(insn
)
624 && X_RS1 (insn
) == 1 && X_RD (insn
) == 1))
628 insn
= sparc_fetch_instruction (pc
);
630 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && !X_I(insn
)
631 && X_RD (insn
) == 0 && X_RS1 (insn
) == 1))
635 /* clr [%g1 - some immediate] */
636 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && X_I(insn
)
637 && X_RS1 (insn
) == 1 && X_RD (insn
) == 0))
640 /* We found a valid stack-check sequence, return the new PC. */
644 /* Third sequence: A probing loop.
645 [first two instructions above]
646 sethi <some immediate>, %g4
650 add %g1, -<some immediate>, %g1
653 clr [%g4 - some immediate] */
655 /* sethi <some immediate>, %g4 */
656 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 0x4 && X_RD (insn
) == 4)
658 /* sub %g1, %g4, %g4 */
659 insn
= sparc_fetch_instruction (pc
);
661 if (!(X_OP (insn
) == 2 && X_OP3 (insn
) == 0x4 && !X_I(insn
)
662 && X_RD (insn
) == 4 && X_RS1 (insn
) == 1 && X_RS2 (insn
) == 4))
666 insn
= sparc_fetch_instruction (pc
);
668 if (!(X_OP (insn
) == 2 && X_OP3 (insn
) == 0x14 && !X_I(insn
)
669 && X_RD (insn
) == 0 && X_RS1 (insn
) == 1 && X_RS2 (insn
) == 4))
673 insn
= sparc_fetch_instruction (pc
);
675 if (!(X_OP (insn
) == 0 && X_COND (insn
) == 0x1))
678 /* add %g1, -<some immediate>, %g1 */
679 insn
= sparc_fetch_instruction (pc
);
681 if (!(X_OP (insn
) == 2 && X_OP3(insn
) == 0 && X_I(insn
)
682 && X_RS1 (insn
) == 1 && X_RD (insn
) == 1))
686 insn
= sparc_fetch_instruction (pc
);
688 if (!(X_OP (insn
) == 0 && X_COND (insn
) == 0x8))
692 insn
= sparc_fetch_instruction (pc
);
694 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && !X_I(insn
)
695 && X_RD (insn
) == 0 && X_RS1 (insn
) == 1))
698 /* clr [%g4 - some immediate] */
699 insn
= sparc_fetch_instruction (pc
);
701 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && X_I(insn
)
702 && X_RS1 (insn
) == 4 && X_RD (insn
) == 0))
705 /* We found a valid stack-check sequence, return the new PC. */
709 /* No stack check code in our prologue, return the start_pc. */
714 sparc_analyze_prologue (CORE_ADDR pc
, CORE_ADDR current_pc
,
715 struct sparc_frame_cache
*cache
)
717 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
722 pc
= sparc_skip_stack_check (pc
);
724 if (current_pc
<= pc
)
727 /* We have to handle to "Procedure Linkage Table" (PLT) special. On
728 SPARC the linker usually defines a symbol (typically
729 _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section.
730 This symbol makes us end up here with PC pointing at the start of
731 the PLT and CURRENT_PC probably pointing at a PLT entry. If we
732 would do our normal prologue analysis, we would probably conclude
733 that we've got a frame when in reality we don't, since the
734 dynamic linker patches up the first PLT with some code that
735 starts with a SAVE instruction. Patch up PC such that it points
736 at the start of our PLT entry. */
737 if (tdep
->plt_entry_size
> 0 && in_plt_section (current_pc
, NULL
))
738 pc
= current_pc
- ((current_pc
- pc
) % tdep
->plt_entry_size
);
740 insn
= sparc_fetch_instruction (pc
);
742 /* Recognize a SETHI insn and record its destination. */
743 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 0x04)
748 insn
= sparc_fetch_instruction (pc
+ 4);
751 /* Allow for an arithmetic operation on DEST or %g1. */
752 if (X_OP (insn
) == 2 && X_I (insn
)
753 && (X_RD (insn
) == 1 || X_RD (insn
) == dest
))
757 insn
= sparc_fetch_instruction (pc
+ 8);
760 /* Check for the SAVE instruction that sets up the frame. */
761 if (X_OP (insn
) == 2 && X_OP3 (insn
) == 0x3c)
763 cache
->frameless_p
= 0;
764 return pc
+ offset
+ 4;
771 sparc_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
773 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
774 return frame_unwind_register_unsigned (next_frame
, tdep
->pc_regnum
);
777 /* Return PC of first real instruction of the function starting at
781 sparc32_skip_prologue (CORE_ADDR start_pc
)
783 struct symtab_and_line sal
;
784 CORE_ADDR func_start
, func_end
;
785 struct sparc_frame_cache cache
;
787 /* This is the preferred method, find the end of the prologue by
788 using the debugging information. */
789 if (find_pc_partial_function (start_pc
, NULL
, &func_start
, &func_end
))
791 sal
= find_pc_line (func_start
, 0);
793 if (sal
.end
< func_end
794 && start_pc
<= sal
.end
)
798 start_pc
= sparc_analyze_prologue (start_pc
, 0xffffffffUL
, &cache
);
800 /* The psABI says that "Although the first 6 words of arguments
801 reside in registers, the standard stack frame reserves space for
802 them.". It also suggests that a function may use that space to
803 "write incoming arguments 0 to 5" into that space, and that's
804 indeed what GCC seems to be doing. In that case GCC will
805 generate debug information that points to the stack slots instead
806 of the registers, so we should consider the instructions that
807 write out these incoming arguments onto the stack. Of course we
808 only need to do this if we have a stack frame. */
810 while (!cache
.frameless_p
)
812 unsigned long insn
= sparc_fetch_instruction (start_pc
);
814 /* Recognize instructions that store incoming arguments in
815 %i0...%i5 into the corresponding stack slot. */
816 if (X_OP (insn
) == 3 && (X_OP3 (insn
) & 0x3c) == 0x04 && X_I (insn
)
817 && (X_RD (insn
) >= 24 && X_RD (insn
) <= 29) && X_RS1 (insn
) == 30
818 && X_SIMM13 (insn
) == 68 + (X_RD (insn
) - 24) * 4)
832 struct sparc_frame_cache
*
833 sparc_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
835 struct sparc_frame_cache
*cache
;
840 cache
= sparc_alloc_frame_cache ();
843 cache
->pc
= frame_func_unwind (next_frame
, NORMAL_FRAME
);
845 sparc_analyze_prologue (cache
->pc
, frame_pc_unwind (next_frame
), cache
);
847 if (cache
->frameless_p
)
849 /* This function is frameless, so %fp (%i6) holds the frame
850 pointer for our calling frame. Use %sp (%o6) as this frame's
853 frame_unwind_register_unsigned (next_frame
, SPARC_SP_REGNUM
);
857 /* For normal frames, %fp (%i6) holds the frame pointer, the
858 base address for the current stack frame. */
860 frame_unwind_register_unsigned (next_frame
, SPARC_FP_REGNUM
);
870 sparc32_struct_return_from_sym (struct symbol
*sym
)
872 struct type
*type
= check_typedef (SYMBOL_TYPE (sym
));
873 enum type_code code
= TYPE_CODE (type
);
875 if (code
== TYPE_CODE_FUNC
|| code
== TYPE_CODE_METHOD
)
877 type
= check_typedef (TYPE_TARGET_TYPE (type
));
878 if (sparc_structure_or_union_p (type
)
879 || (sparc_floating_p (type
) && TYPE_LENGTH (type
) == 16))
886 struct sparc_frame_cache
*
887 sparc32_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
889 struct sparc_frame_cache
*cache
;
895 cache
= sparc_frame_cache (next_frame
, this_cache
);
897 sym
= find_pc_function (cache
->pc
);
900 cache
->struct_return_p
= sparc32_struct_return_from_sym (sym
);
904 /* There is no debugging information for this function to
905 help us determine whether this function returns a struct
906 or not. So we rely on another heuristic which is to check
907 the instruction at the return address and see if this is
908 an "unimp" instruction. If it is, then it is a struct-return
911 int regnum
= cache
->frameless_p
? SPARC_O7_REGNUM
: SPARC_I7_REGNUM
;
913 pc
= frame_unwind_register_unsigned (next_frame
, regnum
) + 8;
914 if (sparc_is_unimp_insn (pc
))
915 cache
->struct_return_p
= 1;
922 sparc32_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
923 struct frame_id
*this_id
)
925 struct sparc_frame_cache
*cache
=
926 sparc32_frame_cache (next_frame
, this_cache
);
928 /* This marks the outermost frame. */
929 if (cache
->base
== 0)
932 (*this_id
) = frame_id_build (cache
->base
, cache
->pc
);
936 sparc32_frame_prev_register (struct frame_info
*next_frame
, void **this_cache
,
937 int regnum
, int *optimizedp
,
938 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
939 int *realnump
, gdb_byte
*valuep
)
941 struct sparc_frame_cache
*cache
=
942 sparc32_frame_cache (next_frame
, this_cache
);
944 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== SPARC32_NPC_REGNUM
)
952 CORE_ADDR pc
= (regnum
== SPARC32_NPC_REGNUM
) ? 4 : 0;
954 /* If this functions has a Structure, Union or
955 Quad-Precision return value, we have to skip the UNIMP
956 instruction that encodes the size of the structure. */
957 if (cache
->struct_return_p
)
960 regnum
= cache
->frameless_p
? SPARC_O7_REGNUM
: SPARC_I7_REGNUM
;
961 pc
+= frame_unwind_register_unsigned (next_frame
, regnum
) + 8;
962 store_unsigned_integer (valuep
, 4, pc
);
967 /* Handle StackGhost. */
969 ULONGEST wcookie
= sparc_fetch_wcookie ();
971 if (wcookie
!= 0 && !cache
->frameless_p
&& regnum
== SPARC_I7_REGNUM
)
979 CORE_ADDR addr
= cache
->base
+ (regnum
- SPARC_L0_REGNUM
) * 4;
982 /* Read the value in from memory. */
983 i7
= get_frame_memory_unsigned (next_frame
, addr
, 4);
984 store_unsigned_integer (valuep
, 4, i7
^ wcookie
);
990 /* The previous frame's `local' and `in' registers have been saved
991 in the register save area. */
992 if (!cache
->frameless_p
993 && regnum
>= SPARC_L0_REGNUM
&& regnum
<= SPARC_I7_REGNUM
)
996 *lvalp
= lval_memory
;
997 *addrp
= cache
->base
+ (regnum
- SPARC_L0_REGNUM
) * 4;
1001 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
1003 /* Read the value in from memory. */
1004 read_memory (*addrp
, valuep
, register_size (gdbarch
, regnum
));
1009 /* The previous frame's `out' registers are accessable as the
1010 current frame's `in' registers. */
1011 if (!cache
->frameless_p
1012 && regnum
>= SPARC_O0_REGNUM
&& regnum
<= SPARC_O7_REGNUM
)
1013 regnum
+= (SPARC_I0_REGNUM
- SPARC_O0_REGNUM
);
1016 *lvalp
= lval_register
;
1020 frame_unwind_register (next_frame
, (*realnump
), valuep
);
1023 static const struct frame_unwind sparc32_frame_unwind
=
1026 sparc32_frame_this_id
,
1027 sparc32_frame_prev_register
1030 static const struct frame_unwind
*
1031 sparc32_frame_sniffer (struct frame_info
*next_frame
)
1033 return &sparc32_frame_unwind
;
1038 sparc32_frame_base_address (struct frame_info
*next_frame
, void **this_cache
)
1040 struct sparc_frame_cache
*cache
=
1041 sparc32_frame_cache (next_frame
, this_cache
);
1046 static const struct frame_base sparc32_frame_base
=
1048 &sparc32_frame_unwind
,
1049 sparc32_frame_base_address
,
1050 sparc32_frame_base_address
,
1051 sparc32_frame_base_address
1054 static struct frame_id
1055 sparc_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1059 sp
= frame_unwind_register_unsigned (next_frame
, SPARC_SP_REGNUM
);
1062 return frame_id_build (sp
, frame_pc_unwind (next_frame
));
1066 /* Extract from an array REGBUF containing the (raw) register state, a
1067 function return value of TYPE, and copy that into VALBUF. */
1070 sparc32_extract_return_value (struct type
*type
, struct regcache
*regcache
,
1073 int len
= TYPE_LENGTH (type
);
1076 gdb_assert (!sparc_structure_or_union_p (type
));
1077 gdb_assert (!(sparc_floating_p (type
) && len
== 16));
1079 if (sparc_floating_p (type
))
1081 /* Floating return values. */
1082 regcache_cooked_read (regcache
, SPARC_F0_REGNUM
, buf
);
1084 regcache_cooked_read (regcache
, SPARC_F1_REGNUM
, buf
+ 4);
1085 memcpy (valbuf
, buf
, len
);
1089 /* Integral and pointer return values. */
1090 gdb_assert (sparc_integral_or_pointer_p (type
));
1092 regcache_cooked_read (regcache
, SPARC_O0_REGNUM
, buf
);
1095 regcache_cooked_read (regcache
, SPARC_O1_REGNUM
, buf
+ 4);
1096 gdb_assert (len
== 8);
1097 memcpy (valbuf
, buf
, 8);
1101 /* Just stripping off any unused bytes should preserve the
1102 signed-ness just fine. */
1103 memcpy (valbuf
, buf
+ 4 - len
, len
);
1108 /* Write into the appropriate registers a function return value stored
1109 in VALBUF of type TYPE. */
1112 sparc32_store_return_value (struct type
*type
, struct regcache
*regcache
,
1113 const gdb_byte
*valbuf
)
1115 int len
= TYPE_LENGTH (type
);
1118 gdb_assert (!sparc_structure_or_union_p (type
));
1119 gdb_assert (!(sparc_floating_p (type
) && len
== 16));
1121 if (sparc_floating_p (type
))
1123 /* Floating return values. */
1124 memcpy (buf
, valbuf
, len
);
1125 regcache_cooked_write (regcache
, SPARC_F0_REGNUM
, buf
);
1127 regcache_cooked_write (regcache
, SPARC_F1_REGNUM
, buf
+ 4);
1131 /* Integral and pointer return values. */
1132 gdb_assert (sparc_integral_or_pointer_p (type
));
1136 gdb_assert (len
== 8);
1137 memcpy (buf
, valbuf
, 8);
1138 regcache_cooked_write (regcache
, SPARC_O1_REGNUM
, buf
+ 4);
1142 /* ??? Do we need to do any sign-extension here? */
1143 memcpy (buf
+ 4 - len
, valbuf
, len
);
1145 regcache_cooked_write (regcache
, SPARC_O0_REGNUM
, buf
);
1149 static enum return_value_convention
1150 sparc32_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
1151 struct regcache
*regcache
, gdb_byte
*readbuf
,
1152 const gdb_byte
*writebuf
)
1154 /* The psABI says that "...every stack frame reserves the word at
1155 %fp+64. If a function returns a structure, union, or
1156 quad-precision value, this word should hold the address of the
1157 object into which the return value should be copied." This
1158 guarantees that we can always find the return value, not just
1159 before the function returns. */
1161 if (sparc_structure_or_union_p (type
)
1162 || (sparc_floating_p (type
) && TYPE_LENGTH (type
) == 16))
1169 regcache_cooked_read_unsigned (regcache
, SPARC_SP_REGNUM
, &sp
);
1170 addr
= read_memory_unsigned_integer (sp
+ 64, 4);
1171 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
1174 return RETURN_VALUE_ABI_PRESERVES_ADDRESS
;
1178 sparc32_extract_return_value (type
, regcache
, readbuf
);
1180 sparc32_store_return_value (type
, regcache
, writebuf
);
1182 return RETURN_VALUE_REGISTER_CONVENTION
;
1186 sparc32_stabs_argument_has_addr (struct gdbarch
*gdbarch
, struct type
*type
)
1188 return (sparc_structure_or_union_p (type
)
1189 || (sparc_floating_p (type
) && TYPE_LENGTH (type
) == 16));
1193 sparc32_dwarf2_struct_return_p (struct frame_info
*next_frame
)
1195 CORE_ADDR pc
= frame_unwind_address_in_block (next_frame
, NORMAL_FRAME
);
1196 struct symbol
*sym
= find_pc_function (pc
);
1199 return sparc32_struct_return_from_sym (sym
);
1204 sparc32_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1205 struct dwarf2_frame_state_reg
*reg
,
1206 struct frame_info
*next_frame
)
1212 case SPARC_G0_REGNUM
:
1213 /* Since %g0 is always zero, there is no point in saving it, and
1214 people will be inclined omit it from the CFI. Make sure we
1215 don't warn about that. */
1216 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
1218 case SPARC_SP_REGNUM
:
1219 reg
->how
= DWARF2_FRAME_REG_CFA
;
1221 case SPARC32_PC_REGNUM
:
1222 case SPARC32_NPC_REGNUM
:
1223 reg
->how
= DWARF2_FRAME_REG_RA_OFFSET
;
1225 if (sparc32_dwarf2_struct_return_p (next_frame
))
1227 if (regnum
== SPARC32_NPC_REGNUM
)
1229 reg
->loc
.offset
= off
;
1235 /* The SPARC Architecture doesn't have hardware single-step support,
1236 and most operating systems don't implement it either, so we provide
1237 software single-step mechanism. */
1240 sparc_analyze_control_transfer (struct frame_info
*frame
,
1241 CORE_ADDR pc
, CORE_ADDR
*npc
)
1243 unsigned long insn
= sparc_fetch_instruction (pc
);
1244 int conditional_p
= X_COND (insn
) & 0x7;
1246 long offset
= 0; /* Must be signed for sign-extend. */
1248 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 3 && (insn
& 0x1000000) == 0)
1250 /* Branch on Integer Register with Prediction (BPr). */
1254 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 6)
1256 /* Branch on Floating-Point Condition Codes (FBfcc). */
1258 offset
= 4 * X_DISP22 (insn
);
1260 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 5)
1262 /* Branch on Floating-Point Condition Codes with Prediction
1265 offset
= 4 * X_DISP19 (insn
);
1267 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 2)
1269 /* Branch on Integer Condition Codes (Bicc). */
1271 offset
= 4 * X_DISP22 (insn
);
1273 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 1)
1275 /* Branch on Integer Condition Codes with Prediction (BPcc). */
1277 offset
= 4 * X_DISP19 (insn
);
1279 else if (X_OP (insn
) == 2 && X_OP3 (insn
) == 0x3a)
1281 /* Trap instruction (TRAP). */
1282 return gdbarch_tdep (get_frame_arch (frame
))->step_trap (frame
, insn
);
1285 /* FIXME: Handle DONE and RETRY instructions. */
1291 /* For conditional branches, return nPC + 4 iff the annul
1293 return (X_A (insn
) ? *npc
+ 4 : 0);
1297 /* For unconditional branches, return the target if its
1298 specified condition is "always" and return nPC + 4 if the
1299 condition is "never". If the annul bit is 1, set *NPC to
1301 if (X_COND (insn
) == 0x0)
1302 pc
= *npc
, offset
= 4;
1306 gdb_assert (offset
!= 0);
1315 sparc_step_trap (struct frame_info
*frame
, unsigned long insn
)
1321 sparc_software_single_step (struct frame_info
*frame
)
1323 struct gdbarch
*arch
= get_frame_arch (frame
);
1324 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
1325 CORE_ADDR npc
, nnpc
;
1327 CORE_ADDR pc
, orig_npc
;
1329 pc
= get_frame_register_unsigned (frame
, tdep
->pc_regnum
);
1330 orig_npc
= npc
= get_frame_register_unsigned (frame
, tdep
->npc_regnum
);
1332 /* Analyze the instruction at PC. */
1333 nnpc
= sparc_analyze_control_transfer (frame
, pc
, &npc
);
1335 insert_single_step_breakpoint (npc
);
1338 insert_single_step_breakpoint (nnpc
);
1340 /* Assert that we have set at least one breakpoint, and that
1341 they're not set at the same spot - unless we're going
1342 from here straight to NULL, i.e. a call or jump to 0. */
1343 gdb_assert (npc
!= 0 || nnpc
!= 0 || orig_npc
== 0);
1344 gdb_assert (nnpc
!= npc
|| orig_npc
== 0);
1350 sparc_write_pc (CORE_ADDR pc
, ptid_t ptid
)
1352 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1354 write_register_pid (tdep
->pc_regnum
, pc
, ptid
);
1355 write_register_pid (tdep
->npc_regnum
, pc
+ 4, ptid
);
1358 /* Unglobalize NAME. */
1361 sparc_stabs_unglobalize_name (char *name
)
1363 /* The Sun compilers (Sun ONE Studio, Forte Developer, Sun WorkShop,
1364 SunPRO) convert file static variables into global values, a
1365 process known as globalization. In order to do this, the
1366 compiler will create a unique prefix and prepend it to each file
1367 static variable. For static variables within a function, this
1368 globalization prefix is followed by the function name (nested
1369 static variables within a function are supposed to generate a
1370 warning message, and are left alone). The procedure is
1371 documented in the Stabs Interface Manual, which is distrubuted
1372 with the compilers, although version 4.0 of the manual seems to
1373 be incorrect in some places, at least for SPARC. The
1374 globalization prefix is encoded into an N_OPT stab, with the form
1375 "G=<prefix>". The globalization prefix always seems to start
1376 with a dollar sign '$'; a dot '.' is used as a seperator. So we
1377 simply strip everything up until the last dot. */
1381 char *p
= strrchr (name
, '.');
1390 /* Return the appropriate register set for the core section identified
1391 by SECT_NAME and SECT_SIZE. */
1393 const struct regset
*
1394 sparc_regset_from_core_section (struct gdbarch
*gdbarch
,
1395 const char *sect_name
, size_t sect_size
)
1397 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1399 if (strcmp (sect_name
, ".reg") == 0 && sect_size
>= tdep
->sizeof_gregset
)
1400 return tdep
->gregset
;
1402 if (strcmp (sect_name
, ".reg2") == 0 && sect_size
>= tdep
->sizeof_fpregset
)
1403 return tdep
->fpregset
;
1409 static struct gdbarch
*
1410 sparc32_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1412 struct gdbarch_tdep
*tdep
;
1413 struct gdbarch
*gdbarch
;
1415 /* If there is already a candidate, use it. */
1416 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
1418 return arches
->gdbarch
;
1420 /* Allocate space for the new architecture. */
1421 tdep
= XMALLOC (struct gdbarch_tdep
);
1422 gdbarch
= gdbarch_alloc (&info
, tdep
);
1424 tdep
->pc_regnum
= SPARC32_PC_REGNUM
;
1425 tdep
->npc_regnum
= SPARC32_NPC_REGNUM
;
1426 tdep
->gregset
= NULL
;
1427 tdep
->sizeof_gregset
= 0;
1428 tdep
->fpregset
= NULL
;
1429 tdep
->sizeof_fpregset
= 0;
1430 tdep
->plt_entry_size
= 0;
1431 tdep
->step_trap
= sparc_step_trap
;
1433 set_gdbarch_long_double_bit (gdbarch
, 128);
1434 set_gdbarch_long_double_format (gdbarch
, floatformats_sparc_quad
);
1436 set_gdbarch_num_regs (gdbarch
, SPARC32_NUM_REGS
);
1437 set_gdbarch_register_name (gdbarch
, sparc32_register_name
);
1438 set_gdbarch_register_type (gdbarch
, sparc32_register_type
);
1439 set_gdbarch_num_pseudo_regs (gdbarch
, SPARC32_NUM_PSEUDO_REGS
);
1440 set_gdbarch_pseudo_register_read (gdbarch
, sparc32_pseudo_register_read
);
1441 set_gdbarch_pseudo_register_write (gdbarch
, sparc32_pseudo_register_write
);
1443 /* Register numbers of various important registers. */
1444 set_gdbarch_sp_regnum (gdbarch
, SPARC_SP_REGNUM
); /* %sp */
1445 set_gdbarch_pc_regnum (gdbarch
, SPARC32_PC_REGNUM
); /* %pc */
1446 set_gdbarch_fp0_regnum (gdbarch
, SPARC_F0_REGNUM
); /* %f0 */
1448 /* Call dummy code. */
1449 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
1450 set_gdbarch_push_dummy_code (gdbarch
, sparc32_push_dummy_code
);
1451 set_gdbarch_push_dummy_call (gdbarch
, sparc32_push_dummy_call
);
1453 set_gdbarch_return_value (gdbarch
, sparc32_return_value
);
1454 set_gdbarch_stabs_argument_has_addr
1455 (gdbarch
, sparc32_stabs_argument_has_addr
);
1457 set_gdbarch_skip_prologue (gdbarch
, sparc32_skip_prologue
);
1459 /* Stack grows downward. */
1460 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
1462 set_gdbarch_breakpoint_from_pc (gdbarch
, sparc_breakpoint_from_pc
);
1464 set_gdbarch_frame_args_skip (gdbarch
, 8);
1466 set_gdbarch_print_insn (gdbarch
, print_insn_sparc
);
1468 set_gdbarch_software_single_step (gdbarch
, sparc_software_single_step
);
1469 set_gdbarch_write_pc (gdbarch
, sparc_write_pc
);
1471 set_gdbarch_unwind_dummy_id (gdbarch
, sparc_unwind_dummy_id
);
1473 set_gdbarch_unwind_pc (gdbarch
, sparc_unwind_pc
);
1475 frame_base_set_default (gdbarch
, &sparc32_frame_base
);
1477 /* Hook in the DWARF CFI frame unwinder. */
1478 dwarf2_frame_set_init_reg (gdbarch
, sparc32_dwarf2_frame_init_reg
);
1479 /* FIXME: kettenis/20050423: Don't enable the unwinder until the
1480 StackGhost issues have been resolved. */
1482 /* Hook in ABI-specific overrides, if they have been registered. */
1483 gdbarch_init_osabi (info
, gdbarch
);
1485 frame_unwind_append_sniffer (gdbarch
, sparc32_frame_sniffer
);
1487 /* If we have register sets, enable the generic core file support. */
1489 set_gdbarch_regset_from_core_section (gdbarch
,
1490 sparc_regset_from_core_section
);
1495 /* Helper functions for dealing with register windows. */
1498 sparc_supply_rwindow (struct regcache
*regcache
, CORE_ADDR sp
, int regnum
)
1506 /* Registers are 64-bit. */
1509 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1511 if (regnum
== i
|| regnum
== -1)
1513 target_read_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 8), buf
, 8);
1515 /* Handle StackGhost. */
1516 if (i
== SPARC_I7_REGNUM
)
1518 ULONGEST wcookie
= sparc_fetch_wcookie ();
1519 ULONGEST i7
= extract_unsigned_integer (buf
+ offset
, 8);
1521 store_unsigned_integer (buf
+ offset
, 8, i7
^ wcookie
);
1524 regcache_raw_supply (regcache
, i
, buf
);
1530 /* Registers are 32-bit. Toss any sign-extension of the stack
1534 /* Clear out the top half of the temporary buffer, and put the
1535 register value in the bottom half if we're in 64-bit mode. */
1536 if (gdbarch_ptr_bit (current_gdbarch
) == 64)
1542 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1544 if (regnum
== i
|| regnum
== -1)
1546 target_read_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 4),
1549 /* Handle StackGhost. */
1550 if (i
== SPARC_I7_REGNUM
)
1552 ULONGEST wcookie
= sparc_fetch_wcookie ();
1553 ULONGEST i7
= extract_unsigned_integer (buf
+ offset
, 4);
1555 store_unsigned_integer (buf
+ offset
, 4, i7
^ wcookie
);
1558 regcache_raw_supply (regcache
, i
, buf
);
1565 sparc_collect_rwindow (const struct regcache
*regcache
,
1566 CORE_ADDR sp
, int regnum
)
1574 /* Registers are 64-bit. */
1577 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1579 if (regnum
== -1 || regnum
== SPARC_SP_REGNUM
|| regnum
== i
)
1581 regcache_raw_collect (regcache
, i
, buf
);
1583 /* Handle StackGhost. */
1584 if (i
== SPARC_I7_REGNUM
)
1586 ULONGEST wcookie
= sparc_fetch_wcookie ();
1587 ULONGEST i7
= extract_unsigned_integer (buf
+ offset
, 8);
1589 store_unsigned_integer (buf
, 8, i7
^ wcookie
);
1592 target_write_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 8), buf
, 8);
1598 /* Registers are 32-bit. Toss any sign-extension of the stack
1602 /* Only use the bottom half if we're in 64-bit mode. */
1603 if (gdbarch_ptr_bit (current_gdbarch
) == 64)
1606 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1608 if (regnum
== -1 || regnum
== SPARC_SP_REGNUM
|| regnum
== i
)
1610 regcache_raw_collect (regcache
, i
, buf
);
1612 /* Handle StackGhost. */
1613 if (i
== SPARC_I7_REGNUM
)
1615 ULONGEST wcookie
= sparc_fetch_wcookie ();
1616 ULONGEST i7
= extract_unsigned_integer (buf
+ offset
, 4);
1618 store_unsigned_integer (buf
+ offset
, 4, i7
^ wcookie
);
1621 target_write_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 4),
1628 /* Helper functions for dealing with register sets. */
1631 sparc32_supply_gregset (const struct sparc_gregset
*gregset
,
1632 struct regcache
*regcache
,
1633 int regnum
, const void *gregs
)
1635 const gdb_byte
*regs
= gregs
;
1638 if (regnum
== SPARC32_PSR_REGNUM
|| regnum
== -1)
1639 regcache_raw_supply (regcache
, SPARC32_PSR_REGNUM
,
1640 regs
+ gregset
->r_psr_offset
);
1642 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== -1)
1643 regcache_raw_supply (regcache
, SPARC32_PC_REGNUM
,
1644 regs
+ gregset
->r_pc_offset
);
1646 if (regnum
== SPARC32_NPC_REGNUM
|| regnum
== -1)
1647 regcache_raw_supply (regcache
, SPARC32_NPC_REGNUM
,
1648 regs
+ gregset
->r_npc_offset
);
1650 if (regnum
== SPARC32_Y_REGNUM
|| regnum
== -1)
1651 regcache_raw_supply (regcache
, SPARC32_Y_REGNUM
,
1652 regs
+ gregset
->r_y_offset
);
1654 if (regnum
== SPARC_G0_REGNUM
|| regnum
== -1)
1655 regcache_raw_supply (regcache
, SPARC_G0_REGNUM
, NULL
);
1657 if ((regnum
>= SPARC_G1_REGNUM
&& regnum
<= SPARC_O7_REGNUM
) || regnum
== -1)
1659 int offset
= gregset
->r_g1_offset
;
1661 for (i
= SPARC_G1_REGNUM
; i
<= SPARC_O7_REGNUM
; i
++)
1663 if (regnum
== i
|| regnum
== -1)
1664 regcache_raw_supply (regcache
, i
, regs
+ offset
);
1669 if ((regnum
>= SPARC_L0_REGNUM
&& regnum
<= SPARC_I7_REGNUM
) || regnum
== -1)
1671 /* Not all of the register set variants include Locals and
1672 Inputs. For those that don't, we read them off the stack. */
1673 if (gregset
->r_l0_offset
== -1)
1677 regcache_cooked_read_unsigned (regcache
, SPARC_SP_REGNUM
, &sp
);
1678 sparc_supply_rwindow (regcache
, sp
, regnum
);
1682 int offset
= gregset
->r_l0_offset
;
1684 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1686 if (regnum
== i
|| regnum
== -1)
1687 regcache_raw_supply (regcache
, i
, regs
+ offset
);
1695 sparc32_collect_gregset (const struct sparc_gregset
*gregset
,
1696 const struct regcache
*regcache
,
1697 int regnum
, void *gregs
)
1699 gdb_byte
*regs
= gregs
;
1702 if (regnum
== SPARC32_PSR_REGNUM
|| regnum
== -1)
1703 regcache_raw_collect (regcache
, SPARC32_PSR_REGNUM
,
1704 regs
+ gregset
->r_psr_offset
);
1706 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== -1)
1707 regcache_raw_collect (regcache
, SPARC32_PC_REGNUM
,
1708 regs
+ gregset
->r_pc_offset
);
1710 if (regnum
== SPARC32_NPC_REGNUM
|| regnum
== -1)
1711 regcache_raw_collect (regcache
, SPARC32_NPC_REGNUM
,
1712 regs
+ gregset
->r_npc_offset
);
1714 if (regnum
== SPARC32_Y_REGNUM
|| regnum
== -1)
1715 regcache_raw_collect (regcache
, SPARC32_Y_REGNUM
,
1716 regs
+ gregset
->r_y_offset
);
1718 if ((regnum
>= SPARC_G1_REGNUM
&& regnum
<= SPARC_O7_REGNUM
) || regnum
== -1)
1720 int offset
= gregset
->r_g1_offset
;
1722 /* %g0 is always zero. */
1723 for (i
= SPARC_G1_REGNUM
; i
<= SPARC_O7_REGNUM
; i
++)
1725 if (regnum
== i
|| regnum
== -1)
1726 regcache_raw_collect (regcache
, i
, regs
+ offset
);
1731 if ((regnum
>= SPARC_L0_REGNUM
&& regnum
<= SPARC_I7_REGNUM
) || regnum
== -1)
1733 /* Not all of the register set variants include Locals and
1734 Inputs. For those that don't, we read them off the stack. */
1735 if (gregset
->r_l0_offset
!= -1)
1737 int offset
= gregset
->r_l0_offset
;
1739 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1741 if (regnum
== i
|| regnum
== -1)
1742 regcache_raw_collect (regcache
, i
, regs
+ offset
);
1750 sparc32_supply_fpregset (struct regcache
*regcache
,
1751 int regnum
, const void *fpregs
)
1753 const gdb_byte
*regs
= fpregs
;
1756 for (i
= 0; i
< 32; i
++)
1758 if (regnum
== (SPARC_F0_REGNUM
+ i
) || regnum
== -1)
1759 regcache_raw_supply (regcache
, SPARC_F0_REGNUM
+ i
, regs
+ (i
* 4));
1762 if (regnum
== SPARC32_FSR_REGNUM
|| regnum
== -1)
1763 regcache_raw_supply (regcache
, SPARC32_FSR_REGNUM
, regs
+ (32 * 4) + 4);
1767 sparc32_collect_fpregset (const struct regcache
*regcache
,
1768 int regnum
, void *fpregs
)
1770 gdb_byte
*regs
= fpregs
;
1773 for (i
= 0; i
< 32; i
++)
1775 if (regnum
== (SPARC_F0_REGNUM
+ i
) || regnum
== -1)
1776 regcache_raw_collect (regcache
, SPARC_F0_REGNUM
+ i
, regs
+ (i
* 4));
1779 if (regnum
== SPARC32_FSR_REGNUM
|| regnum
== -1)
1780 regcache_raw_collect (regcache
, SPARC32_FSR_REGNUM
, regs
+ (32 * 4) + 4);
1786 /* From <machine/reg.h>. */
1787 const struct sparc_gregset sparc32_sunos4_gregset
=
1800 /* Provide a prototype to silence -Wmissing-prototypes. */
1801 void _initialize_sparc_tdep (void);
1804 _initialize_sparc_tdep (void)
1806 register_gdbarch_init (bfd_arch_sparc
, sparc32_gdbarch_init
);
1808 /* Initialize the SPARC-specific register types. */