1 /* Target-dependent code for SPARC.
3 Copyright (C) 2003-2017 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "arch-utils.h"
23 #include "dwarf2-frame.h"
24 #include "floatformat.h"
26 #include "frame-base.h"
27 #include "frame-unwind.h"
36 #include "target-descriptions.h"
39 #include "sparc-tdep.h"
40 #include "sparc-ravenscar-thread.h"
45 /* This file implements the SPARC 32-bit ABI as defined by the section
46 "Low-Level System Information" of the SPARC Compliance Definition
47 (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC. The SCD
48 lists changes with respect to the original 32-bit psABI as defined
49 in the "System V ABI, SPARC Processor Supplement".
51 Note that if we talk about SunOS, we mean SunOS 4.x, which was
52 BSD-based, which is sometimes (retroactively?) referred to as
53 Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and
54 above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9
55 suffering from severe version number inflation). Solaris 2.x is
56 also known as SunOS 5.x, since that's what uname(1) says. Solaris
59 /* Please use the sparc32_-prefix for 32-bit specific code, the
60 sparc64_-prefix for 64-bit specific code and the sparc_-prefix for
61 code that can handle both. The 64-bit specific code lives in
62 sparc64-tdep.c; don't add any here. */
64 /* The SPARC Floating-Point Quad-Precision format is similar to
65 big-endian IA-64 Quad-Precision format. */
66 #define floatformats_sparc_quad floatformats_ia64_quad
68 /* The stack pointer is offset from the stack frame by a BIAS of 2047
69 (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC
70 hosts, so undefine it first. */
74 /* Macros to extract fields from SPARC instructions. */
75 #define X_OP(i) (((i) >> 30) & 0x3)
76 #define X_RD(i) (((i) >> 25) & 0x1f)
77 #define X_A(i) (((i) >> 29) & 1)
78 #define X_COND(i) (((i) >> 25) & 0xf)
79 #define X_OP2(i) (((i) >> 22) & 0x7)
80 #define X_IMM22(i) ((i) & 0x3fffff)
81 #define X_OP3(i) (((i) >> 19) & 0x3f)
82 #define X_RS1(i) (((i) >> 14) & 0x1f)
83 #define X_RS2(i) ((i) & 0x1f)
84 #define X_I(i) (((i) >> 13) & 1)
85 /* Sign extension macros. */
86 #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000)
87 #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000)
88 #define X_DISP10(i) ((((((i) >> 11) && 0x300) | (((i) >> 5) & 0xff)) ^ 0x200) - 0x200)
89 #define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000)
90 /* Macros to identify some instructions. */
91 /* RETURN (RETT in V8) */
92 #define X_RETTURN(i) ((X_OP (i) == 0x2) && (X_OP3 (i) == 0x39))
94 /* Fetch the instruction at PC. Instructions are always big-endian
95 even if the processor operates in little-endian mode. */
98 sparc_fetch_instruction (CORE_ADDR pc
)
104 /* If we can't read the instruction at PC, return zero. */
105 if (target_read_memory (pc
, buf
, sizeof (buf
)))
109 for (i
= 0; i
< sizeof (buf
); i
++)
110 insn
= (insn
<< 8) | buf
[i
];
115 /* Return non-zero if the instruction corresponding to PC is an "unimp"
119 sparc_is_unimp_insn (CORE_ADDR pc
)
121 const unsigned long insn
= sparc_fetch_instruction (pc
);
123 return ((insn
& 0xc1c00000) == 0);
126 /* Return non-zero if the instruction corresponding to PC is an
127 "annulled" branch, i.e. the annul bit is set. */
130 sparc_is_annulled_branch_insn (CORE_ADDR pc
)
132 /* The branch instructions featuring an annul bit can be identified
133 by the following bit patterns:
136 OP2=1: Branch on Integer Condition Codes with Prediction (BPcc).
137 OP2=2: Branch on Integer Condition Codes (Bcc).
138 OP2=5: Branch on FP Condition Codes with Prediction (FBfcc).
139 OP2=6: Branch on FP Condition Codes (FBcc).
141 Branch on Integer Register with Prediction (BPr).
143 This leaves out ILLTRAP (OP2=0), SETHI/NOP (OP2=4) and the V8
144 coprocessor branch instructions (Op2=7). */
146 const unsigned long insn
= sparc_fetch_instruction (pc
);
147 const unsigned op2
= X_OP2 (insn
);
149 if ((X_OP (insn
) == 0)
150 && ((op2
== 1) || (op2
== 2) || (op2
== 5) || (op2
== 6)
151 || ((op2
== 3) && ((insn
& 0x10000000) == 0))))
157 /* OpenBSD/sparc includes StackGhost, which according to the author's
158 website http://stackghost.cerias.purdue.edu "... transparently and
159 automatically protects applications' stack frames; more
160 specifically, it guards the return pointers. The protection
161 mechanisms require no application source or binary modification and
162 imposes only a negligible performance penalty."
164 The same website provides the following description of how
167 "StackGhost interfaces with the kernel trap handler that would
168 normally write out registers to the stack and the handler that
169 would read them back in. By XORing a cookie into the
170 return-address saved in the user stack when it is actually written
171 to the stack, and then XOR it out when the return-address is pulled
172 from the stack, StackGhost can cause attacker corrupted return
173 pointers to behave in a manner the attacker cannot predict.
174 StackGhost can also use several unused bits in the return pointer
175 to detect a smashed return pointer and abort the process."
177 For GDB this means that whenever we're reading %i7 from a stack
178 frame's window save area, we'll have to XOR the cookie.
180 More information on StackGuard can be found on in:
182 Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated
183 Stack Protection." 2001. Published in USENIX Security Symposium
186 /* Fetch StackGhost Per-Process XOR cookie. */
189 sparc_fetch_wcookie (struct gdbarch
*gdbarch
)
191 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
192 struct target_ops
*ops
= ¤t_target
;
196 len
= target_read (ops
, TARGET_OBJECT_WCOOKIE
, NULL
, buf
, 0, 8);
200 /* We should have either an 32-bit or an 64-bit cookie. */
201 gdb_assert (len
== 4 || len
== 8);
203 return extract_unsigned_integer (buf
, len
, byte_order
);
207 /* The functions on this page are intended to be used to classify
208 function arguments. */
210 /* Check whether TYPE is "Integral or Pointer". */
213 sparc_integral_or_pointer_p (const struct type
*type
)
215 int len
= TYPE_LENGTH (type
);
217 switch (TYPE_CODE (type
))
223 case TYPE_CODE_RANGE
:
224 /* We have byte, half-word, word and extended-word/doubleword
225 integral types. The doubleword is an extension to the
226 original 32-bit ABI by the SCD 2.4.x. */
227 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
230 case TYPE_CODE_RVALUE_REF
:
231 /* Allow either 32-bit or 64-bit pointers. */
232 return (len
== 4 || len
== 8);
240 /* Check whether TYPE is "Floating". */
243 sparc_floating_p (const struct type
*type
)
245 switch (TYPE_CODE (type
))
249 int len
= TYPE_LENGTH (type
);
250 return (len
== 4 || len
== 8 || len
== 16);
259 /* Check whether TYPE is "Complex Floating". */
262 sparc_complex_floating_p (const struct type
*type
)
264 switch (TYPE_CODE (type
))
266 case TYPE_CODE_COMPLEX
:
268 int len
= TYPE_LENGTH (type
);
269 return (len
== 8 || len
== 16 || len
== 32);
278 /* Check whether TYPE is "Structure or Union".
280 In terms of Ada subprogram calls, arrays are treated the same as
281 struct and union types. So this function also returns non-zero
285 sparc_structure_or_union_p (const struct type
*type
)
287 switch (TYPE_CODE (type
))
289 case TYPE_CODE_STRUCT
:
290 case TYPE_CODE_UNION
:
291 case TYPE_CODE_ARRAY
:
300 /* Register information. */
301 #define SPARC32_FPU_REGISTERS \
302 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
303 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
304 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", \
305 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
306 #define SPARC32_CP0_REGISTERS \
307 "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr"
309 static const char *sparc_core_register_names
[] = { SPARC_CORE_REGISTERS
};
310 static const char *sparc32_fpu_register_names
[] = { SPARC32_FPU_REGISTERS
};
311 static const char *sparc32_cp0_register_names
[] = { SPARC32_CP0_REGISTERS
};
313 static const char *sparc32_register_names
[] =
315 SPARC_CORE_REGISTERS
,
316 SPARC32_FPU_REGISTERS
,
317 SPARC32_CP0_REGISTERS
320 /* Total number of registers. */
321 #define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names)
323 /* We provide the aliases %d0..%d30 for the floating registers as
324 "psuedo" registers. */
326 static const char *sparc32_pseudo_register_names
[] =
328 "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14",
329 "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30"
332 /* Total number of pseudo registers. */
333 #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names)
335 /* Return the name of pseudo register REGNUM. */
338 sparc32_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
340 regnum
-= gdbarch_num_regs (gdbarch
);
342 if (regnum
< SPARC32_NUM_PSEUDO_REGS
)
343 return sparc32_pseudo_register_names
[regnum
];
345 internal_error (__FILE__
, __LINE__
,
346 _("sparc32_pseudo_register_name: bad register number %d"),
350 /* Return the name of register REGNUM. */
353 sparc32_register_name (struct gdbarch
*gdbarch
, int regnum
)
355 if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
356 return tdesc_register_name (gdbarch
, regnum
);
358 if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
))
359 return sparc32_register_names
[regnum
];
361 return sparc32_pseudo_register_name (gdbarch
, regnum
);
364 /* Construct types for ISA-specific registers. */
367 sparc_psr_type (struct gdbarch
*gdbarch
)
369 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
371 if (!tdep
->sparc_psr_type
)
375 type
= arch_flags_type (gdbarch
, "builtin_type_sparc_psr", 4);
376 append_flags_type_flag (type
, 5, "ET");
377 append_flags_type_flag (type
, 6, "PS");
378 append_flags_type_flag (type
, 7, "S");
379 append_flags_type_flag (type
, 12, "EF");
380 append_flags_type_flag (type
, 13, "EC");
382 tdep
->sparc_psr_type
= type
;
385 return tdep
->sparc_psr_type
;
389 sparc_fsr_type (struct gdbarch
*gdbarch
)
391 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
393 if (!tdep
->sparc_fsr_type
)
397 type
= arch_flags_type (gdbarch
, "builtin_type_sparc_fsr", 4);
398 append_flags_type_flag (type
, 0, "NXA");
399 append_flags_type_flag (type
, 1, "DZA");
400 append_flags_type_flag (type
, 2, "UFA");
401 append_flags_type_flag (type
, 3, "OFA");
402 append_flags_type_flag (type
, 4, "NVA");
403 append_flags_type_flag (type
, 5, "NXC");
404 append_flags_type_flag (type
, 6, "DZC");
405 append_flags_type_flag (type
, 7, "UFC");
406 append_flags_type_flag (type
, 8, "OFC");
407 append_flags_type_flag (type
, 9, "NVC");
408 append_flags_type_flag (type
, 22, "NS");
409 append_flags_type_flag (type
, 23, "NXM");
410 append_flags_type_flag (type
, 24, "DZM");
411 append_flags_type_flag (type
, 25, "UFM");
412 append_flags_type_flag (type
, 26, "OFM");
413 append_flags_type_flag (type
, 27, "NVM");
415 tdep
->sparc_fsr_type
= type
;
418 return tdep
->sparc_fsr_type
;
421 /* Return the GDB type object for the "standard" data type of data in
422 pseudo register REGNUM. */
425 sparc32_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
427 regnum
-= gdbarch_num_regs (gdbarch
);
429 if (regnum
>= SPARC32_D0_REGNUM
&& regnum
<= SPARC32_D30_REGNUM
)
430 return builtin_type (gdbarch
)->builtin_double
;
432 internal_error (__FILE__
, __LINE__
,
433 _("sparc32_pseudo_register_type: bad register number %d"),
437 /* Return the GDB type object for the "standard" data type of data in
441 sparc32_register_type (struct gdbarch
*gdbarch
, int regnum
)
443 if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
444 return tdesc_register_type (gdbarch
, regnum
);
446 if (regnum
>= SPARC_F0_REGNUM
&& regnum
<= SPARC_F31_REGNUM
)
447 return builtin_type (gdbarch
)->builtin_float
;
449 if (regnum
== SPARC_SP_REGNUM
|| regnum
== SPARC_FP_REGNUM
)
450 return builtin_type (gdbarch
)->builtin_data_ptr
;
452 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== SPARC32_NPC_REGNUM
)
453 return builtin_type (gdbarch
)->builtin_func_ptr
;
455 if (regnum
== SPARC32_PSR_REGNUM
)
456 return sparc_psr_type (gdbarch
);
458 if (regnum
== SPARC32_FSR_REGNUM
)
459 return sparc_fsr_type (gdbarch
);
461 if (regnum
>= gdbarch_num_regs (gdbarch
))
462 return sparc32_pseudo_register_type (gdbarch
, regnum
);
464 return builtin_type (gdbarch
)->builtin_int32
;
467 static enum register_status
468 sparc32_pseudo_register_read (struct gdbarch
*gdbarch
,
469 struct regcache
*regcache
,
470 int regnum
, gdb_byte
*buf
)
472 enum register_status status
;
474 regnum
-= gdbarch_num_regs (gdbarch
);
475 gdb_assert (regnum
>= SPARC32_D0_REGNUM
&& regnum
<= SPARC32_D30_REGNUM
);
477 regnum
= SPARC_F0_REGNUM
+ 2 * (regnum
- SPARC32_D0_REGNUM
);
478 status
= regcache_raw_read (regcache
, regnum
, buf
);
479 if (status
== REG_VALID
)
480 status
= regcache_raw_read (regcache
, regnum
+ 1, buf
+ 4);
485 sparc32_pseudo_register_write (struct gdbarch
*gdbarch
,
486 struct regcache
*regcache
,
487 int regnum
, const gdb_byte
*buf
)
489 regnum
-= gdbarch_num_regs (gdbarch
);
490 gdb_assert (regnum
>= SPARC32_D0_REGNUM
&& regnum
<= SPARC32_D30_REGNUM
);
492 regnum
= SPARC_F0_REGNUM
+ 2 * (regnum
- SPARC32_D0_REGNUM
);
493 regcache_raw_write (regcache
, regnum
, buf
);
494 regcache_raw_write (regcache
, regnum
+ 1, buf
+ 4);
497 /* Implement the stack_frame_destroyed_p gdbarch method. */
500 sparc_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
502 /* This function must return true if we are one instruction after an
503 instruction that destroyed the stack frame of the current
504 function. The SPARC instructions used to restore the callers
505 stack frame are RESTORE and RETURN/RETT.
507 Of these RETURN/RETT is a branch instruction and thus we return
508 true if we are in its delay slot.
510 RESTORE is almost always found in the delay slot of a branch
511 instruction that transfers control to the caller, such as JMPL.
512 Thus the next instruction is in the caller frame and we don't
513 need to do anything about it. */
515 unsigned int insn
= sparc_fetch_instruction (pc
- 4);
517 return X_RETTURN (insn
);
522 sparc32_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR address
)
524 /* The ABI requires double-word alignment. */
525 return address
& ~0x7;
529 sparc32_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
531 struct value
**args
, int nargs
,
532 struct type
*value_type
,
533 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
534 struct regcache
*regcache
)
536 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
541 if (using_struct_return (gdbarch
, NULL
, value_type
))
545 /* This is an UNIMP instruction. */
546 store_unsigned_integer (buf
, 4, byte_order
,
547 TYPE_LENGTH (value_type
) & 0x1fff);
548 write_memory (sp
- 8, buf
, 4);
556 sparc32_store_arguments (struct regcache
*regcache
, int nargs
,
557 struct value
**args
, CORE_ADDR sp
,
558 int struct_return
, CORE_ADDR struct_addr
)
560 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
561 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
562 /* Number of words in the "parameter array". */
563 int num_elements
= 0;
567 for (i
= 0; i
< nargs
; i
++)
569 struct type
*type
= value_type (args
[i
]);
570 int len
= TYPE_LENGTH (type
);
572 if (sparc_structure_or_union_p (type
)
573 || (sparc_floating_p (type
) && len
== 16)
574 || sparc_complex_floating_p (type
))
576 /* Structure, Union and Quad-Precision Arguments. */
579 /* Use doubleword alignment for these values. That's always
580 correct, and wasting a few bytes shouldn't be a problem. */
583 write_memory (sp
, value_contents (args
[i
]), len
);
584 args
[i
] = value_from_pointer (lookup_pointer_type (type
), sp
);
587 else if (sparc_floating_p (type
))
589 /* Floating arguments. */
590 gdb_assert (len
== 4 || len
== 8);
591 num_elements
+= (len
/ 4);
595 /* Integral and pointer arguments. */
596 gdb_assert (sparc_integral_or_pointer_p (type
));
599 args
[i
] = value_cast (builtin_type (gdbarch
)->builtin_int32
,
601 num_elements
+= ((len
+ 3) / 4);
605 /* Always allocate at least six words. */
606 sp
-= std::max (6, num_elements
) * 4;
608 /* The psABI says that "Software convention requires space for the
609 struct/union return value pointer, even if the word is unused." */
612 /* The psABI says that "Although software convention and the
613 operating system require every stack frame to be doubleword
617 for (i
= 0; i
< nargs
; i
++)
619 const bfd_byte
*valbuf
= value_contents (args
[i
]);
620 struct type
*type
= value_type (args
[i
]);
621 int len
= TYPE_LENGTH (type
);
623 gdb_assert (len
== 4 || len
== 8);
627 int regnum
= SPARC_O0_REGNUM
+ element
;
629 regcache_cooked_write (regcache
, regnum
, valbuf
);
630 if (len
> 4 && element
< 5)
631 regcache_cooked_write (regcache
, regnum
+ 1, valbuf
+ 4);
634 /* Always store the argument in memory. */
635 write_memory (sp
+ 4 + element
* 4, valbuf
, len
);
639 gdb_assert (element
== num_elements
);
645 store_unsigned_integer (buf
, 4, byte_order
, struct_addr
);
646 write_memory (sp
, buf
, 4);
653 sparc32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
654 struct regcache
*regcache
, CORE_ADDR bp_addr
,
655 int nargs
, struct value
**args
, CORE_ADDR sp
,
656 int struct_return
, CORE_ADDR struct_addr
)
658 CORE_ADDR call_pc
= (struct_return
? (bp_addr
- 12) : (bp_addr
- 8));
660 /* Set return address. */
661 regcache_cooked_write_unsigned (regcache
, SPARC_O7_REGNUM
, call_pc
);
663 /* Set up function arguments. */
664 sp
= sparc32_store_arguments (regcache
, nargs
, args
, sp
,
665 struct_return
, struct_addr
);
667 /* Allocate the 16-word window save area. */
670 /* Stack should be doubleword aligned at this point. */
671 gdb_assert (sp
% 8 == 0);
673 /* Finally, update the stack pointer. */
674 regcache_cooked_write_unsigned (regcache
, SPARC_SP_REGNUM
, sp
);
680 /* Use the program counter to determine the contents and size of a
681 breakpoint instruction. Return a pointer to a string of bytes that
682 encode a breakpoint instruction, store the length of the string in
683 *LEN and optionally adjust *PC to point to the correct memory
684 location for inserting the breakpoint. */
685 constexpr gdb_byte sparc_break_insn
[] = { 0x91, 0xd0, 0x20, 0x01 };
687 typedef BP_MANIPULATION (sparc_break_insn
) sparc_breakpoint
;
690 /* Allocate and initialize a frame cache. */
692 static struct sparc_frame_cache
*
693 sparc_alloc_frame_cache (void)
695 struct sparc_frame_cache
*cache
;
697 cache
= FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache
);
703 /* Frameless until proven otherwise. */
704 cache
->frameless_p
= 1;
705 cache
->frame_offset
= 0;
706 cache
->saved_regs_mask
= 0;
707 cache
->copied_regs_mask
= 0;
708 cache
->struct_return_p
= 0;
713 /* GCC generates several well-known sequences of instructions at the begining
714 of each function prologue when compiling with -fstack-check. If one of
715 such sequences starts at START_PC, then return the address of the
716 instruction immediately past this sequence. Otherwise, return START_PC. */
719 sparc_skip_stack_check (const CORE_ADDR start_pc
)
721 CORE_ADDR pc
= start_pc
;
723 int probing_loop
= 0;
725 /* With GCC, all stack checking sequences begin with the same two
726 instructions, plus an optional one in the case of a probing loop:
728 sethi <some immediate>, %g1
733 sethi <some immediate>, %g1
734 sethi <some immediate>, %g4
739 sethi <some immediate>, %g1
741 sethi <some immediate>, %g4
743 If the optional instruction is found (setting g4), assume that a
744 probing loop will follow. */
746 /* sethi <some immediate>, %g1 */
747 insn
= sparc_fetch_instruction (pc
);
749 if (!(X_OP (insn
) == 0 && X_OP2 (insn
) == 0x4 && X_RD (insn
) == 1))
752 /* optional: sethi <some immediate>, %g4 */
753 insn
= sparc_fetch_instruction (pc
);
755 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 0x4 && X_RD (insn
) == 4)
758 insn
= sparc_fetch_instruction (pc
);
762 /* sub %sp, %g1, %g1 */
763 if (!(X_OP (insn
) == 2 && X_OP3 (insn
) == 0x4 && !X_I(insn
)
764 && X_RD (insn
) == 1 && X_RS1 (insn
) == 14 && X_RS2 (insn
) == 1))
767 insn
= sparc_fetch_instruction (pc
);
770 /* optional: sethi <some immediate>, %g4 */
771 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 0x4 && X_RD (insn
) == 4)
774 insn
= sparc_fetch_instruction (pc
);
778 /* First possible sequence:
779 [first two instructions above]
780 clr [%g1 - some immediate] */
782 /* clr [%g1 - some immediate] */
783 if (X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && X_I(insn
)
784 && X_RS1 (insn
) == 1 && X_RD (insn
) == 0)
786 /* Valid stack-check sequence, return the new PC. */
790 /* Second possible sequence: A small number of probes.
791 [first two instructions above]
793 add %g1, -<some immediate>, %g1
795 [repeat the two instructions above any (small) number of times]
796 clr [%g1 - some immediate] */
799 else if (X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && !X_I(insn
)
800 && X_RS1 (insn
) == 1 && X_RD (insn
) == 0)
804 /* add %g1, -<some immediate>, %g1 */
805 insn
= sparc_fetch_instruction (pc
);
807 if (!(X_OP (insn
) == 2 && X_OP3(insn
) == 0 && X_I(insn
)
808 && X_RS1 (insn
) == 1 && X_RD (insn
) == 1))
812 insn
= sparc_fetch_instruction (pc
);
814 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && !X_I(insn
)
815 && X_RD (insn
) == 0 && X_RS1 (insn
) == 1))
819 /* clr [%g1 - some immediate] */
820 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && X_I(insn
)
821 && X_RS1 (insn
) == 1 && X_RD (insn
) == 0))
824 /* We found a valid stack-check sequence, return the new PC. */
828 /* Third sequence: A probing loop.
829 [first three instructions above]
833 add %g1, -<some immediate>, %g1
837 And an optional last probe for the remainder:
839 clr [%g4 - some immediate] */
843 /* sub %g1, %g4, %g4 */
844 if (!(X_OP (insn
) == 2 && X_OP3 (insn
) == 0x4 && !X_I(insn
)
845 && X_RD (insn
) == 4 && X_RS1 (insn
) == 1 && X_RS2 (insn
) == 4))
849 insn
= sparc_fetch_instruction (pc
);
851 if (!(X_OP (insn
) == 2 && X_OP3 (insn
) == 0x14 && !X_I(insn
)
852 && X_RD (insn
) == 0 && X_RS1 (insn
) == 1 && X_RS2 (insn
) == 4))
856 insn
= sparc_fetch_instruction (pc
);
858 if (!(X_OP (insn
) == 0 && X_COND (insn
) == 0x1))
861 /* add %g1, -<some immediate>, %g1 */
862 insn
= sparc_fetch_instruction (pc
);
864 if (!(X_OP (insn
) == 2 && X_OP3(insn
) == 0 && X_I(insn
)
865 && X_RS1 (insn
) == 1 && X_RD (insn
) == 1))
869 insn
= sparc_fetch_instruction (pc
);
871 if (!(X_OP (insn
) == 0 && X_COND (insn
) == 0x8))
874 /* clr [%g1] (st %g0, [%g1] or st %g0, [%g1+0]) */
875 insn
= sparc_fetch_instruction (pc
);
877 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4
878 && X_RD (insn
) == 0 && X_RS1 (insn
) == 1
879 && (!X_I(insn
) || X_SIMM13 (insn
) == 0)))
882 /* We found a valid stack-check sequence, return the new PC. */
884 /* optional: clr [%g4 - some immediate] */
885 insn
= sparc_fetch_instruction (pc
);
887 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && X_I(insn
)
888 && X_RS1 (insn
) == 4 && X_RD (insn
) == 0))
894 /* No stack check code in our prologue, return the start_pc. */
898 /* Record the effect of a SAVE instruction on CACHE. */
901 sparc_record_save_insn (struct sparc_frame_cache
*cache
)
903 /* The frame is set up. */
904 cache
->frameless_p
= 0;
906 /* The frame pointer contains the CFA. */
907 cache
->frame_offset
= 0;
909 /* The `local' and `in' registers are all saved. */
910 cache
->saved_regs_mask
= 0xffff;
912 /* The `out' registers are all renamed. */
913 cache
->copied_regs_mask
= 0xff;
916 /* Do a full analysis of the prologue at PC and update CACHE accordingly.
917 Bail out early if CURRENT_PC is reached. Return the address where
918 the analysis stopped.
920 We handle both the traditional register window model and the single
921 register window (aka flat) model. */
924 sparc_analyze_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
925 CORE_ADDR current_pc
, struct sparc_frame_cache
*cache
)
927 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
932 pc
= sparc_skip_stack_check (pc
);
934 if (current_pc
<= pc
)
937 /* We have to handle to "Procedure Linkage Table" (PLT) special. On
938 SPARC the linker usually defines a symbol (typically
939 _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section.
940 This symbol makes us end up here with PC pointing at the start of
941 the PLT and CURRENT_PC probably pointing at a PLT entry. If we
942 would do our normal prologue analysis, we would probably conclude
943 that we've got a frame when in reality we don't, since the
944 dynamic linker patches up the first PLT with some code that
945 starts with a SAVE instruction. Patch up PC such that it points
946 at the start of our PLT entry. */
947 if (tdep
->plt_entry_size
> 0 && in_plt_section (current_pc
))
948 pc
= current_pc
- ((current_pc
- pc
) % tdep
->plt_entry_size
);
950 insn
= sparc_fetch_instruction (pc
);
952 /* Recognize store insns and record their sources. */
953 while (X_OP (insn
) == 3
954 && (X_OP3 (insn
) == 0x4 /* stw */
955 || X_OP3 (insn
) == 0x7 /* std */
956 || X_OP3 (insn
) == 0xe) /* stx */
957 && X_RS1 (insn
) == SPARC_SP_REGNUM
)
959 int regnum
= X_RD (insn
);
961 /* Recognize stores into the corresponding stack slots. */
962 if (regnum
>= SPARC_L0_REGNUM
&& regnum
<= SPARC_I7_REGNUM
964 && X_SIMM13 (insn
) == (X_OP3 (insn
) == 0xe
965 ? (regnum
- SPARC_L0_REGNUM
) * 8 + BIAS
966 : (regnum
- SPARC_L0_REGNUM
) * 4))
967 || (!X_I (insn
) && regnum
== SPARC_L0_REGNUM
)))
969 cache
->saved_regs_mask
|= (1 << (regnum
- SPARC_L0_REGNUM
));
970 if (X_OP3 (insn
) == 0x7)
971 cache
->saved_regs_mask
|= (1 << (regnum
+ 1 - SPARC_L0_REGNUM
));
976 insn
= sparc_fetch_instruction (pc
+ offset
);
979 /* Recognize a SETHI insn and record its destination. */
980 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 0x04)
985 insn
= sparc_fetch_instruction (pc
+ offset
);
988 /* Allow for an arithmetic operation on DEST or %g1. */
989 if (X_OP (insn
) == 2 && X_I (insn
)
990 && (X_RD (insn
) == 1 || X_RD (insn
) == dest
))
994 insn
= sparc_fetch_instruction (pc
+ offset
);
997 /* Check for the SAVE instruction that sets up the frame. */
998 if (X_OP (insn
) == 2 && X_OP3 (insn
) == 0x3c)
1000 sparc_record_save_insn (cache
);
1005 /* Check for an arithmetic operation on %sp. */
1006 if (X_OP (insn
) == 2
1007 && (X_OP3 (insn
) == 0 || X_OP3 (insn
) == 0x4)
1008 && X_RS1 (insn
) == SPARC_SP_REGNUM
1009 && X_RD (insn
) == SPARC_SP_REGNUM
)
1013 cache
->frame_offset
= X_SIMM13 (insn
);
1014 if (X_OP3 (insn
) == 0)
1015 cache
->frame_offset
= -cache
->frame_offset
;
1019 insn
= sparc_fetch_instruction (pc
+ offset
);
1021 /* Check for an arithmetic operation that sets up the frame. */
1022 if (X_OP (insn
) == 2
1023 && (X_OP3 (insn
) == 0 || X_OP3 (insn
) == 0x4)
1024 && X_RS1 (insn
) == SPARC_SP_REGNUM
1025 && X_RD (insn
) == SPARC_FP_REGNUM
)
1027 cache
->frameless_p
= 0;
1028 cache
->frame_offset
= 0;
1029 /* We could check that the amount subtracted to %sp above is the
1030 same as the one added here, but this seems superfluous. */
1031 cache
->copied_regs_mask
|= 0x40;
1034 insn
= sparc_fetch_instruction (pc
+ offset
);
1037 /* Check for a move (or) operation that copies the return register. */
1038 if (X_OP (insn
) == 2
1039 && X_OP3 (insn
) == 0x2
1041 && X_RS1 (insn
) == SPARC_G0_REGNUM
1042 && X_RS2 (insn
) == SPARC_O7_REGNUM
1043 && X_RD (insn
) == SPARC_I7_REGNUM
)
1045 cache
->copied_regs_mask
|= 0x80;
1056 sparc_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1058 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1059 return frame_unwind_register_unsigned (this_frame
, tdep
->pc_regnum
);
1062 /* Return PC of first real instruction of the function starting at
1066 sparc32_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
1068 struct symtab_and_line sal
;
1069 CORE_ADDR func_start
, func_end
;
1070 struct sparc_frame_cache cache
;
1072 /* This is the preferred method, find the end of the prologue by
1073 using the debugging information. */
1074 if (find_pc_partial_function (start_pc
, NULL
, &func_start
, &func_end
))
1076 sal
= find_pc_line (func_start
, 0);
1078 if (sal
.end
< func_end
1079 && start_pc
<= sal
.end
)
1083 start_pc
= sparc_analyze_prologue (gdbarch
, start_pc
, 0xffffffffUL
, &cache
);
1085 /* The psABI says that "Although the first 6 words of arguments
1086 reside in registers, the standard stack frame reserves space for
1087 them.". It also suggests that a function may use that space to
1088 "write incoming arguments 0 to 5" into that space, and that's
1089 indeed what GCC seems to be doing. In that case GCC will
1090 generate debug information that points to the stack slots instead
1091 of the registers, so we should consider the instructions that
1092 write out these incoming arguments onto the stack. */
1096 unsigned long insn
= sparc_fetch_instruction (start_pc
);
1098 /* Recognize instructions that store incoming arguments into the
1099 corresponding stack slots. */
1100 if (X_OP (insn
) == 3 && (X_OP3 (insn
) & 0x3c) == 0x04
1101 && X_I (insn
) && X_RS1 (insn
) == SPARC_FP_REGNUM
)
1103 int regnum
= X_RD (insn
);
1105 /* Case of arguments still in %o[0..5]. */
1106 if (regnum
>= SPARC_O0_REGNUM
&& regnum
<= SPARC_O5_REGNUM
1107 && !(cache
.copied_regs_mask
& (1 << (regnum
- SPARC_O0_REGNUM
)))
1108 && X_SIMM13 (insn
) == 68 + (regnum
- SPARC_O0_REGNUM
) * 4)
1114 /* Case of arguments copied into %i[0..5]. */
1115 if (regnum
>= SPARC_I0_REGNUM
&& regnum
<= SPARC_I5_REGNUM
1116 && (cache
.copied_regs_mask
& (1 << (regnum
- SPARC_I0_REGNUM
)))
1117 && X_SIMM13 (insn
) == 68 + (regnum
- SPARC_I0_REGNUM
) * 4)
1130 /* Normal frames. */
1132 struct sparc_frame_cache
*
1133 sparc_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1135 struct sparc_frame_cache
*cache
;
1138 return (struct sparc_frame_cache
*) *this_cache
;
1140 cache
= sparc_alloc_frame_cache ();
1141 *this_cache
= cache
;
1143 cache
->pc
= get_frame_func (this_frame
);
1145 sparc_analyze_prologue (get_frame_arch (this_frame
), cache
->pc
,
1146 get_frame_pc (this_frame
), cache
);
1148 if (cache
->frameless_p
)
1150 /* This function is frameless, so %fp (%i6) holds the frame
1151 pointer for our calling frame. Use %sp (%o6) as this frame's
1154 get_frame_register_unsigned (this_frame
, SPARC_SP_REGNUM
);
1158 /* For normal frames, %fp (%i6) holds the frame pointer, the
1159 base address for the current stack frame. */
1161 get_frame_register_unsigned (this_frame
, SPARC_FP_REGNUM
);
1164 cache
->base
+= cache
->frame_offset
;
1166 if (cache
->base
& 1)
1167 cache
->base
+= BIAS
;
1173 sparc32_struct_return_from_sym (struct symbol
*sym
)
1175 struct type
*type
= check_typedef (SYMBOL_TYPE (sym
));
1176 enum type_code code
= TYPE_CODE (type
);
1178 if (code
== TYPE_CODE_FUNC
|| code
== TYPE_CODE_METHOD
)
1180 type
= check_typedef (TYPE_TARGET_TYPE (type
));
1181 if (sparc_structure_or_union_p (type
)
1182 || (sparc_floating_p (type
) && TYPE_LENGTH (type
) == 16))
1189 struct sparc_frame_cache
*
1190 sparc32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1192 struct sparc_frame_cache
*cache
;
1196 return (struct sparc_frame_cache
*) *this_cache
;
1198 cache
= sparc_frame_cache (this_frame
, this_cache
);
1200 sym
= find_pc_function (cache
->pc
);
1203 cache
->struct_return_p
= sparc32_struct_return_from_sym (sym
);
1207 /* There is no debugging information for this function to
1208 help us determine whether this function returns a struct
1209 or not. So we rely on another heuristic which is to check
1210 the instruction at the return address and see if this is
1211 an "unimp" instruction. If it is, then it is a struct-return
1215 (cache
->copied_regs_mask
& 0x80) ? SPARC_I7_REGNUM
: SPARC_O7_REGNUM
;
1217 pc
= get_frame_register_unsigned (this_frame
, regnum
) + 8;
1218 if (sparc_is_unimp_insn (pc
))
1219 cache
->struct_return_p
= 1;
1226 sparc32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1227 struct frame_id
*this_id
)
1229 struct sparc_frame_cache
*cache
=
1230 sparc32_frame_cache (this_frame
, this_cache
);
1232 /* This marks the outermost frame. */
1233 if (cache
->base
== 0)
1236 (*this_id
) = frame_id_build (cache
->base
, cache
->pc
);
1239 static struct value
*
1240 sparc32_frame_prev_register (struct frame_info
*this_frame
,
1241 void **this_cache
, int regnum
)
1243 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1244 struct sparc_frame_cache
*cache
=
1245 sparc32_frame_cache (this_frame
, this_cache
);
1247 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== SPARC32_NPC_REGNUM
)
1249 CORE_ADDR pc
= (regnum
== SPARC32_NPC_REGNUM
) ? 4 : 0;
1251 /* If this functions has a Structure, Union or Quad-Precision
1252 return value, we have to skip the UNIMP instruction that encodes
1253 the size of the structure. */
1254 if (cache
->struct_return_p
)
1258 (cache
->copied_regs_mask
& 0x80) ? SPARC_I7_REGNUM
: SPARC_O7_REGNUM
;
1259 pc
+= get_frame_register_unsigned (this_frame
, regnum
) + 8;
1260 return frame_unwind_got_constant (this_frame
, regnum
, pc
);
1263 /* Handle StackGhost. */
1265 ULONGEST wcookie
= sparc_fetch_wcookie (gdbarch
);
1267 if (wcookie
!= 0 && !cache
->frameless_p
&& regnum
== SPARC_I7_REGNUM
)
1269 CORE_ADDR addr
= cache
->base
+ (regnum
- SPARC_L0_REGNUM
) * 4;
1272 /* Read the value in from memory. */
1273 i7
= get_frame_memory_unsigned (this_frame
, addr
, 4);
1274 return frame_unwind_got_constant (this_frame
, regnum
, i7
^ wcookie
);
1278 /* The previous frame's `local' and `in' registers may have been saved
1279 in the register save area. */
1280 if (regnum
>= SPARC_L0_REGNUM
&& regnum
<= SPARC_I7_REGNUM
1281 && (cache
->saved_regs_mask
& (1 << (regnum
- SPARC_L0_REGNUM
))))
1283 CORE_ADDR addr
= cache
->base
+ (regnum
- SPARC_L0_REGNUM
) * 4;
1285 return frame_unwind_got_memory (this_frame
, regnum
, addr
);
1288 /* The previous frame's `out' registers may be accessible as the current
1289 frame's `in' registers. */
1290 if (regnum
>= SPARC_O0_REGNUM
&& regnum
<= SPARC_O7_REGNUM
1291 && (cache
->copied_regs_mask
& (1 << (regnum
- SPARC_O0_REGNUM
))))
1292 regnum
+= (SPARC_I0_REGNUM
- SPARC_O0_REGNUM
);
1294 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1297 static const struct frame_unwind sparc32_frame_unwind
=
1300 default_frame_unwind_stop_reason
,
1301 sparc32_frame_this_id
,
1302 sparc32_frame_prev_register
,
1304 default_frame_sniffer
1309 sparc32_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
1311 struct sparc_frame_cache
*cache
=
1312 sparc32_frame_cache (this_frame
, this_cache
);
1317 static const struct frame_base sparc32_frame_base
=
1319 &sparc32_frame_unwind
,
1320 sparc32_frame_base_address
,
1321 sparc32_frame_base_address
,
1322 sparc32_frame_base_address
1325 static struct frame_id
1326 sparc_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1330 sp
= get_frame_register_unsigned (this_frame
, SPARC_SP_REGNUM
);
1333 return frame_id_build (sp
, get_frame_pc (this_frame
));
1337 /* Extract a function return value of TYPE from REGCACHE, and copy
1338 that into VALBUF. */
1341 sparc32_extract_return_value (struct type
*type
, struct regcache
*regcache
,
1344 int len
= TYPE_LENGTH (type
);
1347 gdb_assert (!sparc_structure_or_union_p (type
));
1348 gdb_assert (!(sparc_floating_p (type
) && len
== 16));
1350 if (sparc_floating_p (type
) || sparc_complex_floating_p (type
))
1352 /* Floating return values. */
1353 regcache_cooked_read (regcache
, SPARC_F0_REGNUM
, buf
);
1355 regcache_cooked_read (regcache
, SPARC_F1_REGNUM
, buf
+ 4);
1358 regcache_cooked_read (regcache
, SPARC_F2_REGNUM
, buf
+ 8);
1359 regcache_cooked_read (regcache
, SPARC_F3_REGNUM
, buf
+ 12);
1363 regcache_cooked_read (regcache
, SPARC_F4_REGNUM
, buf
+ 16);
1364 regcache_cooked_read (regcache
, SPARC_F5_REGNUM
, buf
+ 20);
1365 regcache_cooked_read (regcache
, SPARC_F6_REGNUM
, buf
+ 24);
1366 regcache_cooked_read (regcache
, SPARC_F7_REGNUM
, buf
+ 28);
1368 memcpy (valbuf
, buf
, len
);
1372 /* Integral and pointer return values. */
1373 gdb_assert (sparc_integral_or_pointer_p (type
));
1375 regcache_cooked_read (regcache
, SPARC_O0_REGNUM
, buf
);
1378 regcache_cooked_read (regcache
, SPARC_O1_REGNUM
, buf
+ 4);
1379 gdb_assert (len
== 8);
1380 memcpy (valbuf
, buf
, 8);
1384 /* Just stripping off any unused bytes should preserve the
1385 signed-ness just fine. */
1386 memcpy (valbuf
, buf
+ 4 - len
, len
);
1391 /* Store the function return value of type TYPE from VALBUF into
1395 sparc32_store_return_value (struct type
*type
, struct regcache
*regcache
,
1396 const gdb_byte
*valbuf
)
1398 int len
= TYPE_LENGTH (type
);
1401 gdb_assert (!sparc_structure_or_union_p (type
));
1402 gdb_assert (!(sparc_floating_p (type
) && len
== 16));
1403 gdb_assert (len
<= 8);
1405 if (sparc_floating_p (type
) || sparc_complex_floating_p (type
))
1407 /* Floating return values. */
1408 memcpy (buf
, valbuf
, len
);
1409 regcache_cooked_write (regcache
, SPARC_F0_REGNUM
, buf
);
1411 regcache_cooked_write (regcache
, SPARC_F1_REGNUM
, buf
+ 4);
1414 regcache_cooked_write (regcache
, SPARC_F2_REGNUM
, buf
+ 8);
1415 regcache_cooked_write (regcache
, SPARC_F3_REGNUM
, buf
+ 12);
1419 regcache_cooked_write (regcache
, SPARC_F4_REGNUM
, buf
+ 16);
1420 regcache_cooked_write (regcache
, SPARC_F5_REGNUM
, buf
+ 20);
1421 regcache_cooked_write (regcache
, SPARC_F6_REGNUM
, buf
+ 24);
1422 regcache_cooked_write (regcache
, SPARC_F7_REGNUM
, buf
+ 28);
1427 /* Integral and pointer return values. */
1428 gdb_assert (sparc_integral_or_pointer_p (type
));
1432 gdb_assert (len
== 8);
1433 memcpy (buf
, valbuf
, 8);
1434 regcache_cooked_write (regcache
, SPARC_O1_REGNUM
, buf
+ 4);
1438 /* ??? Do we need to do any sign-extension here? */
1439 memcpy (buf
+ 4 - len
, valbuf
, len
);
1441 regcache_cooked_write (regcache
, SPARC_O0_REGNUM
, buf
);
1445 static enum return_value_convention
1446 sparc32_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
1447 struct type
*type
, struct regcache
*regcache
,
1448 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1450 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1452 /* The psABI says that "...every stack frame reserves the word at
1453 %fp+64. If a function returns a structure, union, or
1454 quad-precision value, this word should hold the address of the
1455 object into which the return value should be copied." This
1456 guarantees that we can always find the return value, not just
1457 before the function returns. */
1459 if (sparc_structure_or_union_p (type
)
1460 || (sparc_floating_p (type
) && TYPE_LENGTH (type
) == 16))
1467 regcache_cooked_read_unsigned (regcache
, SPARC_SP_REGNUM
, &sp
);
1468 addr
= read_memory_unsigned_integer (sp
+ 64, 4, byte_order
);
1469 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
1473 regcache_cooked_read_unsigned (regcache
, SPARC_SP_REGNUM
, &sp
);
1474 addr
= read_memory_unsigned_integer (sp
+ 64, 4, byte_order
);
1475 write_memory (addr
, writebuf
, TYPE_LENGTH (type
));
1478 return RETURN_VALUE_ABI_PRESERVES_ADDRESS
;
1482 sparc32_extract_return_value (type
, regcache
, readbuf
);
1484 sparc32_store_return_value (type
, regcache
, writebuf
);
1486 return RETURN_VALUE_REGISTER_CONVENTION
;
1490 sparc32_stabs_argument_has_addr (struct gdbarch
*gdbarch
, struct type
*type
)
1492 return (sparc_structure_or_union_p (type
)
1493 || (sparc_floating_p (type
) && TYPE_LENGTH (type
) == 16)
1494 || sparc_complex_floating_p (type
));
1498 sparc32_dwarf2_struct_return_p (struct frame_info
*this_frame
)
1500 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
1501 struct symbol
*sym
= find_pc_function (pc
);
1504 return sparc32_struct_return_from_sym (sym
);
1509 sparc32_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1510 struct dwarf2_frame_state_reg
*reg
,
1511 struct frame_info
*this_frame
)
1517 case SPARC_G0_REGNUM
:
1518 /* Since %g0 is always zero, there is no point in saving it, and
1519 people will be inclined omit it from the CFI. Make sure we
1520 don't warn about that. */
1521 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
1523 case SPARC_SP_REGNUM
:
1524 reg
->how
= DWARF2_FRAME_REG_CFA
;
1526 case SPARC32_PC_REGNUM
:
1527 case SPARC32_NPC_REGNUM
:
1528 reg
->how
= DWARF2_FRAME_REG_RA_OFFSET
;
1530 if (sparc32_dwarf2_struct_return_p (this_frame
))
1532 if (regnum
== SPARC32_NPC_REGNUM
)
1534 reg
->loc
.offset
= off
;
1540 /* The SPARC Architecture doesn't have hardware single-step support,
1541 and most operating systems don't implement it either, so we provide
1542 software single-step mechanism. */
1545 sparc_analyze_control_transfer (struct regcache
*regcache
,
1546 CORE_ADDR pc
, CORE_ADDR
*npc
)
1548 unsigned long insn
= sparc_fetch_instruction (pc
);
1549 int conditional_p
= X_COND (insn
) & 0x7;
1550 int branch_p
= 0, fused_p
= 0;
1551 long offset
= 0; /* Must be signed for sign-extend. */
1553 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 3)
1555 if ((insn
& 0x10000000) == 0)
1557 /* Branch on Integer Register with Prediction (BPr). */
1563 /* Compare and Branch */
1566 offset
= 4 * X_DISP10 (insn
);
1569 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 6)
1571 /* Branch on Floating-Point Condition Codes (FBfcc). */
1573 offset
= 4 * X_DISP22 (insn
);
1575 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 5)
1577 /* Branch on Floating-Point Condition Codes with Prediction
1580 offset
= 4 * X_DISP19 (insn
);
1582 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 2)
1584 /* Branch on Integer Condition Codes (Bicc). */
1586 offset
= 4 * X_DISP22 (insn
);
1588 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 1)
1590 /* Branch on Integer Condition Codes with Prediction (BPcc). */
1592 offset
= 4 * X_DISP19 (insn
);
1594 else if (X_OP (insn
) == 2 && X_OP3 (insn
) == 0x3a)
1596 struct frame_info
*frame
= get_current_frame ();
1598 /* Trap instruction (TRAP). */
1599 return gdbarch_tdep (get_regcache_arch (regcache
))->step_trap (frame
,
1603 /* FIXME: Handle DONE and RETRY instructions. */
1609 /* Fused compare-and-branch instructions are non-delayed,
1610 and do not have an annuling capability. So we need to
1611 always set a breakpoint on both the NPC and the branch
1613 gdb_assert (offset
!= 0);
1616 else if (conditional_p
)
1618 /* For conditional branches, return nPC + 4 iff the annul
1620 return (X_A (insn
) ? *npc
+ 4 : 0);
1624 /* For unconditional branches, return the target if its
1625 specified condition is "always" and return nPC + 4 if the
1626 condition is "never". If the annul bit is 1, set *NPC to
1628 if (X_COND (insn
) == 0x0)
1629 pc
= *npc
, offset
= 4;
1641 sparc_step_trap (struct frame_info
*frame
, unsigned long insn
)
1646 static VEC (CORE_ADDR
) *
1647 sparc_software_single_step (struct regcache
*regcache
)
1649 struct gdbarch
*arch
= get_regcache_arch (regcache
);
1650 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
1651 CORE_ADDR npc
, nnpc
;
1653 CORE_ADDR pc
, orig_npc
;
1654 VEC (CORE_ADDR
) *next_pcs
= NULL
;
1656 pc
= regcache_raw_get_unsigned (regcache
, tdep
->pc_regnum
);
1657 orig_npc
= npc
= regcache_raw_get_unsigned (regcache
, tdep
->npc_regnum
);
1659 /* Analyze the instruction at PC. */
1660 nnpc
= sparc_analyze_control_transfer (regcache
, pc
, &npc
);
1662 VEC_safe_push (CORE_ADDR
, next_pcs
, npc
);
1665 VEC_safe_push (CORE_ADDR
, next_pcs
, nnpc
);
1667 /* Assert that we have set at least one breakpoint, and that
1668 they're not set at the same spot - unless we're going
1669 from here straight to NULL, i.e. a call or jump to 0. */
1670 gdb_assert (npc
!= 0 || nnpc
!= 0 || orig_npc
== 0);
1671 gdb_assert (nnpc
!= npc
|| orig_npc
== 0);
1677 sparc_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1679 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_regcache_arch (regcache
));
1681 regcache_cooked_write_unsigned (regcache
, tdep
->pc_regnum
, pc
);
1682 regcache_cooked_write_unsigned (regcache
, tdep
->npc_regnum
, pc
+ 4);
1686 /* Iterate over core file register note sections. */
1689 sparc_iterate_over_regset_sections (struct gdbarch
*gdbarch
,
1690 iterate_over_regset_sections_cb
*cb
,
1692 const struct regcache
*regcache
)
1694 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1696 cb (".reg", tdep
->sizeof_gregset
, tdep
->gregset
, NULL
, cb_data
);
1697 cb (".reg2", tdep
->sizeof_fpregset
, tdep
->fpregset
, NULL
, cb_data
);
1702 validate_tdesc_registers (const struct target_desc
*tdesc
,
1703 struct tdesc_arch_data
*tdesc_data
,
1704 const char *feature_name
,
1705 const char *register_names
[],
1706 unsigned int registers_num
,
1707 unsigned int reg_start
)
1710 const struct tdesc_feature
*feature
;
1712 feature
= tdesc_find_feature (tdesc
, feature_name
);
1713 if (feature
== NULL
)
1716 for (unsigned int i
= 0; i
< registers_num
; i
++)
1717 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
1724 static struct gdbarch
*
1725 sparc32_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1727 struct gdbarch_tdep
*tdep
;
1728 const struct target_desc
*tdesc
= info
.target_desc
;
1729 struct gdbarch
*gdbarch
;
1732 /* If there is already a candidate, use it. */
1733 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
1735 return arches
->gdbarch
;
1737 /* Allocate space for the new architecture. */
1738 tdep
= XCNEW (struct gdbarch_tdep
);
1739 gdbarch
= gdbarch_alloc (&info
, tdep
);
1741 tdep
->pc_regnum
= SPARC32_PC_REGNUM
;
1742 tdep
->npc_regnum
= SPARC32_NPC_REGNUM
;
1743 tdep
->step_trap
= sparc_step_trap
;
1744 tdep
->fpu_register_names
= sparc32_fpu_register_names
;
1745 tdep
->fpu_registers_num
= ARRAY_SIZE (sparc32_fpu_register_names
);
1746 tdep
->cp0_register_names
= sparc32_cp0_register_names
;
1747 tdep
->cp0_registers_num
= ARRAY_SIZE (sparc32_cp0_register_names
);
1749 set_gdbarch_long_double_bit (gdbarch
, 128);
1750 set_gdbarch_long_double_format (gdbarch
, floatformats_sparc_quad
);
1752 set_gdbarch_num_regs (gdbarch
, SPARC32_NUM_REGS
);
1753 set_gdbarch_register_name (gdbarch
, sparc32_register_name
);
1754 set_gdbarch_register_type (gdbarch
, sparc32_register_type
);
1755 set_gdbarch_num_pseudo_regs (gdbarch
, SPARC32_NUM_PSEUDO_REGS
);
1756 set_tdesc_pseudo_register_name (gdbarch
, sparc32_pseudo_register_name
);
1757 set_tdesc_pseudo_register_type (gdbarch
, sparc32_pseudo_register_type
);
1758 set_gdbarch_pseudo_register_read (gdbarch
, sparc32_pseudo_register_read
);
1759 set_gdbarch_pseudo_register_write (gdbarch
, sparc32_pseudo_register_write
);
1761 /* Register numbers of various important registers. */
1762 set_gdbarch_sp_regnum (gdbarch
, SPARC_SP_REGNUM
); /* %sp */
1763 set_gdbarch_pc_regnum (gdbarch
, SPARC32_PC_REGNUM
); /* %pc */
1764 set_gdbarch_fp0_regnum (gdbarch
, SPARC_F0_REGNUM
); /* %f0 */
1766 /* Call dummy code. */
1767 set_gdbarch_frame_align (gdbarch
, sparc32_frame_align
);
1768 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
1769 set_gdbarch_push_dummy_code (gdbarch
, sparc32_push_dummy_code
);
1770 set_gdbarch_push_dummy_call (gdbarch
, sparc32_push_dummy_call
);
1772 set_gdbarch_return_value (gdbarch
, sparc32_return_value
);
1773 set_gdbarch_stabs_argument_has_addr
1774 (gdbarch
, sparc32_stabs_argument_has_addr
);
1776 set_gdbarch_skip_prologue (gdbarch
, sparc32_skip_prologue
);
1778 /* Stack grows downward. */
1779 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
1781 set_gdbarch_breakpoint_kind_from_pc (gdbarch
,
1782 sparc_breakpoint::kind_from_pc
);
1783 set_gdbarch_sw_breakpoint_from_kind (gdbarch
,
1784 sparc_breakpoint::bp_from_kind
);
1786 set_gdbarch_frame_args_skip (gdbarch
, 8);
1788 set_gdbarch_print_insn (gdbarch
, print_insn_sparc
);
1790 set_gdbarch_software_single_step (gdbarch
, sparc_software_single_step
);
1791 set_gdbarch_write_pc (gdbarch
, sparc_write_pc
);
1793 set_gdbarch_dummy_id (gdbarch
, sparc_dummy_id
);
1795 set_gdbarch_unwind_pc (gdbarch
, sparc_unwind_pc
);
1797 frame_base_set_default (gdbarch
, &sparc32_frame_base
);
1799 /* Hook in the DWARF CFI frame unwinder. */
1800 dwarf2_frame_set_init_reg (gdbarch
, sparc32_dwarf2_frame_init_reg
);
1801 /* FIXME: kettenis/20050423: Don't enable the unwinder until the
1802 StackGhost issues have been resolved. */
1804 /* Hook in ABI-specific overrides, if they have been registered. */
1805 gdbarch_init_osabi (info
, gdbarch
);
1807 frame_unwind_append_unwinder (gdbarch
, &sparc32_frame_unwind
);
1809 if (tdesc_has_registers (tdesc
))
1811 struct tdesc_arch_data
*tdesc_data
= tdesc_data_alloc ();
1813 /* Validate that the descriptor provides the mandatory registers
1814 and allocate their numbers. */
1815 valid_p
&= validate_tdesc_registers (tdesc
, tdesc_data
,
1816 "org.gnu.gdb.sparc.cpu",
1817 sparc_core_register_names
,
1818 ARRAY_SIZE (sparc_core_register_names
),
1820 valid_p
&= validate_tdesc_registers (tdesc
, tdesc_data
,
1821 "org.gnu.gdb.sparc.fpu",
1822 tdep
->fpu_register_names
,
1823 tdep
->fpu_registers_num
,
1825 valid_p
&= validate_tdesc_registers (tdesc
, tdesc_data
,
1826 "org.gnu.gdb.sparc.cp0",
1827 tdep
->cp0_register_names
,
1828 tdep
->cp0_registers_num
,
1830 + tdep
->fpu_registers_num
);
1833 tdesc_data_cleanup (tdesc_data
);
1837 /* Target description may have changed. */
1838 info
.tdep_info
= tdesc_data
;
1839 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
1842 /* If we have register sets, enable the generic core file support. */
1844 set_gdbarch_iterate_over_regset_sections
1845 (gdbarch
, sparc_iterate_over_regset_sections
);
1847 register_sparc_ravenscar_ops (gdbarch
);
1852 /* Helper functions for dealing with register windows. */
1855 sparc_supply_rwindow (struct regcache
*regcache
, CORE_ADDR sp
, int regnum
)
1857 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1858 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1865 /* Registers are 64-bit. */
1868 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1870 if (regnum
== i
|| regnum
== -1)
1872 target_read_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 8), buf
, 8);
1874 /* Handle StackGhost. */
1875 if (i
== SPARC_I7_REGNUM
)
1877 ULONGEST wcookie
= sparc_fetch_wcookie (gdbarch
);
1880 i7
= extract_unsigned_integer (buf
+ offset
, 8, byte_order
);
1881 store_unsigned_integer (buf
+ offset
, 8, byte_order
,
1885 regcache_raw_supply (regcache
, i
, buf
);
1891 /* Registers are 32-bit. Toss any sign-extension of the stack
1895 /* Clear out the top half of the temporary buffer, and put the
1896 register value in the bottom half if we're in 64-bit mode. */
1897 if (gdbarch_ptr_bit (get_regcache_arch (regcache
)) == 64)
1903 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1905 if (regnum
== i
|| regnum
== -1)
1907 target_read_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 4),
1910 /* Handle StackGhost. */
1911 if (i
== SPARC_I7_REGNUM
)
1913 ULONGEST wcookie
= sparc_fetch_wcookie (gdbarch
);
1916 i7
= extract_unsigned_integer (buf
+ offset
, 4, byte_order
);
1917 store_unsigned_integer (buf
+ offset
, 4, byte_order
,
1921 regcache_raw_supply (regcache
, i
, buf
);
1928 sparc_collect_rwindow (const struct regcache
*regcache
,
1929 CORE_ADDR sp
, int regnum
)
1931 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1932 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1939 /* Registers are 64-bit. */
1942 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1944 if (regnum
== -1 || regnum
== SPARC_SP_REGNUM
|| regnum
== i
)
1946 regcache_raw_collect (regcache
, i
, buf
);
1948 /* Handle StackGhost. */
1949 if (i
== SPARC_I7_REGNUM
)
1951 ULONGEST wcookie
= sparc_fetch_wcookie (gdbarch
);
1954 i7
= extract_unsigned_integer (buf
+ offset
, 8, byte_order
);
1955 store_unsigned_integer (buf
, 8, byte_order
, i7
^ wcookie
);
1958 target_write_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 8), buf
, 8);
1964 /* Registers are 32-bit. Toss any sign-extension of the stack
1968 /* Only use the bottom half if we're in 64-bit mode. */
1969 if (gdbarch_ptr_bit (get_regcache_arch (regcache
)) == 64)
1972 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1974 if (regnum
== -1 || regnum
== SPARC_SP_REGNUM
|| regnum
== i
)
1976 regcache_raw_collect (regcache
, i
, buf
);
1978 /* Handle StackGhost. */
1979 if (i
== SPARC_I7_REGNUM
)
1981 ULONGEST wcookie
= sparc_fetch_wcookie (gdbarch
);
1984 i7
= extract_unsigned_integer (buf
+ offset
, 4, byte_order
);
1985 store_unsigned_integer (buf
+ offset
, 4, byte_order
,
1989 target_write_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 4),
1996 /* Helper functions for dealing with register sets. */
1999 sparc32_supply_gregset (const struct sparc_gregmap
*gregmap
,
2000 struct regcache
*regcache
,
2001 int regnum
, const void *gregs
)
2003 const gdb_byte
*regs
= (const gdb_byte
*) gregs
;
2004 gdb_byte zero
[4] = { 0 };
2007 if (regnum
== SPARC32_PSR_REGNUM
|| regnum
== -1)
2008 regcache_raw_supply (regcache
, SPARC32_PSR_REGNUM
,
2009 regs
+ gregmap
->r_psr_offset
);
2011 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== -1)
2012 regcache_raw_supply (regcache
, SPARC32_PC_REGNUM
,
2013 regs
+ gregmap
->r_pc_offset
);
2015 if (regnum
== SPARC32_NPC_REGNUM
|| regnum
== -1)
2016 regcache_raw_supply (regcache
, SPARC32_NPC_REGNUM
,
2017 regs
+ gregmap
->r_npc_offset
);
2019 if (regnum
== SPARC32_Y_REGNUM
|| regnum
== -1)
2020 regcache_raw_supply (regcache
, SPARC32_Y_REGNUM
,
2021 regs
+ gregmap
->r_y_offset
);
2023 if (regnum
== SPARC_G0_REGNUM
|| regnum
== -1)
2024 regcache_raw_supply (regcache
, SPARC_G0_REGNUM
, &zero
);
2026 if ((regnum
>= SPARC_G1_REGNUM
&& regnum
<= SPARC_O7_REGNUM
) || regnum
== -1)
2028 int offset
= gregmap
->r_g1_offset
;
2030 for (i
= SPARC_G1_REGNUM
; i
<= SPARC_O7_REGNUM
; i
++)
2032 if (regnum
== i
|| regnum
== -1)
2033 regcache_raw_supply (regcache
, i
, regs
+ offset
);
2038 if ((regnum
>= SPARC_L0_REGNUM
&& regnum
<= SPARC_I7_REGNUM
) || regnum
== -1)
2040 /* Not all of the register set variants include Locals and
2041 Inputs. For those that don't, we read them off the stack. */
2042 if (gregmap
->r_l0_offset
== -1)
2046 regcache_cooked_read_unsigned (regcache
, SPARC_SP_REGNUM
, &sp
);
2047 sparc_supply_rwindow (regcache
, sp
, regnum
);
2051 int offset
= gregmap
->r_l0_offset
;
2053 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
2055 if (regnum
== i
|| regnum
== -1)
2056 regcache_raw_supply (regcache
, i
, regs
+ offset
);
2064 sparc32_collect_gregset (const struct sparc_gregmap
*gregmap
,
2065 const struct regcache
*regcache
,
2066 int regnum
, void *gregs
)
2068 gdb_byte
*regs
= (gdb_byte
*) gregs
;
2071 if (regnum
== SPARC32_PSR_REGNUM
|| regnum
== -1)
2072 regcache_raw_collect (regcache
, SPARC32_PSR_REGNUM
,
2073 regs
+ gregmap
->r_psr_offset
);
2075 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== -1)
2076 regcache_raw_collect (regcache
, SPARC32_PC_REGNUM
,
2077 regs
+ gregmap
->r_pc_offset
);
2079 if (regnum
== SPARC32_NPC_REGNUM
|| regnum
== -1)
2080 regcache_raw_collect (regcache
, SPARC32_NPC_REGNUM
,
2081 regs
+ gregmap
->r_npc_offset
);
2083 if (regnum
== SPARC32_Y_REGNUM
|| regnum
== -1)
2084 regcache_raw_collect (regcache
, SPARC32_Y_REGNUM
,
2085 regs
+ gregmap
->r_y_offset
);
2087 if ((regnum
>= SPARC_G1_REGNUM
&& regnum
<= SPARC_O7_REGNUM
) || regnum
== -1)
2089 int offset
= gregmap
->r_g1_offset
;
2091 /* %g0 is always zero. */
2092 for (i
= SPARC_G1_REGNUM
; i
<= SPARC_O7_REGNUM
; i
++)
2094 if (regnum
== i
|| regnum
== -1)
2095 regcache_raw_collect (regcache
, i
, regs
+ offset
);
2100 if ((regnum
>= SPARC_L0_REGNUM
&& regnum
<= SPARC_I7_REGNUM
) || regnum
== -1)
2102 /* Not all of the register set variants include Locals and
2103 Inputs. For those that don't, we read them off the stack. */
2104 if (gregmap
->r_l0_offset
!= -1)
2106 int offset
= gregmap
->r_l0_offset
;
2108 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
2110 if (regnum
== i
|| regnum
== -1)
2111 regcache_raw_collect (regcache
, i
, regs
+ offset
);
2119 sparc32_supply_fpregset (const struct sparc_fpregmap
*fpregmap
,
2120 struct regcache
*regcache
,
2121 int regnum
, const void *fpregs
)
2123 const gdb_byte
*regs
= (const gdb_byte
*) fpregs
;
2126 for (i
= 0; i
< 32; i
++)
2128 if (regnum
== (SPARC_F0_REGNUM
+ i
) || regnum
== -1)
2129 regcache_raw_supply (regcache
, SPARC_F0_REGNUM
+ i
,
2130 regs
+ fpregmap
->r_f0_offset
+ (i
* 4));
2133 if (regnum
== SPARC32_FSR_REGNUM
|| regnum
== -1)
2134 regcache_raw_supply (regcache
, SPARC32_FSR_REGNUM
,
2135 regs
+ fpregmap
->r_fsr_offset
);
2139 sparc32_collect_fpregset (const struct sparc_fpregmap
*fpregmap
,
2140 const struct regcache
*regcache
,
2141 int regnum
, void *fpregs
)
2143 gdb_byte
*regs
= (gdb_byte
*) fpregs
;
2146 for (i
= 0; i
< 32; i
++)
2148 if (regnum
== (SPARC_F0_REGNUM
+ i
) || regnum
== -1)
2149 regcache_raw_collect (regcache
, SPARC_F0_REGNUM
+ i
,
2150 regs
+ fpregmap
->r_f0_offset
+ (i
* 4));
2153 if (regnum
== SPARC32_FSR_REGNUM
|| regnum
== -1)
2154 regcache_raw_collect (regcache
, SPARC32_FSR_REGNUM
,
2155 regs
+ fpregmap
->r_fsr_offset
);
2161 /* From <machine/reg.h>. */
2162 const struct sparc_gregmap sparc32_sunos4_gregmap
=
2174 const struct sparc_fpregmap sparc32_sunos4_fpregmap
=
2180 const struct sparc_fpregmap sparc32_bsd_fpregmap
=
2187 /* Provide a prototype to silence -Wmissing-prototypes. */
2188 void _initialize_sparc_tdep (void);
2191 _initialize_sparc_tdep (void)
2193 register_gdbarch_init (bfd_arch_sparc
, sparc32_gdbarch_init
);