1 /* Target-dependent code for the SPARC for GDB, the GNU debugger.
2 Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997
3 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* ??? Support for calling functions from gdb in sparc64 is unfinished. */
31 #include "gdb_string.h"
34 #include <sys/procfs.h>
39 #if defined(TARGET_SPARCLET) || defined(TARGET_SPARCLITE)
40 #define SPARC_HAS_FPU 0
42 #define SPARC_HAS_FPU 1
45 #ifdef GDB_TARGET_IS_SPARC64
46 #define FP_REGISTER_BYTES (64 * 4)
48 #define FP_REGISTER_BYTES (32 * 4)
51 /* If not defined, assume 32 bit sparc. */
53 #define FP_MAX_REGNUM (FP0_REGNUM + 32)
56 #define SPARC_INTREG_SIZE (REGISTER_RAW_SIZE (G0_REGNUM))
59 extern int stop_after_trap
;
61 /* We don't store all registers immediately when requested, since they
62 get sent over in large chunks anyway. Instead, we accumulate most
63 of the changes and send them over once. "deferred_stores" keeps
64 track of which sets of registers we have locally-changed copies of,
65 so we only need send the groups that have changed. */
67 int deferred_stores
= 0; /* Cumulates stores we want to do eventually. */
70 /* Some machines, such as Fujitsu SPARClite 86x, have a bi-endian mode
71 where instructions are big-endian and data are little-endian.
72 This flag is set when we detect that the target is of this type. */
77 /* Fetch a single instruction. Even on bi-endian machines
78 such as sparc86x, instructions are always big-endian. */
81 fetch_instruction (pc
)
88 read_memory (pc
, buf
, sizeof (buf
));
90 /* Start at the most significant end of the integer, and work towards
91 the least significant. */
93 for (i
= 0; i
< sizeof (buf
); ++i
)
94 retval
= (retval
<< 8) | buf
[i
];
99 /* Branches with prediction are treated like their non-predicting cousins. */
100 /* FIXME: What about floating point branches? */
102 /* Macros to extract fields from sparc instructions. */
103 #define X_OP(i) (((i) >> 30) & 0x3)
104 #define X_RD(i) (((i) >> 25) & 0x1f)
105 #define X_A(i) (((i) >> 29) & 1)
106 #define X_COND(i) (((i) >> 25) & 0xf)
107 #define X_OP2(i) (((i) >> 22) & 0x7)
108 #define X_IMM22(i) ((i) & 0x3fffff)
109 #define X_OP3(i) (((i) >> 19) & 0x3f)
110 #define X_RS1(i) (((i) >> 14) & 0x1f)
111 #define X_I(i) (((i) >> 13) & 1)
112 #define X_IMM13(i) ((i) & 0x1fff)
113 /* Sign extension macros. */
114 #define X_SIMM13(i) ((X_IMM13 (i) ^ 0x1000) - 0x1000)
115 #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000)
116 #define X_CC(i) (((i) >> 20) & 3)
117 #define X_P(i) (((i) >> 19) & 1)
118 #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000)
119 #define X_RCOND(i) (((i) >> 25) & 7)
120 #define X_DISP16(i) ((((((i) >> 6) && 0xc000) | ((i) & 0x3fff)) ^ 0x8000) - 0x8000)
121 #define X_FCN(i) (((i) >> 25) & 31)
125 Error
, not_branch
, bicc
, bicca
, ba
, baa
, ticc
, ta
,
126 #ifdef GDB_TARGET_IS_SPARC64
132 /* Simulate single-step ptrace call for sun4. Code written by Gary
133 Beihl (beihl@mcc.com). */
135 /* npc4 and next_pc describe the situation at the time that the
136 step-breakpoint was set, not necessary the current value of NPC_REGNUM. */
137 static CORE_ADDR next_pc
, npc4
, target
;
138 static int brknpc4
, brktrg
;
139 typedef char binsn_quantum
[BREAKPOINT_MAX
];
140 static binsn_quantum break_mem
[3];
142 static branch_type isbranch
PARAMS ((long, CORE_ADDR
, CORE_ADDR
*));
144 /* single_step() is called just before we want to resume the inferior,
145 if we want to single-step it but there is no hardware or kernel single-step
146 support (as on all SPARCs). We find all the possible targets of the
147 coming instruction and breakpoint them.
149 single_step is also called just after the inferior stops. If we had
150 set up a simulated single-step, we undo our damage. */
153 sparc_software_single_step (ignore
, insert_breakpoints_p
)
154 enum target_signal ignore
; /* pid, but we don't need it */
155 int insert_breakpoints_p
;
161 if (insert_breakpoints_p
)
163 /* Always set breakpoint for NPC. */
164 next_pc
= read_register (NPC_REGNUM
);
165 npc4
= next_pc
+ 4; /* branch not taken */
167 target_insert_breakpoint (next_pc
, break_mem
[0]);
168 /* printf_unfiltered ("set break at %x\n",next_pc); */
170 pc
= read_register (PC_REGNUM
);
171 pc_instruction
= fetch_instruction (pc
);
172 br
= isbranch (pc_instruction
, pc
, &target
);
173 brknpc4
= brktrg
= 0;
177 /* Conditional annulled branch will either end up at
178 npc (if taken) or at npc+4 (if not taken).
181 target_insert_breakpoint (npc4
, break_mem
[1]);
183 else if (br
== baa
&& target
!= next_pc
)
185 /* Unconditional annulled branch will always end up at
188 target_insert_breakpoint (target
, break_mem
[2]);
190 #ifdef GDB_TARGET_IS_SPARC64
191 else if (br
== done_retry
)
194 target_insert_breakpoint (target
, break_mem
[2]);
200 /* Remove breakpoints */
201 target_remove_breakpoint (next_pc
, break_mem
[0]);
204 target_remove_breakpoint (npc4
, break_mem
[1]);
207 target_remove_breakpoint (target
, break_mem
[2]);
211 /* Call this for each newly created frame. For SPARC, we need to calculate
212 the bottom of the frame, and do some extra work if the prologue
213 has been generated via the -mflat option to GCC. In particular,
214 we need to know where the previous fp and the pc have been stashed,
215 since their exact position within the frame may vary. */
218 sparc_init_extra_frame_info (fromleaf
, fi
)
220 struct frame_info
*fi
;
223 CORE_ADDR prologue_start
, prologue_end
;
228 (fi
->frame
== fi
->next
->frame
? fi
->next
->bottom
: fi
->next
->frame
) :
231 /* If fi->next is NULL, then we already set ->frame by passing read_fp()
232 to create_new_frame. */
235 char buf
[MAX_REGISTER_RAW_SIZE
];
237 /* Compute ->frame as if not flat. If it is flat, we'll change
239 if (fi
->next
->next
!= NULL
240 && (fi
->next
->next
->signal_handler_caller
241 || frame_in_dummy (fi
->next
->next
))
242 && frameless_look_for_prologue (fi
->next
))
244 /* A frameless function interrupted by a signal did not change
245 the frame pointer, fix up frame pointer accordingly. */
246 fi
->frame
= FRAME_FP (fi
->next
);
247 fi
->bottom
= fi
->next
->bottom
;
251 /* Should we adjust for stack bias here? */
252 get_saved_register (buf
, 0, 0, fi
, FP_REGNUM
, 0);
253 fi
->frame
= extract_address (buf
, REGISTER_RAW_SIZE (FP_REGNUM
));
254 #ifdef GDB_TARGET_IS_SPARC64
262 /* Decide whether this is a function with a ``flat register window''
263 frame. For such functions, the frame pointer is actually in %i7. */
266 if (find_pc_partial_function (fi
->pc
, &name
, &prologue_start
, &prologue_end
))
268 /* See if the function starts with an add (which will be of a
269 negative number if a flat frame) to the sp. FIXME: Does not
270 handle large frames which will need more than one instruction
272 insn
= fetch_instruction (prologue_start
, 4);
273 if (X_OP (insn
) == 2 && X_RD (insn
) == 14 && X_OP3 (insn
) == 0
274 && X_I (insn
) && X_SIMM13 (insn
) < 0)
276 int offset
= X_SIMM13 (insn
);
278 /* Then look for a save of %i7 into the frame. */
279 insn
= fetch_instruction (prologue_start
+ 4);
283 && X_RS1 (insn
) == 14)
285 char buf
[MAX_REGISTER_RAW_SIZE
];
287 /* We definitely have a flat frame now. */
290 fi
->sp_offset
= offset
;
292 /* Overwrite the frame's address with the value in %i7. */
293 get_saved_register (buf
, 0, 0, fi
, I7_REGNUM
, 0);
294 fi
->frame
= extract_address (buf
, REGISTER_RAW_SIZE (I7_REGNUM
));
295 #ifdef GDB_TARGET_IS_SPARC64
299 /* Record where the fp got saved. */
300 fi
->fp_addr
= fi
->frame
+ fi
->sp_offset
+ X_SIMM13 (insn
);
302 /* Also try to collect where the pc got saved to. */
304 insn
= fetch_instruction (prologue_start
+ 12);
308 && X_RS1 (insn
) == 14)
309 fi
->pc_addr
= fi
->frame
+ fi
->sp_offset
+ X_SIMM13 (insn
);
314 /* Check if the PC is in the function prologue before a SAVE
315 instruction has been executed yet. If so, set the frame
316 to the current value of the stack pointer and set
317 the in_prologue flag. */
319 struct symtab_and_line sal
;
321 sal
= find_pc_line (prologue_start
, 0);
322 if (sal
.line
== 0) /* no line info, use PC */
323 prologue_end
= fi
->pc
;
324 else if (sal
.end
< prologue_end
)
325 prologue_end
= sal
.end
;
326 if (fi
->pc
< prologue_end
)
328 for (addr
= prologue_start
; addr
< fi
->pc
; addr
+= 4)
330 insn
= read_memory_integer (addr
, 4);
331 if (X_OP (insn
) == 2 && X_OP3 (insn
) == 0x3c)
332 break; /* SAVE seen, stop searching */
337 fi
->frame
= read_register (SP_REGNUM
);
342 if (fi
->next
&& fi
->frame
== 0)
344 /* Kludge to cause init_prev_frame_info to destroy the new frame. */
345 fi
->frame
= fi
->next
->frame
;
346 fi
->pc
= fi
->next
->pc
;
351 sparc_frame_chain (frame
)
352 struct frame_info
*frame
;
354 /* Value that will cause FRAME_CHAIN_VALID to not worry about the chain
355 value. If it realy is zero, we detect it later in
356 sparc_init_prev_frame. */
357 return (CORE_ADDR
) 1;
361 sparc_extract_struct_value_address (regbuf
)
362 char regbuf
[REGISTER_BYTES
];
364 return extract_address (regbuf
+ REGISTER_BYTE (O0_REGNUM
),
365 REGISTER_RAW_SIZE (O0_REGNUM
));
368 /* Find the pc saved in frame FRAME. */
371 sparc_frame_saved_pc (frame
)
372 struct frame_info
*frame
;
374 char buf
[MAX_REGISTER_RAW_SIZE
];
377 if (frame
->signal_handler_caller
)
379 /* This is the signal trampoline frame.
380 Get the saved PC from the sigcontext structure. */
382 #ifndef SIGCONTEXT_PC_OFFSET
383 #define SIGCONTEXT_PC_OFFSET 12
386 CORE_ADDR sigcontext_addr
;
387 char scbuf
[TARGET_PTR_BIT
/ HOST_CHAR_BIT
];
388 int saved_pc_offset
= SIGCONTEXT_PC_OFFSET
;
391 /* Solaris2 ucbsigvechandler passes a pointer to a sigcontext
392 as the third parameter. The offset to the saved pc is 12. */
393 find_pc_partial_function (frame
->pc
, &name
,
394 (CORE_ADDR
*) NULL
, (CORE_ADDR
*) NULL
);
395 if (name
&& STREQ (name
, "ucbsigvechandler"))
396 saved_pc_offset
= 12;
398 /* The sigcontext address is contained in register O2. */
399 get_saved_register (buf
, (int *) NULL
, (CORE_ADDR
*) NULL
,
400 frame
, O0_REGNUM
+ 2, (enum lval_type
*) NULL
);
401 sigcontext_addr
= extract_address (buf
, REGISTER_RAW_SIZE (O0_REGNUM
+ 2));
403 /* Don't cause a memory_error when accessing sigcontext in case the
404 stack layout has changed or the stack is corrupt. */
405 target_read_memory (sigcontext_addr
+ saved_pc_offset
,
406 scbuf
, sizeof (scbuf
));
407 return extract_address (scbuf
, sizeof (scbuf
));
409 else if (frame
->in_prologue
||
411 && (frame
->next
->signal_handler_caller
412 || frame_in_dummy (frame
->next
))
413 && frameless_look_for_prologue (frame
)))
415 /* A frameless function interrupted by a signal did not save
416 the PC, it is still in %o7. */
417 get_saved_register (buf
, (int *) NULL
, (CORE_ADDR
*) NULL
,
418 frame
, O7_REGNUM
, (enum lval_type
*) NULL
);
419 return PC_ADJUST (extract_address (buf
, SPARC_INTREG_SIZE
));
422 addr
= frame
->pc_addr
;
424 addr
= frame
->bottom
+ FRAME_SAVED_I0
+
425 SPARC_INTREG_SIZE
* (I7_REGNUM
- I0_REGNUM
);
428 /* A flat frame leaf function might not save the PC anywhere,
429 just leave it in %o7. */
430 return PC_ADJUST (read_register (O7_REGNUM
));
432 read_memory (addr
, buf
, SPARC_INTREG_SIZE
);
433 return PC_ADJUST (extract_address (buf
, SPARC_INTREG_SIZE
));
436 /* Since an individual frame in the frame cache is defined by two
437 arguments (a frame pointer and a stack pointer), we need two
438 arguments to get info for an arbitrary stack frame. This routine
439 takes two arguments and makes the cached frames look as if these
440 two arguments defined a frame on the cache. This allows the rest
441 of info frame to extract the important arguments without
445 setup_arbitrary_frame (argc
, argv
)
449 struct frame_info
*frame
;
452 error ("Sparc frame specifications require two arguments: fp and sp");
454 frame
= create_new_frame (argv
[0], 0);
457 internal_error ("create_new_frame returned invalid frame");
459 frame
->bottom
= argv
[1];
460 frame
->pc
= FRAME_SAVED_PC (frame
);
464 /* Given a pc value, skip it forward past the function prologue by
465 disassembling instructions that appear to be a prologue.
467 If FRAMELESS_P is set, we are only testing to see if the function
468 is frameless. This allows a quicker answer.
470 This routine should be more specific in its actions; making sure
471 that it uses the same register in the initial prologue section. */
473 static CORE_ADDR examine_prologue
PARAMS ((CORE_ADDR
, int, struct frame_info
*,
474 struct frame_saved_regs
*));
477 examine_prologue (start_pc
, frameless_p
, fi
, saved_regs
)
480 struct frame_info
*fi
;
481 struct frame_saved_regs
*saved_regs
;
485 CORE_ADDR pc
= start_pc
;
488 insn
= fetch_instruction (pc
);
490 /* Recognize the `sethi' insn and record its destination. */
491 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 4)
495 insn
= fetch_instruction (pc
);
498 /* Recognize an add immediate value to register to either %g1 or
499 the destination register recorded above. Actually, this might
500 well recognize several different arithmetic operations.
501 It doesn't check that rs1 == rd because in theory "sub %g0, 5, %g1"
502 followed by "save %sp, %g1, %sp" is a valid prologue (Not that
503 I imagine any compiler really does that, however). */
506 && (X_RD (insn
) == 1 || X_RD (insn
) == dest
))
509 insn
= fetch_instruction (pc
);
512 /* Recognize any SAVE insn. */
513 if (X_OP (insn
) == 2 && X_OP3 (insn
) == 60)
516 if (frameless_p
) /* If the save is all we care about, */
517 return pc
; /* return before doing more work */
518 insn
= fetch_instruction (pc
);
520 /* Recognize add to %sp. */
521 else if (X_OP (insn
) == 2 && X_RD (insn
) == 14 && X_OP3 (insn
) == 0)
524 if (frameless_p
) /* If the add is all we care about, */
525 return pc
; /* return before doing more work */
527 insn
= fetch_instruction (pc
);
528 /* Recognize store of frame pointer (i7). */
532 && X_RS1 (insn
) == 14)
535 insn
= fetch_instruction (pc
);
537 /* Recognize sub %sp, <anything>, %i7. */
540 && X_RS1 (insn
) == 14
541 && X_RD (insn
) == 31)
544 insn
= fetch_instruction (pc
);
553 /* Without a save or add instruction, it's not a prologue. */
558 /* Recognize stores into the frame from the input registers.
559 This recognizes all non alternate stores of input register,
560 into a location offset from the frame pointer. */
561 if ((X_OP (insn
) == 3
562 && (X_OP3 (insn
) & 0x3c) == 4 /* Store, non-alternate. */
563 && (X_RD (insn
) & 0x18) == 0x18 /* Input register. */
564 && X_I (insn
) /* Immediate mode. */
565 && X_RS1 (insn
) == 30 /* Off of frame pointer. */
566 /* Into reserved stack space. */
567 && X_SIMM13 (insn
) >= 0x44
568 && X_SIMM13 (insn
) < 0x5b))
573 && X_RS1 (insn
) == 14
576 if (saved_regs
&& X_I (insn
))
577 saved_regs
->regs
[X_RD (insn
)] =
578 fi
->frame
+ fi
->sp_offset
+ X_SIMM13 (insn
);
583 insn
= fetch_instruction (pc
);
590 sparc_skip_prologue (start_pc
, frameless_p
)
594 return examine_prologue (start_pc
, frameless_p
, NULL
, NULL
);
597 /* Check instruction at ADDR to see if it is a branch.
598 All non-annulled instructions will go to NPC or will trap.
599 Set *TARGET if we find a candidate branch; set to zero if not.
601 This isn't static as it's used by remote-sa.sparc.c. */
604 isbranch (instruction
, addr
, target
)
606 CORE_ADDR addr
, *target
;
608 branch_type val
= not_branch
;
609 long int offset
= 0; /* Must be signed for sign-extend. */
613 if (X_OP (instruction
) == 0
614 && (X_OP2 (instruction
) == 2
615 || X_OP2 (instruction
) == 6
616 || X_OP2 (instruction
) == 1
617 || X_OP2 (instruction
) == 3
618 || X_OP2 (instruction
) == 5
619 #ifndef GDB_TARGET_IS_SPARC64
620 || X_OP2 (instruction
) == 7
624 if (X_COND (instruction
) == 8)
625 val
= X_A (instruction
) ? baa
: ba
;
627 val
= X_A (instruction
) ? bicca
: bicc
;
628 switch (X_OP2 (instruction
))
632 #ifndef GDB_TARGET_IS_SPARC64
635 offset
= 4 * X_DISP22 (instruction
);
639 offset
= 4 * X_DISP19 (instruction
);
642 offset
= 4 * X_DISP16 (instruction
);
645 *target
= addr
+ offset
;
647 #ifdef GDB_TARGET_IS_SPARC64
648 else if (X_OP (instruction
) == 2
649 && X_OP3 (instruction
) == 62)
651 if (X_FCN (instruction
) == 0)
654 *target
= read_register (TNPC_REGNUM
);
657 else if (X_FCN (instruction
) == 1)
660 *target
= read_register (TPC_REGNUM
);
669 /* Find register number REGNUM relative to FRAME and put its
670 (raw) contents in *RAW_BUFFER. Set *OPTIMIZED if the variable
671 was optimized out (and thus can't be fetched). If the variable
672 was fetched from memory, set *ADDRP to where it was fetched from,
673 otherwise it was fetched from a register.
675 The argument RAW_BUFFER must point to aligned memory. */
678 sparc_get_saved_register (raw_buffer
, optimized
, addrp
, frame
, regnum
, lval
)
682 struct frame_info
*frame
;
684 enum lval_type
*lval
;
686 struct frame_info
*frame1
;
689 if (!target_has_registers
)
690 error ("No registers.");
697 /* FIXME This code extracted from infcmd.c; should put elsewhere! */
700 /* error ("No selected frame."); */
701 if (!target_has_registers
)
702 error ("The program has no registers now.");
703 if (selected_frame
== NULL
)
704 error ("No selected frame.");
705 /* Try to use selected frame */
706 frame
= get_prev_frame (selected_frame
);
708 error ("Cmd not meaningful in the outermost frame.");
712 frame1
= frame
->next
;
714 /* Get saved PC from the frame info if not in innermost frame. */
715 if (regnum
== PC_REGNUM
&& frame1
!= NULL
)
719 if (raw_buffer
!= NULL
)
721 /* Put it back in target format. */
722 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
), frame
->pc
);
729 while (frame1
!= NULL
)
731 if (frame1
->pc
>= (frame1
->bottom
? frame1
->bottom
:
733 && frame1
->pc
<= FRAME_FP (frame1
))
735 /* Dummy frame. All but the window regs are in there somewhere.
736 The window registers are saved on the stack, just like in a
738 if (regnum
>= G1_REGNUM
&& regnum
< G1_REGNUM
+ 7)
739 addr
= frame1
->frame
+ (regnum
- G0_REGNUM
) * SPARC_INTREG_SIZE
740 - (FP_REGISTER_BYTES
+ 8 * SPARC_INTREG_SIZE
);
741 else if (regnum
>= I0_REGNUM
&& regnum
< I0_REGNUM
+ 8)
742 addr
= (frame1
->prev
->bottom
743 + (regnum
- I0_REGNUM
) * SPARC_INTREG_SIZE
745 else if (regnum
>= L0_REGNUM
&& regnum
< L0_REGNUM
+ 8)
746 addr
= (frame1
->prev
->bottom
747 + (regnum
- L0_REGNUM
) * SPARC_INTREG_SIZE
749 else if (regnum
>= O0_REGNUM
&& regnum
< O0_REGNUM
+ 8)
750 addr
= frame1
->frame
+ (regnum
- O0_REGNUM
) * SPARC_INTREG_SIZE
751 - (FP_REGISTER_BYTES
+ 16 * SPARC_INTREG_SIZE
);
753 else if (regnum
>= FP0_REGNUM
&& regnum
< FP0_REGNUM
+ 32)
754 addr
= frame1
->frame
+ (regnum
- FP0_REGNUM
) * 4
755 - (FP_REGISTER_BYTES
);
756 #ifdef GDB_TARGET_IS_SPARC64
757 else if (regnum
>= FP0_REGNUM
+ 32 && regnum
< FP_MAX_REGNUM
)
758 addr
= frame1
->frame
+ 32 * 4 + (regnum
- FP0_REGNUM
- 32) * 8
759 - (FP_REGISTER_BYTES
);
761 #endif /* FP0_REGNUM */
762 else if (regnum
>= Y_REGNUM
&& regnum
< NUM_REGS
)
763 addr
= frame1
->frame
+ (regnum
- Y_REGNUM
) * SPARC_INTREG_SIZE
764 - (FP_REGISTER_BYTES
+ 24 * SPARC_INTREG_SIZE
);
766 else if (frame1
->flat
)
769 if (regnum
== RP_REGNUM
)
770 addr
= frame1
->pc_addr
;
771 else if (regnum
== I7_REGNUM
)
772 addr
= frame1
->fp_addr
;
775 CORE_ADDR func_start
;
776 struct frame_saved_regs regs
;
777 memset (®s
, 0, sizeof (regs
));
779 find_pc_partial_function (frame1
->pc
, NULL
, &func_start
, NULL
);
780 examine_prologue (func_start
, 0, frame1
, ®s
);
781 addr
= regs
.regs
[regnum
];
786 /* Normal frame. Local and In registers are saved on stack. */
787 if (regnum
>= I0_REGNUM
&& regnum
< I0_REGNUM
+ 8)
788 addr
= (frame1
->prev
->bottom
789 + (regnum
- I0_REGNUM
) * SPARC_INTREG_SIZE
791 else if (regnum
>= L0_REGNUM
&& regnum
< L0_REGNUM
+ 8)
792 addr
= (frame1
->prev
->bottom
793 + (regnum
- L0_REGNUM
) * SPARC_INTREG_SIZE
795 else if (regnum
>= O0_REGNUM
&& regnum
< O0_REGNUM
+ 8)
797 /* Outs become ins. */
798 get_saved_register (raw_buffer
, optimized
, addrp
, frame1
,
799 (regnum
- O0_REGNUM
+ I0_REGNUM
), lval
);
805 frame1
= frame1
->next
;
811 if (regnum
== SP_REGNUM
)
813 if (raw_buffer
!= NULL
)
815 /* Put it back in target format. */
816 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
), addr
);
822 if (raw_buffer
!= NULL
)
823 read_memory (addr
, raw_buffer
, REGISTER_RAW_SIZE (regnum
));
828 *lval
= lval_register
;
829 addr
= REGISTER_BYTE (regnum
);
830 if (raw_buffer
!= NULL
)
831 read_register_gen (regnum
, raw_buffer
);
837 /* Push an empty stack frame, and record in it the current PC, regs, etc.
839 We save the non-windowed registers and the ins. The locals and outs
840 are new; they don't need to be saved. The i's and l's of
841 the last frame were already saved on the stack. */
843 /* Definitely see tm-sparc.h for more doc of the frame format here. */
845 #ifdef GDB_TARGET_IS_SPARC64
846 #define DUMMY_REG_SAVE_OFFSET (128 + 16)
848 #define DUMMY_REG_SAVE_OFFSET 0x60
851 /* See tm-sparc.h for how this is calculated. */
853 #define DUMMY_STACK_REG_BUF_SIZE \
854 (((8+8+8) * SPARC_INTREG_SIZE) + FP_REGISTER_BYTES)
856 #define DUMMY_STACK_REG_BUF_SIZE \
857 (((8+8+8) * SPARC_INTREG_SIZE) )
858 #endif /* FP0_REGNUM */
859 #define DUMMY_STACK_SIZE (DUMMY_STACK_REG_BUF_SIZE + DUMMY_REG_SAVE_OFFSET)
862 sparc_push_dummy_frame ()
864 CORE_ADDR sp
, old_sp
;
865 char register_temp
[DUMMY_STACK_SIZE
];
867 old_sp
= sp
= read_sp ();
869 #ifdef GDB_TARGET_IS_SPARC64
870 /* PC, NPC, CCR, FSR, FPRS, Y, ASI */
871 read_register_bytes (REGISTER_BYTE (PC_REGNUM
), ®ister_temp
[0],
872 REGISTER_RAW_SIZE (PC_REGNUM
) * 7);
873 read_register_bytes (REGISTER_BYTE (PSTATE_REGNUM
), ®ister_temp
[8],
874 REGISTER_RAW_SIZE (PSTATE_REGNUM
));
875 /* FIXME: not sure what needs to be saved here. */
877 /* Y, PS, WIM, TBR, PC, NPC, FPS, CPS regs */
878 read_register_bytes (REGISTER_BYTE (Y_REGNUM
), ®ister_temp
[0],
879 REGISTER_RAW_SIZE (Y_REGNUM
) * 8);
882 read_register_bytes (REGISTER_BYTE (O0_REGNUM
),
883 ®ister_temp
[8 * SPARC_INTREG_SIZE
],
884 SPARC_INTREG_SIZE
* 8);
886 read_register_bytes (REGISTER_BYTE (G0_REGNUM
),
887 ®ister_temp
[16 * SPARC_INTREG_SIZE
],
888 SPARC_INTREG_SIZE
* 8);
891 read_register_bytes (REGISTER_BYTE (FP0_REGNUM
),
892 ®ister_temp
[24 * SPARC_INTREG_SIZE
],
894 #endif /* FP0_REGNUM */
896 sp
-= DUMMY_STACK_SIZE
;
900 write_memory (sp
+ DUMMY_REG_SAVE_OFFSET
, ®ister_temp
[0],
901 DUMMY_STACK_REG_BUF_SIZE
);
903 if (strcmp (target_shortname
, "sim") != 0)
907 /* Set return address register for the call dummy to the current PC. */
908 write_register (I7_REGNUM
, read_pc () - 8);
912 /* The call dummy will write this value to FP before executing
913 the 'save'. This ensures that register window flushes work
914 correctly in the simulator. */
915 write_register (G0_REGNUM
+ 1, read_register (FP_REGNUM
));
917 /* The call dummy will write this value to FP after executing
919 write_register (G0_REGNUM
+ 2, old_sp
);
921 /* The call dummy will write this value to the return address (%i7) after
922 executing the 'save'. */
923 write_register (G0_REGNUM
+ 3, read_pc () - 8);
925 /* Set the FP that the call dummy will be using after the 'save'.
926 This makes backtraces from an inferior function call work properly. */
927 write_register (FP_REGNUM
, old_sp
);
931 /* sparc_frame_find_saved_regs (). This function is here only because
932 pop_frame uses it. Note there is an interesting corner case which
933 I think few ports of GDB get right--if you are popping a frame
934 which does not save some register that *is* saved by a more inner
935 frame (such a frame will never be a dummy frame because dummy
936 frames save all registers). Rewriting pop_frame to use
937 get_saved_register would solve this problem and also get rid of the
938 ugly duplication between sparc_frame_find_saved_regs and
941 Stores, into a struct frame_saved_regs,
942 the addresses of the saved registers of frame described by FRAME_INFO.
943 This includes special registers such as pc and fp saved in special
944 ways in the stack frame. sp is even more special:
945 the address we return for it IS the sp for the next frame.
947 Note that on register window machines, we are currently making the
948 assumption that window registers are being saved somewhere in the
949 frame in which they are being used. If they are stored in an
950 inferior frame, find_saved_register will break.
952 On the Sun 4, the only time all registers are saved is when
953 a dummy frame is involved. Otherwise, the only saved registers
954 are the LOCAL and IN registers which are saved as a result
955 of the "save/restore" opcodes. This condition is determined
956 by address rather than by value.
958 The "pc" is not stored in a frame on the SPARC. (What is stored
959 is a return address minus 8.) sparc_pop_frame knows how to
960 deal with that. Other routines might or might not.
962 See tm-sparc.h (PUSH_DUMMY_FRAME and friends) for CRITICAL information
963 about how this works. */
965 static void sparc_frame_find_saved_regs
PARAMS ((struct frame_info
*,
966 struct frame_saved_regs
*));
969 sparc_frame_find_saved_regs (fi
, saved_regs_addr
)
970 struct frame_info
*fi
;
971 struct frame_saved_regs
*saved_regs_addr
;
974 CORE_ADDR frame_addr
= FRAME_FP (fi
);
977 internal_error ("Bad frame info struct in FRAME_FIND_SAVED_REGS");
979 memset (saved_regs_addr
, 0, sizeof (*saved_regs_addr
));
981 if (fi
->pc
>= (fi
->bottom
? fi
->bottom
:
983 && fi
->pc
<= FRAME_FP (fi
))
985 /* Dummy frame. All but the window regs are in there somewhere. */
986 for (regnum
= G1_REGNUM
; regnum
< G1_REGNUM
+ 7; regnum
++)
987 saved_regs_addr
->regs
[regnum
] =
988 frame_addr
+ (regnum
- G0_REGNUM
) * SPARC_INTREG_SIZE
989 - DUMMY_STACK_REG_BUF_SIZE
+ 16 * SPARC_INTREG_SIZE
;
990 for (regnum
= I0_REGNUM
; regnum
< I0_REGNUM
+ 8; regnum
++)
991 saved_regs_addr
->regs
[regnum
] =
992 frame_addr
+ (regnum
- I0_REGNUM
) * SPARC_INTREG_SIZE
993 - DUMMY_STACK_REG_BUF_SIZE
+ 8 * SPARC_INTREG_SIZE
;
995 for (regnum
= FP0_REGNUM
; regnum
< FP0_REGNUM
+ 32; regnum
++)
996 saved_regs_addr
->regs
[regnum
] =
997 frame_addr
+ (regnum
- FP0_REGNUM
) * 4
998 - DUMMY_STACK_REG_BUF_SIZE
+ 24 * SPARC_INTREG_SIZE
;
999 #ifdef GDB_TARGET_IS_SPARC64
1000 for (regnum
= FP0_REGNUM
+ 32; regnum
< FP_MAX_REGNUM
; regnum
++)
1001 saved_regs_addr
->regs
[regnum
] =
1002 frame_addr
+ 32 * 4 + (regnum
- FP0_REGNUM
- 32) * 4
1003 - DUMMY_STACK_REG_BUF_SIZE
+ 24 * SPARC_INTREG_SIZE
;
1005 #endif /* FP0_REGNUM */
1006 #ifdef GDB_TARGET_IS_SPARC64
1007 for (regnum
= PC_REGNUM
; regnum
< PC_REGNUM
+ 7; regnum
++)
1009 saved_regs_addr
->regs
[regnum
] =
1010 frame_addr
+ (regnum
- PC_REGNUM
) * SPARC_INTREG_SIZE
1011 - DUMMY_STACK_REG_BUF_SIZE
;
1013 saved_regs_addr
->regs
[PSTATE_REGNUM
] =
1014 frame_addr
+ 8 * SPARC_INTREG_SIZE
- DUMMY_STACK_REG_BUF_SIZE
;
1016 for (regnum
= Y_REGNUM
; regnum
< NUM_REGS
; regnum
++)
1017 saved_regs_addr
->regs
[regnum
] =
1018 frame_addr
+ (regnum
- Y_REGNUM
) * SPARC_INTREG_SIZE
1019 - DUMMY_STACK_REG_BUF_SIZE
;
1021 frame_addr
= fi
->bottom
?
1022 fi
->bottom
: read_sp ();
1026 CORE_ADDR func_start
;
1027 find_pc_partial_function (fi
->pc
, NULL
, &func_start
, NULL
);
1028 examine_prologue (func_start
, 0, fi
, saved_regs_addr
);
1030 /* Flat register window frame. */
1031 saved_regs_addr
->regs
[RP_REGNUM
] = fi
->pc_addr
;
1032 saved_regs_addr
->regs
[I7_REGNUM
] = fi
->fp_addr
;
1036 /* Normal frame. Just Local and In registers */
1037 frame_addr
= fi
->bottom
?
1038 fi
->bottom
: read_sp ();
1039 for (regnum
= L0_REGNUM
; regnum
< L0_REGNUM
+ 8; regnum
++)
1040 saved_regs_addr
->regs
[regnum
] =
1041 (frame_addr
+ (regnum
- L0_REGNUM
) * SPARC_INTREG_SIZE
1043 for (regnum
= I0_REGNUM
; regnum
< I0_REGNUM
+ 8; regnum
++)
1044 saved_regs_addr
->regs
[regnum
] =
1045 (frame_addr
+ (regnum
- I0_REGNUM
) * SPARC_INTREG_SIZE
1052 saved_regs_addr
->regs
[O7_REGNUM
] = fi
->pc_addr
;
1056 /* Pull off either the next frame pointer or the stack pointer */
1057 CORE_ADDR next_next_frame_addr
=
1061 for (regnum
= O0_REGNUM
; regnum
< O0_REGNUM
+ 8; regnum
++)
1062 saved_regs_addr
->regs
[regnum
] =
1063 (next_next_frame_addr
1064 + (regnum
- O0_REGNUM
) * SPARC_INTREG_SIZE
1068 /* Otherwise, whatever we would get from ptrace(GETREGS) is accurate */
1069 /* FIXME -- should this adjust for the sparc64 offset? */
1070 saved_regs_addr
->regs
[SP_REGNUM
] = FRAME_FP (fi
);
1073 /* Discard from the stack the innermost frame, restoring all saved registers.
1075 Note that the values stored in fsr by get_frame_saved_regs are *in
1076 the context of the called frame*. What this means is that the i
1077 regs of fsr must be restored into the o regs of the (calling) frame that
1078 we pop into. We don't care about the output regs of the calling frame,
1079 since unless it's a dummy frame, it won't have any output regs in it.
1081 We never have to bother with %l (local) regs, since the called routine's
1082 locals get tossed, and the calling routine's locals are already saved
1085 /* Definitely see tm-sparc.h for more doc of the frame format here. */
1090 register struct frame_info
*frame
= get_current_frame ();
1091 register CORE_ADDR pc
;
1092 struct frame_saved_regs fsr
;
1093 char raw_buffer
[REGISTER_BYTES
];
1096 sparc_frame_find_saved_regs (frame
, &fsr
);
1098 if (fsr
.regs
[FP0_REGNUM
])
1100 read_memory (fsr
.regs
[FP0_REGNUM
], raw_buffer
, FP_REGISTER_BYTES
);
1101 write_register_bytes (REGISTER_BYTE (FP0_REGNUM
),
1102 raw_buffer
, FP_REGISTER_BYTES
);
1104 #ifndef GDB_TARGET_IS_SPARC64
1105 if (fsr
.regs
[FPS_REGNUM
])
1107 read_memory (fsr
.regs
[FPS_REGNUM
], raw_buffer
, 4);
1108 write_register_bytes (REGISTER_BYTE (FPS_REGNUM
), raw_buffer
, 4);
1110 if (fsr
.regs
[CPS_REGNUM
])
1112 read_memory (fsr
.regs
[CPS_REGNUM
], raw_buffer
, 4);
1113 write_register_bytes (REGISTER_BYTE (CPS_REGNUM
), raw_buffer
, 4);
1116 #endif /* FP0_REGNUM */
1117 if (fsr
.regs
[G1_REGNUM
])
1119 read_memory (fsr
.regs
[G1_REGNUM
], raw_buffer
, 7 * SPARC_INTREG_SIZE
);
1120 write_register_bytes (REGISTER_BYTE (G1_REGNUM
), raw_buffer
,
1121 7 * SPARC_INTREG_SIZE
);
1126 /* Each register might or might not have been saved, need to test
1128 for (regnum
= L0_REGNUM
; regnum
< L0_REGNUM
+ 8; ++regnum
)
1129 if (fsr
.regs
[regnum
])
1130 write_register (regnum
, read_memory_integer (fsr
.regs
[regnum
],
1131 SPARC_INTREG_SIZE
));
1132 for (regnum
= I0_REGNUM
; regnum
< I0_REGNUM
+ 8; ++regnum
)
1133 if (fsr
.regs
[regnum
])
1134 write_register (regnum
, read_memory_integer (fsr
.regs
[regnum
],
1135 SPARC_INTREG_SIZE
));
1137 /* Handle all outs except stack pointer (o0-o5; o7). */
1138 for (regnum
= O0_REGNUM
; regnum
< O0_REGNUM
+ 6; ++regnum
)
1139 if (fsr
.regs
[regnum
])
1140 write_register (regnum
, read_memory_integer (fsr
.regs
[regnum
],
1141 SPARC_INTREG_SIZE
));
1142 if (fsr
.regs
[O0_REGNUM
+ 7])
1143 write_register (O0_REGNUM
+ 7,
1144 read_memory_integer (fsr
.regs
[O0_REGNUM
+ 7],
1145 SPARC_INTREG_SIZE
));
1147 write_sp (frame
->frame
);
1149 else if (fsr
.regs
[I0_REGNUM
])
1153 char reg_temp
[REGISTER_BYTES
];
1155 read_memory (fsr
.regs
[I0_REGNUM
], raw_buffer
, 8 * SPARC_INTREG_SIZE
);
1157 /* Get the ins and locals which we are about to restore. Just
1158 moving the stack pointer is all that is really needed, except
1159 store_inferior_registers is then going to write the ins and
1160 locals from the registers array, so we need to muck with the
1162 sp
= fsr
.regs
[SP_REGNUM
];
1163 #ifdef GDB_TARGET_IS_SPARC64
1167 read_memory (sp
, reg_temp
, SPARC_INTREG_SIZE
* 16);
1169 /* Restore the out registers.
1170 Among other things this writes the new stack pointer. */
1171 write_register_bytes (REGISTER_BYTE (O0_REGNUM
), raw_buffer
,
1172 SPARC_INTREG_SIZE
* 8);
1174 write_register_bytes (REGISTER_BYTE (L0_REGNUM
), reg_temp
,
1175 SPARC_INTREG_SIZE
* 16);
1177 #ifndef GDB_TARGET_IS_SPARC64
1178 if (fsr
.regs
[PS_REGNUM
])
1179 write_register (PS_REGNUM
, read_memory_integer (fsr
.regs
[PS_REGNUM
], 4));
1181 if (fsr
.regs
[Y_REGNUM
])
1182 write_register (Y_REGNUM
, read_memory_integer (fsr
.regs
[Y_REGNUM
], REGISTER_RAW_SIZE (Y_REGNUM
)));
1183 if (fsr
.regs
[PC_REGNUM
])
1185 /* Explicitly specified PC (and maybe NPC) -- just restore them. */
1186 write_register (PC_REGNUM
, read_memory_integer (fsr
.regs
[PC_REGNUM
],
1187 REGISTER_RAW_SIZE (PC_REGNUM
)));
1188 if (fsr
.regs
[NPC_REGNUM
])
1189 write_register (NPC_REGNUM
,
1190 read_memory_integer (fsr
.regs
[NPC_REGNUM
],
1191 REGISTER_RAW_SIZE (NPC_REGNUM
)));
1193 else if (frame
->flat
)
1196 pc
= PC_ADJUST ((CORE_ADDR
)
1197 read_memory_integer (frame
->pc_addr
,
1198 REGISTER_RAW_SIZE (PC_REGNUM
)));
1201 /* I think this happens only in the innermost frame, if so then
1202 it is a complicated way of saying
1203 "pc = read_register (O7_REGNUM);". */
1204 char buf
[MAX_REGISTER_RAW_SIZE
];
1205 get_saved_register (buf
, 0, 0, frame
, O7_REGNUM
, 0);
1206 pc
= PC_ADJUST (extract_address
1207 (buf
, REGISTER_RAW_SIZE (O7_REGNUM
)));
1210 write_register (PC_REGNUM
, pc
);
1211 write_register (NPC_REGNUM
, pc
+ 4);
1213 else if (fsr
.regs
[I7_REGNUM
])
1215 /* Return address in %i7 -- adjust it, then restore PC and NPC from it */
1216 pc
= PC_ADJUST ((CORE_ADDR
) read_memory_integer (fsr
.regs
[I7_REGNUM
],
1217 SPARC_INTREG_SIZE
));
1218 write_register (PC_REGNUM
, pc
);
1219 write_register (NPC_REGNUM
, pc
+ 4);
1221 flush_cached_frames ();
1224 /* On the Sun 4 under SunOS, the compile will leave a fake insn which
1225 encodes the structure size being returned. If we detect such
1226 a fake insn, step past it. */
1229 sparc_pc_adjust (pc
)
1236 err
= target_read_memory (pc
+ 8, buf
, 4);
1237 insn
= extract_unsigned_integer (buf
, 4);
1238 if ((err
== 0) && (insn
& 0xffc00000) == 0)
1244 /* If pc is in a shared library trampoline, return its target.
1245 The SunOs 4.x linker rewrites the jump table entries for PIC
1246 compiled modules in the main executable to bypass the dynamic linker
1247 with jumps of the form
1250 and removes the corresponding jump table relocation entry in the
1251 dynamic relocations.
1252 find_solib_trampoline_target relies on the presence of the jump
1253 table relocation entry, so we have to detect these jump instructions
1257 sunos4_skip_trampoline_code (pc
)
1260 unsigned long insn1
;
1264 err
= target_read_memory (pc
, buf
, 4);
1265 insn1
= extract_unsigned_integer (buf
, 4);
1266 if (err
== 0 && (insn1
& 0xffc00000) == 0x03000000)
1268 unsigned long insn2
;
1270 err
= target_read_memory (pc
+ 4, buf
, 4);
1271 insn2
= extract_unsigned_integer (buf
, 4);
1272 if (err
== 0 && (insn2
& 0xffffe000) == 0x81c06000)
1274 CORE_ADDR target_pc
= (insn1
& 0x3fffff) << 10;
1275 int delta
= insn2
& 0x1fff;
1277 /* Sign extend the displacement. */
1280 return target_pc
+ delta
;
1283 return find_solib_trampoline_target (pc
);
1286 #ifdef USE_PROC_FS /* Target dependent support for /proc */
1288 /* The /proc interface divides the target machine's register set up into
1289 two different sets, the general register set (gregset) and the floating
1290 point register set (fpregset). For each set, there is an ioctl to get
1291 the current register set and another ioctl to set the current values.
1293 The actual structure passed through the ioctl interface is, of course,
1294 naturally machine dependent, and is different for each set of registers.
1295 For the sparc for example, the general register set is typically defined
1298 typedef int gregset_t[38];
1304 and the floating point set by:
1306 typedef struct prfpregset {
1309 double pr_dregs[16];
1314 u_char pr_q_entrysize;
1319 These routines provide the packing and unpacking of gregset_t and
1320 fpregset_t formatted data.
1327 /* Given a pointer to a general register set in /proc format (gregset_t *),
1328 unpack the register contents and supply them as gdb's idea of the current
1332 supply_gregset (gregsetp
)
1333 prgregset_t
*gregsetp
;
1336 register prgreg_t
*regp
= (prgreg_t
*) gregsetp
;
1337 static char zerobuf
[MAX_REGISTER_RAW_SIZE
] =
1340 /* GDB register numbers for Gn, On, Ln, In all match /proc reg numbers. */
1341 for (regi
= G0_REGNUM
; regi
<= I7_REGNUM
; regi
++)
1343 supply_register (regi
, (char *) (regp
+ regi
));
1346 /* These require a bit more care. */
1347 supply_register (PS_REGNUM
, (char *) (regp
+ R_PS
));
1348 supply_register (PC_REGNUM
, (char *) (regp
+ R_PC
));
1349 supply_register (NPC_REGNUM
, (char *) (regp
+ R_nPC
));
1350 supply_register (Y_REGNUM
, (char *) (regp
+ R_Y
));
1352 /* Fill inaccessible registers with zero. */
1353 supply_register (WIM_REGNUM
, zerobuf
);
1354 supply_register (TBR_REGNUM
, zerobuf
);
1355 supply_register (CPS_REGNUM
, zerobuf
);
1359 fill_gregset (gregsetp
, regno
)
1360 prgregset_t
*gregsetp
;
1364 register prgreg_t
*regp
= (prgreg_t
*) gregsetp
;
1366 for (regi
= 0; regi
<= R_I7
; regi
++)
1368 if ((regno
== -1) || (regno
== regi
))
1370 *(regp
+ regi
) = *(int *) ®isters
[REGISTER_BYTE (regi
)];
1373 if ((regno
== -1) || (regno
== PS_REGNUM
))
1375 *(regp
+ R_PS
) = *(int *) ®isters
[REGISTER_BYTE (PS_REGNUM
)];
1377 if ((regno
== -1) || (regno
== PC_REGNUM
))
1379 *(regp
+ R_PC
) = *(int *) ®isters
[REGISTER_BYTE (PC_REGNUM
)];
1381 if ((regno
== -1) || (regno
== NPC_REGNUM
))
1383 *(regp
+ R_nPC
) = *(int *) ®isters
[REGISTER_BYTE (NPC_REGNUM
)];
1385 if ((regno
== -1) || (regno
== Y_REGNUM
))
1387 *(regp
+ R_Y
) = *(int *) ®isters
[REGISTER_BYTE (Y_REGNUM
)];
1391 #if defined (FP0_REGNUM)
1393 /* Given a pointer to a floating point register set in /proc format
1394 (fpregset_t *), unpack the register contents and supply them as gdb's
1395 idea of the current floating point register values. */
1398 supply_fpregset (fpregsetp
)
1399 prfpregset_t
*fpregsetp
;
1404 for (regi
= FP0_REGNUM
; regi
< FP_MAX_REGNUM
; regi
++)
1406 from
= (char *) &fpregsetp
->pr_fr
.pr_regs
[regi
- FP0_REGNUM
];
1407 supply_register (regi
, from
);
1409 supply_register (FPS_REGNUM
, (char *) &(fpregsetp
->pr_fsr
));
1412 /* Given a pointer to a floating point register set in /proc format
1413 (fpregset_t *), update the register specified by REGNO from gdb's idea
1414 of the current floating point register set. If REGNO is -1, update
1416 /* ??? This will probably need some changes for sparc64. */
1419 fill_fpregset (fpregsetp
, regno
)
1420 prfpregset_t
*fpregsetp
;
1427 for (regi
= FP0_REGNUM
; regi
< FP_MAX_REGNUM
; regi
++)
1429 if ((regno
== -1) || (regno
== regi
))
1431 from
= (char *) ®isters
[REGISTER_BYTE (regi
)];
1432 to
= (char *) &fpregsetp
->pr_fr
.pr_regs
[regi
- FP0_REGNUM
];
1433 memcpy (to
, from
, REGISTER_RAW_SIZE (regi
));
1436 if ((regno
== -1) || (regno
== FPS_REGNUM
))
1438 fpregsetp
->pr_fsr
= *(int *) ®isters
[REGISTER_BYTE (FPS_REGNUM
)];
1442 #endif /* defined (FP0_REGNUM) */
1444 #endif /* USE_PROC_FS */
1447 #ifdef GET_LONGJMP_TARGET
1449 /* Figure out where the longjmp will land. We expect that we have just entered
1450 longjmp and haven't yet setup the stack frame, so the args are still in the
1451 output regs. %o0 (O0_REGNUM) points at the jmp_buf structure from which we
1452 extract the pc (JB_PC) that we will land at. The pc is copied into ADDR.
1453 This routine returns true on success */
1456 get_longjmp_target (pc
)
1460 #define LONGJMP_TARGET_SIZE 4
1461 char buf
[LONGJMP_TARGET_SIZE
];
1463 jb_addr
= read_register (O0_REGNUM
);
1465 if (target_read_memory (jb_addr
+ JB_PC
* JB_ELEMENT_SIZE
, buf
,
1466 LONGJMP_TARGET_SIZE
))
1469 *pc
= extract_address (buf
, LONGJMP_TARGET_SIZE
);
1473 #endif /* GET_LONGJMP_TARGET */
1475 #ifdef STATIC_TRANSFORM_NAME
1476 /* SunPRO (3.0 at least), encodes the static variables. This is not
1477 related to C++ mangling, it is done for C too. */
1480 sunpro_static_transform_name (name
)
1486 /* For file-local statics there will be a dollar sign, a bunch
1487 of junk (the contents of which match a string given in the
1488 N_OPT), a period and the name. For function-local statics
1489 there will be a bunch of junk (which seems to change the
1490 second character from 'A' to 'B'), a period, the name of the
1491 function, and the name. So just skip everything before the
1493 p
= strrchr (name
, '.');
1499 #endif /* STATIC_TRANSFORM_NAME */
1502 /* Utilities for printing registers.
1503 Page numbers refer to the SPARC Architecture Manual. */
1505 static void dump_ccreg
PARAMS ((char *, int));
1508 dump_ccreg (reg
, val
)
1513 printf_unfiltered ("%s:%s,%s,%s,%s", reg
,
1514 val
& 8 ? "N" : "NN",
1515 val
& 4 ? "Z" : "NZ",
1516 val
& 2 ? "O" : "NO",
1517 val
& 1 ? "C" : "NC"
1529 return "ASI_NUCLEUS";
1531 return "ASI_NUCLEUS_LITTLE";
1533 return "ASI_AS_IF_USER_PRIMARY";
1535 return "ASI_AS_IF_USER_SECONDARY";
1537 return "ASI_AS_IF_USER_PRIMARY_LITTLE";
1539 return "ASI_AS_IF_USER_SECONDARY_LITTLE";
1541 return "ASI_PRIMARY";
1543 return "ASI_SECONDARY";
1545 return "ASI_PRIMARY_NOFAULT";
1547 return "ASI_SECONDARY_NOFAULT";
1549 return "ASI_PRIMARY_LITTLE";
1551 return "ASI_SECONDARY_LITTLE";
1553 return "ASI_PRIMARY_NOFAULT_LITTLE";
1555 return "ASI_SECONDARY_NOFAULT_LITTLE";
1561 /* PRINT_REGISTER_HOOK routine.
1562 Pretty print various registers. */
1563 /* FIXME: Would be nice if this did some fancy things for 32 bit sparc. */
1566 sparc_print_register_hook (regno
)
1571 /* Handle double/quad versions of lower 32 fp regs. */
1572 if (regno
>= FP0_REGNUM
&& regno
< FP0_REGNUM
+ 32
1573 && (regno
& 1) == 0)
1577 if (!read_relative_register_raw_bytes (regno
, value
)
1578 && !read_relative_register_raw_bytes (regno
+ 1, value
+ 4))
1580 printf_unfiltered ("\t");
1581 print_floating (value
, builtin_type_double
, gdb_stdout
);
1583 #if 0 /* FIXME: gdb doesn't handle long doubles */
1584 if ((regno
& 3) == 0)
1586 if (!read_relative_register_raw_bytes (regno
+ 2, value
+ 8)
1587 && !read_relative_register_raw_bytes (regno
+ 3, value
+ 12))
1589 printf_unfiltered ("\t");
1590 print_floating (value
, builtin_type_long_double
, gdb_stdout
);
1597 #if 0 /* FIXME: gdb doesn't handle long doubles */
1598 /* Print upper fp regs as long double if appropriate. */
1599 if (regno
>= FP0_REGNUM
+ 32 && regno
< FP_MAX_REGNUM
1600 /* We test for even numbered regs and not a multiple of 4 because
1601 the upper fp regs are recorded as doubles. */
1602 && (regno
& 1) == 0)
1606 if (!read_relative_register_raw_bytes (regno
, value
)
1607 && !read_relative_register_raw_bytes (regno
+ 1, value
+ 8))
1609 printf_unfiltered ("\t");
1610 print_floating (value
, builtin_type_long_double
, gdb_stdout
);
1616 /* FIXME: Some of these are priviledged registers.
1617 Not sure how they should be handled. */
1619 #define BITS(n, mask) ((int) (((val) >> (n)) & (mask)))
1621 val
= read_register (regno
);
1626 #ifdef GDB_TARGET_IS_SPARC64
1628 printf_unfiltered ("\t");
1629 dump_ccreg ("xcc", val
>> 4);
1630 printf_unfiltered (", ");
1631 dump_ccreg ("icc", val
& 15);
1634 printf ("\tfef:%d, du:%d, dl:%d",
1635 BITS (2, 1), BITS (1, 1), BITS (0, 1));
1639 static char *fcc
[4] =
1640 {"=", "<", ">", "?"};
1641 static char *rd
[4] =
1642 {"N", "0", "+", "-"};
1643 /* Long, yes, but I'd rather leave it as is and use a wide screen. */
1644 printf ("\t0:%s, 1:%s, 2:%s, 3:%s, rd:%s, tem:%d, ns:%d, ver:%d, ftt:%d, qne:%d, aexc:%d, cexc:%d",
1645 fcc
[BITS (10, 3)], fcc
[BITS (32, 3)],
1646 fcc
[BITS (34, 3)], fcc
[BITS (36, 3)],
1647 rd
[BITS (30, 3)], BITS (23, 31), BITS (22, 1), BITS (17, 7),
1648 BITS (14, 7), BITS (13, 1), BITS (5, 31), BITS (0, 31));
1653 char *asi
= decode_asi (val
);
1655 printf ("\t%s", asi
);
1659 printf ("\tmanuf:%d, impl:%d, mask:%d, maxtl:%d, maxwin:%d",
1660 BITS (48, 0xffff), BITS (32, 0xffff),
1661 BITS (24, 0xff), BITS (8, 0xff), BITS (0, 31));
1665 static char *mm
[4] =
1666 {"tso", "pso", "rso", "?"};
1667 printf ("\tcle:%d, tle:%d, mm:%s, red:%d, pef:%d, am:%d, priv:%d, ie:%d, ag:%d",
1668 BITS (9, 1), BITS (8, 1), mm
[BITS (6, 3)], BITS (5, 1),
1669 BITS (4, 1), BITS (3, 1), BITS (2, 1), BITS (1, 1),
1674 /* FIXME: print all 4? */
1677 /* FIXME: print all 4? */
1680 /* FIXME: print all 4? */
1683 /* FIXME: print all 4? */
1686 printf ("\tother:%d, normal:%d", BITS (3, 7), BITS (0, 7));
1689 printf ("\t%d", BITS (0, 31));
1691 case CANSAVE_REGNUM
:
1692 printf ("\t%-2d before spill", BITS (0, 31));
1694 case CANRESTORE_REGNUM
:
1695 printf ("\t%-2d before fill", BITS (0, 31));
1697 case CLEANWIN_REGNUM
:
1698 printf ("\t%-2d before clean", BITS (0, 31));
1700 case OTHERWIN_REGNUM
:
1701 printf ("\t%d", BITS (0, 31));
1705 printf ("\ticc:%c%c%c%c, pil:%d, s:%d, ps:%d, et:%d, cwp:%d",
1706 BITS (23, 1) ? 'N' : '-', BITS (22, 1) ? 'Z' : '-',
1707 BITS (21, 1) ? 'V' : '-', BITS (20, 1) ? 'C' : '-',
1708 BITS (8, 15), BITS (7, 1), BITS (6, 1), BITS (5, 1),
1713 static char *fcc
[4] =
1714 {"=", "<", ">", "?"};
1715 static char *rd
[4] =
1716 {"N", "0", "+", "-"};
1717 /* Long, yes, but I'd rather leave it as is and use a wide screen. */
1718 printf ("\trd:%s, tem:%d, ns:%d, ver:%d, ftt:%d, qne:%d, "
1719 "fcc:%s, aexc:%d, cexc:%d",
1720 rd
[BITS (30, 3)], BITS (23, 31), BITS (22, 1), BITS (17, 7),
1721 BITS (14, 7), BITS (13, 1), fcc
[BITS (10, 3)], BITS (5, 31),
1726 #endif /* GDB_TARGET_IS_SPARC64 */
1733 gdb_print_insn_sparc (memaddr
, info
)
1735 disassemble_info
*info
;
1737 /* It's necessary to override mach again because print_insn messes it up. */
1738 info
->mach
= TARGET_ARCHITECTURE
->mach
;
1739 return print_insn_sparc (memaddr
, info
);
1742 /* The SPARC passes the arguments on the stack; arguments smaller
1743 than an int are promoted to an int. */
1746 sparc_push_arguments (nargs
, args
, sp
, struct_return
, struct_addr
)
1751 CORE_ADDR struct_addr
;
1754 int accumulate_size
= 0;
1761 struct sparc_arg
*sparc_args
=
1762 (struct sparc_arg
*) alloca (nargs
* sizeof (struct sparc_arg
));
1763 struct sparc_arg
*m_arg
;
1765 /* Promote arguments if necessary, and calculate their stack offsets
1767 for (i
= 0, m_arg
= sparc_args
; i
< nargs
; i
++, m_arg
++)
1769 value_ptr arg
= args
[i
];
1770 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
1771 /* Cast argument to long if necessary as the compiler does it too. */
1772 switch (TYPE_CODE (arg_type
))
1775 case TYPE_CODE_BOOL
:
1776 case TYPE_CODE_CHAR
:
1777 case TYPE_CODE_RANGE
:
1778 case TYPE_CODE_ENUM
:
1779 if (TYPE_LENGTH (arg_type
) < TYPE_LENGTH (builtin_type_long
))
1781 arg_type
= builtin_type_long
;
1782 arg
= value_cast (arg_type
, arg
);
1788 m_arg
->len
= TYPE_LENGTH (arg_type
);
1789 m_arg
->offset
= accumulate_size
;
1790 accumulate_size
= (accumulate_size
+ m_arg
->len
+ 3) & ~3;
1791 m_arg
->contents
= VALUE_CONTENTS (arg
);
1794 /* Make room for the arguments on the stack. */
1795 accumulate_size
+= CALL_DUMMY_STACK_ADJUST
;
1796 sp
= ((sp
- accumulate_size
) & ~7) + CALL_DUMMY_STACK_ADJUST
;
1798 /* `Push' arguments on the stack. */
1799 for (i
= nargs
; m_arg
--, --i
>= 0;)
1800 write_memory (sp
+ m_arg
->offset
, m_arg
->contents
, m_arg
->len
);
1806 /* Extract from an array REGBUF containing the (raw) register state
1807 a function return value of type TYPE, and copy that, in virtual format,
1811 sparc_extract_return_value (type
, regbuf
, valbuf
)
1816 int typelen
= TYPE_LENGTH (type
);
1817 int regsize
= REGISTER_RAW_SIZE (O0_REGNUM
);
1819 if (TYPE_CODE (type
) == TYPE_CODE_FLT
&& SPARC_HAS_FPU
)
1820 memcpy (valbuf
, ®buf
[REGISTER_BYTE (FP0_REGNUM
)], typelen
);
1823 ®buf
[O0_REGNUM
* regsize
+
1825 || TARGET_BYTE_ORDER
== LITTLE_ENDIAN
? 0
1826 : regsize
- typelen
)],
1831 /* Write into appropriate registers a function return value
1832 of type TYPE, given in virtual format. On SPARCs with FPUs,
1833 float values are returned in %f0 (and %f1). In all other cases,
1834 values are returned in register %o0. */
1837 sparc_store_return_value (type
, valbuf
)
1842 char buffer
[MAX_REGISTER_RAW_SIZE
];
1844 if (TYPE_CODE (type
) == TYPE_CODE_FLT
&& SPARC_HAS_FPU
)
1845 /* Floating-point values are returned in the register pair */
1846 /* formed by %f0 and %f1 (doubles are, anyway). */
1849 /* Other values are returned in register %o0. */
1852 /* Add leading zeros to the value. */
1853 if (TYPE_LENGTH (type
) < REGISTER_RAW_SIZE (regno
))
1855 bzero (buffer
, REGISTER_RAW_SIZE (regno
));
1856 memcpy (buffer
+ REGISTER_RAW_SIZE (regno
) - TYPE_LENGTH (type
), valbuf
,
1857 TYPE_LENGTH (type
));
1858 write_register_bytes (REGISTER_BYTE (regno
), buffer
,
1859 REGISTER_RAW_SIZE (regno
));
1862 write_register_bytes (REGISTER_BYTE (regno
), valbuf
, TYPE_LENGTH (type
));
1866 /* Insert the function address into a call dummy instruction sequence
1869 For structs and unions, if the function was compiled with Sun cc,
1870 it expects 'unimp' after the call. But gcc doesn't use that
1871 (twisted) convention. So leave a nop there for gcc (FIX_CALL_DUMMY
1872 can assume it is operating on a pristine CALL_DUMMY, not one that
1873 has already been customized for a different function). */
1876 sparc_fix_call_dummy (dummy
, pc
, fun
, value_type
, using_gcc
)
1880 struct type
*value_type
;
1885 /* Store the relative adddress of the target function into the
1886 'call' instruction. */
1887 store_unsigned_integer (dummy
+ CALL_DUMMY_CALL_OFFSET
, 4,
1889 | (((fun
- (pc
+ CALL_DUMMY_CALL_OFFSET
)) >> 2)
1892 /* Comply with strange Sun cc calling convention for struct-returning
1895 && (TYPE_CODE (value_type
) == TYPE_CODE_STRUCT
1896 || TYPE_CODE (value_type
) == TYPE_CODE_UNION
))
1897 store_unsigned_integer (dummy
+ CALL_DUMMY_CALL_OFFSET
+ 8, 4,
1898 TYPE_LENGTH (value_type
) & 0x1fff);
1900 #ifndef GDB_TARGET_IS_SPARC64
1901 /* If this is not a simulator target, change the first four instructions
1902 of the call dummy to NOPs. Those instructions include a 'save'
1903 instruction and are designed to work around problems with register
1904 window flushing in the simulator. */
1905 if (strcmp (target_shortname
, "sim") != 0)
1907 for (i
= 0; i
< 4; i
++)
1908 store_unsigned_integer (dummy
+ (i
* 4), 4, 0x01000000);
1912 /* If this is a bi-endian target, GDB has written the call dummy
1913 in little-endian order. We must byte-swap it back to big-endian. */
1916 for (i
= 0; i
< CALL_DUMMY_LENGTH
; i
+= 4)
1918 char tmp
= dummy
[i
];
1919 dummy
[i
] = dummy
[i
+ 3];
1922 dummy
[i
+ 1] = dummy
[i
+ 2];
1929 /* Set target byte order based on machine type. */
1932 sparc_target_architecture_hook (ap
)
1933 const bfd_arch_info_type
*ap
;
1937 if (ap
->mach
== bfd_mach_sparc_sparclite_le
)
1939 if (TARGET_BYTE_ORDER_SELECTABLE_P
)
1941 target_byte_order
= LITTLE_ENDIAN
;
1946 warning ("This GDB does not support little endian sparclite.");
1956 _initialize_sparc_tdep ()
1958 tm_print_insn
= gdb_print_insn_sparc
;
1959 tm_print_insn_info
.mach
= TM_PRINT_INSN_MACH
; /* Selects sparc/sparclite */
1960 target_architecture_hook
= sparc_target_architecture_hook
;
1964 #ifdef GDB_TARGET_IS_SPARC64
1966 /* Compensate for stack bias. Note that we currently don't handle mixed
1971 CORE_ADDR sp
= read_register (SP_REGNUM
);
1981 CORE_ADDR fp
= read_register (FP_REGNUM
);
1989 sparc64_write_sp (val
)
1992 CORE_ADDR oldsp
= read_register (SP_REGNUM
);
1994 write_register (SP_REGNUM
, val
- 2047);
1996 write_register (SP_REGNUM
, val
);
2000 sparc64_write_fp (val
)
2003 CORE_ADDR oldfp
= read_register (FP_REGNUM
);
2005 write_register (FP_REGNUM
, val
- 2047);
2007 write_register (FP_REGNUM
, val
);
2010 /* The SPARC 64 ABI passes floating-point arguments in FP0-31. They are
2011 also copied onto the stack in the correct places. */
2014 sp64_push_arguments (nargs
, args
, sp
, struct_return
, struct_retaddr
)
2018 unsigned char struct_return
;
2019 CORE_ADDR struct_retaddr
;
2025 sp
= (sp
& ~(((unsigned long) TYPE_LENGTH (builtin_type_long
)) - 1UL));
2027 /* Figure out how much space we'll need. */
2028 for (x
= nargs
- 1; x
>= 0; x
--)
2030 int len
= TYPE_LENGTH (check_typedef (VALUE_TYPE (args
[x
])));
2031 value_ptr copyarg
= args
[x
];
2034 /* This code is, of course, no longer correct. */
2035 if (copylen
< TYPE_LENGTH (builtin_type_long
))
2037 copyarg
= value_cast (builtin_type_long
, copyarg
);
2038 copylen
= TYPE_LENGTH (builtin_type_long
);
2047 /* Now write the arguments onto the stack, while writing FP arguments
2048 into the FP registers. */
2049 for (x
= 0; x
< nargs
; x
++)
2051 int len
= TYPE_LENGTH (check_typedef (VALUE_TYPE (args
[x
])));
2052 value_ptr copyarg
= args
[x
];
2055 /* This code is, of course, no longer correct. */
2056 if (copylen
< TYPE_LENGTH (builtin_type_long
))
2058 copyarg
= value_cast (builtin_type_long
, copyarg
);
2059 copylen
= TYPE_LENGTH (builtin_type_long
);
2061 write_memory (tempsp
, VALUE_CONTENTS (copyarg
), copylen
);
2063 if (TYPE_CODE (VALUE_TYPE (args
[x
])) == TYPE_CODE_FLT
&& regnum
< 32)
2065 /* This gets copied into a FP register. */
2066 int nextreg
= regnum
+ 2;
2067 char *data
= VALUE_CONTENTS (args
[x
]);
2068 /* Floats go into the lower half of a FP register pair; quads
2076 write_register_bytes (REGISTER_BYTE (FP0_REGNUM
+ regnum
),
2085 /* Values <= 32 bytes are returned in o0-o3 (floating-point values are
2086 returned in f0-f3). */
2088 sparc64_extract_return_value (type
, regbuf
, valbuf
, bitoffset
)
2094 int typelen
= TYPE_LENGTH (type
);
2095 int regsize
= REGISTER_RAW_SIZE (O0_REGNUM
);
2097 if (TYPE_CODE (type
) == TYPE_CODE_FLT
&& SPARC_HAS_FPU
)
2099 memcpy (valbuf
, ®buf
[REGISTER_BYTE (FP0_REGNUM
)], typelen
);
2103 if (TYPE_CODE (type
) != TYPE_CODE_STRUCT
2104 || (TYPE_LENGTH (type
) > 32))
2107 ®buf
[O0_REGNUM
* regsize
+
2108 (typelen
>= regsize
? 0 : regsize
- typelen
)],
2114 char *o0
= ®buf
[O0_REGNUM
* regsize
];
2115 char *f0
= ®buf
[FP0_REGNUM
* regsize
];
2118 for (x
= 0; x
< TYPE_NFIELDS (type
); x
++)
2120 struct field
*f
= &TYPE_FIELDS (type
)[x
];
2121 /* FIXME: We may need to handle static fields here. */
2122 int whichreg
= (f
->loc
.bitpos
+ bitoffset
) / 32;
2123 int remainder
= ((f
->loc
.bitpos
+ bitoffset
) % 32) / 8;
2124 int where
= (f
->loc
.bitpos
+ bitoffset
) / 8;
2125 int size
= TYPE_LENGTH (f
->type
);
2126 int typecode
= TYPE_CODE (f
->type
);
2128 if (typecode
== TYPE_CODE_STRUCT
)
2130 sparc64_extract_return_value (f
->type
,
2133 bitoffset
+ f
->loc
.bitpos
);
2135 else if (typecode
== TYPE_CODE_FLT
)
2137 memcpy (valbuf
+ where
, &f0
[whichreg
* 4] + remainder
, size
);
2141 memcpy (valbuf
+ where
, &o0
[whichreg
* 4] + remainder
, size
);