1 /* Target-dependent code for SPARC.
3 Copyright (C) 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "arch-utils.h"
23 #include "dwarf2-frame.h"
24 #include "floatformat.h"
26 #include "frame-base.h"
27 #include "frame-unwind.h"
38 #include "gdb_assert.h"
39 #include "gdb_string.h"
41 #include "sparc-tdep.h"
45 /* This file implements the SPARC 32-bit ABI as defined by the section
46 "Low-Level System Information" of the SPARC Compliance Definition
47 (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC. The SCD
48 lists changes with respect to the original 32-bit psABI as defined
49 in the "System V ABI, SPARC Processor Supplement".
51 Note that if we talk about SunOS, we mean SunOS 4.x, which was
52 BSD-based, which is sometimes (retroactively?) referred to as
53 Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and
54 above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9
55 suffering from severe version number inflation). Solaris 2.x is
56 also known as SunOS 5.x, since that's what uname(1) says. Solaris
59 /* Please use the sparc32_-prefix for 32-bit specific code, the
60 sparc64_-prefix for 64-bit specific code and the sparc_-prefix for
61 code that can handle both. The 64-bit specific code lives in
62 sparc64-tdep.c; don't add any here. */
64 /* The SPARC Floating-Point Quad-Precision format is similar to
65 big-endian IA-64 Quad-recision format. */
66 #define floatformats_sparc_quad floatformats_ia64_quad
68 /* The stack pointer is offset from the stack frame by a BIAS of 2047
69 (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC
70 hosts, so undefine it first. */
74 /* Macros to extract fields from SPARC instructions. */
75 #define X_OP(i) (((i) >> 30) & 0x3)
76 #define X_RD(i) (((i) >> 25) & 0x1f)
77 #define X_A(i) (((i) >> 29) & 1)
78 #define X_COND(i) (((i) >> 25) & 0xf)
79 #define X_OP2(i) (((i) >> 22) & 0x7)
80 #define X_IMM22(i) ((i) & 0x3fffff)
81 #define X_OP3(i) (((i) >> 19) & 0x3f)
82 #define X_RS1(i) (((i) >> 14) & 0x1f)
83 #define X_RS2(i) ((i) & 0x1f)
84 #define X_I(i) (((i) >> 13) & 1)
85 /* Sign extension macros. */
86 #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000)
87 #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000)
88 #define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000)
90 /* Fetch the instruction at PC. Instructions are always big-endian
91 even if the processor operates in little-endian mode. */
94 sparc_fetch_instruction (CORE_ADDR pc
)
100 /* If we can't read the instruction at PC, return zero. */
101 if (read_memory_nobpt (pc
, buf
, sizeof (buf
)))
105 for (i
= 0; i
< sizeof (buf
); i
++)
106 insn
= (insn
<< 8) | buf
[i
];
111 /* Return non-zero if the instruction corresponding to PC is an "unimp"
115 sparc_is_unimp_insn (CORE_ADDR pc
)
117 const unsigned long insn
= sparc_fetch_instruction (pc
);
119 return ((insn
& 0xc1c00000) == 0);
122 /* OpenBSD/sparc includes StackGhost, which according to the author's
123 website http://stackghost.cerias.purdue.edu "... transparently and
124 automatically protects applications' stack frames; more
125 specifically, it guards the return pointers. The protection
126 mechanisms require no application source or binary modification and
127 imposes only a negligible performance penalty."
129 The same website provides the following description of how
132 "StackGhost interfaces with the kernel trap handler that would
133 normally write out registers to the stack and the handler that
134 would read them back in. By XORing a cookie into the
135 return-address saved in the user stack when it is actually written
136 to the stack, and then XOR it out when the return-address is pulled
137 from the stack, StackGhost can cause attacker corrupted return
138 pointers to behave in a manner the attacker cannot predict.
139 StackGhost can also use several unused bits in the return pointer
140 to detect a smashed return pointer and abort the process."
142 For GDB this means that whenever we're reading %i7 from a stack
143 frame's window save area, we'll have to XOR the cookie.
145 More information on StackGuard can be found on in:
147 Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated
148 Stack Protection." 2001. Published in USENIX Security Symposium
151 /* Fetch StackGhost Per-Process XOR cookie. */
154 sparc_fetch_wcookie (void)
156 struct target_ops
*ops
= ¤t_target
;
160 len
= target_read (ops
, TARGET_OBJECT_WCOOKIE
, NULL
, buf
, 0, 8);
164 /* We should have either an 32-bit or an 64-bit cookie. */
165 gdb_assert (len
== 4 || len
== 8);
167 return extract_unsigned_integer (buf
, len
);
171 /* The functions on this page are intended to be used to classify
172 function arguments. */
174 /* Check whether TYPE is "Integral or Pointer". */
177 sparc_integral_or_pointer_p (const struct type
*type
)
179 int len
= TYPE_LENGTH (type
);
181 switch (TYPE_CODE (type
))
187 case TYPE_CODE_RANGE
:
188 /* We have byte, half-word, word and extended-word/doubleword
189 integral types. The doubleword is an extension to the
190 original 32-bit ABI by the SCD 2.4.x. */
191 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
194 /* Allow either 32-bit or 64-bit pointers. */
195 return (len
== 4 || len
== 8);
203 /* Check whether TYPE is "Floating". */
206 sparc_floating_p (const struct type
*type
)
208 switch (TYPE_CODE (type
))
212 int len
= TYPE_LENGTH (type
);
213 return (len
== 4 || len
== 8 || len
== 16);
222 /* Check whether TYPE is "Structure or Union". */
225 sparc_structure_or_union_p (const struct type
*type
)
227 switch (TYPE_CODE (type
))
229 case TYPE_CODE_STRUCT
:
230 case TYPE_CODE_UNION
:
239 /* Register information. */
241 static const char *sparc32_register_names
[] =
243 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
244 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
245 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
246 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
248 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
249 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
250 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
251 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
253 "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr"
256 /* Total number of registers. */
257 #define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names)
259 /* We provide the aliases %d0..%d30 for the floating registers as
260 "psuedo" registers. */
262 static const char *sparc32_pseudo_register_names
[] =
264 "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14",
265 "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30"
268 /* Total number of pseudo registers. */
269 #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names)
271 /* Return the name of register REGNUM. */
274 sparc32_register_name (int regnum
)
276 if (regnum
>= 0 && regnum
< SPARC32_NUM_REGS
)
277 return sparc32_register_names
[regnum
];
279 if (regnum
< SPARC32_NUM_REGS
+ SPARC32_NUM_PSEUDO_REGS
)
280 return sparc32_pseudo_register_names
[regnum
- SPARC32_NUM_REGS
];
287 struct type
*sparc_psr_type
;
290 struct type
*sparc_fsr_type
;
292 /* Construct types for ISA-specific registers. */
295 sparc_init_types (void)
299 type
= init_flags_type ("builtin_type_sparc_psr", 4);
300 append_flags_type_flag (type
, 5, "ET");
301 append_flags_type_flag (type
, 6, "PS");
302 append_flags_type_flag (type
, 7, "S");
303 append_flags_type_flag (type
, 12, "EF");
304 append_flags_type_flag (type
, 13, "EC");
305 sparc_psr_type
= type
;
307 type
= init_flags_type ("builtin_type_sparc_fsr", 4);
308 append_flags_type_flag (type
, 0, "NXA");
309 append_flags_type_flag (type
, 1, "DZA");
310 append_flags_type_flag (type
, 2, "UFA");
311 append_flags_type_flag (type
, 3, "OFA");
312 append_flags_type_flag (type
, 4, "NVA");
313 append_flags_type_flag (type
, 5, "NXC");
314 append_flags_type_flag (type
, 6, "DZC");
315 append_flags_type_flag (type
, 7, "UFC");
316 append_flags_type_flag (type
, 8, "OFC");
317 append_flags_type_flag (type
, 9, "NVC");
318 append_flags_type_flag (type
, 22, "NS");
319 append_flags_type_flag (type
, 23, "NXM");
320 append_flags_type_flag (type
, 24, "DZM");
321 append_flags_type_flag (type
, 25, "UFM");
322 append_flags_type_flag (type
, 26, "OFM");
323 append_flags_type_flag (type
, 27, "NVM");
324 sparc_fsr_type
= type
;
327 /* Return the GDB type object for the "standard" data type of data in
331 sparc32_register_type (struct gdbarch
*gdbarch
, int regnum
)
333 if (regnum
>= SPARC_F0_REGNUM
&& regnum
<= SPARC_F31_REGNUM
)
334 return builtin_type_float
;
336 if (regnum
>= SPARC32_D0_REGNUM
&& regnum
<= SPARC32_D30_REGNUM
)
337 return builtin_type_double
;
339 if (regnum
== SPARC_SP_REGNUM
|| regnum
== SPARC_FP_REGNUM
)
340 return builtin_type_void_data_ptr
;
342 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== SPARC32_NPC_REGNUM
)
343 return builtin_type_void_func_ptr
;
345 if (regnum
== SPARC32_PSR_REGNUM
)
346 return sparc_psr_type
;
348 if (regnum
== SPARC32_FSR_REGNUM
)
349 return sparc_fsr_type
;
351 return builtin_type_int32
;
355 sparc32_pseudo_register_read (struct gdbarch
*gdbarch
,
356 struct regcache
*regcache
,
357 int regnum
, gdb_byte
*buf
)
359 gdb_assert (regnum
>= SPARC32_D0_REGNUM
&& regnum
<= SPARC32_D30_REGNUM
);
361 regnum
= SPARC_F0_REGNUM
+ 2 * (regnum
- SPARC32_D0_REGNUM
);
362 regcache_raw_read (regcache
, regnum
, buf
);
363 regcache_raw_read (regcache
, regnum
+ 1, buf
+ 4);
367 sparc32_pseudo_register_write (struct gdbarch
*gdbarch
,
368 struct regcache
*regcache
,
369 int regnum
, const gdb_byte
*buf
)
371 gdb_assert (regnum
>= SPARC32_D0_REGNUM
&& regnum
<= SPARC32_D30_REGNUM
);
373 regnum
= SPARC_F0_REGNUM
+ 2 * (regnum
- SPARC32_D0_REGNUM
);
374 regcache_raw_write (regcache
, regnum
, buf
);
375 regcache_raw_write (regcache
, regnum
+ 1, buf
+ 4);
380 sparc32_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
381 CORE_ADDR funcaddr
, int using_gcc
,
382 struct value
**args
, int nargs
,
383 struct type
*value_type
,
384 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
385 struct regcache
*regcache
)
390 if (using_struct_return (value_type
, using_gcc
))
394 /* This is an UNIMP instruction. */
395 store_unsigned_integer (buf
, 4, TYPE_LENGTH (value_type
) & 0x1fff);
396 write_memory (sp
- 8, buf
, 4);
404 sparc32_store_arguments (struct regcache
*regcache
, int nargs
,
405 struct value
**args
, CORE_ADDR sp
,
406 int struct_return
, CORE_ADDR struct_addr
)
408 /* Number of words in the "parameter array". */
409 int num_elements
= 0;
413 for (i
= 0; i
< nargs
; i
++)
415 struct type
*type
= value_type (args
[i
]);
416 int len
= TYPE_LENGTH (type
);
418 if (sparc_structure_or_union_p (type
)
419 || (sparc_floating_p (type
) && len
== 16))
421 /* Structure, Union and Quad-Precision Arguments. */
424 /* Use doubleword alignment for these values. That's always
425 correct, and wasting a few bytes shouldn't be a problem. */
428 write_memory (sp
, value_contents (args
[i
]), len
);
429 args
[i
] = value_from_pointer (lookup_pointer_type (type
), sp
);
432 else if (sparc_floating_p (type
))
434 /* Floating arguments. */
435 gdb_assert (len
== 4 || len
== 8);
436 num_elements
+= (len
/ 4);
440 /* Integral and pointer arguments. */
441 gdb_assert (sparc_integral_or_pointer_p (type
));
444 args
[i
] = value_cast (builtin_type_int32
, args
[i
]);
445 num_elements
+= ((len
+ 3) / 4);
449 /* Always allocate at least six words. */
450 sp
-= max (6, num_elements
) * 4;
452 /* The psABI says that "Software convention requires space for the
453 struct/union return value pointer, even if the word is unused." */
456 /* The psABI says that "Although software convention and the
457 operating system require every stack frame to be doubleword
461 for (i
= 0; i
< nargs
; i
++)
463 const bfd_byte
*valbuf
= value_contents (args
[i
]);
464 struct type
*type
= value_type (args
[i
]);
465 int len
= TYPE_LENGTH (type
);
467 gdb_assert (len
== 4 || len
== 8);
471 int regnum
= SPARC_O0_REGNUM
+ element
;
473 regcache_cooked_write (regcache
, regnum
, valbuf
);
474 if (len
> 4 && element
< 5)
475 regcache_cooked_write (regcache
, regnum
+ 1, valbuf
+ 4);
478 /* Always store the argument in memory. */
479 write_memory (sp
+ 4 + element
* 4, valbuf
, len
);
483 gdb_assert (element
== num_elements
);
489 store_unsigned_integer (buf
, 4, struct_addr
);
490 write_memory (sp
, buf
, 4);
497 sparc32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
498 struct regcache
*regcache
, CORE_ADDR bp_addr
,
499 int nargs
, struct value
**args
, CORE_ADDR sp
,
500 int struct_return
, CORE_ADDR struct_addr
)
502 CORE_ADDR call_pc
= (struct_return
? (bp_addr
- 12) : (bp_addr
- 8));
504 /* Set return address. */
505 regcache_cooked_write_unsigned (regcache
, SPARC_O7_REGNUM
, call_pc
);
507 /* Set up function arguments. */
508 sp
= sparc32_store_arguments (regcache
, nargs
, args
, sp
,
509 struct_return
, struct_addr
);
511 /* Allocate the 16-word window save area. */
514 /* Stack should be doubleword aligned at this point. */
515 gdb_assert (sp
% 8 == 0);
517 /* Finally, update the stack pointer. */
518 regcache_cooked_write_unsigned (regcache
, SPARC_SP_REGNUM
, sp
);
524 /* Use the program counter to determine the contents and size of a
525 breakpoint instruction. Return a pointer to a string of bytes that
526 encode a breakpoint instruction, store the length of the string in
527 *LEN and optionally adjust *PC to point to the correct memory
528 location for inserting the breakpoint. */
530 static const gdb_byte
*
531 sparc_breakpoint_from_pc (CORE_ADDR
*pc
, int *len
)
533 static const gdb_byte break_insn
[] = { 0x91, 0xd0, 0x20, 0x01 };
535 *len
= sizeof (break_insn
);
540 /* Allocate and initialize a frame cache. */
542 static struct sparc_frame_cache
*
543 sparc_alloc_frame_cache (void)
545 struct sparc_frame_cache
*cache
;
548 cache
= FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache
);
554 /* Frameless until proven otherwise. */
555 cache
->frameless_p
= 1;
557 cache
->struct_return_p
= 0;
562 /* GCC generates several well-known sequences of instructions at the begining
563 of each function prologue when compiling with -fstack-check. If one of
564 such sequences starts at START_PC, then return the address of the
565 instruction immediately past this sequence. Otherwise, return START_PC. */
568 sparc_skip_stack_check (const CORE_ADDR start_pc
)
570 CORE_ADDR pc
= start_pc
;
572 int offset_stack_checking_sequence
= 0;
574 /* With GCC, all stack checking sequences begin with the same two
577 /* sethi <some immediate>,%g1 */
578 insn
= sparc_fetch_instruction (pc
);
580 if (!(X_OP (insn
) == 0 && X_OP2 (insn
) == 0x4 && X_RD (insn
) == 1))
583 /* sub %sp, %g1, %g1 */
584 insn
= sparc_fetch_instruction (pc
);
586 if (!(X_OP (insn
) == 2 && X_OP3 (insn
) == 0x4 && !X_I(insn
)
587 && X_RD (insn
) == 1 && X_RS1 (insn
) == 14 && X_RS2 (insn
) == 1))
590 insn
= sparc_fetch_instruction (pc
);
593 /* First possible sequence:
594 [first two instructions above]
595 clr [%g1 - some immediate] */
597 /* clr [%g1 - some immediate] */
598 if (X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && X_I(insn
)
599 && X_RS1 (insn
) == 1 && X_RD (insn
) == 0)
601 /* Valid stack-check sequence, return the new PC. */
605 /* Second possible sequence: A small number of probes.
606 [first two instructions above]
608 add %g1, -<some immediate>, %g1
610 [repeat the two instructions above any (small) number of times]
611 clr [%g1 - some immediate] */
614 else if (X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && !X_I(insn
)
615 && X_RS1 (insn
) == 1 && X_RD (insn
) == 0)
619 /* add %g1, -<some immediate>, %g1 */
620 insn
= sparc_fetch_instruction (pc
);
622 if (!(X_OP (insn
) == 2 && X_OP3(insn
) == 0 && X_I(insn
)
623 && X_RS1 (insn
) == 1 && X_RD (insn
) == 1))
627 insn
= sparc_fetch_instruction (pc
);
629 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && !X_I(insn
)
630 && X_RD (insn
) == 0 && X_RS1 (insn
) == 1))
634 /* clr [%g1 - some immediate] */
635 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && X_I(insn
)
636 && X_RS1 (insn
) == 1 && X_RD (insn
) == 0))
639 /* We found a valid stack-check sequence, return the new PC. */
643 /* Third sequence: A probing loop.
644 [first two instructions above]
645 sethi <some immediate>, %g4
649 add %g1, -<some immediate>, %g1
652 clr [%g4 - some immediate] */
654 /* sethi <some immediate>, %g4 */
655 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 0x4 && X_RD (insn
) == 4)
657 /* sub %g1, %g4, %g4 */
658 insn
= sparc_fetch_instruction (pc
);
660 if (!(X_OP (insn
) == 2 && X_OP3 (insn
) == 0x4 && !X_I(insn
)
661 && X_RD (insn
) == 4 && X_RS1 (insn
) == 1 && X_RS2 (insn
) == 4))
665 insn
= sparc_fetch_instruction (pc
);
667 if (!(X_OP (insn
) == 2 && X_OP3 (insn
) == 0x14 && !X_I(insn
)
668 && X_RD (insn
) == 0 && X_RS1 (insn
) == 1 && X_RS2 (insn
) == 4))
672 insn
= sparc_fetch_instruction (pc
);
674 if (!(X_OP (insn
) == 0 && X_COND (insn
) == 0x1))
677 /* add %g1, -<some immediate>, %g1 */
678 insn
= sparc_fetch_instruction (pc
);
680 if (!(X_OP (insn
) == 2 && X_OP3(insn
) == 0 && X_I(insn
)
681 && X_RS1 (insn
) == 1 && X_RD (insn
) == 1))
685 insn
= sparc_fetch_instruction (pc
);
687 if (!(X_OP (insn
) == 0 && X_COND (insn
) == 0x8))
691 insn
= sparc_fetch_instruction (pc
);
693 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && !X_I(insn
)
694 && X_RD (insn
) == 0 && X_RS1 (insn
) == 1))
697 /* clr [%g4 - some immediate] */
698 insn
= sparc_fetch_instruction (pc
);
700 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && X_I(insn
)
701 && X_RS1 (insn
) == 4 && X_RD (insn
) == 0))
704 /* We found a valid stack-check sequence, return the new PC. */
708 /* No stack check code in our prologue, return the start_pc. */
713 sparc_analyze_prologue (CORE_ADDR pc
, CORE_ADDR current_pc
,
714 struct sparc_frame_cache
*cache
)
716 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
721 pc
= sparc_skip_stack_check (pc
);
723 if (current_pc
<= pc
)
726 /* We have to handle to "Procedure Linkage Table" (PLT) special. On
727 SPARC the linker usually defines a symbol (typically
728 _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section.
729 This symbol makes us end up here with PC pointing at the start of
730 the PLT and CURRENT_PC probably pointing at a PLT entry. If we
731 would do our normal prologue analysis, we would probably conclude
732 that we've got a frame when in reality we don't, since the
733 dynamic linker patches up the first PLT with some code that
734 starts with a SAVE instruction. Patch up PC such that it points
735 at the start of our PLT entry. */
736 if (tdep
->plt_entry_size
> 0 && in_plt_section (current_pc
, NULL
))
737 pc
= current_pc
- ((current_pc
- pc
) % tdep
->plt_entry_size
);
739 insn
= sparc_fetch_instruction (pc
);
741 /* Recognize a SETHI insn and record its destination. */
742 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 0x04)
747 insn
= sparc_fetch_instruction (pc
+ 4);
750 /* Allow for an arithmetic operation on DEST or %g1. */
751 if (X_OP (insn
) == 2 && X_I (insn
)
752 && (X_RD (insn
) == 1 || X_RD (insn
) == dest
))
756 insn
= sparc_fetch_instruction (pc
+ 8);
759 /* Check for the SAVE instruction that sets up the frame. */
760 if (X_OP (insn
) == 2 && X_OP3 (insn
) == 0x3c)
762 cache
->frameless_p
= 0;
763 return pc
+ offset
+ 4;
770 sparc_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
772 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
773 return frame_unwind_register_unsigned (next_frame
, tdep
->pc_regnum
);
776 /* Return PC of first real instruction of the function starting at
780 sparc32_skip_prologue (CORE_ADDR start_pc
)
782 struct symtab_and_line sal
;
783 CORE_ADDR func_start
, func_end
;
784 struct sparc_frame_cache cache
;
786 /* This is the preferred method, find the end of the prologue by
787 using the debugging information. */
788 if (find_pc_partial_function (start_pc
, NULL
, &func_start
, &func_end
))
790 sal
= find_pc_line (func_start
, 0);
792 if (sal
.end
< func_end
793 && start_pc
<= sal
.end
)
797 start_pc
= sparc_analyze_prologue (start_pc
, 0xffffffffUL
, &cache
);
799 /* The psABI says that "Although the first 6 words of arguments
800 reside in registers, the standard stack frame reserves space for
801 them.". It also suggests that a function may use that space to
802 "write incoming arguments 0 to 5" into that space, and that's
803 indeed what GCC seems to be doing. In that case GCC will
804 generate debug information that points to the stack slots instead
805 of the registers, so we should consider the instructions that
806 write out these incoming arguments onto the stack. Of course we
807 only need to do this if we have a stack frame. */
809 while (!cache
.frameless_p
)
811 unsigned long insn
= sparc_fetch_instruction (start_pc
);
813 /* Recognize instructions that store incoming arguments in
814 %i0...%i5 into the corresponding stack slot. */
815 if (X_OP (insn
) == 3 && (X_OP3 (insn
) & 0x3c) == 0x04 && X_I (insn
)
816 && (X_RD (insn
) >= 24 && X_RD (insn
) <= 29) && X_RS1 (insn
) == 30
817 && X_SIMM13 (insn
) == 68 + (X_RD (insn
) - 24) * 4)
831 struct sparc_frame_cache
*
832 sparc_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
834 struct sparc_frame_cache
*cache
;
839 cache
= sparc_alloc_frame_cache ();
842 cache
->pc
= frame_func_unwind (next_frame
, NORMAL_FRAME
);
844 sparc_analyze_prologue (cache
->pc
, frame_pc_unwind (next_frame
), cache
);
846 if (cache
->frameless_p
)
848 /* This function is frameless, so %fp (%i6) holds the frame
849 pointer for our calling frame. Use %sp (%o6) as this frame's
852 frame_unwind_register_unsigned (next_frame
, SPARC_SP_REGNUM
);
856 /* For normal frames, %fp (%i6) holds the frame pointer, the
857 base address for the current stack frame. */
859 frame_unwind_register_unsigned (next_frame
, SPARC_FP_REGNUM
);
869 sparc32_struct_return_from_sym (struct symbol
*sym
)
871 struct type
*type
= check_typedef (SYMBOL_TYPE (sym
));
872 enum type_code code
= TYPE_CODE (type
);
874 if (code
== TYPE_CODE_FUNC
|| code
== TYPE_CODE_METHOD
)
876 type
= check_typedef (TYPE_TARGET_TYPE (type
));
877 if (sparc_structure_or_union_p (type
)
878 || (sparc_floating_p (type
) && TYPE_LENGTH (type
) == 16))
885 struct sparc_frame_cache
*
886 sparc32_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
888 struct sparc_frame_cache
*cache
;
894 cache
= sparc_frame_cache (next_frame
, this_cache
);
896 sym
= find_pc_function (cache
->pc
);
899 cache
->struct_return_p
= sparc32_struct_return_from_sym (sym
);
903 /* There is no debugging information for this function to
904 help us determine whether this function returns a struct
905 or not. So we rely on another heuristic which is to check
906 the instruction at the return address and see if this is
907 an "unimp" instruction. If it is, then it is a struct-return
910 int regnum
= cache
->frameless_p
? SPARC_O7_REGNUM
: SPARC_I7_REGNUM
;
912 pc
= frame_unwind_register_unsigned (next_frame
, regnum
) + 8;
913 if (sparc_is_unimp_insn (pc
))
914 cache
->struct_return_p
= 1;
921 sparc32_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
922 struct frame_id
*this_id
)
924 struct sparc_frame_cache
*cache
=
925 sparc32_frame_cache (next_frame
, this_cache
);
927 /* This marks the outermost frame. */
928 if (cache
->base
== 0)
931 (*this_id
) = frame_id_build (cache
->base
, cache
->pc
);
935 sparc32_frame_prev_register (struct frame_info
*next_frame
, void **this_cache
,
936 int regnum
, int *optimizedp
,
937 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
938 int *realnump
, gdb_byte
*valuep
)
940 struct sparc_frame_cache
*cache
=
941 sparc32_frame_cache (next_frame
, this_cache
);
943 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== SPARC32_NPC_REGNUM
)
951 CORE_ADDR pc
= (regnum
== SPARC32_NPC_REGNUM
) ? 4 : 0;
953 /* If this functions has a Structure, Union or
954 Quad-Precision return value, we have to skip the UNIMP
955 instruction that encodes the size of the structure. */
956 if (cache
->struct_return_p
)
959 regnum
= cache
->frameless_p
? SPARC_O7_REGNUM
: SPARC_I7_REGNUM
;
960 pc
+= frame_unwind_register_unsigned (next_frame
, regnum
) + 8;
961 store_unsigned_integer (valuep
, 4, pc
);
966 /* Handle StackGhost. */
968 ULONGEST wcookie
= sparc_fetch_wcookie ();
970 if (wcookie
!= 0 && !cache
->frameless_p
&& regnum
== SPARC_I7_REGNUM
)
978 CORE_ADDR addr
= cache
->base
+ (regnum
- SPARC_L0_REGNUM
) * 4;
981 /* Read the value in from memory. */
982 i7
= get_frame_memory_unsigned (next_frame
, addr
, 4);
983 store_unsigned_integer (valuep
, 4, i7
^ wcookie
);
989 /* The previous frame's `local' and `in' registers have been saved
990 in the register save area. */
991 if (!cache
->frameless_p
992 && regnum
>= SPARC_L0_REGNUM
&& regnum
<= SPARC_I7_REGNUM
)
995 *lvalp
= lval_memory
;
996 *addrp
= cache
->base
+ (regnum
- SPARC_L0_REGNUM
) * 4;
1000 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
1002 /* Read the value in from memory. */
1003 read_memory (*addrp
, valuep
, register_size (gdbarch
, regnum
));
1008 /* The previous frame's `out' registers are accessable as the
1009 current frame's `in' registers. */
1010 if (!cache
->frameless_p
1011 && regnum
>= SPARC_O0_REGNUM
&& regnum
<= SPARC_O7_REGNUM
)
1012 regnum
+= (SPARC_I0_REGNUM
- SPARC_O0_REGNUM
);
1015 *lvalp
= lval_register
;
1019 frame_unwind_register (next_frame
, (*realnump
), valuep
);
1022 static const struct frame_unwind sparc32_frame_unwind
=
1025 sparc32_frame_this_id
,
1026 sparc32_frame_prev_register
1029 static const struct frame_unwind
*
1030 sparc32_frame_sniffer (struct frame_info
*next_frame
)
1032 return &sparc32_frame_unwind
;
1037 sparc32_frame_base_address (struct frame_info
*next_frame
, void **this_cache
)
1039 struct sparc_frame_cache
*cache
=
1040 sparc32_frame_cache (next_frame
, this_cache
);
1045 static const struct frame_base sparc32_frame_base
=
1047 &sparc32_frame_unwind
,
1048 sparc32_frame_base_address
,
1049 sparc32_frame_base_address
,
1050 sparc32_frame_base_address
1053 static struct frame_id
1054 sparc_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1058 sp
= frame_unwind_register_unsigned (next_frame
, SPARC_SP_REGNUM
);
1061 return frame_id_build (sp
, frame_pc_unwind (next_frame
));
1065 /* Extract from an array REGBUF containing the (raw) register state, a
1066 function return value of TYPE, and copy that into VALBUF. */
1069 sparc32_extract_return_value (struct type
*type
, struct regcache
*regcache
,
1072 int len
= TYPE_LENGTH (type
);
1075 gdb_assert (!sparc_structure_or_union_p (type
));
1076 gdb_assert (!(sparc_floating_p (type
) && len
== 16));
1078 if (sparc_floating_p (type
))
1080 /* Floating return values. */
1081 regcache_cooked_read (regcache
, SPARC_F0_REGNUM
, buf
);
1083 regcache_cooked_read (regcache
, SPARC_F1_REGNUM
, buf
+ 4);
1084 memcpy (valbuf
, buf
, len
);
1088 /* Integral and pointer return values. */
1089 gdb_assert (sparc_integral_or_pointer_p (type
));
1091 regcache_cooked_read (regcache
, SPARC_O0_REGNUM
, buf
);
1094 regcache_cooked_read (regcache
, SPARC_O1_REGNUM
, buf
+ 4);
1095 gdb_assert (len
== 8);
1096 memcpy (valbuf
, buf
, 8);
1100 /* Just stripping off any unused bytes should preserve the
1101 signed-ness just fine. */
1102 memcpy (valbuf
, buf
+ 4 - len
, len
);
1107 /* Write into the appropriate registers a function return value stored
1108 in VALBUF of type TYPE. */
1111 sparc32_store_return_value (struct type
*type
, struct regcache
*regcache
,
1112 const gdb_byte
*valbuf
)
1114 int len
= TYPE_LENGTH (type
);
1117 gdb_assert (!sparc_structure_or_union_p (type
));
1118 gdb_assert (!(sparc_floating_p (type
) && len
== 16));
1120 if (sparc_floating_p (type
))
1122 /* Floating return values. */
1123 memcpy (buf
, valbuf
, len
);
1124 regcache_cooked_write (regcache
, SPARC_F0_REGNUM
, buf
);
1126 regcache_cooked_write (regcache
, SPARC_F1_REGNUM
, buf
+ 4);
1130 /* Integral and pointer return values. */
1131 gdb_assert (sparc_integral_or_pointer_p (type
));
1135 gdb_assert (len
== 8);
1136 memcpy (buf
, valbuf
, 8);
1137 regcache_cooked_write (regcache
, SPARC_O1_REGNUM
, buf
+ 4);
1141 /* ??? Do we need to do any sign-extension here? */
1142 memcpy (buf
+ 4 - len
, valbuf
, len
);
1144 regcache_cooked_write (regcache
, SPARC_O0_REGNUM
, buf
);
1148 static enum return_value_convention
1149 sparc32_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
1150 struct regcache
*regcache
, gdb_byte
*readbuf
,
1151 const gdb_byte
*writebuf
)
1153 /* The psABI says that "...every stack frame reserves the word at
1154 %fp+64. If a function returns a structure, union, or
1155 quad-precision value, this word should hold the address of the
1156 object into which the return value should be copied." This
1157 guarantees that we can always find the return value, not just
1158 before the function returns. */
1160 if (sparc_structure_or_union_p (type
)
1161 || (sparc_floating_p (type
) && TYPE_LENGTH (type
) == 16))
1168 regcache_cooked_read_unsigned (regcache
, SPARC_SP_REGNUM
, &sp
);
1169 addr
= read_memory_unsigned_integer (sp
+ 64, 4);
1170 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
1173 return RETURN_VALUE_ABI_PRESERVES_ADDRESS
;
1177 sparc32_extract_return_value (type
, regcache
, readbuf
);
1179 sparc32_store_return_value (type
, regcache
, writebuf
);
1181 return RETURN_VALUE_REGISTER_CONVENTION
;
1185 sparc32_stabs_argument_has_addr (struct gdbarch
*gdbarch
, struct type
*type
)
1187 return (sparc_structure_or_union_p (type
)
1188 || (sparc_floating_p (type
) && TYPE_LENGTH (type
) == 16));
1192 sparc32_dwarf2_struct_return_p (struct frame_info
*next_frame
)
1194 CORE_ADDR pc
= frame_unwind_address_in_block (next_frame
, NORMAL_FRAME
);
1195 struct symbol
*sym
= find_pc_function (pc
);
1198 return sparc32_struct_return_from_sym (sym
);
1203 sparc32_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1204 struct dwarf2_frame_state_reg
*reg
,
1205 struct frame_info
*next_frame
)
1211 case SPARC_G0_REGNUM
:
1212 /* Since %g0 is always zero, there is no point in saving it, and
1213 people will be inclined omit it from the CFI. Make sure we
1214 don't warn about that. */
1215 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
1217 case SPARC_SP_REGNUM
:
1218 reg
->how
= DWARF2_FRAME_REG_CFA
;
1220 case SPARC32_PC_REGNUM
:
1221 case SPARC32_NPC_REGNUM
:
1222 reg
->how
= DWARF2_FRAME_REG_RA_OFFSET
;
1224 if (sparc32_dwarf2_struct_return_p (next_frame
))
1226 if (regnum
== SPARC32_NPC_REGNUM
)
1228 reg
->loc
.offset
= off
;
1234 /* The SPARC Architecture doesn't have hardware single-step support,
1235 and most operating systems don't implement it either, so we provide
1236 software single-step mechanism. */
1239 sparc_analyze_control_transfer (struct frame_info
*frame
,
1240 CORE_ADDR pc
, CORE_ADDR
*npc
)
1242 unsigned long insn
= sparc_fetch_instruction (pc
);
1243 int conditional_p
= X_COND (insn
) & 0x7;
1245 long offset
= 0; /* Must be signed for sign-extend. */
1247 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 3 && (insn
& 0x1000000) == 0)
1249 /* Branch on Integer Register with Prediction (BPr). */
1253 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 6)
1255 /* Branch on Floating-Point Condition Codes (FBfcc). */
1257 offset
= 4 * X_DISP22 (insn
);
1259 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 5)
1261 /* Branch on Floating-Point Condition Codes with Prediction
1264 offset
= 4 * X_DISP19 (insn
);
1266 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 2)
1268 /* Branch on Integer Condition Codes (Bicc). */
1270 offset
= 4 * X_DISP22 (insn
);
1272 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 1)
1274 /* Branch on Integer Condition Codes with Prediction (BPcc). */
1276 offset
= 4 * X_DISP19 (insn
);
1278 else if (X_OP (insn
) == 2 && X_OP3 (insn
) == 0x3a)
1280 /* Trap instruction (TRAP). */
1281 return gdbarch_tdep (get_frame_arch (frame
))->step_trap (frame
, insn
);
1284 /* FIXME: Handle DONE and RETRY instructions. */
1290 /* For conditional branches, return nPC + 4 iff the annul
1292 return (X_A (insn
) ? *npc
+ 4 : 0);
1296 /* For unconditional branches, return the target if its
1297 specified condition is "always" and return nPC + 4 if the
1298 condition is "never". If the annul bit is 1, set *NPC to
1300 if (X_COND (insn
) == 0x0)
1301 pc
= *npc
, offset
= 4;
1305 gdb_assert (offset
!= 0);
1314 sparc_step_trap (struct frame_info
*frame
, unsigned long insn
)
1320 sparc_software_single_step (struct frame_info
*frame
)
1322 struct gdbarch
*arch
= get_frame_arch (frame
);
1323 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
1324 CORE_ADDR npc
, nnpc
;
1326 CORE_ADDR pc
, orig_npc
;
1328 pc
= get_frame_register_unsigned (frame
, tdep
->pc_regnum
);
1329 orig_npc
= npc
= get_frame_register_unsigned (frame
, tdep
->npc_regnum
);
1331 /* Analyze the instruction at PC. */
1332 nnpc
= sparc_analyze_control_transfer (frame
, pc
, &npc
);
1334 insert_single_step_breakpoint (npc
);
1337 insert_single_step_breakpoint (nnpc
);
1339 /* Assert that we have set at least one breakpoint, and that
1340 they're not set at the same spot - unless we're going
1341 from here straight to NULL, i.e. a call or jump to 0. */
1342 gdb_assert (npc
!= 0 || nnpc
!= 0 || orig_npc
== 0);
1343 gdb_assert (nnpc
!= npc
|| orig_npc
== 0);
1349 sparc_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1351 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_regcache_arch (regcache
));
1353 regcache_cooked_write_unsigned (regcache
, tdep
->pc_regnum
, pc
);
1354 regcache_cooked_write_unsigned (regcache
, tdep
->npc_regnum
, pc
+ 4);
1357 /* Unglobalize NAME. */
1360 sparc_stabs_unglobalize_name (char *name
)
1362 /* The Sun compilers (Sun ONE Studio, Forte Developer, Sun WorkShop,
1363 SunPRO) convert file static variables into global values, a
1364 process known as globalization. In order to do this, the
1365 compiler will create a unique prefix and prepend it to each file
1366 static variable. For static variables within a function, this
1367 globalization prefix is followed by the function name (nested
1368 static variables within a function are supposed to generate a
1369 warning message, and are left alone). The procedure is
1370 documented in the Stabs Interface Manual, which is distrubuted
1371 with the compilers, although version 4.0 of the manual seems to
1372 be incorrect in some places, at least for SPARC. The
1373 globalization prefix is encoded into an N_OPT stab, with the form
1374 "G=<prefix>". The globalization prefix always seems to start
1375 with a dollar sign '$'; a dot '.' is used as a seperator. So we
1376 simply strip everything up until the last dot. */
1380 char *p
= strrchr (name
, '.');
1389 /* Return the appropriate register set for the core section identified
1390 by SECT_NAME and SECT_SIZE. */
1392 const struct regset
*
1393 sparc_regset_from_core_section (struct gdbarch
*gdbarch
,
1394 const char *sect_name
, size_t sect_size
)
1396 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1398 if (strcmp (sect_name
, ".reg") == 0 && sect_size
>= tdep
->sizeof_gregset
)
1399 return tdep
->gregset
;
1401 if (strcmp (sect_name
, ".reg2") == 0 && sect_size
>= tdep
->sizeof_fpregset
)
1402 return tdep
->fpregset
;
1408 static struct gdbarch
*
1409 sparc32_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1411 struct gdbarch_tdep
*tdep
;
1412 struct gdbarch
*gdbarch
;
1414 /* If there is already a candidate, use it. */
1415 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
1417 return arches
->gdbarch
;
1419 /* Allocate space for the new architecture. */
1420 tdep
= XMALLOC (struct gdbarch_tdep
);
1421 gdbarch
= gdbarch_alloc (&info
, tdep
);
1423 tdep
->pc_regnum
= SPARC32_PC_REGNUM
;
1424 tdep
->npc_regnum
= SPARC32_NPC_REGNUM
;
1425 tdep
->gregset
= NULL
;
1426 tdep
->sizeof_gregset
= 0;
1427 tdep
->fpregset
= NULL
;
1428 tdep
->sizeof_fpregset
= 0;
1429 tdep
->plt_entry_size
= 0;
1430 tdep
->step_trap
= sparc_step_trap
;
1432 set_gdbarch_long_double_bit (gdbarch
, 128);
1433 set_gdbarch_long_double_format (gdbarch
, floatformats_sparc_quad
);
1435 set_gdbarch_num_regs (gdbarch
, SPARC32_NUM_REGS
);
1436 set_gdbarch_register_name (gdbarch
, sparc32_register_name
);
1437 set_gdbarch_register_type (gdbarch
, sparc32_register_type
);
1438 set_gdbarch_num_pseudo_regs (gdbarch
, SPARC32_NUM_PSEUDO_REGS
);
1439 set_gdbarch_pseudo_register_read (gdbarch
, sparc32_pseudo_register_read
);
1440 set_gdbarch_pseudo_register_write (gdbarch
, sparc32_pseudo_register_write
);
1442 /* Register numbers of various important registers. */
1443 set_gdbarch_sp_regnum (gdbarch
, SPARC_SP_REGNUM
); /* %sp */
1444 set_gdbarch_pc_regnum (gdbarch
, SPARC32_PC_REGNUM
); /* %pc */
1445 set_gdbarch_fp0_regnum (gdbarch
, SPARC_F0_REGNUM
); /* %f0 */
1447 /* Call dummy code. */
1448 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
1449 set_gdbarch_push_dummy_code (gdbarch
, sparc32_push_dummy_code
);
1450 set_gdbarch_push_dummy_call (gdbarch
, sparc32_push_dummy_call
);
1452 set_gdbarch_return_value (gdbarch
, sparc32_return_value
);
1453 set_gdbarch_stabs_argument_has_addr
1454 (gdbarch
, sparc32_stabs_argument_has_addr
);
1456 set_gdbarch_skip_prologue (gdbarch
, sparc32_skip_prologue
);
1458 /* Stack grows downward. */
1459 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
1461 set_gdbarch_breakpoint_from_pc (gdbarch
, sparc_breakpoint_from_pc
);
1463 set_gdbarch_frame_args_skip (gdbarch
, 8);
1465 set_gdbarch_print_insn (gdbarch
, print_insn_sparc
);
1467 set_gdbarch_software_single_step (gdbarch
, sparc_software_single_step
);
1468 set_gdbarch_write_pc (gdbarch
, sparc_write_pc
);
1470 set_gdbarch_unwind_dummy_id (gdbarch
, sparc_unwind_dummy_id
);
1472 set_gdbarch_unwind_pc (gdbarch
, sparc_unwind_pc
);
1474 frame_base_set_default (gdbarch
, &sparc32_frame_base
);
1476 /* Hook in the DWARF CFI frame unwinder. */
1477 dwarf2_frame_set_init_reg (gdbarch
, sparc32_dwarf2_frame_init_reg
);
1478 /* FIXME: kettenis/20050423: Don't enable the unwinder until the
1479 StackGhost issues have been resolved. */
1481 /* Hook in ABI-specific overrides, if they have been registered. */
1482 gdbarch_init_osabi (info
, gdbarch
);
1484 frame_unwind_append_sniffer (gdbarch
, sparc32_frame_sniffer
);
1486 /* If we have register sets, enable the generic core file support. */
1488 set_gdbarch_regset_from_core_section (gdbarch
,
1489 sparc_regset_from_core_section
);
1494 /* Helper functions for dealing with register windows. */
1497 sparc_supply_rwindow (struct regcache
*regcache
, CORE_ADDR sp
, int regnum
)
1505 /* Registers are 64-bit. */
1508 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1510 if (regnum
== i
|| regnum
== -1)
1512 target_read_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 8), buf
, 8);
1514 /* Handle StackGhost. */
1515 if (i
== SPARC_I7_REGNUM
)
1517 ULONGEST wcookie
= sparc_fetch_wcookie ();
1518 ULONGEST i7
= extract_unsigned_integer (buf
+ offset
, 8);
1520 store_unsigned_integer (buf
+ offset
, 8, i7
^ wcookie
);
1523 regcache_raw_supply (regcache
, i
, buf
);
1529 /* Registers are 32-bit. Toss any sign-extension of the stack
1533 /* Clear out the top half of the temporary buffer, and put the
1534 register value in the bottom half if we're in 64-bit mode. */
1535 if (gdbarch_ptr_bit (current_gdbarch
) == 64)
1541 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1543 if (regnum
== i
|| regnum
== -1)
1545 target_read_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 4),
1548 /* Handle StackGhost. */
1549 if (i
== SPARC_I7_REGNUM
)
1551 ULONGEST wcookie
= sparc_fetch_wcookie ();
1552 ULONGEST i7
= extract_unsigned_integer (buf
+ offset
, 4);
1554 store_unsigned_integer (buf
+ offset
, 4, i7
^ wcookie
);
1557 regcache_raw_supply (regcache
, i
, buf
);
1564 sparc_collect_rwindow (const struct regcache
*regcache
,
1565 CORE_ADDR sp
, int regnum
)
1573 /* Registers are 64-bit. */
1576 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1578 if (regnum
== -1 || regnum
== SPARC_SP_REGNUM
|| regnum
== i
)
1580 regcache_raw_collect (regcache
, i
, buf
);
1582 /* Handle StackGhost. */
1583 if (i
== SPARC_I7_REGNUM
)
1585 ULONGEST wcookie
= sparc_fetch_wcookie ();
1586 ULONGEST i7
= extract_unsigned_integer (buf
+ offset
, 8);
1588 store_unsigned_integer (buf
, 8, i7
^ wcookie
);
1591 target_write_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 8), buf
, 8);
1597 /* Registers are 32-bit. Toss any sign-extension of the stack
1601 /* Only use the bottom half if we're in 64-bit mode. */
1602 if (gdbarch_ptr_bit (current_gdbarch
) == 64)
1605 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1607 if (regnum
== -1 || regnum
== SPARC_SP_REGNUM
|| regnum
== i
)
1609 regcache_raw_collect (regcache
, i
, buf
);
1611 /* Handle StackGhost. */
1612 if (i
== SPARC_I7_REGNUM
)
1614 ULONGEST wcookie
= sparc_fetch_wcookie ();
1615 ULONGEST i7
= extract_unsigned_integer (buf
+ offset
, 4);
1617 store_unsigned_integer (buf
+ offset
, 4, i7
^ wcookie
);
1620 target_write_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 4),
1627 /* Helper functions for dealing with register sets. */
1630 sparc32_supply_gregset (const struct sparc_gregset
*gregset
,
1631 struct regcache
*regcache
,
1632 int regnum
, const void *gregs
)
1634 const gdb_byte
*regs
= gregs
;
1637 if (regnum
== SPARC32_PSR_REGNUM
|| regnum
== -1)
1638 regcache_raw_supply (regcache
, SPARC32_PSR_REGNUM
,
1639 regs
+ gregset
->r_psr_offset
);
1641 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== -1)
1642 regcache_raw_supply (regcache
, SPARC32_PC_REGNUM
,
1643 regs
+ gregset
->r_pc_offset
);
1645 if (regnum
== SPARC32_NPC_REGNUM
|| regnum
== -1)
1646 regcache_raw_supply (regcache
, SPARC32_NPC_REGNUM
,
1647 regs
+ gregset
->r_npc_offset
);
1649 if (regnum
== SPARC32_Y_REGNUM
|| regnum
== -1)
1650 regcache_raw_supply (regcache
, SPARC32_Y_REGNUM
,
1651 regs
+ gregset
->r_y_offset
);
1653 if (regnum
== SPARC_G0_REGNUM
|| regnum
== -1)
1654 regcache_raw_supply (regcache
, SPARC_G0_REGNUM
, NULL
);
1656 if ((regnum
>= SPARC_G1_REGNUM
&& regnum
<= SPARC_O7_REGNUM
) || regnum
== -1)
1658 int offset
= gregset
->r_g1_offset
;
1660 for (i
= SPARC_G1_REGNUM
; i
<= SPARC_O7_REGNUM
; i
++)
1662 if (regnum
== i
|| regnum
== -1)
1663 regcache_raw_supply (regcache
, i
, regs
+ offset
);
1668 if ((regnum
>= SPARC_L0_REGNUM
&& regnum
<= SPARC_I7_REGNUM
) || regnum
== -1)
1670 /* Not all of the register set variants include Locals and
1671 Inputs. For those that don't, we read them off the stack. */
1672 if (gregset
->r_l0_offset
== -1)
1676 regcache_cooked_read_unsigned (regcache
, SPARC_SP_REGNUM
, &sp
);
1677 sparc_supply_rwindow (regcache
, sp
, regnum
);
1681 int offset
= gregset
->r_l0_offset
;
1683 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1685 if (regnum
== i
|| regnum
== -1)
1686 regcache_raw_supply (regcache
, i
, regs
+ offset
);
1694 sparc32_collect_gregset (const struct sparc_gregset
*gregset
,
1695 const struct regcache
*regcache
,
1696 int regnum
, void *gregs
)
1698 gdb_byte
*regs
= gregs
;
1701 if (regnum
== SPARC32_PSR_REGNUM
|| regnum
== -1)
1702 regcache_raw_collect (regcache
, SPARC32_PSR_REGNUM
,
1703 regs
+ gregset
->r_psr_offset
);
1705 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== -1)
1706 regcache_raw_collect (regcache
, SPARC32_PC_REGNUM
,
1707 regs
+ gregset
->r_pc_offset
);
1709 if (regnum
== SPARC32_NPC_REGNUM
|| regnum
== -1)
1710 regcache_raw_collect (regcache
, SPARC32_NPC_REGNUM
,
1711 regs
+ gregset
->r_npc_offset
);
1713 if (regnum
== SPARC32_Y_REGNUM
|| regnum
== -1)
1714 regcache_raw_collect (regcache
, SPARC32_Y_REGNUM
,
1715 regs
+ gregset
->r_y_offset
);
1717 if ((regnum
>= SPARC_G1_REGNUM
&& regnum
<= SPARC_O7_REGNUM
) || regnum
== -1)
1719 int offset
= gregset
->r_g1_offset
;
1721 /* %g0 is always zero. */
1722 for (i
= SPARC_G1_REGNUM
; i
<= SPARC_O7_REGNUM
; i
++)
1724 if (regnum
== i
|| regnum
== -1)
1725 regcache_raw_collect (regcache
, i
, regs
+ offset
);
1730 if ((regnum
>= SPARC_L0_REGNUM
&& regnum
<= SPARC_I7_REGNUM
) || regnum
== -1)
1732 /* Not all of the register set variants include Locals and
1733 Inputs. For those that don't, we read them off the stack. */
1734 if (gregset
->r_l0_offset
!= -1)
1736 int offset
= gregset
->r_l0_offset
;
1738 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1740 if (regnum
== i
|| regnum
== -1)
1741 regcache_raw_collect (regcache
, i
, regs
+ offset
);
1749 sparc32_supply_fpregset (struct regcache
*regcache
,
1750 int regnum
, const void *fpregs
)
1752 const gdb_byte
*regs
= fpregs
;
1755 for (i
= 0; i
< 32; i
++)
1757 if (regnum
== (SPARC_F0_REGNUM
+ i
) || regnum
== -1)
1758 regcache_raw_supply (regcache
, SPARC_F0_REGNUM
+ i
, regs
+ (i
* 4));
1761 if (regnum
== SPARC32_FSR_REGNUM
|| regnum
== -1)
1762 regcache_raw_supply (regcache
, SPARC32_FSR_REGNUM
, regs
+ (32 * 4) + 4);
1766 sparc32_collect_fpregset (const struct regcache
*regcache
,
1767 int regnum
, void *fpregs
)
1769 gdb_byte
*regs
= fpregs
;
1772 for (i
= 0; i
< 32; i
++)
1774 if (regnum
== (SPARC_F0_REGNUM
+ i
) || regnum
== -1)
1775 regcache_raw_collect (regcache
, SPARC_F0_REGNUM
+ i
, regs
+ (i
* 4));
1778 if (regnum
== SPARC32_FSR_REGNUM
|| regnum
== -1)
1779 regcache_raw_collect (regcache
, SPARC32_FSR_REGNUM
, regs
+ (32 * 4) + 4);
1785 /* From <machine/reg.h>. */
1786 const struct sparc_gregset sparc32_sunos4_gregset
=
1799 /* Provide a prototype to silence -Wmissing-prototypes. */
1800 void _initialize_sparc_tdep (void);
1803 _initialize_sparc_tdep (void)
1805 register_gdbarch_init (bfd_arch_sparc
, sparc32_gdbarch_init
);
1807 /* Initialize the SPARC-specific register types. */