1 /* Target-dependent code for SPARC.
3 Copyright (C) 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include "arch-utils.h"
24 #include "dwarf2-frame.h"
25 #include "floatformat.h"
27 #include "frame-base.h"
28 #include "frame-unwind.h"
39 #include "gdb_assert.h"
40 #include "gdb_string.h"
42 #include "sparc-tdep.h"
46 /* This file implements the SPARC 32-bit ABI as defined by the section
47 "Low-Level System Information" of the SPARC Compliance Definition
48 (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC. The SCD
49 lists changes with respect to the original 32-bit psABI as defined
50 in the "System V ABI, SPARC Processor Supplement".
52 Note that if we talk about SunOS, we mean SunOS 4.x, which was
53 BSD-based, which is sometimes (retroactively?) referred to as
54 Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and
55 above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9
56 suffering from severe version number inflation). Solaris 2.x is
57 also known as SunOS 5.x, since that's what uname(1) says. Solaris
60 /* Please use the sparc32_-prefix for 32-bit specific code, the
61 sparc64_-prefix for 64-bit specific code and the sparc_-prefix for
62 code that can handle both. The 64-bit specific code lives in
63 sparc64-tdep.c; don't add any here. */
65 /* The SPARC Floating-Point Quad-Precision format is similar to
66 big-endian IA-64 Quad-Precision format. */
67 #define floatformats_sparc_quad floatformats_ia64_quad
69 /* The stack pointer is offset from the stack frame by a BIAS of 2047
70 (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC
71 hosts, so undefine it first. */
75 /* Macros to extract fields from SPARC instructions. */
76 #define X_OP(i) (((i) >> 30) & 0x3)
77 #define X_RD(i) (((i) >> 25) & 0x1f)
78 #define X_A(i) (((i) >> 29) & 1)
79 #define X_COND(i) (((i) >> 25) & 0xf)
80 #define X_OP2(i) (((i) >> 22) & 0x7)
81 #define X_IMM22(i) ((i) & 0x3fffff)
82 #define X_OP3(i) (((i) >> 19) & 0x3f)
83 #define X_RS1(i) (((i) >> 14) & 0x1f)
84 #define X_RS2(i) ((i) & 0x1f)
85 #define X_I(i) (((i) >> 13) & 1)
86 /* Sign extension macros. */
87 #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000)
88 #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000)
89 #define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000)
91 /* Fetch the instruction at PC. Instructions are always big-endian
92 even if the processor operates in little-endian mode. */
95 sparc_fetch_instruction (CORE_ADDR pc
)
101 /* If we can't read the instruction at PC, return zero. */
102 if (target_read_memory (pc
, buf
, sizeof (buf
)))
106 for (i
= 0; i
< sizeof (buf
); i
++)
107 insn
= (insn
<< 8) | buf
[i
];
112 /* Return non-zero if the instruction corresponding to PC is an "unimp"
116 sparc_is_unimp_insn (CORE_ADDR pc
)
118 const unsigned long insn
= sparc_fetch_instruction (pc
);
120 return ((insn
& 0xc1c00000) == 0);
123 /* OpenBSD/sparc includes StackGhost, which according to the author's
124 website http://stackghost.cerias.purdue.edu "... transparently and
125 automatically protects applications' stack frames; more
126 specifically, it guards the return pointers. The protection
127 mechanisms require no application source or binary modification and
128 imposes only a negligible performance penalty."
130 The same website provides the following description of how
133 "StackGhost interfaces with the kernel trap handler that would
134 normally write out registers to the stack and the handler that
135 would read them back in. By XORing a cookie into the
136 return-address saved in the user stack when it is actually written
137 to the stack, and then XOR it out when the return-address is pulled
138 from the stack, StackGhost can cause attacker corrupted return
139 pointers to behave in a manner the attacker cannot predict.
140 StackGhost can also use several unused bits in the return pointer
141 to detect a smashed return pointer and abort the process."
143 For GDB this means that whenever we're reading %i7 from a stack
144 frame's window save area, we'll have to XOR the cookie.
146 More information on StackGuard can be found on in:
148 Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated
149 Stack Protection." 2001. Published in USENIX Security Symposium
152 /* Fetch StackGhost Per-Process XOR cookie. */
155 sparc_fetch_wcookie (struct gdbarch
*gdbarch
)
157 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
158 struct target_ops
*ops
= ¤t_target
;
162 len
= target_read (ops
, TARGET_OBJECT_WCOOKIE
, NULL
, buf
, 0, 8);
166 /* We should have either an 32-bit or an 64-bit cookie. */
167 gdb_assert (len
== 4 || len
== 8);
169 return extract_unsigned_integer (buf
, len
, byte_order
);
173 /* The functions on this page are intended to be used to classify
174 function arguments. */
176 /* Check whether TYPE is "Integral or Pointer". */
179 sparc_integral_or_pointer_p (const struct type
*type
)
181 int len
= TYPE_LENGTH (type
);
183 switch (TYPE_CODE (type
))
189 case TYPE_CODE_RANGE
:
190 /* We have byte, half-word, word and extended-word/doubleword
191 integral types. The doubleword is an extension to the
192 original 32-bit ABI by the SCD 2.4.x. */
193 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
196 /* Allow either 32-bit or 64-bit pointers. */
197 return (len
== 4 || len
== 8);
205 /* Check whether TYPE is "Floating". */
208 sparc_floating_p (const struct type
*type
)
210 switch (TYPE_CODE (type
))
214 int len
= TYPE_LENGTH (type
);
215 return (len
== 4 || len
== 8 || len
== 16);
224 /* Check whether TYPE is "Structure or Union".
226 In terms of Ada subprogram calls, arrays are treated the same as
227 struct and union types. So this function also returns non-zero
231 sparc_structure_or_union_p (const struct type
*type
)
233 switch (TYPE_CODE (type
))
235 case TYPE_CODE_STRUCT
:
236 case TYPE_CODE_UNION
:
237 case TYPE_CODE_ARRAY
:
246 /* Register information. */
248 static const char *sparc32_register_names
[] =
250 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
251 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
252 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
253 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
255 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
256 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
257 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
258 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
260 "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr"
263 /* Total number of registers. */
264 #define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names)
266 /* We provide the aliases %d0..%d30 for the floating registers as
267 "psuedo" registers. */
269 static const char *sparc32_pseudo_register_names
[] =
271 "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14",
272 "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30"
275 /* Total number of pseudo registers. */
276 #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names)
278 /* Return the name of register REGNUM. */
281 sparc32_register_name (struct gdbarch
*gdbarch
, int regnum
)
283 if (regnum
>= 0 && regnum
< SPARC32_NUM_REGS
)
284 return sparc32_register_names
[regnum
];
286 if (regnum
< SPARC32_NUM_REGS
+ SPARC32_NUM_PSEUDO_REGS
)
287 return sparc32_pseudo_register_names
[regnum
- SPARC32_NUM_REGS
];
292 /* Construct types for ISA-specific registers. */
295 sparc_psr_type (struct gdbarch
*gdbarch
)
297 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
299 if (!tdep
->sparc_psr_type
)
303 type
= arch_flags_type (gdbarch
, "builtin_type_sparc_psr", 4);
304 append_flags_type_flag (type
, 5, "ET");
305 append_flags_type_flag (type
, 6, "PS");
306 append_flags_type_flag (type
, 7, "S");
307 append_flags_type_flag (type
, 12, "EF");
308 append_flags_type_flag (type
, 13, "EC");
310 tdep
->sparc_psr_type
= type
;
313 return tdep
->sparc_psr_type
;
317 sparc_fsr_type (struct gdbarch
*gdbarch
)
319 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
321 if (!tdep
->sparc_fsr_type
)
325 type
= arch_flags_type (gdbarch
, "builtin_type_sparc_fsr", 4);
326 append_flags_type_flag (type
, 0, "NXA");
327 append_flags_type_flag (type
, 1, "DZA");
328 append_flags_type_flag (type
, 2, "UFA");
329 append_flags_type_flag (type
, 3, "OFA");
330 append_flags_type_flag (type
, 4, "NVA");
331 append_flags_type_flag (type
, 5, "NXC");
332 append_flags_type_flag (type
, 6, "DZC");
333 append_flags_type_flag (type
, 7, "UFC");
334 append_flags_type_flag (type
, 8, "OFC");
335 append_flags_type_flag (type
, 9, "NVC");
336 append_flags_type_flag (type
, 22, "NS");
337 append_flags_type_flag (type
, 23, "NXM");
338 append_flags_type_flag (type
, 24, "DZM");
339 append_flags_type_flag (type
, 25, "UFM");
340 append_flags_type_flag (type
, 26, "OFM");
341 append_flags_type_flag (type
, 27, "NVM");
343 tdep
->sparc_fsr_type
= type
;
346 return tdep
->sparc_fsr_type
;
349 /* Return the GDB type object for the "standard" data type of data in
353 sparc32_register_type (struct gdbarch
*gdbarch
, int regnum
)
355 if (regnum
>= SPARC_F0_REGNUM
&& regnum
<= SPARC_F31_REGNUM
)
356 return builtin_type (gdbarch
)->builtin_float
;
358 if (regnum
>= SPARC32_D0_REGNUM
&& regnum
<= SPARC32_D30_REGNUM
)
359 return builtin_type (gdbarch
)->builtin_double
;
361 if (regnum
== SPARC_SP_REGNUM
|| regnum
== SPARC_FP_REGNUM
)
362 return builtin_type (gdbarch
)->builtin_data_ptr
;
364 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== SPARC32_NPC_REGNUM
)
365 return builtin_type (gdbarch
)->builtin_func_ptr
;
367 if (regnum
== SPARC32_PSR_REGNUM
)
368 return sparc_psr_type (gdbarch
);
370 if (regnum
== SPARC32_FSR_REGNUM
)
371 return sparc_fsr_type (gdbarch
);
373 return builtin_type (gdbarch
)->builtin_int32
;
376 static enum register_status
377 sparc32_pseudo_register_read (struct gdbarch
*gdbarch
,
378 struct regcache
*regcache
,
379 int regnum
, gdb_byte
*buf
)
381 enum register_status status
;
383 gdb_assert (regnum
>= SPARC32_D0_REGNUM
&& regnum
<= SPARC32_D30_REGNUM
);
385 regnum
= SPARC_F0_REGNUM
+ 2 * (regnum
- SPARC32_D0_REGNUM
);
386 status
= regcache_raw_read (regcache
, regnum
, buf
);
387 if (status
== REG_VALID
)
388 status
= regcache_raw_read (regcache
, regnum
+ 1, buf
+ 4);
393 sparc32_pseudo_register_write (struct gdbarch
*gdbarch
,
394 struct regcache
*regcache
,
395 int regnum
, const gdb_byte
*buf
)
397 gdb_assert (regnum
>= SPARC32_D0_REGNUM
&& regnum
<= SPARC32_D30_REGNUM
);
399 regnum
= SPARC_F0_REGNUM
+ 2 * (regnum
- SPARC32_D0_REGNUM
);
400 regcache_raw_write (regcache
, regnum
, buf
);
401 regcache_raw_write (regcache
, regnum
+ 1, buf
+ 4);
406 sparc32_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR address
)
408 /* The ABI requires double-word alignment. */
409 return address
& ~0x7;
413 sparc32_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
415 struct value
**args
, int nargs
,
416 struct type
*value_type
,
417 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
418 struct regcache
*regcache
)
420 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
425 if (using_struct_return (gdbarch
, NULL
, value_type
))
429 /* This is an UNIMP instruction. */
430 store_unsigned_integer (buf
, 4, byte_order
,
431 TYPE_LENGTH (value_type
) & 0x1fff);
432 write_memory (sp
- 8, buf
, 4);
440 sparc32_store_arguments (struct regcache
*regcache
, int nargs
,
441 struct value
**args
, CORE_ADDR sp
,
442 int struct_return
, CORE_ADDR struct_addr
)
444 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
445 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
446 /* Number of words in the "parameter array". */
447 int num_elements
= 0;
451 for (i
= 0; i
< nargs
; i
++)
453 struct type
*type
= value_type (args
[i
]);
454 int len
= TYPE_LENGTH (type
);
456 if (sparc_structure_or_union_p (type
)
457 || (sparc_floating_p (type
) && len
== 16))
459 /* Structure, Union and Quad-Precision Arguments. */
462 /* Use doubleword alignment for these values. That's always
463 correct, and wasting a few bytes shouldn't be a problem. */
466 write_memory (sp
, value_contents (args
[i
]), len
);
467 args
[i
] = value_from_pointer (lookup_pointer_type (type
), sp
);
470 else if (sparc_floating_p (type
))
472 /* Floating arguments. */
473 gdb_assert (len
== 4 || len
== 8);
474 num_elements
+= (len
/ 4);
478 /* Integral and pointer arguments. */
479 gdb_assert (sparc_integral_or_pointer_p (type
));
482 args
[i
] = value_cast (builtin_type (gdbarch
)->builtin_int32
,
484 num_elements
+= ((len
+ 3) / 4);
488 /* Always allocate at least six words. */
489 sp
-= max (6, num_elements
) * 4;
491 /* The psABI says that "Software convention requires space for the
492 struct/union return value pointer, even if the word is unused." */
495 /* The psABI says that "Although software convention and the
496 operating system require every stack frame to be doubleword
500 for (i
= 0; i
< nargs
; i
++)
502 const bfd_byte
*valbuf
= value_contents (args
[i
]);
503 struct type
*type
= value_type (args
[i
]);
504 int len
= TYPE_LENGTH (type
);
506 gdb_assert (len
== 4 || len
== 8);
510 int regnum
= SPARC_O0_REGNUM
+ element
;
512 regcache_cooked_write (regcache
, regnum
, valbuf
);
513 if (len
> 4 && element
< 5)
514 regcache_cooked_write (regcache
, regnum
+ 1, valbuf
+ 4);
517 /* Always store the argument in memory. */
518 write_memory (sp
+ 4 + element
* 4, valbuf
, len
);
522 gdb_assert (element
== num_elements
);
528 store_unsigned_integer (buf
, 4, byte_order
, struct_addr
);
529 write_memory (sp
, buf
, 4);
536 sparc32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
537 struct regcache
*regcache
, CORE_ADDR bp_addr
,
538 int nargs
, struct value
**args
, CORE_ADDR sp
,
539 int struct_return
, CORE_ADDR struct_addr
)
541 CORE_ADDR call_pc
= (struct_return
? (bp_addr
- 12) : (bp_addr
- 8));
543 /* Set return address. */
544 regcache_cooked_write_unsigned (regcache
, SPARC_O7_REGNUM
, call_pc
);
546 /* Set up function arguments. */
547 sp
= sparc32_store_arguments (regcache
, nargs
, args
, sp
,
548 struct_return
, struct_addr
);
550 /* Allocate the 16-word window save area. */
553 /* Stack should be doubleword aligned at this point. */
554 gdb_assert (sp
% 8 == 0);
556 /* Finally, update the stack pointer. */
557 regcache_cooked_write_unsigned (regcache
, SPARC_SP_REGNUM
, sp
);
563 /* Use the program counter to determine the contents and size of a
564 breakpoint instruction. Return a pointer to a string of bytes that
565 encode a breakpoint instruction, store the length of the string in
566 *LEN and optionally adjust *PC to point to the correct memory
567 location for inserting the breakpoint. */
569 static const gdb_byte
*
570 sparc_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pc
, int *len
)
572 static const gdb_byte break_insn
[] = { 0x91, 0xd0, 0x20, 0x01 };
574 *len
= sizeof (break_insn
);
579 /* Allocate and initialize a frame cache. */
581 static struct sparc_frame_cache
*
582 sparc_alloc_frame_cache (void)
584 struct sparc_frame_cache
*cache
;
587 cache
= FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache
);
593 /* Frameless until proven otherwise. */
594 cache
->frameless_p
= 1;
595 cache
->frame_offset
= 0;
596 cache
->saved_regs_mask
= 0;
597 cache
->copied_regs_mask
= 0;
598 cache
->struct_return_p
= 0;
603 /* GCC generates several well-known sequences of instructions at the begining
604 of each function prologue when compiling with -fstack-check. If one of
605 such sequences starts at START_PC, then return the address of the
606 instruction immediately past this sequence. Otherwise, return START_PC. */
609 sparc_skip_stack_check (const CORE_ADDR start_pc
)
611 CORE_ADDR pc
= start_pc
;
613 int offset_stack_checking_sequence
= 0;
614 int probing_loop
= 0;
616 /* With GCC, all stack checking sequences begin with the same two
617 instructions, plus an optional one in the case of a probing loop:
619 sethi <some immediate>, %g1
624 sethi <some immediate>, %g1
625 sethi <some immediate>, %g4
630 sethi <some immediate>, %g1
632 sethi <some immediate>, %g4
634 If the optional instruction is found (setting g4), assume that a
635 probing loop will follow. */
637 /* sethi <some immediate>, %g1 */
638 insn
= sparc_fetch_instruction (pc
);
640 if (!(X_OP (insn
) == 0 && X_OP2 (insn
) == 0x4 && X_RD (insn
) == 1))
643 /* optional: sethi <some immediate>, %g4 */
644 insn
= sparc_fetch_instruction (pc
);
646 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 0x4 && X_RD (insn
) == 4)
649 insn
= sparc_fetch_instruction (pc
);
653 /* sub %sp, %g1, %g1 */
654 if (!(X_OP (insn
) == 2 && X_OP3 (insn
) == 0x4 && !X_I(insn
)
655 && X_RD (insn
) == 1 && X_RS1 (insn
) == 14 && X_RS2 (insn
) == 1))
658 insn
= sparc_fetch_instruction (pc
);
661 /* optional: sethi <some immediate>, %g4 */
662 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 0x4 && X_RD (insn
) == 4)
665 insn
= sparc_fetch_instruction (pc
);
669 /* First possible sequence:
670 [first two instructions above]
671 clr [%g1 - some immediate] */
673 /* clr [%g1 - some immediate] */
674 if (X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && X_I(insn
)
675 && X_RS1 (insn
) == 1 && X_RD (insn
) == 0)
677 /* Valid stack-check sequence, return the new PC. */
681 /* Second possible sequence: A small number of probes.
682 [first two instructions above]
684 add %g1, -<some immediate>, %g1
686 [repeat the two instructions above any (small) number of times]
687 clr [%g1 - some immediate] */
690 else if (X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && !X_I(insn
)
691 && X_RS1 (insn
) == 1 && X_RD (insn
) == 0)
695 /* add %g1, -<some immediate>, %g1 */
696 insn
= sparc_fetch_instruction (pc
);
698 if (!(X_OP (insn
) == 2 && X_OP3(insn
) == 0 && X_I(insn
)
699 && X_RS1 (insn
) == 1 && X_RD (insn
) == 1))
703 insn
= sparc_fetch_instruction (pc
);
705 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && !X_I(insn
)
706 && X_RD (insn
) == 0 && X_RS1 (insn
) == 1))
710 /* clr [%g1 - some immediate] */
711 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && X_I(insn
)
712 && X_RS1 (insn
) == 1 && X_RD (insn
) == 0))
715 /* We found a valid stack-check sequence, return the new PC. */
719 /* Third sequence: A probing loop.
720 [first three instructions above]
724 add %g1, -<some immediate>, %g1
728 And an optional last probe for the remainder:
730 clr [%g4 - some immediate] */
734 /* sub %g1, %g4, %g4 */
735 if (!(X_OP (insn
) == 2 && X_OP3 (insn
) == 0x4 && !X_I(insn
)
736 && X_RD (insn
) == 4 && X_RS1 (insn
) == 1 && X_RS2 (insn
) == 4))
740 insn
= sparc_fetch_instruction (pc
);
742 if (!(X_OP (insn
) == 2 && X_OP3 (insn
) == 0x14 && !X_I(insn
)
743 && X_RD (insn
) == 0 && X_RS1 (insn
) == 1 && X_RS2 (insn
) == 4))
747 insn
= sparc_fetch_instruction (pc
);
749 if (!(X_OP (insn
) == 0 && X_COND (insn
) == 0x1))
752 /* add %g1, -<some immediate>, %g1 */
753 insn
= sparc_fetch_instruction (pc
);
755 if (!(X_OP (insn
) == 2 && X_OP3(insn
) == 0 && X_I(insn
)
756 && X_RS1 (insn
) == 1 && X_RD (insn
) == 1))
760 insn
= sparc_fetch_instruction (pc
);
762 if (!(X_OP (insn
) == 0 && X_COND (insn
) == 0x8))
765 /* clr [%g1] (st %g0, [%g1] or st %g0, [%g1+0]) */
766 insn
= sparc_fetch_instruction (pc
);
768 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4
769 && X_RD (insn
) == 0 && X_RS1 (insn
) == 1
770 && (!X_I(insn
) || X_SIMM13 (insn
) == 0)))
773 /* We found a valid stack-check sequence, return the new PC. */
775 /* optional: clr [%g4 - some immediate] */
776 insn
= sparc_fetch_instruction (pc
);
778 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && X_I(insn
)
779 && X_RS1 (insn
) == 4 && X_RD (insn
) == 0))
785 /* No stack check code in our prologue, return the start_pc. */
789 /* Record the effect of a SAVE instruction on CACHE. */
792 sparc_record_save_insn (struct sparc_frame_cache
*cache
)
794 /* The frame is set up. */
795 cache
->frameless_p
= 0;
797 /* The frame pointer contains the CFA. */
798 cache
->frame_offset
= 0;
800 /* The `local' and `in' registers are all saved. */
801 cache
->saved_regs_mask
= 0xffff;
803 /* The `out' registers are all renamed. */
804 cache
->copied_regs_mask
= 0xff;
807 /* Do a full analysis of the prologue at PC and update CACHE accordingly.
808 Bail out early if CURRENT_PC is reached. Return the address where
809 the analysis stopped.
811 We handle both the traditional register window model and the single
812 register window (aka flat) model. */
815 sparc_analyze_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
816 CORE_ADDR current_pc
, struct sparc_frame_cache
*cache
)
818 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
823 pc
= sparc_skip_stack_check (pc
);
825 if (current_pc
<= pc
)
828 /* We have to handle to "Procedure Linkage Table" (PLT) special. On
829 SPARC the linker usually defines a symbol (typically
830 _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section.
831 This symbol makes us end up here with PC pointing at the start of
832 the PLT and CURRENT_PC probably pointing at a PLT entry. If we
833 would do our normal prologue analysis, we would probably conclude
834 that we've got a frame when in reality we don't, since the
835 dynamic linker patches up the first PLT with some code that
836 starts with a SAVE instruction. Patch up PC such that it points
837 at the start of our PLT entry. */
838 if (tdep
->plt_entry_size
> 0 && in_plt_section (current_pc
, NULL
))
839 pc
= current_pc
- ((current_pc
- pc
) % tdep
->plt_entry_size
);
841 insn
= sparc_fetch_instruction (pc
);
843 /* Recognize store insns and record their sources. */
844 while (X_OP (insn
) == 3
845 && (X_OP3 (insn
) == 0x4 /* stw */
846 || X_OP3 (insn
) == 0x7 /* std */
847 || X_OP3 (insn
) == 0xe) /* stx */
848 && X_RS1 (insn
) == SPARC_SP_REGNUM
)
850 int regnum
= X_RD (insn
);
852 /* Recognize stores into the corresponding stack slots. */
853 if (regnum
>= SPARC_L0_REGNUM
&& regnum
<= SPARC_I7_REGNUM
855 && X_SIMM13 (insn
) == (X_OP3 (insn
) == 0xe
856 ? (regnum
- SPARC_L0_REGNUM
) * 8 + BIAS
857 : (regnum
- SPARC_L0_REGNUM
) * 4))
858 || (!X_I (insn
) && regnum
== SPARC_L0_REGNUM
)))
860 cache
->saved_regs_mask
|= (1 << (regnum
- SPARC_L0_REGNUM
));
861 if (X_OP3 (insn
) == 0x7)
862 cache
->saved_regs_mask
|= (1 << (regnum
+ 1 - SPARC_L0_REGNUM
));
867 insn
= sparc_fetch_instruction (pc
+ offset
);
870 /* Recognize a SETHI insn and record its destination. */
871 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 0x04)
876 insn
= sparc_fetch_instruction (pc
+ offset
);
879 /* Allow for an arithmetic operation on DEST or %g1. */
880 if (X_OP (insn
) == 2 && X_I (insn
)
881 && (X_RD (insn
) == 1 || X_RD (insn
) == dest
))
885 insn
= sparc_fetch_instruction (pc
+ offset
);
888 /* Check for the SAVE instruction that sets up the frame. */
889 if (X_OP (insn
) == 2 && X_OP3 (insn
) == 0x3c)
891 sparc_record_save_insn (cache
);
896 /* Check for an arithmetic operation on %sp. */
898 && (X_OP3 (insn
) == 0 || X_OP3 (insn
) == 0x4)
899 && X_RS1 (insn
) == SPARC_SP_REGNUM
900 && X_RD (insn
) == SPARC_SP_REGNUM
)
904 cache
->frame_offset
= X_SIMM13 (insn
);
905 if (X_OP3 (insn
) == 0)
906 cache
->frame_offset
= -cache
->frame_offset
;
910 insn
= sparc_fetch_instruction (pc
+ offset
);
912 /* Check for an arithmetic operation that sets up the frame. */
914 && (X_OP3 (insn
) == 0 || X_OP3 (insn
) == 0x4)
915 && X_RS1 (insn
) == SPARC_SP_REGNUM
916 && X_RD (insn
) == SPARC_FP_REGNUM
)
918 cache
->frameless_p
= 0;
919 cache
->frame_offset
= 0;
920 /* We could check that the amount subtracted to %sp above is the
921 same as the one added here, but this seems superfluous. */
922 cache
->copied_regs_mask
|= 0x40;
925 insn
= sparc_fetch_instruction (pc
+ offset
);
928 /* Check for a move (or) operation that copies the return register. */
930 && X_OP3 (insn
) == 0x2
932 && X_RS1 (insn
) == SPARC_G0_REGNUM
933 && X_RS2 (insn
) == SPARC_O7_REGNUM
934 && X_RD (insn
) == SPARC_I7_REGNUM
)
936 cache
->copied_regs_mask
|= 0x80;
947 sparc_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
949 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
950 return frame_unwind_register_unsigned (this_frame
, tdep
->pc_regnum
);
953 /* Return PC of first real instruction of the function starting at
957 sparc32_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
959 struct symtab_and_line sal
;
960 CORE_ADDR func_start
, func_end
;
961 struct sparc_frame_cache cache
;
963 /* This is the preferred method, find the end of the prologue by
964 using the debugging information. */
965 if (find_pc_partial_function (start_pc
, NULL
, &func_start
, &func_end
))
967 sal
= find_pc_line (func_start
, 0);
969 if (sal
.end
< func_end
970 && start_pc
<= sal
.end
)
974 start_pc
= sparc_analyze_prologue (gdbarch
, start_pc
, 0xffffffffUL
, &cache
);
976 /* The psABI says that "Although the first 6 words of arguments
977 reside in registers, the standard stack frame reserves space for
978 them.". It also suggests that a function may use that space to
979 "write incoming arguments 0 to 5" into that space, and that's
980 indeed what GCC seems to be doing. In that case GCC will
981 generate debug information that points to the stack slots instead
982 of the registers, so we should consider the instructions that
983 write out these incoming arguments onto the stack. */
987 unsigned long insn
= sparc_fetch_instruction (start_pc
);
989 /* Recognize instructions that store incoming arguments into the
990 corresponding stack slots. */
991 if (X_OP (insn
) == 3 && (X_OP3 (insn
) & 0x3c) == 0x04
992 && X_I (insn
) && X_RS1 (insn
) == SPARC_FP_REGNUM
)
994 int regnum
= X_RD (insn
);
996 /* Case of arguments still in %o[0..5]. */
997 if (regnum
>= SPARC_O0_REGNUM
&& regnum
<= SPARC_O5_REGNUM
998 && !(cache
.copied_regs_mask
& (1 << (regnum
- SPARC_O0_REGNUM
)))
999 && X_SIMM13 (insn
) == 68 + (regnum
- SPARC_O0_REGNUM
) * 4)
1005 /* Case of arguments copied into %i[0..5]. */
1006 if (regnum
>= SPARC_I0_REGNUM
&& regnum
<= SPARC_I5_REGNUM
1007 && (cache
.copied_regs_mask
& (1 << (regnum
- SPARC_I0_REGNUM
)))
1008 && X_SIMM13 (insn
) == 68 + (regnum
- SPARC_I0_REGNUM
) * 4)
1021 /* Normal frames. */
1023 struct sparc_frame_cache
*
1024 sparc_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1026 struct sparc_frame_cache
*cache
;
1031 cache
= sparc_alloc_frame_cache ();
1032 *this_cache
= cache
;
1034 cache
->pc
= get_frame_func (this_frame
);
1036 sparc_analyze_prologue (get_frame_arch (this_frame
), cache
->pc
,
1037 get_frame_pc (this_frame
), cache
);
1039 if (cache
->frameless_p
)
1041 /* This function is frameless, so %fp (%i6) holds the frame
1042 pointer for our calling frame. Use %sp (%o6) as this frame's
1045 get_frame_register_unsigned (this_frame
, SPARC_SP_REGNUM
);
1049 /* For normal frames, %fp (%i6) holds the frame pointer, the
1050 base address for the current stack frame. */
1052 get_frame_register_unsigned (this_frame
, SPARC_FP_REGNUM
);
1055 cache
->base
+= cache
->frame_offset
;
1057 if (cache
->base
& 1)
1058 cache
->base
+= BIAS
;
1064 sparc32_struct_return_from_sym (struct symbol
*sym
)
1066 struct type
*type
= check_typedef (SYMBOL_TYPE (sym
));
1067 enum type_code code
= TYPE_CODE (type
);
1069 if (code
== TYPE_CODE_FUNC
|| code
== TYPE_CODE_METHOD
)
1071 type
= check_typedef (TYPE_TARGET_TYPE (type
));
1072 if (sparc_structure_or_union_p (type
)
1073 || (sparc_floating_p (type
) && TYPE_LENGTH (type
) == 16))
1080 struct sparc_frame_cache
*
1081 sparc32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1083 struct sparc_frame_cache
*cache
;
1089 cache
= sparc_frame_cache (this_frame
, this_cache
);
1091 sym
= find_pc_function (cache
->pc
);
1094 cache
->struct_return_p
= sparc32_struct_return_from_sym (sym
);
1098 /* There is no debugging information for this function to
1099 help us determine whether this function returns a struct
1100 or not. So we rely on another heuristic which is to check
1101 the instruction at the return address and see if this is
1102 an "unimp" instruction. If it is, then it is a struct-return
1106 (cache
->copied_regs_mask
& 0x80) ? SPARC_I7_REGNUM
: SPARC_O7_REGNUM
;
1108 pc
= get_frame_register_unsigned (this_frame
, regnum
) + 8;
1109 if (sparc_is_unimp_insn (pc
))
1110 cache
->struct_return_p
= 1;
1117 sparc32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1118 struct frame_id
*this_id
)
1120 struct sparc_frame_cache
*cache
=
1121 sparc32_frame_cache (this_frame
, this_cache
);
1123 /* This marks the outermost frame. */
1124 if (cache
->base
== 0)
1127 (*this_id
) = frame_id_build (cache
->base
, cache
->pc
);
1130 static struct value
*
1131 sparc32_frame_prev_register (struct frame_info
*this_frame
,
1132 void **this_cache
, int regnum
)
1134 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1135 struct sparc_frame_cache
*cache
=
1136 sparc32_frame_cache (this_frame
, this_cache
);
1138 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== SPARC32_NPC_REGNUM
)
1140 CORE_ADDR pc
= (regnum
== SPARC32_NPC_REGNUM
) ? 4 : 0;
1142 /* If this functions has a Structure, Union or Quad-Precision
1143 return value, we have to skip the UNIMP instruction that encodes
1144 the size of the structure. */
1145 if (cache
->struct_return_p
)
1149 (cache
->copied_regs_mask
& 0x80) ? SPARC_I7_REGNUM
: SPARC_O7_REGNUM
;
1150 pc
+= get_frame_register_unsigned (this_frame
, regnum
) + 8;
1151 return frame_unwind_got_constant (this_frame
, regnum
, pc
);
1154 /* Handle StackGhost. */
1156 ULONGEST wcookie
= sparc_fetch_wcookie (gdbarch
);
1158 if (wcookie
!= 0 && !cache
->frameless_p
&& regnum
== SPARC_I7_REGNUM
)
1160 CORE_ADDR addr
= cache
->base
+ (regnum
- SPARC_L0_REGNUM
) * 4;
1163 /* Read the value in from memory. */
1164 i7
= get_frame_memory_unsigned (this_frame
, addr
, 4);
1165 return frame_unwind_got_constant (this_frame
, regnum
, i7
^ wcookie
);
1169 /* The previous frame's `local' and `in' registers may have been saved
1170 in the register save area. */
1171 if (regnum
>= SPARC_L0_REGNUM
&& regnum
<= SPARC_I7_REGNUM
1172 && (cache
->saved_regs_mask
& (1 << (regnum
- SPARC_L0_REGNUM
))))
1174 CORE_ADDR addr
= cache
->base
+ (regnum
- SPARC_L0_REGNUM
) * 4;
1176 return frame_unwind_got_memory (this_frame
, regnum
, addr
);
1179 /* The previous frame's `out' registers may be accessible as the current
1180 frame's `in' registers. */
1181 if (regnum
>= SPARC_O0_REGNUM
&& regnum
<= SPARC_O7_REGNUM
1182 && (cache
->copied_regs_mask
& (1 << (regnum
- SPARC_O0_REGNUM
))))
1183 regnum
+= (SPARC_I0_REGNUM
- SPARC_O0_REGNUM
);
1185 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1188 static const struct frame_unwind sparc32_frame_unwind
=
1191 default_frame_unwind_stop_reason
,
1192 sparc32_frame_this_id
,
1193 sparc32_frame_prev_register
,
1195 default_frame_sniffer
1200 sparc32_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
1202 struct sparc_frame_cache
*cache
=
1203 sparc32_frame_cache (this_frame
, this_cache
);
1208 static const struct frame_base sparc32_frame_base
=
1210 &sparc32_frame_unwind
,
1211 sparc32_frame_base_address
,
1212 sparc32_frame_base_address
,
1213 sparc32_frame_base_address
1216 static struct frame_id
1217 sparc_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1221 sp
= get_frame_register_unsigned (this_frame
, SPARC_SP_REGNUM
);
1224 return frame_id_build (sp
, get_frame_pc (this_frame
));
1228 /* Extract a function return value of TYPE from REGCACHE, and copy
1229 that into VALBUF. */
1232 sparc32_extract_return_value (struct type
*type
, struct regcache
*regcache
,
1235 int len
= TYPE_LENGTH (type
);
1238 gdb_assert (!sparc_structure_or_union_p (type
));
1239 gdb_assert (!(sparc_floating_p (type
) && len
== 16));
1241 if (sparc_floating_p (type
))
1243 /* Floating return values. */
1244 regcache_cooked_read (regcache
, SPARC_F0_REGNUM
, buf
);
1246 regcache_cooked_read (regcache
, SPARC_F1_REGNUM
, buf
+ 4);
1247 memcpy (valbuf
, buf
, len
);
1251 /* Integral and pointer return values. */
1252 gdb_assert (sparc_integral_or_pointer_p (type
));
1254 regcache_cooked_read (regcache
, SPARC_O0_REGNUM
, buf
);
1257 regcache_cooked_read (regcache
, SPARC_O1_REGNUM
, buf
+ 4);
1258 gdb_assert (len
== 8);
1259 memcpy (valbuf
, buf
, 8);
1263 /* Just stripping off any unused bytes should preserve the
1264 signed-ness just fine. */
1265 memcpy (valbuf
, buf
+ 4 - len
, len
);
1270 /* Store the function return value of type TYPE from VALBUF into
1274 sparc32_store_return_value (struct type
*type
, struct regcache
*regcache
,
1275 const gdb_byte
*valbuf
)
1277 int len
= TYPE_LENGTH (type
);
1280 gdb_assert (!sparc_structure_or_union_p (type
));
1281 gdb_assert (!(sparc_floating_p (type
) && len
== 16));
1282 gdb_assert (len
<= 8);
1284 if (sparc_floating_p (type
))
1286 /* Floating return values. */
1287 memcpy (buf
, valbuf
, len
);
1288 regcache_cooked_write (regcache
, SPARC_F0_REGNUM
, buf
);
1290 regcache_cooked_write (regcache
, SPARC_F1_REGNUM
, buf
+ 4);
1294 /* Integral and pointer return values. */
1295 gdb_assert (sparc_integral_or_pointer_p (type
));
1299 gdb_assert (len
== 8);
1300 memcpy (buf
, valbuf
, 8);
1301 regcache_cooked_write (regcache
, SPARC_O1_REGNUM
, buf
+ 4);
1305 /* ??? Do we need to do any sign-extension here? */
1306 memcpy (buf
+ 4 - len
, valbuf
, len
);
1308 regcache_cooked_write (regcache
, SPARC_O0_REGNUM
, buf
);
1312 static enum return_value_convention
1313 sparc32_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
1314 struct type
*type
, struct regcache
*regcache
,
1315 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1317 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1319 /* The psABI says that "...every stack frame reserves the word at
1320 %fp+64. If a function returns a structure, union, or
1321 quad-precision value, this word should hold the address of the
1322 object into which the return value should be copied." This
1323 guarantees that we can always find the return value, not just
1324 before the function returns. */
1326 if (sparc_structure_or_union_p (type
)
1327 || (sparc_floating_p (type
) && TYPE_LENGTH (type
) == 16))
1334 regcache_cooked_read_unsigned (regcache
, SPARC_SP_REGNUM
, &sp
);
1335 addr
= read_memory_unsigned_integer (sp
+ 64, 4, byte_order
);
1336 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
1339 return RETURN_VALUE_ABI_PRESERVES_ADDRESS
;
1343 sparc32_extract_return_value (type
, regcache
, readbuf
);
1345 sparc32_store_return_value (type
, regcache
, writebuf
);
1347 return RETURN_VALUE_REGISTER_CONVENTION
;
1351 sparc32_stabs_argument_has_addr (struct gdbarch
*gdbarch
, struct type
*type
)
1353 return (sparc_structure_or_union_p (type
)
1354 || (sparc_floating_p (type
) && TYPE_LENGTH (type
) == 16));
1358 sparc32_dwarf2_struct_return_p (struct frame_info
*this_frame
)
1360 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
1361 struct symbol
*sym
= find_pc_function (pc
);
1364 return sparc32_struct_return_from_sym (sym
);
1369 sparc32_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1370 struct dwarf2_frame_state_reg
*reg
,
1371 struct frame_info
*this_frame
)
1377 case SPARC_G0_REGNUM
:
1378 /* Since %g0 is always zero, there is no point in saving it, and
1379 people will be inclined omit it from the CFI. Make sure we
1380 don't warn about that. */
1381 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
1383 case SPARC_SP_REGNUM
:
1384 reg
->how
= DWARF2_FRAME_REG_CFA
;
1386 case SPARC32_PC_REGNUM
:
1387 case SPARC32_NPC_REGNUM
:
1388 reg
->how
= DWARF2_FRAME_REG_RA_OFFSET
;
1390 if (sparc32_dwarf2_struct_return_p (this_frame
))
1392 if (regnum
== SPARC32_NPC_REGNUM
)
1394 reg
->loc
.offset
= off
;
1400 /* The SPARC Architecture doesn't have hardware single-step support,
1401 and most operating systems don't implement it either, so we provide
1402 software single-step mechanism. */
1405 sparc_analyze_control_transfer (struct frame_info
*frame
,
1406 CORE_ADDR pc
, CORE_ADDR
*npc
)
1408 unsigned long insn
= sparc_fetch_instruction (pc
);
1409 int conditional_p
= X_COND (insn
) & 0x7;
1411 long offset
= 0; /* Must be signed for sign-extend. */
1413 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 3 && (insn
& 0x1000000) == 0)
1415 /* Branch on Integer Register with Prediction (BPr). */
1419 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 6)
1421 /* Branch on Floating-Point Condition Codes (FBfcc). */
1423 offset
= 4 * X_DISP22 (insn
);
1425 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 5)
1427 /* Branch on Floating-Point Condition Codes with Prediction
1430 offset
= 4 * X_DISP19 (insn
);
1432 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 2)
1434 /* Branch on Integer Condition Codes (Bicc). */
1436 offset
= 4 * X_DISP22 (insn
);
1438 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 1)
1440 /* Branch on Integer Condition Codes with Prediction (BPcc). */
1442 offset
= 4 * X_DISP19 (insn
);
1444 else if (X_OP (insn
) == 2 && X_OP3 (insn
) == 0x3a)
1446 /* Trap instruction (TRAP). */
1447 return gdbarch_tdep (get_frame_arch (frame
))->step_trap (frame
, insn
);
1450 /* FIXME: Handle DONE and RETRY instructions. */
1456 /* For conditional branches, return nPC + 4 iff the annul
1458 return (X_A (insn
) ? *npc
+ 4 : 0);
1462 /* For unconditional branches, return the target if its
1463 specified condition is "always" and return nPC + 4 if the
1464 condition is "never". If the annul bit is 1, set *NPC to
1466 if (X_COND (insn
) == 0x0)
1467 pc
= *npc
, offset
= 4;
1471 gdb_assert (offset
!= 0);
1480 sparc_step_trap (struct frame_info
*frame
, unsigned long insn
)
1486 sparc_software_single_step (struct frame_info
*frame
)
1488 struct gdbarch
*arch
= get_frame_arch (frame
);
1489 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
1490 struct address_space
*aspace
= get_frame_address_space (frame
);
1491 CORE_ADDR npc
, nnpc
;
1493 CORE_ADDR pc
, orig_npc
;
1495 pc
= get_frame_register_unsigned (frame
, tdep
->pc_regnum
);
1496 orig_npc
= npc
= get_frame_register_unsigned (frame
, tdep
->npc_regnum
);
1498 /* Analyze the instruction at PC. */
1499 nnpc
= sparc_analyze_control_transfer (frame
, pc
, &npc
);
1501 insert_single_step_breakpoint (arch
, aspace
, npc
);
1504 insert_single_step_breakpoint (arch
, aspace
, nnpc
);
1506 /* Assert that we have set at least one breakpoint, and that
1507 they're not set at the same spot - unless we're going
1508 from here straight to NULL, i.e. a call or jump to 0. */
1509 gdb_assert (npc
!= 0 || nnpc
!= 0 || orig_npc
== 0);
1510 gdb_assert (nnpc
!= npc
|| orig_npc
== 0);
1516 sparc_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1518 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_regcache_arch (regcache
));
1520 regcache_cooked_write_unsigned (regcache
, tdep
->pc_regnum
, pc
);
1521 regcache_cooked_write_unsigned (regcache
, tdep
->npc_regnum
, pc
+ 4);
1525 /* Return the appropriate register set for the core section identified
1526 by SECT_NAME and SECT_SIZE. */
1528 static const struct regset
*
1529 sparc_regset_from_core_section (struct gdbarch
*gdbarch
,
1530 const char *sect_name
, size_t sect_size
)
1532 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1534 if (strcmp (sect_name
, ".reg") == 0 && sect_size
>= tdep
->sizeof_gregset
)
1535 return tdep
->gregset
;
1537 if (strcmp (sect_name
, ".reg2") == 0 && sect_size
>= tdep
->sizeof_fpregset
)
1538 return tdep
->fpregset
;
1544 static struct gdbarch
*
1545 sparc32_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1547 struct gdbarch_tdep
*tdep
;
1548 struct gdbarch
*gdbarch
;
1550 /* If there is already a candidate, use it. */
1551 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
1553 return arches
->gdbarch
;
1555 /* Allocate space for the new architecture. */
1556 tdep
= XZALLOC (struct gdbarch_tdep
);
1557 gdbarch
= gdbarch_alloc (&info
, tdep
);
1559 tdep
->pc_regnum
= SPARC32_PC_REGNUM
;
1560 tdep
->npc_regnum
= SPARC32_NPC_REGNUM
;
1561 tdep
->step_trap
= sparc_step_trap
;
1563 set_gdbarch_long_double_bit (gdbarch
, 128);
1564 set_gdbarch_long_double_format (gdbarch
, floatformats_sparc_quad
);
1566 set_gdbarch_num_regs (gdbarch
, SPARC32_NUM_REGS
);
1567 set_gdbarch_register_name (gdbarch
, sparc32_register_name
);
1568 set_gdbarch_register_type (gdbarch
, sparc32_register_type
);
1569 set_gdbarch_num_pseudo_regs (gdbarch
, SPARC32_NUM_PSEUDO_REGS
);
1570 set_gdbarch_pseudo_register_read (gdbarch
, sparc32_pseudo_register_read
);
1571 set_gdbarch_pseudo_register_write (gdbarch
, sparc32_pseudo_register_write
);
1573 /* Register numbers of various important registers. */
1574 set_gdbarch_sp_regnum (gdbarch
, SPARC_SP_REGNUM
); /* %sp */
1575 set_gdbarch_pc_regnum (gdbarch
, SPARC32_PC_REGNUM
); /* %pc */
1576 set_gdbarch_fp0_regnum (gdbarch
, SPARC_F0_REGNUM
); /* %f0 */
1578 /* Call dummy code. */
1579 set_gdbarch_frame_align (gdbarch
, sparc32_frame_align
);
1580 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
1581 set_gdbarch_push_dummy_code (gdbarch
, sparc32_push_dummy_code
);
1582 set_gdbarch_push_dummy_call (gdbarch
, sparc32_push_dummy_call
);
1584 set_gdbarch_return_value (gdbarch
, sparc32_return_value
);
1585 set_gdbarch_stabs_argument_has_addr
1586 (gdbarch
, sparc32_stabs_argument_has_addr
);
1588 set_gdbarch_skip_prologue (gdbarch
, sparc32_skip_prologue
);
1590 /* Stack grows downward. */
1591 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
1593 set_gdbarch_breakpoint_from_pc (gdbarch
, sparc_breakpoint_from_pc
);
1595 set_gdbarch_frame_args_skip (gdbarch
, 8);
1597 set_gdbarch_print_insn (gdbarch
, print_insn_sparc
);
1599 set_gdbarch_software_single_step (gdbarch
, sparc_software_single_step
);
1600 set_gdbarch_write_pc (gdbarch
, sparc_write_pc
);
1602 set_gdbarch_dummy_id (gdbarch
, sparc_dummy_id
);
1604 set_gdbarch_unwind_pc (gdbarch
, sparc_unwind_pc
);
1606 frame_base_set_default (gdbarch
, &sparc32_frame_base
);
1608 /* Hook in the DWARF CFI frame unwinder. */
1609 dwarf2_frame_set_init_reg (gdbarch
, sparc32_dwarf2_frame_init_reg
);
1610 /* FIXME: kettenis/20050423: Don't enable the unwinder until the
1611 StackGhost issues have been resolved. */
1613 /* Hook in ABI-specific overrides, if they have been registered. */
1614 gdbarch_init_osabi (info
, gdbarch
);
1616 frame_unwind_append_unwinder (gdbarch
, &sparc32_frame_unwind
);
1618 /* If we have register sets, enable the generic core file support. */
1620 set_gdbarch_regset_from_core_section (gdbarch
,
1621 sparc_regset_from_core_section
);
1626 /* Helper functions for dealing with register windows. */
1629 sparc_supply_rwindow (struct regcache
*regcache
, CORE_ADDR sp
, int regnum
)
1631 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1632 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1639 /* Registers are 64-bit. */
1642 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1644 if (regnum
== i
|| regnum
== -1)
1646 target_read_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 8), buf
, 8);
1648 /* Handle StackGhost. */
1649 if (i
== SPARC_I7_REGNUM
)
1651 ULONGEST wcookie
= sparc_fetch_wcookie (gdbarch
);
1654 i7
= extract_unsigned_integer (buf
+ offset
, 8, byte_order
);
1655 store_unsigned_integer (buf
+ offset
, 8, byte_order
,
1659 regcache_raw_supply (regcache
, i
, buf
);
1665 /* Registers are 32-bit. Toss any sign-extension of the stack
1669 /* Clear out the top half of the temporary buffer, and put the
1670 register value in the bottom half if we're in 64-bit mode. */
1671 if (gdbarch_ptr_bit (get_regcache_arch (regcache
)) == 64)
1677 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1679 if (regnum
== i
|| regnum
== -1)
1681 target_read_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 4),
1684 /* Handle StackGhost. */
1685 if (i
== SPARC_I7_REGNUM
)
1687 ULONGEST wcookie
= sparc_fetch_wcookie (gdbarch
);
1690 i7
= extract_unsigned_integer (buf
+ offset
, 4, byte_order
);
1691 store_unsigned_integer (buf
+ offset
, 4, byte_order
,
1695 regcache_raw_supply (regcache
, i
, buf
);
1702 sparc_collect_rwindow (const struct regcache
*regcache
,
1703 CORE_ADDR sp
, int regnum
)
1705 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1706 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1713 /* Registers are 64-bit. */
1716 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1718 if (regnum
== -1 || regnum
== SPARC_SP_REGNUM
|| regnum
== i
)
1720 regcache_raw_collect (regcache
, i
, buf
);
1722 /* Handle StackGhost. */
1723 if (i
== SPARC_I7_REGNUM
)
1725 ULONGEST wcookie
= sparc_fetch_wcookie (gdbarch
);
1728 i7
= extract_unsigned_integer (buf
+ offset
, 8, byte_order
);
1729 store_unsigned_integer (buf
, 8, byte_order
, i7
^ wcookie
);
1732 target_write_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 8), buf
, 8);
1738 /* Registers are 32-bit. Toss any sign-extension of the stack
1742 /* Only use the bottom half if we're in 64-bit mode. */
1743 if (gdbarch_ptr_bit (get_regcache_arch (regcache
)) == 64)
1746 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1748 if (regnum
== -1 || regnum
== SPARC_SP_REGNUM
|| regnum
== i
)
1750 regcache_raw_collect (regcache
, i
, buf
);
1752 /* Handle StackGhost. */
1753 if (i
== SPARC_I7_REGNUM
)
1755 ULONGEST wcookie
= sparc_fetch_wcookie (gdbarch
);
1758 i7
= extract_unsigned_integer (buf
+ offset
, 4, byte_order
);
1759 store_unsigned_integer (buf
+ offset
, 4, byte_order
,
1763 target_write_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 4),
1770 /* Helper functions for dealing with register sets. */
1773 sparc32_supply_gregset (const struct sparc_gregset
*gregset
,
1774 struct regcache
*regcache
,
1775 int regnum
, const void *gregs
)
1777 const gdb_byte
*regs
= gregs
;
1778 gdb_byte zero
[4] = { 0 };
1781 if (regnum
== SPARC32_PSR_REGNUM
|| regnum
== -1)
1782 regcache_raw_supply (regcache
, SPARC32_PSR_REGNUM
,
1783 regs
+ gregset
->r_psr_offset
);
1785 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== -1)
1786 regcache_raw_supply (regcache
, SPARC32_PC_REGNUM
,
1787 regs
+ gregset
->r_pc_offset
);
1789 if (regnum
== SPARC32_NPC_REGNUM
|| regnum
== -1)
1790 regcache_raw_supply (regcache
, SPARC32_NPC_REGNUM
,
1791 regs
+ gregset
->r_npc_offset
);
1793 if (regnum
== SPARC32_Y_REGNUM
|| regnum
== -1)
1794 regcache_raw_supply (regcache
, SPARC32_Y_REGNUM
,
1795 regs
+ gregset
->r_y_offset
);
1797 if (regnum
== SPARC_G0_REGNUM
|| regnum
== -1)
1798 regcache_raw_supply (regcache
, SPARC_G0_REGNUM
, &zero
);
1800 if ((regnum
>= SPARC_G1_REGNUM
&& regnum
<= SPARC_O7_REGNUM
) || regnum
== -1)
1802 int offset
= gregset
->r_g1_offset
;
1804 for (i
= SPARC_G1_REGNUM
; i
<= SPARC_O7_REGNUM
; i
++)
1806 if (regnum
== i
|| regnum
== -1)
1807 regcache_raw_supply (regcache
, i
, regs
+ offset
);
1812 if ((regnum
>= SPARC_L0_REGNUM
&& regnum
<= SPARC_I7_REGNUM
) || regnum
== -1)
1814 /* Not all of the register set variants include Locals and
1815 Inputs. For those that don't, we read them off the stack. */
1816 if (gregset
->r_l0_offset
== -1)
1820 regcache_cooked_read_unsigned (regcache
, SPARC_SP_REGNUM
, &sp
);
1821 sparc_supply_rwindow (regcache
, sp
, regnum
);
1825 int offset
= gregset
->r_l0_offset
;
1827 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1829 if (regnum
== i
|| regnum
== -1)
1830 regcache_raw_supply (regcache
, i
, regs
+ offset
);
1838 sparc32_collect_gregset (const struct sparc_gregset
*gregset
,
1839 const struct regcache
*regcache
,
1840 int regnum
, void *gregs
)
1842 gdb_byte
*regs
= gregs
;
1845 if (regnum
== SPARC32_PSR_REGNUM
|| regnum
== -1)
1846 regcache_raw_collect (regcache
, SPARC32_PSR_REGNUM
,
1847 regs
+ gregset
->r_psr_offset
);
1849 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== -1)
1850 regcache_raw_collect (regcache
, SPARC32_PC_REGNUM
,
1851 regs
+ gregset
->r_pc_offset
);
1853 if (regnum
== SPARC32_NPC_REGNUM
|| regnum
== -1)
1854 regcache_raw_collect (regcache
, SPARC32_NPC_REGNUM
,
1855 regs
+ gregset
->r_npc_offset
);
1857 if (regnum
== SPARC32_Y_REGNUM
|| regnum
== -1)
1858 regcache_raw_collect (regcache
, SPARC32_Y_REGNUM
,
1859 regs
+ gregset
->r_y_offset
);
1861 if ((regnum
>= SPARC_G1_REGNUM
&& regnum
<= SPARC_O7_REGNUM
) || regnum
== -1)
1863 int offset
= gregset
->r_g1_offset
;
1865 /* %g0 is always zero. */
1866 for (i
= SPARC_G1_REGNUM
; i
<= SPARC_O7_REGNUM
; i
++)
1868 if (regnum
== i
|| regnum
== -1)
1869 regcache_raw_collect (regcache
, i
, regs
+ offset
);
1874 if ((regnum
>= SPARC_L0_REGNUM
&& regnum
<= SPARC_I7_REGNUM
) || regnum
== -1)
1876 /* Not all of the register set variants include Locals and
1877 Inputs. For those that don't, we read them off the stack. */
1878 if (gregset
->r_l0_offset
!= -1)
1880 int offset
= gregset
->r_l0_offset
;
1882 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1884 if (regnum
== i
|| regnum
== -1)
1885 regcache_raw_collect (regcache
, i
, regs
+ offset
);
1893 sparc32_supply_fpregset (struct regcache
*regcache
,
1894 int regnum
, const void *fpregs
)
1896 const gdb_byte
*regs
= fpregs
;
1899 for (i
= 0; i
< 32; i
++)
1901 if (regnum
== (SPARC_F0_REGNUM
+ i
) || regnum
== -1)
1902 regcache_raw_supply (regcache
, SPARC_F0_REGNUM
+ i
, regs
+ (i
* 4));
1905 if (regnum
== SPARC32_FSR_REGNUM
|| regnum
== -1)
1906 regcache_raw_supply (regcache
, SPARC32_FSR_REGNUM
, regs
+ (32 * 4) + 4);
1910 sparc32_collect_fpregset (const struct regcache
*regcache
,
1911 int regnum
, void *fpregs
)
1913 gdb_byte
*regs
= fpregs
;
1916 for (i
= 0; i
< 32; i
++)
1918 if (regnum
== (SPARC_F0_REGNUM
+ i
) || regnum
== -1)
1919 regcache_raw_collect (regcache
, SPARC_F0_REGNUM
+ i
, regs
+ (i
* 4));
1922 if (regnum
== SPARC32_FSR_REGNUM
|| regnum
== -1)
1923 regcache_raw_collect (regcache
, SPARC32_FSR_REGNUM
, regs
+ (32 * 4) + 4);
1929 /* From <machine/reg.h>. */
1930 const struct sparc_gregset sparc32_sunos4_gregset
=
1943 /* Provide a prototype to silence -Wmissing-prototypes. */
1944 void _initialize_sparc_tdep (void);
1947 _initialize_sparc_tdep (void)
1949 register_gdbarch_init (bfd_arch_sparc
, sparc32_gdbarch_init
);