1 /* Target-dependent code for SPARC.
3 Copyright (C) 2003-2017 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "arch-utils.h"
23 #include "dwarf2-frame.h"
24 #include "floatformat.h"
26 #include "frame-base.h"
27 #include "frame-unwind.h"
38 #include "sparc-tdep.h"
39 #include "sparc-ravenscar-thread.h"
44 /* This file implements the SPARC 32-bit ABI as defined by the section
45 "Low-Level System Information" of the SPARC Compliance Definition
46 (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC. The SCD
47 lists changes with respect to the original 32-bit psABI as defined
48 in the "System V ABI, SPARC Processor Supplement".
50 Note that if we talk about SunOS, we mean SunOS 4.x, which was
51 BSD-based, which is sometimes (retroactively?) referred to as
52 Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and
53 above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9
54 suffering from severe version number inflation). Solaris 2.x is
55 also known as SunOS 5.x, since that's what uname(1) says. Solaris
58 /* Please use the sparc32_-prefix for 32-bit specific code, the
59 sparc64_-prefix for 64-bit specific code and the sparc_-prefix for
60 code that can handle both. The 64-bit specific code lives in
61 sparc64-tdep.c; don't add any here. */
63 /* The SPARC Floating-Point Quad-Precision format is similar to
64 big-endian IA-64 Quad-Precision format. */
65 #define floatformats_sparc_quad floatformats_ia64_quad
67 /* The stack pointer is offset from the stack frame by a BIAS of 2047
68 (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC
69 hosts, so undefine it first. */
73 /* Macros to extract fields from SPARC instructions. */
74 #define X_OP(i) (((i) >> 30) & 0x3)
75 #define X_RD(i) (((i) >> 25) & 0x1f)
76 #define X_A(i) (((i) >> 29) & 1)
77 #define X_COND(i) (((i) >> 25) & 0xf)
78 #define X_OP2(i) (((i) >> 22) & 0x7)
79 #define X_IMM22(i) ((i) & 0x3fffff)
80 #define X_OP3(i) (((i) >> 19) & 0x3f)
81 #define X_RS1(i) (((i) >> 14) & 0x1f)
82 #define X_RS2(i) ((i) & 0x1f)
83 #define X_I(i) (((i) >> 13) & 1)
84 /* Sign extension macros. */
85 #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000)
86 #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000)
87 #define X_DISP10(i) ((((((i) >> 11) && 0x300) | (((i) >> 5) & 0xff)) ^ 0x200) - 0x200)
88 #define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000)
89 /* Macros to identify some instructions. */
90 /* RETURN (RETT in V8) */
91 #define X_RETTURN(i) ((X_OP (i) == 0x2) && (X_OP3 (i) == 0x39))
93 /* Fetch the instruction at PC. Instructions are always big-endian
94 even if the processor operates in little-endian mode. */
97 sparc_fetch_instruction (CORE_ADDR pc
)
103 /* If we can't read the instruction at PC, return zero. */
104 if (target_read_memory (pc
, buf
, sizeof (buf
)))
108 for (i
= 0; i
< sizeof (buf
); i
++)
109 insn
= (insn
<< 8) | buf
[i
];
114 /* Return non-zero if the instruction corresponding to PC is an "unimp"
118 sparc_is_unimp_insn (CORE_ADDR pc
)
120 const unsigned long insn
= sparc_fetch_instruction (pc
);
122 return ((insn
& 0xc1c00000) == 0);
125 /* Return non-zero if the instruction corresponding to PC is an
126 "annulled" branch, i.e. the annul bit is set. */
129 sparc_is_annulled_branch_insn (CORE_ADDR pc
)
131 /* The branch instructions featuring an annul bit can be identified
132 by the following bit patterns:
135 OP2=1: Branch on Integer Condition Codes with Prediction (BPcc).
136 OP2=2: Branch on Integer Condition Codes (Bcc).
137 OP2=5: Branch on FP Condition Codes with Prediction (FBfcc).
138 OP2=6: Branch on FP Condition Codes (FBcc).
140 Branch on Integer Register with Prediction (BPr).
142 This leaves out ILLTRAP (OP2=0), SETHI/NOP (OP2=4) and the V8
143 coprocessor branch instructions (Op2=7). */
145 const unsigned long insn
= sparc_fetch_instruction (pc
);
146 const unsigned op2
= X_OP2 (insn
);
148 if ((X_OP (insn
) == 0)
149 && ((op2
== 1) || (op2
== 2) || (op2
== 5) || (op2
== 6)
150 || ((op2
== 3) && ((insn
& 0x10000000) == 0))))
156 /* OpenBSD/sparc includes StackGhost, which according to the author's
157 website http://stackghost.cerias.purdue.edu "... transparently and
158 automatically protects applications' stack frames; more
159 specifically, it guards the return pointers. The protection
160 mechanisms require no application source or binary modification and
161 imposes only a negligible performance penalty."
163 The same website provides the following description of how
166 "StackGhost interfaces with the kernel trap handler that would
167 normally write out registers to the stack and the handler that
168 would read them back in. By XORing a cookie into the
169 return-address saved in the user stack when it is actually written
170 to the stack, and then XOR it out when the return-address is pulled
171 from the stack, StackGhost can cause attacker corrupted return
172 pointers to behave in a manner the attacker cannot predict.
173 StackGhost can also use several unused bits in the return pointer
174 to detect a smashed return pointer and abort the process."
176 For GDB this means that whenever we're reading %i7 from a stack
177 frame's window save area, we'll have to XOR the cookie.
179 More information on StackGuard can be found on in:
181 Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated
182 Stack Protection." 2001. Published in USENIX Security Symposium
185 /* Fetch StackGhost Per-Process XOR cookie. */
188 sparc_fetch_wcookie (struct gdbarch
*gdbarch
)
190 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
191 struct target_ops
*ops
= ¤t_target
;
195 len
= target_read (ops
, TARGET_OBJECT_WCOOKIE
, NULL
, buf
, 0, 8);
199 /* We should have either an 32-bit or an 64-bit cookie. */
200 gdb_assert (len
== 4 || len
== 8);
202 return extract_unsigned_integer (buf
, len
, byte_order
);
206 /* The functions on this page are intended to be used to classify
207 function arguments. */
209 /* Check whether TYPE is "Integral or Pointer". */
212 sparc_integral_or_pointer_p (const struct type
*type
)
214 int len
= TYPE_LENGTH (type
);
216 switch (TYPE_CODE (type
))
222 case TYPE_CODE_RANGE
:
223 /* We have byte, half-word, word and extended-word/doubleword
224 integral types. The doubleword is an extension to the
225 original 32-bit ABI by the SCD 2.4.x. */
226 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
229 /* Allow either 32-bit or 64-bit pointers. */
230 return (len
== 4 || len
== 8);
238 /* Check whether TYPE is "Floating". */
241 sparc_floating_p (const struct type
*type
)
243 switch (TYPE_CODE (type
))
247 int len
= TYPE_LENGTH (type
);
248 return (len
== 4 || len
== 8 || len
== 16);
257 /* Check whether TYPE is "Complex Floating". */
260 sparc_complex_floating_p (const struct type
*type
)
262 switch (TYPE_CODE (type
))
264 case TYPE_CODE_COMPLEX
:
266 int len
= TYPE_LENGTH (type
);
267 return (len
== 8 || len
== 16 || len
== 32);
276 /* Check whether TYPE is "Structure or Union".
278 In terms of Ada subprogram calls, arrays are treated the same as
279 struct and union types. So this function also returns non-zero
283 sparc_structure_or_union_p (const struct type
*type
)
285 switch (TYPE_CODE (type
))
287 case TYPE_CODE_STRUCT
:
288 case TYPE_CODE_UNION
:
289 case TYPE_CODE_ARRAY
:
298 /* Register information. */
300 static const char *sparc32_register_names
[] =
302 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
303 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
304 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
305 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
307 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
308 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
309 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
310 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
312 "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr"
315 /* Total number of registers. */
316 #define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names)
318 /* We provide the aliases %d0..%d30 for the floating registers as
319 "psuedo" registers. */
321 static const char *sparc32_pseudo_register_names
[] =
323 "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14",
324 "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30"
327 /* Total number of pseudo registers. */
328 #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names)
330 /* Return the name of register REGNUM. */
333 sparc32_register_name (struct gdbarch
*gdbarch
, int regnum
)
335 if (regnum
>= 0 && regnum
< SPARC32_NUM_REGS
)
336 return sparc32_register_names
[regnum
];
338 if (regnum
< SPARC32_NUM_REGS
+ SPARC32_NUM_PSEUDO_REGS
)
339 return sparc32_pseudo_register_names
[regnum
- SPARC32_NUM_REGS
];
344 /* Construct types for ISA-specific registers. */
347 sparc_psr_type (struct gdbarch
*gdbarch
)
349 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
351 if (!tdep
->sparc_psr_type
)
355 type
= arch_flags_type (gdbarch
, "builtin_type_sparc_psr", 4);
356 append_flags_type_flag (type
, 5, "ET");
357 append_flags_type_flag (type
, 6, "PS");
358 append_flags_type_flag (type
, 7, "S");
359 append_flags_type_flag (type
, 12, "EF");
360 append_flags_type_flag (type
, 13, "EC");
362 tdep
->sparc_psr_type
= type
;
365 return tdep
->sparc_psr_type
;
369 sparc_fsr_type (struct gdbarch
*gdbarch
)
371 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
373 if (!tdep
->sparc_fsr_type
)
377 type
= arch_flags_type (gdbarch
, "builtin_type_sparc_fsr", 4);
378 append_flags_type_flag (type
, 0, "NXA");
379 append_flags_type_flag (type
, 1, "DZA");
380 append_flags_type_flag (type
, 2, "UFA");
381 append_flags_type_flag (type
, 3, "OFA");
382 append_flags_type_flag (type
, 4, "NVA");
383 append_flags_type_flag (type
, 5, "NXC");
384 append_flags_type_flag (type
, 6, "DZC");
385 append_flags_type_flag (type
, 7, "UFC");
386 append_flags_type_flag (type
, 8, "OFC");
387 append_flags_type_flag (type
, 9, "NVC");
388 append_flags_type_flag (type
, 22, "NS");
389 append_flags_type_flag (type
, 23, "NXM");
390 append_flags_type_flag (type
, 24, "DZM");
391 append_flags_type_flag (type
, 25, "UFM");
392 append_flags_type_flag (type
, 26, "OFM");
393 append_flags_type_flag (type
, 27, "NVM");
395 tdep
->sparc_fsr_type
= type
;
398 return tdep
->sparc_fsr_type
;
401 /* Return the GDB type object for the "standard" data type of data in
405 sparc32_register_type (struct gdbarch
*gdbarch
, int regnum
)
407 if (regnum
>= SPARC_F0_REGNUM
&& regnum
<= SPARC_F31_REGNUM
)
408 return builtin_type (gdbarch
)->builtin_float
;
410 if (regnum
>= SPARC32_D0_REGNUM
&& regnum
<= SPARC32_D30_REGNUM
)
411 return builtin_type (gdbarch
)->builtin_double
;
413 if (regnum
== SPARC_SP_REGNUM
|| regnum
== SPARC_FP_REGNUM
)
414 return builtin_type (gdbarch
)->builtin_data_ptr
;
416 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== SPARC32_NPC_REGNUM
)
417 return builtin_type (gdbarch
)->builtin_func_ptr
;
419 if (regnum
== SPARC32_PSR_REGNUM
)
420 return sparc_psr_type (gdbarch
);
422 if (regnum
== SPARC32_FSR_REGNUM
)
423 return sparc_fsr_type (gdbarch
);
425 return builtin_type (gdbarch
)->builtin_int32
;
428 static enum register_status
429 sparc32_pseudo_register_read (struct gdbarch
*gdbarch
,
430 struct regcache
*regcache
,
431 int regnum
, gdb_byte
*buf
)
433 enum register_status status
;
435 gdb_assert (regnum
>= SPARC32_D0_REGNUM
&& regnum
<= SPARC32_D30_REGNUM
);
437 regnum
= SPARC_F0_REGNUM
+ 2 * (regnum
- SPARC32_D0_REGNUM
);
438 status
= regcache_raw_read (regcache
, regnum
, buf
);
439 if (status
== REG_VALID
)
440 status
= regcache_raw_read (regcache
, regnum
+ 1, buf
+ 4);
445 sparc32_pseudo_register_write (struct gdbarch
*gdbarch
,
446 struct regcache
*regcache
,
447 int regnum
, const gdb_byte
*buf
)
449 gdb_assert (regnum
>= SPARC32_D0_REGNUM
&& regnum
<= SPARC32_D30_REGNUM
);
451 regnum
= SPARC_F0_REGNUM
+ 2 * (regnum
- SPARC32_D0_REGNUM
);
452 regcache_raw_write (regcache
, regnum
, buf
);
453 regcache_raw_write (regcache
, regnum
+ 1, buf
+ 4);
456 /* Implement the stack_frame_destroyed_p gdbarch method. */
459 sparc_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
461 /* This function must return true if we are one instruction after an
462 instruction that destroyed the stack frame of the current
463 function. The SPARC instructions used to restore the callers
464 stack frame are RESTORE and RETURN/RETT.
466 Of these RETURN/RETT is a branch instruction and thus we return
467 true if we are in its delay slot.
469 RESTORE is almost always found in the delay slot of a branch
470 instruction that transfers control to the caller, such as JMPL.
471 Thus the next instruction is in the caller frame and we don't
472 need to do anything about it. */
474 unsigned int insn
= sparc_fetch_instruction (pc
- 4);
476 return X_RETTURN (insn
);
481 sparc32_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR address
)
483 /* The ABI requires double-word alignment. */
484 return address
& ~0x7;
488 sparc32_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
490 struct value
**args
, int nargs
,
491 struct type
*value_type
,
492 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
493 struct regcache
*regcache
)
495 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
500 if (using_struct_return (gdbarch
, NULL
, value_type
))
504 /* This is an UNIMP instruction. */
505 store_unsigned_integer (buf
, 4, byte_order
,
506 TYPE_LENGTH (value_type
) & 0x1fff);
507 write_memory (sp
- 8, buf
, 4);
515 sparc32_store_arguments (struct regcache
*regcache
, int nargs
,
516 struct value
**args
, CORE_ADDR sp
,
517 int struct_return
, CORE_ADDR struct_addr
)
519 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
520 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
521 /* Number of words in the "parameter array". */
522 int num_elements
= 0;
526 for (i
= 0; i
< nargs
; i
++)
528 struct type
*type
= value_type (args
[i
]);
529 int len
= TYPE_LENGTH (type
);
531 if (sparc_structure_or_union_p (type
)
532 || (sparc_floating_p (type
) && len
== 16)
533 || sparc_complex_floating_p (type
))
535 /* Structure, Union and Quad-Precision Arguments. */
538 /* Use doubleword alignment for these values. That's always
539 correct, and wasting a few bytes shouldn't be a problem. */
542 write_memory (sp
, value_contents (args
[i
]), len
);
543 args
[i
] = value_from_pointer (lookup_pointer_type (type
), sp
);
546 else if (sparc_floating_p (type
))
548 /* Floating arguments. */
549 gdb_assert (len
== 4 || len
== 8);
550 num_elements
+= (len
/ 4);
554 /* Integral and pointer arguments. */
555 gdb_assert (sparc_integral_or_pointer_p (type
));
558 args
[i
] = value_cast (builtin_type (gdbarch
)->builtin_int32
,
560 num_elements
+= ((len
+ 3) / 4);
564 /* Always allocate at least six words. */
565 sp
-= std::max (6, num_elements
) * 4;
567 /* The psABI says that "Software convention requires space for the
568 struct/union return value pointer, even if the word is unused." */
571 /* The psABI says that "Although software convention and the
572 operating system require every stack frame to be doubleword
576 for (i
= 0; i
< nargs
; i
++)
578 const bfd_byte
*valbuf
= value_contents (args
[i
]);
579 struct type
*type
= value_type (args
[i
]);
580 int len
= TYPE_LENGTH (type
);
582 gdb_assert (len
== 4 || len
== 8);
586 int regnum
= SPARC_O0_REGNUM
+ element
;
588 regcache_cooked_write (regcache
, regnum
, valbuf
);
589 if (len
> 4 && element
< 5)
590 regcache_cooked_write (regcache
, regnum
+ 1, valbuf
+ 4);
593 /* Always store the argument in memory. */
594 write_memory (sp
+ 4 + element
* 4, valbuf
, len
);
598 gdb_assert (element
== num_elements
);
604 store_unsigned_integer (buf
, 4, byte_order
, struct_addr
);
605 write_memory (sp
, buf
, 4);
612 sparc32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
613 struct regcache
*regcache
, CORE_ADDR bp_addr
,
614 int nargs
, struct value
**args
, CORE_ADDR sp
,
615 int struct_return
, CORE_ADDR struct_addr
)
617 CORE_ADDR call_pc
= (struct_return
? (bp_addr
- 12) : (bp_addr
- 8));
619 /* Set return address. */
620 regcache_cooked_write_unsigned (regcache
, SPARC_O7_REGNUM
, call_pc
);
622 /* Set up function arguments. */
623 sp
= sparc32_store_arguments (regcache
, nargs
, args
, sp
,
624 struct_return
, struct_addr
);
626 /* Allocate the 16-word window save area. */
629 /* Stack should be doubleword aligned at this point. */
630 gdb_assert (sp
% 8 == 0);
632 /* Finally, update the stack pointer. */
633 regcache_cooked_write_unsigned (regcache
, SPARC_SP_REGNUM
, sp
);
639 /* Use the program counter to determine the contents and size of a
640 breakpoint instruction. Return a pointer to a string of bytes that
641 encode a breakpoint instruction, store the length of the string in
642 *LEN and optionally adjust *PC to point to the correct memory
643 location for inserting the breakpoint. */
644 constexpr gdb_byte sparc_break_insn
[] = { 0x91, 0xd0, 0x20, 0x01 };
646 typedef BP_MANIPULATION (sparc_break_insn
) sparc_breakpoint
;
649 /* Allocate and initialize a frame cache. */
651 static struct sparc_frame_cache
*
652 sparc_alloc_frame_cache (void)
654 struct sparc_frame_cache
*cache
;
656 cache
= FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache
);
662 /* Frameless until proven otherwise. */
663 cache
->frameless_p
= 1;
664 cache
->frame_offset
= 0;
665 cache
->saved_regs_mask
= 0;
666 cache
->copied_regs_mask
= 0;
667 cache
->struct_return_p
= 0;
672 /* GCC generates several well-known sequences of instructions at the begining
673 of each function prologue when compiling with -fstack-check. If one of
674 such sequences starts at START_PC, then return the address of the
675 instruction immediately past this sequence. Otherwise, return START_PC. */
678 sparc_skip_stack_check (const CORE_ADDR start_pc
)
680 CORE_ADDR pc
= start_pc
;
682 int probing_loop
= 0;
684 /* With GCC, all stack checking sequences begin with the same two
685 instructions, plus an optional one in the case of a probing loop:
687 sethi <some immediate>, %g1
692 sethi <some immediate>, %g1
693 sethi <some immediate>, %g4
698 sethi <some immediate>, %g1
700 sethi <some immediate>, %g4
702 If the optional instruction is found (setting g4), assume that a
703 probing loop will follow. */
705 /* sethi <some immediate>, %g1 */
706 insn
= sparc_fetch_instruction (pc
);
708 if (!(X_OP (insn
) == 0 && X_OP2 (insn
) == 0x4 && X_RD (insn
) == 1))
711 /* optional: sethi <some immediate>, %g4 */
712 insn
= sparc_fetch_instruction (pc
);
714 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 0x4 && X_RD (insn
) == 4)
717 insn
= sparc_fetch_instruction (pc
);
721 /* sub %sp, %g1, %g1 */
722 if (!(X_OP (insn
) == 2 && X_OP3 (insn
) == 0x4 && !X_I(insn
)
723 && X_RD (insn
) == 1 && X_RS1 (insn
) == 14 && X_RS2 (insn
) == 1))
726 insn
= sparc_fetch_instruction (pc
);
729 /* optional: sethi <some immediate>, %g4 */
730 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 0x4 && X_RD (insn
) == 4)
733 insn
= sparc_fetch_instruction (pc
);
737 /* First possible sequence:
738 [first two instructions above]
739 clr [%g1 - some immediate] */
741 /* clr [%g1 - some immediate] */
742 if (X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && X_I(insn
)
743 && X_RS1 (insn
) == 1 && X_RD (insn
) == 0)
745 /* Valid stack-check sequence, return the new PC. */
749 /* Second possible sequence: A small number of probes.
750 [first two instructions above]
752 add %g1, -<some immediate>, %g1
754 [repeat the two instructions above any (small) number of times]
755 clr [%g1 - some immediate] */
758 else if (X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && !X_I(insn
)
759 && X_RS1 (insn
) == 1 && X_RD (insn
) == 0)
763 /* add %g1, -<some immediate>, %g1 */
764 insn
= sparc_fetch_instruction (pc
);
766 if (!(X_OP (insn
) == 2 && X_OP3(insn
) == 0 && X_I(insn
)
767 && X_RS1 (insn
) == 1 && X_RD (insn
) == 1))
771 insn
= sparc_fetch_instruction (pc
);
773 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && !X_I(insn
)
774 && X_RD (insn
) == 0 && X_RS1 (insn
) == 1))
778 /* clr [%g1 - some immediate] */
779 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && X_I(insn
)
780 && X_RS1 (insn
) == 1 && X_RD (insn
) == 0))
783 /* We found a valid stack-check sequence, return the new PC. */
787 /* Third sequence: A probing loop.
788 [first three instructions above]
792 add %g1, -<some immediate>, %g1
796 And an optional last probe for the remainder:
798 clr [%g4 - some immediate] */
802 /* sub %g1, %g4, %g4 */
803 if (!(X_OP (insn
) == 2 && X_OP3 (insn
) == 0x4 && !X_I(insn
)
804 && X_RD (insn
) == 4 && X_RS1 (insn
) == 1 && X_RS2 (insn
) == 4))
808 insn
= sparc_fetch_instruction (pc
);
810 if (!(X_OP (insn
) == 2 && X_OP3 (insn
) == 0x14 && !X_I(insn
)
811 && X_RD (insn
) == 0 && X_RS1 (insn
) == 1 && X_RS2 (insn
) == 4))
815 insn
= sparc_fetch_instruction (pc
);
817 if (!(X_OP (insn
) == 0 && X_COND (insn
) == 0x1))
820 /* add %g1, -<some immediate>, %g1 */
821 insn
= sparc_fetch_instruction (pc
);
823 if (!(X_OP (insn
) == 2 && X_OP3(insn
) == 0 && X_I(insn
)
824 && X_RS1 (insn
) == 1 && X_RD (insn
) == 1))
828 insn
= sparc_fetch_instruction (pc
);
830 if (!(X_OP (insn
) == 0 && X_COND (insn
) == 0x8))
833 /* clr [%g1] (st %g0, [%g1] or st %g0, [%g1+0]) */
834 insn
= sparc_fetch_instruction (pc
);
836 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4
837 && X_RD (insn
) == 0 && X_RS1 (insn
) == 1
838 && (!X_I(insn
) || X_SIMM13 (insn
) == 0)))
841 /* We found a valid stack-check sequence, return the new PC. */
843 /* optional: clr [%g4 - some immediate] */
844 insn
= sparc_fetch_instruction (pc
);
846 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && X_I(insn
)
847 && X_RS1 (insn
) == 4 && X_RD (insn
) == 0))
853 /* No stack check code in our prologue, return the start_pc. */
857 /* Record the effect of a SAVE instruction on CACHE. */
860 sparc_record_save_insn (struct sparc_frame_cache
*cache
)
862 /* The frame is set up. */
863 cache
->frameless_p
= 0;
865 /* The frame pointer contains the CFA. */
866 cache
->frame_offset
= 0;
868 /* The `local' and `in' registers are all saved. */
869 cache
->saved_regs_mask
= 0xffff;
871 /* The `out' registers are all renamed. */
872 cache
->copied_regs_mask
= 0xff;
875 /* Do a full analysis of the prologue at PC and update CACHE accordingly.
876 Bail out early if CURRENT_PC is reached. Return the address where
877 the analysis stopped.
879 We handle both the traditional register window model and the single
880 register window (aka flat) model. */
883 sparc_analyze_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
884 CORE_ADDR current_pc
, struct sparc_frame_cache
*cache
)
886 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
891 pc
= sparc_skip_stack_check (pc
);
893 if (current_pc
<= pc
)
896 /* We have to handle to "Procedure Linkage Table" (PLT) special. On
897 SPARC the linker usually defines a symbol (typically
898 _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section.
899 This symbol makes us end up here with PC pointing at the start of
900 the PLT and CURRENT_PC probably pointing at a PLT entry. If we
901 would do our normal prologue analysis, we would probably conclude
902 that we've got a frame when in reality we don't, since the
903 dynamic linker patches up the first PLT with some code that
904 starts with a SAVE instruction. Patch up PC such that it points
905 at the start of our PLT entry. */
906 if (tdep
->plt_entry_size
> 0 && in_plt_section (current_pc
))
907 pc
= current_pc
- ((current_pc
- pc
) % tdep
->plt_entry_size
);
909 insn
= sparc_fetch_instruction (pc
);
911 /* Recognize store insns and record their sources. */
912 while (X_OP (insn
) == 3
913 && (X_OP3 (insn
) == 0x4 /* stw */
914 || X_OP3 (insn
) == 0x7 /* std */
915 || X_OP3 (insn
) == 0xe) /* stx */
916 && X_RS1 (insn
) == SPARC_SP_REGNUM
)
918 int regnum
= X_RD (insn
);
920 /* Recognize stores into the corresponding stack slots. */
921 if (regnum
>= SPARC_L0_REGNUM
&& regnum
<= SPARC_I7_REGNUM
923 && X_SIMM13 (insn
) == (X_OP3 (insn
) == 0xe
924 ? (regnum
- SPARC_L0_REGNUM
) * 8 + BIAS
925 : (regnum
- SPARC_L0_REGNUM
) * 4))
926 || (!X_I (insn
) && regnum
== SPARC_L0_REGNUM
)))
928 cache
->saved_regs_mask
|= (1 << (regnum
- SPARC_L0_REGNUM
));
929 if (X_OP3 (insn
) == 0x7)
930 cache
->saved_regs_mask
|= (1 << (regnum
+ 1 - SPARC_L0_REGNUM
));
935 insn
= sparc_fetch_instruction (pc
+ offset
);
938 /* Recognize a SETHI insn and record its destination. */
939 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 0x04)
944 insn
= sparc_fetch_instruction (pc
+ offset
);
947 /* Allow for an arithmetic operation on DEST or %g1. */
948 if (X_OP (insn
) == 2 && X_I (insn
)
949 && (X_RD (insn
) == 1 || X_RD (insn
) == dest
))
953 insn
= sparc_fetch_instruction (pc
+ offset
);
956 /* Check for the SAVE instruction that sets up the frame. */
957 if (X_OP (insn
) == 2 && X_OP3 (insn
) == 0x3c)
959 sparc_record_save_insn (cache
);
964 /* Check for an arithmetic operation on %sp. */
966 && (X_OP3 (insn
) == 0 || X_OP3 (insn
) == 0x4)
967 && X_RS1 (insn
) == SPARC_SP_REGNUM
968 && X_RD (insn
) == SPARC_SP_REGNUM
)
972 cache
->frame_offset
= X_SIMM13 (insn
);
973 if (X_OP3 (insn
) == 0)
974 cache
->frame_offset
= -cache
->frame_offset
;
978 insn
= sparc_fetch_instruction (pc
+ offset
);
980 /* Check for an arithmetic operation that sets up the frame. */
982 && (X_OP3 (insn
) == 0 || X_OP3 (insn
) == 0x4)
983 && X_RS1 (insn
) == SPARC_SP_REGNUM
984 && X_RD (insn
) == SPARC_FP_REGNUM
)
986 cache
->frameless_p
= 0;
987 cache
->frame_offset
= 0;
988 /* We could check that the amount subtracted to %sp above is the
989 same as the one added here, but this seems superfluous. */
990 cache
->copied_regs_mask
|= 0x40;
993 insn
= sparc_fetch_instruction (pc
+ offset
);
996 /* Check for a move (or) operation that copies the return register. */
998 && X_OP3 (insn
) == 0x2
1000 && X_RS1 (insn
) == SPARC_G0_REGNUM
1001 && X_RS2 (insn
) == SPARC_O7_REGNUM
1002 && X_RD (insn
) == SPARC_I7_REGNUM
)
1004 cache
->copied_regs_mask
|= 0x80;
1015 sparc_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1017 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1018 return frame_unwind_register_unsigned (this_frame
, tdep
->pc_regnum
);
1021 /* Return PC of first real instruction of the function starting at
1025 sparc32_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
1027 struct symtab_and_line sal
;
1028 CORE_ADDR func_start
, func_end
;
1029 struct sparc_frame_cache cache
;
1031 /* This is the preferred method, find the end of the prologue by
1032 using the debugging information. */
1033 if (find_pc_partial_function (start_pc
, NULL
, &func_start
, &func_end
))
1035 sal
= find_pc_line (func_start
, 0);
1037 if (sal
.end
< func_end
1038 && start_pc
<= sal
.end
)
1042 start_pc
= sparc_analyze_prologue (gdbarch
, start_pc
, 0xffffffffUL
, &cache
);
1044 /* The psABI says that "Although the first 6 words of arguments
1045 reside in registers, the standard stack frame reserves space for
1046 them.". It also suggests that a function may use that space to
1047 "write incoming arguments 0 to 5" into that space, and that's
1048 indeed what GCC seems to be doing. In that case GCC will
1049 generate debug information that points to the stack slots instead
1050 of the registers, so we should consider the instructions that
1051 write out these incoming arguments onto the stack. */
1055 unsigned long insn
= sparc_fetch_instruction (start_pc
);
1057 /* Recognize instructions that store incoming arguments into the
1058 corresponding stack slots. */
1059 if (X_OP (insn
) == 3 && (X_OP3 (insn
) & 0x3c) == 0x04
1060 && X_I (insn
) && X_RS1 (insn
) == SPARC_FP_REGNUM
)
1062 int regnum
= X_RD (insn
);
1064 /* Case of arguments still in %o[0..5]. */
1065 if (regnum
>= SPARC_O0_REGNUM
&& regnum
<= SPARC_O5_REGNUM
1066 && !(cache
.copied_regs_mask
& (1 << (regnum
- SPARC_O0_REGNUM
)))
1067 && X_SIMM13 (insn
) == 68 + (regnum
- SPARC_O0_REGNUM
) * 4)
1073 /* Case of arguments copied into %i[0..5]. */
1074 if (regnum
>= SPARC_I0_REGNUM
&& regnum
<= SPARC_I5_REGNUM
1075 && (cache
.copied_regs_mask
& (1 << (regnum
- SPARC_I0_REGNUM
)))
1076 && X_SIMM13 (insn
) == 68 + (regnum
- SPARC_I0_REGNUM
) * 4)
1089 /* Normal frames. */
1091 struct sparc_frame_cache
*
1092 sparc_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1094 struct sparc_frame_cache
*cache
;
1097 return (struct sparc_frame_cache
*) *this_cache
;
1099 cache
= sparc_alloc_frame_cache ();
1100 *this_cache
= cache
;
1102 cache
->pc
= get_frame_func (this_frame
);
1104 sparc_analyze_prologue (get_frame_arch (this_frame
), cache
->pc
,
1105 get_frame_pc (this_frame
), cache
);
1107 if (cache
->frameless_p
)
1109 /* This function is frameless, so %fp (%i6) holds the frame
1110 pointer for our calling frame. Use %sp (%o6) as this frame's
1113 get_frame_register_unsigned (this_frame
, SPARC_SP_REGNUM
);
1117 /* For normal frames, %fp (%i6) holds the frame pointer, the
1118 base address for the current stack frame. */
1120 get_frame_register_unsigned (this_frame
, SPARC_FP_REGNUM
);
1123 cache
->base
+= cache
->frame_offset
;
1125 if (cache
->base
& 1)
1126 cache
->base
+= BIAS
;
1132 sparc32_struct_return_from_sym (struct symbol
*sym
)
1134 struct type
*type
= check_typedef (SYMBOL_TYPE (sym
));
1135 enum type_code code
= TYPE_CODE (type
);
1137 if (code
== TYPE_CODE_FUNC
|| code
== TYPE_CODE_METHOD
)
1139 type
= check_typedef (TYPE_TARGET_TYPE (type
));
1140 if (sparc_structure_or_union_p (type
)
1141 || (sparc_floating_p (type
) && TYPE_LENGTH (type
) == 16))
1148 struct sparc_frame_cache
*
1149 sparc32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1151 struct sparc_frame_cache
*cache
;
1155 return (struct sparc_frame_cache
*) *this_cache
;
1157 cache
= sparc_frame_cache (this_frame
, this_cache
);
1159 sym
= find_pc_function (cache
->pc
);
1162 cache
->struct_return_p
= sparc32_struct_return_from_sym (sym
);
1166 /* There is no debugging information for this function to
1167 help us determine whether this function returns a struct
1168 or not. So we rely on another heuristic which is to check
1169 the instruction at the return address and see if this is
1170 an "unimp" instruction. If it is, then it is a struct-return
1174 (cache
->copied_regs_mask
& 0x80) ? SPARC_I7_REGNUM
: SPARC_O7_REGNUM
;
1176 pc
= get_frame_register_unsigned (this_frame
, regnum
) + 8;
1177 if (sparc_is_unimp_insn (pc
))
1178 cache
->struct_return_p
= 1;
1185 sparc32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1186 struct frame_id
*this_id
)
1188 struct sparc_frame_cache
*cache
=
1189 sparc32_frame_cache (this_frame
, this_cache
);
1191 /* This marks the outermost frame. */
1192 if (cache
->base
== 0)
1195 (*this_id
) = frame_id_build (cache
->base
, cache
->pc
);
1198 static struct value
*
1199 sparc32_frame_prev_register (struct frame_info
*this_frame
,
1200 void **this_cache
, int regnum
)
1202 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1203 struct sparc_frame_cache
*cache
=
1204 sparc32_frame_cache (this_frame
, this_cache
);
1206 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== SPARC32_NPC_REGNUM
)
1208 CORE_ADDR pc
= (regnum
== SPARC32_NPC_REGNUM
) ? 4 : 0;
1210 /* If this functions has a Structure, Union or Quad-Precision
1211 return value, we have to skip the UNIMP instruction that encodes
1212 the size of the structure. */
1213 if (cache
->struct_return_p
)
1217 (cache
->copied_regs_mask
& 0x80) ? SPARC_I7_REGNUM
: SPARC_O7_REGNUM
;
1218 pc
+= get_frame_register_unsigned (this_frame
, regnum
) + 8;
1219 return frame_unwind_got_constant (this_frame
, regnum
, pc
);
1222 /* Handle StackGhost. */
1224 ULONGEST wcookie
= sparc_fetch_wcookie (gdbarch
);
1226 if (wcookie
!= 0 && !cache
->frameless_p
&& regnum
== SPARC_I7_REGNUM
)
1228 CORE_ADDR addr
= cache
->base
+ (regnum
- SPARC_L0_REGNUM
) * 4;
1231 /* Read the value in from memory. */
1232 i7
= get_frame_memory_unsigned (this_frame
, addr
, 4);
1233 return frame_unwind_got_constant (this_frame
, regnum
, i7
^ wcookie
);
1237 /* The previous frame's `local' and `in' registers may have been saved
1238 in the register save area. */
1239 if (regnum
>= SPARC_L0_REGNUM
&& regnum
<= SPARC_I7_REGNUM
1240 && (cache
->saved_regs_mask
& (1 << (regnum
- SPARC_L0_REGNUM
))))
1242 CORE_ADDR addr
= cache
->base
+ (regnum
- SPARC_L0_REGNUM
) * 4;
1244 return frame_unwind_got_memory (this_frame
, regnum
, addr
);
1247 /* The previous frame's `out' registers may be accessible as the current
1248 frame's `in' registers. */
1249 if (regnum
>= SPARC_O0_REGNUM
&& regnum
<= SPARC_O7_REGNUM
1250 && (cache
->copied_regs_mask
& (1 << (regnum
- SPARC_O0_REGNUM
))))
1251 regnum
+= (SPARC_I0_REGNUM
- SPARC_O0_REGNUM
);
1253 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1256 static const struct frame_unwind sparc32_frame_unwind
=
1259 default_frame_unwind_stop_reason
,
1260 sparc32_frame_this_id
,
1261 sparc32_frame_prev_register
,
1263 default_frame_sniffer
1268 sparc32_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
1270 struct sparc_frame_cache
*cache
=
1271 sparc32_frame_cache (this_frame
, this_cache
);
1276 static const struct frame_base sparc32_frame_base
=
1278 &sparc32_frame_unwind
,
1279 sparc32_frame_base_address
,
1280 sparc32_frame_base_address
,
1281 sparc32_frame_base_address
1284 static struct frame_id
1285 sparc_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1289 sp
= get_frame_register_unsigned (this_frame
, SPARC_SP_REGNUM
);
1292 return frame_id_build (sp
, get_frame_pc (this_frame
));
1296 /* Extract a function return value of TYPE from REGCACHE, and copy
1297 that into VALBUF. */
1300 sparc32_extract_return_value (struct type
*type
, struct regcache
*regcache
,
1303 int len
= TYPE_LENGTH (type
);
1306 gdb_assert (!sparc_structure_or_union_p (type
));
1307 gdb_assert (!(sparc_floating_p (type
) && len
== 16));
1309 if (sparc_floating_p (type
) || sparc_complex_floating_p (type
))
1311 /* Floating return values. */
1312 regcache_cooked_read (regcache
, SPARC_F0_REGNUM
, buf
);
1314 regcache_cooked_read (regcache
, SPARC_F1_REGNUM
, buf
+ 4);
1317 regcache_cooked_read (regcache
, SPARC_F2_REGNUM
, buf
+ 8);
1318 regcache_cooked_read (regcache
, SPARC_F3_REGNUM
, buf
+ 12);
1322 regcache_cooked_read (regcache
, SPARC_F4_REGNUM
, buf
+ 16);
1323 regcache_cooked_read (regcache
, SPARC_F5_REGNUM
, buf
+ 20);
1324 regcache_cooked_read (regcache
, SPARC_F6_REGNUM
, buf
+ 24);
1325 regcache_cooked_read (regcache
, SPARC_F7_REGNUM
, buf
+ 28);
1327 memcpy (valbuf
, buf
, len
);
1331 /* Integral and pointer return values. */
1332 gdb_assert (sparc_integral_or_pointer_p (type
));
1334 regcache_cooked_read (regcache
, SPARC_O0_REGNUM
, buf
);
1337 regcache_cooked_read (regcache
, SPARC_O1_REGNUM
, buf
+ 4);
1338 gdb_assert (len
== 8);
1339 memcpy (valbuf
, buf
, 8);
1343 /* Just stripping off any unused bytes should preserve the
1344 signed-ness just fine. */
1345 memcpy (valbuf
, buf
+ 4 - len
, len
);
1350 /* Store the function return value of type TYPE from VALBUF into
1354 sparc32_store_return_value (struct type
*type
, struct regcache
*regcache
,
1355 const gdb_byte
*valbuf
)
1357 int len
= TYPE_LENGTH (type
);
1360 gdb_assert (!sparc_structure_or_union_p (type
));
1361 gdb_assert (!(sparc_floating_p (type
) && len
== 16));
1362 gdb_assert (len
<= 8);
1364 if (sparc_floating_p (type
) || sparc_complex_floating_p (type
))
1366 /* Floating return values. */
1367 memcpy (buf
, valbuf
, len
);
1368 regcache_cooked_write (regcache
, SPARC_F0_REGNUM
, buf
);
1370 regcache_cooked_write (regcache
, SPARC_F1_REGNUM
, buf
+ 4);
1373 regcache_cooked_write (regcache
, SPARC_F2_REGNUM
, buf
+ 8);
1374 regcache_cooked_write (regcache
, SPARC_F3_REGNUM
, buf
+ 12);
1378 regcache_cooked_write (regcache
, SPARC_F4_REGNUM
, buf
+ 16);
1379 regcache_cooked_write (regcache
, SPARC_F5_REGNUM
, buf
+ 20);
1380 regcache_cooked_write (regcache
, SPARC_F6_REGNUM
, buf
+ 24);
1381 regcache_cooked_write (regcache
, SPARC_F7_REGNUM
, buf
+ 28);
1386 /* Integral and pointer return values. */
1387 gdb_assert (sparc_integral_or_pointer_p (type
));
1391 gdb_assert (len
== 8);
1392 memcpy (buf
, valbuf
, 8);
1393 regcache_cooked_write (regcache
, SPARC_O1_REGNUM
, buf
+ 4);
1397 /* ??? Do we need to do any sign-extension here? */
1398 memcpy (buf
+ 4 - len
, valbuf
, len
);
1400 regcache_cooked_write (regcache
, SPARC_O0_REGNUM
, buf
);
1404 static enum return_value_convention
1405 sparc32_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
1406 struct type
*type
, struct regcache
*regcache
,
1407 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1409 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1411 /* The psABI says that "...every stack frame reserves the word at
1412 %fp+64. If a function returns a structure, union, or
1413 quad-precision value, this word should hold the address of the
1414 object into which the return value should be copied." This
1415 guarantees that we can always find the return value, not just
1416 before the function returns. */
1418 if (sparc_structure_or_union_p (type
)
1419 || (sparc_floating_p (type
) && TYPE_LENGTH (type
) == 16))
1426 regcache_cooked_read_unsigned (regcache
, SPARC_SP_REGNUM
, &sp
);
1427 addr
= read_memory_unsigned_integer (sp
+ 64, 4, byte_order
);
1428 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
1432 regcache_cooked_read_unsigned (regcache
, SPARC_SP_REGNUM
, &sp
);
1433 addr
= read_memory_unsigned_integer (sp
+ 64, 4, byte_order
);
1434 write_memory (addr
, writebuf
, TYPE_LENGTH (type
));
1437 return RETURN_VALUE_ABI_PRESERVES_ADDRESS
;
1441 sparc32_extract_return_value (type
, regcache
, readbuf
);
1443 sparc32_store_return_value (type
, regcache
, writebuf
);
1445 return RETURN_VALUE_REGISTER_CONVENTION
;
1449 sparc32_stabs_argument_has_addr (struct gdbarch
*gdbarch
, struct type
*type
)
1451 return (sparc_structure_or_union_p (type
)
1452 || (sparc_floating_p (type
) && TYPE_LENGTH (type
) == 16)
1453 || sparc_complex_floating_p (type
));
1457 sparc32_dwarf2_struct_return_p (struct frame_info
*this_frame
)
1459 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
1460 struct symbol
*sym
= find_pc_function (pc
);
1463 return sparc32_struct_return_from_sym (sym
);
1468 sparc32_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1469 struct dwarf2_frame_state_reg
*reg
,
1470 struct frame_info
*this_frame
)
1476 case SPARC_G0_REGNUM
:
1477 /* Since %g0 is always zero, there is no point in saving it, and
1478 people will be inclined omit it from the CFI. Make sure we
1479 don't warn about that. */
1480 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
1482 case SPARC_SP_REGNUM
:
1483 reg
->how
= DWARF2_FRAME_REG_CFA
;
1485 case SPARC32_PC_REGNUM
:
1486 case SPARC32_NPC_REGNUM
:
1487 reg
->how
= DWARF2_FRAME_REG_RA_OFFSET
;
1489 if (sparc32_dwarf2_struct_return_p (this_frame
))
1491 if (regnum
== SPARC32_NPC_REGNUM
)
1493 reg
->loc
.offset
= off
;
1499 /* The SPARC Architecture doesn't have hardware single-step support,
1500 and most operating systems don't implement it either, so we provide
1501 software single-step mechanism. */
1504 sparc_analyze_control_transfer (struct regcache
*regcache
,
1505 CORE_ADDR pc
, CORE_ADDR
*npc
)
1507 unsigned long insn
= sparc_fetch_instruction (pc
);
1508 int conditional_p
= X_COND (insn
) & 0x7;
1509 int branch_p
= 0, fused_p
= 0;
1510 long offset
= 0; /* Must be signed for sign-extend. */
1512 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 3)
1514 if ((insn
& 0x10000000) == 0)
1516 /* Branch on Integer Register with Prediction (BPr). */
1522 /* Compare and Branch */
1525 offset
= 4 * X_DISP10 (insn
);
1528 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 6)
1530 /* Branch on Floating-Point Condition Codes (FBfcc). */
1532 offset
= 4 * X_DISP22 (insn
);
1534 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 5)
1536 /* Branch on Floating-Point Condition Codes with Prediction
1539 offset
= 4 * X_DISP19 (insn
);
1541 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 2)
1543 /* Branch on Integer Condition Codes (Bicc). */
1545 offset
= 4 * X_DISP22 (insn
);
1547 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 1)
1549 /* Branch on Integer Condition Codes with Prediction (BPcc). */
1551 offset
= 4 * X_DISP19 (insn
);
1553 else if (X_OP (insn
) == 2 && X_OP3 (insn
) == 0x3a)
1555 struct frame_info
*frame
= get_current_frame ();
1557 /* Trap instruction (TRAP). */
1558 return gdbarch_tdep (get_regcache_arch (regcache
))->step_trap (frame
,
1562 /* FIXME: Handle DONE and RETRY instructions. */
1568 /* Fused compare-and-branch instructions are non-delayed,
1569 and do not have an annuling capability. So we need to
1570 always set a breakpoint on both the NPC and the branch
1572 gdb_assert (offset
!= 0);
1575 else if (conditional_p
)
1577 /* For conditional branches, return nPC + 4 iff the annul
1579 return (X_A (insn
) ? *npc
+ 4 : 0);
1583 /* For unconditional branches, return the target if its
1584 specified condition is "always" and return nPC + 4 if the
1585 condition is "never". If the annul bit is 1, set *NPC to
1587 if (X_COND (insn
) == 0x0)
1588 pc
= *npc
, offset
= 4;
1600 sparc_step_trap (struct frame_info
*frame
, unsigned long insn
)
1605 static VEC (CORE_ADDR
) *
1606 sparc_software_single_step (struct regcache
*regcache
)
1608 struct gdbarch
*arch
= get_regcache_arch (regcache
);
1609 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
1610 CORE_ADDR npc
, nnpc
;
1612 CORE_ADDR pc
, orig_npc
;
1613 VEC (CORE_ADDR
) *next_pcs
= NULL
;
1615 pc
= regcache_raw_get_unsigned (regcache
, tdep
->pc_regnum
);
1616 orig_npc
= npc
= regcache_raw_get_unsigned (regcache
, tdep
->npc_regnum
);
1618 /* Analyze the instruction at PC. */
1619 nnpc
= sparc_analyze_control_transfer (regcache
, pc
, &npc
);
1621 VEC_safe_push (CORE_ADDR
, next_pcs
, npc
);
1624 VEC_safe_push (CORE_ADDR
, next_pcs
, nnpc
);
1626 /* Assert that we have set at least one breakpoint, and that
1627 they're not set at the same spot - unless we're going
1628 from here straight to NULL, i.e. a call or jump to 0. */
1629 gdb_assert (npc
!= 0 || nnpc
!= 0 || orig_npc
== 0);
1630 gdb_assert (nnpc
!= npc
|| orig_npc
== 0);
1636 sparc_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1638 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_regcache_arch (regcache
));
1640 regcache_cooked_write_unsigned (regcache
, tdep
->pc_regnum
, pc
);
1641 regcache_cooked_write_unsigned (regcache
, tdep
->npc_regnum
, pc
+ 4);
1645 /* Iterate over core file register note sections. */
1648 sparc_iterate_over_regset_sections (struct gdbarch
*gdbarch
,
1649 iterate_over_regset_sections_cb
*cb
,
1651 const struct regcache
*regcache
)
1653 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1655 cb (".reg", tdep
->sizeof_gregset
, tdep
->gregset
, NULL
, cb_data
);
1656 cb (".reg2", tdep
->sizeof_fpregset
, tdep
->fpregset
, NULL
, cb_data
);
1660 static struct gdbarch
*
1661 sparc32_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1663 struct gdbarch_tdep
*tdep
;
1664 struct gdbarch
*gdbarch
;
1666 /* If there is already a candidate, use it. */
1667 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
1669 return arches
->gdbarch
;
1671 /* Allocate space for the new architecture. */
1672 tdep
= XCNEW (struct gdbarch_tdep
);
1673 gdbarch
= gdbarch_alloc (&info
, tdep
);
1675 tdep
->pc_regnum
= SPARC32_PC_REGNUM
;
1676 tdep
->npc_regnum
= SPARC32_NPC_REGNUM
;
1677 tdep
->step_trap
= sparc_step_trap
;
1679 set_gdbarch_long_double_bit (gdbarch
, 128);
1680 set_gdbarch_long_double_format (gdbarch
, floatformats_sparc_quad
);
1682 set_gdbarch_num_regs (gdbarch
, SPARC32_NUM_REGS
);
1683 set_gdbarch_register_name (gdbarch
, sparc32_register_name
);
1684 set_gdbarch_register_type (gdbarch
, sparc32_register_type
);
1685 set_gdbarch_num_pseudo_regs (gdbarch
, SPARC32_NUM_PSEUDO_REGS
);
1686 set_gdbarch_pseudo_register_read (gdbarch
, sparc32_pseudo_register_read
);
1687 set_gdbarch_pseudo_register_write (gdbarch
, sparc32_pseudo_register_write
);
1689 /* Register numbers of various important registers. */
1690 set_gdbarch_sp_regnum (gdbarch
, SPARC_SP_REGNUM
); /* %sp */
1691 set_gdbarch_pc_regnum (gdbarch
, SPARC32_PC_REGNUM
); /* %pc */
1692 set_gdbarch_fp0_regnum (gdbarch
, SPARC_F0_REGNUM
); /* %f0 */
1694 /* Call dummy code. */
1695 set_gdbarch_frame_align (gdbarch
, sparc32_frame_align
);
1696 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
1697 set_gdbarch_push_dummy_code (gdbarch
, sparc32_push_dummy_code
);
1698 set_gdbarch_push_dummy_call (gdbarch
, sparc32_push_dummy_call
);
1700 set_gdbarch_return_value (gdbarch
, sparc32_return_value
);
1701 set_gdbarch_stabs_argument_has_addr
1702 (gdbarch
, sparc32_stabs_argument_has_addr
);
1704 set_gdbarch_skip_prologue (gdbarch
, sparc32_skip_prologue
);
1706 /* Stack grows downward. */
1707 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
1709 set_gdbarch_breakpoint_kind_from_pc (gdbarch
,
1710 sparc_breakpoint::kind_from_pc
);
1711 set_gdbarch_sw_breakpoint_from_kind (gdbarch
,
1712 sparc_breakpoint::bp_from_kind
);
1714 set_gdbarch_frame_args_skip (gdbarch
, 8);
1716 set_gdbarch_print_insn (gdbarch
, print_insn_sparc
);
1718 set_gdbarch_software_single_step (gdbarch
, sparc_software_single_step
);
1719 set_gdbarch_write_pc (gdbarch
, sparc_write_pc
);
1721 set_gdbarch_dummy_id (gdbarch
, sparc_dummy_id
);
1723 set_gdbarch_unwind_pc (gdbarch
, sparc_unwind_pc
);
1725 frame_base_set_default (gdbarch
, &sparc32_frame_base
);
1727 /* Hook in the DWARF CFI frame unwinder. */
1728 dwarf2_frame_set_init_reg (gdbarch
, sparc32_dwarf2_frame_init_reg
);
1729 /* FIXME: kettenis/20050423: Don't enable the unwinder until the
1730 StackGhost issues have been resolved. */
1732 /* Hook in ABI-specific overrides, if they have been registered. */
1733 gdbarch_init_osabi (info
, gdbarch
);
1735 frame_unwind_append_unwinder (gdbarch
, &sparc32_frame_unwind
);
1737 /* If we have register sets, enable the generic core file support. */
1739 set_gdbarch_iterate_over_regset_sections
1740 (gdbarch
, sparc_iterate_over_regset_sections
);
1742 register_sparc_ravenscar_ops (gdbarch
);
1747 /* Helper functions for dealing with register windows. */
1750 sparc_supply_rwindow (struct regcache
*regcache
, CORE_ADDR sp
, int regnum
)
1752 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1753 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1760 /* Registers are 64-bit. */
1763 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1765 if (regnum
== i
|| regnum
== -1)
1767 target_read_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 8), buf
, 8);
1769 /* Handle StackGhost. */
1770 if (i
== SPARC_I7_REGNUM
)
1772 ULONGEST wcookie
= sparc_fetch_wcookie (gdbarch
);
1775 i7
= extract_unsigned_integer (buf
+ offset
, 8, byte_order
);
1776 store_unsigned_integer (buf
+ offset
, 8, byte_order
,
1780 regcache_raw_supply (regcache
, i
, buf
);
1786 /* Registers are 32-bit. Toss any sign-extension of the stack
1790 /* Clear out the top half of the temporary buffer, and put the
1791 register value in the bottom half if we're in 64-bit mode. */
1792 if (gdbarch_ptr_bit (get_regcache_arch (regcache
)) == 64)
1798 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1800 if (regnum
== i
|| regnum
== -1)
1802 target_read_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 4),
1805 /* Handle StackGhost. */
1806 if (i
== SPARC_I7_REGNUM
)
1808 ULONGEST wcookie
= sparc_fetch_wcookie (gdbarch
);
1811 i7
= extract_unsigned_integer (buf
+ offset
, 4, byte_order
);
1812 store_unsigned_integer (buf
+ offset
, 4, byte_order
,
1816 regcache_raw_supply (regcache
, i
, buf
);
1823 sparc_collect_rwindow (const struct regcache
*regcache
,
1824 CORE_ADDR sp
, int regnum
)
1826 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1827 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1834 /* Registers are 64-bit. */
1837 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1839 if (regnum
== -1 || regnum
== SPARC_SP_REGNUM
|| regnum
== i
)
1841 regcache_raw_collect (regcache
, i
, buf
);
1843 /* Handle StackGhost. */
1844 if (i
== SPARC_I7_REGNUM
)
1846 ULONGEST wcookie
= sparc_fetch_wcookie (gdbarch
);
1849 i7
= extract_unsigned_integer (buf
+ offset
, 8, byte_order
);
1850 store_unsigned_integer (buf
, 8, byte_order
, i7
^ wcookie
);
1853 target_write_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 8), buf
, 8);
1859 /* Registers are 32-bit. Toss any sign-extension of the stack
1863 /* Only use the bottom half if we're in 64-bit mode. */
1864 if (gdbarch_ptr_bit (get_regcache_arch (regcache
)) == 64)
1867 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1869 if (regnum
== -1 || regnum
== SPARC_SP_REGNUM
|| regnum
== i
)
1871 regcache_raw_collect (regcache
, i
, buf
);
1873 /* Handle StackGhost. */
1874 if (i
== SPARC_I7_REGNUM
)
1876 ULONGEST wcookie
= sparc_fetch_wcookie (gdbarch
);
1879 i7
= extract_unsigned_integer (buf
+ offset
, 4, byte_order
);
1880 store_unsigned_integer (buf
+ offset
, 4, byte_order
,
1884 target_write_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 4),
1891 /* Helper functions for dealing with register sets. */
1894 sparc32_supply_gregset (const struct sparc_gregmap
*gregmap
,
1895 struct regcache
*regcache
,
1896 int regnum
, const void *gregs
)
1898 const gdb_byte
*regs
= (const gdb_byte
*) gregs
;
1899 gdb_byte zero
[4] = { 0 };
1902 if (regnum
== SPARC32_PSR_REGNUM
|| regnum
== -1)
1903 regcache_raw_supply (regcache
, SPARC32_PSR_REGNUM
,
1904 regs
+ gregmap
->r_psr_offset
);
1906 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== -1)
1907 regcache_raw_supply (regcache
, SPARC32_PC_REGNUM
,
1908 regs
+ gregmap
->r_pc_offset
);
1910 if (regnum
== SPARC32_NPC_REGNUM
|| regnum
== -1)
1911 regcache_raw_supply (regcache
, SPARC32_NPC_REGNUM
,
1912 regs
+ gregmap
->r_npc_offset
);
1914 if (regnum
== SPARC32_Y_REGNUM
|| regnum
== -1)
1915 regcache_raw_supply (regcache
, SPARC32_Y_REGNUM
,
1916 regs
+ gregmap
->r_y_offset
);
1918 if (regnum
== SPARC_G0_REGNUM
|| regnum
== -1)
1919 regcache_raw_supply (regcache
, SPARC_G0_REGNUM
, &zero
);
1921 if ((regnum
>= SPARC_G1_REGNUM
&& regnum
<= SPARC_O7_REGNUM
) || regnum
== -1)
1923 int offset
= gregmap
->r_g1_offset
;
1925 for (i
= SPARC_G1_REGNUM
; i
<= SPARC_O7_REGNUM
; i
++)
1927 if (regnum
== i
|| regnum
== -1)
1928 regcache_raw_supply (regcache
, i
, regs
+ offset
);
1933 if ((regnum
>= SPARC_L0_REGNUM
&& regnum
<= SPARC_I7_REGNUM
) || regnum
== -1)
1935 /* Not all of the register set variants include Locals and
1936 Inputs. For those that don't, we read them off the stack. */
1937 if (gregmap
->r_l0_offset
== -1)
1941 regcache_cooked_read_unsigned (regcache
, SPARC_SP_REGNUM
, &sp
);
1942 sparc_supply_rwindow (regcache
, sp
, regnum
);
1946 int offset
= gregmap
->r_l0_offset
;
1948 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1950 if (regnum
== i
|| regnum
== -1)
1951 regcache_raw_supply (regcache
, i
, regs
+ offset
);
1959 sparc32_collect_gregset (const struct sparc_gregmap
*gregmap
,
1960 const struct regcache
*regcache
,
1961 int regnum
, void *gregs
)
1963 gdb_byte
*regs
= (gdb_byte
*) gregs
;
1966 if (regnum
== SPARC32_PSR_REGNUM
|| regnum
== -1)
1967 regcache_raw_collect (regcache
, SPARC32_PSR_REGNUM
,
1968 regs
+ gregmap
->r_psr_offset
);
1970 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== -1)
1971 regcache_raw_collect (regcache
, SPARC32_PC_REGNUM
,
1972 regs
+ gregmap
->r_pc_offset
);
1974 if (regnum
== SPARC32_NPC_REGNUM
|| regnum
== -1)
1975 regcache_raw_collect (regcache
, SPARC32_NPC_REGNUM
,
1976 regs
+ gregmap
->r_npc_offset
);
1978 if (regnum
== SPARC32_Y_REGNUM
|| regnum
== -1)
1979 regcache_raw_collect (regcache
, SPARC32_Y_REGNUM
,
1980 regs
+ gregmap
->r_y_offset
);
1982 if ((regnum
>= SPARC_G1_REGNUM
&& regnum
<= SPARC_O7_REGNUM
) || regnum
== -1)
1984 int offset
= gregmap
->r_g1_offset
;
1986 /* %g0 is always zero. */
1987 for (i
= SPARC_G1_REGNUM
; i
<= SPARC_O7_REGNUM
; i
++)
1989 if (regnum
== i
|| regnum
== -1)
1990 regcache_raw_collect (regcache
, i
, regs
+ offset
);
1995 if ((regnum
>= SPARC_L0_REGNUM
&& regnum
<= SPARC_I7_REGNUM
) || regnum
== -1)
1997 /* Not all of the register set variants include Locals and
1998 Inputs. For those that don't, we read them off the stack. */
1999 if (gregmap
->r_l0_offset
!= -1)
2001 int offset
= gregmap
->r_l0_offset
;
2003 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
2005 if (regnum
== i
|| regnum
== -1)
2006 regcache_raw_collect (regcache
, i
, regs
+ offset
);
2014 sparc32_supply_fpregset (const struct sparc_fpregmap
*fpregmap
,
2015 struct regcache
*regcache
,
2016 int regnum
, const void *fpregs
)
2018 const gdb_byte
*regs
= (const gdb_byte
*) fpregs
;
2021 for (i
= 0; i
< 32; i
++)
2023 if (regnum
== (SPARC_F0_REGNUM
+ i
) || regnum
== -1)
2024 regcache_raw_supply (regcache
, SPARC_F0_REGNUM
+ i
,
2025 regs
+ fpregmap
->r_f0_offset
+ (i
* 4));
2028 if (regnum
== SPARC32_FSR_REGNUM
|| regnum
== -1)
2029 regcache_raw_supply (regcache
, SPARC32_FSR_REGNUM
,
2030 regs
+ fpregmap
->r_fsr_offset
);
2034 sparc32_collect_fpregset (const struct sparc_fpregmap
*fpregmap
,
2035 const struct regcache
*regcache
,
2036 int regnum
, void *fpregs
)
2038 gdb_byte
*regs
= (gdb_byte
*) fpregs
;
2041 for (i
= 0; i
< 32; i
++)
2043 if (regnum
== (SPARC_F0_REGNUM
+ i
) || regnum
== -1)
2044 regcache_raw_collect (regcache
, SPARC_F0_REGNUM
+ i
,
2045 regs
+ fpregmap
->r_f0_offset
+ (i
* 4));
2048 if (regnum
== SPARC32_FSR_REGNUM
|| regnum
== -1)
2049 regcache_raw_collect (regcache
, SPARC32_FSR_REGNUM
,
2050 regs
+ fpregmap
->r_fsr_offset
);
2056 /* From <machine/reg.h>. */
2057 const struct sparc_gregmap sparc32_sunos4_gregmap
=
2069 const struct sparc_fpregmap sparc32_sunos4_fpregmap
=
2075 const struct sparc_fpregmap sparc32_bsd_fpregmap
=
2082 /* Provide a prototype to silence -Wmissing-prototypes. */
2083 void _initialize_sparc_tdep (void);
2086 _initialize_sparc_tdep (void)
2088 register_gdbarch_init (bfd_arch_sparc
, sparc32_gdbarch_init
);