1 /* Target-dependent code for the SPARC for GDB, the GNU debugger.
3 Copyright 1986, 1987, 1989, 1990, 1991, 1992, 1993, 1994, 1995,
4 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation,
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
24 /* ??? Support for calling functions from gdb in sparc64 is unfinished. */
27 #include "arch-utils.h"
34 #include "gdb_string.h"
38 #include <sys/procfs.h>
39 /* Prototypes for supply_gregset etc. */
45 #include "symfile.h" /* for 'entry_point_address' */
48 * Some local macros that have multi-arch and non-multi-arch versions:
51 #if (GDB_MULTI_ARCH > 0)
53 /* Does the target have Floating Point registers? */
54 #define SPARC_HAS_FPU (gdbarch_tdep (current_gdbarch)->has_fpu)
55 /* Number of bytes devoted to Floating Point registers: */
56 #define FP_REGISTER_BYTES (gdbarch_tdep (current_gdbarch)->fp_register_bytes)
57 /* Highest numbered Floating Point register. */
58 #define FP_MAX_REGNUM (gdbarch_tdep (current_gdbarch)->fp_max_regnum)
59 /* Size of a general (integer) register: */
60 #define SPARC_INTREG_SIZE (gdbarch_tdep (current_gdbarch)->intreg_size)
61 /* Offset within the call dummy stack of the saved registers. */
62 #define DUMMY_REG_SAVE_OFFSET (gdbarch_tdep (current_gdbarch)->reg_save_offset)
64 #else /* non-multi-arch */
67 /* Does the target have Floating Point registers? */
68 #if defined(TARGET_SPARCLET) || defined(TARGET_SPARCLITE)
69 #define SPARC_HAS_FPU 0
71 #define SPARC_HAS_FPU 1
74 /* Number of bytes devoted to Floating Point registers: */
75 #if (GDB_TARGET_IS_SPARC64)
76 #define FP_REGISTER_BYTES (64 * 4)
79 #define FP_REGISTER_BYTES (32 * 4)
81 #define FP_REGISTER_BYTES 0
85 /* Highest numbered Floating Point register. */
86 #if (GDB_TARGET_IS_SPARC64)
87 #define FP_MAX_REGNUM (FP0_REGNUM + 48)
89 #define FP_MAX_REGNUM (FP0_REGNUM + 32)
92 /* Size of a general (integer) register: */
93 #define SPARC_INTREG_SIZE (REGISTER_RAW_SIZE (G0_REGNUM))
95 /* Offset within the call dummy stack of the saved registers. */
96 #if (GDB_TARGET_IS_SPARC64)
97 #define DUMMY_REG_SAVE_OFFSET (128 + 16)
99 #define DUMMY_REG_SAVE_OFFSET 0x60
102 #endif /* GDB_MULTI_ARCH */
107 int fp_register_bytes
;
112 int call_dummy_call_offset
;
116 /* Now make GDB_TARGET_IS_SPARC64 a runtime test. */
117 /* FIXME MVS: or try testing bfd_arch_info.arch and bfd_arch_info.mach ...
118 * define GDB_TARGET_IS_SPARC64 \
119 * (TARGET_ARCHITECTURE->arch == bfd_arch_sparc && \
120 * (TARGET_ARCHITECTURE->mach == bfd_mach_sparc_v9 || \
121 * TARGET_ARCHITECTURE->mach == bfd_mach_sparc_v9a))
125 extern int stop_after_trap
;
127 /* We don't store all registers immediately when requested, since they
128 get sent over in large chunks anyway. Instead, we accumulate most
129 of the changes and send them over once. "deferred_stores" keeps
130 track of which sets of registers we have locally-changed copies of,
131 so we only need send the groups that have changed. */
133 int deferred_stores
= 0; /* Accumulated stores we want to do eventually. */
136 /* Some machines, such as Fujitsu SPARClite 86x, have a bi-endian mode
137 where instructions are big-endian and data are little-endian.
138 This flag is set when we detect that the target is of this type. */
143 /* Fetch a single instruction. Even on bi-endian machines
144 such as sparc86x, instructions are always big-endian. */
147 fetch_instruction (CORE_ADDR pc
)
149 unsigned long retval
;
151 unsigned char buf
[4];
153 read_memory (pc
, buf
, sizeof (buf
));
155 /* Start at the most significant end of the integer, and work towards
156 the least significant. */
158 for (i
= 0; i
< sizeof (buf
); ++i
)
159 retval
= (retval
<< 8) | buf
[i
];
164 /* Branches with prediction are treated like their non-predicting cousins. */
165 /* FIXME: What about floating point branches? */
167 /* Macros to extract fields from sparc instructions. */
168 #define X_OP(i) (((i) >> 30) & 0x3)
169 #define X_RD(i) (((i) >> 25) & 0x1f)
170 #define X_A(i) (((i) >> 29) & 1)
171 #define X_COND(i) (((i) >> 25) & 0xf)
172 #define X_OP2(i) (((i) >> 22) & 0x7)
173 #define X_IMM22(i) ((i) & 0x3fffff)
174 #define X_OP3(i) (((i) >> 19) & 0x3f)
175 #define X_RS1(i) (((i) >> 14) & 0x1f)
176 #define X_I(i) (((i) >> 13) & 1)
177 #define X_IMM13(i) ((i) & 0x1fff)
178 /* Sign extension macros. */
179 #define X_SIMM13(i) ((X_IMM13 (i) ^ 0x1000) - 0x1000)
180 #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000)
181 #define X_CC(i) (((i) >> 20) & 3)
182 #define X_P(i) (((i) >> 19) & 1)
183 #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000)
184 #define X_RCOND(i) (((i) >> 25) & 7)
185 #define X_DISP16(i) ((((((i) >> 6) && 0xc000) | ((i) & 0x3fff)) ^ 0x8000) - 0x8000)
186 #define X_FCN(i) (((i) >> 25) & 31)
190 Error
, not_branch
, bicc
, bicca
, ba
, baa
, ticc
, ta
, done_retry
193 /* Simulate single-step ptrace call for sun4. Code written by Gary
194 Beihl (beihl@mcc.com). */
196 /* npc4 and next_pc describe the situation at the time that the
197 step-breakpoint was set, not necessary the current value of NPC_REGNUM. */
198 static CORE_ADDR next_pc
, npc4
, target
;
199 static int brknpc4
, brktrg
;
200 typedef char binsn_quantum
[BREAKPOINT_MAX
];
201 static binsn_quantum break_mem
[3];
203 static branch_type
isbranch (long, CORE_ADDR
, CORE_ADDR
*);
205 /* single_step() is called just before we want to resume the inferior,
206 if we want to single-step it but there is no hardware or kernel single-step
207 support (as on all SPARCs). We find all the possible targets of the
208 coming instruction and breakpoint them.
210 single_step is also called just after the inferior stops. If we had
211 set up a simulated single-step, we undo our damage. */
214 sparc_software_single_step (enum target_signal ignore
, /* pid, but we don't need it */
215 int insert_breakpoints_p
)
221 if (insert_breakpoints_p
)
223 /* Always set breakpoint for NPC. */
224 next_pc
= read_register (NPC_REGNUM
);
225 npc4
= next_pc
+ 4; /* branch not taken */
227 target_insert_breakpoint (next_pc
, break_mem
[0]);
228 /* printf_unfiltered ("set break at %x\n",next_pc); */
230 pc
= read_register (PC_REGNUM
);
231 pc_instruction
= fetch_instruction (pc
);
232 br
= isbranch (pc_instruction
, pc
, &target
);
233 brknpc4
= brktrg
= 0;
237 /* Conditional annulled branch will either end up at
238 npc (if taken) or at npc+4 (if not taken).
241 target_insert_breakpoint (npc4
, break_mem
[1]);
243 else if (br
== baa
&& target
!= next_pc
)
245 /* Unconditional annulled branch will always end up at
248 target_insert_breakpoint (target
, break_mem
[2]);
250 else if (GDB_TARGET_IS_SPARC64
&& br
== done_retry
)
253 target_insert_breakpoint (target
, break_mem
[2]);
258 /* Remove breakpoints */
259 target_remove_breakpoint (next_pc
, break_mem
[0]);
262 target_remove_breakpoint (npc4
, break_mem
[1]);
265 target_remove_breakpoint (target
, break_mem
[2]);
269 struct frame_extra_info
274 /* Following fields only relevant for flat frames. */
277 /* Add this to ->frame to get the value of the stack pointer at the
278 time of the register saves. */
282 /* Call this for each newly created frame. For SPARC, we need to
283 calculate the bottom of the frame, and do some extra work if the
284 prologue has been generated via the -mflat option to GCC. In
285 particular, we need to know where the previous fp and the pc have
286 been stashed, since their exact position within the frame may vary. */
289 sparc_init_extra_frame_info (int fromleaf
, struct frame_info
*fi
)
292 CORE_ADDR prologue_start
, prologue_end
;
295 fi
->extra_info
= (struct frame_extra_info
*)
296 frame_obstack_alloc (sizeof (struct frame_extra_info
));
297 frame_saved_regs_zalloc (fi
);
299 fi
->extra_info
->bottom
=
301 (fi
->frame
== fi
->next
->frame
? fi
->next
->extra_info
->bottom
:
302 fi
->next
->frame
) : read_sp ());
304 /* If fi->next is NULL, then we already set ->frame by passing read_fp()
305 to create_new_frame. */
310 buf
= alloca (MAX_REGISTER_RAW_SIZE
);
312 /* Compute ->frame as if not flat. If it is flat, we'll change
314 if (fi
->next
->next
!= NULL
315 && (fi
->next
->next
->signal_handler_caller
316 || frame_in_dummy (fi
->next
->next
))
317 && frameless_look_for_prologue (fi
->next
))
319 /* A frameless function interrupted by a signal did not change
320 the frame pointer, fix up frame pointer accordingly. */
321 fi
->frame
= FRAME_FP (fi
->next
);
322 fi
->extra_info
->bottom
= fi
->next
->extra_info
->bottom
;
326 /* Should we adjust for stack bias here? */
327 get_saved_register (buf
, 0, 0, fi
, FP_REGNUM
, 0);
328 fi
->frame
= extract_address (buf
, REGISTER_RAW_SIZE (FP_REGNUM
));
330 if (GDB_TARGET_IS_SPARC64
&& (fi
->frame
& 1))
335 /* Decide whether this is a function with a ``flat register window''
336 frame. For such functions, the frame pointer is actually in %i7. */
337 fi
->extra_info
->flat
= 0;
338 fi
->extra_info
->in_prologue
= 0;
339 if (find_pc_partial_function (fi
->pc
, &name
, &prologue_start
, &prologue_end
))
341 /* See if the function starts with an add (which will be of a
342 negative number if a flat frame) to the sp. FIXME: Does not
343 handle large frames which will need more than one instruction
345 insn
= fetch_instruction (prologue_start
);
346 if (X_OP (insn
) == 2 && X_RD (insn
) == 14 && X_OP3 (insn
) == 0
347 && X_I (insn
) && X_SIMM13 (insn
) < 0)
349 int offset
= X_SIMM13 (insn
);
351 /* Then look for a save of %i7 into the frame. */
352 insn
= fetch_instruction (prologue_start
+ 4);
356 && X_RS1 (insn
) == 14)
360 buf
= alloca (MAX_REGISTER_RAW_SIZE
);
362 /* We definitely have a flat frame now. */
363 fi
->extra_info
->flat
= 1;
365 fi
->extra_info
->sp_offset
= offset
;
367 /* Overwrite the frame's address with the value in %i7. */
368 get_saved_register (buf
, 0, 0, fi
, I7_REGNUM
, 0);
369 fi
->frame
= extract_address (buf
, REGISTER_RAW_SIZE (I7_REGNUM
));
371 if (GDB_TARGET_IS_SPARC64
&& (fi
->frame
& 1))
374 /* Record where the fp got saved. */
375 fi
->extra_info
->fp_addr
=
376 fi
->frame
+ fi
->extra_info
->sp_offset
+ X_SIMM13 (insn
);
378 /* Also try to collect where the pc got saved to. */
379 fi
->extra_info
->pc_addr
= 0;
380 insn
= fetch_instruction (prologue_start
+ 12);
384 && X_RS1 (insn
) == 14)
385 fi
->extra_info
->pc_addr
=
386 fi
->frame
+ fi
->extra_info
->sp_offset
+ X_SIMM13 (insn
);
391 /* Check if the PC is in the function prologue before a SAVE
392 instruction has been executed yet. If so, set the frame
393 to the current value of the stack pointer and set
394 the in_prologue flag. */
396 struct symtab_and_line sal
;
398 sal
= find_pc_line (prologue_start
, 0);
399 if (sal
.line
== 0) /* no line info, use PC */
400 prologue_end
= fi
->pc
;
401 else if (sal
.end
< prologue_end
)
402 prologue_end
= sal
.end
;
403 if (fi
->pc
< prologue_end
)
405 for (addr
= prologue_start
; addr
< fi
->pc
; addr
+= 4)
407 insn
= read_memory_integer (addr
, 4);
408 if (X_OP (insn
) == 2 && X_OP3 (insn
) == 0x3c)
409 break; /* SAVE seen, stop searching */
413 fi
->extra_info
->in_prologue
= 1;
414 fi
->frame
= read_register (SP_REGNUM
);
419 if (fi
->next
&& fi
->frame
== 0)
421 /* Kludge to cause init_prev_frame_info to destroy the new frame. */
422 fi
->frame
= fi
->next
->frame
;
423 fi
->pc
= fi
->next
->pc
;
428 sparc_frame_chain (struct frame_info
*frame
)
430 /* Value that will cause FRAME_CHAIN_VALID to not worry about the chain
431 value. If it really is zero, we detect it later in
432 sparc_init_prev_frame. */
433 return (CORE_ADDR
) 1;
437 sparc_extract_struct_value_address (char *regbuf
)
439 return extract_address (regbuf
+ REGISTER_BYTE (O0_REGNUM
),
440 REGISTER_RAW_SIZE (O0_REGNUM
));
443 /* Find the pc saved in frame FRAME. */
446 sparc_frame_saved_pc (struct frame_info
*frame
)
451 buf
= alloca (MAX_REGISTER_RAW_SIZE
);
452 if (frame
->signal_handler_caller
)
454 /* This is the signal trampoline frame.
455 Get the saved PC from the sigcontext structure. */
457 #ifndef SIGCONTEXT_PC_OFFSET
458 #define SIGCONTEXT_PC_OFFSET 12
461 CORE_ADDR sigcontext_addr
;
463 int saved_pc_offset
= SIGCONTEXT_PC_OFFSET
;
466 scbuf
= alloca (TARGET_PTR_BIT
/ HOST_CHAR_BIT
);
468 /* Solaris2 ucbsigvechandler passes a pointer to a sigcontext
469 as the third parameter. The offset to the saved pc is 12. */
470 find_pc_partial_function (frame
->pc
, &name
,
471 (CORE_ADDR
*) NULL
, (CORE_ADDR
*) NULL
);
472 if (name
&& STREQ (name
, "ucbsigvechandler"))
473 saved_pc_offset
= 12;
475 /* The sigcontext address is contained in register O2. */
476 get_saved_register (buf
, (int *) NULL
, (CORE_ADDR
*) NULL
,
477 frame
, O0_REGNUM
+ 2, (enum lval_type
*) NULL
);
478 sigcontext_addr
= extract_address (buf
, REGISTER_RAW_SIZE (O0_REGNUM
+ 2));
480 /* Don't cause a memory_error when accessing sigcontext in case the
481 stack layout has changed or the stack is corrupt. */
482 target_read_memory (sigcontext_addr
+ saved_pc_offset
,
483 scbuf
, sizeof (scbuf
));
484 return extract_address (scbuf
, sizeof (scbuf
));
486 else if (frame
->extra_info
->in_prologue
||
487 (frame
->next
!= NULL
&&
488 (frame
->next
->signal_handler_caller
||
489 frame_in_dummy (frame
->next
)) &&
490 frameless_look_for_prologue (frame
)))
492 /* A frameless function interrupted by a signal did not save
493 the PC, it is still in %o7. */
494 get_saved_register (buf
, (int *) NULL
, (CORE_ADDR
*) NULL
,
495 frame
, O7_REGNUM
, (enum lval_type
*) NULL
);
496 return PC_ADJUST (extract_address (buf
, SPARC_INTREG_SIZE
));
498 if (frame
->extra_info
->flat
)
499 addr
= frame
->extra_info
->pc_addr
;
501 addr
= frame
->extra_info
->bottom
+ FRAME_SAVED_I0
+
502 SPARC_INTREG_SIZE
* (I7_REGNUM
- I0_REGNUM
);
505 /* A flat frame leaf function might not save the PC anywhere,
506 just leave it in %o7. */
507 return PC_ADJUST (read_register (O7_REGNUM
));
509 read_memory (addr
, buf
, SPARC_INTREG_SIZE
);
510 return PC_ADJUST (extract_address (buf
, SPARC_INTREG_SIZE
));
513 /* Since an individual frame in the frame cache is defined by two
514 arguments (a frame pointer and a stack pointer), we need two
515 arguments to get info for an arbitrary stack frame. This routine
516 takes two arguments and makes the cached frames look as if these
517 two arguments defined a frame on the cache. This allows the rest
518 of info frame to extract the important arguments without
522 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
524 struct frame_info
*frame
;
527 error ("Sparc frame specifications require two arguments: fp and sp");
529 frame
= create_new_frame (argv
[0], 0);
532 internal_error (__FILE__
, __LINE__
,
533 "create_new_frame returned invalid frame");
535 frame
->extra_info
->bottom
= argv
[1];
536 frame
->pc
= FRAME_SAVED_PC (frame
);
540 /* Given a pc value, skip it forward past the function prologue by
541 disassembling instructions that appear to be a prologue.
543 If FRAMELESS_P is set, we are only testing to see if the function
544 is frameless. This allows a quicker answer.
546 This routine should be more specific in its actions; making sure
547 that it uses the same register in the initial prologue section. */
549 static CORE_ADDR
examine_prologue (CORE_ADDR
, int, struct frame_info
*,
553 examine_prologue (CORE_ADDR start_pc
, int frameless_p
, struct frame_info
*fi
,
554 CORE_ADDR
*saved_regs
)
558 CORE_ADDR pc
= start_pc
;
561 insn
= fetch_instruction (pc
);
563 /* Recognize the `sethi' insn and record its destination. */
564 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 4)
568 insn
= fetch_instruction (pc
);
571 /* Recognize an add immediate value to register to either %g1 or
572 the destination register recorded above. Actually, this might
573 well recognize several different arithmetic operations.
574 It doesn't check that rs1 == rd because in theory "sub %g0, 5, %g1"
575 followed by "save %sp, %g1, %sp" is a valid prologue (Not that
576 I imagine any compiler really does that, however). */
579 && (X_RD (insn
) == 1 || X_RD (insn
) == dest
))
582 insn
= fetch_instruction (pc
);
585 /* Recognize any SAVE insn. */
586 if (X_OP (insn
) == 2 && X_OP3 (insn
) == 60)
589 if (frameless_p
) /* If the save is all we care about, */
590 return pc
; /* return before doing more work */
591 insn
= fetch_instruction (pc
);
593 /* Recognize add to %sp. */
594 else if (X_OP (insn
) == 2 && X_RD (insn
) == 14 && X_OP3 (insn
) == 0)
597 if (frameless_p
) /* If the add is all we care about, */
598 return pc
; /* return before doing more work */
600 insn
= fetch_instruction (pc
);
601 /* Recognize store of frame pointer (i7). */
605 && X_RS1 (insn
) == 14)
608 insn
= fetch_instruction (pc
);
610 /* Recognize sub %sp, <anything>, %i7. */
613 && X_RS1 (insn
) == 14
614 && X_RD (insn
) == 31)
617 insn
= fetch_instruction (pc
);
626 /* Without a save or add instruction, it's not a prologue. */
631 /* Recognize stores into the frame from the input registers.
632 This recognizes all non alternate stores of an input register,
633 into a location offset from the frame pointer between
636 /* The above will fail for arguments that are promoted
637 (eg. shorts to ints or floats to doubles), because the compiler
638 will pass them in positive-offset frame space, but the prologue
639 will save them (after conversion) in negative frame space at an
640 unpredictable offset. Therefore I am going to remove the
641 restriction on the target-address of the save, on the theory
642 that any unbroken sequence of saves from input registers must
643 be part of the prologue. In un-optimized code (at least), I'm
644 fairly sure that the compiler would emit SOME other instruction
645 (eg. a move or add) before emitting another save that is actually
646 a part of the function body.
648 Besides, the reserved stack space is different for SPARC64 anyway.
653 && (X_OP3 (insn
) & 0x3c) == 4 /* Store, non-alternate. */
654 && (X_RD (insn
) & 0x18) == 0x18 /* Input register. */
655 && X_I (insn
) /* Immediate mode. */
656 && X_RS1 (insn
) == 30) /* Off of frame pointer. */
657 ; /* empty statement -- fall thru to end of loop */
658 else if (GDB_TARGET_IS_SPARC64
660 && (X_OP3 (insn
) & 0x3c) == 12 /* store, extended (64-bit) */
661 && (X_RD (insn
) & 0x18) == 0x18 /* input register */
662 && X_I (insn
) /* immediate mode */
663 && X_RS1 (insn
) == 30) /* off of frame pointer */
664 ; /* empty statement -- fall thru to end of loop */
665 else if (X_OP (insn
) == 3
666 && (X_OP3 (insn
) & 0x3c) == 36 /* store, floating-point */
667 && X_I (insn
) /* immediate mode */
668 && X_RS1 (insn
) == 30) /* off of frame pointer */
669 ; /* empty statement -- fall thru to end of loop */
672 && X_OP3 (insn
) == 4 /* store? */
673 && X_RS1 (insn
) == 14) /* off of frame pointer */
675 if (saved_regs
&& X_I (insn
))
676 saved_regs
[X_RD (insn
)] =
677 fi
->frame
+ fi
->extra_info
->sp_offset
+ X_SIMM13 (insn
);
682 insn
= fetch_instruction (pc
);
689 sparc_skip_prologue (CORE_ADDR start_pc
, int frameless_p
)
691 return examine_prologue (start_pc
, frameless_p
, NULL
, NULL
);
694 /* Check instruction at ADDR to see if it is a branch.
695 All non-annulled instructions will go to NPC or will trap.
696 Set *TARGET if we find a candidate branch; set to zero if not.
698 This isn't static as it's used by remote-sa.sparc.c. */
701 isbranch (long instruction
, CORE_ADDR addr
, CORE_ADDR
*target
)
703 branch_type val
= not_branch
;
704 long int offset
= 0; /* Must be signed for sign-extend. */
708 if (X_OP (instruction
) == 0
709 && (X_OP2 (instruction
) == 2
710 || X_OP2 (instruction
) == 6
711 || X_OP2 (instruction
) == 1
712 || X_OP2 (instruction
) == 3
713 || X_OP2 (instruction
) == 5
714 || (GDB_TARGET_IS_SPARC64
&& X_OP2 (instruction
) == 7)))
716 if (X_COND (instruction
) == 8)
717 val
= X_A (instruction
) ? baa
: ba
;
719 val
= X_A (instruction
) ? bicca
: bicc
;
720 switch (X_OP2 (instruction
))
723 if (!GDB_TARGET_IS_SPARC64
)
728 offset
= 4 * X_DISP22 (instruction
);
732 offset
= 4 * X_DISP19 (instruction
);
735 offset
= 4 * X_DISP16 (instruction
);
738 *target
= addr
+ offset
;
740 else if (GDB_TARGET_IS_SPARC64
741 && X_OP (instruction
) == 2
742 && X_OP3 (instruction
) == 62)
744 if (X_FCN (instruction
) == 0)
747 *target
= read_register (TNPC_REGNUM
);
750 else if (X_FCN (instruction
) == 1)
753 *target
= read_register (TPC_REGNUM
);
761 /* Find register number REGNUM relative to FRAME and put its
762 (raw) contents in *RAW_BUFFER. Set *OPTIMIZED if the variable
763 was optimized out (and thus can't be fetched). If the variable
764 was fetched from memory, set *ADDRP to where it was fetched from,
765 otherwise it was fetched from a register.
767 The argument RAW_BUFFER must point to aligned memory. */
770 sparc_get_saved_register (char *raw_buffer
, int *optimized
, CORE_ADDR
*addrp
,
771 struct frame_info
*frame
, int regnum
,
772 enum lval_type
*lval
)
774 struct frame_info
*frame1
;
777 if (!target_has_registers
)
778 error ("No registers.");
785 /* FIXME This code extracted from infcmd.c; should put elsewhere! */
788 /* error ("No selected frame."); */
789 if (!target_has_registers
)
790 error ("The program has no registers now.");
791 if (selected_frame
== NULL
)
792 error ("No selected frame.");
793 /* Try to use selected frame */
794 frame
= get_prev_frame (selected_frame
);
796 error ("Cmd not meaningful in the outermost frame.");
800 frame1
= frame
->next
;
802 /* Get saved PC from the frame info if not in innermost frame. */
803 if (regnum
== PC_REGNUM
&& frame1
!= NULL
)
807 if (raw_buffer
!= NULL
)
809 /* Put it back in target format. */
810 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
), frame
->pc
);
817 while (frame1
!= NULL
)
819 /* FIXME MVS: wrong test for dummy frame at entry. */
821 if (frame1
->pc
>= (frame1
->extra_info
->bottom
?
822 frame1
->extra_info
->bottom
: read_sp ())
823 && frame1
->pc
<= FRAME_FP (frame1
))
825 /* Dummy frame. All but the window regs are in there somewhere.
826 The window registers are saved on the stack, just like in a
828 if (regnum
>= G1_REGNUM
&& regnum
< G1_REGNUM
+ 7)
829 addr
= frame1
->frame
+ (regnum
- G0_REGNUM
) * SPARC_INTREG_SIZE
830 - (FP_REGISTER_BYTES
+ 8 * SPARC_INTREG_SIZE
);
831 else if (regnum
>= I0_REGNUM
&& regnum
< I0_REGNUM
+ 8)
832 addr
= (frame1
->prev
->extra_info
->bottom
833 + (regnum
- I0_REGNUM
) * SPARC_INTREG_SIZE
835 else if (regnum
>= L0_REGNUM
&& regnum
< L0_REGNUM
+ 8)
836 addr
= (frame1
->prev
->extra_info
->bottom
837 + (regnum
- L0_REGNUM
) * SPARC_INTREG_SIZE
839 else if (regnum
>= O0_REGNUM
&& regnum
< O0_REGNUM
+ 8)
840 addr
= frame1
->frame
+ (regnum
- O0_REGNUM
) * SPARC_INTREG_SIZE
841 - (FP_REGISTER_BYTES
+ 16 * SPARC_INTREG_SIZE
);
842 else if (SPARC_HAS_FPU
&&
843 regnum
>= FP0_REGNUM
&& regnum
< FP0_REGNUM
+ 32)
844 addr
= frame1
->frame
+ (regnum
- FP0_REGNUM
) * 4
845 - (FP_REGISTER_BYTES
);
846 else if (GDB_TARGET_IS_SPARC64
&& SPARC_HAS_FPU
&&
847 regnum
>= FP0_REGNUM
+ 32 && regnum
< FP_MAX_REGNUM
)
848 addr
= frame1
->frame
+ 32 * 4 + (regnum
- FP0_REGNUM
- 32) * 8
849 - (FP_REGISTER_BYTES
);
850 else if (regnum
>= Y_REGNUM
&& regnum
< NUM_REGS
)
851 addr
= frame1
->frame
+ (regnum
- Y_REGNUM
) * SPARC_INTREG_SIZE
852 - (FP_REGISTER_BYTES
+ 24 * SPARC_INTREG_SIZE
);
854 else if (frame1
->extra_info
->flat
)
857 if (regnum
== RP_REGNUM
)
858 addr
= frame1
->extra_info
->pc_addr
;
859 else if (regnum
== I7_REGNUM
)
860 addr
= frame1
->extra_info
->fp_addr
;
863 CORE_ADDR func_start
;
866 regs
= alloca (NUM_REGS
* sizeof (CORE_ADDR
));
867 memset (regs
, 0, NUM_REGS
* sizeof (CORE_ADDR
));
869 find_pc_partial_function (frame1
->pc
, NULL
, &func_start
, NULL
);
870 examine_prologue (func_start
, 0, frame1
, regs
);
876 /* Normal frame. Local and In registers are saved on stack. */
877 if (regnum
>= I0_REGNUM
&& regnum
< I0_REGNUM
+ 8)
878 addr
= (frame1
->prev
->extra_info
->bottom
879 + (regnum
- I0_REGNUM
) * SPARC_INTREG_SIZE
881 else if (regnum
>= L0_REGNUM
&& regnum
< L0_REGNUM
+ 8)
882 addr
= (frame1
->prev
->extra_info
->bottom
883 + (regnum
- L0_REGNUM
) * SPARC_INTREG_SIZE
885 else if (regnum
>= O0_REGNUM
&& regnum
< O0_REGNUM
+ 8)
887 /* Outs become ins. */
888 get_saved_register (raw_buffer
, optimized
, addrp
, frame1
,
889 (regnum
- O0_REGNUM
+ I0_REGNUM
), lval
);
895 frame1
= frame1
->next
;
901 if (regnum
== SP_REGNUM
)
903 if (raw_buffer
!= NULL
)
905 /* Put it back in target format. */
906 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
), addr
);
912 if (raw_buffer
!= NULL
)
913 read_memory (addr
, raw_buffer
, REGISTER_RAW_SIZE (regnum
));
918 *lval
= lval_register
;
919 addr
= REGISTER_BYTE (regnum
);
920 if (raw_buffer
!= NULL
)
921 read_register_gen (regnum
, raw_buffer
);
927 /* Push an empty stack frame, and record in it the current PC, regs, etc.
929 We save the non-windowed registers and the ins. The locals and outs
930 are new; they don't need to be saved. The i's and l's of
931 the last frame were already saved on the stack. */
933 /* Definitely see tm-sparc.h for more doc of the frame format here. */
935 /* See tm-sparc.h for how this is calculated. */
937 #define DUMMY_STACK_REG_BUF_SIZE \
938 (((8+8+8) * SPARC_INTREG_SIZE) + FP_REGISTER_BYTES)
939 #define DUMMY_STACK_SIZE \
940 (DUMMY_STACK_REG_BUF_SIZE + DUMMY_REG_SAVE_OFFSET)
943 sparc_push_dummy_frame (void)
945 CORE_ADDR sp
, old_sp
;
948 register_temp
= alloca (DUMMY_STACK_SIZE
);
950 old_sp
= sp
= read_sp ();
952 if (GDB_TARGET_IS_SPARC64
)
954 /* PC, NPC, CCR, FSR, FPRS, Y, ASI */
955 read_register_bytes (REGISTER_BYTE (PC_REGNUM
), ®ister_temp
[0],
956 REGISTER_RAW_SIZE (PC_REGNUM
) * 7);
957 read_register_bytes (REGISTER_BYTE (PSTATE_REGNUM
),
958 ®ister_temp
[7 * SPARC_INTREG_SIZE
],
959 REGISTER_RAW_SIZE (PSTATE_REGNUM
));
960 /* FIXME: not sure what needs to be saved here. */
964 /* Y, PS, WIM, TBR, PC, NPC, FPS, CPS regs */
965 read_register_bytes (REGISTER_BYTE (Y_REGNUM
), ®ister_temp
[0],
966 REGISTER_RAW_SIZE (Y_REGNUM
) * 8);
969 read_register_bytes (REGISTER_BYTE (O0_REGNUM
),
970 ®ister_temp
[8 * SPARC_INTREG_SIZE
],
971 SPARC_INTREG_SIZE
* 8);
973 read_register_bytes (REGISTER_BYTE (G0_REGNUM
),
974 ®ister_temp
[16 * SPARC_INTREG_SIZE
],
975 SPARC_INTREG_SIZE
* 8);
978 read_register_bytes (REGISTER_BYTE (FP0_REGNUM
),
979 ®ister_temp
[24 * SPARC_INTREG_SIZE
],
982 sp
-= DUMMY_STACK_SIZE
;
986 write_memory (sp
+ DUMMY_REG_SAVE_OFFSET
, ®ister_temp
[0],
987 DUMMY_STACK_REG_BUF_SIZE
);
989 if (strcmp (target_shortname
, "sim") != 0)
991 /* NOTE: cagney/2002-04-04: The code below originally contained
992 GDB's _only_ call to write_fp(). That call was eliminated by
993 inlining the corresponding code. For the 64 bit case, the
994 old function (sparc64_write_fp) did the below although I'm
995 not clear why. The same goes for why this is only done when
996 the underlying target is a simulator. */
997 if (GDB_TARGET_IS_SPARC64
)
999 /* Target is a 64 bit SPARC. */
1000 CORE_ADDR oldfp
= read_register (FP_REGNUM
);
1002 write_register (FP_REGNUM
, old_sp
- 2047);
1004 write_register (FP_REGNUM
, old_sp
);
1008 /* Target is a 32 bit SPARC. */
1009 write_register (FP_REGNUM
, old_sp
);
1011 /* Set return address register for the call dummy to the current PC. */
1012 write_register (I7_REGNUM
, read_pc () - 8);
1016 /* The call dummy will write this value to FP before executing
1017 the 'save'. This ensures that register window flushes work
1018 correctly in the simulator. */
1019 write_register (G0_REGNUM
+ 1, read_register (FP_REGNUM
));
1021 /* The call dummy will write this value to FP after executing
1023 write_register (G0_REGNUM
+ 2, old_sp
);
1025 /* The call dummy will write this value to the return address (%i7) after
1026 executing the 'save'. */
1027 write_register (G0_REGNUM
+ 3, read_pc () - 8);
1029 /* Set the FP that the call dummy will be using after the 'save'.
1030 This makes backtraces from an inferior function call work properly. */
1031 write_register (FP_REGNUM
, old_sp
);
1035 /* sparc_frame_find_saved_regs (). This function is here only because
1036 pop_frame uses it. Note there is an interesting corner case which
1037 I think few ports of GDB get right--if you are popping a frame
1038 which does not save some register that *is* saved by a more inner
1039 frame (such a frame will never be a dummy frame because dummy
1040 frames save all registers). Rewriting pop_frame to use
1041 get_saved_register would solve this problem and also get rid of the
1042 ugly duplication between sparc_frame_find_saved_regs and
1045 Stores, into an array of CORE_ADDR,
1046 the addresses of the saved registers of frame described by FRAME_INFO.
1047 This includes special registers such as pc and fp saved in special
1048 ways in the stack frame. sp is even more special:
1049 the address we return for it IS the sp for the next frame.
1051 Note that on register window machines, we are currently making the
1052 assumption that window registers are being saved somewhere in the
1053 frame in which they are being used. If they are stored in an
1054 inferior frame, find_saved_register will break.
1056 On the Sun 4, the only time all registers are saved is when
1057 a dummy frame is involved. Otherwise, the only saved registers
1058 are the LOCAL and IN registers which are saved as a result
1059 of the "save/restore" opcodes. This condition is determined
1060 by address rather than by value.
1062 The "pc" is not stored in a frame on the SPARC. (What is stored
1063 is a return address minus 8.) sparc_pop_frame knows how to
1064 deal with that. Other routines might or might not.
1066 See tm-sparc.h (PUSH_DUMMY_FRAME and friends) for CRITICAL information
1067 about how this works. */
1069 static void sparc_frame_find_saved_regs (struct frame_info
*, CORE_ADDR
*);
1072 sparc_frame_find_saved_regs (struct frame_info
*fi
, CORE_ADDR
*saved_regs_addr
)
1074 register int regnum
;
1075 CORE_ADDR frame_addr
= FRAME_FP (fi
);
1078 internal_error (__FILE__
, __LINE__
,
1079 "Bad frame info struct in FRAME_FIND_SAVED_REGS");
1081 memset (saved_regs_addr
, 0, NUM_REGS
* sizeof (CORE_ADDR
));
1083 if (fi
->pc
>= (fi
->extra_info
->bottom
?
1084 fi
->extra_info
->bottom
: read_sp ())
1085 && fi
->pc
<= FRAME_FP (fi
))
1087 /* Dummy frame. All but the window regs are in there somewhere. */
1088 for (regnum
= G1_REGNUM
; regnum
< G1_REGNUM
+ 7; regnum
++)
1089 saved_regs_addr
[regnum
] =
1090 frame_addr
+ (regnum
- G0_REGNUM
) * SPARC_INTREG_SIZE
1091 - DUMMY_STACK_REG_BUF_SIZE
+ 16 * SPARC_INTREG_SIZE
;
1093 for (regnum
= I0_REGNUM
; regnum
< I0_REGNUM
+ 8; regnum
++)
1094 saved_regs_addr
[regnum
] =
1095 frame_addr
+ (regnum
- I0_REGNUM
) * SPARC_INTREG_SIZE
1096 - DUMMY_STACK_REG_BUF_SIZE
+ 8 * SPARC_INTREG_SIZE
;
1099 for (regnum
= FP0_REGNUM
; regnum
< FP_MAX_REGNUM
; regnum
++)
1100 saved_regs_addr
[regnum
] = frame_addr
+ (regnum
- FP0_REGNUM
) * 4
1101 - DUMMY_STACK_REG_BUF_SIZE
+ 24 * SPARC_INTREG_SIZE
;
1103 if (GDB_TARGET_IS_SPARC64
)
1105 for (regnum
= PC_REGNUM
; regnum
< PC_REGNUM
+ 7; regnum
++)
1107 saved_regs_addr
[regnum
] =
1108 frame_addr
+ (regnum
- PC_REGNUM
) * SPARC_INTREG_SIZE
1109 - DUMMY_STACK_REG_BUF_SIZE
;
1111 saved_regs_addr
[PSTATE_REGNUM
] =
1112 frame_addr
+ 8 * SPARC_INTREG_SIZE
- DUMMY_STACK_REG_BUF_SIZE
;
1115 for (regnum
= Y_REGNUM
; regnum
< NUM_REGS
; regnum
++)
1116 saved_regs_addr
[regnum
] =
1117 frame_addr
+ (regnum
- Y_REGNUM
) * SPARC_INTREG_SIZE
1118 - DUMMY_STACK_REG_BUF_SIZE
;
1120 frame_addr
= fi
->extra_info
->bottom
?
1121 fi
->extra_info
->bottom
: read_sp ();
1123 else if (fi
->extra_info
->flat
)
1125 CORE_ADDR func_start
;
1126 find_pc_partial_function (fi
->pc
, NULL
, &func_start
, NULL
);
1127 examine_prologue (func_start
, 0, fi
, saved_regs_addr
);
1129 /* Flat register window frame. */
1130 saved_regs_addr
[RP_REGNUM
] = fi
->extra_info
->pc_addr
;
1131 saved_regs_addr
[I7_REGNUM
] = fi
->extra_info
->fp_addr
;
1135 /* Normal frame. Just Local and In registers */
1136 frame_addr
= fi
->extra_info
->bottom
?
1137 fi
->extra_info
->bottom
: read_sp ();
1138 for (regnum
= L0_REGNUM
; regnum
< L0_REGNUM
+ 8; regnum
++)
1139 saved_regs_addr
[regnum
] =
1140 (frame_addr
+ (regnum
- L0_REGNUM
) * SPARC_INTREG_SIZE
1142 for (regnum
= I0_REGNUM
; regnum
< I0_REGNUM
+ 8; regnum
++)
1143 saved_regs_addr
[regnum
] =
1144 (frame_addr
+ (regnum
- I0_REGNUM
) * SPARC_INTREG_SIZE
1149 if (fi
->extra_info
->flat
)
1151 saved_regs_addr
[O7_REGNUM
] = fi
->extra_info
->pc_addr
;
1155 /* Pull off either the next frame pointer or the stack pointer */
1156 CORE_ADDR next_next_frame_addr
=
1157 (fi
->next
->extra_info
->bottom
?
1158 fi
->next
->extra_info
->bottom
: read_sp ());
1159 for (regnum
= O0_REGNUM
; regnum
< O0_REGNUM
+ 8; regnum
++)
1160 saved_regs_addr
[regnum
] =
1161 (next_next_frame_addr
1162 + (regnum
- O0_REGNUM
) * SPARC_INTREG_SIZE
1166 /* Otherwise, whatever we would get from ptrace(GETREGS) is accurate */
1167 /* FIXME -- should this adjust for the sparc64 offset? */
1168 saved_regs_addr
[SP_REGNUM
] = FRAME_FP (fi
);
1171 /* Discard from the stack the innermost frame, restoring all saved registers.
1173 Note that the values stored in fsr by get_frame_saved_regs are *in
1174 the context of the called frame*. What this means is that the i
1175 regs of fsr must be restored into the o regs of the (calling) frame that
1176 we pop into. We don't care about the output regs of the calling frame,
1177 since unless it's a dummy frame, it won't have any output regs in it.
1179 We never have to bother with %l (local) regs, since the called routine's
1180 locals get tossed, and the calling routine's locals are already saved
1183 /* Definitely see tm-sparc.h for more doc of the frame format here. */
1186 sparc_pop_frame (void)
1188 register struct frame_info
*frame
= get_current_frame ();
1189 register CORE_ADDR pc
;
1194 fsr
= alloca (NUM_REGS
* sizeof (CORE_ADDR
));
1195 raw_buffer
= alloca (REGISTER_BYTES
);
1196 sparc_frame_find_saved_regs (frame
, &fsr
[0]);
1199 if (fsr
[FP0_REGNUM
])
1201 read_memory (fsr
[FP0_REGNUM
], raw_buffer
, FP_REGISTER_BYTES
);
1202 write_register_bytes (REGISTER_BYTE (FP0_REGNUM
),
1203 raw_buffer
, FP_REGISTER_BYTES
);
1205 if (!(GDB_TARGET_IS_SPARC64
))
1207 if (fsr
[FPS_REGNUM
])
1209 read_memory (fsr
[FPS_REGNUM
], raw_buffer
, SPARC_INTREG_SIZE
);
1210 write_register_gen (FPS_REGNUM
, raw_buffer
);
1212 if (fsr
[CPS_REGNUM
])
1214 read_memory (fsr
[CPS_REGNUM
], raw_buffer
, SPARC_INTREG_SIZE
);
1215 write_register_gen (CPS_REGNUM
, raw_buffer
);
1221 read_memory (fsr
[G1_REGNUM
], raw_buffer
, 7 * SPARC_INTREG_SIZE
);
1222 write_register_bytes (REGISTER_BYTE (G1_REGNUM
), raw_buffer
,
1223 7 * SPARC_INTREG_SIZE
);
1226 if (frame
->extra_info
->flat
)
1228 /* Each register might or might not have been saved, need to test
1230 for (regnum
= L0_REGNUM
; regnum
< L0_REGNUM
+ 8; ++regnum
)
1232 write_register (regnum
, read_memory_integer (fsr
[regnum
],
1233 SPARC_INTREG_SIZE
));
1234 for (regnum
= I0_REGNUM
; regnum
< I0_REGNUM
+ 8; ++regnum
)
1236 write_register (regnum
, read_memory_integer (fsr
[regnum
],
1237 SPARC_INTREG_SIZE
));
1239 /* Handle all outs except stack pointer (o0-o5; o7). */
1240 for (regnum
= O0_REGNUM
; regnum
< O0_REGNUM
+ 6; ++regnum
)
1242 write_register (regnum
, read_memory_integer (fsr
[regnum
],
1243 SPARC_INTREG_SIZE
));
1244 if (fsr
[O0_REGNUM
+ 7])
1245 write_register (O0_REGNUM
+ 7,
1246 read_memory_integer (fsr
[O0_REGNUM
+ 7],
1247 SPARC_INTREG_SIZE
));
1249 write_sp (frame
->frame
);
1251 else if (fsr
[I0_REGNUM
])
1257 reg_temp
= alloca (REGISTER_BYTES
);
1259 read_memory (fsr
[I0_REGNUM
], raw_buffer
, 8 * SPARC_INTREG_SIZE
);
1261 /* Get the ins and locals which we are about to restore. Just
1262 moving the stack pointer is all that is really needed, except
1263 store_inferior_registers is then going to write the ins and
1264 locals from the registers array, so we need to muck with the
1266 sp
= fsr
[SP_REGNUM
];
1268 if (GDB_TARGET_IS_SPARC64
&& (sp
& 1))
1271 read_memory (sp
, reg_temp
, SPARC_INTREG_SIZE
* 16);
1273 /* Restore the out registers.
1274 Among other things this writes the new stack pointer. */
1275 write_register_bytes (REGISTER_BYTE (O0_REGNUM
), raw_buffer
,
1276 SPARC_INTREG_SIZE
* 8);
1278 write_register_bytes (REGISTER_BYTE (L0_REGNUM
), reg_temp
,
1279 SPARC_INTREG_SIZE
* 16);
1282 if (!(GDB_TARGET_IS_SPARC64
))
1284 write_register (PS_REGNUM
,
1285 read_memory_integer (fsr
[PS_REGNUM
],
1286 REGISTER_RAW_SIZE (PS_REGNUM
)));
1289 write_register (Y_REGNUM
,
1290 read_memory_integer (fsr
[Y_REGNUM
],
1291 REGISTER_RAW_SIZE (Y_REGNUM
)));
1294 /* Explicitly specified PC (and maybe NPC) -- just restore them. */
1295 write_register (PC_REGNUM
,
1296 read_memory_integer (fsr
[PC_REGNUM
],
1297 REGISTER_RAW_SIZE (PC_REGNUM
)));
1298 if (fsr
[NPC_REGNUM
])
1299 write_register (NPC_REGNUM
,
1300 read_memory_integer (fsr
[NPC_REGNUM
],
1301 REGISTER_RAW_SIZE (NPC_REGNUM
)));
1303 else if (frame
->extra_info
->flat
)
1305 if (frame
->extra_info
->pc_addr
)
1306 pc
= PC_ADJUST ((CORE_ADDR
)
1307 read_memory_integer (frame
->extra_info
->pc_addr
,
1308 REGISTER_RAW_SIZE (PC_REGNUM
)));
1311 /* I think this happens only in the innermost frame, if so then
1312 it is a complicated way of saying
1313 "pc = read_register (O7_REGNUM);". */
1316 buf
= alloca (MAX_REGISTER_RAW_SIZE
);
1317 get_saved_register (buf
, 0, 0, frame
, O7_REGNUM
, 0);
1318 pc
= PC_ADJUST (extract_address
1319 (buf
, REGISTER_RAW_SIZE (O7_REGNUM
)));
1322 write_register (PC_REGNUM
, pc
);
1323 write_register (NPC_REGNUM
, pc
+ 4);
1325 else if (fsr
[I7_REGNUM
])
1327 /* Return address in %i7 -- adjust it, then restore PC and NPC from it */
1328 pc
= PC_ADJUST ((CORE_ADDR
) read_memory_integer (fsr
[I7_REGNUM
],
1329 SPARC_INTREG_SIZE
));
1330 write_register (PC_REGNUM
, pc
);
1331 write_register (NPC_REGNUM
, pc
+ 4);
1333 flush_cached_frames ();
1336 /* On the Sun 4 under SunOS, the compile will leave a fake insn which
1337 encodes the structure size being returned. If we detect such
1338 a fake insn, step past it. */
1341 sparc_pc_adjust (CORE_ADDR pc
)
1347 err
= target_read_memory (pc
+ 8, buf
, 4);
1348 insn
= extract_unsigned_integer (buf
, 4);
1349 if ((err
== 0) && (insn
& 0xffc00000) == 0)
1355 /* If pc is in a shared library trampoline, return its target.
1356 The SunOs 4.x linker rewrites the jump table entries for PIC
1357 compiled modules in the main executable to bypass the dynamic linker
1358 with jumps of the form
1361 and removes the corresponding jump table relocation entry in the
1362 dynamic relocations.
1363 find_solib_trampoline_target relies on the presence of the jump
1364 table relocation entry, so we have to detect these jump instructions
1368 sunos4_skip_trampoline_code (CORE_ADDR pc
)
1370 unsigned long insn1
;
1374 err
= target_read_memory (pc
, buf
, 4);
1375 insn1
= extract_unsigned_integer (buf
, 4);
1376 if (err
== 0 && (insn1
& 0xffc00000) == 0x03000000)
1378 unsigned long insn2
;
1380 err
= target_read_memory (pc
+ 4, buf
, 4);
1381 insn2
= extract_unsigned_integer (buf
, 4);
1382 if (err
== 0 && (insn2
& 0xffffe000) == 0x81c06000)
1384 CORE_ADDR target_pc
= (insn1
& 0x3fffff) << 10;
1385 int delta
= insn2
& 0x1fff;
1387 /* Sign extend the displacement. */
1390 return target_pc
+ delta
;
1393 return find_solib_trampoline_target (pc
);
1396 #ifdef USE_PROC_FS /* Target dependent support for /proc */
1398 /* The /proc interface divides the target machine's register set up into
1399 two different sets, the general register set (gregset) and the floating
1400 point register set (fpregset). For each set, there is an ioctl to get
1401 the current register set and another ioctl to set the current values.
1403 The actual structure passed through the ioctl interface is, of course,
1404 naturally machine dependent, and is different for each set of registers.
1405 For the sparc for example, the general register set is typically defined
1408 typedef int gregset_t[38];
1414 and the floating point set by:
1416 typedef struct prfpregset {
1419 double pr_dregs[16];
1424 u_char pr_q_entrysize;
1429 These routines provide the packing and unpacking of gregset_t and
1430 fpregset_t formatted data.
1435 /* Given a pointer to a general register set in /proc format (gregset_t *),
1436 unpack the register contents and supply them as gdb's idea of the current
1440 supply_gregset (gdb_gregset_t
*gregsetp
)
1442 prgreg_t
*regp
= (prgreg_t
*) gregsetp
;
1443 int regi
, offset
= 0;
1445 /* If the host is 64-bit sparc, but the target is 32-bit sparc,
1446 then the gregset may contain 64-bit ints while supply_register
1447 is expecting 32-bit ints. Compensate. */
1448 if (sizeof (regp
[0]) == 8 && SPARC_INTREG_SIZE
== 4)
1451 /* GDB register numbers for Gn, On, Ln, In all match /proc reg numbers. */
1452 /* FIXME MVS: assumes the order of the first 32 elements... */
1453 for (regi
= G0_REGNUM
; regi
<= I7_REGNUM
; regi
++)
1455 supply_register (regi
, ((char *) (regp
+ regi
)) + offset
);
1458 /* These require a bit more care. */
1459 supply_register (PC_REGNUM
, ((char *) (regp
+ R_PC
)) + offset
);
1460 supply_register (NPC_REGNUM
, ((char *) (regp
+ R_nPC
)) + offset
);
1461 supply_register (Y_REGNUM
, ((char *) (regp
+ R_Y
)) + offset
);
1463 if (GDB_TARGET_IS_SPARC64
)
1466 supply_register (CCR_REGNUM
, ((char *) (regp
+ R_CCR
)) + offset
);
1468 supply_register (CCR_REGNUM
, NULL
);
1471 supply_register (FPRS_REGNUM
, ((char *) (regp
+ R_FPRS
)) + offset
);
1473 supply_register (FPRS_REGNUM
, NULL
);
1476 supply_register (ASI_REGNUM
, ((char *) (regp
+ R_ASI
)) + offset
);
1478 supply_register (ASI_REGNUM
, NULL
);
1484 supply_register (PS_REGNUM
, ((char *) (regp
+ R_PS
)) + offset
);
1486 supply_register (PS_REGNUM
, NULL
);
1489 /* For 64-bit hosts, R_WIM and R_TBR may not be defined.
1490 Steal R_ASI and R_FPRS, and hope for the best! */
1492 #if !defined (R_WIM) && defined (R_ASI)
1496 #if !defined (R_TBR) && defined (R_FPRS)
1497 #define R_TBR R_FPRS
1501 supply_register (WIM_REGNUM
, ((char *) (regp
+ R_WIM
)) + offset
);
1503 supply_register (WIM_REGNUM
, NULL
);
1507 supply_register (TBR_REGNUM
, ((char *) (regp
+ R_TBR
)) + offset
);
1509 supply_register (TBR_REGNUM
, NULL
);
1513 /* Fill inaccessible registers with zero. */
1514 if (GDB_TARGET_IS_SPARC64
)
1517 * don't know how to get value of any of the following:
1519 supply_register (VER_REGNUM
, NULL
);
1520 supply_register (TICK_REGNUM
, NULL
);
1521 supply_register (PIL_REGNUM
, NULL
);
1522 supply_register (PSTATE_REGNUM
, NULL
);
1523 supply_register (TSTATE_REGNUM
, NULL
);
1524 supply_register (TBA_REGNUM
, NULL
);
1525 supply_register (TL_REGNUM
, NULL
);
1526 supply_register (TT_REGNUM
, NULL
);
1527 supply_register (TPC_REGNUM
, NULL
);
1528 supply_register (TNPC_REGNUM
, NULL
);
1529 supply_register (WSTATE_REGNUM
, NULL
);
1530 supply_register (CWP_REGNUM
, NULL
);
1531 supply_register (CANSAVE_REGNUM
, NULL
);
1532 supply_register (CANRESTORE_REGNUM
, NULL
);
1533 supply_register (CLEANWIN_REGNUM
, NULL
);
1534 supply_register (OTHERWIN_REGNUM
, NULL
);
1535 supply_register (ASR16_REGNUM
, NULL
);
1536 supply_register (ASR17_REGNUM
, NULL
);
1537 supply_register (ASR18_REGNUM
, NULL
);
1538 supply_register (ASR19_REGNUM
, NULL
);
1539 supply_register (ASR20_REGNUM
, NULL
);
1540 supply_register (ASR21_REGNUM
, NULL
);
1541 supply_register (ASR22_REGNUM
, NULL
);
1542 supply_register (ASR23_REGNUM
, NULL
);
1543 supply_register (ASR24_REGNUM
, NULL
);
1544 supply_register (ASR25_REGNUM
, NULL
);
1545 supply_register (ASR26_REGNUM
, NULL
);
1546 supply_register (ASR27_REGNUM
, NULL
);
1547 supply_register (ASR28_REGNUM
, NULL
);
1548 supply_register (ASR29_REGNUM
, NULL
);
1549 supply_register (ASR30_REGNUM
, NULL
);
1550 supply_register (ASR31_REGNUM
, NULL
);
1551 supply_register (ICC_REGNUM
, NULL
);
1552 supply_register (XCC_REGNUM
, NULL
);
1556 supply_register (CPS_REGNUM
, NULL
);
1561 fill_gregset (gdb_gregset_t
*gregsetp
, int regno
)
1563 prgreg_t
*regp
= (prgreg_t
*) gregsetp
;
1564 int regi
, offset
= 0;
1566 /* If the host is 64-bit sparc, but the target is 32-bit sparc,
1567 then the gregset may contain 64-bit ints while supply_register
1568 is expecting 32-bit ints. Compensate. */
1569 if (sizeof (regp
[0]) == 8 && SPARC_INTREG_SIZE
== 4)
1572 for (regi
= 0; regi
<= R_I7
; regi
++)
1573 if ((regno
== -1) || (regno
== regi
))
1574 read_register_gen (regi
, (char *) (regp
+ regi
) + offset
);
1576 if ((regno
== -1) || (regno
== PC_REGNUM
))
1577 read_register_gen (PC_REGNUM
, (char *) (regp
+ R_PC
) + offset
);
1579 if ((regno
== -1) || (regno
== NPC_REGNUM
))
1580 read_register_gen (NPC_REGNUM
, (char *) (regp
+ R_nPC
) + offset
);
1582 if ((regno
== -1) || (regno
== Y_REGNUM
))
1583 read_register_gen (Y_REGNUM
, (char *) (regp
+ R_Y
) + offset
);
1585 if (GDB_TARGET_IS_SPARC64
)
1588 if (regno
== -1 || regno
== CCR_REGNUM
)
1589 read_register_gen (CCR_REGNUM
, ((char *) (regp
+ R_CCR
)) + offset
);
1592 if (regno
== -1 || regno
== FPRS_REGNUM
)
1593 read_register_gen (FPRS_REGNUM
, ((char *) (regp
+ R_FPRS
)) + offset
);
1596 if (regno
== -1 || regno
== ASI_REGNUM
)
1597 read_register_gen (ASI_REGNUM
, ((char *) (regp
+ R_ASI
)) + offset
);
1603 if (regno
== -1 || regno
== PS_REGNUM
)
1604 read_register_gen (PS_REGNUM
, ((char *) (regp
+ R_PS
)) + offset
);
1607 /* For 64-bit hosts, R_WIM and R_TBR may not be defined.
1608 Steal R_ASI and R_FPRS, and hope for the best! */
1610 #if !defined (R_WIM) && defined (R_ASI)
1614 #if !defined (R_TBR) && defined (R_FPRS)
1615 #define R_TBR R_FPRS
1619 if (regno
== -1 || regno
== WIM_REGNUM
)
1620 read_register_gen (WIM_REGNUM
, ((char *) (regp
+ R_WIM
)) + offset
);
1622 if (regno
== -1 || regno
== WIM_REGNUM
)
1623 read_register_gen (WIM_REGNUM
, NULL
);
1627 if (regno
== -1 || regno
== TBR_REGNUM
)
1628 read_register_gen (TBR_REGNUM
, ((char *) (regp
+ R_TBR
)) + offset
);
1630 if (regno
== -1 || regno
== TBR_REGNUM
)
1631 read_register_gen (TBR_REGNUM
, NULL
);
1636 /* Given a pointer to a floating point register set in /proc format
1637 (fpregset_t *), unpack the register contents and supply them as gdb's
1638 idea of the current floating point register values. */
1641 supply_fpregset (gdb_fpregset_t
*fpregsetp
)
1649 for (regi
= FP0_REGNUM
; regi
< FP_MAX_REGNUM
; regi
++)
1651 from
= (char *) &fpregsetp
->pr_fr
.pr_regs
[regi
- FP0_REGNUM
];
1652 supply_register (regi
, from
);
1655 if (GDB_TARGET_IS_SPARC64
)
1658 * don't know how to get value of the following.
1660 supply_register (FSR_REGNUM
, NULL
); /* zero it out for now */
1661 supply_register (FCC0_REGNUM
, NULL
);
1662 supply_register (FCC1_REGNUM
, NULL
); /* don't know how to get value */
1663 supply_register (FCC2_REGNUM
, NULL
); /* don't know how to get value */
1664 supply_register (FCC3_REGNUM
, NULL
); /* don't know how to get value */
1668 supply_register (FPS_REGNUM
, (char *) &(fpregsetp
->pr_fsr
));
1672 /* Given a pointer to a floating point register set in /proc format
1673 (fpregset_t *), update the register specified by REGNO from gdb's idea
1674 of the current floating point register set. If REGNO is -1, update
1676 /* This will probably need some changes for sparc64. */
1679 fill_fpregset (gdb_fpregset_t
*fpregsetp
, int regno
)
1688 for (regi
= FP0_REGNUM
; regi
< FP_MAX_REGNUM
; regi
++)
1690 if ((regno
== -1) || (regno
== regi
))
1692 from
= (char *) ®isters
[REGISTER_BYTE (regi
)];
1693 to
= (char *) &fpregsetp
->pr_fr
.pr_regs
[regi
- FP0_REGNUM
];
1694 memcpy (to
, from
, REGISTER_RAW_SIZE (regi
));
1698 if (!(GDB_TARGET_IS_SPARC64
)) /* FIXME: does Sparc64 have this register? */
1699 if ((regno
== -1) || (regno
== FPS_REGNUM
))
1701 from
= (char *)®isters
[REGISTER_BYTE (FPS_REGNUM
)];
1702 to
= (char *) &fpregsetp
->pr_fsr
;
1703 memcpy (to
, from
, REGISTER_RAW_SIZE (FPS_REGNUM
));
1707 #endif /* USE_PROC_FS */
1709 /* Because of Multi-arch, GET_LONGJMP_TARGET is always defined. So test
1710 for a definition of JB_PC. */
1713 /* Figure out where the longjmp will land. We expect that we have just entered
1714 longjmp and haven't yet setup the stack frame, so the args are still in the
1715 output regs. %o0 (O0_REGNUM) points at the jmp_buf structure from which we
1716 extract the pc (JB_PC) that we will land at. The pc is copied into ADDR.
1717 This routine returns true on success */
1720 get_longjmp_target (CORE_ADDR
*pc
)
1723 #define LONGJMP_TARGET_SIZE 4
1724 char buf
[LONGJMP_TARGET_SIZE
];
1726 jb_addr
= read_register (O0_REGNUM
);
1728 if (target_read_memory (jb_addr
+ JB_PC
* JB_ELEMENT_SIZE
, buf
,
1729 LONGJMP_TARGET_SIZE
))
1732 *pc
= extract_address (buf
, LONGJMP_TARGET_SIZE
);
1736 #endif /* GET_LONGJMP_TARGET */
1738 #ifdef STATIC_TRANSFORM_NAME
1739 /* SunPRO (3.0 at least), encodes the static variables. This is not
1740 related to C++ mangling, it is done for C too. */
1743 sunpro_static_transform_name (char *name
)
1748 /* For file-local statics there will be a dollar sign, a bunch
1749 of junk (the contents of which match a string given in the
1750 N_OPT), a period and the name. For function-local statics
1751 there will be a bunch of junk (which seems to change the
1752 second character from 'A' to 'B'), a period, the name of the
1753 function, and the name. So just skip everything before the
1755 p
= strrchr (name
, '.');
1761 #endif /* STATIC_TRANSFORM_NAME */
1764 /* Utilities for printing registers.
1765 Page numbers refer to the SPARC Architecture Manual. */
1767 static void dump_ccreg (char *, int);
1770 dump_ccreg (char *reg
, int val
)
1773 printf_unfiltered ("%s:%s,%s,%s,%s", reg
,
1774 val
& 8 ? "N" : "NN",
1775 val
& 4 ? "Z" : "NZ",
1776 val
& 2 ? "O" : "NO",
1777 val
& 1 ? "C" : "NC");
1781 decode_asi (int val
)
1787 return "ASI_NUCLEUS";
1789 return "ASI_NUCLEUS_LITTLE";
1791 return "ASI_AS_IF_USER_PRIMARY";
1793 return "ASI_AS_IF_USER_SECONDARY";
1795 return "ASI_AS_IF_USER_PRIMARY_LITTLE";
1797 return "ASI_AS_IF_USER_SECONDARY_LITTLE";
1799 return "ASI_PRIMARY";
1801 return "ASI_SECONDARY";
1803 return "ASI_PRIMARY_NOFAULT";
1805 return "ASI_SECONDARY_NOFAULT";
1807 return "ASI_PRIMARY_LITTLE";
1809 return "ASI_SECONDARY_LITTLE";
1811 return "ASI_PRIMARY_NOFAULT_LITTLE";
1813 return "ASI_SECONDARY_NOFAULT_LITTLE";
1819 /* PRINT_REGISTER_HOOK routine.
1820 Pretty print various registers. */
1821 /* FIXME: Would be nice if this did some fancy things for 32 bit sparc. */
1824 sparc_print_register_hook (int regno
)
1828 /* Handle double/quad versions of lower 32 fp regs. */
1829 if (regno
>= FP0_REGNUM
&& regno
< FP0_REGNUM
+ 32
1830 && (regno
& 1) == 0)
1834 if (frame_register_read (selected_frame
, regno
, value
)
1835 && frame_register_read (selected_frame
, regno
+ 1, value
+ 4))
1837 printf_unfiltered ("\t");
1838 print_floating (value
, builtin_type_double
, gdb_stdout
);
1840 #if 0 /* FIXME: gdb doesn't handle long doubles */
1841 if ((regno
& 3) == 0)
1843 if (frame_register_read (selected_frame
, regno
+ 2, value
+ 8)
1844 && frame_register_read (selected_frame
, regno
+ 3, value
+ 12))
1846 printf_unfiltered ("\t");
1847 print_floating (value
, builtin_type_long_double
, gdb_stdout
);
1854 #if 0 /* FIXME: gdb doesn't handle long doubles */
1855 /* Print upper fp regs as long double if appropriate. */
1856 if (regno
>= FP0_REGNUM
+ 32 && regno
< FP_MAX_REGNUM
1857 /* We test for even numbered regs and not a multiple of 4 because
1858 the upper fp regs are recorded as doubles. */
1859 && (regno
& 1) == 0)
1863 if (frame_register_read (selected_frame
, regno
, value
)
1864 && frame_register_read (selected_frame
, regno
+ 1, value
+ 8))
1866 printf_unfiltered ("\t");
1867 print_floating (value
, builtin_type_long_double
, gdb_stdout
);
1873 /* FIXME: Some of these are priviledged registers.
1874 Not sure how they should be handled. */
1876 #define BITS(n, mask) ((int) (((val) >> (n)) & (mask)))
1878 val
= read_register (regno
);
1881 if (GDB_TARGET_IS_SPARC64
)
1885 printf_unfiltered ("\t");
1886 dump_ccreg ("xcc", val
>> 4);
1887 printf_unfiltered (", ");
1888 dump_ccreg ("icc", val
& 15);
1891 printf ("\tfef:%d, du:%d, dl:%d",
1892 BITS (2, 1), BITS (1, 1), BITS (0, 1));
1896 static char *fcc
[4] =
1897 {"=", "<", ">", "?"};
1898 static char *rd
[4] =
1899 {"N", "0", "+", "-"};
1900 /* Long, but I'd rather leave it as is and use a wide screen. */
1901 printf_filtered ("\t0:%s, 1:%s, 2:%s, 3:%s, rd:%s, tem:%d, ",
1902 fcc
[BITS (10, 3)], fcc
[BITS (32, 3)],
1903 fcc
[BITS (34, 3)], fcc
[BITS (36, 3)],
1904 rd
[BITS (30, 3)], BITS (23, 31));
1905 printf_filtered ("ns:%d, ver:%d, ftt:%d, qne:%d, aexc:%d, cexc:%d",
1906 BITS (22, 1), BITS (17, 7), BITS (14, 7),
1907 BITS (13, 1), BITS (5, 31), BITS (0, 31));
1912 char *asi
= decode_asi (val
);
1914 printf ("\t%s", asi
);
1918 printf ("\tmanuf:%d, impl:%d, mask:%d, maxtl:%d, maxwin:%d",
1919 BITS (48, 0xffff), BITS (32, 0xffff),
1920 BITS (24, 0xff), BITS (8, 0xff), BITS (0, 31));
1924 static char *mm
[4] =
1925 {"tso", "pso", "rso", "?"};
1926 printf_filtered ("\tcle:%d, tle:%d, mm:%s, red:%d, ",
1927 BITS (9, 1), BITS (8, 1),
1928 mm
[BITS (6, 3)], BITS (5, 1));
1929 printf_filtered ("pef:%d, am:%d, priv:%d, ie:%d, ag:%d",
1930 BITS (4, 1), BITS (3, 1), BITS (2, 1),
1931 BITS (1, 1), BITS (0, 1));
1935 /* FIXME: print all 4? */
1938 /* FIXME: print all 4? */
1941 /* FIXME: print all 4? */
1944 /* FIXME: print all 4? */
1947 printf ("\tother:%d, normal:%d", BITS (3, 7), BITS (0, 7));
1950 printf ("\t%d", BITS (0, 31));
1952 case CANSAVE_REGNUM
:
1953 printf ("\t%-2d before spill", BITS (0, 31));
1955 case CANRESTORE_REGNUM
:
1956 printf ("\t%-2d before fill", BITS (0, 31));
1958 case CLEANWIN_REGNUM
:
1959 printf ("\t%-2d before clean", BITS (0, 31));
1961 case OTHERWIN_REGNUM
:
1962 printf ("\t%d", BITS (0, 31));
1969 printf ("\ticc:%c%c%c%c, pil:%d, s:%d, ps:%d, et:%d, cwp:%d",
1970 BITS (23, 1) ? 'N' : '-', BITS (22, 1) ? 'Z' : '-',
1971 BITS (21, 1) ? 'V' : '-', BITS (20, 1) ? 'C' : '-',
1972 BITS (8, 15), BITS (7, 1), BITS (6, 1), BITS (5, 1),
1977 static char *fcc
[4] =
1978 {"=", "<", ">", "?"};
1979 static char *rd
[4] =
1980 {"N", "0", "+", "-"};
1981 /* Long, but I'd rather leave it as is and use a wide screen. */
1982 printf ("\trd:%s, tem:%d, ns:%d, ver:%d, ftt:%d, qne:%d, "
1983 "fcc:%s, aexc:%d, cexc:%d",
1984 rd
[BITS (30, 3)], BITS (23, 31), BITS (22, 1), BITS (17, 7),
1985 BITS (14, 7), BITS (13, 1), fcc
[BITS (10, 3)], BITS (5, 31),
1995 gdb_print_insn_sparc (bfd_vma memaddr
, disassemble_info
*info
)
1997 /* It's necessary to override mach again because print_insn messes it up. */
1998 info
->mach
= TARGET_ARCHITECTURE
->mach
;
1999 return print_insn_sparc (memaddr
, info
);
2002 /* The SPARC passes the arguments on the stack; arguments smaller
2003 than an int are promoted to an int. The first 6 words worth of
2004 args are also passed in registers o0 - o5. */
2007 sparc32_push_arguments (int nargs
, struct value
**args
, CORE_ADDR sp
,
2008 int struct_return
, CORE_ADDR struct_addr
)
2011 int accumulate_size
= 0;
2018 struct sparc_arg
*sparc_args
=
2019 (struct sparc_arg
*) alloca (nargs
* sizeof (struct sparc_arg
));
2020 struct sparc_arg
*m_arg
;
2022 /* Promote arguments if necessary, and calculate their stack offsets
2024 for (i
= 0, m_arg
= sparc_args
; i
< nargs
; i
++, m_arg
++)
2026 struct value
*arg
= args
[i
];
2027 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2028 /* Cast argument to long if necessary as the compiler does it too. */
2029 switch (TYPE_CODE (arg_type
))
2032 case TYPE_CODE_BOOL
:
2033 case TYPE_CODE_CHAR
:
2034 case TYPE_CODE_RANGE
:
2035 case TYPE_CODE_ENUM
:
2036 if (TYPE_LENGTH (arg_type
) < TYPE_LENGTH (builtin_type_long
))
2038 arg_type
= builtin_type_long
;
2039 arg
= value_cast (arg_type
, arg
);
2045 m_arg
->len
= TYPE_LENGTH (arg_type
);
2046 m_arg
->offset
= accumulate_size
;
2047 accumulate_size
= (accumulate_size
+ m_arg
->len
+ 3) & ~3;
2048 m_arg
->contents
= VALUE_CONTENTS (arg
);
2051 /* Make room for the arguments on the stack. */
2052 accumulate_size
+= CALL_DUMMY_STACK_ADJUST
;
2053 sp
= ((sp
- accumulate_size
) & ~7) + CALL_DUMMY_STACK_ADJUST
;
2055 /* `Push' arguments on the stack. */
2056 for (i
= 0, oregnum
= 0, m_arg
= sparc_args
;
2060 write_memory (sp
+ m_arg
->offset
, m_arg
->contents
, m_arg
->len
);
2062 j
< m_arg
->len
&& oregnum
< 6;
2063 j
+= SPARC_INTREG_SIZE
, oregnum
++)
2064 write_register_gen (O0_REGNUM
+ oregnum
, m_arg
->contents
+ j
);
2071 /* Extract from an array REGBUF containing the (raw) register state
2072 a function return value of type TYPE, and copy that, in virtual format,
2076 sparc32_extract_return_value (struct type
*type
, char *regbuf
, char *valbuf
)
2078 int typelen
= TYPE_LENGTH (type
);
2079 int regsize
= REGISTER_RAW_SIZE (O0_REGNUM
);
2081 if (TYPE_CODE (type
) == TYPE_CODE_FLT
&& SPARC_HAS_FPU
)
2082 memcpy (valbuf
, ®buf
[REGISTER_BYTE (FP0_REGNUM
)], typelen
);
2085 ®buf
[O0_REGNUM
* regsize
+
2087 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
? 0
2088 : regsize
- typelen
)],
2093 /* Write into appropriate registers a function return value
2094 of type TYPE, given in virtual format. On SPARCs with FPUs,
2095 float values are returned in %f0 (and %f1). In all other cases,
2096 values are returned in register %o0. */
2099 sparc_store_return_value (struct type
*type
, char *valbuf
)
2104 buffer
= alloca (MAX_REGISTER_RAW_SIZE
);
2106 if (TYPE_CODE (type
) == TYPE_CODE_FLT
&& SPARC_HAS_FPU
)
2107 /* Floating-point values are returned in the register pair */
2108 /* formed by %f0 and %f1 (doubles are, anyway). */
2111 /* Other values are returned in register %o0. */
2114 /* Add leading zeros to the value. */
2115 if (TYPE_LENGTH (type
) < REGISTER_RAW_SIZE (regno
))
2117 memset (buffer
, 0, REGISTER_RAW_SIZE (regno
));
2118 memcpy (buffer
+ REGISTER_RAW_SIZE (regno
) - TYPE_LENGTH (type
), valbuf
,
2119 TYPE_LENGTH (type
));
2120 write_register_gen (regno
, buffer
);
2123 write_register_bytes (REGISTER_BYTE (regno
), valbuf
, TYPE_LENGTH (type
));
2127 sparclet_store_return_value (struct type
*type
, char *valbuf
)
2129 /* Other values are returned in register %o0. */
2130 write_register_bytes (REGISTER_BYTE (O0_REGNUM
), valbuf
,
2131 TYPE_LENGTH (type
));
2135 #ifndef CALL_DUMMY_CALL_OFFSET
2136 #define CALL_DUMMY_CALL_OFFSET \
2137 (gdbarch_tdep (current_gdbarch)->call_dummy_call_offset)
2138 #endif /* CALL_DUMMY_CALL_OFFSET */
2140 /* Insert the function address into a call dummy instruction sequence
2143 For structs and unions, if the function was compiled with Sun cc,
2144 it expects 'unimp' after the call. But gcc doesn't use that
2145 (twisted) convention. So leave a nop there for gcc (FIX_CALL_DUMMY
2146 can assume it is operating on a pristine CALL_DUMMY, not one that
2147 has already been customized for a different function). */
2150 sparc_fix_call_dummy (char *dummy
, CORE_ADDR pc
, CORE_ADDR fun
,
2151 struct type
*value_type
, int using_gcc
)
2155 /* Store the relative adddress of the target function into the
2156 'call' instruction. */
2157 store_unsigned_integer (dummy
+ CALL_DUMMY_CALL_OFFSET
, 4,
2159 | (((fun
- (pc
+ CALL_DUMMY_CALL_OFFSET
)) >> 2)
2162 /* If the called function returns an aggregate value, fill in the UNIMP
2163 instruction containing the size of the returned aggregate return value,
2164 which follows the call instruction.
2165 For details see the SPARC Architecture Manual Version 8, Appendix D.3.
2167 Adjust the call_dummy_breakpoint_offset for the bp_call_dummy breakpoint
2168 to the proper address in the call dummy, so that `finish' after a stop
2169 in a call dummy works.
2170 Tweeking current_gdbarch is not an optimal solution, but the call to
2171 sparc_fix_call_dummy is immediately followed by a call to run_stack_dummy,
2172 which is the only function where dummy_breakpoint_offset is actually
2173 used, if it is non-zero. */
2174 if (TYPE_CODE (value_type
) == TYPE_CODE_STRUCT
2175 || TYPE_CODE (value_type
) == TYPE_CODE_UNION
)
2177 store_unsigned_integer (dummy
+ CALL_DUMMY_CALL_OFFSET
+ 8, 4,
2178 TYPE_LENGTH (value_type
) & 0x1fff);
2179 set_gdbarch_call_dummy_breakpoint_offset (current_gdbarch
, 0x30);
2182 set_gdbarch_call_dummy_breakpoint_offset (current_gdbarch
, 0x2c);
2184 if (!(GDB_TARGET_IS_SPARC64
))
2186 /* If this is not a simulator target, change the first four
2187 instructions of the call dummy to NOPs. Those instructions
2188 include a 'save' instruction and are designed to work around
2189 problems with register window flushing in the simulator. */
2191 if (strcmp (target_shortname
, "sim") != 0)
2193 for (i
= 0; i
< 4; i
++)
2194 store_unsigned_integer (dummy
+ (i
* 4), 4, 0x01000000);
2198 /* If this is a bi-endian target, GDB has written the call dummy
2199 in little-endian order. We must byte-swap it back to big-endian. */
2202 for (i
= 0; i
< CALL_DUMMY_LENGTH
; i
+= 4)
2204 char tmp
= dummy
[i
];
2205 dummy
[i
] = dummy
[i
+ 3];
2208 dummy
[i
+ 1] = dummy
[i
+ 2];
2215 /* Set target byte order based on machine type. */
2218 sparc_target_architecture_hook (const bfd_arch_info_type
*ap
)
2222 if (ap
->mach
== bfd_mach_sparc_sparclite_le
)
2224 target_byte_order
= BFD_ENDIAN_LITTLE
;
2234 * Module "constructor" function.
2237 static struct gdbarch
* sparc_gdbarch_init (struct gdbarch_info info
,
2238 struct gdbarch_list
*arches
);
2241 _initialize_sparc_tdep (void)
2243 /* Hook us into the gdbarch mechanism. */
2244 register_gdbarch_init (bfd_arch_sparc
, sparc_gdbarch_init
);
2246 tm_print_insn
= gdb_print_insn_sparc
;
2247 tm_print_insn_info
.mach
= TM_PRINT_INSN_MACH
; /* Selects sparc/sparclite */
2248 target_architecture_hook
= sparc_target_architecture_hook
;
2251 /* Compensate for stack bias. Note that we currently don't handle
2252 mixed 32/64 bit code. */
2255 sparc64_read_sp (void)
2257 CORE_ADDR sp
= read_register (SP_REGNUM
);
2265 sparc64_read_fp (void)
2267 CORE_ADDR fp
= read_register (FP_REGNUM
);
2275 sparc64_write_sp (CORE_ADDR val
)
2277 CORE_ADDR oldsp
= read_register (SP_REGNUM
);
2279 write_register (SP_REGNUM
, val
- 2047);
2281 write_register (SP_REGNUM
, val
);
2284 /* The SPARC 64 ABI passes floating-point arguments in FP0 to FP31,
2285 and all other arguments in O0 to O5. They are also copied onto
2286 the stack in the correct places. Apparently (empirically),
2287 structs of less than 16 bytes are passed member-by-member in
2288 separate registers, but I am unable to figure out the algorithm.
2289 Some members go in floating point regs, but I don't know which.
2291 FIXME: Handle small structs (less than 16 bytes containing floats).
2293 The counting regimen for using both integer and FP registers
2294 for argument passing is rather odd -- a single counter is used
2295 for both; this means that if the arguments alternate between
2296 int and float, we will waste every other register of both types. */
2299 sparc64_push_arguments (int nargs
, struct value
**args
, CORE_ADDR sp
,
2300 int struct_return
, CORE_ADDR struct_retaddr
)
2302 int i
, j
, register_counter
= 0;
2304 struct type
*sparc_intreg_type
=
2305 TYPE_LENGTH (builtin_type_long
) == SPARC_INTREG_SIZE
?
2306 builtin_type_long
: builtin_type_long_long
;
2308 sp
= (sp
& ~(((unsigned long) SPARC_INTREG_SIZE
) - 1UL));
2310 /* Figure out how much space we'll need. */
2311 for (i
= nargs
- 1; i
>= 0; i
--)
2313 int len
= TYPE_LENGTH (check_typedef (VALUE_TYPE (args
[i
])));
2314 struct value
*copyarg
= args
[i
];
2317 if (copylen
< SPARC_INTREG_SIZE
)
2319 copyarg
= value_cast (sparc_intreg_type
, copyarg
);
2320 copylen
= SPARC_INTREG_SIZE
;
2329 /* if STRUCT_RETURN, then first argument is the struct return location. */
2331 write_register (O0_REGNUM
+ register_counter
++, struct_retaddr
);
2333 /* Now write the arguments onto the stack, while writing FP
2334 arguments into the FP registers, and other arguments into the
2335 first six 'O' registers. */
2337 for (i
= 0; i
< nargs
; i
++)
2339 int len
= TYPE_LENGTH (check_typedef (VALUE_TYPE (args
[i
])));
2340 struct value
*copyarg
= args
[i
];
2341 enum type_code typecode
= TYPE_CODE (VALUE_TYPE (args
[i
]));
2344 if (typecode
== TYPE_CODE_INT
||
2345 typecode
== TYPE_CODE_BOOL
||
2346 typecode
== TYPE_CODE_CHAR
||
2347 typecode
== TYPE_CODE_RANGE
||
2348 typecode
== TYPE_CODE_ENUM
)
2349 if (len
< SPARC_INTREG_SIZE
)
2351 /* Small ints will all take up the size of one intreg on
2353 copyarg
= value_cast (sparc_intreg_type
, copyarg
);
2354 copylen
= SPARC_INTREG_SIZE
;
2357 write_memory (tempsp
, VALUE_CONTENTS (copyarg
), copylen
);
2360 /* Corner case: Structs consisting of a single float member are floats.
2361 * FIXME! I don't know about structs containing multiple floats!
2362 * Structs containing mixed floats and ints are even more weird.
2367 /* Separate float args from all other args. */
2368 if (typecode
== TYPE_CODE_FLT
&& SPARC_HAS_FPU
)
2370 if (register_counter
< 16)
2372 /* This arg gets copied into a FP register. */
2376 case 4: /* Single-precision (float) */
2377 fpreg
= FP0_REGNUM
+ 2 * register_counter
+ 1;
2378 register_counter
+= 1;
2380 case 8: /* Double-precision (double) */
2381 fpreg
= FP0_REGNUM
+ 2 * register_counter
;
2382 register_counter
+= 1;
2384 case 16: /* Quad-precision (long double) */
2385 fpreg
= FP0_REGNUM
+ 2 * register_counter
;
2386 register_counter
+= 2;
2389 internal_error (__FILE__
, __LINE__
, "bad switch");
2391 write_register_bytes (REGISTER_BYTE (fpreg
),
2392 VALUE_CONTENTS (args
[i
]),
2396 else /* all other args go into the first six 'o' registers */
2399 j
< len
&& register_counter
< 6;
2400 j
+= SPARC_INTREG_SIZE
)
2402 int oreg
= O0_REGNUM
+ register_counter
;
2404 write_register_gen (oreg
, VALUE_CONTENTS (copyarg
) + j
);
2405 register_counter
+= 1;
2412 /* Values <= 32 bytes are returned in o0-o3 (floating-point values are
2413 returned in f0-f3). */
2416 sp64_extract_return_value (struct type
*type
, char *regbuf
, char *valbuf
,
2419 int typelen
= TYPE_LENGTH (type
);
2420 int regsize
= REGISTER_RAW_SIZE (O0_REGNUM
);
2422 if (TYPE_CODE (type
) == TYPE_CODE_FLT
&& SPARC_HAS_FPU
)
2424 memcpy (valbuf
, ®buf
[REGISTER_BYTE (FP0_REGNUM
)], typelen
);
2428 if (TYPE_CODE (type
) != TYPE_CODE_STRUCT
2429 || (TYPE_LENGTH (type
) > 32))
2432 ®buf
[O0_REGNUM
* regsize
+
2433 (typelen
>= regsize
? 0 : regsize
- typelen
)],
2439 char *o0
= ®buf
[O0_REGNUM
* regsize
];
2440 char *f0
= ®buf
[FP0_REGNUM
* regsize
];
2443 for (x
= 0; x
< TYPE_NFIELDS (type
); x
++)
2445 struct field
*f
= &TYPE_FIELDS (type
)[x
];
2446 /* FIXME: We may need to handle static fields here. */
2447 int whichreg
= (f
->loc
.bitpos
+ bitoffset
) / 32;
2448 int remainder
= ((f
->loc
.bitpos
+ bitoffset
) % 32) / 8;
2449 int where
= (f
->loc
.bitpos
+ bitoffset
) / 8;
2450 int size
= TYPE_LENGTH (f
->type
);
2451 int typecode
= TYPE_CODE (f
->type
);
2453 if (typecode
== TYPE_CODE_STRUCT
)
2455 sp64_extract_return_value (f
->type
,
2458 bitoffset
+ f
->loc
.bitpos
);
2460 else if (typecode
== TYPE_CODE_FLT
&& SPARC_HAS_FPU
)
2462 memcpy (valbuf
+ where
, &f0
[whichreg
* 4] + remainder
, size
);
2466 memcpy (valbuf
+ where
, &o0
[whichreg
* 4] + remainder
, size
);
2473 sparc64_extract_return_value (struct type
*type
, char *regbuf
, char *valbuf
)
2475 sp64_extract_return_value (type
, regbuf
, valbuf
, 0);
2479 sparclet_extract_return_value (struct type
*type
,
2483 regbuf
+= REGISTER_RAW_SIZE (O0_REGNUM
) * 8;
2484 if (TYPE_LENGTH (type
) < REGISTER_RAW_SIZE (O0_REGNUM
))
2485 regbuf
+= REGISTER_RAW_SIZE (O0_REGNUM
) - TYPE_LENGTH (type
);
2487 memcpy ((void *) valbuf
, regbuf
, TYPE_LENGTH (type
));
2492 sparc32_stack_align (CORE_ADDR addr
)
2494 return ((addr
+ 7) & -8);
2498 sparc64_stack_align (CORE_ADDR addr
)
2500 return ((addr
+ 15) & -16);
2504 sparc_print_extra_frame_info (struct frame_info
*fi
)
2506 if (fi
&& fi
->extra_info
&& fi
->extra_info
->flat
)
2507 printf_filtered (" flat, pc saved at 0x%s, fp saved at 0x%s\n",
2508 paddr_nz (fi
->extra_info
->pc_addr
),
2509 paddr_nz (fi
->extra_info
->fp_addr
));
2512 /* MULTI_ARCH support */
2515 sparc32_register_name (int regno
)
2517 static char *register_names
[] =
2518 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
2519 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
2520 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
2521 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
2523 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
2524 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
2525 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
2526 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
2528 "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr"
2532 regno
>= (sizeof (register_names
) / sizeof (register_names
[0])))
2535 return register_names
[regno
];
2539 sparc64_register_name (int regno
)
2541 static char *register_names
[] =
2542 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
2543 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
2544 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
2545 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
2547 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
2548 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
2549 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
2550 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
2551 "f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46",
2552 "f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62",
2554 "pc", "npc", "ccr", "fsr", "fprs", "y", "asi", "ver",
2555 "tick", "pil", "pstate", "tstate", "tba", "tl", "tt", "tpc",
2556 "tnpc", "wstate", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
2557 "asr16", "asr17", "asr18", "asr19", "asr20", "asr21", "asr22", "asr23",
2558 "asr24", "asr25", "asr26", "asr27", "asr28", "asr29", "asr30", "asr31",
2559 /* These are here at the end to simplify removing them if we have to. */
2560 "icc", "xcc", "fcc0", "fcc1", "fcc2", "fcc3"
2564 regno
>= (sizeof (register_names
) / sizeof (register_names
[0])))
2567 return register_names
[regno
];
2571 sparclite_register_name (int regno
)
2573 static char *register_names
[] =
2574 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
2575 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
2576 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
2577 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
2579 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
2580 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
2581 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
2582 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
2584 "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr",
2585 "dia1", "dia2", "dda1", "dda2", "ddv1", "ddv2", "dcr", "dsr"
2589 regno
>= (sizeof (register_names
) / sizeof (register_names
[0])))
2592 return register_names
[regno
];
2596 sparclet_register_name (int regno
)
2598 static char *register_names
[] =
2599 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
2600 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
2601 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
2602 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
2604 "", "", "", "", "", "", "", "", /* no floating point registers */
2605 "", "", "", "", "", "", "", "",
2606 "", "", "", "", "", "", "", "",
2607 "", "", "", "", "", "", "", "",
2609 "y", "psr", "wim", "tbr", "pc", "npc", "", "", /* no FPSR or CPSR */
2610 "ccsr", "ccpr", "cccrcr", "ccor", "ccobr", "ccibr", "ccir", "",
2612 /* ASR15 ASR19 (don't display them) */
2613 "asr1", "", "asr17", "asr18", "", "asr20", "asr21", "asr22"
2614 /* None of the rest get displayed */
2616 "awr0", "awr1", "awr2", "awr3", "awr4", "awr5", "awr6", "awr7",
2617 "awr8", "awr9", "awr10", "awr11", "awr12", "awr13", "awr14", "awr15",
2618 "awr16", "awr17", "awr18", "awr19", "awr20", "awr21", "awr22", "awr23",
2619 "awr24", "awr25", "awr26", "awr27", "awr28", "awr29", "awr30", "awr31",
2625 regno
>= (sizeof (register_names
) / sizeof (register_names
[0])))
2628 return register_names
[regno
];
2632 sparc_push_return_address (CORE_ADDR pc_unused
, CORE_ADDR sp
)
2634 if (CALL_DUMMY_LOCATION
== AT_ENTRY_POINT
)
2636 /* The return PC of the dummy_frame is the former 'current' PC
2637 (where we were before we made the target function call).
2638 This is saved in %i7 by push_dummy_frame.
2640 We will save the 'call dummy location' (ie. the address
2641 to which the target function will return) in %o7.
2642 This address will actually be the program's entry point.
2643 There will be a special call_dummy breakpoint there. */
2645 write_register (O7_REGNUM
,
2646 CALL_DUMMY_ADDRESS () - 8);
2652 /* Should call_function allocate stack space for a struct return? */
2655 sparc64_use_struct_convention (int gcc_p
, struct type
*type
)
2657 return (TYPE_LENGTH (type
) > 32);
2660 /* Store the address of the place in which to copy the structure the
2661 subroutine will return. This is called from call_function_by_hand.
2662 The ultimate mystery is, tho, what is the value "16"?
2664 MVS: That's the offset from where the sp is now, to where the
2665 subroutine is gonna expect to find the struct return address. */
2668 sparc32_store_struct_return (CORE_ADDR addr
, CORE_ADDR sp
)
2673 val
= alloca (SPARC_INTREG_SIZE
);
2674 store_unsigned_integer (val
, SPARC_INTREG_SIZE
, addr
);
2675 write_memory (sp
+ (16 * SPARC_INTREG_SIZE
), val
, SPARC_INTREG_SIZE
);
2677 if (CALL_DUMMY_LOCATION
== AT_ENTRY_POINT
)
2679 /* Now adjust the value of the link register, which was previously
2680 stored by push_return_address. Functions that return structs are
2681 peculiar in that they return to link register + 12, rather than
2682 link register + 8. */
2684 o7
= read_register (O7_REGNUM
);
2685 write_register (O7_REGNUM
, o7
- 4);
2690 sparc64_store_struct_return (CORE_ADDR addr
, CORE_ADDR sp
)
2692 /* FIXME: V9 uses %o0 for this. */
2693 /* FIXME MVS: Only for small enough structs!!! */
2695 target_write_memory (sp
+ (16 * SPARC_INTREG_SIZE
),
2696 (char *) &addr
, SPARC_INTREG_SIZE
);
2698 if (CALL_DUMMY_LOCATION
== AT_ENTRY_POINT
)
2700 /* Now adjust the value of the link register, which was previously
2701 stored by push_return_address. Functions that return structs are
2702 peculiar in that they return to link register + 12, rather than
2703 link register + 8. */
2705 write_register (O7_REGNUM
, read_register (O7_REGNUM
) - 4);
2710 /* Default target data type for register REGNO. */
2712 static struct type
*
2713 sparc32_register_virtual_type (int regno
)
2715 if (regno
== PC_REGNUM
||
2716 regno
== FP_REGNUM
||
2718 return builtin_type_unsigned_int
;
2720 return builtin_type_int
;
2722 return builtin_type_float
;
2723 return builtin_type_int
;
2726 static struct type
*
2727 sparc64_register_virtual_type (int regno
)
2729 if (regno
== PC_REGNUM
||
2730 regno
== FP_REGNUM
||
2732 return builtin_type_unsigned_long_long
;
2734 return builtin_type_long_long
;
2736 return builtin_type_float
;
2738 return builtin_type_double
;
2739 return builtin_type_long_long
;
2742 /* Number of bytes of storage in the actual machine representation for
2746 sparc32_register_size (int regno
)
2752 sparc64_register_size (int regno
)
2754 return (regno
< 32 ? 8 : regno
< 64 ? 4 : 8);
2757 /* Index within the `registers' buffer of the first byte of the space
2758 for register REGNO. */
2761 sparc32_register_byte (int regno
)
2767 sparc64_register_byte (int regno
)
2771 else if (regno
< 64)
2772 return 32 * 8 + (regno
- 32) * 4;
2773 else if (regno
< 80)
2774 return 32 * 8 + 32 * 4 + (regno
- 64) * 8;
2776 return 64 * 8 + (regno
- 80) * 8;
2779 /* Advance PC across any function entry prologue instructions to reach
2780 some "real" code. SKIP_PROLOGUE_FRAMELESS_P advances the PC past
2781 some of the prologue, but stops as soon as it knows that the
2782 function has a frame. Its result is equal to its input PC if the
2783 function is frameless, unequal otherwise. */
2786 sparc_gdbarch_skip_prologue (CORE_ADDR ip
)
2788 return examine_prologue (ip
, 0, NULL
, NULL
);
2791 /* Immediately after a function call, return the saved pc.
2792 Can't go through the frames for this because on some machines
2793 the new frame is not set up until the new function executes
2794 some instructions. */
2797 sparc_saved_pc_after_call (struct frame_info
*fi
)
2799 return sparc_pc_adjust (read_register (RP_REGNUM
));
2802 /* Convert registers between 'raw' and 'virtual' formats.
2803 They are the same on sparc, so there's nothing to do. */
2806 sparc_convert_to_virtual (int regnum
, struct type
*type
, char *from
, char *to
)
2807 { /* do nothing (should never be called) */
2811 sparc_convert_to_raw (struct type
*type
, int regnum
, char *from
, char *to
)
2812 { /* do nothing (should never be called) */
2815 /* Init saved regs: nothing to do, just a place-holder function. */
2818 sparc_frame_init_saved_regs (struct frame_info
*fi_ignored
)
2822 /* gdbarch fix call dummy:
2823 All this function does is rearrange the arguments before calling
2824 sparc_fix_call_dummy (which does the real work). */
2827 sparc_gdbarch_fix_call_dummy (char *dummy
,
2831 struct value
**args
,
2835 if (CALL_DUMMY_LOCATION
== ON_STACK
)
2836 sparc_fix_call_dummy (dummy
, pc
, fun
, type
, gcc_p
);
2839 /* Coerce float to double: a no-op. */
2842 sparc_coerce_float_to_double (struct type
*formal
, struct type
*actual
)
2847 /* CALL_DUMMY_ADDRESS: fetch the breakpoint address for a call dummy. */
2850 sparc_call_dummy_address (void)
2852 return (CALL_DUMMY_START_OFFSET
) + CALL_DUMMY_BREAKPOINT_OFFSET
;
2855 /* Supply the Y register number to those that need it. */
2858 sparc_y_regnum (void)
2860 return gdbarch_tdep (current_gdbarch
)->y_regnum
;
2864 sparc_reg_struct_has_addr (int gcc_p
, struct type
*type
)
2866 if (GDB_TARGET_IS_SPARC64
)
2867 return (TYPE_LENGTH (type
) > 32);
2869 return (gcc_p
!= 1);
2873 sparc_intreg_size (void)
2875 return SPARC_INTREG_SIZE
;
2879 sparc_return_value_on_stack (struct type
*type
)
2881 if (TYPE_CODE (type
) == TYPE_CODE_FLT
&&
2882 TYPE_LENGTH (type
) > 8)
2889 * Gdbarch "constructor" function.
2892 #define SPARC32_CALL_DUMMY_ON_STACK
2894 #define SPARC_SP_REGNUM 14
2895 #define SPARC_FP_REGNUM 30
2896 #define SPARC_FP0_REGNUM 32
2897 #define SPARC32_NPC_REGNUM 69
2898 #define SPARC32_PC_REGNUM 68
2899 #define SPARC32_Y_REGNUM 64
2900 #define SPARC64_PC_REGNUM 80
2901 #define SPARC64_NPC_REGNUM 81
2902 #define SPARC64_Y_REGNUM 85
2904 static struct gdbarch
*
2905 sparc_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2907 struct gdbarch
*gdbarch
;
2908 struct gdbarch_tdep
*tdep
;
2910 static LONGEST call_dummy_32
[] =
2911 { 0xbc100001, 0x9de38000, 0xbc100002, 0xbe100003,
2912 0xda03a058, 0xd803a054, 0xd603a050, 0xd403a04c,
2913 0xd203a048, 0x40000000, 0xd003a044, 0x01000000,
2914 0x91d02001, 0x01000000
2916 static LONGEST call_dummy_64
[] =
2917 { 0x9de3bec0fd3fa7f7LL
, 0xf93fa7eff53fa7e7LL
,
2918 0xf13fa7dfed3fa7d7LL
, 0xe93fa7cfe53fa7c7LL
,
2919 0xe13fa7bfdd3fa7b7LL
, 0xd93fa7afd53fa7a7LL
,
2920 0xd13fa79fcd3fa797LL
, 0xc93fa78fc53fa787LL
,
2921 0xc13fa77fcc3fa777LL
, 0xc83fa76fc43fa767LL
,
2922 0xc03fa75ffc3fa757LL
, 0xf83fa74ff43fa747LL
,
2923 0xf03fa73f01000000LL
, 0x0100000001000000LL
,
2924 0x0100000091580000LL
, 0xd027a72b93500000LL
,
2925 0xd027a72791480000LL
, 0xd027a72391400000LL
,
2926 0xd027a71fda5ba8a7LL
, 0xd85ba89fd65ba897LL
,
2927 0xd45ba88fd25ba887LL
, 0x9fc02000d05ba87fLL
,
2928 0x0100000091d02001LL
, 0x0100000001000000LL
2930 static LONGEST call_dummy_nil
[] = {0};
2932 /* First see if there is already a gdbarch that can satisfy the request. */
2933 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2935 return arches
->gdbarch
;
2937 /* None found: is the request for a sparc architecture? */
2938 if (info
.bfd_arch_info
->arch
!= bfd_arch_sparc
)
2939 return NULL
; /* No; then it's not for us. */
2941 /* Yes: create a new gdbarch for the specified machine type. */
2942 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
2943 gdbarch
= gdbarch_alloc (&info
, tdep
);
2945 /* First set settings that are common for all sparc architectures. */
2946 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
2947 set_gdbarch_breakpoint_from_pc (gdbarch
, memory_breakpoint_from_pc
);
2948 set_gdbarch_coerce_float_to_double (gdbarch
,
2949 sparc_coerce_float_to_double
);
2950 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1);
2951 set_gdbarch_call_dummy_p (gdbarch
, 1);
2952 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 1);
2953 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
2954 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2955 set_gdbarch_extract_struct_value_address (gdbarch
,
2956 sparc_extract_struct_value_address
);
2957 set_gdbarch_fix_call_dummy (gdbarch
, sparc_gdbarch_fix_call_dummy
);
2958 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2959 set_gdbarch_fp_regnum (gdbarch
, SPARC_FP_REGNUM
);
2960 set_gdbarch_fp0_regnum (gdbarch
, SPARC_FP0_REGNUM
);
2961 set_gdbarch_frame_args_address (gdbarch
, default_frame_address
);
2962 set_gdbarch_frame_chain (gdbarch
, sparc_frame_chain
);
2963 set_gdbarch_frame_init_saved_regs (gdbarch
, sparc_frame_init_saved_regs
);
2964 set_gdbarch_frame_locals_address (gdbarch
, default_frame_address
);
2965 set_gdbarch_frame_num_args (gdbarch
, frame_num_args_unknown
);
2966 set_gdbarch_frame_saved_pc (gdbarch
, sparc_frame_saved_pc
);
2967 set_gdbarch_frameless_function_invocation (gdbarch
,
2968 frameless_look_for_prologue
);
2969 set_gdbarch_get_saved_register (gdbarch
, sparc_get_saved_register
);
2970 set_gdbarch_init_extra_frame_info (gdbarch
, sparc_init_extra_frame_info
);
2971 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2972 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2973 set_gdbarch_long_double_bit (gdbarch
, 16 * TARGET_CHAR_BIT
);
2974 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2975 set_gdbarch_max_register_raw_size (gdbarch
, 8);
2976 set_gdbarch_max_register_virtual_size (gdbarch
, 8);
2977 set_gdbarch_pop_frame (gdbarch
, sparc_pop_frame
);
2978 set_gdbarch_push_return_address (gdbarch
, sparc_push_return_address
);
2979 set_gdbarch_push_dummy_frame (gdbarch
, sparc_push_dummy_frame
);
2980 set_gdbarch_read_pc (gdbarch
, generic_target_read_pc
);
2981 set_gdbarch_register_convert_to_raw (gdbarch
, sparc_convert_to_raw
);
2982 set_gdbarch_register_convert_to_virtual (gdbarch
,
2983 sparc_convert_to_virtual
);
2984 set_gdbarch_register_convertible (gdbarch
,
2985 generic_register_convertible_not
);
2986 set_gdbarch_reg_struct_has_addr (gdbarch
, sparc_reg_struct_has_addr
);
2987 set_gdbarch_return_value_on_stack (gdbarch
, sparc_return_value_on_stack
);
2988 set_gdbarch_saved_pc_after_call (gdbarch
, sparc_saved_pc_after_call
);
2989 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
2990 set_gdbarch_skip_prologue (gdbarch
, sparc_gdbarch_skip_prologue
);
2991 set_gdbarch_sp_regnum (gdbarch
, SPARC_SP_REGNUM
);
2992 set_gdbarch_use_generic_dummy_frames (gdbarch
, 0);
2993 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
2996 * Settings that depend only on 32/64 bit word size
2999 switch (info
.bfd_arch_info
->mach
)
3001 case bfd_mach_sparc
:
3002 case bfd_mach_sparc_sparclet
:
3003 case bfd_mach_sparc_sparclite
:
3004 case bfd_mach_sparc_v8plus
:
3005 case bfd_mach_sparc_v8plusa
:
3006 case bfd_mach_sparc_sparclite_le
:
3007 /* 32-bit machine types: */
3009 #ifdef SPARC32_CALL_DUMMY_ON_STACK
3010 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_on_stack
);
3011 set_gdbarch_call_dummy_address (gdbarch
, sparc_call_dummy_address
);
3012 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0x30);
3013 set_gdbarch_call_dummy_length (gdbarch
, 0x38);
3014 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
3015 set_gdbarch_call_dummy_words (gdbarch
, call_dummy_32
);
3017 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_at_entry_point
);
3018 set_gdbarch_call_dummy_address (gdbarch
, entry_point_address
);
3019 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
3020 set_gdbarch_call_dummy_length (gdbarch
, 0);
3021 set_gdbarch_call_dummy_location (gdbarch
, AT_ENTRY_POINT
);
3022 set_gdbarch_call_dummy_words (gdbarch
, call_dummy_nil
);
3024 set_gdbarch_call_dummy_stack_adjust (gdbarch
, 68);
3025 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
3026 set_gdbarch_frame_args_skip (gdbarch
, 68);
3027 set_gdbarch_function_start_offset (gdbarch
, 0);
3028 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
3029 set_gdbarch_npc_regnum (gdbarch
, SPARC32_NPC_REGNUM
);
3030 set_gdbarch_pc_regnum (gdbarch
, SPARC32_PC_REGNUM
);
3031 set_gdbarch_ptr_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
3032 set_gdbarch_push_arguments (gdbarch
, sparc32_push_arguments
);
3033 set_gdbarch_read_fp (gdbarch
, generic_target_read_fp
);
3034 set_gdbarch_read_sp (gdbarch
, generic_target_read_sp
);
3036 set_gdbarch_register_byte (gdbarch
, sparc32_register_byte
);
3037 set_gdbarch_register_raw_size (gdbarch
, sparc32_register_size
);
3038 set_gdbarch_register_size (gdbarch
, 4);
3039 set_gdbarch_register_virtual_size (gdbarch
, sparc32_register_size
);
3040 set_gdbarch_register_virtual_type (gdbarch
,
3041 sparc32_register_virtual_type
);
3042 #ifdef SPARC32_CALL_DUMMY_ON_STACK
3043 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (call_dummy_32
));
3045 set_gdbarch_sizeof_call_dummy_words (gdbarch
, 0);
3047 set_gdbarch_stack_align (gdbarch
, sparc32_stack_align
);
3048 set_gdbarch_store_struct_return (gdbarch
, sparc32_store_struct_return
);
3049 set_gdbarch_use_struct_convention (gdbarch
,
3050 generic_use_struct_convention
);
3051 set_gdbarch_write_sp (gdbarch
, generic_target_write_sp
);
3052 tdep
->y_regnum
= SPARC32_Y_REGNUM
;
3053 tdep
->fp_max_regnum
= SPARC_FP0_REGNUM
+ 32;
3054 tdep
->intreg_size
= 4;
3055 tdep
->reg_save_offset
= 0x60;
3056 tdep
->call_dummy_call_offset
= 0x24;
3059 case bfd_mach_sparc_v9
:
3060 case bfd_mach_sparc_v9a
:
3061 /* 64-bit machine types: */
3062 default: /* Any new machine type is likely to be 64-bit. */
3064 #ifdef SPARC64_CALL_DUMMY_ON_STACK
3065 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_on_stack
);
3066 set_gdbarch_call_dummy_address (gdbarch
, sparc_call_dummy_address
);
3067 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 8 * 4);
3068 set_gdbarch_call_dummy_length (gdbarch
, 192);
3069 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
3070 set_gdbarch_call_dummy_start_offset (gdbarch
, 148);
3071 set_gdbarch_call_dummy_words (gdbarch
, call_dummy_64
);
3073 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_at_entry_point
);
3074 set_gdbarch_call_dummy_address (gdbarch
, entry_point_address
);
3075 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
3076 set_gdbarch_call_dummy_length (gdbarch
, 0);
3077 set_gdbarch_call_dummy_location (gdbarch
, AT_ENTRY_POINT
);
3078 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
3079 set_gdbarch_call_dummy_words (gdbarch
, call_dummy_nil
);
3081 set_gdbarch_call_dummy_stack_adjust (gdbarch
, 128);
3082 set_gdbarch_frame_args_skip (gdbarch
, 136);
3083 set_gdbarch_function_start_offset (gdbarch
, 0);
3084 set_gdbarch_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
3085 set_gdbarch_npc_regnum (gdbarch
, SPARC64_NPC_REGNUM
);
3086 set_gdbarch_pc_regnum (gdbarch
, SPARC64_PC_REGNUM
);
3087 set_gdbarch_ptr_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
3088 set_gdbarch_push_arguments (gdbarch
, sparc64_push_arguments
);
3089 /* NOTE different for at_entry */
3090 set_gdbarch_read_fp (gdbarch
, sparc64_read_fp
);
3091 set_gdbarch_read_sp (gdbarch
, sparc64_read_sp
);
3092 /* Some of the registers aren't 64 bits, but it's a lot simpler just
3093 to assume they all are (since most of them are). */
3094 set_gdbarch_register_byte (gdbarch
, sparc64_register_byte
);
3095 set_gdbarch_register_raw_size (gdbarch
, sparc64_register_size
);
3096 set_gdbarch_register_size (gdbarch
, 8);
3097 set_gdbarch_register_virtual_size (gdbarch
, sparc64_register_size
);
3098 set_gdbarch_register_virtual_type (gdbarch
,
3099 sparc64_register_virtual_type
);
3100 #ifdef SPARC64_CALL_DUMMY_ON_STACK
3101 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (call_dummy_64
));
3103 set_gdbarch_sizeof_call_dummy_words (gdbarch
, 0);
3105 set_gdbarch_stack_align (gdbarch
, sparc64_stack_align
);
3106 set_gdbarch_store_struct_return (gdbarch
, sparc64_store_struct_return
);
3107 set_gdbarch_use_struct_convention (gdbarch
,
3108 sparc64_use_struct_convention
);
3109 set_gdbarch_write_sp (gdbarch
, sparc64_write_sp
);
3110 tdep
->y_regnum
= SPARC64_Y_REGNUM
;
3111 tdep
->fp_max_regnum
= SPARC_FP0_REGNUM
+ 48;
3112 tdep
->intreg_size
= 8;
3113 tdep
->reg_save_offset
= 0x90;
3114 tdep
->call_dummy_call_offset
= 148 + 4 * 5;
3119 * Settings that vary per-architecture:
3122 switch (info
.bfd_arch_info
->mach
)
3124 case bfd_mach_sparc
:
3125 set_gdbarch_extract_return_value (gdbarch
, sparc32_extract_return_value
);
3126 set_gdbarch_frame_chain_valid (gdbarch
, file_frame_chain_valid
);
3127 set_gdbarch_num_regs (gdbarch
, 72);
3128 set_gdbarch_register_bytes (gdbarch
, 32*4 + 32*4 + 8*4);
3129 set_gdbarch_register_name (gdbarch
, sparc32_register_name
);
3130 set_gdbarch_store_return_value (gdbarch
, sparc_store_return_value
);
3131 tdep
->has_fpu
= 1; /* (all but sparclet and sparclite) */
3132 tdep
->fp_register_bytes
= 32 * 4;
3133 tdep
->print_insn_mach
= bfd_mach_sparc
;
3135 case bfd_mach_sparc_sparclet
:
3136 set_gdbarch_extract_return_value (gdbarch
,
3137 sparclet_extract_return_value
);
3138 set_gdbarch_frame_chain_valid (gdbarch
, file_frame_chain_valid
);
3139 set_gdbarch_num_regs (gdbarch
, 32 + 32 + 8 + 8 + 8);
3140 set_gdbarch_register_bytes (gdbarch
, 32*4 + 32*4 + 8*4 + 8*4 + 8*4);
3141 set_gdbarch_register_name (gdbarch
, sparclet_register_name
);
3142 set_gdbarch_store_return_value (gdbarch
, sparclet_store_return_value
);
3143 tdep
->has_fpu
= 0; /* (all but sparclet and sparclite) */
3144 tdep
->fp_register_bytes
= 0;
3145 tdep
->print_insn_mach
= bfd_mach_sparc_sparclet
;
3147 case bfd_mach_sparc_sparclite
:
3148 set_gdbarch_extract_return_value (gdbarch
, sparc32_extract_return_value
);
3149 set_gdbarch_frame_chain_valid (gdbarch
, func_frame_chain_valid
);
3150 set_gdbarch_num_regs (gdbarch
, 80);
3151 set_gdbarch_register_bytes (gdbarch
, 32*4 + 32*4 + 8*4 + 8*4);
3152 set_gdbarch_register_name (gdbarch
, sparclite_register_name
);
3153 set_gdbarch_store_return_value (gdbarch
, sparc_store_return_value
);
3154 tdep
->has_fpu
= 0; /* (all but sparclet and sparclite) */
3155 tdep
->fp_register_bytes
= 0;
3156 tdep
->print_insn_mach
= bfd_mach_sparc_sparclite
;
3158 case bfd_mach_sparc_v8plus
:
3159 set_gdbarch_extract_return_value (gdbarch
, sparc32_extract_return_value
);
3160 set_gdbarch_frame_chain_valid (gdbarch
, file_frame_chain_valid
);
3161 set_gdbarch_num_regs (gdbarch
, 72);
3162 set_gdbarch_register_bytes (gdbarch
, 32*4 + 32*4 + 8*4);
3163 set_gdbarch_register_name (gdbarch
, sparc32_register_name
);
3164 set_gdbarch_store_return_value (gdbarch
, sparc_store_return_value
);
3165 tdep
->print_insn_mach
= bfd_mach_sparc
;
3166 tdep
->fp_register_bytes
= 32 * 4;
3167 tdep
->has_fpu
= 1; /* (all but sparclet and sparclite) */
3169 case bfd_mach_sparc_v8plusa
:
3170 set_gdbarch_extract_return_value (gdbarch
, sparc32_extract_return_value
);
3171 set_gdbarch_frame_chain_valid (gdbarch
, file_frame_chain_valid
);
3172 set_gdbarch_num_regs (gdbarch
, 72);
3173 set_gdbarch_register_bytes (gdbarch
, 32*4 + 32*4 + 8*4);
3174 set_gdbarch_register_name (gdbarch
, sparc32_register_name
);
3175 set_gdbarch_store_return_value (gdbarch
, sparc_store_return_value
);
3176 tdep
->has_fpu
= 1; /* (all but sparclet and sparclite) */
3177 tdep
->fp_register_bytes
= 32 * 4;
3178 tdep
->print_insn_mach
= bfd_mach_sparc
;
3180 case bfd_mach_sparc_sparclite_le
:
3181 set_gdbarch_extract_return_value (gdbarch
, sparc32_extract_return_value
);
3182 set_gdbarch_frame_chain_valid (gdbarch
, func_frame_chain_valid
);
3183 set_gdbarch_num_regs (gdbarch
, 80);
3184 set_gdbarch_register_bytes (gdbarch
, 32*4 + 32*4 + 8*4 + 8*4);
3185 set_gdbarch_register_name (gdbarch
, sparclite_register_name
);
3186 set_gdbarch_store_return_value (gdbarch
, sparc_store_return_value
);
3187 tdep
->has_fpu
= 0; /* (all but sparclet and sparclite) */
3188 tdep
->fp_register_bytes
= 0;
3189 tdep
->print_insn_mach
= bfd_mach_sparc_sparclite
;
3191 case bfd_mach_sparc_v9
:
3192 set_gdbarch_extract_return_value (gdbarch
, sparc64_extract_return_value
);
3193 set_gdbarch_frame_chain_valid (gdbarch
, file_frame_chain_valid
);
3194 set_gdbarch_num_regs (gdbarch
, 125);
3195 set_gdbarch_register_bytes (gdbarch
, 32*8 + 32*8 + 45*8);
3196 set_gdbarch_register_name (gdbarch
, sparc64_register_name
);
3197 set_gdbarch_store_return_value (gdbarch
, sparc_store_return_value
);
3198 tdep
->has_fpu
= 1; /* (all but sparclet and sparclite) */
3199 tdep
->fp_register_bytes
= 64 * 4;
3200 tdep
->print_insn_mach
= bfd_mach_sparc_v9a
;
3202 case bfd_mach_sparc_v9a
:
3203 set_gdbarch_extract_return_value (gdbarch
, sparc64_extract_return_value
);
3204 set_gdbarch_frame_chain_valid (gdbarch
, file_frame_chain_valid
);
3205 set_gdbarch_num_regs (gdbarch
, 125);
3206 set_gdbarch_register_bytes (gdbarch
, 32*8 + 32*8 + 45*8);
3207 set_gdbarch_register_name (gdbarch
, sparc64_register_name
);
3208 set_gdbarch_store_return_value (gdbarch
, sparc_store_return_value
);
3209 tdep
->has_fpu
= 1; /* (all but sparclet and sparclite) */
3210 tdep
->fp_register_bytes
= 64 * 4;
3211 tdep
->print_insn_mach
= bfd_mach_sparc_v9a
;