1 /* Target-dependent code for SPARC.
3 Copyright (C) 2003-2017 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "arch-utils.h"
24 #include "dwarf2-frame.h"
25 #include "floatformat.h"
27 #include "frame-base.h"
28 #include "frame-unwind.h"
37 #include "target-descriptions.h"
40 #include "sparc-tdep.h"
41 #include "sparc-ravenscar-thread.h"
46 /* This file implements the SPARC 32-bit ABI as defined by the section
47 "Low-Level System Information" of the SPARC Compliance Definition
48 (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC. The SCD
49 lists changes with respect to the original 32-bit psABI as defined
50 in the "System V ABI, SPARC Processor Supplement".
52 Note that if we talk about SunOS, we mean SunOS 4.x, which was
53 BSD-based, which is sometimes (retroactively?) referred to as
54 Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and
55 above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9
56 suffering from severe version number inflation). Solaris 2.x is
57 also known as SunOS 5.x, since that's what uname(1) says. Solaris
60 /* Please use the sparc32_-prefix for 32-bit specific code, the
61 sparc64_-prefix for 64-bit specific code and the sparc_-prefix for
62 code that can handle both. The 64-bit specific code lives in
63 sparc64-tdep.c; don't add any here. */
65 /* The SPARC Floating-Point Quad-Precision format is similar to
66 big-endian IA-64 Quad-Precision format. */
67 #define floatformats_sparc_quad floatformats_ia64_quad
69 /* The stack pointer is offset from the stack frame by a BIAS of 2047
70 (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC
71 hosts, so undefine it first. */
75 /* Macros to extract fields from SPARC instructions. */
76 #define X_OP(i) (((i) >> 30) & 0x3)
77 #define X_RD(i) (((i) >> 25) & 0x1f)
78 #define X_A(i) (((i) >> 29) & 1)
79 #define X_COND(i) (((i) >> 25) & 0xf)
80 #define X_OP2(i) (((i) >> 22) & 0x7)
81 #define X_IMM22(i) ((i) & 0x3fffff)
82 #define X_OP3(i) (((i) >> 19) & 0x3f)
83 #define X_RS1(i) (((i) >> 14) & 0x1f)
84 #define X_RS2(i) ((i) & 0x1f)
85 #define X_I(i) (((i) >> 13) & 1)
86 /* Sign extension macros. */
87 #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000)
88 #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000)
89 #define X_DISP10(i) ((((((i) >> 11) && 0x300) | (((i) >> 5) & 0xff)) ^ 0x200) - 0x200)
90 #define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000)
91 /* Macros to identify some instructions. */
92 /* RETURN (RETT in V8) */
93 #define X_RETTURN(i) ((X_OP (i) == 0x2) && (X_OP3 (i) == 0x39))
95 /* Fetch the instruction at PC. Instructions are always big-endian
96 even if the processor operates in little-endian mode. */
99 sparc_fetch_instruction (CORE_ADDR pc
)
105 /* If we can't read the instruction at PC, return zero. */
106 if (target_read_memory (pc
, buf
, sizeof (buf
)))
110 for (i
= 0; i
< sizeof (buf
); i
++)
111 insn
= (insn
<< 8) | buf
[i
];
116 /* Return non-zero if the instruction corresponding to PC is an "unimp"
120 sparc_is_unimp_insn (CORE_ADDR pc
)
122 const unsigned long insn
= sparc_fetch_instruction (pc
);
124 return ((insn
& 0xc1c00000) == 0);
127 /* Return non-zero if the instruction corresponding to PC is an
128 "annulled" branch, i.e. the annul bit is set. */
131 sparc_is_annulled_branch_insn (CORE_ADDR pc
)
133 /* The branch instructions featuring an annul bit can be identified
134 by the following bit patterns:
137 OP2=1: Branch on Integer Condition Codes with Prediction (BPcc).
138 OP2=2: Branch on Integer Condition Codes (Bcc).
139 OP2=5: Branch on FP Condition Codes with Prediction (FBfcc).
140 OP2=6: Branch on FP Condition Codes (FBcc).
142 Branch on Integer Register with Prediction (BPr).
144 This leaves out ILLTRAP (OP2=0), SETHI/NOP (OP2=4) and the V8
145 coprocessor branch instructions (Op2=7). */
147 const unsigned long insn
= sparc_fetch_instruction (pc
);
148 const unsigned op2
= X_OP2 (insn
);
150 if ((X_OP (insn
) == 0)
151 && ((op2
== 1) || (op2
== 2) || (op2
== 5) || (op2
== 6)
152 || ((op2
== 3) && ((insn
& 0x10000000) == 0))))
158 /* OpenBSD/sparc includes StackGhost, which according to the author's
159 website http://stackghost.cerias.purdue.edu "... transparently and
160 automatically protects applications' stack frames; more
161 specifically, it guards the return pointers. The protection
162 mechanisms require no application source or binary modification and
163 imposes only a negligible performance penalty."
165 The same website provides the following description of how
168 "StackGhost interfaces with the kernel trap handler that would
169 normally write out registers to the stack and the handler that
170 would read them back in. By XORing a cookie into the
171 return-address saved in the user stack when it is actually written
172 to the stack, and then XOR it out when the return-address is pulled
173 from the stack, StackGhost can cause attacker corrupted return
174 pointers to behave in a manner the attacker cannot predict.
175 StackGhost can also use several unused bits in the return pointer
176 to detect a smashed return pointer and abort the process."
178 For GDB this means that whenever we're reading %i7 from a stack
179 frame's window save area, we'll have to XOR the cookie.
181 More information on StackGuard can be found on in:
183 Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated
184 Stack Protection." 2001. Published in USENIX Security Symposium
187 /* Fetch StackGhost Per-Process XOR cookie. */
190 sparc_fetch_wcookie (struct gdbarch
*gdbarch
)
192 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
193 struct target_ops
*ops
= ¤t_target
;
197 len
= target_read (ops
, TARGET_OBJECT_WCOOKIE
, NULL
, buf
, 0, 8);
201 /* We should have either an 32-bit or an 64-bit cookie. */
202 gdb_assert (len
== 4 || len
== 8);
204 return extract_unsigned_integer (buf
, len
, byte_order
);
208 /* The functions on this page are intended to be used to classify
209 function arguments. */
211 /* Check whether TYPE is "Integral or Pointer". */
214 sparc_integral_or_pointer_p (const struct type
*type
)
216 int len
= TYPE_LENGTH (type
);
218 switch (TYPE_CODE (type
))
224 case TYPE_CODE_RANGE
:
225 /* We have byte, half-word, word and extended-word/doubleword
226 integral types. The doubleword is an extension to the
227 original 32-bit ABI by the SCD 2.4.x. */
228 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
231 case TYPE_CODE_RVALUE_REF
:
232 /* Allow either 32-bit or 64-bit pointers. */
233 return (len
== 4 || len
== 8);
241 /* Check whether TYPE is "Floating". */
244 sparc_floating_p (const struct type
*type
)
246 switch (TYPE_CODE (type
))
250 int len
= TYPE_LENGTH (type
);
251 return (len
== 4 || len
== 8 || len
== 16);
260 /* Check whether TYPE is "Complex Floating". */
263 sparc_complex_floating_p (const struct type
*type
)
265 switch (TYPE_CODE (type
))
267 case TYPE_CODE_COMPLEX
:
269 int len
= TYPE_LENGTH (type
);
270 return (len
== 8 || len
== 16 || len
== 32);
279 /* Check whether TYPE is "Structure or Union".
281 In terms of Ada subprogram calls, arrays are treated the same as
282 struct and union types. So this function also returns non-zero
286 sparc_structure_or_union_p (const struct type
*type
)
288 switch (TYPE_CODE (type
))
290 case TYPE_CODE_STRUCT
:
291 case TYPE_CODE_UNION
:
292 case TYPE_CODE_ARRAY
:
301 /* Register information. */
302 #define SPARC32_FPU_REGISTERS \
303 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
304 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
305 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", \
306 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
307 #define SPARC32_CP0_REGISTERS \
308 "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr"
310 static const char *sparc_core_register_names
[] = { SPARC_CORE_REGISTERS
};
311 static const char *sparc32_fpu_register_names
[] = { SPARC32_FPU_REGISTERS
};
312 static const char *sparc32_cp0_register_names
[] = { SPARC32_CP0_REGISTERS
};
314 static const char *sparc32_register_names
[] =
316 SPARC_CORE_REGISTERS
,
317 SPARC32_FPU_REGISTERS
,
318 SPARC32_CP0_REGISTERS
321 /* Total number of registers. */
322 #define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names)
324 /* We provide the aliases %d0..%d30 for the floating registers as
325 "psuedo" registers. */
327 static const char *sparc32_pseudo_register_names
[] =
329 "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14",
330 "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30"
333 /* Total number of pseudo registers. */
334 #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names)
336 /* Return the name of pseudo register REGNUM. */
339 sparc32_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
341 regnum
-= gdbarch_num_regs (gdbarch
);
343 if (regnum
< SPARC32_NUM_PSEUDO_REGS
)
344 return sparc32_pseudo_register_names
[regnum
];
346 internal_error (__FILE__
, __LINE__
,
347 _("sparc32_pseudo_register_name: bad register number %d"),
351 /* Return the name of register REGNUM. */
354 sparc32_register_name (struct gdbarch
*gdbarch
, int regnum
)
356 if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
357 return tdesc_register_name (gdbarch
, regnum
);
359 if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
))
360 return sparc32_register_names
[regnum
];
362 return sparc32_pseudo_register_name (gdbarch
, regnum
);
365 /* Construct types for ISA-specific registers. */
368 sparc_psr_type (struct gdbarch
*gdbarch
)
370 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
372 if (!tdep
->sparc_psr_type
)
376 type
= arch_flags_type (gdbarch
, "builtin_type_sparc_psr", 4);
377 append_flags_type_flag (type
, 5, "ET");
378 append_flags_type_flag (type
, 6, "PS");
379 append_flags_type_flag (type
, 7, "S");
380 append_flags_type_flag (type
, 12, "EF");
381 append_flags_type_flag (type
, 13, "EC");
383 tdep
->sparc_psr_type
= type
;
386 return tdep
->sparc_psr_type
;
390 sparc_fsr_type (struct gdbarch
*gdbarch
)
392 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
394 if (!tdep
->sparc_fsr_type
)
398 type
= arch_flags_type (gdbarch
, "builtin_type_sparc_fsr", 4);
399 append_flags_type_flag (type
, 0, "NXA");
400 append_flags_type_flag (type
, 1, "DZA");
401 append_flags_type_flag (type
, 2, "UFA");
402 append_flags_type_flag (type
, 3, "OFA");
403 append_flags_type_flag (type
, 4, "NVA");
404 append_flags_type_flag (type
, 5, "NXC");
405 append_flags_type_flag (type
, 6, "DZC");
406 append_flags_type_flag (type
, 7, "UFC");
407 append_flags_type_flag (type
, 8, "OFC");
408 append_flags_type_flag (type
, 9, "NVC");
409 append_flags_type_flag (type
, 22, "NS");
410 append_flags_type_flag (type
, 23, "NXM");
411 append_flags_type_flag (type
, 24, "DZM");
412 append_flags_type_flag (type
, 25, "UFM");
413 append_flags_type_flag (type
, 26, "OFM");
414 append_flags_type_flag (type
, 27, "NVM");
416 tdep
->sparc_fsr_type
= type
;
419 return tdep
->sparc_fsr_type
;
422 /* Return the GDB type object for the "standard" data type of data in
423 pseudo register REGNUM. */
426 sparc32_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
428 regnum
-= gdbarch_num_regs (gdbarch
);
430 if (regnum
>= SPARC32_D0_REGNUM
&& regnum
<= SPARC32_D30_REGNUM
)
431 return builtin_type (gdbarch
)->builtin_double
;
433 internal_error (__FILE__
, __LINE__
,
434 _("sparc32_pseudo_register_type: bad register number %d"),
438 /* Return the GDB type object for the "standard" data type of data in
442 sparc32_register_type (struct gdbarch
*gdbarch
, int regnum
)
444 if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
445 return tdesc_register_type (gdbarch
, regnum
);
447 if (regnum
>= SPARC_F0_REGNUM
&& regnum
<= SPARC_F31_REGNUM
)
448 return builtin_type (gdbarch
)->builtin_float
;
450 if (regnum
== SPARC_SP_REGNUM
|| regnum
== SPARC_FP_REGNUM
)
451 return builtin_type (gdbarch
)->builtin_data_ptr
;
453 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== SPARC32_NPC_REGNUM
)
454 return builtin_type (gdbarch
)->builtin_func_ptr
;
456 if (regnum
== SPARC32_PSR_REGNUM
)
457 return sparc_psr_type (gdbarch
);
459 if (regnum
== SPARC32_FSR_REGNUM
)
460 return sparc_fsr_type (gdbarch
);
462 if (regnum
>= gdbarch_num_regs (gdbarch
))
463 return sparc32_pseudo_register_type (gdbarch
, regnum
);
465 return builtin_type (gdbarch
)->builtin_int32
;
468 static enum register_status
469 sparc32_pseudo_register_read (struct gdbarch
*gdbarch
,
470 struct regcache
*regcache
,
471 int regnum
, gdb_byte
*buf
)
473 enum register_status status
;
475 regnum
-= gdbarch_num_regs (gdbarch
);
476 gdb_assert (regnum
>= SPARC32_D0_REGNUM
&& regnum
<= SPARC32_D30_REGNUM
);
478 regnum
= SPARC_F0_REGNUM
+ 2 * (regnum
- SPARC32_D0_REGNUM
);
479 status
= regcache_raw_read (regcache
, regnum
, buf
);
480 if (status
== REG_VALID
)
481 status
= regcache_raw_read (regcache
, regnum
+ 1, buf
+ 4);
486 sparc32_pseudo_register_write (struct gdbarch
*gdbarch
,
487 struct regcache
*regcache
,
488 int regnum
, const gdb_byte
*buf
)
490 regnum
-= gdbarch_num_regs (gdbarch
);
491 gdb_assert (regnum
>= SPARC32_D0_REGNUM
&& regnum
<= SPARC32_D30_REGNUM
);
493 regnum
= SPARC_F0_REGNUM
+ 2 * (regnum
- SPARC32_D0_REGNUM
);
494 regcache_raw_write (regcache
, regnum
, buf
);
495 regcache_raw_write (regcache
, regnum
+ 1, buf
+ 4);
498 /* Implement the stack_frame_destroyed_p gdbarch method. */
501 sparc_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
503 /* This function must return true if we are one instruction after an
504 instruction that destroyed the stack frame of the current
505 function. The SPARC instructions used to restore the callers
506 stack frame are RESTORE and RETURN/RETT.
508 Of these RETURN/RETT is a branch instruction and thus we return
509 true if we are in its delay slot.
511 RESTORE is almost always found in the delay slot of a branch
512 instruction that transfers control to the caller, such as JMPL.
513 Thus the next instruction is in the caller frame and we don't
514 need to do anything about it. */
516 unsigned int insn
= sparc_fetch_instruction (pc
- 4);
518 return X_RETTURN (insn
);
523 sparc32_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR address
)
525 /* The ABI requires double-word alignment. */
526 return address
& ~0x7;
530 sparc32_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
532 struct value
**args
, int nargs
,
533 struct type
*value_type
,
534 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
535 struct regcache
*regcache
)
537 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
542 if (using_struct_return (gdbarch
, NULL
, value_type
))
546 /* This is an UNIMP instruction. */
547 store_unsigned_integer (buf
, 4, byte_order
,
548 TYPE_LENGTH (value_type
) & 0x1fff);
549 write_memory (sp
- 8, buf
, 4);
557 sparc32_store_arguments (struct regcache
*regcache
, int nargs
,
558 struct value
**args
, CORE_ADDR sp
,
559 int struct_return
, CORE_ADDR struct_addr
)
561 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
562 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
563 /* Number of words in the "parameter array". */
564 int num_elements
= 0;
568 for (i
= 0; i
< nargs
; i
++)
570 struct type
*type
= value_type (args
[i
]);
571 int len
= TYPE_LENGTH (type
);
573 if (sparc_structure_or_union_p (type
)
574 || (sparc_floating_p (type
) && len
== 16)
575 || sparc_complex_floating_p (type
))
577 /* Structure, Union and Quad-Precision Arguments. */
580 /* Use doubleword alignment for these values. That's always
581 correct, and wasting a few bytes shouldn't be a problem. */
584 write_memory (sp
, value_contents (args
[i
]), len
);
585 args
[i
] = value_from_pointer (lookup_pointer_type (type
), sp
);
588 else if (sparc_floating_p (type
))
590 /* Floating arguments. */
591 gdb_assert (len
== 4 || len
== 8);
592 num_elements
+= (len
/ 4);
596 /* Integral and pointer arguments. */
597 gdb_assert (sparc_integral_or_pointer_p (type
));
600 args
[i
] = value_cast (builtin_type (gdbarch
)->builtin_int32
,
602 num_elements
+= ((len
+ 3) / 4);
606 /* Always allocate at least six words. */
607 sp
-= std::max (6, num_elements
) * 4;
609 /* The psABI says that "Software convention requires space for the
610 struct/union return value pointer, even if the word is unused." */
613 /* The psABI says that "Although software convention and the
614 operating system require every stack frame to be doubleword
618 for (i
= 0; i
< nargs
; i
++)
620 const bfd_byte
*valbuf
= value_contents (args
[i
]);
621 struct type
*type
= value_type (args
[i
]);
622 int len
= TYPE_LENGTH (type
);
624 gdb_assert (len
== 4 || len
== 8);
628 int regnum
= SPARC_O0_REGNUM
+ element
;
630 regcache_cooked_write (regcache
, regnum
, valbuf
);
631 if (len
> 4 && element
< 5)
632 regcache_cooked_write (regcache
, regnum
+ 1, valbuf
+ 4);
635 /* Always store the argument in memory. */
636 write_memory (sp
+ 4 + element
* 4, valbuf
, len
);
640 gdb_assert (element
== num_elements
);
646 store_unsigned_integer (buf
, 4, byte_order
, struct_addr
);
647 write_memory (sp
, buf
, 4);
654 sparc32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
655 struct regcache
*regcache
, CORE_ADDR bp_addr
,
656 int nargs
, struct value
**args
, CORE_ADDR sp
,
657 int struct_return
, CORE_ADDR struct_addr
)
659 CORE_ADDR call_pc
= (struct_return
? (bp_addr
- 12) : (bp_addr
- 8));
661 /* Set return address. */
662 regcache_cooked_write_unsigned (regcache
, SPARC_O7_REGNUM
, call_pc
);
664 /* Set up function arguments. */
665 sp
= sparc32_store_arguments (regcache
, nargs
, args
, sp
,
666 struct_return
, struct_addr
);
668 /* Allocate the 16-word window save area. */
671 /* Stack should be doubleword aligned at this point. */
672 gdb_assert (sp
% 8 == 0);
674 /* Finally, update the stack pointer. */
675 regcache_cooked_write_unsigned (regcache
, SPARC_SP_REGNUM
, sp
);
681 /* Use the program counter to determine the contents and size of a
682 breakpoint instruction. Return a pointer to a string of bytes that
683 encode a breakpoint instruction, store the length of the string in
684 *LEN and optionally adjust *PC to point to the correct memory
685 location for inserting the breakpoint. */
686 constexpr gdb_byte sparc_break_insn
[] = { 0x91, 0xd0, 0x20, 0x01 };
688 typedef BP_MANIPULATION (sparc_break_insn
) sparc_breakpoint
;
691 /* Allocate and initialize a frame cache. */
693 static struct sparc_frame_cache
*
694 sparc_alloc_frame_cache (void)
696 struct sparc_frame_cache
*cache
;
698 cache
= FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache
);
704 /* Frameless until proven otherwise. */
705 cache
->frameless_p
= 1;
706 cache
->frame_offset
= 0;
707 cache
->saved_regs_mask
= 0;
708 cache
->copied_regs_mask
= 0;
709 cache
->struct_return_p
= 0;
714 /* GCC generates several well-known sequences of instructions at the begining
715 of each function prologue when compiling with -fstack-check. If one of
716 such sequences starts at START_PC, then return the address of the
717 instruction immediately past this sequence. Otherwise, return START_PC. */
720 sparc_skip_stack_check (const CORE_ADDR start_pc
)
722 CORE_ADDR pc
= start_pc
;
724 int probing_loop
= 0;
726 /* With GCC, all stack checking sequences begin with the same two
727 instructions, plus an optional one in the case of a probing loop:
729 sethi <some immediate>, %g1
734 sethi <some immediate>, %g1
735 sethi <some immediate>, %g4
740 sethi <some immediate>, %g1
742 sethi <some immediate>, %g4
744 If the optional instruction is found (setting g4), assume that a
745 probing loop will follow. */
747 /* sethi <some immediate>, %g1 */
748 insn
= sparc_fetch_instruction (pc
);
750 if (!(X_OP (insn
) == 0 && X_OP2 (insn
) == 0x4 && X_RD (insn
) == 1))
753 /* optional: sethi <some immediate>, %g4 */
754 insn
= sparc_fetch_instruction (pc
);
756 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 0x4 && X_RD (insn
) == 4)
759 insn
= sparc_fetch_instruction (pc
);
763 /* sub %sp, %g1, %g1 */
764 if (!(X_OP (insn
) == 2 && X_OP3 (insn
) == 0x4 && !X_I(insn
)
765 && X_RD (insn
) == 1 && X_RS1 (insn
) == 14 && X_RS2 (insn
) == 1))
768 insn
= sparc_fetch_instruction (pc
);
771 /* optional: sethi <some immediate>, %g4 */
772 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 0x4 && X_RD (insn
) == 4)
775 insn
= sparc_fetch_instruction (pc
);
779 /* First possible sequence:
780 [first two instructions above]
781 clr [%g1 - some immediate] */
783 /* clr [%g1 - some immediate] */
784 if (X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && X_I(insn
)
785 && X_RS1 (insn
) == 1 && X_RD (insn
) == 0)
787 /* Valid stack-check sequence, return the new PC. */
791 /* Second possible sequence: A small number of probes.
792 [first two instructions above]
794 add %g1, -<some immediate>, %g1
796 [repeat the two instructions above any (small) number of times]
797 clr [%g1 - some immediate] */
800 else if (X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && !X_I(insn
)
801 && X_RS1 (insn
) == 1 && X_RD (insn
) == 0)
805 /* add %g1, -<some immediate>, %g1 */
806 insn
= sparc_fetch_instruction (pc
);
808 if (!(X_OP (insn
) == 2 && X_OP3(insn
) == 0 && X_I(insn
)
809 && X_RS1 (insn
) == 1 && X_RD (insn
) == 1))
813 insn
= sparc_fetch_instruction (pc
);
815 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && !X_I(insn
)
816 && X_RD (insn
) == 0 && X_RS1 (insn
) == 1))
820 /* clr [%g1 - some immediate] */
821 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && X_I(insn
)
822 && X_RS1 (insn
) == 1 && X_RD (insn
) == 0))
825 /* We found a valid stack-check sequence, return the new PC. */
829 /* Third sequence: A probing loop.
830 [first three instructions above]
834 add %g1, -<some immediate>, %g1
838 And an optional last probe for the remainder:
840 clr [%g4 - some immediate] */
844 /* sub %g1, %g4, %g4 */
845 if (!(X_OP (insn
) == 2 && X_OP3 (insn
) == 0x4 && !X_I(insn
)
846 && X_RD (insn
) == 4 && X_RS1 (insn
) == 1 && X_RS2 (insn
) == 4))
850 insn
= sparc_fetch_instruction (pc
);
852 if (!(X_OP (insn
) == 2 && X_OP3 (insn
) == 0x14 && !X_I(insn
)
853 && X_RD (insn
) == 0 && X_RS1 (insn
) == 1 && X_RS2 (insn
) == 4))
857 insn
= sparc_fetch_instruction (pc
);
859 if (!(X_OP (insn
) == 0 && X_COND (insn
) == 0x1))
862 /* add %g1, -<some immediate>, %g1 */
863 insn
= sparc_fetch_instruction (pc
);
865 if (!(X_OP (insn
) == 2 && X_OP3(insn
) == 0 && X_I(insn
)
866 && X_RS1 (insn
) == 1 && X_RD (insn
) == 1))
870 insn
= sparc_fetch_instruction (pc
);
872 if (!(X_OP (insn
) == 0 && X_COND (insn
) == 0x8))
875 /* clr [%g1] (st %g0, [%g1] or st %g0, [%g1+0]) */
876 insn
= sparc_fetch_instruction (pc
);
878 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4
879 && X_RD (insn
) == 0 && X_RS1 (insn
) == 1
880 && (!X_I(insn
) || X_SIMM13 (insn
) == 0)))
883 /* We found a valid stack-check sequence, return the new PC. */
885 /* optional: clr [%g4 - some immediate] */
886 insn
= sparc_fetch_instruction (pc
);
888 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && X_I(insn
)
889 && X_RS1 (insn
) == 4 && X_RD (insn
) == 0))
895 /* No stack check code in our prologue, return the start_pc. */
899 /* Record the effect of a SAVE instruction on CACHE. */
902 sparc_record_save_insn (struct sparc_frame_cache
*cache
)
904 /* The frame is set up. */
905 cache
->frameless_p
= 0;
907 /* The frame pointer contains the CFA. */
908 cache
->frame_offset
= 0;
910 /* The `local' and `in' registers are all saved. */
911 cache
->saved_regs_mask
= 0xffff;
913 /* The `out' registers are all renamed. */
914 cache
->copied_regs_mask
= 0xff;
917 /* Do a full analysis of the prologue at PC and update CACHE accordingly.
918 Bail out early if CURRENT_PC is reached. Return the address where
919 the analysis stopped.
921 We handle both the traditional register window model and the single
922 register window (aka flat) model. */
925 sparc_analyze_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
926 CORE_ADDR current_pc
, struct sparc_frame_cache
*cache
)
928 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
933 pc
= sparc_skip_stack_check (pc
);
935 if (current_pc
<= pc
)
938 /* We have to handle to "Procedure Linkage Table" (PLT) special. On
939 SPARC the linker usually defines a symbol (typically
940 _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section.
941 This symbol makes us end up here with PC pointing at the start of
942 the PLT and CURRENT_PC probably pointing at a PLT entry. If we
943 would do our normal prologue analysis, we would probably conclude
944 that we've got a frame when in reality we don't, since the
945 dynamic linker patches up the first PLT with some code that
946 starts with a SAVE instruction. Patch up PC such that it points
947 at the start of our PLT entry. */
948 if (tdep
->plt_entry_size
> 0 && in_plt_section (current_pc
))
949 pc
= current_pc
- ((current_pc
- pc
) % tdep
->plt_entry_size
);
951 insn
= sparc_fetch_instruction (pc
);
953 /* Recognize store insns and record their sources. */
954 while (X_OP (insn
) == 3
955 && (X_OP3 (insn
) == 0x4 /* stw */
956 || X_OP3 (insn
) == 0x7 /* std */
957 || X_OP3 (insn
) == 0xe) /* stx */
958 && X_RS1 (insn
) == SPARC_SP_REGNUM
)
960 int regnum
= X_RD (insn
);
962 /* Recognize stores into the corresponding stack slots. */
963 if (regnum
>= SPARC_L0_REGNUM
&& regnum
<= SPARC_I7_REGNUM
965 && X_SIMM13 (insn
) == (X_OP3 (insn
) == 0xe
966 ? (regnum
- SPARC_L0_REGNUM
) * 8 + BIAS
967 : (regnum
- SPARC_L0_REGNUM
) * 4))
968 || (!X_I (insn
) && regnum
== SPARC_L0_REGNUM
)))
970 cache
->saved_regs_mask
|= (1 << (regnum
- SPARC_L0_REGNUM
));
971 if (X_OP3 (insn
) == 0x7)
972 cache
->saved_regs_mask
|= (1 << (regnum
+ 1 - SPARC_L0_REGNUM
));
977 insn
= sparc_fetch_instruction (pc
+ offset
);
980 /* Recognize a SETHI insn and record its destination. */
981 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 0x04)
986 insn
= sparc_fetch_instruction (pc
+ offset
);
989 /* Allow for an arithmetic operation on DEST or %g1. */
990 if (X_OP (insn
) == 2 && X_I (insn
)
991 && (X_RD (insn
) == 1 || X_RD (insn
) == dest
))
995 insn
= sparc_fetch_instruction (pc
+ offset
);
998 /* Check for the SAVE instruction that sets up the frame. */
999 if (X_OP (insn
) == 2 && X_OP3 (insn
) == 0x3c)
1001 sparc_record_save_insn (cache
);
1006 /* Check for an arithmetic operation on %sp. */
1007 if (X_OP (insn
) == 2
1008 && (X_OP3 (insn
) == 0 || X_OP3 (insn
) == 0x4)
1009 && X_RS1 (insn
) == SPARC_SP_REGNUM
1010 && X_RD (insn
) == SPARC_SP_REGNUM
)
1014 cache
->frame_offset
= X_SIMM13 (insn
);
1015 if (X_OP3 (insn
) == 0)
1016 cache
->frame_offset
= -cache
->frame_offset
;
1020 insn
= sparc_fetch_instruction (pc
+ offset
);
1022 /* Check for an arithmetic operation that sets up the frame. */
1023 if (X_OP (insn
) == 2
1024 && (X_OP3 (insn
) == 0 || X_OP3 (insn
) == 0x4)
1025 && X_RS1 (insn
) == SPARC_SP_REGNUM
1026 && X_RD (insn
) == SPARC_FP_REGNUM
)
1028 cache
->frameless_p
= 0;
1029 cache
->frame_offset
= 0;
1030 /* We could check that the amount subtracted to %sp above is the
1031 same as the one added here, but this seems superfluous. */
1032 cache
->copied_regs_mask
|= 0x40;
1035 insn
= sparc_fetch_instruction (pc
+ offset
);
1038 /* Check for a move (or) operation that copies the return register. */
1039 if (X_OP (insn
) == 2
1040 && X_OP3 (insn
) == 0x2
1042 && X_RS1 (insn
) == SPARC_G0_REGNUM
1043 && X_RS2 (insn
) == SPARC_O7_REGNUM
1044 && X_RD (insn
) == SPARC_I7_REGNUM
)
1046 cache
->copied_regs_mask
|= 0x80;
1057 sparc_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1059 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1060 return frame_unwind_register_unsigned (this_frame
, tdep
->pc_regnum
);
1063 /* Return PC of first real instruction of the function starting at
1067 sparc32_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
1069 struct symtab_and_line sal
;
1070 CORE_ADDR func_start
, func_end
;
1071 struct sparc_frame_cache cache
;
1073 /* This is the preferred method, find the end of the prologue by
1074 using the debugging information. */
1075 if (find_pc_partial_function (start_pc
, NULL
, &func_start
, &func_end
))
1077 sal
= find_pc_line (func_start
, 0);
1079 if (sal
.end
< func_end
1080 && start_pc
<= sal
.end
)
1084 start_pc
= sparc_analyze_prologue (gdbarch
, start_pc
, 0xffffffffUL
, &cache
);
1086 /* The psABI says that "Although the first 6 words of arguments
1087 reside in registers, the standard stack frame reserves space for
1088 them.". It also suggests that a function may use that space to
1089 "write incoming arguments 0 to 5" into that space, and that's
1090 indeed what GCC seems to be doing. In that case GCC will
1091 generate debug information that points to the stack slots instead
1092 of the registers, so we should consider the instructions that
1093 write out these incoming arguments onto the stack. */
1097 unsigned long insn
= sparc_fetch_instruction (start_pc
);
1099 /* Recognize instructions that store incoming arguments into the
1100 corresponding stack slots. */
1101 if (X_OP (insn
) == 3 && (X_OP3 (insn
) & 0x3c) == 0x04
1102 && X_I (insn
) && X_RS1 (insn
) == SPARC_FP_REGNUM
)
1104 int regnum
= X_RD (insn
);
1106 /* Case of arguments still in %o[0..5]. */
1107 if (regnum
>= SPARC_O0_REGNUM
&& regnum
<= SPARC_O5_REGNUM
1108 && !(cache
.copied_regs_mask
& (1 << (regnum
- SPARC_O0_REGNUM
)))
1109 && X_SIMM13 (insn
) == 68 + (regnum
- SPARC_O0_REGNUM
) * 4)
1115 /* Case of arguments copied into %i[0..5]. */
1116 if (regnum
>= SPARC_I0_REGNUM
&& regnum
<= SPARC_I5_REGNUM
1117 && (cache
.copied_regs_mask
& (1 << (regnum
- SPARC_I0_REGNUM
)))
1118 && X_SIMM13 (insn
) == 68 + (regnum
- SPARC_I0_REGNUM
) * 4)
1131 /* Normal frames. */
1133 struct sparc_frame_cache
*
1134 sparc_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1136 struct sparc_frame_cache
*cache
;
1139 return (struct sparc_frame_cache
*) *this_cache
;
1141 cache
= sparc_alloc_frame_cache ();
1142 *this_cache
= cache
;
1144 cache
->pc
= get_frame_func (this_frame
);
1146 sparc_analyze_prologue (get_frame_arch (this_frame
), cache
->pc
,
1147 get_frame_pc (this_frame
), cache
);
1149 if (cache
->frameless_p
)
1151 /* This function is frameless, so %fp (%i6) holds the frame
1152 pointer for our calling frame. Use %sp (%o6) as this frame's
1155 get_frame_register_unsigned (this_frame
, SPARC_SP_REGNUM
);
1159 /* For normal frames, %fp (%i6) holds the frame pointer, the
1160 base address for the current stack frame. */
1162 get_frame_register_unsigned (this_frame
, SPARC_FP_REGNUM
);
1165 cache
->base
+= cache
->frame_offset
;
1167 if (cache
->base
& 1)
1168 cache
->base
+= BIAS
;
1174 sparc32_struct_return_from_sym (struct symbol
*sym
)
1176 struct type
*type
= check_typedef (SYMBOL_TYPE (sym
));
1177 enum type_code code
= TYPE_CODE (type
);
1179 if (code
== TYPE_CODE_FUNC
|| code
== TYPE_CODE_METHOD
)
1181 type
= check_typedef (TYPE_TARGET_TYPE (type
));
1182 if (sparc_structure_or_union_p (type
)
1183 || (sparc_floating_p (type
) && TYPE_LENGTH (type
) == 16))
1190 struct sparc_frame_cache
*
1191 sparc32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1193 struct sparc_frame_cache
*cache
;
1197 return (struct sparc_frame_cache
*) *this_cache
;
1199 cache
= sparc_frame_cache (this_frame
, this_cache
);
1201 sym
= find_pc_function (cache
->pc
);
1204 cache
->struct_return_p
= sparc32_struct_return_from_sym (sym
);
1208 /* There is no debugging information for this function to
1209 help us determine whether this function returns a struct
1210 or not. So we rely on another heuristic which is to check
1211 the instruction at the return address and see if this is
1212 an "unimp" instruction. If it is, then it is a struct-return
1216 (cache
->copied_regs_mask
& 0x80) ? SPARC_I7_REGNUM
: SPARC_O7_REGNUM
;
1218 pc
= get_frame_register_unsigned (this_frame
, regnum
) + 8;
1219 if (sparc_is_unimp_insn (pc
))
1220 cache
->struct_return_p
= 1;
1227 sparc32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1228 struct frame_id
*this_id
)
1230 struct sparc_frame_cache
*cache
=
1231 sparc32_frame_cache (this_frame
, this_cache
);
1233 /* This marks the outermost frame. */
1234 if (cache
->base
== 0)
1237 (*this_id
) = frame_id_build (cache
->base
, cache
->pc
);
1240 static struct value
*
1241 sparc32_frame_prev_register (struct frame_info
*this_frame
,
1242 void **this_cache
, int regnum
)
1244 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1245 struct sparc_frame_cache
*cache
=
1246 sparc32_frame_cache (this_frame
, this_cache
);
1248 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== SPARC32_NPC_REGNUM
)
1250 CORE_ADDR pc
= (regnum
== SPARC32_NPC_REGNUM
) ? 4 : 0;
1252 /* If this functions has a Structure, Union or Quad-Precision
1253 return value, we have to skip the UNIMP instruction that encodes
1254 the size of the structure. */
1255 if (cache
->struct_return_p
)
1259 (cache
->copied_regs_mask
& 0x80) ? SPARC_I7_REGNUM
: SPARC_O7_REGNUM
;
1260 pc
+= get_frame_register_unsigned (this_frame
, regnum
) + 8;
1261 return frame_unwind_got_constant (this_frame
, regnum
, pc
);
1264 /* Handle StackGhost. */
1266 ULONGEST wcookie
= sparc_fetch_wcookie (gdbarch
);
1268 if (wcookie
!= 0 && !cache
->frameless_p
&& regnum
== SPARC_I7_REGNUM
)
1270 CORE_ADDR addr
= cache
->base
+ (regnum
- SPARC_L0_REGNUM
) * 4;
1273 /* Read the value in from memory. */
1274 i7
= get_frame_memory_unsigned (this_frame
, addr
, 4);
1275 return frame_unwind_got_constant (this_frame
, regnum
, i7
^ wcookie
);
1279 /* The previous frame's `local' and `in' registers may have been saved
1280 in the register save area. */
1281 if (regnum
>= SPARC_L0_REGNUM
&& regnum
<= SPARC_I7_REGNUM
1282 && (cache
->saved_regs_mask
& (1 << (regnum
- SPARC_L0_REGNUM
))))
1284 CORE_ADDR addr
= cache
->base
+ (regnum
- SPARC_L0_REGNUM
) * 4;
1286 return frame_unwind_got_memory (this_frame
, regnum
, addr
);
1289 /* The previous frame's `out' registers may be accessible as the current
1290 frame's `in' registers. */
1291 if (regnum
>= SPARC_O0_REGNUM
&& regnum
<= SPARC_O7_REGNUM
1292 && (cache
->copied_regs_mask
& (1 << (regnum
- SPARC_O0_REGNUM
))))
1293 regnum
+= (SPARC_I0_REGNUM
- SPARC_O0_REGNUM
);
1295 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1298 static const struct frame_unwind sparc32_frame_unwind
=
1301 default_frame_unwind_stop_reason
,
1302 sparc32_frame_this_id
,
1303 sparc32_frame_prev_register
,
1305 default_frame_sniffer
1310 sparc32_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
1312 struct sparc_frame_cache
*cache
=
1313 sparc32_frame_cache (this_frame
, this_cache
);
1318 static const struct frame_base sparc32_frame_base
=
1320 &sparc32_frame_unwind
,
1321 sparc32_frame_base_address
,
1322 sparc32_frame_base_address
,
1323 sparc32_frame_base_address
1326 static struct frame_id
1327 sparc_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1331 sp
= get_frame_register_unsigned (this_frame
, SPARC_SP_REGNUM
);
1334 return frame_id_build (sp
, get_frame_pc (this_frame
));
1338 /* Extract a function return value of TYPE from REGCACHE, and copy
1339 that into VALBUF. */
1342 sparc32_extract_return_value (struct type
*type
, struct regcache
*regcache
,
1345 int len
= TYPE_LENGTH (type
);
1348 gdb_assert (!sparc_structure_or_union_p (type
));
1349 gdb_assert (!(sparc_floating_p (type
) && len
== 16));
1351 if (sparc_floating_p (type
) || sparc_complex_floating_p (type
))
1353 /* Floating return values. */
1354 regcache_cooked_read (regcache
, SPARC_F0_REGNUM
, buf
);
1356 regcache_cooked_read (regcache
, SPARC_F1_REGNUM
, buf
+ 4);
1359 regcache_cooked_read (regcache
, SPARC_F2_REGNUM
, buf
+ 8);
1360 regcache_cooked_read (regcache
, SPARC_F3_REGNUM
, buf
+ 12);
1364 regcache_cooked_read (regcache
, SPARC_F4_REGNUM
, buf
+ 16);
1365 regcache_cooked_read (regcache
, SPARC_F5_REGNUM
, buf
+ 20);
1366 regcache_cooked_read (regcache
, SPARC_F6_REGNUM
, buf
+ 24);
1367 regcache_cooked_read (regcache
, SPARC_F7_REGNUM
, buf
+ 28);
1369 memcpy (valbuf
, buf
, len
);
1373 /* Integral and pointer return values. */
1374 gdb_assert (sparc_integral_or_pointer_p (type
));
1376 regcache_cooked_read (regcache
, SPARC_O0_REGNUM
, buf
);
1379 regcache_cooked_read (regcache
, SPARC_O1_REGNUM
, buf
+ 4);
1380 gdb_assert (len
== 8);
1381 memcpy (valbuf
, buf
, 8);
1385 /* Just stripping off any unused bytes should preserve the
1386 signed-ness just fine. */
1387 memcpy (valbuf
, buf
+ 4 - len
, len
);
1392 /* Store the function return value of type TYPE from VALBUF into
1396 sparc32_store_return_value (struct type
*type
, struct regcache
*regcache
,
1397 const gdb_byte
*valbuf
)
1399 int len
= TYPE_LENGTH (type
);
1402 gdb_assert (!sparc_structure_or_union_p (type
));
1403 gdb_assert (!(sparc_floating_p (type
) && len
== 16));
1404 gdb_assert (len
<= 8);
1406 if (sparc_floating_p (type
) || sparc_complex_floating_p (type
))
1408 /* Floating return values. */
1409 memcpy (buf
, valbuf
, len
);
1410 regcache_cooked_write (regcache
, SPARC_F0_REGNUM
, buf
);
1412 regcache_cooked_write (regcache
, SPARC_F1_REGNUM
, buf
+ 4);
1415 regcache_cooked_write (regcache
, SPARC_F2_REGNUM
, buf
+ 8);
1416 regcache_cooked_write (regcache
, SPARC_F3_REGNUM
, buf
+ 12);
1420 regcache_cooked_write (regcache
, SPARC_F4_REGNUM
, buf
+ 16);
1421 regcache_cooked_write (regcache
, SPARC_F5_REGNUM
, buf
+ 20);
1422 regcache_cooked_write (regcache
, SPARC_F6_REGNUM
, buf
+ 24);
1423 regcache_cooked_write (regcache
, SPARC_F7_REGNUM
, buf
+ 28);
1428 /* Integral and pointer return values. */
1429 gdb_assert (sparc_integral_or_pointer_p (type
));
1433 gdb_assert (len
== 8);
1434 memcpy (buf
, valbuf
, 8);
1435 regcache_cooked_write (regcache
, SPARC_O1_REGNUM
, buf
+ 4);
1439 /* ??? Do we need to do any sign-extension here? */
1440 memcpy (buf
+ 4 - len
, valbuf
, len
);
1442 regcache_cooked_write (regcache
, SPARC_O0_REGNUM
, buf
);
1446 static enum return_value_convention
1447 sparc32_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
1448 struct type
*type
, struct regcache
*regcache
,
1449 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1451 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1453 /* The psABI says that "...every stack frame reserves the word at
1454 %fp+64. If a function returns a structure, union, or
1455 quad-precision value, this word should hold the address of the
1456 object into which the return value should be copied." This
1457 guarantees that we can always find the return value, not just
1458 before the function returns. */
1460 if (sparc_structure_or_union_p (type
)
1461 || (sparc_floating_p (type
) && TYPE_LENGTH (type
) == 16))
1468 regcache_cooked_read_unsigned (regcache
, SPARC_SP_REGNUM
, &sp
);
1469 addr
= read_memory_unsigned_integer (sp
+ 64, 4, byte_order
);
1470 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
1474 regcache_cooked_read_unsigned (regcache
, SPARC_SP_REGNUM
, &sp
);
1475 addr
= read_memory_unsigned_integer (sp
+ 64, 4, byte_order
);
1476 write_memory (addr
, writebuf
, TYPE_LENGTH (type
));
1479 return RETURN_VALUE_ABI_PRESERVES_ADDRESS
;
1483 sparc32_extract_return_value (type
, regcache
, readbuf
);
1485 sparc32_store_return_value (type
, regcache
, writebuf
);
1487 return RETURN_VALUE_REGISTER_CONVENTION
;
1491 sparc32_stabs_argument_has_addr (struct gdbarch
*gdbarch
, struct type
*type
)
1493 return (sparc_structure_or_union_p (type
)
1494 || (sparc_floating_p (type
) && TYPE_LENGTH (type
) == 16)
1495 || sparc_complex_floating_p (type
));
1499 sparc32_dwarf2_struct_return_p (struct frame_info
*this_frame
)
1501 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
1502 struct symbol
*sym
= find_pc_function (pc
);
1505 return sparc32_struct_return_from_sym (sym
);
1510 sparc32_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1511 struct dwarf2_frame_state_reg
*reg
,
1512 struct frame_info
*this_frame
)
1518 case SPARC_G0_REGNUM
:
1519 /* Since %g0 is always zero, there is no point in saving it, and
1520 people will be inclined omit it from the CFI. Make sure we
1521 don't warn about that. */
1522 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
1524 case SPARC_SP_REGNUM
:
1525 reg
->how
= DWARF2_FRAME_REG_CFA
;
1527 case SPARC32_PC_REGNUM
:
1528 case SPARC32_NPC_REGNUM
:
1529 reg
->how
= DWARF2_FRAME_REG_RA_OFFSET
;
1531 if (sparc32_dwarf2_struct_return_p (this_frame
))
1533 if (regnum
== SPARC32_NPC_REGNUM
)
1535 reg
->loc
.offset
= off
;
1540 /* Implement the execute_dwarf_cfa_vendor_op method. */
1543 sparc_execute_dwarf_cfa_vendor_op (struct gdbarch
*gdbarch
, gdb_byte op
,
1544 struct dwarf2_frame_state
*fs
)
1546 /* Only DW_CFA_GNU_window_save is expected on SPARC. */
1547 if (op
!= DW_CFA_GNU_window_save
)
1551 int size
= register_size (gdbarch
, 0);
1553 dwarf2_frame_state_alloc_regs (&fs
->regs
, 32);
1554 for (reg
= 8; reg
< 16; reg
++)
1556 fs
->regs
.reg
[reg
].how
= DWARF2_FRAME_REG_SAVED_REG
;
1557 fs
->regs
.reg
[reg
].loc
.reg
= reg
+ 16;
1559 for (reg
= 16; reg
< 32; reg
++)
1561 fs
->regs
.reg
[reg
].how
= DWARF2_FRAME_REG_SAVED_OFFSET
;
1562 fs
->regs
.reg
[reg
].loc
.offset
= (reg
- 16) * size
;
1569 /* The SPARC Architecture doesn't have hardware single-step support,
1570 and most operating systems don't implement it either, so we provide
1571 software single-step mechanism. */
1574 sparc_analyze_control_transfer (struct regcache
*regcache
,
1575 CORE_ADDR pc
, CORE_ADDR
*npc
)
1577 unsigned long insn
= sparc_fetch_instruction (pc
);
1578 int conditional_p
= X_COND (insn
) & 0x7;
1579 int branch_p
= 0, fused_p
= 0;
1580 long offset
= 0; /* Must be signed for sign-extend. */
1582 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 3)
1584 if ((insn
& 0x10000000) == 0)
1586 /* Branch on Integer Register with Prediction (BPr). */
1592 /* Compare and Branch */
1595 offset
= 4 * X_DISP10 (insn
);
1598 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 6)
1600 /* Branch on Floating-Point Condition Codes (FBfcc). */
1602 offset
= 4 * X_DISP22 (insn
);
1604 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 5)
1606 /* Branch on Floating-Point Condition Codes with Prediction
1609 offset
= 4 * X_DISP19 (insn
);
1611 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 2)
1613 /* Branch on Integer Condition Codes (Bicc). */
1615 offset
= 4 * X_DISP22 (insn
);
1617 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 1)
1619 /* Branch on Integer Condition Codes with Prediction (BPcc). */
1621 offset
= 4 * X_DISP19 (insn
);
1623 else if (X_OP (insn
) == 2 && X_OP3 (insn
) == 0x3a)
1625 struct frame_info
*frame
= get_current_frame ();
1627 /* Trap instruction (TRAP). */
1628 return gdbarch_tdep (get_regcache_arch (regcache
))->step_trap (frame
,
1632 /* FIXME: Handle DONE and RETRY instructions. */
1638 /* Fused compare-and-branch instructions are non-delayed,
1639 and do not have an annuling capability. So we need to
1640 always set a breakpoint on both the NPC and the branch
1642 gdb_assert (offset
!= 0);
1645 else if (conditional_p
)
1647 /* For conditional branches, return nPC + 4 iff the annul
1649 return (X_A (insn
) ? *npc
+ 4 : 0);
1653 /* For unconditional branches, return the target if its
1654 specified condition is "always" and return nPC + 4 if the
1655 condition is "never". If the annul bit is 1, set *NPC to
1657 if (X_COND (insn
) == 0x0)
1658 pc
= *npc
, offset
= 4;
1670 sparc_step_trap (struct frame_info
*frame
, unsigned long insn
)
1675 static std::vector
<CORE_ADDR
>
1676 sparc_software_single_step (struct regcache
*regcache
)
1678 struct gdbarch
*arch
= get_regcache_arch (regcache
);
1679 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
1680 CORE_ADDR npc
, nnpc
;
1682 CORE_ADDR pc
, orig_npc
;
1683 std::vector
<CORE_ADDR
> next_pcs
;
1685 pc
= regcache_raw_get_unsigned (regcache
, tdep
->pc_regnum
);
1686 orig_npc
= npc
= regcache_raw_get_unsigned (regcache
, tdep
->npc_regnum
);
1688 /* Analyze the instruction at PC. */
1689 nnpc
= sparc_analyze_control_transfer (regcache
, pc
, &npc
);
1691 next_pcs
.push_back (npc
);
1694 next_pcs
.push_back (nnpc
);
1696 /* Assert that we have set at least one breakpoint, and that
1697 they're not set at the same spot - unless we're going
1698 from here straight to NULL, i.e. a call or jump to 0. */
1699 gdb_assert (npc
!= 0 || nnpc
!= 0 || orig_npc
== 0);
1700 gdb_assert (nnpc
!= npc
|| orig_npc
== 0);
1706 sparc_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1708 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_regcache_arch (regcache
));
1710 regcache_cooked_write_unsigned (regcache
, tdep
->pc_regnum
, pc
);
1711 regcache_cooked_write_unsigned (regcache
, tdep
->npc_regnum
, pc
+ 4);
1715 /* Iterate over core file register note sections. */
1718 sparc_iterate_over_regset_sections (struct gdbarch
*gdbarch
,
1719 iterate_over_regset_sections_cb
*cb
,
1721 const struct regcache
*regcache
)
1723 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1725 cb (".reg", tdep
->sizeof_gregset
, tdep
->gregset
, NULL
, cb_data
);
1726 cb (".reg2", tdep
->sizeof_fpregset
, tdep
->fpregset
, NULL
, cb_data
);
1731 validate_tdesc_registers (const struct target_desc
*tdesc
,
1732 struct tdesc_arch_data
*tdesc_data
,
1733 const char *feature_name
,
1734 const char *register_names
[],
1735 unsigned int registers_num
,
1736 unsigned int reg_start
)
1739 const struct tdesc_feature
*feature
;
1741 feature
= tdesc_find_feature (tdesc
, feature_name
);
1742 if (feature
== NULL
)
1745 for (unsigned int i
= 0; i
< registers_num
; i
++)
1746 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
1753 static struct gdbarch
*
1754 sparc32_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1756 struct gdbarch_tdep
*tdep
;
1757 const struct target_desc
*tdesc
= info
.target_desc
;
1758 struct gdbarch
*gdbarch
;
1761 /* If there is already a candidate, use it. */
1762 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
1764 return arches
->gdbarch
;
1766 /* Allocate space for the new architecture. */
1767 tdep
= XCNEW (struct gdbarch_tdep
);
1768 gdbarch
= gdbarch_alloc (&info
, tdep
);
1770 tdep
->pc_regnum
= SPARC32_PC_REGNUM
;
1771 tdep
->npc_regnum
= SPARC32_NPC_REGNUM
;
1772 tdep
->step_trap
= sparc_step_trap
;
1773 tdep
->fpu_register_names
= sparc32_fpu_register_names
;
1774 tdep
->fpu_registers_num
= ARRAY_SIZE (sparc32_fpu_register_names
);
1775 tdep
->cp0_register_names
= sparc32_cp0_register_names
;
1776 tdep
->cp0_registers_num
= ARRAY_SIZE (sparc32_cp0_register_names
);
1778 set_gdbarch_long_double_bit (gdbarch
, 128);
1779 set_gdbarch_long_double_format (gdbarch
, floatformats_sparc_quad
);
1781 set_gdbarch_wchar_bit (gdbarch
, 16);
1782 set_gdbarch_wchar_signed (gdbarch
, 1);
1784 set_gdbarch_num_regs (gdbarch
, SPARC32_NUM_REGS
);
1785 set_gdbarch_register_name (gdbarch
, sparc32_register_name
);
1786 set_gdbarch_register_type (gdbarch
, sparc32_register_type
);
1787 set_gdbarch_num_pseudo_regs (gdbarch
, SPARC32_NUM_PSEUDO_REGS
);
1788 set_tdesc_pseudo_register_name (gdbarch
, sparc32_pseudo_register_name
);
1789 set_tdesc_pseudo_register_type (gdbarch
, sparc32_pseudo_register_type
);
1790 set_gdbarch_pseudo_register_read (gdbarch
, sparc32_pseudo_register_read
);
1791 set_gdbarch_pseudo_register_write (gdbarch
, sparc32_pseudo_register_write
);
1793 /* Register numbers of various important registers. */
1794 set_gdbarch_sp_regnum (gdbarch
, SPARC_SP_REGNUM
); /* %sp */
1795 set_gdbarch_pc_regnum (gdbarch
, SPARC32_PC_REGNUM
); /* %pc */
1796 set_gdbarch_fp0_regnum (gdbarch
, SPARC_F0_REGNUM
); /* %f0 */
1798 /* Call dummy code. */
1799 set_gdbarch_frame_align (gdbarch
, sparc32_frame_align
);
1800 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
1801 set_gdbarch_push_dummy_code (gdbarch
, sparc32_push_dummy_code
);
1802 set_gdbarch_push_dummy_call (gdbarch
, sparc32_push_dummy_call
);
1804 set_gdbarch_return_value (gdbarch
, sparc32_return_value
);
1805 set_gdbarch_stabs_argument_has_addr
1806 (gdbarch
, sparc32_stabs_argument_has_addr
);
1808 set_gdbarch_skip_prologue (gdbarch
, sparc32_skip_prologue
);
1810 /* Stack grows downward. */
1811 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
1813 set_gdbarch_breakpoint_kind_from_pc (gdbarch
,
1814 sparc_breakpoint::kind_from_pc
);
1815 set_gdbarch_sw_breakpoint_from_kind (gdbarch
,
1816 sparc_breakpoint::bp_from_kind
);
1818 set_gdbarch_frame_args_skip (gdbarch
, 8);
1820 set_gdbarch_print_insn (gdbarch
, print_insn_sparc
);
1822 set_gdbarch_software_single_step (gdbarch
, sparc_software_single_step
);
1823 set_gdbarch_write_pc (gdbarch
, sparc_write_pc
);
1825 set_gdbarch_dummy_id (gdbarch
, sparc_dummy_id
);
1827 set_gdbarch_unwind_pc (gdbarch
, sparc_unwind_pc
);
1829 frame_base_set_default (gdbarch
, &sparc32_frame_base
);
1831 /* Hook in the DWARF CFI frame unwinder. */
1832 dwarf2_frame_set_init_reg (gdbarch
, sparc32_dwarf2_frame_init_reg
);
1833 /* Register DWARF vendor CFI handler. */
1834 set_gdbarch_execute_dwarf_cfa_vendor_op (gdbarch
,
1835 sparc_execute_dwarf_cfa_vendor_op
);
1836 /* FIXME: kettenis/20050423: Don't enable the unwinder until the
1837 StackGhost issues have been resolved. */
1839 /* Hook in ABI-specific overrides, if they have been registered. */
1840 gdbarch_init_osabi (info
, gdbarch
);
1842 frame_unwind_append_unwinder (gdbarch
, &sparc32_frame_unwind
);
1844 if (tdesc_has_registers (tdesc
))
1846 struct tdesc_arch_data
*tdesc_data
= tdesc_data_alloc ();
1848 /* Validate that the descriptor provides the mandatory registers
1849 and allocate their numbers. */
1850 valid_p
&= validate_tdesc_registers (tdesc
, tdesc_data
,
1851 "org.gnu.gdb.sparc.cpu",
1852 sparc_core_register_names
,
1853 ARRAY_SIZE (sparc_core_register_names
),
1855 valid_p
&= validate_tdesc_registers (tdesc
, tdesc_data
,
1856 "org.gnu.gdb.sparc.fpu",
1857 tdep
->fpu_register_names
,
1858 tdep
->fpu_registers_num
,
1860 valid_p
&= validate_tdesc_registers (tdesc
, tdesc_data
,
1861 "org.gnu.gdb.sparc.cp0",
1862 tdep
->cp0_register_names
,
1863 tdep
->cp0_registers_num
,
1865 + tdep
->fpu_registers_num
);
1868 tdesc_data_cleanup (tdesc_data
);
1872 /* Target description may have changed. */
1873 info
.tdep_info
= tdesc_data
;
1874 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
1877 /* If we have register sets, enable the generic core file support. */
1879 set_gdbarch_iterate_over_regset_sections
1880 (gdbarch
, sparc_iterate_over_regset_sections
);
1882 register_sparc_ravenscar_ops (gdbarch
);
1887 /* Helper functions for dealing with register windows. */
1890 sparc_supply_rwindow (struct regcache
*regcache
, CORE_ADDR sp
, int regnum
)
1892 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1893 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1900 /* Registers are 64-bit. */
1903 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1905 if (regnum
== i
|| regnum
== -1)
1907 target_read_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 8), buf
, 8);
1909 /* Handle StackGhost. */
1910 if (i
== SPARC_I7_REGNUM
)
1912 ULONGEST wcookie
= sparc_fetch_wcookie (gdbarch
);
1915 i7
= extract_unsigned_integer (buf
+ offset
, 8, byte_order
);
1916 store_unsigned_integer (buf
+ offset
, 8, byte_order
,
1920 regcache_raw_supply (regcache
, i
, buf
);
1926 /* Registers are 32-bit. Toss any sign-extension of the stack
1930 /* Clear out the top half of the temporary buffer, and put the
1931 register value in the bottom half if we're in 64-bit mode. */
1932 if (gdbarch_ptr_bit (get_regcache_arch (regcache
)) == 64)
1938 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1940 if (regnum
== i
|| regnum
== -1)
1942 target_read_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 4),
1945 /* Handle StackGhost. */
1946 if (i
== SPARC_I7_REGNUM
)
1948 ULONGEST wcookie
= sparc_fetch_wcookie (gdbarch
);
1951 i7
= extract_unsigned_integer (buf
+ offset
, 4, byte_order
);
1952 store_unsigned_integer (buf
+ offset
, 4, byte_order
,
1956 regcache_raw_supply (regcache
, i
, buf
);
1963 sparc_collect_rwindow (const struct regcache
*regcache
,
1964 CORE_ADDR sp
, int regnum
)
1966 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1967 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1974 /* Registers are 64-bit. */
1977 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1979 if (regnum
== -1 || regnum
== SPARC_SP_REGNUM
|| regnum
== i
)
1981 regcache_raw_collect (regcache
, i
, buf
);
1983 /* Handle StackGhost. */
1984 if (i
== SPARC_I7_REGNUM
)
1986 ULONGEST wcookie
= sparc_fetch_wcookie (gdbarch
);
1989 i7
= extract_unsigned_integer (buf
+ offset
, 8, byte_order
);
1990 store_unsigned_integer (buf
, 8, byte_order
, i7
^ wcookie
);
1993 target_write_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 8), buf
, 8);
1999 /* Registers are 32-bit. Toss any sign-extension of the stack
2003 /* Only use the bottom half if we're in 64-bit mode. */
2004 if (gdbarch_ptr_bit (get_regcache_arch (regcache
)) == 64)
2007 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
2009 if (regnum
== -1 || regnum
== SPARC_SP_REGNUM
|| regnum
== i
)
2011 regcache_raw_collect (regcache
, i
, buf
);
2013 /* Handle StackGhost. */
2014 if (i
== SPARC_I7_REGNUM
)
2016 ULONGEST wcookie
= sparc_fetch_wcookie (gdbarch
);
2019 i7
= extract_unsigned_integer (buf
+ offset
, 4, byte_order
);
2020 store_unsigned_integer (buf
+ offset
, 4, byte_order
,
2024 target_write_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 4),
2031 /* Helper functions for dealing with register sets. */
2034 sparc32_supply_gregset (const struct sparc_gregmap
*gregmap
,
2035 struct regcache
*regcache
,
2036 int regnum
, const void *gregs
)
2038 const gdb_byte
*regs
= (const gdb_byte
*) gregs
;
2039 gdb_byte zero
[4] = { 0 };
2042 if (regnum
== SPARC32_PSR_REGNUM
|| regnum
== -1)
2043 regcache_raw_supply (regcache
, SPARC32_PSR_REGNUM
,
2044 regs
+ gregmap
->r_psr_offset
);
2046 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== -1)
2047 regcache_raw_supply (regcache
, SPARC32_PC_REGNUM
,
2048 regs
+ gregmap
->r_pc_offset
);
2050 if (regnum
== SPARC32_NPC_REGNUM
|| regnum
== -1)
2051 regcache_raw_supply (regcache
, SPARC32_NPC_REGNUM
,
2052 regs
+ gregmap
->r_npc_offset
);
2054 if (regnum
== SPARC32_Y_REGNUM
|| regnum
== -1)
2055 regcache_raw_supply (regcache
, SPARC32_Y_REGNUM
,
2056 regs
+ gregmap
->r_y_offset
);
2058 if (regnum
== SPARC_G0_REGNUM
|| regnum
== -1)
2059 regcache_raw_supply (regcache
, SPARC_G0_REGNUM
, &zero
);
2061 if ((regnum
>= SPARC_G1_REGNUM
&& regnum
<= SPARC_O7_REGNUM
) || regnum
== -1)
2063 int offset
= gregmap
->r_g1_offset
;
2065 for (i
= SPARC_G1_REGNUM
; i
<= SPARC_O7_REGNUM
; i
++)
2067 if (regnum
== i
|| regnum
== -1)
2068 regcache_raw_supply (regcache
, i
, regs
+ offset
);
2073 if ((regnum
>= SPARC_L0_REGNUM
&& regnum
<= SPARC_I7_REGNUM
) || regnum
== -1)
2075 /* Not all of the register set variants include Locals and
2076 Inputs. For those that don't, we read them off the stack. */
2077 if (gregmap
->r_l0_offset
== -1)
2081 regcache_cooked_read_unsigned (regcache
, SPARC_SP_REGNUM
, &sp
);
2082 sparc_supply_rwindow (regcache
, sp
, regnum
);
2086 int offset
= gregmap
->r_l0_offset
;
2088 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
2090 if (regnum
== i
|| regnum
== -1)
2091 regcache_raw_supply (regcache
, i
, regs
+ offset
);
2099 sparc32_collect_gregset (const struct sparc_gregmap
*gregmap
,
2100 const struct regcache
*regcache
,
2101 int regnum
, void *gregs
)
2103 gdb_byte
*regs
= (gdb_byte
*) gregs
;
2106 if (regnum
== SPARC32_PSR_REGNUM
|| regnum
== -1)
2107 regcache_raw_collect (regcache
, SPARC32_PSR_REGNUM
,
2108 regs
+ gregmap
->r_psr_offset
);
2110 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== -1)
2111 regcache_raw_collect (regcache
, SPARC32_PC_REGNUM
,
2112 regs
+ gregmap
->r_pc_offset
);
2114 if (regnum
== SPARC32_NPC_REGNUM
|| regnum
== -1)
2115 regcache_raw_collect (regcache
, SPARC32_NPC_REGNUM
,
2116 regs
+ gregmap
->r_npc_offset
);
2118 if (regnum
== SPARC32_Y_REGNUM
|| regnum
== -1)
2119 regcache_raw_collect (regcache
, SPARC32_Y_REGNUM
,
2120 regs
+ gregmap
->r_y_offset
);
2122 if ((regnum
>= SPARC_G1_REGNUM
&& regnum
<= SPARC_O7_REGNUM
) || regnum
== -1)
2124 int offset
= gregmap
->r_g1_offset
;
2126 /* %g0 is always zero. */
2127 for (i
= SPARC_G1_REGNUM
; i
<= SPARC_O7_REGNUM
; i
++)
2129 if (regnum
== i
|| regnum
== -1)
2130 regcache_raw_collect (regcache
, i
, regs
+ offset
);
2135 if ((regnum
>= SPARC_L0_REGNUM
&& regnum
<= SPARC_I7_REGNUM
) || regnum
== -1)
2137 /* Not all of the register set variants include Locals and
2138 Inputs. For those that don't, we read them off the stack. */
2139 if (gregmap
->r_l0_offset
!= -1)
2141 int offset
= gregmap
->r_l0_offset
;
2143 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
2145 if (regnum
== i
|| regnum
== -1)
2146 regcache_raw_collect (regcache
, i
, regs
+ offset
);
2154 sparc32_supply_fpregset (const struct sparc_fpregmap
*fpregmap
,
2155 struct regcache
*regcache
,
2156 int regnum
, const void *fpregs
)
2158 const gdb_byte
*regs
= (const gdb_byte
*) fpregs
;
2161 for (i
= 0; i
< 32; i
++)
2163 if (regnum
== (SPARC_F0_REGNUM
+ i
) || regnum
== -1)
2164 regcache_raw_supply (regcache
, SPARC_F0_REGNUM
+ i
,
2165 regs
+ fpregmap
->r_f0_offset
+ (i
* 4));
2168 if (regnum
== SPARC32_FSR_REGNUM
|| regnum
== -1)
2169 regcache_raw_supply (regcache
, SPARC32_FSR_REGNUM
,
2170 regs
+ fpregmap
->r_fsr_offset
);
2174 sparc32_collect_fpregset (const struct sparc_fpregmap
*fpregmap
,
2175 const struct regcache
*regcache
,
2176 int regnum
, void *fpregs
)
2178 gdb_byte
*regs
= (gdb_byte
*) fpregs
;
2181 for (i
= 0; i
< 32; i
++)
2183 if (regnum
== (SPARC_F0_REGNUM
+ i
) || regnum
== -1)
2184 regcache_raw_collect (regcache
, SPARC_F0_REGNUM
+ i
,
2185 regs
+ fpregmap
->r_f0_offset
+ (i
* 4));
2188 if (regnum
== SPARC32_FSR_REGNUM
|| regnum
== -1)
2189 regcache_raw_collect (regcache
, SPARC32_FSR_REGNUM
,
2190 regs
+ fpregmap
->r_fsr_offset
);
2196 /* From <machine/reg.h>. */
2197 const struct sparc_gregmap sparc32_sunos4_gregmap
=
2209 const struct sparc_fpregmap sparc32_sunos4_fpregmap
=
2215 const struct sparc_fpregmap sparc32_bsd_fpregmap
=
2222 /* Provide a prototype to silence -Wmissing-prototypes. */
2223 void _initialize_sparc_tdep (void);
2226 _initialize_sparc_tdep (void)
2228 register_gdbarch_init (bfd_arch_sparc
, sparc32_gdbarch_init
);