2007-04-12 Luis Machado <luisgpm@br.ibm.com>
[deliverable/binutils-gdb.git] / gdb / sparc-tdep.c
1 /* Target-dependent code for SPARC.
2
3 Copyright (C) 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street, Fifth Floor,
20 Boston, MA 02110-1301, USA. */
21
22 #include "defs.h"
23 #include "arch-utils.h"
24 #include "dis-asm.h"
25 #include "dwarf2-frame.h"
26 #include "floatformat.h"
27 #include "frame.h"
28 #include "frame-base.h"
29 #include "frame-unwind.h"
30 #include "gdbcore.h"
31 #include "gdbtypes.h"
32 #include "inferior.h"
33 #include "symtab.h"
34 #include "objfiles.h"
35 #include "osabi.h"
36 #include "regcache.h"
37 #include "target.h"
38 #include "value.h"
39
40 #include "gdb_assert.h"
41 #include "gdb_string.h"
42
43 #include "sparc-tdep.h"
44
45 struct regset;
46
47 /* This file implements the SPARC 32-bit ABI as defined by the section
48 "Low-Level System Information" of the SPARC Compliance Definition
49 (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC. The SCD
50 lists changes with respect to the original 32-bit psABI as defined
51 in the "System V ABI, SPARC Processor Supplement".
52
53 Note that if we talk about SunOS, we mean SunOS 4.x, which was
54 BSD-based, which is sometimes (retroactively?) referred to as
55 Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and
56 above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9
57 suffering from severe version number inflation). Solaris 2.x is
58 also known as SunOS 5.x, since that's what uname(1) says. Solaris
59 2.x is SVR4-based. */
60
61 /* Please use the sparc32_-prefix for 32-bit specific code, the
62 sparc64_-prefix for 64-bit specific code and the sparc_-prefix for
63 code that can handle both. The 64-bit specific code lives in
64 sparc64-tdep.c; don't add any here. */
65
66 /* The SPARC Floating-Point Quad-Precision format is similar to
67 big-endian IA-64 Quad-recision format. */
68 #define floatformats_sparc_quad floatformats_ia64_quad
69
70 /* The stack pointer is offset from the stack frame by a BIAS of 2047
71 (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC
72 hosts, so undefine it first. */
73 #undef BIAS
74 #define BIAS 2047
75
76 /* Macros to extract fields from SPARC instructions. */
77 #define X_OP(i) (((i) >> 30) & 0x3)
78 #define X_RD(i) (((i) >> 25) & 0x1f)
79 #define X_A(i) (((i) >> 29) & 1)
80 #define X_COND(i) (((i) >> 25) & 0xf)
81 #define X_OP2(i) (((i) >> 22) & 0x7)
82 #define X_IMM22(i) ((i) & 0x3fffff)
83 #define X_OP3(i) (((i) >> 19) & 0x3f)
84 #define X_RS1(i) (((i) >> 14) & 0x1f)
85 #define X_RS2(i) ((i) & 0x1f)
86 #define X_I(i) (((i) >> 13) & 1)
87 /* Sign extension macros. */
88 #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000)
89 #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000)
90 #define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000)
91
92 /* Fetch the instruction at PC. Instructions are always big-endian
93 even if the processor operates in little-endian mode. */
94
95 unsigned long
96 sparc_fetch_instruction (CORE_ADDR pc)
97 {
98 gdb_byte buf[4];
99 unsigned long insn;
100 int i;
101
102 /* If we can't read the instruction at PC, return zero. */
103 if (read_memory_nobpt (pc, buf, sizeof (buf)))
104 return 0;
105
106 insn = 0;
107 for (i = 0; i < sizeof (buf); i++)
108 insn = (insn << 8) | buf[i];
109 return insn;
110 }
111 \f
112
113 /* Return non-zero if the instruction corresponding to PC is an "unimp"
114 instruction. */
115
116 static int
117 sparc_is_unimp_insn (CORE_ADDR pc)
118 {
119 const unsigned long insn = sparc_fetch_instruction (pc);
120
121 return ((insn & 0xc1c00000) == 0);
122 }
123
124 /* OpenBSD/sparc includes StackGhost, which according to the author's
125 website http://stackghost.cerias.purdue.edu "... transparently and
126 automatically protects applications' stack frames; more
127 specifically, it guards the return pointers. The protection
128 mechanisms require no application source or binary modification and
129 imposes only a negligible performance penalty."
130
131 The same website provides the following description of how
132 StackGhost works:
133
134 "StackGhost interfaces with the kernel trap handler that would
135 normally write out registers to the stack and the handler that
136 would read them back in. By XORing a cookie into the
137 return-address saved in the user stack when it is actually written
138 to the stack, and then XOR it out when the return-address is pulled
139 from the stack, StackGhost can cause attacker corrupted return
140 pointers to behave in a manner the attacker cannot predict.
141 StackGhost can also use several unused bits in the return pointer
142 to detect a smashed return pointer and abort the process."
143
144 For GDB this means that whenever we're reading %i7 from a stack
145 frame's window save area, we'll have to XOR the cookie.
146
147 More information on StackGuard can be found on in:
148
149 Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated
150 Stack Protection." 2001. Published in USENIX Security Symposium
151 '01. */
152
153 /* Fetch StackGhost Per-Process XOR cookie. */
154
155 ULONGEST
156 sparc_fetch_wcookie (void)
157 {
158 struct target_ops *ops = &current_target;
159 gdb_byte buf[8];
160 int len;
161
162 len = target_read (ops, TARGET_OBJECT_WCOOKIE, NULL, buf, 0, 8);
163 if (len == -1)
164 return 0;
165
166 /* We should have either an 32-bit or an 64-bit cookie. */
167 gdb_assert (len == 4 || len == 8);
168
169 return extract_unsigned_integer (buf, len);
170 }
171 \f
172
173 /* Return the contents if register REGNUM as an address. */
174
175 CORE_ADDR
176 sparc_address_from_register (int regnum)
177 {
178 ULONGEST addr;
179
180 regcache_cooked_read_unsigned (current_regcache, regnum, &addr);
181 return addr;
182 }
183 \f
184
185 /* The functions on this page are intended to be used to classify
186 function arguments. */
187
188 /* Check whether TYPE is "Integral or Pointer". */
189
190 static int
191 sparc_integral_or_pointer_p (const struct type *type)
192 {
193 int len = TYPE_LENGTH (type);
194
195 switch (TYPE_CODE (type))
196 {
197 case TYPE_CODE_INT:
198 case TYPE_CODE_BOOL:
199 case TYPE_CODE_CHAR:
200 case TYPE_CODE_ENUM:
201 case TYPE_CODE_RANGE:
202 /* We have byte, half-word, word and extended-word/doubleword
203 integral types. The doubleword is an extension to the
204 original 32-bit ABI by the SCD 2.4.x. */
205 return (len == 1 || len == 2 || len == 4 || len == 8);
206 case TYPE_CODE_PTR:
207 case TYPE_CODE_REF:
208 /* Allow either 32-bit or 64-bit pointers. */
209 return (len == 4 || len == 8);
210 default:
211 break;
212 }
213
214 return 0;
215 }
216
217 /* Check whether TYPE is "Floating". */
218
219 static int
220 sparc_floating_p (const struct type *type)
221 {
222 switch (TYPE_CODE (type))
223 {
224 case TYPE_CODE_FLT:
225 {
226 int len = TYPE_LENGTH (type);
227 return (len == 4 || len == 8 || len == 16);
228 }
229 default:
230 break;
231 }
232
233 return 0;
234 }
235
236 /* Check whether TYPE is "Structure or Union". */
237
238 static int
239 sparc_structure_or_union_p (const struct type *type)
240 {
241 switch (TYPE_CODE (type))
242 {
243 case TYPE_CODE_STRUCT:
244 case TYPE_CODE_UNION:
245 return 1;
246 default:
247 break;
248 }
249
250 return 0;
251 }
252
253 /* Register information. */
254
255 static const char *sparc32_register_names[] =
256 {
257 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
258 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
259 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
260 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
261
262 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
263 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
264 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
265 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
266
267 "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr"
268 };
269
270 /* Total number of registers. */
271 #define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names)
272
273 /* We provide the aliases %d0..%d30 for the floating registers as
274 "psuedo" registers. */
275
276 static const char *sparc32_pseudo_register_names[] =
277 {
278 "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14",
279 "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30"
280 };
281
282 /* Total number of pseudo registers. */
283 #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names)
284
285 /* Return the name of register REGNUM. */
286
287 static const char *
288 sparc32_register_name (int regnum)
289 {
290 if (regnum >= 0 && regnum < SPARC32_NUM_REGS)
291 return sparc32_register_names[regnum];
292
293 if (regnum < SPARC32_NUM_REGS + SPARC32_NUM_PSEUDO_REGS)
294 return sparc32_pseudo_register_names[regnum - SPARC32_NUM_REGS];
295
296 return NULL;
297 }
298 \f
299
300 /* Type for %psr. */
301 struct type *sparc_psr_type;
302
303 /* Type for %fsr. */
304 struct type *sparc_fsr_type;
305
306 /* Construct types for ISA-specific registers. */
307
308 static void
309 sparc_init_types (void)
310 {
311 struct type *type;
312
313 type = init_flags_type ("builtin_type_sparc_psr", 4);
314 append_flags_type_flag (type, 5, "ET");
315 append_flags_type_flag (type, 6, "PS");
316 append_flags_type_flag (type, 7, "S");
317 append_flags_type_flag (type, 12, "EF");
318 append_flags_type_flag (type, 13, "EC");
319 sparc_psr_type = type;
320
321 type = init_flags_type ("builtin_type_sparc_fsr", 4);
322 append_flags_type_flag (type, 0, "NXA");
323 append_flags_type_flag (type, 1, "DZA");
324 append_flags_type_flag (type, 2, "UFA");
325 append_flags_type_flag (type, 3, "OFA");
326 append_flags_type_flag (type, 4, "NVA");
327 append_flags_type_flag (type, 5, "NXC");
328 append_flags_type_flag (type, 6, "DZC");
329 append_flags_type_flag (type, 7, "UFC");
330 append_flags_type_flag (type, 8, "OFC");
331 append_flags_type_flag (type, 9, "NVC");
332 append_flags_type_flag (type, 22, "NS");
333 append_flags_type_flag (type, 23, "NXM");
334 append_flags_type_flag (type, 24, "DZM");
335 append_flags_type_flag (type, 25, "UFM");
336 append_flags_type_flag (type, 26, "OFM");
337 append_flags_type_flag (type, 27, "NVM");
338 sparc_fsr_type = type;
339 }
340
341 /* Return the GDB type object for the "standard" data type of data in
342 register REGNUM. */
343
344 static struct type *
345 sparc32_register_type (struct gdbarch *gdbarch, int regnum)
346 {
347 if (regnum >= SPARC_F0_REGNUM && regnum <= SPARC_F31_REGNUM)
348 return builtin_type_float;
349
350 if (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM)
351 return builtin_type_double;
352
353 if (regnum == SPARC_SP_REGNUM || regnum == SPARC_FP_REGNUM)
354 return builtin_type_void_data_ptr;
355
356 if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM)
357 return builtin_type_void_func_ptr;
358
359 if (regnum == SPARC32_PSR_REGNUM)
360 return sparc_psr_type;
361
362 if (regnum == SPARC32_FSR_REGNUM)
363 return sparc_fsr_type;
364
365 return builtin_type_int32;
366 }
367
368 static void
369 sparc32_pseudo_register_read (struct gdbarch *gdbarch,
370 struct regcache *regcache,
371 int regnum, gdb_byte *buf)
372 {
373 gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM);
374
375 regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM);
376 regcache_raw_read (regcache, regnum, buf);
377 regcache_raw_read (regcache, regnum + 1, buf + 4);
378 }
379
380 static void
381 sparc32_pseudo_register_write (struct gdbarch *gdbarch,
382 struct regcache *regcache,
383 int regnum, const gdb_byte *buf)
384 {
385 gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM);
386
387 regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM);
388 regcache_raw_write (regcache, regnum, buf);
389 regcache_raw_write (regcache, regnum + 1, buf + 4);
390 }
391 \f
392
393 static CORE_ADDR
394 sparc32_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp,
395 CORE_ADDR funcaddr, int using_gcc,
396 struct value **args, int nargs,
397 struct type *value_type,
398 CORE_ADDR *real_pc, CORE_ADDR *bp_addr)
399 {
400 *bp_addr = sp - 4;
401 *real_pc = funcaddr;
402
403 if (using_struct_return (value_type, using_gcc))
404 {
405 gdb_byte buf[4];
406
407 /* This is an UNIMP instruction. */
408 store_unsigned_integer (buf, 4, TYPE_LENGTH (value_type) & 0x1fff);
409 write_memory (sp - 8, buf, 4);
410 return sp - 8;
411 }
412
413 return sp - 4;
414 }
415
416 static CORE_ADDR
417 sparc32_store_arguments (struct regcache *regcache, int nargs,
418 struct value **args, CORE_ADDR sp,
419 int struct_return, CORE_ADDR struct_addr)
420 {
421 /* Number of words in the "parameter array". */
422 int num_elements = 0;
423 int element = 0;
424 int i;
425
426 for (i = 0; i < nargs; i++)
427 {
428 struct type *type = value_type (args[i]);
429 int len = TYPE_LENGTH (type);
430
431 if (sparc_structure_or_union_p (type)
432 || (sparc_floating_p (type) && len == 16))
433 {
434 /* Structure, Union and Quad-Precision Arguments. */
435 sp -= len;
436
437 /* Use doubleword alignment for these values. That's always
438 correct, and wasting a few bytes shouldn't be a problem. */
439 sp &= ~0x7;
440
441 write_memory (sp, value_contents (args[i]), len);
442 args[i] = value_from_pointer (lookup_pointer_type (type), sp);
443 num_elements++;
444 }
445 else if (sparc_floating_p (type))
446 {
447 /* Floating arguments. */
448 gdb_assert (len == 4 || len == 8);
449 num_elements += (len / 4);
450 }
451 else
452 {
453 /* Integral and pointer arguments. */
454 gdb_assert (sparc_integral_or_pointer_p (type));
455
456 if (len < 4)
457 args[i] = value_cast (builtin_type_int32, args[i]);
458 num_elements += ((len + 3) / 4);
459 }
460 }
461
462 /* Always allocate at least six words. */
463 sp -= max (6, num_elements) * 4;
464
465 /* The psABI says that "Software convention requires space for the
466 struct/union return value pointer, even if the word is unused." */
467 sp -= 4;
468
469 /* The psABI says that "Although software convention and the
470 operating system require every stack frame to be doubleword
471 aligned." */
472 sp &= ~0x7;
473
474 for (i = 0; i < nargs; i++)
475 {
476 const bfd_byte *valbuf = value_contents (args[i]);
477 struct type *type = value_type (args[i]);
478 int len = TYPE_LENGTH (type);
479
480 gdb_assert (len == 4 || len == 8);
481
482 if (element < 6)
483 {
484 int regnum = SPARC_O0_REGNUM + element;
485
486 regcache_cooked_write (regcache, regnum, valbuf);
487 if (len > 4 && element < 5)
488 regcache_cooked_write (regcache, regnum + 1, valbuf + 4);
489 }
490
491 /* Always store the argument in memory. */
492 write_memory (sp + 4 + element * 4, valbuf, len);
493 element += len / 4;
494 }
495
496 gdb_assert (element == num_elements);
497
498 if (struct_return)
499 {
500 gdb_byte buf[4];
501
502 store_unsigned_integer (buf, 4, struct_addr);
503 write_memory (sp, buf, 4);
504 }
505
506 return sp;
507 }
508
509 static CORE_ADDR
510 sparc32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
511 struct regcache *regcache, CORE_ADDR bp_addr,
512 int nargs, struct value **args, CORE_ADDR sp,
513 int struct_return, CORE_ADDR struct_addr)
514 {
515 CORE_ADDR call_pc = (struct_return ? (bp_addr - 12) : (bp_addr - 8));
516
517 /* Set return address. */
518 regcache_cooked_write_unsigned (regcache, SPARC_O7_REGNUM, call_pc);
519
520 /* Set up function arguments. */
521 sp = sparc32_store_arguments (regcache, nargs, args, sp,
522 struct_return, struct_addr);
523
524 /* Allocate the 16-word window save area. */
525 sp -= 16 * 4;
526
527 /* Stack should be doubleword aligned at this point. */
528 gdb_assert (sp % 8 == 0);
529
530 /* Finally, update the stack pointer. */
531 regcache_cooked_write_unsigned (regcache, SPARC_SP_REGNUM, sp);
532
533 return sp;
534 }
535 \f
536
537 /* Use the program counter to determine the contents and size of a
538 breakpoint instruction. Return a pointer to a string of bytes that
539 encode a breakpoint instruction, store the length of the string in
540 *LEN and optionally adjust *PC to point to the correct memory
541 location for inserting the breakpoint. */
542
543 static const gdb_byte *
544 sparc_breakpoint_from_pc (CORE_ADDR *pc, int *len)
545 {
546 static const gdb_byte break_insn[] = { 0x91, 0xd0, 0x20, 0x01 };
547
548 *len = sizeof (break_insn);
549 return break_insn;
550 }
551 \f
552
553 /* Allocate and initialize a frame cache. */
554
555 static struct sparc_frame_cache *
556 sparc_alloc_frame_cache (void)
557 {
558 struct sparc_frame_cache *cache;
559 int i;
560
561 cache = FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache);
562
563 /* Base address. */
564 cache->base = 0;
565 cache->pc = 0;
566
567 /* Frameless until proven otherwise. */
568 cache->frameless_p = 1;
569
570 cache->struct_return_p = 0;
571
572 return cache;
573 }
574
575 /* GCC generates several well-known sequences of instructions at the begining
576 of each function prologue when compiling with -fstack-check. If one of
577 such sequences starts at START_PC, then return the address of the
578 instruction immediately past this sequence. Otherwise, return START_PC. */
579
580 static CORE_ADDR
581 sparc_skip_stack_check (const CORE_ADDR start_pc)
582 {
583 CORE_ADDR pc = start_pc;
584 unsigned long insn;
585 int offset_stack_checking_sequence = 0;
586
587 /* With GCC, all stack checking sequences begin with the same two
588 instructions. */
589
590 /* sethi <some immediate>,%g1 */
591 insn = sparc_fetch_instruction (pc);
592 pc = pc + 4;
593 if (!(X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 1))
594 return start_pc;
595
596 /* sub %sp, %g1, %g1 */
597 insn = sparc_fetch_instruction (pc);
598 pc = pc + 4;
599 if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn)
600 && X_RD (insn) == 1 && X_RS1 (insn) == 14 && X_RS2 (insn) == 1))
601 return start_pc;
602
603 insn = sparc_fetch_instruction (pc);
604 pc = pc + 4;
605
606 /* First possible sequence:
607 [first two instructions above]
608 clr [%g1 - some immediate] */
609
610 /* clr [%g1 - some immediate] */
611 if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn)
612 && X_RS1 (insn) == 1 && X_RD (insn) == 0)
613 {
614 /* Valid stack-check sequence, return the new PC. */
615 return pc;
616 }
617
618 /* Second possible sequence: A small number of probes.
619 [first two instructions above]
620 clr [%g1]
621 add %g1, -<some immediate>, %g1
622 clr [%g1]
623 [repeat the two instructions above any (small) number of times]
624 clr [%g1 - some immediate] */
625
626 /* clr [%g1] */
627 else if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn)
628 && X_RS1 (insn) == 1 && X_RD (insn) == 0)
629 {
630 while (1)
631 {
632 /* add %g1, -<some immediate>, %g1 */
633 insn = sparc_fetch_instruction (pc);
634 pc = pc + 4;
635 if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn)
636 && X_RS1 (insn) == 1 && X_RD (insn) == 1))
637 break;
638
639 /* clr [%g1] */
640 insn = sparc_fetch_instruction (pc);
641 pc = pc + 4;
642 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn)
643 && X_RD (insn) == 0 && X_RS1 (insn) == 1))
644 return start_pc;
645 }
646
647 /* clr [%g1 - some immediate] */
648 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn)
649 && X_RS1 (insn) == 1 && X_RD (insn) == 0))
650 return start_pc;
651
652 /* We found a valid stack-check sequence, return the new PC. */
653 return pc;
654 }
655
656 /* Third sequence: A probing loop.
657 [first two instructions above]
658 sethi <some immediate>, %g4
659 sub %g1, %g4, %g4
660 cmp %g1, %g4
661 be <disp>
662 add %g1, -<some immediate>, %g1
663 ba <disp>
664 clr [%g1]
665 clr [%g4 - some immediate] */
666
667 /* sethi <some immediate>, %g4 */
668 else if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4)
669 {
670 /* sub %g1, %g4, %g4 */
671 insn = sparc_fetch_instruction (pc);
672 pc = pc + 4;
673 if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn)
674 && X_RD (insn) == 4 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4))
675 return start_pc;
676
677 /* cmp %g1, %g4 */
678 insn = sparc_fetch_instruction (pc);
679 pc = pc + 4;
680 if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x14 && !X_I(insn)
681 && X_RD (insn) == 0 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4))
682 return start_pc;
683
684 /* be <disp> */
685 insn = sparc_fetch_instruction (pc);
686 pc = pc + 4;
687 if (!(X_OP (insn) == 0 && X_COND (insn) == 0x1))
688 return start_pc;
689
690 /* add %g1, -<some immediate>, %g1 */
691 insn = sparc_fetch_instruction (pc);
692 pc = pc + 4;
693 if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn)
694 && X_RS1 (insn) == 1 && X_RD (insn) == 1))
695 return start_pc;
696
697 /* ba <disp> */
698 insn = sparc_fetch_instruction (pc);
699 pc = pc + 4;
700 if (!(X_OP (insn) == 0 && X_COND (insn) == 0x8))
701 return start_pc;
702
703 /* clr [%g1] */
704 insn = sparc_fetch_instruction (pc);
705 pc = pc + 4;
706 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn)
707 && X_RD (insn) == 0 && X_RS1 (insn) == 1))
708 return start_pc;
709
710 /* clr [%g4 - some immediate] */
711 insn = sparc_fetch_instruction (pc);
712 pc = pc + 4;
713 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn)
714 && X_RS1 (insn) == 4 && X_RD (insn) == 0))
715 return start_pc;
716
717 /* We found a valid stack-check sequence, return the new PC. */
718 return pc;
719 }
720
721 /* No stack check code in our prologue, return the start_pc. */
722 return start_pc;
723 }
724
725 CORE_ADDR
726 sparc_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc,
727 struct sparc_frame_cache *cache)
728 {
729 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
730 unsigned long insn;
731 int offset = 0;
732 int dest = -1;
733
734 pc = sparc_skip_stack_check (pc);
735
736 if (current_pc <= pc)
737 return current_pc;
738
739 /* We have to handle to "Procedure Linkage Table" (PLT) special. On
740 SPARC the linker usually defines a symbol (typically
741 _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section.
742 This symbol makes us end up here with PC pointing at the start of
743 the PLT and CURRENT_PC probably pointing at a PLT entry. If we
744 would do our normal prologue analysis, we would probably conclude
745 that we've got a frame when in reality we don't, since the
746 dynamic linker patches up the first PLT with some code that
747 starts with a SAVE instruction. Patch up PC such that it points
748 at the start of our PLT entry. */
749 if (tdep->plt_entry_size > 0 && in_plt_section (current_pc, NULL))
750 pc = current_pc - ((current_pc - pc) % tdep->plt_entry_size);
751
752 insn = sparc_fetch_instruction (pc);
753
754 /* Recognize a SETHI insn and record its destination. */
755 if (X_OP (insn) == 0 && X_OP2 (insn) == 0x04)
756 {
757 dest = X_RD (insn);
758 offset += 4;
759
760 insn = sparc_fetch_instruction (pc + 4);
761 }
762
763 /* Allow for an arithmetic operation on DEST or %g1. */
764 if (X_OP (insn) == 2 && X_I (insn)
765 && (X_RD (insn) == 1 || X_RD (insn) == dest))
766 {
767 offset += 4;
768
769 insn = sparc_fetch_instruction (pc + 8);
770 }
771
772 /* Check for the SAVE instruction that sets up the frame. */
773 if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c)
774 {
775 cache->frameless_p = 0;
776 return pc + offset + 4;
777 }
778
779 return pc;
780 }
781
782 static CORE_ADDR
783 sparc_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
784 {
785 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
786 return frame_unwind_register_unsigned (next_frame, tdep->pc_regnum);
787 }
788
789 /* Return PC of first real instruction of the function starting at
790 START_PC. */
791
792 static CORE_ADDR
793 sparc32_skip_prologue (CORE_ADDR start_pc)
794 {
795 struct symtab_and_line sal;
796 CORE_ADDR func_start, func_end;
797 struct sparc_frame_cache cache;
798
799 /* This is the preferred method, find the end of the prologue by
800 using the debugging information. */
801 if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end))
802 {
803 sal = find_pc_line (func_start, 0);
804
805 if (sal.end < func_end
806 && start_pc <= sal.end)
807 return sal.end;
808 }
809
810 start_pc = sparc_analyze_prologue (start_pc, 0xffffffffUL, &cache);
811
812 /* The psABI says that "Although the first 6 words of arguments
813 reside in registers, the standard stack frame reserves space for
814 them.". It also suggests that a function may use that space to
815 "write incoming arguments 0 to 5" into that space, and that's
816 indeed what GCC seems to be doing. In that case GCC will
817 generate debug information that points to the stack slots instead
818 of the registers, so we should consider the instructions that
819 write out these incoming arguments onto the stack. Of course we
820 only need to do this if we have a stack frame. */
821
822 while (!cache.frameless_p)
823 {
824 unsigned long insn = sparc_fetch_instruction (start_pc);
825
826 /* Recognize instructions that store incoming arguments in
827 %i0...%i5 into the corresponding stack slot. */
828 if (X_OP (insn) == 3 && (X_OP3 (insn) & 0x3c) == 0x04 && X_I (insn)
829 && (X_RD (insn) >= 24 && X_RD (insn) <= 29) && X_RS1 (insn) == 30
830 && X_SIMM13 (insn) == 68 + (X_RD (insn) - 24) * 4)
831 {
832 start_pc += 4;
833 continue;
834 }
835
836 break;
837 }
838
839 return start_pc;
840 }
841
842 /* Normal frames. */
843
844 struct sparc_frame_cache *
845 sparc_frame_cache (struct frame_info *next_frame, void **this_cache)
846 {
847 struct sparc_frame_cache *cache;
848
849 if (*this_cache)
850 return *this_cache;
851
852 cache = sparc_alloc_frame_cache ();
853 *this_cache = cache;
854
855 cache->pc = frame_func_unwind (next_frame, NORMAL_FRAME);
856 if (cache->pc != 0)
857 sparc_analyze_prologue (cache->pc, frame_pc_unwind (next_frame), cache);
858
859 if (cache->frameless_p)
860 {
861 /* This function is frameless, so %fp (%i6) holds the frame
862 pointer for our calling frame. Use %sp (%o6) as this frame's
863 base address. */
864 cache->base =
865 frame_unwind_register_unsigned (next_frame, SPARC_SP_REGNUM);
866 }
867 else
868 {
869 /* For normal frames, %fp (%i6) holds the frame pointer, the
870 base address for the current stack frame. */
871 cache->base =
872 frame_unwind_register_unsigned (next_frame, SPARC_FP_REGNUM);
873 }
874
875 if (cache->base & 1)
876 cache->base += BIAS;
877
878 return cache;
879 }
880
881 static int
882 sparc32_struct_return_from_sym (struct symbol *sym)
883 {
884 struct type *type = check_typedef (SYMBOL_TYPE (sym));
885 enum type_code code = TYPE_CODE (type);
886
887 if (code == TYPE_CODE_FUNC || code == TYPE_CODE_METHOD)
888 {
889 type = check_typedef (TYPE_TARGET_TYPE (type));
890 if (sparc_structure_or_union_p (type)
891 || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16))
892 return 1;
893 }
894
895 return 0;
896 }
897
898 struct sparc_frame_cache *
899 sparc32_frame_cache (struct frame_info *next_frame, void **this_cache)
900 {
901 struct sparc_frame_cache *cache;
902 struct symbol *sym;
903
904 if (*this_cache)
905 return *this_cache;
906
907 cache = sparc_frame_cache (next_frame, this_cache);
908
909 sym = find_pc_function (cache->pc);
910 if (sym)
911 {
912 cache->struct_return_p = sparc32_struct_return_from_sym (sym);
913 }
914 else
915 {
916 /* There is no debugging information for this function to
917 help us determine whether this function returns a struct
918 or not. So we rely on another heuristic which is to check
919 the instruction at the return address and see if this is
920 an "unimp" instruction. If it is, then it is a struct-return
921 function. */
922 CORE_ADDR pc;
923 int regnum = cache->frameless_p ? SPARC_O7_REGNUM : SPARC_I7_REGNUM;
924
925 pc = frame_unwind_register_unsigned (next_frame, regnum) + 8;
926 if (sparc_is_unimp_insn (pc))
927 cache->struct_return_p = 1;
928 }
929
930 return cache;
931 }
932
933 static void
934 sparc32_frame_this_id (struct frame_info *next_frame, void **this_cache,
935 struct frame_id *this_id)
936 {
937 struct sparc_frame_cache *cache =
938 sparc32_frame_cache (next_frame, this_cache);
939
940 /* This marks the outermost frame. */
941 if (cache->base == 0)
942 return;
943
944 (*this_id) = frame_id_build (cache->base, cache->pc);
945 }
946
947 static void
948 sparc32_frame_prev_register (struct frame_info *next_frame, void **this_cache,
949 int regnum, int *optimizedp,
950 enum lval_type *lvalp, CORE_ADDR *addrp,
951 int *realnump, gdb_byte *valuep)
952 {
953 struct sparc_frame_cache *cache =
954 sparc32_frame_cache (next_frame, this_cache);
955
956 if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM)
957 {
958 *optimizedp = 0;
959 *lvalp = not_lval;
960 *addrp = 0;
961 *realnump = -1;
962 if (valuep)
963 {
964 CORE_ADDR pc = (regnum == SPARC32_NPC_REGNUM) ? 4 : 0;
965
966 /* If this functions has a Structure, Union or
967 Quad-Precision return value, we have to skip the UNIMP
968 instruction that encodes the size of the structure. */
969 if (cache->struct_return_p)
970 pc += 4;
971
972 regnum = cache->frameless_p ? SPARC_O7_REGNUM : SPARC_I7_REGNUM;
973 pc += frame_unwind_register_unsigned (next_frame, regnum) + 8;
974 store_unsigned_integer (valuep, 4, pc);
975 }
976 return;
977 }
978
979 /* Handle StackGhost. */
980 {
981 ULONGEST wcookie = sparc_fetch_wcookie ();
982
983 if (wcookie != 0 && !cache->frameless_p && regnum == SPARC_I7_REGNUM)
984 {
985 *optimizedp = 0;
986 *lvalp = not_lval;
987 *addrp = 0;
988 *realnump = -1;
989 if (valuep)
990 {
991 CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4;
992 ULONGEST i7;
993
994 /* Read the value in from memory. */
995 i7 = get_frame_memory_unsigned (next_frame, addr, 4);
996 store_unsigned_integer (valuep, 4, i7 ^ wcookie);
997 }
998 return;
999 }
1000 }
1001
1002 /* The previous frame's `local' and `in' registers have been saved
1003 in the register save area. */
1004 if (!cache->frameless_p
1005 && regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM)
1006 {
1007 *optimizedp = 0;
1008 *lvalp = lval_memory;
1009 *addrp = cache->base + (regnum - SPARC_L0_REGNUM) * 4;
1010 *realnump = -1;
1011 if (valuep)
1012 {
1013 struct gdbarch *gdbarch = get_frame_arch (next_frame);
1014
1015 /* Read the value in from memory. */
1016 read_memory (*addrp, valuep, register_size (gdbarch, regnum));
1017 }
1018 return;
1019 }
1020
1021 /* The previous frame's `out' registers are accessable as the
1022 current frame's `in' registers. */
1023 if (!cache->frameless_p
1024 && regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O7_REGNUM)
1025 regnum += (SPARC_I0_REGNUM - SPARC_O0_REGNUM);
1026
1027 *optimizedp = 0;
1028 *lvalp = lval_register;
1029 *addrp = 0;
1030 *realnump = regnum;
1031 if (valuep)
1032 frame_unwind_register (next_frame, (*realnump), valuep);
1033 }
1034
1035 static const struct frame_unwind sparc32_frame_unwind =
1036 {
1037 NORMAL_FRAME,
1038 sparc32_frame_this_id,
1039 sparc32_frame_prev_register
1040 };
1041
1042 static const struct frame_unwind *
1043 sparc32_frame_sniffer (struct frame_info *next_frame)
1044 {
1045 return &sparc32_frame_unwind;
1046 }
1047 \f
1048
1049 static CORE_ADDR
1050 sparc32_frame_base_address (struct frame_info *next_frame, void **this_cache)
1051 {
1052 struct sparc_frame_cache *cache =
1053 sparc32_frame_cache (next_frame, this_cache);
1054
1055 return cache->base;
1056 }
1057
1058 static const struct frame_base sparc32_frame_base =
1059 {
1060 &sparc32_frame_unwind,
1061 sparc32_frame_base_address,
1062 sparc32_frame_base_address,
1063 sparc32_frame_base_address
1064 };
1065
1066 static struct frame_id
1067 sparc_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
1068 {
1069 CORE_ADDR sp;
1070
1071 sp = frame_unwind_register_unsigned (next_frame, SPARC_SP_REGNUM);
1072 if (sp & 1)
1073 sp += BIAS;
1074 return frame_id_build (sp, frame_pc_unwind (next_frame));
1075 }
1076 \f
1077
1078 /* Extract from an array REGBUF containing the (raw) register state, a
1079 function return value of TYPE, and copy that into VALBUF. */
1080
1081 static void
1082 sparc32_extract_return_value (struct type *type, struct regcache *regcache,
1083 gdb_byte *valbuf)
1084 {
1085 int len = TYPE_LENGTH (type);
1086 gdb_byte buf[8];
1087
1088 gdb_assert (!sparc_structure_or_union_p (type));
1089 gdb_assert (!(sparc_floating_p (type) && len == 16));
1090
1091 if (sparc_floating_p (type))
1092 {
1093 /* Floating return values. */
1094 regcache_cooked_read (regcache, SPARC_F0_REGNUM, buf);
1095 if (len > 4)
1096 regcache_cooked_read (regcache, SPARC_F1_REGNUM, buf + 4);
1097 memcpy (valbuf, buf, len);
1098 }
1099 else
1100 {
1101 /* Integral and pointer return values. */
1102 gdb_assert (sparc_integral_or_pointer_p (type));
1103
1104 regcache_cooked_read (regcache, SPARC_O0_REGNUM, buf);
1105 if (len > 4)
1106 {
1107 regcache_cooked_read (regcache, SPARC_O1_REGNUM, buf + 4);
1108 gdb_assert (len == 8);
1109 memcpy (valbuf, buf, 8);
1110 }
1111 else
1112 {
1113 /* Just stripping off any unused bytes should preserve the
1114 signed-ness just fine. */
1115 memcpy (valbuf, buf + 4 - len, len);
1116 }
1117 }
1118 }
1119
1120 /* Write into the appropriate registers a function return value stored
1121 in VALBUF of type TYPE. */
1122
1123 static void
1124 sparc32_store_return_value (struct type *type, struct regcache *regcache,
1125 const gdb_byte *valbuf)
1126 {
1127 int len = TYPE_LENGTH (type);
1128 gdb_byte buf[8];
1129
1130 gdb_assert (!sparc_structure_or_union_p (type));
1131 gdb_assert (!(sparc_floating_p (type) && len == 16));
1132
1133 if (sparc_floating_p (type))
1134 {
1135 /* Floating return values. */
1136 memcpy (buf, valbuf, len);
1137 regcache_cooked_write (regcache, SPARC_F0_REGNUM, buf);
1138 if (len > 4)
1139 regcache_cooked_write (regcache, SPARC_F1_REGNUM, buf + 4);
1140 }
1141 else
1142 {
1143 /* Integral and pointer return values. */
1144 gdb_assert (sparc_integral_or_pointer_p (type));
1145
1146 if (len > 4)
1147 {
1148 gdb_assert (len == 8);
1149 memcpy (buf, valbuf, 8);
1150 regcache_cooked_write (regcache, SPARC_O1_REGNUM, buf + 4);
1151 }
1152 else
1153 {
1154 /* ??? Do we need to do any sign-extension here? */
1155 memcpy (buf + 4 - len, valbuf, len);
1156 }
1157 regcache_cooked_write (regcache, SPARC_O0_REGNUM, buf);
1158 }
1159 }
1160
1161 static enum return_value_convention
1162 sparc32_return_value (struct gdbarch *gdbarch, struct type *type,
1163 struct regcache *regcache, gdb_byte *readbuf,
1164 const gdb_byte *writebuf)
1165 {
1166 /* The psABI says that "...every stack frame reserves the word at
1167 %fp+64. If a function returns a structure, union, or
1168 quad-precision value, this word should hold the address of the
1169 object into which the return value should be copied." This
1170 guarantees that we can always find the return value, not just
1171 before the function returns. */
1172
1173 if (sparc_structure_or_union_p (type)
1174 || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16))
1175 {
1176 if (readbuf)
1177 {
1178 ULONGEST sp;
1179 CORE_ADDR addr;
1180
1181 regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp);
1182 addr = read_memory_unsigned_integer (sp + 64, 4);
1183 read_memory (addr, readbuf, TYPE_LENGTH (type));
1184 }
1185
1186 return RETURN_VALUE_ABI_PRESERVES_ADDRESS;
1187 }
1188
1189 if (readbuf)
1190 sparc32_extract_return_value (type, regcache, readbuf);
1191 if (writebuf)
1192 sparc32_store_return_value (type, regcache, writebuf);
1193
1194 return RETURN_VALUE_REGISTER_CONVENTION;
1195 }
1196
1197 static int
1198 sparc32_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type)
1199 {
1200 return (sparc_structure_or_union_p (type)
1201 || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16));
1202 }
1203
1204 static int
1205 sparc32_dwarf2_struct_return_p (struct frame_info *next_frame)
1206 {
1207 CORE_ADDR pc = frame_unwind_address_in_block (next_frame, NORMAL_FRAME);
1208 struct symbol *sym = find_pc_function (pc);
1209
1210 if (sym)
1211 return sparc32_struct_return_from_sym (sym);
1212 return 0;
1213 }
1214
1215 static void
1216 sparc32_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
1217 struct dwarf2_frame_state_reg *reg,
1218 struct frame_info *next_frame)
1219 {
1220 int off;
1221
1222 switch (regnum)
1223 {
1224 case SPARC_G0_REGNUM:
1225 /* Since %g0 is always zero, there is no point in saving it, and
1226 people will be inclined omit it from the CFI. Make sure we
1227 don't warn about that. */
1228 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
1229 break;
1230 case SPARC_SP_REGNUM:
1231 reg->how = DWARF2_FRAME_REG_CFA;
1232 break;
1233 case SPARC32_PC_REGNUM:
1234 case SPARC32_NPC_REGNUM:
1235 reg->how = DWARF2_FRAME_REG_RA_OFFSET;
1236 off = 8;
1237 if (sparc32_dwarf2_struct_return_p (next_frame))
1238 off += 4;
1239 if (regnum == SPARC32_NPC_REGNUM)
1240 off += 4;
1241 reg->loc.offset = off;
1242 break;
1243 }
1244 }
1245
1246 \f
1247 /* The SPARC Architecture doesn't have hardware single-step support,
1248 and most operating systems don't implement it either, so we provide
1249 software single-step mechanism. */
1250
1251 static CORE_ADDR
1252 sparc_analyze_control_transfer (struct gdbarch *arch,
1253 CORE_ADDR pc, CORE_ADDR *npc)
1254 {
1255 unsigned long insn = sparc_fetch_instruction (pc);
1256 int conditional_p = X_COND (insn) & 0x7;
1257 int branch_p = 0;
1258 long offset = 0; /* Must be signed for sign-extend. */
1259
1260 if (X_OP (insn) == 0 && X_OP2 (insn) == 3 && (insn & 0x1000000) == 0)
1261 {
1262 /* Branch on Integer Register with Prediction (BPr). */
1263 branch_p = 1;
1264 conditional_p = 1;
1265 }
1266 else if (X_OP (insn) == 0 && X_OP2 (insn) == 6)
1267 {
1268 /* Branch on Floating-Point Condition Codes (FBfcc). */
1269 branch_p = 1;
1270 offset = 4 * X_DISP22 (insn);
1271 }
1272 else if (X_OP (insn) == 0 && X_OP2 (insn) == 5)
1273 {
1274 /* Branch on Floating-Point Condition Codes with Prediction
1275 (FBPfcc). */
1276 branch_p = 1;
1277 offset = 4 * X_DISP19 (insn);
1278 }
1279 else if (X_OP (insn) == 0 && X_OP2 (insn) == 2)
1280 {
1281 /* Branch on Integer Condition Codes (Bicc). */
1282 branch_p = 1;
1283 offset = 4 * X_DISP22 (insn);
1284 }
1285 else if (X_OP (insn) == 0 && X_OP2 (insn) == 1)
1286 {
1287 /* Branch on Integer Condition Codes with Prediction (BPcc). */
1288 branch_p = 1;
1289 offset = 4 * X_DISP19 (insn);
1290 }
1291 else if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3a)
1292 {
1293 /* Trap instruction (TRAP). */
1294 return gdbarch_tdep (arch)->step_trap (insn);
1295 }
1296
1297 /* FIXME: Handle DONE and RETRY instructions. */
1298
1299 if (branch_p)
1300 {
1301 if (conditional_p)
1302 {
1303 /* For conditional branches, return nPC + 4 iff the annul
1304 bit is 1. */
1305 return (X_A (insn) ? *npc + 4 : 0);
1306 }
1307 else
1308 {
1309 /* For unconditional branches, return the target if its
1310 specified condition is "always" and return nPC + 4 if the
1311 condition is "never". If the annul bit is 1, set *NPC to
1312 zero. */
1313 if (X_COND (insn) == 0x0)
1314 pc = *npc, offset = 4;
1315 if (X_A (insn))
1316 *npc = 0;
1317
1318 gdb_assert (offset != 0);
1319 return pc + offset;
1320 }
1321 }
1322
1323 return 0;
1324 }
1325
1326 static CORE_ADDR
1327 sparc_step_trap (unsigned long insn)
1328 {
1329 return 0;
1330 }
1331
1332 int
1333 sparc_software_single_step (enum target_signal sig, int insert_breakpoints_p)
1334 {
1335 struct gdbarch *arch = current_gdbarch;
1336 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
1337 CORE_ADDR npc, nnpc;
1338
1339 if (insert_breakpoints_p)
1340 {
1341 CORE_ADDR pc, orig_npc;
1342
1343 pc = sparc_address_from_register (tdep->pc_regnum);
1344 orig_npc = npc = sparc_address_from_register (tdep->npc_regnum);
1345
1346 /* Analyze the instruction at PC. */
1347 nnpc = sparc_analyze_control_transfer (arch, pc, &npc);
1348 if (npc != 0)
1349 insert_single_step_breakpoint (npc);
1350
1351 if (nnpc != 0)
1352 insert_single_step_breakpoint (nnpc);
1353
1354 /* Assert that we have set at least one breakpoint, and that
1355 they're not set at the same spot - unless we're going
1356 from here straight to NULL, i.e. a call or jump to 0. */
1357 gdb_assert (npc != 0 || nnpc != 0 || orig_npc == 0);
1358 gdb_assert (nnpc != npc || orig_npc == 0);
1359 }
1360 else
1361 remove_single_step_breakpoints ();
1362
1363 return 1;
1364 }
1365
1366 static void
1367 sparc_write_pc (CORE_ADDR pc, ptid_t ptid)
1368 {
1369 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1370
1371 write_register_pid (tdep->pc_regnum, pc, ptid);
1372 write_register_pid (tdep->npc_regnum, pc + 4, ptid);
1373 }
1374 \f
1375 /* Unglobalize NAME. */
1376
1377 char *
1378 sparc_stabs_unglobalize_name (char *name)
1379 {
1380 /* The Sun compilers (Sun ONE Studio, Forte Developer, Sun WorkShop,
1381 SunPRO) convert file static variables into global values, a
1382 process known as globalization. In order to do this, the
1383 compiler will create a unique prefix and prepend it to each file
1384 static variable. For static variables within a function, this
1385 globalization prefix is followed by the function name (nested
1386 static variables within a function are supposed to generate a
1387 warning message, and are left alone). The procedure is
1388 documented in the Stabs Interface Manual, which is distrubuted
1389 with the compilers, although version 4.0 of the manual seems to
1390 be incorrect in some places, at least for SPARC. The
1391 globalization prefix is encoded into an N_OPT stab, with the form
1392 "G=<prefix>". The globalization prefix always seems to start
1393 with a dollar sign '$'; a dot '.' is used as a seperator. So we
1394 simply strip everything up until the last dot. */
1395
1396 if (name[0] == '$')
1397 {
1398 char *p = strrchr (name, '.');
1399 if (p)
1400 return p + 1;
1401 }
1402
1403 return name;
1404 }
1405 \f
1406
1407 /* Return the appropriate register set for the core section identified
1408 by SECT_NAME and SECT_SIZE. */
1409
1410 const struct regset *
1411 sparc_regset_from_core_section (struct gdbarch *gdbarch,
1412 const char *sect_name, size_t sect_size)
1413 {
1414 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1415
1416 if (strcmp (sect_name, ".reg") == 0 && sect_size >= tdep->sizeof_gregset)
1417 return tdep->gregset;
1418
1419 if (strcmp (sect_name, ".reg2") == 0 && sect_size >= tdep->sizeof_fpregset)
1420 return tdep->fpregset;
1421
1422 return NULL;
1423 }
1424 \f
1425
1426 static struct gdbarch *
1427 sparc32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1428 {
1429 struct gdbarch_tdep *tdep;
1430 struct gdbarch *gdbarch;
1431
1432 /* If there is already a candidate, use it. */
1433 arches = gdbarch_list_lookup_by_info (arches, &info);
1434 if (arches != NULL)
1435 return arches->gdbarch;
1436
1437 /* Allocate space for the new architecture. */
1438 tdep = XMALLOC (struct gdbarch_tdep);
1439 gdbarch = gdbarch_alloc (&info, tdep);
1440
1441 tdep->pc_regnum = SPARC32_PC_REGNUM;
1442 tdep->npc_regnum = SPARC32_NPC_REGNUM;
1443 tdep->gregset = NULL;
1444 tdep->sizeof_gregset = 0;
1445 tdep->fpregset = NULL;
1446 tdep->sizeof_fpregset = 0;
1447 tdep->plt_entry_size = 0;
1448 tdep->step_trap = sparc_step_trap;
1449
1450 set_gdbarch_long_double_bit (gdbarch, 128);
1451 set_gdbarch_long_double_format (gdbarch, floatformats_sparc_quad);
1452
1453 set_gdbarch_num_regs (gdbarch, SPARC32_NUM_REGS);
1454 set_gdbarch_register_name (gdbarch, sparc32_register_name);
1455 set_gdbarch_register_type (gdbarch, sparc32_register_type);
1456 set_gdbarch_num_pseudo_regs (gdbarch, SPARC32_NUM_PSEUDO_REGS);
1457 set_gdbarch_pseudo_register_read (gdbarch, sparc32_pseudo_register_read);
1458 set_gdbarch_pseudo_register_write (gdbarch, sparc32_pseudo_register_write);
1459
1460 /* Register numbers of various important registers. */
1461 set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM); /* %sp */
1462 set_gdbarch_pc_regnum (gdbarch, SPARC32_PC_REGNUM); /* %pc */
1463 set_gdbarch_fp0_regnum (gdbarch, SPARC_F0_REGNUM); /* %f0 */
1464
1465 /* Call dummy code. */
1466 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
1467 set_gdbarch_push_dummy_code (gdbarch, sparc32_push_dummy_code);
1468 set_gdbarch_push_dummy_call (gdbarch, sparc32_push_dummy_call);
1469
1470 set_gdbarch_return_value (gdbarch, sparc32_return_value);
1471 set_gdbarch_stabs_argument_has_addr
1472 (gdbarch, sparc32_stabs_argument_has_addr);
1473
1474 set_gdbarch_skip_prologue (gdbarch, sparc32_skip_prologue);
1475
1476 /* Stack grows downward. */
1477 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1478
1479 set_gdbarch_breakpoint_from_pc (gdbarch, sparc_breakpoint_from_pc);
1480
1481 set_gdbarch_frame_args_skip (gdbarch, 8);
1482
1483 set_gdbarch_print_insn (gdbarch, print_insn_sparc);
1484
1485 set_gdbarch_software_single_step (gdbarch, sparc_software_single_step);
1486 set_gdbarch_write_pc (gdbarch, sparc_write_pc);
1487
1488 set_gdbarch_unwind_dummy_id (gdbarch, sparc_unwind_dummy_id);
1489
1490 set_gdbarch_unwind_pc (gdbarch, sparc_unwind_pc);
1491
1492 frame_base_set_default (gdbarch, &sparc32_frame_base);
1493
1494 /* Hook in the DWARF CFI frame unwinder. */
1495 dwarf2_frame_set_init_reg (gdbarch, sparc32_dwarf2_frame_init_reg);
1496 /* FIXME: kettenis/20050423: Don't enable the unwinder until the
1497 StackGhost issues have been resolved. */
1498
1499 /* Hook in ABI-specific overrides, if they have been registered. */
1500 gdbarch_init_osabi (info, gdbarch);
1501
1502 frame_unwind_append_sniffer (gdbarch, sparc32_frame_sniffer);
1503
1504 /* If we have register sets, enable the generic core file support. */
1505 if (tdep->gregset)
1506 set_gdbarch_regset_from_core_section (gdbarch,
1507 sparc_regset_from_core_section);
1508
1509 return gdbarch;
1510 }
1511 \f
1512 /* Helper functions for dealing with register windows. */
1513
1514 void
1515 sparc_supply_rwindow (struct regcache *regcache, CORE_ADDR sp, int regnum)
1516 {
1517 int offset = 0;
1518 gdb_byte buf[8];
1519 int i;
1520
1521 if (sp & 1)
1522 {
1523 /* Registers are 64-bit. */
1524 sp += BIAS;
1525
1526 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1527 {
1528 if (regnum == i || regnum == -1)
1529 {
1530 target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8);
1531
1532 /* Handle StackGhost. */
1533 if (i == SPARC_I7_REGNUM)
1534 {
1535 ULONGEST wcookie = sparc_fetch_wcookie ();
1536 ULONGEST i7 = extract_unsigned_integer (buf + offset, 8);
1537
1538 store_unsigned_integer (buf + offset, 8, i7 ^ wcookie);
1539 }
1540
1541 regcache_raw_supply (regcache, i, buf);
1542 }
1543 }
1544 }
1545 else
1546 {
1547 /* Registers are 32-bit. Toss any sign-extension of the stack
1548 pointer. */
1549 sp &= 0xffffffffUL;
1550
1551 /* Clear out the top half of the temporary buffer, and put the
1552 register value in the bottom half if we're in 64-bit mode. */
1553 if (gdbarch_ptr_bit (current_gdbarch) == 64)
1554 {
1555 memset (buf, 0, 4);
1556 offset = 4;
1557 }
1558
1559 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1560 {
1561 if (regnum == i || regnum == -1)
1562 {
1563 target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 4),
1564 buf + offset, 4);
1565
1566 /* Handle StackGhost. */
1567 if (i == SPARC_I7_REGNUM)
1568 {
1569 ULONGEST wcookie = sparc_fetch_wcookie ();
1570 ULONGEST i7 = extract_unsigned_integer (buf + offset, 4);
1571
1572 store_unsigned_integer (buf + offset, 4, i7 ^ wcookie);
1573 }
1574
1575 regcache_raw_supply (regcache, i, buf);
1576 }
1577 }
1578 }
1579 }
1580
1581 void
1582 sparc_collect_rwindow (const struct regcache *regcache,
1583 CORE_ADDR sp, int regnum)
1584 {
1585 int offset = 0;
1586 gdb_byte buf[8];
1587 int i;
1588
1589 if (sp & 1)
1590 {
1591 /* Registers are 64-bit. */
1592 sp += BIAS;
1593
1594 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1595 {
1596 if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i)
1597 {
1598 regcache_raw_collect (regcache, i, buf);
1599
1600 /* Handle StackGhost. */
1601 if (i == SPARC_I7_REGNUM)
1602 {
1603 ULONGEST wcookie = sparc_fetch_wcookie ();
1604 ULONGEST i7 = extract_unsigned_integer (buf + offset, 8);
1605
1606 store_unsigned_integer (buf, 8, i7 ^ wcookie);
1607 }
1608
1609 target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8);
1610 }
1611 }
1612 }
1613 else
1614 {
1615 /* Registers are 32-bit. Toss any sign-extension of the stack
1616 pointer. */
1617 sp &= 0xffffffffUL;
1618
1619 /* Only use the bottom half if we're in 64-bit mode. */
1620 if (gdbarch_ptr_bit (current_gdbarch) == 64)
1621 offset = 4;
1622
1623 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1624 {
1625 if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i)
1626 {
1627 regcache_raw_collect (regcache, i, buf);
1628
1629 /* Handle StackGhost. */
1630 if (i == SPARC_I7_REGNUM)
1631 {
1632 ULONGEST wcookie = sparc_fetch_wcookie ();
1633 ULONGEST i7 = extract_unsigned_integer (buf + offset, 4);
1634
1635 store_unsigned_integer (buf + offset, 4, i7 ^ wcookie);
1636 }
1637
1638 target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 4),
1639 buf + offset, 4);
1640 }
1641 }
1642 }
1643 }
1644
1645 /* Helper functions for dealing with register sets. */
1646
1647 void
1648 sparc32_supply_gregset (const struct sparc_gregset *gregset,
1649 struct regcache *regcache,
1650 int regnum, const void *gregs)
1651 {
1652 const gdb_byte *regs = gregs;
1653 int i;
1654
1655 if (regnum == SPARC32_PSR_REGNUM || regnum == -1)
1656 regcache_raw_supply (regcache, SPARC32_PSR_REGNUM,
1657 regs + gregset->r_psr_offset);
1658
1659 if (regnum == SPARC32_PC_REGNUM || regnum == -1)
1660 regcache_raw_supply (regcache, SPARC32_PC_REGNUM,
1661 regs + gregset->r_pc_offset);
1662
1663 if (regnum == SPARC32_NPC_REGNUM || regnum == -1)
1664 regcache_raw_supply (regcache, SPARC32_NPC_REGNUM,
1665 regs + gregset->r_npc_offset);
1666
1667 if (regnum == SPARC32_Y_REGNUM || regnum == -1)
1668 regcache_raw_supply (regcache, SPARC32_Y_REGNUM,
1669 regs + gregset->r_y_offset);
1670
1671 if (regnum == SPARC_G0_REGNUM || regnum == -1)
1672 regcache_raw_supply (regcache, SPARC_G0_REGNUM, NULL);
1673
1674 if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1)
1675 {
1676 int offset = gregset->r_g1_offset;
1677
1678 for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++)
1679 {
1680 if (regnum == i || regnum == -1)
1681 regcache_raw_supply (regcache, i, regs + offset);
1682 offset += 4;
1683 }
1684 }
1685
1686 if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1)
1687 {
1688 /* Not all of the register set variants include Locals and
1689 Inputs. For those that don't, we read them off the stack. */
1690 if (gregset->r_l0_offset == -1)
1691 {
1692 ULONGEST sp;
1693
1694 regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp);
1695 sparc_supply_rwindow (regcache, sp, regnum);
1696 }
1697 else
1698 {
1699 int offset = gregset->r_l0_offset;
1700
1701 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1702 {
1703 if (regnum == i || regnum == -1)
1704 regcache_raw_supply (regcache, i, regs + offset);
1705 offset += 4;
1706 }
1707 }
1708 }
1709 }
1710
1711 void
1712 sparc32_collect_gregset (const struct sparc_gregset *gregset,
1713 const struct regcache *regcache,
1714 int regnum, void *gregs)
1715 {
1716 gdb_byte *regs = gregs;
1717 int i;
1718
1719 if (regnum == SPARC32_PSR_REGNUM || regnum == -1)
1720 regcache_raw_collect (regcache, SPARC32_PSR_REGNUM,
1721 regs + gregset->r_psr_offset);
1722
1723 if (regnum == SPARC32_PC_REGNUM || regnum == -1)
1724 regcache_raw_collect (regcache, SPARC32_PC_REGNUM,
1725 regs + gregset->r_pc_offset);
1726
1727 if (regnum == SPARC32_NPC_REGNUM || regnum == -1)
1728 regcache_raw_collect (regcache, SPARC32_NPC_REGNUM,
1729 regs + gregset->r_npc_offset);
1730
1731 if (regnum == SPARC32_Y_REGNUM || regnum == -1)
1732 regcache_raw_collect (regcache, SPARC32_Y_REGNUM,
1733 regs + gregset->r_y_offset);
1734
1735 if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1)
1736 {
1737 int offset = gregset->r_g1_offset;
1738
1739 /* %g0 is always zero. */
1740 for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++)
1741 {
1742 if (regnum == i || regnum == -1)
1743 regcache_raw_collect (regcache, i, regs + offset);
1744 offset += 4;
1745 }
1746 }
1747
1748 if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1)
1749 {
1750 /* Not all of the register set variants include Locals and
1751 Inputs. For those that don't, we read them off the stack. */
1752 if (gregset->r_l0_offset != -1)
1753 {
1754 int offset = gregset->r_l0_offset;
1755
1756 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1757 {
1758 if (regnum == i || regnum == -1)
1759 regcache_raw_collect (regcache, i, regs + offset);
1760 offset += 4;
1761 }
1762 }
1763 }
1764 }
1765
1766 void
1767 sparc32_supply_fpregset (struct regcache *regcache,
1768 int regnum, const void *fpregs)
1769 {
1770 const gdb_byte *regs = fpregs;
1771 int i;
1772
1773 for (i = 0; i < 32; i++)
1774 {
1775 if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1)
1776 regcache_raw_supply (regcache, SPARC_F0_REGNUM + i, regs + (i * 4));
1777 }
1778
1779 if (regnum == SPARC32_FSR_REGNUM || regnum == -1)
1780 regcache_raw_supply (regcache, SPARC32_FSR_REGNUM, regs + (32 * 4) + 4);
1781 }
1782
1783 void
1784 sparc32_collect_fpregset (const struct regcache *regcache,
1785 int regnum, void *fpregs)
1786 {
1787 gdb_byte *regs = fpregs;
1788 int i;
1789
1790 for (i = 0; i < 32; i++)
1791 {
1792 if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1)
1793 regcache_raw_collect (regcache, SPARC_F0_REGNUM + i, regs + (i * 4));
1794 }
1795
1796 if (regnum == SPARC32_FSR_REGNUM || regnum == -1)
1797 regcache_raw_collect (regcache, SPARC32_FSR_REGNUM, regs + (32 * 4) + 4);
1798 }
1799 \f
1800
1801 /* SunOS 4. */
1802
1803 /* From <machine/reg.h>. */
1804 const struct sparc_gregset sparc32_sunos4_gregset =
1805 {
1806 0 * 4, /* %psr */
1807 1 * 4, /* %pc */
1808 2 * 4, /* %npc */
1809 3 * 4, /* %y */
1810 -1, /* %wim */
1811 -1, /* %tbr */
1812 4 * 4, /* %g1 */
1813 -1 /* %l0 */
1814 };
1815 \f
1816
1817 /* Provide a prototype to silence -Wmissing-prototypes. */
1818 void _initialize_sparc_tdep (void);
1819
1820 void
1821 _initialize_sparc_tdep (void)
1822 {
1823 register_gdbarch_init (bfd_arch_sparc, sparc32_gdbarch_init);
1824
1825 /* Initialize the SPARC-specific register types. */
1826 sparc_init_types();
1827 }
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